CSM 16B Quest

Review Session
Presenters: Naomi Sagan, Dexter Lee, Jay Monga, Gavin Liu
Topics
Part 1: 16A Review
● Equivalent resistance
● KCL/KVL
● Nodal analysis
● Equivalent circuits, superposition
● Capacitor voltage current relation

Part 2: 16B Material

● MOSFETS: define NMOS/PMOS, switch model, RC model
● Analyzing transistor logic gates (pull-up, pull-down networks)
● Transistor energy consumption
Equivalent Resistance
- Series: Add up the resistors together

- Parallel: Add up the reciprocal values of the resistors together

Tip: Redraw the circuit into something you are familiar with
-- Really important in 16B
KCL
- KCL: Sum of current going into a node = Sum of current going out of a node
- Does not matter how you label a current as long as you are consistent with the passive sign
convention -- it will work out in the end
KVL
- KVL: Sum of voltages in the loop = 0
- Does not matter whether you go clockwise or counter-clockwise, either equation should be
equivalent to each other
- Personally, I prefer KCL over KVL when analyzing a circuit since KVL is more prone to error in
choosing which way to loop and memorizing whether its adding or subtracting
- Another way to view KVL:
- Going from lower to higher voltage ( - → +), add the voltages
- Going from higher to lower voltage ( + → - ), subtract the voltages
Putting it together: Nodal Analysis
- Not exactly the same as how 16A I find this way less tedious and a lot faster:
- Step 1: Pick a node to perform KCL on. Usually pick the node where it connects the most
elements
- Step 2: Label current going through the elements in the node you choose and use KCL to
equate the currents in Step 1
- Step 3: Convert the KCL equation into V-R relationships or other variables present in the
circuit
- Step 4: Solve for the Vout or other desired variables
- Example after this slide
Example Question
Solution
Solution
Past Exam Question
Solution
Equivalent Circuits and Superposition
Thevenin and Norton Equivalence
Thevenin and Norton Equivalence
Break
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Transistors
Building blocks of Digital Logic
Transistors
Building blocks of Digital Logic
Transistors
Building blocks of Digital Logic
Transistor Models

Voltage-controlled switch: Simplest way to model ideal transistors, which

doesn’t factor in internal resistance or capacitance

PMOS NMOS
Transistor Models
Resistor-switch model: Same as switch model, except there is some
internal resistance Ron when the switch is closed. Accounts for some
power consumption.

PMOS NMOS
Transistor Models
RC-model: Same as the resistor-switch model, and you add a
capacitor between the gate and the source. Accounts for some
power consumption and switching delay.

PMOS NMOS
Transistor Configurations

CMOS Inverter: Consists of one PMOS and one NMOS in series;

think about how Vout changes with Vin!

Vin Vout

0 1
1 0

We can use transistors to model various logic functions!

NOT Gate
Transistor Configurations

CMOS Inverter: Consists of one PMOS and one NMOS in series;

think about how Vout changes with Vin!

- +
Vin Vout

0 1 -
1 0

-
We can use transistors to model various logic functions! -
NOT Gate
Transistor Configurations

CMOS Inverter: Consists of one PMOS and one NMOS in series;

think about how Vout changes with Vin!

+ +
Vin Vout

0 1 +
1 0

+ -
We can use transistors to model various logic functions!

NOT Gate
Transistor Configurations
Logic Gates: Specific configurations of pull-down and pull-up networks let us implement
digital logic!

Under what conditions is Vout

high? Low?
Transistor Configurations
Logic Gates: Specific configurations of pull-down and pull-up networks let us implement
digital logic!

Under what conditions is Vout

high? Low?
Vout will only be low if PA
and PB are both open.
This happens when VA
and VB are both high.
Transistor Configurations
Logic Gates: Specific configurations of pull-down and pull-up networks let us implement
digital logic!

Under what conditions is Vout

high? Low?
Vout will only be low if PA
and PB are both open.
This happens when VA
and VB are both high.

A B Out
0 0 VDD
0 1 VDD
1 0 VDD
1 1 GND NAND Gate
Transistor Configurations
Logic Gates: Specific configurations of pull-down and pull-up networks let us implement
digital logic!

Under what conditions is Vout

high? Low?
Vout will only be high if PA
and PB are both closed.
This happens when VA
and VB are both low.

NAND Gate
Transistor Configurations
Logic Gates: Specific configurations of pull-down and pull-up networks let us implement
digital logic!

Under what conditions is Vout

high? Low?
Vout will only be high if PA
and PB are both closed.
This happens when VA
and VB are both low.

A B Out
0 0 VDD
0 1 GND
1 0 GND
1 1 GND NAND Gate NOR Gate
Transistor Configurations
Logic Gates: Chaining together basic NOT, NAND, NOR lets us create more complicated
logic!
Transistor Configurations
Logic Gates: Chaining together basic NOT, NAND, NOR lets us create more complicated
logic!

NAND -> NOT = AND

Transistor Configurations
Logic Gates: Chaining together basic NOT, NAND, NOR lets us create more complicated
logic!

NAND -> NOT = AND NOR -> NOT = OR

Transistor Configurations
Logic Gates: Chaining together basic NOT, NAND, NOR lets us create more complicated
logic!

When in doubt,
truth tables
will be your
friend :)

NAND -> NOT = AND NOR -> NOT = OR

Spring 2017 - Midterm 1
Hint: Think about what
needs to happen for my
output to be high? low?
A B C Out
A B C Out

1 0 0 V_DD
A B C Out

1 0 0 V_DD
0 1 0 V_DD
A B C Out

1 0 0 V_DD
0 1 0 V_DD
0 0 1 V_DD
 Notice that if any one or two of A, B, C have voltage,
A B C Out the output will be V_DD. At least one of the PMOS’s
will be closed, and there will be no direct connection to
1 0 0 V_DD ground. However, this changes if they ALL have voltage.
0 1 0 V_DD
0 0 1 V_DD
 Notice that if any one or two of A, B, C have voltage,
A B C Out the output will be V_DD. At least one of the PMOS’s
will be closed, and there will be no direct connection to
1 0 0 V_DD ground. However, this changes if they ALL have voltage.
0 1 0 V_DD
0 0 1 V_DD
1 1 1 0

If A and B
and C have
voltage, then
the PMOS’s
will open
while the
NMOS’s
close.
Therefore,
OUT will be
just ground.
 Notice that if any one or two of A, B, C have voltage,
A B C Out the output will be V_DD. At least one of the PMOS’s
will be closed, and there will be no direct connection to
1 0 0 V_DD ground. However, this changes if they ALL have voltage.
0 1 0 V_DD
0 0 1 V_DD
1 1 1 0

If A and B
and C have
voltage, then
the PMOS’s
will open
OUT = 0 when A ^ B ^ C while the
NMOS’s
close.
Therefore,
OUT will be
just ground.
Spring 2017 - Midterm 1
Power and Energy
Key Points:
● Energy is dissipated when current flows through a resistor.
● Energy is stored when a capacitor charges, and released when it discharges.
● Voltage sources supply energy to a circuit.
● The rate energy is supplied or consumed is power.

● For power across a resistor,

● The energy stored by a capacitor charging up to voltage V is
● A positive power value signifies energy consumed, and a negative value signifies
energy supplied.
Power and Energy
Practice:
Consider this RC circuit. Given that the voltage
across the resistor is and the
capacitor is fully uncharged at time t = 0,
1. What is the power consumption of the
resistor with respect to time?
2. How much energy is dissipated by the
resistor from t = 0 to t = T, where T = RC?
3. What about t = 0 to t = ∞?

** Note: deriving VR(t) is not in scope for this exam.

Power and Energy
Practice:

1. For a resistor, remember that

We know the voltage across the resistor,

so we can say that
Power and Energy
Practice:
2. To find the amount of energy dissipated by
the resistor from time t = 0 to t = T,
integrate the power from 0 to T.
Power and Energy
Practice:
3. For this part, change the upper limit of
integration to infinity:
Power and Energy
Practice:

4. How much charge is pulled from the voltage

source as the capacitor charges?
a. Hint: the amount of charge on a capacitor is Q = CV

5. How much energy does the voltage source

supply to the circuit?
a. Hint: Recall that
Power and Energy
Practice:

4. Charge is conserved, so the amount of

charge pulled from the voltage source is
equal to the amount of charge stored by
the capacitor.

The capacitor charges to a voltage of VS, so

the voltage source supplies CVS Coulombs
of charge.
Power and Energy
Practice:

5. To find the energy supplied by the voltage

source, integrate the power of the voltage
source and apply the hint to get:

Applying the fundamental theorem of

calculus:
Power and Energy
Practice: 5. The amount of charge supplied by the
voltage source is CVS.

The source supplies charge, so charge

leaves the source. So,

Putting everything together:

Power and Transistor Networks
● In transistor networks, power is consumed/dissipated whenever current flows
through a resistor.
● In CMOS networks, this occurs when the output switches from high to low or
from low to high.
● In NMOS or PMOS networks, this can happen even when the output is at steady
state, i.e. not switching.
Power and Transistor Networks
Practice: Let’s consider NMOS, PMOS, and CMOS inverters. First, look at an inverter
made with an NMOS transistor and a resistor:

1. Let’s say Vin is high (Vin = VDD, for instance). What is

the output of the inverter? How much power is
consumed by the inverter in steady state?
2. Repeat part 1, but assume Vin is low (Vin = 0).

Use the resistor-switch model for the transistor, and

assume that it has resistance Ron.
Power and Transistor Networks

1. When Vin is high, VGS of the NMOS transistor is greater than Vtn, so
the switch of the transistor is closed, so we can model it as a
resistor from Vout to ground.

We can use the voltage divider to find Vout:

Note: if Ron << R, then Vout ≅0

Current is flowing from VDD to ground, so power is consumed.

The amount of power is P = VDD2/Rtotal, or
Power and Transistor Networks

2. When Vin is low, VGS of the NMOS transistor is less than Vtn, so the
switch of the transistor is open, so we can model it as an open
circuit.

The circuit is open, so no current flows through R, and Vout = VDD

and no power is consumed in steady state.
Power and Transistor Networks
Now consider a PMOS inverter. When does it consume power -- when the output is high
or low? Is this the same or different as the NMOS inverter?
Power and Transistor Networks

The PMOS inverter consumes power when the input is

low. When the input is low, VGS < |Vtp|, so the switch on the
resistor-switch model is closed.

As a result, there is a path for current to flow from VDD to

ground, and power is dissipated. This is the opposite of
the NMOS inverter.

As before, the power consumed is

Power and Transistor Networks
● A CMOS inverter does not consume power in steady state. However, it typically
consumes power when the output switches from high to low or vice versa.

To see why, consider a CMOS inverter with a capacitor

attached to the output. You can think of this as
representing the gate capacitance of another inverter
that the output is connected to.

Assume that the input to the capacitor is Vin = VDD, and

then it switches to Vin = 0. What does the resulting circuit
look like?
Power and Transistor Networks
● A CMOS inverter does not consume power in steady state. However, it typically
consumes power when the output switches from high to low or vice versa.

The circuit after Vin switches looks like a charging RC

circuit, identical to the one we examined earlier!

Using the results you derived earlier, how much

energy is dissipated by the resistor as the inverter’s
output switches?
Power and Transistor Networks
● A CMOS inverter does not consume power in steady state. However, it typically
consumes power when the output switches from high to low or vice versa.

As we saw earlier, the energy dissipated by the resistor is

Good Luck!!
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