Input/Output Organization

Chapter 19
S. Dandamudi

Outline
• Introduction • External interface
• Accessing I/O devices ∗ Serial transmission
• An example I/O device ∗ Parallel interface
∗ Keyboard • USB
• I/O data transfer ∗ Motivation
∗ Programmed I/O ∗ USB architecture
∗ DMA ∗ USB transactions
• Error detection and • IEEE 1394
correction
∗ Advantages
∗ Parity encoding
∗ Transactions
∗ Error correction
∗ CRC ∗ Bus arbitration
∗ Configuration
2003  S. Dandamudi Chapter 19: Page 2
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

1
 Introduction
• I/O devices serve two main purposes
∗ To communicate with outside world
∗ To store data
• I/O controller acts as an interface between the
systems bus and I/O device
∗ Relieves the processor of low-level details
∗ Takes care of electrical interface
• I/O controllers have three types of registers
∗ Data
∗ Command
∗ Status
2003  S. Dandamudi Chapter 19: Page 3
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

Introduction (cont’d)

2003  S. Dandamudi Chapter 19: Page 4

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

2
 Introduction (cont’d)
• To communicate with an I/O device, we need
∗ Access to various registers (data, status,…)
» This access depends on I/O mapping
– Two basic ways
4Memory-mapped I/O
4Isolated I/O
∗ A protocol to communicate (to send data, …)
» Three types
– Programmed I/O
– Direct memory access (DMA)
– Interrupt-driven I/O

2003  S. Dandamudi Chapter 19: Page 5

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

Accessing I/O Devices

• I/O address mapping
∗ Memory-mapped I/O
» Reading and writing are similar to memory read/write
» Uses same memory read and write signals
» Most processors use this I/O mapping
∗ Isolated I/O
» Separate I/O address space
» Separate I/O read and write signals are needed
» Pentium supports isolated I/O
– 64 KB address space
4Can be any combination of 8-, 16- and 32-bit I/O
ports
– Also supports memory-mapped I/O

2003  S. Dandamudi Chapter 19: Page 6

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

3
 Accessing I/O Devices (cont’d)
• Accessing I/O ports in Pentium
∗ Register I/O instructions
in accumulator, port8 ; direct format
– Useful to access first 256 ports
in accumulator,DX ; indirect format
– DX gives the port address
∗ Block I/O instructions
» ins and outs
– Both take no operands---as in string instructions
» ins: port address in DX, memory address in ES:(E)DI
» outs: port address in DX, memory address in ES:(E)SI
» We can use rep prefix for block transfer of data

2003  S. Dandamudi Chapter 19: Page 7

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

An Example I/O Device

• Keyboard
∗ Keyboard controller scans and reports
– Key depressions and releases
» Supplies key identity as a scan code
– Scan code is like a sequence number of the key
4Key’s scan code depends on its position on the
keyboard
4No relation to the ASCII value of the key
∗ Interfaced through an 8-bit parallel I/O port
» Originally supported by 8255 programmable peripheral
interface chip (PPI)

2003  S. Dandamudi Chapter 19: Page 8

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

4
 An Example I/O Device (cont’d)
• 8255 PPI has three 8-bit registers
» Port A (PA)
» Port B (PB)
» Port C (PC)
∗ These ports are mapped as follows
8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H

2003  S. Dandamudi Chapter 19: Page 9

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

An Example I/O Device (cont’d)

Mapping of 8255 I/O ports

2003  S. Dandamudi Chapter 19: Page 10

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

5
 An Example I/O Device (cont’d)
• Mapping I/O ports is similar to mapping memory
∗ Partial mapping
∗ Full mapping
» See our discussion in Chapter 16
• Keyboard scan code and status can be read from
port 60H
∗ 7-bit scan code is available from
» PA0 – PA6
∗ Key status is available from PA7
» PA7 = 0 – key depressed
» PA0 = 1 – key released

2003  S. Dandamudi Chapter 19: Page 11

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

I/O Data Transfer

• Data transfer involves two phases
∗ A data transfer phase
» It can be done either by
– Programmed I/O
– DMA
∗ An end-notification phase
» Programmed I/O
» Interrupt
• Three basic techniques
∗ Programmed I/O
∗ DMA
∗ Interrupt-driven I/O (discussed in Chapter 20)
2003  S. Dandamudi Chapter 19: Page 12
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

6
 I/O Data Transfer (cont’d)
• Programmed I/O
∗ Done by busy-waiting
» This process is called polling
• Example
∗ Reading a key from the keyboard involves
» Waiting for PA7 bit to go low
– Indicates that a key is pressed
» Reading the key scan code
» Translating it to the ASCII value
» Waiting until the key is released
∗ Program 19.1 uses this process to read input from the
keyboard

2003  S. Dandamudi Chapter 19: Page 13

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

I/O Data Transfer (cont’d)

• Direct memory access (DMA)
∗ Problems with programmed I/O
» Processor wastes time polling
– In our example
4Waiting for a key to be pressed,
4Waiting for it to be released
» May not satisfy timing constraints associated with some
devices
– Disk read or write
∗ DMA
» Frees the processor of the data transfer responsibility

2003  S. Dandamudi Chapter 19: Page 14

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

7
 I/O Data Transfer (cont’d)

2003  S. Dandamudi Chapter 19: Page 15

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

I/O Data Transfer (cont’d)

• DMA is implemented using a DMA controller
∗ DMA controller
» Acts as slave to processor
» Receives instructions from processor
» Example: Reading from an I/O device
– Processor gives details to the DMA controller
4I/O device number
4Main memory buffer address
4Number of bytes to transfer
4Direction of transfer (memory → I/O device, or vice
versa)

2003  S. Dandamudi Chapter 19: Page 16

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

8
 I/O Data Transfer (cont’d)
• Steps in a DMA operation
∗ Processor initiates the DMA controller
» Gives device number, memory buffer pointer, …
– Called channel initialization
» Once initialized, it is ready for data transfer
∗ When ready, I/O device informs the DMA controller
» DMA controller starts the data transfer process
– Obtains bus by going through bus arbitration
– Places memory address and appropriate control signals
– Completes transfer and releases the bus
– Updates memory address and count value
– If more to read, loops back to repeat the process
∗ Notify the processor when done
» Typically uses an interrupt

2003  S. Dandamudi Chapter 19: Page 17

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

I/O Data Transfer (cont’d)

DMA controller details

2003  S. Dandamudi Chapter 19: Page 18

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

9
 I/O Data Transfer (cont’d)
DMA transfer timing

2003  S. Dandamudi Chapter 19: Page 19

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

I/O Data Transfer (cont’d)

8237 DMA controller

2003  S. Dandamudi Chapter 19: Page 20

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

10
 I/O Data Transfer (cont’d)
• 8237 supports four DMA channels
• It has the following internal registers
∗ Current address register
» One 16-bit register for each channel
» Holds address for the current DMA transfer
∗ Current word register
» Keeps the byte count
» Generates terminal count (TC) signal when the count goes
from zero to FFFFH
∗ Command register
» Used to program 8257 (type of priority, …)

2003  S. Dandamudi Chapter 19: Page 21

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

I/O Data Transfer (cont’d)

∗ Mode register
» Each channel can be programmed to
– Read or write
– Autoincrement or autodecrement the address
– Autoinitialize the channel
∗ Request register
» For software-initiated DMA
∗ Mask register
» Used to disable a specific channel
∗ Status register
∗ Temporary register
» Used for memory-to-memory transfers

2003  S. Dandamudi Chapter 19: Page 22

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

11
 I/O Data Transfer (cont’d)
• 8237 supports four types of data transfer
∗ Single cycle transfer
» Only single transfer takes place
» Useful for slow devices
∗ Block transfer mode
» Transfers data until TC is generated or external EOP signal is
received
∗ Demand transfer mode
» Similar to the block transfer mode
» In addition to TC and EOP, transfer can be terminated by
deactivating DREQ signal
∗ Cascade mode
» Useful to expand the number channels beyond four
2003  S. Dandamudi Chapter 19: Page 23
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

Error Detection and Correction

• Parity encoding
» Simplest mechanism
» Adds rudimentary error detection capability
∗ Add a parity bit such that the total number of 1s is
» odd (odd-parity)
» even (even-parity)
∗ Advantage:
» Simple to implement
∗ Disadvantage
» Can be used to detect single-bit errors
– Cannot detect even number of bit errors

2003  S. Dandamudi Chapter 19: Page 24

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

12
 Error Detection and Correction (cont’d)
• Error correction
∗ Need to know the error bit position
» To correct, simply flip the bit
∗ To correct single-bit errors in d data bits
» Add p parity bits
» Codeword C = d + p bits
∗ How many parity bits do we need?
» Depends on d
» Hamming distance between codewords
– Number of bit positions in which the two codewords differ
» Hamming distance of code
– Smallest Hamming distance between any pair of
codewords in the code
2003  S. Dandamudi Chapter 19: Page 25
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

Error Detection and Correction (cont’d)

• Constructing codewords to correct single bit errors
∗ Count bit positions from left to right starting from 1
∗ Parity bits are in positions that are a power of 2
» Parity bits are called check bits
» Example for 8-bit data (d = 8)
– We need 4 check bits
– Codeword is 12 bits long

2003  S. Dandamudi Chapter 19: Page 26

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

13
 Error Detection and Correction (cont’d)
• Check bits are derived as in the parity scheme
» Uses even parity
∗ Each check bit is responsible for checking certain bits
» P1: checks bits 1, 3, 5, 7, 9, and 11
» P2: checks bits 2, 3, 6,7, 10, and 11
» P4: checks bits 4,5,6,7, and 12
» P8: checks bits 8,9,10,11, and 12
∗ Example

2003  S. Dandamudi Chapter 19: Page 27

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

Error Detection and Correction (cont’d)

• How is error bit position computed?
Error bit position = sum of weights of check bits in error
∗ Suppose P1, P2, and P8 are in error but not P4
» Error bit position = 1 + 2 + 8 = 11th bit
• What is the logic? 0: 0000
1: 0001
∗ Write the numbers 1,2, 3,4,… in binary 2: 0010
» P1 checks those bit positions for which the 3: 0011
rightmost column has 1 (i.e., with weight 2 = 1)
0 4: 0100
5: 0101
» P2 check those bits positions for which the second
6: 0110
rightmost column has 1 (i.e., with weight 21 = 2) 7: 0111
» ... 8: 1000

2003  S. Dandamudi Chapter 19: Page 28

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

14
 Error Detection and Correction (cont’d)

Circuit to identify
error bit position

2003  S. Dandamudi Chapter 19: Page 29

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

Error Detection and Correction (cont’d)

• SECDED
∗ Single-error correction and double error detection
» Often used in high-performance systems
∗ Previous scheme gives single-error detection and
correction capability
∗ To incorporate double error detection
» Add an additional parity bit
– This bit is added as the leftmost bit P0 that is not used by
the error correction scheme
» Example
– Previous example would have 8 data bits and 5 check bits
for SECDED capability
2003  S. Dandamudi Chapter 19: Page 30
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

15
 Error Detection and Correction (cont’d)
• CRC
∗ Cyclic redundancy check
» Computed for a block of data
» Widely used to detect burst errors
» Uses fixed number of bits
– Mostly 16 or 32 bits depending on the block size
∗ Basic idea: If
D =Q+R
G
D−R = Q
G
» Based on integer division

2003  S. Dandamudi Chapter 19: Page 31

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

Error Detection and Correction (cont’d)

• CRC uses a polynomial of degree n
∗ Example:
» USB polynomial for data packets

x16 + x15 + x2 + 1
» USB polynomial for token packets

x5 + x2 + 1
» Polynomial identifies the 1 bit positions
– USB data polynomial: 11000000000000101
– USB token polynomial: 100101
» Such polynomials are called polynomial generators

2003  S. Dandamudi Chapter 19: Page 32

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

16
 Error Detection and Correction (cont’d)
• A bit of theory behind CRC
C = (d + n)-bit codeword
D = d-bit data
R = n-bit remainder (i.e., CRC code)
G = degree n polynomial generator
∗ Goal: To generate C such that
» Remainder of (C/G) = 0
∗ Since we append n bits to the right
C = D × 2n ⊕ R
⊕ = XOR operation

2003  S. Dandamudi Chapter 19: Page 33

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

Error Detection and Correction (cont’d)

∗ We generate R as
D × 2n R
=Q⊕
G G
∗ Add the remainder R to generate the codeword
∗ When this codeword is divided by G, we get
remainder as zero
C D × 2n ⊕ R
=
G G
zero Error-free
» From above, we get
condition
C R R R⊕R
=Q⊕ ⊕ =Q⊕ =Q
G G G G

2003  S. Dandamudi Chapter 19: Page 34

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

17
 Error Detection and Correction (cont’d)

CRC calculation
for 10100101

Codeword is
1010010101110

2003  S. Dandamudi Chapter 19: Page 35

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

Error Detection and Correction (cont’d)

Error free message

results in a zero
remainder

2003  S. Dandamudi Chapter 19: Page 36

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

18
 Error Detection and Correction (cont’d)
• A serial CRC generator circuit
∗ Uses polynomial generator
x16 + x15 + x2 + 1

2003  S. Dandamudi Chapter 19: Page 37

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

Error Detection and Correction (cont’d)

CRC generator/checker chip

2003  S. Dandamudi Chapter 19: Page 38

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

19
 Error Detection and Correction (cont’d)

Using 74F401 to generate

CRC for the generator
x16 + x15 + x2 + 1

2003  S. Dandamudi Chapter 19: Page 39

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

External Interface
• Two ways of interfacing I/O devices
∗ Serial
» Cheaper
» Slower
∗ Parallel
» Faster
» Data skew
» Limited to small distances

2003  S. Dandamudi Chapter 19: Page 40

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

20
 External Interface (cont’d)
Two basic modes of data transmission

2003  S. Dandamudi Chapter 19: Page 41

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

External Interface (cont’d)

• Serial transmission
∗ Asynchronous
» Each byte is encoded for transmission
– Start and stop bits
» No need for sender and receiver synchronization
∗ Synchronous
» Sender and receiver must synchronize
– Done in hardware using phase locked loops (PLLs)
» Block of data can be sent
» More efficient
– Less overhead than asynchronous transmission
» Expensive

2003  S. Dandamudi Chapter 19: Page 42

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

21
 External Interface (cont’d)

2003  S. Dandamudi Chapter 19: Page 43

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

External Interface (cont’d)

Asynchronous transmission

2003  S. Dandamudi Chapter 19: Page 44

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

22
 External Interface (cont’d)
• EIA-232 serial interface
∗ Low-speed serial transmission
∗ Adopted by Electronics
Industry Association (EIA)
» Popularly known by its
predecessor RS-232
∗ It uses a 9-pin connector DB-9
» Uses 8 signals
∗ Typically used to connect a
modem to a computer

2003  S. Dandamudi Chapter 19: Page 45

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

External Interface (cont’d)

• Transmission protocol uses three phases
∗ Connection setup
» Computer A asserts DTE Ready
– Transmits phone# via Transmit Data line (pin 2)
» Modem B alerts its computer via Ring Indicator (pin 9)
– Computer B asserts DTE Ready (pin 4)
– Modem B generates carrier and turns its DCE Ready
» Modem A detects the carrier signal from modem B
– Modem A alters its computer via Carrier Detect (pin 1)
– Turns its DCE Ready
∗ Data transmission
» Done by handshaking using
– request-to-send (RTS) and clear-to-send (CTS) signals
∗ Connection termination
» Done by deactivating RTS
2003  S. Dandamudi Chapter 19: Page 46
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

23
 External Interface (cont’d)
• Parallel printer interface
∗ A simple parallel interface
∗ Uses 25-pin DB-25
» 8 data signals
– Latched by strobe (pin 1)
» Data transfer uses simple handshaking
– Uses acknowledge (CK) signal
4After each byte, computer waits for ACK
» 5 lines for printer status
– Busy, out-of-paper, online/offline, autofeed, and fault
» Can be initialized with INIT
– Clears the printer buffer and resets the printer
2003  S. Dandamudi Chapter 19: Page 47
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

External Interface (cont’d)

2003  S. Dandamudi Chapter 19: Page 48

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

24
 External Interface (cont’d)
• SCSI
∗ Pronounced “scuzzy”
∗ Small Computer System Interface
» Supports both internal and external connection
∗ Comes in two bus widths
» 8 bits
– Known as narrow SCSI
– Uses a 50-pin connector
– Device id can range from 0 to 7
» 16 bits
– Known as wide SCSI
– Uses a 68-pin connector
– Device id can range from 0 to 15
2003  S. Dandamudi Chapter 19: Page 49
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

External Interface (cont’d)

2003  S. Dandamudi Chapter 19: Page 50

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

25
 External Interface (cont’d)

cont’d
2003  S. Dandamudi Chapter 19: Page 51
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

External Interface (cont’d)

2003  S. Dandamudi Chapter 19: Page 52

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

26
 External Interface (cont’d)
• SCSI uses client-server model
∗ Uses terms initiator and target for client and server
» Initiator issues commands to targets to perform a task
– Initiators are typically SCSI host adaptors
» Targets receive the command and perform the task
– Targets are SCSI devices like disk drives
• SCSI transfer proceeds in phases
∗ Command
∗ Message in IN and OUT from
∗ Message out
the initiator point
∗ Data in
of view
∗ Data out
∗ Status

2003  S. Dandamudi Chapter 19: Page 53

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

External Interface (cont’d)

∗ SCSI uses asynchronous mode for all bus negotiations
» Uses handshaking using REQ and ACK signals for each byte
of data
∗ On a synchronous SCSI
» Data are transferred synchronously
» REQ-ACK signals are not used for each byte
» A number of bytes (e.g., 8) can be sent without waiting for
ACK
– Improves throughput
– Minimizes adverse impact of cable propagation delay

2003  S. Dandamudi Chapter 19: Page 54

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

27
 USB
• Universal Serial Bus
∗ Originally developed in 1995 by a consortium including
» Compaq, HP, Intel, Lucent, Microsoft, and Philips
∗ USB 1.1 supports
» Low-speed devices (1.5 Mbps)
» Full-speed devices (12 Mbps)
∗ USB 2.0 supports
» High-speed devices
– Up to 480 Mbps (a factor of 40 over USB 1.1)
» Uses the same connectors
– Transmission speed is negotiated on device-by-device
basis

2003  S. Dandamudi Chapter 19: Page 55

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

USB (cont’d)
• Motivation for USB
∗ Avoid device-specific interfaces
» Eliminates multitude of interfaces
– PS/2, serial, parallel, monitor, microphone, keyboard,…
∗ Avoid non-shareable interfaces
» Standard interfaces support only one device
∗ Avoid I/O address space and IRQ problems
» USB does not require memory or address space
∗ Avoid installation and configuration problems
» Don’t have to open the box to install and configure jumpers
∗ Allow hot attachment of devices
2003  S. Dandamudi Chapter 19: Page 56
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

28
 USB (cont’d)
• Additional advantages of USB
∗ Power distribution
» Simple devices can be bus-powered
– Examples: mouse, keyboards, floppy disk drives, wireless
LANs, …
∗ Control peripherals
» Possible because USB allows data to flow in both directions
∗ Expandable through hubs
∗ Power conservation
» Enters suspend state if there is no activity for 3 ms
∗ Error detection and recovery
» Uses CRC

2003  S. Dandamudi Chapter 19: Page 57

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

USB (cont’d)

USB cables

2003  S. Dandamudi Chapter 19: Page 58

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

29
 USB (cont’d)
• USB encoding
∗ Uses NRZI encoding
» Non-Return to Zero-Inverted

2003  S. Dandamudi Chapter 19: Page 59

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

USB (cont’d)
• NRZI encoding
∗ A signal transition occurs if the next bit is zero
» It is called differential encoding
∗ Two desirable properties
» Signal transitions, not levels, need to be detected
» Long string of zeros causes signal changes
∗ Still a problem
» Long strings of 1s do not causes signal change
∗ To solve this problem
» Uses bit stuffing
– A zero is inserted after every six consecutive 1s

2003  S. Dandamudi Chapter 19: Page 60

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

30
 USB (cont’d)
Bit stuffing

2003  S. Dandamudi Chapter 19: Page 61

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

USB (cont’d)

• Transfer types
» Four types of transfer
∗ Interrupt transfer
» Uses polling
– Polling interval can range from 1 ms to 255 ms
∗ Isochronous transfer
» Used in real-time applications that require constant data
transfer rate
– Example: Reading audio from CD-ROM
» These transfers are scheduled regularly
» Do not use error detection and recovery

2003  S. Dandamudi Chapter 19: Page 62

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

31
 USB (cont’d)
∗ Control transfer
» Used to configure and set up USB devices
» Three phases
– Setup stage
4Conveys type of request made to target device
– Data stage
4Optional stage
4Control transfers that require data use this stage
– Status stage
4Checks the status of the operation
» Allocates a guaranteed bandwidth of 10%
» Error detection and recovery are used
– Recovery is by means of retries

2003  S. Dandamudi Chapter 19: Page 63

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

USB (cont’d)
∗ Bulk transfer
» For devices with no specific data transfer rate
requirements
– Example: sending data to a printer
» Lowest priority bandwidth allocation
» If the other three types of transfers take 100% of the
bandwidth
– Bulk transfers are deferred until load decreases
» Error detection and recovery are used
– Recovery is by means of retries

2003  S. Dandamudi Chapter 19: Page 64

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

32
 USB (cont’d)
• USB architecture
∗ USB host controller
» Initiates transactions over USB
∗ Root hub
» Provides connection points
∗ Two types of host controllers
» Open host controller (OHC)
– Defined by Intel
» Universal host controller (UHC)
– Specified by National Semiconductor, Microsoft, Compaq
» Difference between the two
– How they schedule the four types of transfers

2003  S. Dandamudi Chapter 19: Page 65

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

USB (cont’d)

• UHC scheduling
∗ Schedules periodic transfers first
» Periodic transfers: isochronous and interrupts
» Can take up to 90% of bandwidth
∗ These transfers are followed by control and bulk
transfers
» Control transfers are guaranteed 10% of bandwidth
∗ Bulk transfers are scheduled only if there is bandwidth
available

2003  S. Dandamudi Chapter 19: Page 66

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

33
 USB (cont’d)

2003  S. Dandamudi Chapter 19: Page 67

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

USB (cont’d)

• OHC scheduling
∗ Different from UHC scheduling
∗ Reserves space for non-periodic transfers first
» Non-periodic transfers: control and bulk
» 10% bandwidth reserved
∗ Next periodic transfers are scheduled
» Guarantees 90% bandwidth
∗ Left over bandwidth is allocated to non-periodic
transfers

2003  S. Dandamudi Chapter 19: Page 68

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

34
 USB (cont’d)
• Bus powered devices
∗ Low-power
» Less than 100 mA
» Can be bus-powered
∗ High-powered
» Between 100 mA and 500 mA
– Full-powered ports can power these devices
» Can be designed to have their own power
» Operate in three modes
– Configured (500 mA)
– Unconfigured (100 mA)
– Suspended ( about 2.5 mA)

2003  S. Dandamudi Chapter 19: Page 69

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

USB (cont’d)
• USB hubs
∗ Bus-powered
» No extra power supply required
» Must be connected to an upstream port that can supply 500 mA
» Downstream ports can only supply 100 mA
– Number of ports is limited to four
– Support only low-powered devices
∗ Self-powered
» Support 4 high-powered devices
» Support 4 bus-powered USB hubs
∗ Most 4-port hubs are dual-powered

2003  S. Dandamudi Chapter 19: Page 70

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

35
 USB (cont’d)

Hubs can be used to expand

Upstream port

Downstream ports

2003  S. Dandamudi Chapter 19: Page 71

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

USB (cont’d)
• USB transactions
∗ Transfers are done in one or more transactions
» Each transaction consists of several packets
∗ Transactions may have between 1 and 3 phases
» Token packet phase
– Specifies transaction type and target device address
» Data packet phase (optional)
– Maximum of 1023 bytes are transferred
» Handshake packet phase
– Except for isochronous transfers, others use error detection
for guaranteed delivery
– Provides feedback on whether data has been received
without error
2003  S. Dandamudi Chapter 19: Page 72
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

36
 USB (cont’d)
USB IRP frame

2003  S. Dandamudi Chapter 19: Page 73

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

USB (cont’d)

Token packets use CRC-5

Hardware encoded
special pattern

Specifies token, data,

or handshake packet Complement of type field
2003  S. Dandamudi Chapter 19: Page 74
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

37
 USB (cont’d)

USB 1.1 transactions

2003  S. Dandamudi Chapter 19: Page 75

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

USB (cont’d)
• USB 2.0
∗ USB 1.1 uses 1 ms frames
∗ USB 2.0 uses 125 µs frames
» 1/8 of USB 1.1
∗ Supports 40X data rates
» Up to 480 Mbps
∗ Competitive with
» SCSI
» IEEE 1394 (FireWire)
∗ Widely available now

2003  S. Dandamudi Chapter 19: Page 76

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

38
 IEEE 1394
• Apple originally developed this standard for high-
speed peripherals
∗ Known by a variety of names
» Apple: FireWire
» Sony: i.ILINK
∗ IEEE standardized it as IEEE 1394
» First released in 1995 as IEEE 1394-1995
» A slightly revised version as 1394a
» Next version 1394b
∗ Shares many of the features of USB

2003  S. Dandamudi Chapter 19: Page 77

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

IEEE 1394 (cont’d)

• Advantages
∗ High speed
» Supports three speeds
– 100, 200, 400 Mbps
4Competes with USB 2.0
– Plans to boost it to 3.2 Gbps
∗ Hot attachment
» Like USB
» No need to shut down power to attach devices
∗ Peer-to-peer support
» USB is processor-centric
» Supports peer-to-peer communication without involving the
processor
2003  S. Dandamudi Chapter 19: Page 78
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

39
 IEEE 1394 (cont’d)
∗ Expandable bus
» Devices can be connected in daisy-chain fashion
» Hubs can used to expand
∗ Power distribution
» Like the USB, cables distribute power
– Much higher power than USB
4Voltage between 8 and 33 V
4Current an be up to 1.5 Amps
∗ Error detection and recovery
» As in USB, uses CRC
» Uses retransmission in case of error
∗ Long cables
» Like the USB
2003  S. Dandamudi Chapter 19: Page 79
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

IEEE 1394 (cont’d)

IEEE 1394 6-pin and 4-pin connectors

4-pin connector does

not distribute power
2003  S. Dandamudi Chapter 19: Page 80
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

40
 IEEE 1394 (cont’d)
• Encoding
∗ Uses a simple NRZ encoding
∗ Strobe signal is encoded
» Changes the signal even if successive bits are the same

2003  S. Dandamudi Chapter 19: Page 81

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

IEEE 1394 (cont’d)

• Transfer types
∗ Asynchronous
» For applications that require correct delivery of data
– Example: writing a file to a disk drive
» Uses an acknowledgement to confirm delivery
» Guaranteed bandwidth of 20%
∗ Isochronous
» For real-time applications
» No acknowledgement
» Up to 80% of bandwidth allocated
∗ Bandwidth allocation on a cycle-by-cycle basis
» Cycle time: 125 µs

2003  S. Dandamudi Chapter 19: Page 82

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

41
 IEEE 1394 (cont’d)

2003  S. Dandamudi Chapter 19: Page 83

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

IEEE 1394 (cont’d)

• Transactions
∗ Follow request and reply format
∗ Each packet is encapsulated between Data_Prefix
and Data_end

2003  S. Dandamudi Chapter 19: Page 84

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

42
 IEEE 1394 (cont’d)
• Isochronous transactions
∗ Similar to asynchronous transactions
∗ Main difference:
» No acknowledgement packets

2003  S. Dandamudi Chapter 19: Page 85

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

IEEE 1394 (cont’d)

• Bus arbitration
∗ Needed because of peer-to-peer communication
∗ Arbitration must respect
» Bandwidth allocation to isochronous channels
» Fairness-based allocation for asynchronous channels
∗ Uses fairness interval
» During each interval
– All nodes with pending asynchronous transaction are
allowed bus ownership once
∗ Nodes with pending isochronous transactions go
through arbitration during each cycle
∗ IRM is used for isochronous bandwidth allocations
2003  S. Dandamudi Chapter 19: Page 86
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

43
 IEEE 1394 (cont’d)
• Configuration
∗ Does not require the host system
∗ Consists of two main phases
» Tree identification
– Used to find the network topology
– Uses two special signals
4Parent_notify and Child_Notify
» Self-identification
– Done after the tree identification
– Assigns unique ids to nodes

2003  S. Dandamudi Chapter 19: Page 87

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

IEEE 1394 (cont’d)

Tree identification

2003  S. Dandamudi Chapter 19: Page 88

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

44
 IEEE 1394 (cont’d)
Tree identification

2003  S. Dandamudi Chapter 19: Page 89

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

IEEE 1394 (cont’d)

Tree identification

All leaf nodes have been identified

2003  S. Dandamudi Chapter 19: Page 90

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

45
 IEEE 1394 (cont’d)
Tree identification

Final topology after tree

identification process
2003  S. Dandamudi Chapter 19: Page 91
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

IEEE 1394 (cont’d)

Self-identification

Initial network with

count values set to 0

2003  S. Dandamudi Chapter 19: Page 92

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

46
 IEEE 1394 (cont’d)
Self-identification

Node A received grant message

Assigns itself ID zero

2003  S. Dandamudi Chapter 19: Page 93

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

IEEE 1394 (cont’d)

Self-identification

2003  S. Dandamudi Chapter 19: Page 94

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

47
 IEEE 1394 (cont’d)
Self-identification

Final assignment of node ids

2003  S. Dandamudi Chapter 19: Page 95

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

Bus Wars
• SCSI is dominant in disk and storage device
interfaces
∗ Parallel interface
∗ Its bandwidth could go up to 640 MB/s
• IEEE 1394
∗ Serial interface
∗ Supports peer-to-peer applications
∗ Dominant in video applications
• USB
∗ Useful in low-cost, host-to-peripheral applications
∗ USB 2.0 provides high-speed support
Last slide

2003  S. Dandamudi Chapter 19: Page 96

To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

48