READ ONLY MEMORY (ROM) CELL DESIGN AND ANALYSIS

PROJECT TERM REPORT

A report submitted in partial of fulfilment of the requirements for the Award of

Degree of

BACHELOR OF TECHNOLOGY

in

ELECTRONICS AND COMMUNICATION ENGINEERING

By

JAISMIN THAKUR (17MI417)

NIVALI YADAV (17MI424)

SONIA THAKUR (17MI428)

Under the Supervision of

Dr. Rajeevan Chandel

Professor, NIT Hamirpur HP, India

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

NATIONAL INSTITUTE OF TECHNOLOGY HAMIRPUR (HP), INDIA

Duration: 25th June 2020 to 10th July 2020

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 NATIONAL INSTITUTE OF TECHNOLOGY HAMIRPUR (HP)

CANDIDATE’S DECLARATION

We hereby certify that the Summer Project Term work being presented in the report entitled
“Read Only Memory (ROM) Cell Design and Analysis ”, in the partial fulfilment of the
requirements for the award of Degree of Bachelor of Technology and submitted in the
Department of Electronics and Communication Engineering of the National Institute of
Technology, Hamirpur (HP), India, is an authentic record of our own work carried out during
the period 25th June 2020 to 10th July 2020 under the supervision of Dr. (Mrs.) Rajeevan
Chandel, Professor, E&CE Department, NIT HAMIRPUR (HP).

The matter presented in the present report has not been submitted by us for the award of any
degree of this or any other institute/University.

JAISMIN THAKUR (17MI417)

NIVALI YADAV (17MI424)

SONIA THAKUR (17MI428)

III YEAR, E&CE, NIT HAMIRPUR

Email: [email protected]

[email protected]

[email protected]

This is to certify that the above statement made by the candidates is correct to the best of my
knowledge.
Date: 10th July 2020
Prof. Rajeevan Chandel

Professor

ECE Department, NIT Hamirpur H.P.

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 ACKNOWLEDGEMENT

We would like to express our sincere gratitude towards our mentor, Dr. Rajeevan Chandel,
Professor, E&CE Department, NIT Hamirpur (HP) for giving us this opportunity and for
her unconditional support and guidance. This project could not have been completed without
your help. Ma’am made it an excellent learning experience for us, despite the difficult Covid
19 period.

We express our special thanks to Dr. Ashok Kumar, Head, E&CE Department, NIT
Hamirpur for giving us this opportunity to work under the supervision of such a great mentor
who constantly guided us to the right path for this project, always motivated us to work harder
and helped a lot on each step of accomplishment of this report.

We worked together and overcome all the difficulties which resulted in successful completion
of the project. We express our immense gratitude to our families for their unending support.

We thank God Almighty for everything and pray to let the Covid-19 phase pass away smoothly.

JAISMIN THAKUR (17MI417)

NIVALI YADAV (17MI424)

SONIA THAKUR (17MI428)

III YEAR, E&CE, NIT HAMIRPUR (HP)

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 ABSTRACT

ROM devices are used for storage of data that does not require modification, hence the name
‘Read Only Memory’. This definition however, has become less clear over the years and now
includes devices whose data are occasionally modified. Most personal computers contain a
small amount of ROM that stores critical programs such as the program that boots the
computer. In addition, ROMs are used extensively in calculators and peripheral devices such
as laser printers, whose fonts are often stored in ROMs. The great advantage of all ROM
devices is that they are non-volatile. This means that when the power is removed the stored
data is not lost.

ROM consists of a decoder and a memory array. When a particular input sequence is applied
to the n decoder inputs, exactly one of the 2n outputs is set to 1. This output line selects one of
the words in the memory array.

The objective of the present report is to design, analyse and implementation of two different
MOS ROM arrays i.e. NOR based ROM array and NAND based ROM array. The
Semiconductor MOS memory ROM (Read only memory) array can be implemented as a
simple combinational Boolean network which produces a specified output value for each input
combination i.e. for each address.

In this report 4 x 4 NOR based ROM array and 4 x 4 NAND based ROM array are designed
by using 180nm technology. The post layout simulation of these designs is performed and
power is also analysed.

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 TABLE OF CONTENTS

CANDIDATE’S DECLARATION………………………………………………………….2

ACKNOWLEDGEMENT…………………………………………………………………...3

ABSTRACT…………………………………………………………………………………..4

TABLE OF CONTENTS…………………………………………………………………….5

1. AN OVERVIEW
1.1. Overview of Memory Types…………………………………………………………7
1.2. The Term Project Undertaken……………………………………………………......7
1.3. Literature Review……………………………………………………………….……8

2. TANNER EDA TOOLS

2.1. Introduction………………………………………………………………………….10
2.2. Schematic Edit Tool (S-Edit) ……………………………………………………….10
2.3. Circuit Simulator (T-Edit) …………………………………………………………..11
2.4. Waveform Edit (W-Edit) ……………………………………………………………12
2.5. Layout (L-Edit) ……………………………………………………………………...13

3. INTRODUCTION
3.1. Semiconductor Read Only Memory (ROM)………………………………….……..14

4. NOR-BASED ROM
4.1. 4 x 4 NOR-based ROM Array………………………………………….…………….15
4.2. Design of Row Decoder for NOR-based ROM Array………………………….……18
4.3. Design of Column Decoder for NOR-based ROM Array………………………........20

5. NAND-BASED ROM
5.1. 4 x 4 NAND-based ROM Array……………………………………….…..................22
5.2. Implementation of Row Decoder for NAND-based ROM………………….……….24

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 5.3. Disadvantages of ROM Array.……………………………………………………....26

6. SIMULATION RESULTS AND DISCUSSION

6.1. General Steps to Simulate Circuit using Tanner EDA Tools ………………………...27
6.2. Technology Used ……………………………………………………………………29
6.3. Simulation of NOR-based ROM …….……………………………………………...29
6.4. Simulation of NAND-based ROM …………………………………………………..35
6.5. Discussion …………………………………………………………………………..41

7. CONCLUSION AND FUTURE SCOPE ………………………………...42

8. BIBLIOGRAPHY…………………………………………………………43

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 CHAPTER 1
AN OVERVIEW

1.1 Overview of Memory Types

Semiconductor Memories

Read Only Memory (ROM)

Read/Write Memory or Random-Access Memory (RAM)

• Mask (Fuse) ROM

Random Access Non-Random Access • Programmable ROM (PROM)
Memory (RAM) Memory (RAM) • Erasable PROM
• Electrically EPROM
• Static RAM • FIFO/LIFO • Flash Memory
• Dynamic RAM • Shift Register • Ferroelectric RAM (FRAM)
• Register File • Content Addressable • Magnetic RAM (MRAM)

1.2 The Term Project Undertaken

In an actual ROM layout, the array can be initially manufactured with NMOS transistors at
every row-column intersection. The “1” bit are then realized by omitting the drain or source
connection, or the gate electrode of the corresponding NMOS transistors in the final
metallization step. To save silicon area, the transistors in every two rows are arranged to share
a common ground line, also routed in n-type diffusion. To store a “0” bit at a particular address
location, the drain diffusion of the corresponding transistor must be connected to the metal bit
line via a metal-to-diffusion contact. Omission of this contact, on the other hand, results in
stored in “1” bit. Figure 1.1 depicts the layout of the ROM array in which unit cell is 12 x 8λ
(about 1/10 size of SRAM).

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Therefore, design, analysis and implementation of ROM array are dealt with in this term project
report.

Figure 1.1 Layout of the ROM array.

1.3 Literature Review

Nobutaro Shibata, et al. [5] have described Gate-array RAM/ROM macros using the new
10T-type base cell from the viewpoint of reducing the design cost and enhancing the
performance. The 10T-type base cell described in this paper has the potential to provide a
higher operating speed and low power consumption if the parasitic bit line capacitance is
reduced to the same level as conventional full-custom SRAM macros. With ROM macros, the
customization time is < 1 h, including the time needed to convert the logical ROM data
provided by customers into physical layout data.

Zhibiao Shao, et al. [6] have discussed Read Only Memory Architecture oriented towards
high speed and low power consumption. These two goals have been achieved using a
precharge-discharge dynamic logic combined with the NOR-type cell array. This architecture
is well suited for memories embedded within ASICs or SOCs due to its excellent speed/power
performance and is very convenient for implementation using typical CMOS ASIC Process.
1K words x 28 bits CMOS mask ROM has been implemented and this CMOS ROM has been
used as micro-code memory in the micro-programmed microprocessor.

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B.D. Yang, et al. [7] have proposed a reduction method of power consumption for reducing
ROM core size. In a memory, most power is dissipated in line of high capacitance such as
decoder lines, word lines and bit lines. So, their proposed method leads to up to 40.6%, 42.12%,
and 32.82%, respectively reduction in area, power consumption and number of transistors
compared with conventional method.

Sadia Nowrin, et al. [8] have presented the design methodologies of a novel reversible ROM.
They proposed the core components with optimum gate count, garbage outputs, quantum cost,
delay and transistor count. In addition, they realized each component and related gate using
MOS transistors. Then proved the efficiency of the proposed circuits by comparative results,
theorems and algorithms. This proposed reversible ROM can be used in Bootstrap memory,
Embedded Microcontroller Program.

Sidhant kukrety, et al. [9] have presented a low power high-speed 32-Bit ROM circuit
implemented on 0.18µm CMOS process. The circuit is build using a parallel ROM core
structure and runs on 1.8V supply voltage. A novel Address Transition Decoder (ATD) circuit
is proposed which energizes the ROM components such as Row decoder, Column Decoder,
ROM core etc, for short time intervals when there is a transition in input address bits. The
power consumed in ROM with proposed ATD circuit is 0.78 mW, which corresponds to
82.27% reduction in power as compared to ROM without ATD circuit (4.46 mW).

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 CHAPTER 2

TANNER EDA TOOLS

2.1 Introduction

Tanner EDA is a suite of tools for the design of integrated circuits. These tools allow you to enter
schematics, perform SPICE simulations, do physical design (i.e., chip layout), waveform probing,
full-custom layout editing, placement and routing and perform design rule checks (DRC) and layout
versus schematic (LVS) checks. Tanner EDA provides software solutions for the design, layout and
verification of analog and mixed-signal integrated circuits (ICs).

Why it is used?

Before going to the time consuming and costly process of chips fabrication, this tool helps to
design and simulate new ideas in Analogue Integrated Circuits.

Tools Used

There are 4 tools that are used for this process:

• S-edit - a schematic capture tool

• T-SPICE - the SPICE simulation engine integrated with S-edit
• L-edit - the physical design tool
• W-edit – a waveform capture tool

2.2 S-EDIT

It is a schematic capture tool that is used to document circuits that can be driven forward into a
layout of an integrated circuit. It also provides the ability to perform SPICE simulations of the
circuits using a simulation engine called T-SPICE. T-SPICE can be setup and invoked from within
S-edit.

It is hierarchy of files, modules and symbols. It introduces symbols and schematic modes. It
provides facility of:

• Beginning a design

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 • Viewing, drawing and editing of objects
• Design connectivity
• Properties, netlist and simulation
• Instance and browse schematic and symbol mode
It requires a sound knowledge of S-Edit design hierarchy of files and modules for an effective
schematic design. Its design files consist of modules.

Modules are nothing but functional units of design such as transistors, amplifiers etc.

Module contains two components:

• Primitives: Geometrical objects created with drawing tools.

• Instances: References to other modules in file and these are the original.
S-Edit has two viewing modes:

• Schematic Mode: To create or view a schematic

• Symbol Mode: To represent symbol of a large functional unit like operational
amplifier
.
2.3 T-EDIT

Input file of a T-Spice is also known as circuit description, the netlist and the input deck. This input
file is called as The Heart of T-Spice. This is a plain text file that contains the device statement
and simulation commands, drawn from the SPICE circuit description language with which T-Spice
constructs a model of the circuit to be simulated. Any text editor can create and modify these input
files.

It is a tool used for simulation of circuit. It provides facilities like

• Design simulation
• Simulation commands
• Device statements
• Noise and small signal models
• User designed external models
T-Spice uses KCL to solve the circuit problems. According to T-spice, a circuit is a set of devices
attached to nodes. Because of its this main feature it is able to do various analysis and measure
various values like

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 • DC operating point analysis
• DC transfer analysis
• AC analysis
• Transient analysis
• Noise analysis
By adding different commands in netlist in input file, we can also calculate different values like
power consumed, time delay, gain, bandwidth etc. This is only possible as its input file can be
edited.

2.4 W-EDIT

It is difficult to visualise the complex numerical data resulting from simulation of circuits to test,
understand and improve these circuits. So, waveform editor provides this ease by doing graphical
data presentation.

Advantages of including W-Edit

• Charts can automatically configure for the type of data we want to present
• Charts views can be panned back and forth, zoomed in and zoomed out, specifying
the exact X-Y coordinate range.
• Properties of axes, charts, colours, traces, texts can be customised.
• It has a tight integration with T-SPICE so it can directly generate the graphical
representation of data produced by T-SPICE.
• Multiple traces from different output files can be viewed simultaneously in one or
several windows.
• Traces can be copied or moved between the charts and windows.
Numerical data is input to W-Edit in form of plane and binary text files. Headers and comments
information is supplied by T-SPICE for automatic graph configuration. It saves data by charts,
traces, axis and other environment settings.

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2.5 L-EDIT

• Layout edit is a tool which is used to represent the masks that are used to fabricate
an integrated circuit. Layout description in this is done by cells, masks primitives
and files.
• We can upload as many files as desired in memory.
• File can be made up of any number of cells.
• These cells are either hierarchically related or are independent. These cells can
contain any number of mask primitives and cell instances
Component parameters are totally different in layout level than schematic level. With the help of
this tool we can analyse the response of a system before passing it forward to time consuming and
costly process of fabrication. Some rules are there to design layout diagram of a schematic circuit
using which user can compare the output response with expected one.

It is a full-featured, high performance, interactive, graphical mask layout editor. It generates layouts
quickly and easily and supports full hierarchical designs. It allows unlimited number of layers, cells
and hierarchical levels. It includes all major drawing primitives and includes 900, 450 and all other
angle drawing modes.

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 CHAPTER 3
INTRODUCTION

3.1 Semiconductor Read Only Memory (ROM)

Memory is like an array of mailboxes (registries of binary data). A stored array of binary data
which can be read only, but not changed. Read only memories are used to store constants,
control information and program instructions in digital systems. They may also be thought of
as components that provide a fixed, specified binary output for every binary input. The read
only memory array can also be seen as a simple combinational Boolean network which
produces a specified output value for each input combination, i.e., for each address. Thus,
storing binary information at a particular address location can be achieved by the presence or
absence of a data path from the selected row (word line) to the selected column (bit line), which
is equivalent to the presence or absence of a device at that particular location. In the following,
we will examine two different implementations for MOS ROM arrays.
The two different types of implementations of ROM array are:
1. NOR-based ROM array
2. NAND-based ROM array

3.2 NOR-based ROM Array

The building block of this ROM Array is a pseudo NMOS gate. Unlike in a standard CMOS
gate, the PMOS pull-up circuitry is replaced by a single PMOS with its gate tied up to GND,
hence being permanently on acting as a load resistor. If none of the NMOS transistors is
activated (all Ri being low) then the output signal C is high. If any of the NMOS transistors is
activated (Ri being low) then the output signal C is high. If any of the NMOS transistors is
activated (Ri being high) then the output signal C is low.

3.3 NAND-based ROM Array

A NAND-based ROM Array consists of m n-input pseudo-NMOS NAND gates, one n-input
NAND per column. In this case, we have up to n serially connected NMOS transistors in each
column. For every row address only one-word line is activated by applying a low signal to the
gates of NMOS transistors in a row. When no word line is activated, all NMOS transistors are
on and the line signals, Ci are all low.
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 CHAPTER 4
NOR-BASED ROM

4.1 4 x 4 NOR-based ROM Array

Consider the first 4 x 4 memory as shown in figure 4.1. Here, each column consists of a pseudo
NMOS NOR gate driven by some of the row signals, i.e. the word line.

Figure 4.1 4 x 4 NOR-based ROM array.

➢ One-word line “Ri” is activated by raising its voltage to VDD .

➢ If an active transistor exists at the cross point of a column and the selected row, the
column voltage is pulled down to the logic low level by that transistor.
➢ If no active transistor exists at the cross point, the column voltage is pulled high by the
PMOS load device.
➢ Logic “1” is stored: Absent transistor
➢ Logic “0” is stored: Present transistor
➢ To reduce static power consumption, the PMOS load transistors in ROM array shown
in figure 4.1 can be driven by a periodic pre-charge signal, resulting in a Dynamic ROM
The truth table for NOR-based ROM is shown in Table 4.1 below.

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 TABLE 4.1 Truth Table for NOR-based ROM Array

INPUTS OUTPUTS

R1 R2 R3 R4 C1 C2 C3 C4

1 0 0 0 0 1 0 1

0 1 0 0 0 0 1 1

0 0 1 0 1 0 0 1

0 0 0 1 0 1 1 0

Layout of Contact-Mask Programmable NOR ROM

➢ “0” bit: drain is connected to metal line via a metal-to-diffusion contact
➢ “1” bit: omission the connect between drain and metal line.
➢ To save silicon area: the transistors on every two adjacent rows share a common ground
line, also are routed in n-type diffusion.
Figure 4.2 shows NMOS transistors in a NOR ROM array, forming the intersection of two
metal lines and two polysilicon word lines.

Figure 4.2 Metal column line to load device.

➢ In reality, the metal lines are laid out directly on top of diffusion columns to reduce the
horizontal dimension.

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 Figure 4.3 Layout of contact Mask Programmable 4-bit x 4-bit NOR ROM

Implant-Mask Programmable NOR ROM Array.

Figure 4.4 Implant-Mask Programmable NOR ROM Array

➢ VT0 is implanted to activate 1 bit:
➢ Let VT0 > VDD  permanently turn off transistor
 disconnect the contact

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Figure 4.3 shows a different type of NOR ROM layout implementation which is based on
deactivation of the NMOS transistor by raising their threshold voltage through channel
implants.

Figure 4.3 Layout of NOR-based ROM Array.

➢ Each diffusion-to-metal contact is shared by two adjacent transistors

 need smaller area than contact-mask ROM layout.

4.2 Design of Row Decoder for NOR-based ROM Array

A row decoder is designed to drive a NOR ROM array that select one of the 2𝑁 word lines by
raising its voltage to VOH . For example, consider the simple row address decoder shown in
figure 4.4, which decodes a two-bit row address and selects one out of four-word lines by
raising its level.

Figure 4.4 Row address decoder for 2-address bits and 4-word lines.

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Another implementation of this decoder is NOR Array consisting of 4 rows (outputs) and 4
columns (two address bits and their complements). NOR based decoder array can be built just
like NOR ROM array using the same selective programming approach as shown in figure 4.5
and its truth table is shown in table 4.2 below.

Figure 4.5 NOR-based row decoder circuit for 2 address bits and 4 address lines.

TABLE 4.2 Truth table for NOR-based row decoder

INPUTS OUTPUTS

A1 A2 R1 R2 R3 R4

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

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The ROM array and its row decoder can thus be fabricated as two adjacent NOR arrays, as
shown in figure 4.6.

Figure 4.6 Implementation of row decoder circuit and the ROM array as two adjacent NOR arrays.

4.3 Design of Column Decoder

To select one out of 2M bits lines of the ROM array, and to route the data of the selected bit
line to the data output.

NOR-based column address decoder and pass transistors

➢ Only one NMOS pass transistor is turned on at a time.
➢ Number of transistors required: 2M (M + 1) (2M pass transistors, M2M decoder).

Figure 4.7 Column decoder using a NOR address decoder and NMOS pass transistors for every bit line.

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Binary Tree Decoder
➢ A binary selection tree with consecutive stages.
➢ The pass transistor network is used to select one out of every two-bit line at each stage.
The NOR address decoder is not needed.
➢ Advantage: Reduce the transistor count 2M+1 − 2 + 2M
➢ Disadvantage: Large number of series connected NMOS pass transistors  long data
access time.
➢ To overcome this constraint, column address decoders can be built as a combination of
the two structures presented here, i.e., consisting of relatively shallow, partial tree
decoders and additional selection circuits similar to that shown in figure 3.8.

Figure 4.8 Column decoder circuit for eight-bit lines, implemented as a binary tree decoder which is driven
directly by the three column address bits.

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 CHAPTER 5

NAND-BASED ROM

5.1 4 x 4 NAND-based ROM Array

In this type of ROM array which is shown in figure 5.1, each bit line consists of a depletion-
load NAND gate, driven by some of the row signals, i.e. the word lines. In normal
operation, all word lines are held at the logic HIGH voltage level except for the selected
line, which is pulled down to logic LOW level. If a transistor exists at the cross point of a
column and the selected row, that transistor is turned off and column voltage is pulled
HIGH by the load device. On the other hand, if no transistor exists (shorted) at that
particular cross point, the column voltage is pulled LOW by the other NMOS transistors in
the multi-input NAND structure. Thus, a logic "1"-bit is stored by the presence of a
transistor that can be deactivated, while a logic "0"-bit is stored by a shorted or normally
ON transistor at the cross point.

Figure 5.1 4 x 4 NAND based ROM Array

➢ The NAND-based ROM array can be fabricated initially with a transistor

connection present at every row-column intersection.

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 ➢ All word lines are kept at logic “1” level, except the selected line pulled down by
“0” level.
➢ Logic “0” is stored: Absent transistor
➢ Logic “1” is stored: Present transistor
➢ A "0"-bit is then stored by lowering the threshold voltage of the corresponding
NMOS transistor at the cross point through a channel implant, so that the transistor
remains ON regardless of the gate voltage.
➢ The availability of this process step is also the reason why depletion-type NMOS
load transistors are used instead of PMOS loads.
The truth table of NAND-based ROM is shown in table 5.1.

TABLE 5.1 Truth Table for NAND-based ROM Array

INPUTS OUTPUTS

R1 R2 R3 R4 C1 C2 C3 C4

0 1 1 1 0 1 0 1

1 0 1 1 0 0 1 1

1 1 0 1 1 0 0 1

1 1 1 0 0 1 1 0

Two different types of layout implementations of NAND ROM array

Figure 5.2 Programming using Implants Only

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 Figure 5.3 Programming using 1-Metal Layer Only

➢ In the implant-mask NAND ROM array, vertical columns of n-type diffusion intersect
at regular intervals with horizontal rows of polysilicon, which results in an NMOS
transistor at each intersection point.
➢ The transistor with threshold voltage implant operates as normally-ON depletion
devices, thereby providing a continuous current path regardless of the gate voltage
level.
➢ No contact in the array  More compact than NOR ROM array
➢ Series-connected NMOS transistors exist in each column
 The access time is slower than NOR ROM

5.2 Implementation of Row Decoder and ROM

➢ A row decoder designed to drive a NAND ROM as shown in fig. 5.4

➢ Lower the voltage level of the selected row to logic "0" while keeping all other rows at
a logic-high level.
➢ This function can be implemented by using an N-input NAND gate for each of the
➢ row outputs.
➢ The truth table of a simple address decoder for four rows and the double NAND-array
implementation of the decoder and the ROM are shown in Table 5.2.

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 ➢ Can also be implemented as two adjacent NAND planes.

Figure 5.4 Implementation of the row decoder circuit and the ROM array as two adjacent NAND planes.

TABLE 5.2 Truth table of NAND-based Row decoder

INPUTS OUTPUTS

A1 A2 R1 R2 R3 R4

0 0 1 1 1 0

0 1 1 1 0 1

1 0 1 0 1 1

1 1 0 1 1 1

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5.3 Disadvantages of ROM Array

➢ The bit cells of the ROM array may be programmed by mask programming. In a
mask programmed ROM array, the data is physically encoded in the circuit and data
is programmed during fabrication only. Thus, it is impossible to change the
respective content of the bit cells after fabrication of the ROM array. This leads to
a number of serious disadvantages.
➢ Apart from the fact that it is only economical to buy a storage device comprising a
mask programmed ROM array in large quantities, one major technical disadvantage
is that the turnaround time between completing the design for a mask programmed
ROM array and receiving the finished product is long.
➢ Furthermore, a storage device comprising a mask programmed ROM array is
usually impractical for research and development work since designers frequently
need to modify the contents of the bit cells of the ROM array as they refine a design.
➢ Another disadvantage is that if a storage device is shipped with a faulty ROM array,
the only way to fix it is to recall the product and physically replace the ROM array
in every unit shipped.

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 CHAPTER 6

SIMULATION RESULTS AND DISCUSSION

The results obtained are presented in this chapter along with their implications. The simulation
work is carried out in Tanner EDA tools [4].

6.1 General Steps to Simulate Circuit Using Tanner EDA Tools

i) Start S-Edit
ii) Start a New Design:
Using the pull-down menus, create a new design:
File – New - New Design
A dialog will appear asking for a design name and location. When we give the name, S-edit
will create a folder of that name in the directory that we provide that will contain all of the
design files.
Enter the name and browse to the directory
Click "OK"
iii) Create a new Cell
Using the pull- down menus, create a new cell view:
Cell – New View:
Enter the cell name and clock "OK"
A blank schematic page will appear.
iv) Enter the symbol libraries, devices and models:
First, we need to include a library which contains the symbols.
On the left side of the S-edit screen we’ll see a Libraries window, click on the “Add” button.
Browse to “Libraries” and click “OK”. Similarly add devices and models.
v) Enter the components to form desired circuit:
On the left, click on “Devices” in the upper window. This will display all of the symbols
available in this group.
Click on the desired component and the symbol of the component will show up in the
symbol viewer window at the bottom.
To place the component, we will click on "Instance" button. A dialog box appears that
allows to set up the component parameters and the symbol attaches to the mouse so that it
can be placed in the schematic.
vi) Apply required voltages to the terminals.
vii) Add ground from the misc.

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viii) Connect components using the "wire" icon.
ix) Setup proper analysis:
Using the pull-down menus:
Setup – SPICE Simulations
On the left, click on the required analysis.
On the right, enter the value of the parameters.
x) Enter the T-Spice tool and write the required netlist.
xi) Simulate the design:
a) First, check you design using the pull- down menus:
Tools – Design Checks (any warnings or errors will be shown at the bottom)
b) Simulate your design:
Click on the Green Arrow to start the simulator:
The T-Spice window will appear. If everything is OK, the waveform viewer will also appear.
If the windows viewer did NOT automatically appear, you can click on the file in the T-Spice
window and select “Show Waveform".

6.2 Technology Used

In VLSI technology means technology mode. The technology node refers to a specific
semiconductor manufacturing process and its design rules. Different nodes often imply
different circuit generations and architectures.

According to Moore’s law, the number of transistors will continue to double in every 1.5 years.
That means the same silicon area would accommodate more and more number of transistors.
To achieve this, transistor size is gradually getting reduced. This we say, transistor size is
shifting from one technology mode to a smaller technology mode by scaling process.

The technology we have used here for simulation purpose is 180nm technology. This
means complementary (NMOS and PMOS) Metal Oxide Semiconductor with small device is
having length of 180nm.

2λ = 180nm => λ = 90nm

Generally, the smaller the technology node means the smaller the feature size, producing
smaller transistors which are both faster and more power-efficient.

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6.3 Simulation of NOR-based ROM

STEPS OF SIMULATION:

1) Open S-Edit and create a new design. Open a new cell window.
2) Include the libraries for devices and components.
3) Place the components according to the circuit diagram and make proper schematic.

Figure 6.1 Schematic of 4 x 4 NOR-based ROM Array

4) Select the NMOS and set L=180nm and W=1080nm.

5) Save the file and open T-Edit.
6) In T-Edit add 180nm technology model files and write netlist.

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 Figure 6.2 SPICE Code for NOR-based ROM Array

7) Save it and run it. Note the value of power.

8) Open the W-Edit and note the output waveform.

Figure 6.3 Output waveform of NOR-based ROM Array

Simulation of NOR-based row decoder

Schematic in S-Edit looks like

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 Figure 6.4 Schematic of NOR-based row decoder

Netlist gets some changes and looks like

Figure 6.5 SPICE Code for simulation of NOR-based Row decoder

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And output waveform appears like

Figure 6.6 Output Waveform of NOR-based Row decoder

Simulation of row decoder circuit and the ROM array as two adjacent NOR
planes

Schematic in S-Edit looks like

Figure 6.7 Schematic of Block diagram of row decoder circuit and the ROM Array as two adjacent NOR planes

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 Figure 6.8 full Schematic of NOR-based ROM Array with NOR-based row decoder

Netlist gets some changes and looks like

Figure 6.9 SPICE Code for simulation of row decoder circuit with ROM Array

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And Output Waveform appears like

Figure 6.10 Output waveform of Row decoder circuit with ROM Array

6.4 Simulation of NAND-based ROM

STEPS FOR SIMULATION:

1) Open S-Edit and create a new design. Open a new cell window.
2) Include the libraries for devices and components.
3) Place the components according to the circuit diagram and make proper schematic.

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 Figure 6.11 Schematic of 4 x 4 NAND-based ROM Array

4) Select NMOS and set the value of L=180nm and W=270nm.

5) Save the file and open T-Edit.

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 Figure 6.12 SPICE Code for Simulation of NAND-based ROM Array

6) Add 180nm model file and write the netlist

7) Save the file and run it. Note the value of power.
8) Open W-Edit and observe the waveform.

Figure 6.13 Output Waveform of NAND-based ROM Array

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Simulation of NAND-based Row Decoder

Schematic in S-Edit looks like

Figure 6.14 Schematic of NAND-based Row decoder

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Netlist gets some changes and looks like

Figure 6.15 SPICE Code for simulation of NAND-based Row decoder

And output waveform appears like

Figure 6.16 Output Waveform of NAND-based Row decoder

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Simulation of row decoder circuit and the ROM Array as two adjacent
NAND planes

Schematic in S-Edit looks like

Figure 6.17 Schematic of block diagram of row decoder circuit and the ROM Array as two adjacent NAND planes

Figure 6.18 Schematic of row decoder circuit and the ROM Array as two adjacent NAND planes

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Netlist gets some changes and looks like

Figure 6.19 SPICE Code for simulation of row decoder circuit with ROM Array

And Output waveform appears like

Figure 6.20 Output Waveform of row decoder circuit with ROM Array

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6.5 Discussion

The design and simulation of two different implementations of ROM Array i.e. NOR-based
ROM Array and NAND-based ROM Array in 180nm CMOS technology is analysed at
transistor level. Transient analysis is carried out in the simulation process and power
consumption is estimated. The power results of NOR-based ROM are given in Table 1 while
power results of NAND-based ROM are given in Table 2.

TABLE 1 Power Dissipation in NOR-based ROM

Power ROM Array Row Decoder Row decoder with ROM Array

Average Power 1.052mW 2.386mW 3.436mW

Consumption

Maximum 1.245mW 2.972mW 4.121mW

Power

Minimum 1.022mW 2.295mW 3.329mW

Power

TABLE 2 Power Dissipation in NAND-based ROM

Power ROM Array Row Decoder Row decoder with ROM Array

Average Power 1.287mW 5.126mW 1.847mW

Consumption

Maximum 1.719mW 0.834mW 2.532mW

Power

Minimum 1.008mW 0.487mW 1.533mW

Power

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 CONCLUSION AND FUTURE SCOPE

Conclusion

We worked on the topic Read Only Memory (ROM) Cell Design and Analysis. It was a
wonderful project and a great learning opportunity. Firstly, we studied the two different
implementation of ROM Array i.e. NOR-based ROM Array and NAND-based ROM Array
and their row decoder. Then we went on to simulate each of these circuits using Tanner EDA
Tool. This tool also helped us a lot to get a clear view about the different implementations of
Semiconductor MOS ROM Array. Analysing each of their waveforms and power values helped
us to understand the topic in a more practical way. Working on this new topic and simulating
it give us confidence and generated a deeper interest in this field.

Future Scope

To address the different limitations, concerns and high density requirement of a mask ROM
array, a layout may be designed using leaf cells / bitcells that have both FEOL (front-end-of-
line) and BEOL (back-end-of-line) layers except for the programming layer, and
programming cells that have only a via layer to connect the source/drain regions of a respective
transistor of the leaf cells / bitcells with respective tracks, for example a bit line track and a
referential track.

In Future, this approach will reduce the turn-around time because only the via layer has to be
changed for different customers depending upon the data to be entered and stored in the
memory array. Also, if there is any faulty ROM array, the costs for rectification are only caused
by the costs for the mask to program the via layer.

In the future the semiconductor memory technology will also change more and more to smaller
structures, for example from 28 nm technology to 16 nm technology.

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 BIBLIOGRAPHY

[1] Sung-Mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuits: Analysis and
Design, ed 3rd, Tata McGraw-Hill; New York, pp. 402-413, 2003.
[2] Jan. M. Rabaey, Digital Integrated Circuits: A Design Perspective, Prentice-Hall
International; pp.560-572,1999.
[3] David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture,
ed 2nd, Morgan Kaufmann; USA, pp. 268-270, 2013.
[4] Mentor Graphics Website: Tanner Tools Guide < www.mentor.com/tannereda/>
[5] Nobutaro Shibata and Yoshinori Gotoh, “High-Density RAM/ROM Macros Using
CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing
Design Cost”, 2015 IEEE Transactions on Very Large-Scale Integration (VLSI)
Systems, vol.23, no.8, pp.1-7.
[6] Lin Hu & Zhibiao Shao, “High-Performance ROM Design for Embedded
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Only Memory with MOS transistors”, 2015 International Journal of VLSI Design &
Communication Systems (VLSICS), vol.6, no.5, pp.74-77.
[9] Sidhant kukrety, Gurmohan Singh, Vemu Sulochana, “A Low Power 32 Bit CMOS
ROM Using a Novel ATD Circuit”, 2013 International Journal of Electrical and
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