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Universidad Autónoma "Tomás Frías" Facultad de Ingeniería Tecnológica

This document describes a laboratory assignment to design a digital alarm clock in Verilog. The alarm clock allows the user to input the hour and minute from a keyboard and includes an audible alarm. The design is broken down into modules for the clock signal dividers, hour and minute accumulators, comparator, 7-segment display decoder, and top-level module.

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juan jose peñaloza cabello
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41 views8 pages

Universidad Autónoma "Tomás Frías" Facultad de Ingeniería Tecnológica

This document describes a laboratory assignment to design a digital alarm clock in Verilog. The alarm clock allows the user to input the hour and minute from a keyboard and includes an audible alarm. The design is broken down into modules for the clock signal dividers, hour and minute accumulators, comparator, 7-segment display decoder, and top-level module.

Uploaded by

juan jose peñaloza cabello
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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UNIVERSIDAD AUTÓNOMA “TOMÁS FRÍAS”

FACULTAD DE INGENIERÍA TECNOLÓGICA

ELECTRÓNICA DIGITAL II Y LABORATORIO ETN 601

LABORATORIO # 4
PRE INFORME

ESTUDIANTES: Andrea Micaela Quispe Patiño Ingeniería Electrónica

Jhonny W. Peñaloza Cabello Ingeniería Mecatrónica

Moisés Torrez Inclan Ingeniería Electrónica

DOCENTE: M.Sc.Ing. Ramiro Russo Negrón

FECHA DE PRESENTACIÓN: 27 de noviembre de 2018


1. Diseñar en verilog un reloj despertador que se pueda introducir la hora
y minuto de la alarma desde el teclado y con alarma sonora

PROCEDIMIENTO DE DISEÑO.-

ck Ck2 Contador1 [0:1]Z Selector [0:7]sel


DivFrec21

ck ck1
DivFrec1 B
[0:3]m1,m2 [0:3]BCD [0:6]seg
MUX C
RELOJ h1,h2 D

rst [0:3]ho1,ho2

pul2 acumuladorh

rst [0:3]mi2,mi1
Acumulador1
pul1

h2 h1: m2 m1
2 3: 5 9
Pul2 = h++
Pul1= m++
Código en Verilog

module divfrec21(ck, ck1);


input ck;
output ck1;

reg [12:0] x;

assign ck1 = x[12];

initial x = 0;

always @(posedge ck)


begin
x = x + 1;
end
endmodule
module divfrec1(ck, ck1);
input ck;
output ck1;

reg [20:0] x;

assign ck1 = x[20];

initial x = 0;

always @(posedge ck)


begin
x = x + 1;
end
endmodule

module acumulador1h (rst, pul2, ho1, ho2);


input rst, pul2;
output [0:3] ho1, ho2;

reg [0:3] h1, h2;

assign ho2 = h2;


assign ho1 = h1;
//assign mi2 = m2;
//assign mi1 = m1;

initial
begin
h2 = 0;
h1 = 0;
//m2 = 0;
//m1 = 0;
end

always @(negedge rst or posedge pul2)


begin
if(rst == 0)
begin
//m1 = 0;
//m2 = 0;
h1 = 0;
h2 = 0;
end

else
begin
if(pul2 == 1)
begin
if(h1 == 9)
begin
h1 = 0;
h2 = h2 + 1;
end
else
begin
h1 = h1+1;
end

if(h2==2 && h1==4)


begin
h1 = 0;
h2 = 0;
end
end
end
end

endmodule

module acumulador1 (rst, pul1, mi2, mi1);


input rst, pul1;
output [0:3] mi2, mi1;

reg [0:3] m2, m1;

//assign ho2 = h2;


//assign ho1 = h1;
assign mi2 = m2;
assign mi1 = m1;

initial
begin
// h2 = 0;
// h1 = 0;
m2 = 0;
m1 = 0;
end

always @(negedge rst or posedge pul1)


begin
if(rst == 0)
begin
m1 = 0;
m2 = 0;
// h1 = 0;
// h2 = 0;
end

else
begin
if(pul1 == 1)
begin
m1 = m1 + 1;
if(m1 == 10)
begin
m1 = 0;
m2= m2 + 1;
if(m2==6)
begin
m1 = 0;
m2 = 0;
end
end
end
end
end
endmodule

module contador1(ck, Z);


input ck;
output [0:1] Z;

reg [0:1]S;
assign Z = S;
initial S = 3;

always @(posedge ck)


begin
S=S+1;
end
endmodule

module reloj1(ck, ho2, ho1, mi2, mi1, r, h2, h1, m2, m1, buz);
input ck, r;
input [0:3] ho2, ho1, mi2, mi1;
output buz;
output [0:3] m1, m2, h1, h2;

reg [0:3] m1, m2, h1, h2;


reg buz;

initial
begin
m1 = 0;
m2 = 0;
h1 = 0;
h2 = 0;
buz = 0;
end

always @(posedge ck)


begin
if(r == 1)
begin
m1 = m1 - 1;
if(m1 == 15)
begin
m1 = 9;
m2 = m2 - 1;
if(m2 == 15)
begin
m2 = 5;
h1 = h1 - 1;
if(h1 == 15)
begin
h1 = 9;
h2 = h2 - 1;
if(h2 == 15)
begin
m1 = 0;
m2 = 0;
h1 = 0;
h2 = 0;
buz = 1;
end
end
end
end
end

else
begin
h2 = ho2;
h1 = ho1;
m2 = mi2;
m1 = mi1;
buz = 0;
end
end

endmodule

module multx1(Z, m1, m2, h1, h2, BCD);


input [0:1] Z;
input [0:3] m1, m2, h1, h2;
output [0:3] BCD;

reg [0:3] BCD;

always @(m1 or m2 or h1 or h2)


begin
case(Z)
0: BCD = h2;
1: BCD = h1;
2: BCD = m2;
3: BCD = m1;
endcase
end
endmodule

module selector1(Z, sel);


input [0:1] Z;
output [0:7] sel;

reg [0:7] sel;

always @(Z)
begin
case(Z)
0: sel = 8'b10000000;
1: sel = 8'b01000000;
2: sel = 8'b00100000;
3: sel = 8'b00010000;
endcase
end
endmodule

module convBCD1(BCD, seg);


input [0:3] BCD;
output [0:6] seg;

reg [0:6] X;
assign seg = X;

always @(BCD)
begin
case(BCD)
0: X = 7'b1111110;
1: X = 7'b0110000;
2: X = 7'b1101101;
3: X = 7'b1111001;
4: X = 7'b0110011;
5: X = 7'b1011011;
6: X = 7'b1011111;
7: X = 7'b1110000;
8: X = 7'b1111111;
9: X = 7'b1111011;
default X = 7'b0000000;
endcase
end
endmodule

module alrp1(ck, rst, pul1, pul2, r, seg, sel, buz);


input ck, rst, pul1, pul2, r;
output buz;
output [0:6] seg;
output [0:7] sel;

wire [0:3] h1, h2, m1, m2, BCD, ho2, ho1, mi2, mi1;
wire [0:1] Z;
wire ck1, ck2, x;

acumulador1 ac1(rst, pul1,mi2, mi1);


acumulador1h ac2(rst,pul2,ho1,ho2);
reloj1 rel1(ck1, ho2, ho1, mi2, mi1, r, h2, h1, m2, m1, x);

divfrec1 div1(ck, ck1); //1seg


divfrec21 divi2(ck, ck2); //0.0001seg
assign buz = ck2 & x;
contador1 cont1(ck2, Z);
selector1 sel1(Z, sel);
multx1 mult1(Z, m1, m2, h1, h2, BCD);
convBCD1 conv1(BCD, seg);
endmodule

TABLA DE ASIGNACIÒN DE PINES.-

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