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HWD2108 Audio Power Amplifier

Dual 105 mW Headphone Amplifier

General Description Key Specifications
The HWD2108 is a dual audio power amplifier capable of n THD+N at 1kHz at 105mW continuous average output
delivering 105mW per channel of continuous average power power into 16Ω 0.1% (typ)
into a 16Ω load with 0.1% (THD+N) from a 5V power supply. n THD+N at 1kHz at 70mW continuous average output
audio power amplifiers were designed specifically to power into 32Ω 0.1% (typ)
provide high quality output power with a minimal amount of n Output power at 0.1% THD+N at 1kHz into 32Ω 70mW
external components using surface mount packaging. Since (typ)
the HWD2108 does not require bootstrap capacitors or snub-
ber networks, it is optimally suited for low-power portable Features
systems.
n LLP, MSOP, and SOP surface mount packaging
The unity-gain stable HWD2108 can be configured by external n Switch on/off click suppression
gain-setting resistors.
n Excellent power supply ripple rejection
n Unity-gain stable
n Minimum external components

Applications
n Headphone Amplifier
n Personal Computers
n Portable electronic devices

Typical Application

*Refer to the Application Information Section for information concerning proper selection of the input and output coupling capacitors.

FIGURE 1. Typical Audio Amplifier Application Circuit

1
Connection Diagrams
LLP Package

Top View
Order Number HWD2108LD

SOP & MSOP Package

Top View
Order Number HWD2108M, HWD2108MM
Typical Application

2
 Absolute Maximum Ratings (Note 3) θJC (MSOP) 56˚C/W
If Military/Aerospace specified devices are required, θJA (MSOP) 210˚C/W
please contact the CSMSC Semiconductor Sales Office/ θJC (SOP) 35˚C/W
Distributors for availability and specifications.
θJA (SOP) 170˚C/W
Supply Voltage 6.0V θJC (LLP) 15˚C/W
Storage Temperature −65˚C to +150˚C θJA (LLP) 117˚C/W (Note 9)
Input Voltage −0.3V to VDD + 0.3V θJA (LLP) 150˚C/W (Note 10)
Power Dissipation (Note 4) Internally limited
ESD Susceptibility (Note 5) 3500V
Operating Ratings
ESD Susceptibility (Note 6) 250V
Junction Temperature 150˚C Temperature Range

Soldering Information (Note 1) TMIN ≤ TA ≤ TMAX −40˚C ≤ T A ≤ 85˚C

Small Outline Package Supply Voltage 2.0V ≤ VDD ≤ 5.5V

Vapor Phase (60 seconds) 215˚C Note 1: See AN-450 “Surface Mounting and their Effects on Product Reli-
ability” for other methods of soldering surface mount devices.
Infrared (15 seconds) 220˚C
Thermal Resistance

Electrical Characteristics (Notes 2, 3)

The following specifications apply for VDD = 5V unless otherwise specified, limits apply to TA = 25˚C.
Symbol Parameter Conditions HWD2108 Units
Typ (Note Limit (Note (Limits)
7) 8)
VDD Supply Voltage 2.0 V (min)
5.5 V (max)
IDD Supply Current VIN = 0V, IO = 0A 1.2 3.0 mA (max)
Ptot Total Power Dissipation VIN = 0V, IO = 0A 6 16.5 mW (max)
VOS Input Offset Voltage VIN = 0V 10 50 mV (max)
Ibias Input Bias Current 10 pA
0 V
VCM Common Mode Voltage
4.3 V
GV Open-Loop Voltage Gain RL = 5kΩ 67 dB
Io Max Output Current THD+N < 0.1 % 70 mA
RO Output Resistance 0.1 Ω
VO Output Swing RL = 32Ω, 0.1% THD+N, Min .3
V
RL = 32Ω, 0.1% THD+N, Max 4.7
PSRR Power Supply Rejection Ratio Cb = 1.0µF, Vripple = 100mVPP, 89 dB
f = 100Hz
Crosstalk Channel Separation RL = 32Ω 75 dB
THD+N Total Harmonic Distortion + Noise f = 1 kHz
RL = 16Ω, 0.05 %
VO =3.5VPP (at 0 dB) 66 dB
RL = 32Ω, 0.05 %
VO =3.5VPP (at 0 dB) 66 dB
SNR Signal-to-Noise Ratio VO = 3.5Vpp (at 0 dB) 105 dB
fG Unity Gain Frequency Open Loop, RL = 5kΩ 5.5 MHz
Po Output Power THD+N = 0.1%, f = 1 kHz
RL = 16Ω 105 mW
RL = 32Ω 70 60 mW
THD+N = 10%, f = 1 kHz
RL = 16Ω 150 mW
RL = 32Ω 90 mW
CI Input Capacitance 3 pF

3
 Electrical Characteristics (Notes 2, 3) (Continued)
The following specifications apply for VDD = 5V unless otherwise specified, limits apply to TA = 25˚C.
Symbol Parameter Conditions HWD2108 Units
Typ (Note Limit (Note (Limits)
7) 8)
CL Load Capacitance 200 pF
SR Slew Rate Unity Gain Inverting 3 V/µs

Electrical Characteristics (Notes 2, 3)

The following specifications apply for VDD = 3.3V unless otherwise specified, limits apply to TA = 25˚C.
Symbol Parameter Conditions Conditions Units
Typ (Note Limit (Note (Limits)
7) 8)
IDD Supply Current VIN = 0V, IO = 0A 1.0 mA (max)
VOS Input Offset Voltage VIN = 0V 7 mV (max)
Po Output Power THD+N = 0.1%, f = 1 kHz
RL = 16Ω 40 mW
RL = 32Ω 28 mW
THD+N = 10%, f = 1 kHz
RL = 16Ω 56 mW
RL = 32Ω 38 mW

Electrical Characteristics (Notes 2, 3)

The following specifications apply for VDD = 2.6V unless otherwise specified, limits apply to TA = 25˚C.
Symbol Parameter Conditions Conditions Units
Typ (Note Limit (Note (Limits)
7) 8)
IDD Supply Current VIN = 0V, IO = 0A 0.9 mA (max)
VOS Input Offset Voltage VIN = 0V 5 mV (max)
Po Output Power THD+N = 0.1%, f = 1 kHz
RL = 16Ω 20 mW
RL = 32Ω 16 mW
THD+N = 10%, f = 1 kHz
RL = 16Ω 31 mW
RL = 32Ω 22 mW

Note 2: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature TA. The maximum
allowable power dissipation is P DMAX = (TJMAX − TA) / θJA. For the HWD2108, TJMAX = 150˚C, and the typical junction-to-ambient thermal resistance, when board
mounted, is 210˚C/W for package MUA08A and 170˚C/W for package M08A.
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: Machine Model, 220 pF–240 pF discharged through all pins.
Note 7: Typicals are measured at 25˚C and represent the parametric norm.
Note 8: Tested limits are guaranteed to CSMSC’s AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are guaranteed by design, test,
or statistical analysis.
Note 9: The given θJA is for an HWD2108 packaged in an LDA08B with the Exposed-DAP soldered to a printed circuit board copper pad with an area equivalent to
that of the Exposed-DAP itself.
Note 10: The given θJA is for an HWD2108 packaged in an LDA08B with the Exposed-DAP not soldered to any printed circuit board copper.

4
External Components Description (Figure 1)

Components Functional Description

The inverting input resistance, along with Rf, set the closed-loop gain. Ri, along with Ci, form a high
1. Ri
pass filter with fc = 1/(2πRiCi).
The input coupling capacitor blocks DC voltage at the amplifier’s input terminals. Ci, along with Ri,
2. Ci create a highpass filter with fC = 1/(2πRiCi). Refer to the section, Selecting Proper External
Components, for an explanation of determining the value of Ci.
3. Rf The feedback resistance, along with Ri, set closed-loop gain.
This is the supply bypass capacitor. It provides power supply filtering. Refer to the Application
4. CS
Information section for proper placement and selection of the supply bypass capacitor.
This is the half-supply bypass pin capacitor. It provides half-supply filtering. Refer to the section,
5. CB Selecting Proper External Components, for information concerning proper placement and selection
of CB.
This is the output coupling capacitor. It blocks the DC voltage at the amplifier’s output and forms a high
6. CO
pass filter with RL at fO = 1/(2πRLCO)
7. RB This is the resistor which forms a voltage divider that provides 1/2 VDD to the non-inverting input of the
amplifier.

Typical Performance
Characteristics
THD+N vs Frequency THD+N vs Frequency

THD+N vs Frequency THD+N vs Frequency

5
Typical Performance Characteristics (Continued)

THD+N vs Frequency THD+N vs Frequency

THD+N vs Frequency THD+N vs Frequency

THD+N vs Frequency THD+N vs Frequency

6
Typical Performance Characteristics (Continued)

THD+N vs Output Power THD+N vs Output Power

THD+N vs Output Power THD+N vs Output Power

THD+N vs Output Power THD+N vs Output Power

7
Typical Performance Characteristics (Continued)

THD+N vs Output Power THD+N vs Output Power

Output Power vs
THD+N vs Output Power Load Resistance

Output Power vs Output Power vs

Load Resistance Load Resistance

8
Typical Performance Characteristics (Continued)

Output Power vs Output Power vs

Supply Voltage Power Supply

Output Power vs Clipping Voltage vs

Power Supply Supply Voltage

Power Dissipation vs Power Dissipation vs

Output Power Output Power

9
Typical Performance Characteristics (Continued)

Power Dissipation vs
Output Power Channel Separation

Channel Separation Noise Floor

Open Loop
Power Supply Rejection Ratio Frequency Response

10
Typical Performance Characteristics (Continued)

Open Loop Open Loop

Frequency Response Frequency Response

Supply Current vs Frequency Response vs

Supply Voltage Output Capacitor Size

Frequency Response vs Frequency Response vs

Output Capacitor Size Output Capacitor Size

11
Typical Performance Characteristics (Continued)

Typical Application Typical Application

Frequency Response Frequency Response

12
Application Information POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is
EXPOSED-DAP PACKAGE PCB MOUNTING critical for low noise performance and high power supply
CONSIDERATION rejection. Applications that employ a 5V regulator typically
The HWD2108’s exposed-dap (die attach paddle) package use a 10µF in parallel with a 0.1µF filter capacitors to stabi-
(LD) provides a low thermal resistance between the die and lize the regulator’s output, reduce noise on the supply line,
the PCB to which the part is mounted and soldered. This and improve the supply’s transient response. However, their
allows rapid heat transfer from the die to the surrounding presence does not eliminate the need for a local 0.1µF
PCB copper traces, ground plane, and surrounding air. supply bypass capacitor, CS, connected between the
HWD2108’s supply pins and ground. Keep the length of leads
The LD package should have its DAP soldered to a copper and traces that connect capacitors between the HWD2108’s
pad on the PCB. The DAP’s PCB copper pad may be con- power supply pin and ground as short as possible. Connect-
nected to a large plane of continuous unbroken copper. This ing a 1.0µF capacitor, CB, between the IN A(+) / IN B(+) node
plane forms a thermal mass, heat sink, and radiation area. and ground improves the internal bias voltage’s stability and
However, since the HWD2108 is designed for headphone ap- improves the amplifier’s PSRR. The PSRR improvements
plications, connecting a copper plane to the DAP’s PCB increase as the bypass pin capacitor value increases. Too
copper pad is not required. The HWD2108’s Power Dissipation large, however, increases the amplifier’s turn-on time. The
vs Output Power Curve in the Typical Performance Char- selection of bypass capacitor values, especially CB, depends
acteristics shows that the maximum power dissipated is just on desired PSRR requirements, click and pop performance
45mW per amplifier with a 5V power supply and a 32Ω load. (as explained in the section, Selecting Proper External
Further detailed and specific information concerning PCB Components), system cost, and size constraints.
layout, fabrication, and mounting an LD (LLP) package is
available from CSMSC Semiconductor’s Package Engineer- SELECTING PROPER EXTERNAL COMPONENTS
ing Group under application note AN1187. Optimizing the HWD2108’s performance requires properly se-
lecting external components. Though the HWD2108 operates
POWER DISSIPATION well when using external components with wide tolerances,
Power dissipation is a major concern when using any power best performance is achieved by optimizing component val-
amplifier and must be thoroughly understood to ensure a ues.
successful design. Equation 1 states the maximum power The HWD2108 is unity-gain stable, giving a designer maximum
dissipation point for a single-ended amplifier operating at a design flexibility. The gain should be set to no more than a
given supply voltage and driving a specified output load. given application requires. This allows the amplifier to
achieve minimum THD+N and maximum signal-to-noise ra-
PDMAX = (VDD) 2
/ (2π2RL) (1) tio. These parameters are compromised as the closed-loop
gain increases. However, low gain demands input signals
with greater voltage swings to achieve maximum output
Since the HWD2108 has two operational amplifiers in one power. Fortunately, many signal sources such as audio
package, the maximum internal power dissipation point is CODECs have outputs of 1VRMS (2.83VP-P). Please refer to
twice that of the number which results from Equation 1. Even the Audio Power Amplifier Design section for more infor-
with the large internal power dissipation, the HWD2108 does mation on selecting the proper gain.
not require heat sinking over a large range of ambient tem-
perature. From Equation 1, assuming a 5V power supply and Input and Output Capacitor Value Selection
a 32Ω load, the maximum power dissipation point is 40mW Amplifying the lowest audio frequencies requires high value
per amplifier. Thus the maximum package dissipation point input and output coupling capacitors (CI and CO in Figure 1).
is 80mW. The maximum power dissipation point obtained A high value capacitor can be expensive and may compro-
must not be greater than the power dissipation that results mise space efficiency in portable designs. In many cases,
from Equation 2: however, the speakers used in portable systems, whether
internal or external, have little ability to reproduce signals
PDMAX = (TJMAX − TA) / θJA (2) below 150Hz. Applications using speakers with this limited
frequency response reap little improvement by using high
value input and output capacitors.
For package MUA08A, θJA = 210˚C/W. TJMAX = 150˚C for
the HWD2108. Depending on the ambient temperature,AT, of Besides affecting system cost and size, Ci has an effect on
the system surroundings, Equation 2 can be used to find the the HWD2108’s click and pop performance. The magnitude of
maximum internal power dissipation supported by the IC the pop is directly proportional to the input capacitor’s size.
packaging. If the result of Equation 1 is greater than that of Thus, pops can be minimized by selecting an input capacitor
Equation 2, then either the supply voltage must be de- value that is no higher than necessary to meet the desired
creased, the load impedance increased or TA reduced. For −3dB frequency.
the typical application of a 5V power supply, with a 32Ω load, As shown in Figure 1, the input resistor, RI and the input
the maximum ambient temperature possible without violating capacitor, CI, produce a −3dB high pass filter cutoff fre-
the maximum junction temperature is approximately 133.2˚C quency that is found using Equation (3). In addition, the
provided that device operation is around the maximum output load RL, and the output capacitor CO, produce a -3db
power dissipation point. Power dissipation is a function of high pass filter cutoff frequency defined by Equation (4).
output power and thus, if typical operation is not around the
maximum power dissipation point, the ambient temperature fI-3db =1/2πRICI (3)
may be increased accordingly. Refer to the Typical Perfor-
mance Characteristics curves for power dissipation infor-
mation for lower output powers. fO-3db =1/2πRLCO (4)
Application Information (Continued) package. Once the power dissipation equations have been
addressed, the required gain can be determined from Equa-
tion (7).
Also, careful consideration must be taken in selecting a
certain type of capacitor to be used in the system. Different
types of capacitors (tantalum, electrolytic, ceramic) have
unique performance characteristics and may affect overall (7)
system performance.

Bypass Capacitor Value Thus, a minimum gain of 1.497 allows the HWD2108 to reach
full output swing and maintain low noise and THD+N perfro-
Besides minimizing the input capacitor size, careful consid-
mance. For this example, let AV =1.5.
eration should be paid to the value of the bypass capacitor,
CB. Since CB determines how fast the HWD2108 settles to The amplifiers overall gain is set using the input (Ri ) and
quiescent operation, its value is critical when minimizing feedback (Rf ) resistors. With the desired input impedance
turn-on pops. The slower the HWD2108’s outputs ramp to their set at 20kΩ, the feedback resistor is found using Equation
quiescent DC voltage (nominally 1/2 VDD), the smaller the (8).
turn-on pop. Choosing CB equal to 1.0µF or larger, will
minimize turn-on pops. As discussed above, choosing Ci no AV = Rf/Ri (8)
larger than necessary for the desired bandwith helps mini-
mize clicks and pops.
The value of Rf is 30kΩ.
AUDIO POWER AMPLIFIER DESIGN
The last step in this design is setting the amplifier’s −3db
Design a Dual 70mW/32Ω Audio Amplifier frequency bandwidth. To achieve the desired ± 0.25dB pass
Given: band magnitude variation limit, the low frequency response
must extend to at lease one−fifth the lower bandwidth limit
Power Output 70mW and the high frequency response must extend to at least five
Load Impedance 32Ω times the upper bandwidth limit. The gain variation for both
Input Level 1Vrms (max) response limits is 0.17dB, well within the ± 0.25dB desired
limit. The results are an
Input Impedance 20kΩ
Bandwidth 100Hz–20kHz ± 0.50dB
fL = 100Hz/5 = 20Hz (9)
The design begins by specifying the minimum supply voltage
necessary to obtain the specified output power. One way to
and a
find the minimum supply voltage is to use the Output Power
vs Supply Voltage curve in the Typical Performance Char-
acteristics section. Another way, using Equation (5), is to fH = 20kHz*5 = 100kHz (10)
calculate the peak output voltage necessary to achieve the
desired output power for a given load impedance. To ac-
As stated in the External Components section, both Ri in
count for the amplifier’s dropout voltage, two additional volt-
conjunction with Ci, and Co with RL, create first order high-
ages, based on the Dropout Voltage vs Supply Voltage in the
pass filters. Thus to obtain the desired low frequency re-
Typical Performance Characteristics curves, must be
sponse of 100Hz within ± 0.5dB, both poles must be taken
added to the result obtained by Equation (5). For a
into consideration. The combination of two single order filters
single-ended application, the result is Equation (6).
at the same frequency forms a second order response. This
results in a signal which is down 0.34dB at five times away
from the single order filter −3dB point. Thus, a frequency of
20Hz is used in the following equations to ensure that the
(5) response is better than 0.5dB down at 100Hz.

VDD ≥ (2VOPEAK + (VODTOP + VODBOT)) (6) Ci ≥ 1 / (2π * 20 kΩ * 20 Hz) = 0.397µF; use 0.39µF.

The Output Power vs Supply Voltage graph for a 32Ω load Co ≥ 1 / (2π * 32Ω * 20 Hz) = 249µF; use 330µF.
indicates a minimum supply voltage of 4.8V. This is easily The high frequency pole is determined by the product of the
met by the commonly used 5V supply voltage. The additional desired high frequency pole, fH, and the closed-loop gain,
voltage creates the benefit of headroom, allowing the AV. With a closed-loop gain of 1.5 and fH = 100kHz, the
HWD2108 to produce peak output power in excess of 70mW resulting GBWP = 150kHz which is much smaller than the
without clipping or other audible distortion. The choice of HWD2108’s GBWP of 900kHz. This figure displays that if a
supply voltage must also not create a situation that violates designer has a need to design an amplifier with a higher
maximum power dissipation as explained above in the gain, the HWD2108 can still be used without running into
Power Dissipation section. Remember that the maximum bandwidth limitations.
power dissipation point from Equation (1) must be multiplied
by two since there are two independent amplifiers inside the

14
Demonstration Board Layout

Recommended LD PC Board Layout:

Recommended SO PC Board Layout: Top Silkscreen
Top Silkscreen

Recommended SOP PC Board Layout:

Top Layer Recommended LD PC Board Layout:
Top Layer

Recommended SOP PC Board Layout: Recommended LD PC Board Layout:

Bottom Layer Bottom Layer

15
Physical Dimensions inches (millimeters)
unless otherwise noted

Order Number HWD2108LD

Order Number HWD2108M

16
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Order Number HWD2108MM

17
 Chengdu Sino Microelectronics System Co.,Ltd
(Http://www.csmsc.com)

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