DIGITAL SYSTEM DESIGN LAB 8

DESIGN AND IMPLEMENTATION OF DIGITAL CIRCUITS USING

BEHAVIORAL MODELING.

Objectives:
On successful completion of this lab, students will be able to:
a) Explain the significance of structured procedures always and initial in behavioral
modeling.
b) Use event-based timing control mechanism in behavioral modeling. Regular event
control, named event control, and event OR control.
c) Use conditional statements using if and else. case, casex, and casez statement and
looping statements such as while, for, repeat, and forever.
d) Design and Implement the digital circuits using behavioral modeling.

Structured Procedures:
There are two structured procedure statements in Verilog: always and initial. These
statements are the two most basic statements in behavioral modeling. All other behavioral
statements can appear only inside these structured procedure statements. Verilog run in
parallel rather than in sequence. Each always and initial statement represents a, separate
activity flow in Verilog. Each activity flow starts at simulation time 0. The statements always and
initial cannot be nested.
initial Statement:
All statements inside an initial statement constitute an initial block. An initial block starts at
time 0, executes exactly once during a simulation, and then does not execute again. If there are
multiple initial blocks, each block starts to execute concurrently at time 0. Each block finishes
execution independently of other blocks. Multiple behavioral statements must be grouped,
typically using the keywords begin and end.
always Statement:
All behavioral statements inside an always statement constitute an always block. The
always statement starts at time 0 and executes the statements in the always block continuously
in a looping fashion. This statement is used to model a block of activity that is repeated
continuously in a digital circuit.
DIGITAL SYSTEM DESIGN LAB 8

Procedural Assignments:
Procedural assignments update values of reg, integer, real, or time variables. The value
placed on a variable will remain unchanged until another procedural assignment updates the
variable with a different value. The syntax for the simplest form of procedural assignment is

shown below.

The left-hand side of a procedural assignment <lvalue> can be one of the following:
 A reg, integer, real, or time register variable or a memory element.
 A bit select of these variables.
 A part select of these variables.
 A concatenation of any of the above.

Event-Based Timing Control:

An event is the change in the value on a register or a net. Events can be utilized to
trigger execution of a statement or a block of statements. There are four types of event-based
timing control: regular event control, named event control, event OR control, and level-
sensitive timing control.
Regular event control:
The @ symbol is used to specify an event control. Statements can be executed on
changes in signal value or at a positive or negative transition of the signal value. The keyword
posedge is used for a positive transition.
Named event control:
Verilog provides the capability to declare an event and then trigger and recognize the
occurrence of that event. The event does not hold any data. A named event is declared by the
keyword event. An event is triggered by the symbol ->. The triggering of the event is recognized
by the symbol @.
Event OR control:
Sometimes a transition on any one of multiple signals or events can trigger the execution of a
statement or a block of statements. This is expressed as an OR of events or signals. The list of
events or signals expressed as an OR is also known as a sensitivity list. The keyword or is used to
specify multiple triggers.

Level-Sensitive Timing Control:

Event control discussed earlier waited for the change of a signal value or the triggering
of an event. The symbol @ provided edge-sensitive control. Verilog also allows level-sensitive
DIGITAL SYSTEM DESIGN LAB 8

timing control, that is, the ability to wait for a certain condition to be true before a statement or
a block of statements is executed. The keyword wait is used for level-sensitive constructs.

always
wait (count_enable) #20 count = count + 1;

Conditional Statements:
Conditional statements are used for making decisions based upon certain conditions.
These conditions are used to decide whether or not a statement should be executed. Keywords
if and else are used for conditional statements. There are three types of conditional statements.

//Type 1 conditional statement. No else statement.

//Statement executes or does not execute.
if (<expression>) true-statement ;
//Type 2 conditional statement. One else statement
//Either true-statement or false-statement is evaluated
if (<expression>) true-statement ; else false-statement ;
//Type 3 conditional statement. Nested if-else-if.
//Choice of multiple statements. Only one is executed.
if (<expressionl>) true-statement1 ;
else if (<expression2>) true-statement2 ;
else if (cexpression3>) true-statement3 ;
else defaul t-statement ;

A block must be grouped, typically by using keywords begin and end.

Multiway Branching:
Conditional Statements, there were many alternatives, from which one was chosen. The
nested if-else-if can become unwieldy if there are too many alternatives. A shortcut to achieve
the same result is to use the case statement
DIGITAL SYSTEM DESIGN LAB 8

case Statement:
The keywords case, endcase, and default are used in the case statement. Each of
statement1, statement2 ..., default-statement can be a single statement or a block of multiple
statements. A block of multiple statements must be grouped by keywords begin and end. The
expression is compared to the alternatives in the order they are written. For the first alternative
that matches, the corresponding statement or block is executed. If none of the alternatives
match, the default-statement is executed. The default-statement is optional. Placing of multiple
default statements in one case statement is not allowed. The case statements can be nested.

case ( expression)

alternativel: statementl;

alternative2: statement2;

alternative3: statement3;

...

default: defaul t-statement;

endcase

The case statement compares 0, 1, X, and z values in the expression and the alternative bit for
bit. If the expression and the alternative are of unequal bit width, they are zero filled to match
the bit width of the widest of the expression and the alternative.
casex, casez Keywords:
There are two variations of the case statement. They are denoted by keywords, casex and
casez.
casez treats all z values in the case alternatives or the case expression as don't cares. All bit
positions with z can also represented by ? in that position.
casex treats all X and z values in the case item or the case expression as don't cares.

Loops:
There are four types of looping statements in Verilog: while, for, repeat, and
forever. The syntax of these loops is very similar to the syntax of loops in the C programming
language. All looping statements can appear only inside an initial or always block. Loops may
contain delay expressions.
DIGITAL SYSTEM DESIGN LAB 8

While Loop:
The keyword while is used to specify this loop. The while loop executes until the while-
expression becomes false. If the loop is entered when the while-expression is false, the loop is
not executed at all. If multiple statements are to be executed in the loop, they must be grouped
typically using keywords begin and end.
For Loop:
The keyword for is used to specify this loop. The for loop contains three parts:

 An initial condition
 A check to see if the terminating condition is true
 A procedural assignment to change value of the control variable
Repeat Loop:
The keyword repeat is used for this loop. The repeat construct executes the loop a fixed
number of times. A repeat construct cannot be used to loop on a general logical expression.
A while loop is used for that purpose. A repeat construct must contain a number, which can
be a constant, a variable or a signal value.

Forever loop:

The keyword forever is used to express this loop. The loop does not contain any expression
and executes forever until the $finish task is encountered. The loop is equivalent to a while
loop with an expression that always evaluates to true, e.g., while (1). A forever loop can be
exit by use of the disable statement.

Example1: Half Adder Using Behavioral Modeling

module Half_Adder_Behavioral(S,C,x,y);

output S,C;
input x, y;
reg S,C;

always @ (a or b)
begin
S = a^b;
C = a&b;
end
endmodule
DIGITAL SYSTEM DESIGN LAB 8

Example 2: Use of Conditional Statement:

Design 2x1 Mux using Data flow modeling

module Mux2X1(F,S,I0,I1);
input S,I0,I1;
output F;
reg F;
always @ (S or I0 or I1)
begin
if (S==0)
F = I0;
else
F = I1;
end
endmodule

Example 3 Decoder 2 to 4 line:

module Decoder(E,A,B,D);
input A,B,E;
output [3:0] D;
reg [3:0] D;
always @(E or A or B)
begin
if(E==1)
D = 4'b1111;
else
case ({A,B})
DIGITAL SYSTEM DESIGN LAB 8

Task1: Implement the Design problem of Lab7 using behavioral modeling.

Task2: Design and implement the given truth table for Encoder.

Design Problem: Design a digital circuit of magnitude comparator which takes two 8 bit
numbers from the user and then compare there magnitude. If input A is greater the B turn on
the Green Led, when A is less the B turn on Blue led and when A is not equal to B turn on the
Red led. Red, blue and green leds are present on nexys4 board.