1st Edition

ANALOG
SOLUTIONS
FOR XILINX
FPGAs
Product Guide

www.maximintegrated.com
Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

Table of Contents
3 A message from the Vice President, Portfolio and
Solutions Marketing, Xilinx, Inc.
4 Introduction
6 Powering Xilinx FPGAs and CPLDs
Featured Products
Selector Guide and Tables
19 Signal Conversion Solutions for FPGAs
Featured Products
Selector Guide and Tables
28 Design Protection Solutions for FPGAs
Selector Guide and Tables
32 Interfacing High-Speed DACs and ADCs to FPGAs
Selector Guide and Tables

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www.maximintegrated.com/xilinx Analog Solutions for Xilinx FPGAs Product Guide

Analog Solutions for Xilinx FPGAs

A message from the Vice President,
Portfolio and Solutions Marketing, Xilinx, Inc.
Dear Customers,
From consumer electronics to industrial and telecom infrastructure equipment systems,
sitting alongside the analog and mixed signal ICs that interface with the outside world are field
programmable gate arrays (FPGAs) that deliver significant value through programmable system
integration. If you are designing a system that requires integrating several key components to acquire
and process data, you’re probably weighing your FPGA choices right now. So how do you determine
which parts are not only the best for your design, but also work well together? Xilinx and Maxim are
the winning formula to help you achieve success.
For over a quarter century, both Xilinx and Maxim have specialized in integrated solutions
designed to meet your most demanding system requirements. We have built our reputations as
technology leaders, each with over $2 billion in revenues serving similar markets and common
customers like you.
Xilinx devices integrate memory, clocking, DSP functions, SerDes, and even embedded PowerPC and
ARM processors within a programmable fabric to enable virtually any application. Maxim produces
power management, data converters, sensors, I/O interfaces, RF, and other mixed signal functions to
complete the system.
So what can Xilinx and Maxim do for you? Consider ease of use. Xilinx provides programmable
solutions to solve your toughest design challenges through its Targeted Design Platforms, a
comprehensive and growing portfolio of development kits, complete with boards, tools, IP cores,
reference designs, and FPGA Mezzanine Card (FMC) support, enabling designers to begin
application development immediately. Maxim enables FPGA design with analog and digital power
regulators and modules. Additionally, Maxim’s signal-chain building blocks and IP security parts
perfectly complement Xilinx's FPGAs. Your design also calls for incorporating video, voice, or data.
Xilinx and Maxim have those bases covered, too.
As FPGAs grow in their use, so does the need for flexible and robust interfaces for the analog world
around it. Maxim audio/video amplifiers and codecs, signal conditioning filters, signal integrity and
protection circuits, as well as GHz DACs deliver superior performance.
That's not all. You have worldwide support, which is always available to help you with your design.
Leverage our solid team of field application engineers dedicated to resolving issues and design entire
systems. Xilinx and Maxim also share Avnet as their primary distributor, eliminating the hassle of
navigating multiple sales channels.
And above all, our companies deliver innovative solutions that add value to your products, allowing
you to focus on your project at hand.
Xilinx and Maxim are building a future founded on expertise and innovation. In the following pages,
discover more ways to use Xilinx FPGAs with Maxim ICs to realize your objectives faster.
Sincerely,

Hugh Durdan
VP, Portfolio and Solutions Marketing
Xilinx, Inc.
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Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

Introduction
Designing with (LUTs) called field programmable
gate arrays (FPGAs). In addition to
the real world are analog in nature
(temperature, pressure, sound, vision,
Programmable Logic in implementing Boolean logic and registers voltage, current, frequency, and others).
in the configurable logic array, you Most data travel on wires or wireless
an Analog World can also use built-in features such as media as analog signals that need to
Programmable logic devices (PLDs) memory, clock management, I/O drivers, be converted into 0s and 1s for the
revolutionized digital design over 25 high-speed transceivers, Ethernet MACs, FPGA to process (Figure 1). Making
years ago, promising designers a blank DSP building blocks, and embedded the analog world accessible to the digital
chip to design literally many function processors inside the FPGA. world is where Maxim shines. As one of
and to program it in the field. PLDs can the top 3 players in nearly every analog
be low-logic density devices that use Using programmable logic devices, data function, Maxim has built a reputation for
nonvolatile sea-of-gates cells called is input, processed, and manipulated, innovation and quality. With a focus on
complex programmable logic devices then output. However, this processing ease of use, our products simplify your
(CPLDs) or they can be high-density is generally limited to the digital system design allowing you to focus on
devices based on SRAM look-up tables domain while most of the signals in your unique algorithms.

CONFIGURATION
CLOCKS AND TIMING IP PROTECTION MEMORY

DATA CONVERTERS MULTIMEDIA

ANALOG HUMAN-MACHINE
BUILDING BLOCKS INTERFACE

SYSTEM POWER
I/O INTERFACES
MONITORING MANAGEMENT

Figure 1. A Typical System Application Showing FPGA Working with Analog Functions

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www.maximintegrated.com/xilinx Analog Solutions for Xilinx FPGAs Product Guide

Power Management sequence to differentiate between or current levels required by many

authorized and counterfeit devices, interface standards. RS-232, RS-485,
FPGAs and CPLDs require anywhere thereby protecting the design investment CAN, IO-Link , Ethernet, optical, and
M

from 3 to 15 or more voltage rails. from copying and cloning. Read about IrDA are just a few common examples.
M

The logic fabric is usually at the the benefits of our proprietary approach Maxim’s portfolio provides solutions to
latest process technology node that in the Design Protection Solutions for these interface problems. Many of these
determines the core supply voltage. FPGAs section. Reference designs with solutions include additional features for
Configuration, housekeeping circuitry, FPGA logic are available. ESD and fault protection. In other cases,
various I/Os, SerDes transceivers, clock high-density interface ports like 24+
managers, and other functions have Multimedia port SATA and SAS transceivers can be
differing requirements for voltage rails, offloaded from the FPGA to a companion
sequencing/tracking, and voltage ripple FPGAs are increasingly used to process
audio along with data. In most instances, chip for optimizing costs.
limits. Learn the best ways to manage
this complex challenge starting in the these systems require audio/video data We provide power-over-Ethernet ICs to
Powering Xilinx FPGAs and CPLDs section. converters, amplifiers, filters, equalizers, power devices such as security cameras,
signal conditioners, on-screen display IP phones, WiFi access points, and
Data Converters blocks, video decoders, and audio codecs. others through Ethernet. We can help
Maxim offers multimedia subsystem ICs, you communicate over power lines using
FPGAs in communications applications allowing the FPGA designer to focus on
typically need high-speed data con- our powerline communication (PLC) ICs.
the advanced audio/video processing
verters, while those in industrial and
medical applications frequently require
stages of the design. Building Blocks
high precision and resolution. Maxim’s Human-Machine Interface Maxim provides building blocks such
data converter portfolio includes a as level translators, MEMS-based
wide variety of devices that serve these Most systems interact with their human real-time clocks, oscillators, amplifiers,
applications, including multi-GSPS operators and the real world. Maxim comparators, multiplexers, signal
high-performance and 16-bit to 24-bit provides a wide variety of state-of- conditioners, filters, potentiometers, ESD/
precision ADCs and DACs. Turn to the the art components to detect touch, fault protection, and other ICs to make
Signal Conversion Solutions for FPGAs temperature, proximity, light, and motion your design robust and reliable.
section for information about high-speed and convert those analog signals to the
data converters. digital domain for processing within your System Monitoring
FPGA. This includes devices suitable
FPGAs are used in rack-mounted
IP Protection for high-volume consumer applications
communications/computing
in addition to those built for the rugged
While field programmability offers industrial environments. infrastructure or sensitive industrial/
flexibility during the design process, it medical and defense applications. For
can also expose your underlying IP to I/O Interfaces these applications, Maxim provides a
significant risks of reverse engineering full spectrum of solutions for enclosure
and theft. Maxim provides 1-Wire M While FPGAs include various I/O management, thermal management,
secure EEPROMs that use a single pin on drivers such as LVTTL, LVCMOS, fan control, and hot-swap controllers,
the FPGA or CPLD to secure the design LVDS, HSTL/SSTL, and multigigabit including fault-detection/logging and
implemented. The secure memory uses serial transceivers, process limitations security/authentication.
a challenge-and-response authentication preclude them from driving the voltage

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Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

Powering Xilinx FPGAs and CPLDs

Overview Understanding FPGA Power Rails Figure 2 illustrates a typical Virtex
series FPGA used in a communications
While Xilinx's FPGAs that are based Modern PLDs have a core supply rail
application, a Kintex series FPGA used
on SRAM technology offer higher that powers most of the device and
in an industrial application, and an
logic density and consume higher consumes the highest power. With every
Artix series FPGA used in a consumer
power, Xilinx's CPLDs based on flash new technology node, there is a new
application.
technology offer lower logic density and core supply voltage rail. Auxiliary voltage
consume lower power. PLD vendors use supply rails power supporting circuits Consider the latest FPGAs from Xilinx
the latest process technology node in on a PLD such as configuration logic, as an example to understand the power
every generation of devices to increase clock managers, and other housekeeping needs better. Table 1 provides a summary
the logic density and integrate more circuits. In addition, FPGAs are typically of the key voltage rails in the Xilinx
features. Examples include block RAMs, used to bridge one interface standard 7 series FPGAs inclusive of Virtex-7,
clock managers, DSP functions, system to another, and each I/O driver has its Kintex-7, and Artix-7, as well as Zynq - M

interfaces, and even ARM /PowerPC M M

unique voltage rail ranging from 1.2 to 7000 processing platform devices. While
processors. 3.3V. Examples include LVTTL/LVCMOS, this table shows the latest FPGAs, the
LVDS, bus LVDS, mini LVDS, HSTL, SSTL, power-supply requirements of previous
The integration of disparate functions and TMDS, among others. generation FPGAs are quite similar. Xilinx
and regular technology node migration recommends a typical power-on and
results in several power supply rails for a Special care is needed in powering high-
power-off sequence. The recommended
PLD. The benefits of integration and ease speed SerDes transceivers, each of which
sequence for power-on is VCCINT,
of use are questionable if you cannot can consume 1 to several amperes of
VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO.
power these programmable devices in current and run at speeds of 155Mbps
The recommended power-off sequence is
an easy and cost-effective manner. Most to 28Gbps and beyond. For example, a
the reverse of the power-on sequence.
digital designers either underestimate 100G Ethernet application uses many such
transceivers and consumes 10A or more
the power supply needs of a PLD or are
of current. Because of the high speeds
Power Architectures
overwhelmed by them. Maxim can help
you achieve first-time success with your involved, a noisy power rail is particularly The power architecture that supports a PLD
FPGA power design and meet your time- detrimental to their performance. is influenced by the intended application:
to-market objectives by following simple communications and computing, industrial
guidelines discussed in this chapter.

Power Requirements Table 1. Xilinx 7 Series FPGAs and Zynq-7000 Extensible Processing
of PLDs Platform Power-Supply Requirements
As PLDs assume the role of a System- Power Rail Nominal Voltage (V) Description
on-Chip (SoC) on your board, powering VCCINT 0.9/1.0 Voltage supply for the internal core logic
these devices is comparable to powering VCCAUX 1.8 Voltage supply for auxiliary logic
an entire system. A typical high-end
VCCAUX_IO 1.8/2 Voltage supply for auxiliary logic in I/Os
Virtex series FPGA easily has 10 to 15
M

VCCO 1.2 to 3.3 Voltage supply for output drivers in I/O banks
unique rails. On the other hand, devices
from a lower density Spartan , Kintex™, M VCCBRAM 1 Voltage supply for block RAMs
Artix™ , and CoolRunner series can
M
VCCADC 1.8 A/D converter voltage supply
have 2 to 10 rails depending on your VBATT 1.5 Security key battery backup voltage supply
application. You need to pick the right MGTAVCC 1.0 Voltage supply for GTP/GTX/GTH transceiver
set of power regulators based on the Voltage supply for GTP/GTX/GTH transceiver
overall power level of each of the rails, MGTAVTT 1.2
termination circuits
their sequencing, and their system Analog supply voltage for the resistor calibration
power management needs. As process MGTAVTTRCAL 1.2
circuit GTX/GTH transceivers column
technology nodes become smaller Auxiliary analog quad PLL (QPLL) supply for the
in FPGAs, there is a need for tighter MGTAVCCAUX 1.8 GTX/GTH transceivers
tolerances on the voltage supply rails. Note: The lowest-speed -1L and -2L versions of the devices have a 0.9V core voltage.
Maxim provides 1% regulation accuracy Supply rails for voltage references for I/Os and MGT are not shown.
across line/load and PVT variations.
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www.maximintegrated.com/xilinx Analog Solutions for Xilinx FPGAs Product Guide

or automotive, or handheld consumer.

Most high-performance/high-power
FPGA applications in communications and A) POWERING A VIRTEX SERIES FPGA IN A COMMUNICATIONS APPLICATION
computing infrastructure applications are
built on line cards that are powered by a PLUG-IN CARD 1

48V or 72V backplane in a rack-mounted -48V FIRST STAGE SECOND STAGE

BACKPLANE
system. A two-stage intermediate bus POL1
1.0V, 16A

architecture (IBA) is typically used in

these applications for the individual cards POL2
1.2V, 10A
-48V → 5V
(Figure 2A). The first stage is a step-down ISOLATED
5.0V
FPGA
converter that converts the 48V or 72V REGULATOR
POL3
1.1V, 10A
to an isolated intermediate voltage such
as 12V or 5V. The plug-in cards are often POL4
3.3V, 1A
isolated from each other for safety reasons
and to eliminate the possibility of current
loops and interference between the cards.
The second stage of the IBA is to convert PLUG-IN CARD 10
the intermediate voltage to multiple lower
FIRST STAGE SECOND STAGE
DC voltages, using nonisolated regulators 1.2V, 5A
that are in close proximity to the FPGA and POL1

often called point-of-load (POL) regulators. -48V → 12V

12V 1.1V, 2A
Multiple-output POLs are called PMICs. ISOLATED POL2 FPGA
REGULATOR
FPGAs used in industrial and automotive POL3
3.3V, 0.5A
applications are typically powered by
an isolated AC-DC or DC-DC supply
followed by a 24V supply that is
nonisolated (Figure 2B). POL regulators B) POWERING AN KINTEX SERIES FPGA IN AN INDUSTRIAL APPLICATION
located next to the FPGA generate the
specific voltages required by the FPGA. ISOLATED
24V
BACKPLANE 1V, 3A
Consumer and handheld equipment run
PMIC1 1.2V, 2A
on 3.6V to 12V batteries. The specific
OPTIONAL
voltages required by an FPGA in such STAGE
an application can be generated by AC-DC
5V/ 1V, 6A I/O
POLs directly from the battery voltage OR
DC-DC
24V
12V
POL FPGA

(Figure 2C).
1.8V, 1A
Maxim provides power solutions for PMIC2
3.3V, 0.75A
every stage of these three architectures: 1.5V, 0.5A

• Front-end isolated AC-DC and

DC-DC power regulators from 5W to
hundreds of watts of power with high C) POWERING AN ARTIX/Spartan SERIES FPGA OR CoolRunner-II CPLD IN A CONSUMER APPLICATION
efficiencies
3.3V, 50mA
• 4.5V to 60V (24V nominal)
PMIC 1.5V, 100mA
nonisolated DC-DC buck regulators
often used in industrial and building
automation applications where FPGAs
3.6V/ 1.8V, 50mA I/O
are common 7.2V
POL FPGA/CPLD

• Primary stage controllers supporting

up to 300A
• Secondary stage single- and multirail Figure 2. Typical FPGA Power Architecture Used in Communications, Industrial, and
POL regulators to power FPGAs and Consumer Applications
CPLDs

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Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

System Considerations most cases, this makes LDOs inefficient for your competitiveness. A good example
power levels exceeding 100mW. Yet, LDOs illustrating this concept is a Kintex-7
System-level design considerations are very easy to design and use. development board using over a dozen
influence the choice of power architec- 20A and 10A power modules, resulting in
ture. Simpler power system designs can SMPS regulators use a pulse-width more than 100A of current supplied.
use single- and multirail regulators that modulation (PWM) controller with
take a 5V/12V input and supply power MOSFETs (internal or external) acting Advanced Features
to all FPGA rails with built-in sequencing as switches and an inductor acting as an
and minimal external components. energy storage device. By controlling the Power regulators provide several
Ease of use is paramount in such duty cycle, an SMPS regulator manages advanced features beyond the
applications. Features that simplify the energy in the inductor thereby input/output voltages and currents.
these power designs include internal regulating the output voltage despite line Depending on your application, a
MOSFETs, internal compensation, and load variations. Efficiencies as high feature can be critical for success or
digital programmability, and even as 90% to 95% are realized, unlike with completely unnecessary. It is important
internal inductors. LDO regulators. to understand the types of features
available in today’s regulators.
Infrastructure equipment uses FPGAs, The Four Ps of Power
DSPs, ASICs, and peripherals on the Startup Sequencing/Tracking
board that are powered by numerous The four Ps of power are: products,
Three or more voltage rails are typically
POL regulators controlled by a master process, packaging, and price.
required to power an FPGA and
controller. PMBus™ protocol or I2C/ Process technology is a key part of need sequencing for power-up and
SPI- based control with a microcontroller power-supply choice. The process used power-down. Sequencing limits the
is often used in these applications. It to develop power regulators determines inrush current during power-up. If the
might be necessary to control both the performance of the MOSFETs sequencing is ignored, the devices that
the power of the FPGAs on the board used, and thereby, the efficiency and require sequencing can be damaged or
and also several other devices along die area. A MOSFET with low RDSON can latchup. This can cause your FPGA
with dynamic power management and (drain-source on-resistance) is more device to malfunction. There are three
monitoring. Also, it is suggested to turn efficient dissipating lower power without types of sequencing: coincident tracking,
on/off some ICs based on trigger events. occupying a larger die area. Similarly, sequential tracking, and ratiometric
Maxim provides advanced system power smaller geometries aid in the integration tracking. An example of sequential
management ICs (i.e., the MAX34440 of digital logic, such as sequencing and tracking is shown in Figure 3.
and MAX34441) to control multiple POL PMBus control, with power regulators.
regulators and fans, enabling dynamic Sequencing and tracking capabilities are
A careful balance of process technology
power regulation (hibernate, standby, integrated into many of Maxim’s multi-
and cost is required to meet FPGA power
etc.) and superior monitoring and fault output power regulators. Stand-alone ICs
requirements. Typically, the top three
logging. that perform sequencing and tracking
suppliers have these process capabilities,
are also available.
Applications that run on batteries take unlike vendors who cut corners to sell
advantage of Xilinx's FPGAs’ power cheap regulators. Monotonic Startup Voltage Ramp
saving modes to keep the FPGA circuits Due to the amount of power required Most Xilinx FPGA and CPLD rails have
in hibernate modes most of the time, from the regulators by the FPGAs, the a monotonic voltage ramp requirement,
except when crunching algorithms. The regulators’ ability to manage the heat meaning that the rails should rise
regulators that power the FPGAs can generated is critical. A superior power continuously to their setpoint and not
also save energy and improve efficiency regulator can regulate properly over droop. Drooping could result if the
by employing techniques such as pulse- temperature and uses industry-leading POL does not have enough output
skipping. Many Maxim regulators use packages such as a QFN with an exposed capacitance (Figure 4).
such technologies to provide light-load pad.
operation mode and control. Soft-Start
Price of the regulator is usually a critical
Most Xilinx FPGAs specify minimum and
Power Regulation Primer factor. The number of regulators used on
maximum startup ramp rates. Power-
a board can easily multiply. Therefore,
DC-DC power regulators come in two the cost of additional features must be supply regulators implement soft-start
major categories: low dropout (LDO) carefully weighed against the benefit by gradually increasing the current limit
regulators and switching-mode power provided. Sometimes power regulators at startup. This slows the rate of rise of
supply (SMPS) regulators. LDOs convert loaded with features are selected for Xilinx the voltage rail and reduces the peak
the VIN to VOUT at the required current and development boards, but such products inrush current to the FPGA. POLs allow
dissipate the power difference as heat. In are not cost-effective and can reduce soft-start times to be programmed.

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www.maximintegrated.com/xilinx Analog Solutions for Xilinx FPGAs Product Guide

Power-Supply Transient Response Remote Sensing Estimating Your FPGA’s

FPGAs can implement many functions There can be a significant voltage drop Power Needs
at different frequencies due to their on a PCB between the power-supply First, determine the input voltage. Second,
multiple clock domains. This can output and the FPGA power-supply identify the supply rails and load currents
result in large step changes in current pins. This occurs particularly in needed by the FPGA for your application.
requirements. Transient response applications where the load current And third, use our product selector guide to
refers to a power supply’s ability to is high and it is not possible to place pick the appropriate part (Figure 6).
respond to abrupt changes in load the regulator circuit close enough to
current. A regulator should respond the FPGA power pins. Remote sensing Once you have determined the input
without significantly overshooting or resolves this issue by using a dedicated voltage, use Xilinx's Power Estimator
undershooting its setpoint and without pair of traces to accurately measure spreadsheet (www.xilinx.com/power)
sustained ringing or ripple in the output the voltage at the FPGA’s power-supply to get a list of all power supply rails
voltage. pins (Figure 5) and compensating and a rough estimate of the current
for the drop. Remote sensing is also consumption for each. Xilinx also
Synchronizing to an External Clock recommended for voltage rails with very provides XPower tools built into their
FPGAs are used in applications that tight tolerances (≤ 3%). ISE design environment that provide a
M

need power regulators to synchronize more accurate power requirement based

with common clocks to streamline Programming Options on resource utilization, clock frequency,
communication between the system Power regulators can include one or and toggle rates. Figure 7 shows an
controller and the power supplies. Many several programming options such as example of Xilinx Power Estimator
POLs provide an external SYNC pin to output voltages, switching frequency, spreadsheet for Virtex-7 FPGAs.
allow the system designer to synchronize and slew rate. A traditional approach is Maxim recommends that you extract the
one or multiple regulators to a common to provide this capability through I/O voltages and currents into a table and
system clock. pins on the regulator that can be tied to determine your power architecture. Every
a specific resistance value. Depending time you add an intermediate regulator,
Multirail Regulators and on the resistance, an appropriate you might be sacrificing system-level
Multiphase Operation programming option is chosen. This power efficiency. This is because you get
FPGAs need multiple regulators for can quickly become complicated and less than 100% efficiency at each stage.
regulating all the supply rails. Quite often unwieldy depending on the number of Going from the main system input voltage
dual/triple/quad regulators are used for programming options. Increasingly, many to all the FPGA rails is an ideal method
optimal layout. Multirail regulators can power regulators provide an I2C or SPI except when the efficiency loss is so high
often be used in a multiphase configuration interface to digitally program the options with one stage (typically when either VIN/
operating in parallel to increase the current with a tiny register set. Quite often, these VOUT voltage change is high or currents
capability. Their switching frequencies options can be changed in the field by a handled are in excess of 50A) that you are
are synchronized and phase shifted by system microcontroller as required. better off dividing it into multiple stages.
360/n degrees, where n identifies each Identify the power requirements of other
phase. Multiphase operation yields lower Choosing Power Regulators external components such as memories,
input ripple current, reduced output ripple Most power-supply vendors complicate processors, data converters, and I/O
voltage, and better thermal management. choosing power supply regulators for drivers to determine whether you can
They are best for VCC and transceiver FPGAs by providing too many tools and regulate them together with the FPGA
power rails. web interfaces just to pick a part. Not rails based on total current. Also, note any
Maxim. Our goal is to provide you with special sequencing, ramp-up, soft-start,
the right information to evaluate and and other requirements. Finally, evaluate
choose the power supply you need in a cost, efficiency, and size targets. A checklist
few simple steps. is provided in Table 2 to help you.
V
VOUT VIN
V REGULATOR
VCC VSENS+

REMOTE
VCCIO FEEDBACK FPGA
VCC SENSE
AMP VSENS-
NONMONOTONIC RAMP

t t GND GND

Figure 3. Sequential Tracking Figure 4. Nonmonotonic Startup Voltage Ramp Figure 5. Remote Sensing

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Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

Which Features Do You Need? User Preferences Optional Features

Using Table 2, you should have a thorough Most users have preferences for their Depending on your application, you
understanding of your FPGA’s power power-supply design. On the one hand, might need advanced system control
budget, its supply rails, and other system- some customers want to buy a PWM using PMBus or other means. You might
level considerations. Let us examine the controller and use external MOSFETs, need multi-phase operation to handle
must-have power regulator features for external compensation, and an external high currents, remote sensing capability,
every FPGA designer, the application- system control. On the other hand, synchronization to an external clock, and
specific optional features, and preferences. some customers prefer a fully integrated power monitoring functions. Or you might
controller and MOSFETs as well as need to control the slew rate to mitigate
Necessities built-in internal compensation, digital voltage ripple on SerDes channels in high-
Every FPGA design needs power programmability, and system control. speed transceiver applications.
regulators with the ability to select the Maxim provides parts for the entire
spectrum of customer choice. Keeping the Digital Power Control
output voltage, as well as sequencing,
adjustable soft-start, monotonic ramp- digital designer in mind, we are developing A new trend in the industry is the use
up, and a good transient response. a family of parts with GUI-based program- of digital control loop regulators for
ming facilitated by I2C. enhanced automatic compensation
to simplify design and reduce cost.
Most digital power solutions today
use proportional-integral-derivative
CHOOSING YOUR FPGA POWER REGULATORS (PID) controllers, but performance is
• USE THE FPGA VENDOR POWER ESTIMATION SPREADSHEET. compromised because of the windowed
1 ADCs used. Maxim’s InTune™ digital-
• IDENTIFY ALL THE REQUIRED VOLTAGE RAILS AND CURRENTS.
• USE THE MAXIM POWER REGULATOR CHECKLIST.
control power products are based
2
• IDENTIFY/DECIDE: VIN, VOUT, IOUT, SEQUENCE, I2C/PMBus, PROGRAMMABILITY, SPECIAL NEEDS. on state-space or model-predictive
control, rather than the PID control used
3 • USE THE MAXIM PRODUCT SELECTOR TO CHOOSE PARTS.
by competitors. The result is a faster
Figure 6. Choosing Your FPGA Power Regulators transient response. Unlike competing
PID controllers, the InTune architecture
uses a feedback ADC that digitizes the
Table 2. FPGA Power Supply Checklist
full output voltage range. Its automatic
Checklist Item Answer compensation routine is based on
Basic Requirements   measured parameters providing better
accuracy, and thus better efficiency.
Identify input voltage rail (e.g., VIN = 5V)  
List all FPGA voltage rails and the current required for
each (e.g., VCC = 0.85V at 5A, VCCIO = 1.5V at 2A)
  Design and Simulate the
Sequencing requirements and order (timing diagram),   Power Supply
power-on/-off, under fault recovery While many power regulators come with
Switching frequency desired   built-in compensation, you still need to
Soft-start ramp rate (e.g., 5ms)   choose the right inductor value for your
unique output current requirement. If the
Single-/multirail regulators required?  
regulator needs external compensation,
Internal compensation required?   you need to select the right RC values
Configuration: I2 C or use resistor values?   to compensate for your output voltage
Advanced Features and Requirements   in the control loop. Maxim provides a
Output voltage ripple targets (mV) for transceivers   web-based design and simulation tool
Sink current capability (for DDR)   for power supplies called EE-Sim (www.M

maximintegrated/eesim). It asks for

Synchronize to external clock?  
your design requirements and outputs a
Power-up in prebiased load?   complete schematic and bill of materials.
PMBus control or I2C/SPI required?   You can make changes to the component
Protection features   values on the schematic to fine-tune your
Remote sensing capability needed?   power design.

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PICK THE
DEVICE 1 3
CAPTURE
DETAILS
THE VOLTAGE
RAILS AND
REQUIRED
CURRENT AND
MOVE TO
CHECKLIST
(TABLE 2)

2 ENTER THE UTILIZATION

AND PERFORMANCE OF ALL
FPGA RESOURCES
Figure 7. Xilinx Power Estimator Tool
PICK INPUT VOLTAGE, OUTPUT VOLTAGE, LOAD CURRENT,
1
SWITCHING FREQUENCY, AND OTHER BASIC PARAMETERS.

REVIEW GAIN/PHASE MARGIN, TRANSIENT

ANALYSIS, STEADY-STATE ANALYSIS.
3
YOU CAN DOWNLOAD THE DESIGN AND
SIMULATION ENGINE FOR FREE.

TOOL GENERATES A
SCHEMATIC. CHANGE
2
THE VALUES OF R, C,
AND L IF NEEDED.

Figure 8. EE-Sim Simulation Tool (MAX8686)

  11
Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

EE-Sim also provides rapid simulation Let us consider both the IC cost and the QFN and CSP packages simplify PCB
of your power regulator design. Unlike total solution cost. A good FPGA power design. With GUI-based programming,
SPICE models that take a long time to regulator should integrate into the IC the choosing the power regulator options
converge, making it frustrating to design, necessary features previously discussed. is as easy as choosing the FPGA
EE-Sim relies on advanced SIMPLIS This reduces the overall solution cost programming options in ISE .M

models with a simple web interface that and size.

is quick and easy. An EE-Sim example is
shown in Figure 8, which recommends Efficiency is a function of the power
the external component values as well as architecture of the primary and secondary
Bode plots to identify phase margin and stage regulators as well as a function
efficiency plots. If you want to download of the performance of each individual
the simulation model for additional regulator. Maxim’s power regulators are
analysis offline, a free version of EE-Sim acclaimed as the most efficient for a given
power level. Plus, we offer 1% regulation
is available.
accuracy over PVT, an accuracy that very
Addressing Your Requirements: few vendors can match.
Cost, Size, Efficiency, and Ease Finally, there is ease of use. Maxim’s
of Use FPGA power regulators are user-friendly
and becoming even easier to use. Almost
In addition to voltages, currents, and
all our FPGA power regulators have
features, you will most likely choose your
internal MOSFETs. Several have internal
power supply based on few key metrics:
compensation circuits for common
cost, size, efficiency, and ease of use.
output voltages. Our thermally efficient

12
www.maximintegrated.com/xilinx Analog Solutions for Xilinx FPGAs Product Guide

Featured Products
Highly Integrated Step-Down DC-DC Regulator Benefits
Provides Up to 25A for High Logic Density FPGAs • Enough margin to safely power FPGAs
from popular 5V/12V inputs
MAX8686 ◦◦ Wide 4.5V to 20V input voltage
range
The MAX8686 current-mode, synchronous PWM step-down regulator with
◦◦ Adjustable output from 0.7V to 5.5V
integrated MOSFETs provides the designer with a high-density, flexible solution for a
◦◦ 25A output capability per phase
wide range of input voltage and load current requirements. This device combines the
◦◦ 300kHz to 1MHz switching frequency
benefits of high integration with a thermally efficient TQFN package.
• Enable high voltage regulation accuracy
for FPGAs with low core voltages
◦◦ 1% accurate internal reference
VIN = 12V
IN BST ◦◦ Differential remote sense

PGND LX
VOUT = 1.2V/25A • Designed to simplify powering FPGAs/
CPLDs
RS+
◦◦ Monotonic startup (prebias)
REFIN MAX8686
RS-
◦◦ Adjustable soft-start to reduce inrush
current
PHASE/REFO CS+
◦◦ Output sink and source current
COMP CS- capability
POK
POK OUTPUT ◦◦ Reference input for output tracking
EN/SLOPE • Integrated protection features enable
ENABLE
INPUT
robust design
◦◦ Thermal overload protection
FREQ SS GND ILIM
◦◦ Undervoltage lockout (UVLO)
◦◦ Output overvoltage protection
◦◦ Adjustable current limit supports
a wide range of load conditions
• 6mm x 6mm, TQFN-EP package
reduces board size

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Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

Dual, 4MHz Internal FET Step-Down DC-DC Benefits

Regulator Reduces Size and Cost • Designed to simplify powering
FPGAs/CPLDs
MAX15021 ◦◦ Monotonic startup (prebias)
◦◦ Internal digital soft-start to reduce
The MAX15021 dual output, synchronous PWM step-down regulator with integrated
inrush current
MOSFETs provides the designer with a high-density solution that maximizes board
◦◦ Sequencing and coincidental/
space and reduces the overall solution cost.
ratiometric tracking
VOUT1 • Reduces solution size
VIN CI2
◦◦ Fast 4MHz switching minimizes
R1OUT2
RI2 inductor size
C1 ◦◦ 180° out-of-phase switching
R1
CF2 RF2 reduces input ripple current
R2OUT2 ◦◦ Lead-free, 28-pin, 5mm x 5mm
C2 CIN2 CDD2 CCF2
TQFN-EP package

AVIN EN2 PVIN2 DVDD2 FB2 COMP2 L2

• Flexible and adjustable voltage and
LX2 VOUT2 power ranges ensure compatibility
with a variety of FPGAs
RS2
COUT2 ◦◦ Allows easy reuse among multiple
CS2 FPGA designs
PGND2
VIN ◦◦ Reduces total design time and
CDD1
inventory holding costs
DVDD1
◦◦ 2.5V to 5.5V input voltage range
EN1
VIN
VAVIN ◦◦ 0.6V to 5.5V adjustable output
CIN1
◦◦ Output current capabilities of 4A
PVIN1
(reg. 1) and 2A (reg. 2)
MAX15021 L1 VOUT1
◦◦ 500kHz to 4MHz switching
LX1
frequency
RS1
COUT1 • Operates over the -40°C to +125°C
CS1 temperature range
PGND1

CI1

R1OUT1
RI1

FB1
RT SGND SEL COMP1
R2OUT1
PGND SGND
CF1 RF1

RT CT
CCF1

14
www.maximintegrated.com/xilinx Analog Solutions for Xilinx FPGAs Product Guide

Example Designs for Xilinx FPGAs

VIN = 12V VIN = 12V

MAX8686 x 2 VCCINT, VCCBRAM

DC-DC 1V, 20A
VCCO MAX8686
VCCAUX, VCCAUX_IO, VCCO, 3.3V, 8A DC-DC
MAX8686 VCCADC, MGTVCCAUX
DC-DC 1.8V, 6A VCCO MAX8686
2.5V, 8A DC-DC
MAX8686 MGTAVCC
10mVRIPPLE 1.0V, 6A VCCO MAX8654
1.5/1.35V, 4A DC-DC
MAX8654 MGTAVTT, MGTAVTTRCAL VCCAUX_IO 2.0V, 3A
10mVRIPPLE 1.2V, 4A

MAX8654
DC-DC

POWER-ON SEQUENCING ORDER

Figure 9. Virtex-7 FPGA Power Architecture Example

VIN = 12V VIN = 12V

MAX8686 VCCINT, VCCBRAM

DC-DC 1V, 6A
VCCO MAX8686
VCCAUX, VCCAUX_IO, VCCO, 3.3V, 8A DC-DC
MAX8686 VCCADC, MGTVCCAUX
DC-DC 1.8V, 6A VCCO MAX8686
2.5V, 8A DC-DC
MAX8686 MGTAVCC
10mVRIPPLE 1.0V, 6A VCCO MAX8654
1.5/1.35V, 4A DC-DC
MAX8654 MGTAVTT, MGTAVTTRCAL VCCAUX_IO 2.0V, 2A
10mVRIPPLE 1.2V, 4A

MAX15041
DC-DC

POWER-ON SEQUENCING ORDER

Figure 10. Kintex-7 FPGA Power Architecture Example

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Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

Example Designs for Xilinx FPGAs (continued)

VTT, 0.75V, 1A
DDR3 TERMINATION

VIN = 5V REFIN MAX1510 IN VIN = 5V

SOURCE/SINK
LDO

VCCO, VCCAUX 1.8V, 2A MAX15053

VCCODDR, 1.5V, 2A MODULE
MAX15021
VCCADC, 1.8V 150mA MAX1983
DUAL DC-DC
LDO
VCCINT, VCCBRAM 1V, 3A
VREFP, 1.25V, 5mA MAX6037A
VOLTAGE REFERENCE 0.2%, 50ppm/°C

POWER-ON SEQUENCING ORDER

Figure 11. Artix-7 FPGA Power Architecture Example

VTT, 0.75V, 1A
DDR3 TERMINATION

MAX1510
VIN = 5V REFIN IN VIN = 5V
SOURCE/SINK
LDO

VCCODDR, 1.5V, 1.5A

MAX15021 VCCO 1.8V, 0.8A MAX15053
DUAL DC-DC MODULE
VCCINT, 1V, 1.3A
VCCADC, 1.8V 150mA MAX1983
ADJUSTABLE VCCO, 3.3/2.5/1.8V, 2A LDO
MAX15021
DUAL DC-DC VREFP, 1.25V, 5mA MAX6037A
VOLTAGE REFERENCE 0.2%, 50ppm/°C
VCCAUX 1.8V, 0.8A

POWER-ON SEQUENCING ORDER

Figure 12. Zynq Extended Processing Platform Power Architecture Example

16
www.maximintegrated.com/xilinx Analog Solutions for Xilinx FPGAs Product Guide

Selector Guide and Tables

Core Power Regulator, VCCINT (0.9V to 1.2V Depending on FPGA/CPLD Generation)
Input Voltage (V) ≤ 500mA ≤ 1A to 1.8A ≤ 2A to 5A ≤ 5A to 10A ≤ 30A
MAX8516 LDO
MAX8526 LDO
MAX8517 LDO
MAX8527 LDO
MAX8518 LDO MAX8566 Buck
MAX8528 LDO
1.8 MAX8902 LDO MAX8526 LDO MAX8646 Buck MAX1956 Controller
MAX8556 LDO
MAX8527 LDO MAX1956 Controller
MAX8557 LDO
MAX8528 LDO
MAX8643 Buck
MAX8794 LDO
MAX8526 LDO
MAX8527 LDO
MAX8528 LDO
MAX8516 LDO
MAX8902 LDO MAX15053 Buck MAX15039 Buck
MAX8517 LDO
2.7 to 5.5 MAX1983 LDO MAX8643 Buck MAX15112 Buck MAX15118 Buck
MAX8518 LDO
MAX8649 Buck MAX15038 Buck MAX15108 Buck
MAX8649 Buck
MAX15050 Buck
MAX15051 Buck
MAX17083 Buck
MAX8654 Buck MAX8686 Buck
MAX15036 Buck
MAX8686 Buck MAX8597 Controller
MAX15036 Buck MAX15036 Buck MAX15037 Buck
4.5 to 14 MAX8598 Controller MAX8598 Controller
MAX15037 Buck MAX15037 Buck MAX15066 Buck
MAX8599 Controller MAX8599 Controller
MAX8654 Buck
MAX15026 Controller MAX15026 Controller
MAX15006 LDO MAX8597 Controller
MAX15007 LDO MAX17502 Buck MAX8792 Controller MAX8598 Controller
MAX8792 Controller
4.5 to 24 MAX17501 Buck MAX15041 Buck MAX15041 Buck MAX8599 Controller
MAX15026 Controller
MAX15041 Buck MAX8792 Controller MAX15026 Controller MAX15035 Buck
MAX1776 Buck MAX15026 Controller
MAX8597 Controller
MAX15041 Buck MAX8598 Controller
MAX15026 Controller
MAX15026 Controller MAX8599 Controller
4.5 to 28 MAX15041 Buck MAX15041 Buck MAX15046A/
MAX15046A/ MAX15026 Controller
MAX15046B Controller
MAX15046B Controller MAX15046A/
MAX15046B Controller

Auxiliary, I/O, and MGT Power Regulators (1.2V, 1.5V, 1.8V, 2.5V, 3.3V)
Input Voltage (V) ≤ 500mA ≤ 1A to 1.8A ≤ 2A to 5A ≤ 5A to 10A ≤ 30A
MAX8516 LDO
MAX8517 LDO
MAX17016 Buck
MAX8518 LDO MAX8556 LDO
MAX15108 Buck MAX1956 Controller
1.8 MAX8902 LDO MAX8526 LDO MAX8557 LDO
MAX1956 Controller MAX8792 Controller
MAX8527 LDO MAX8794 LDO
MAX8792 Controller
MAX8528 LDO
MAX8794 LDO
(Continued on following page)

  17
Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

Auxiliary, I/O, and MGT Power Regulators (1.2V, 1.5V, 1.8V, 2.5V, 3.3V) (continued)
Input Voltage (V) ≤ 500mA ≤ 1A to 1.8A ≤ 2A to 5A ≤ 5A to 10A ≤ 30A
MAX15118 Buck
MAX15039 Buck
MAX15038 Buck MAX15112 Buck
MAX8654 Buck
MAX15039 Buck MAX17016 Buck
MAX15108 Buck
MAX15050 Buck MAX1956 Controller
MAX15053 Buck MAX17016 Buck
2.7 to 5.5 MAX8902 LDO MAX17083 Buck MAX15026
MAX15038 Buck MAX1956
MAX15026 Controller
Controller
Controller MAX8792 Controller
MAX8792
MAX1956 Controller MAX8598 Controller
Controller
MAX8599 Controller
MAX8655 Buck
MAX15041 Buck MAX15035 Buck
MAX17016 Buck
MAX15036 Buck MAX8654 Buck
MAX15035 Buck
MAX15037 Buck MAX17016 Buck
MAX8902 LDO MAX8792 Controller
4.5 to 14 MAX15041 Buck MAX8654 Buck MAX8792
MAX1776 Buck MAX15026
MAX5089 Buck Controller
Controller
MAX15026 MAX15026
MAX8598 Controller
Controller Controller
MAX8599 Controller

Multiple Output Power Regulators

Input Voltage (V) Quad Regulators ≤ 2A to 3A per Output ≤ 5A per Output ≤ 15A per Output 25A per Output
MAX8833 Dual Buck
1.8 — MAX8833 Dual Buck — —
MAX8855 Dual Buck
MAX15021 Dual Buck
2.7 to 5.5 — — — —
MAX15022 Dual Buck
MAX17017 MAX15002 Dual MAX15002 Dual
1 Controller, 2 Controller Controller
Bucks, 1 LDO MAX15048 Triple MAX15048 Triple MAX15002 Dual
4.5 to 14 —
MAX17019 Controller Controller Controller
1 Controller, 2 MAX15049 Triple MAX15049 Triple
Bucks, 1 LDO Controller Controller
MAX15002 Dual MAX15002 Dual MAX15002 Dual
Controller Controller Controller MAX15002 Dual
MAX17017 MAX15023 Dual MAX15023 Dual MAX15023 Dual Controller
1 Controller, 2 Controller Controller Controller MAX15023 Dual
Bucks, 1 LDO MAX17007B Dual MAX17007B Dual MAX17007B Dual Controller
4.5 to 28
MAX17019 Controller Controller Controller MAX15034 Dual
1 Controller, 2 MAX15048 Triple MAX15048 Triple MAX15048 Triple Controller
Bucks, 1 LDO Controller Controller Controller MAX17007B Dual
MAX15049 Triple MAX15049 Triple MAX15049 Triple Controller
Controller Controller Controller

Note: Some applications can require forced air cooling to achieve full output current. Voltage ranges can vary slightly. Refer to the data sheet for the
specific voltage range for each part. Minimum VOUT is 1.25V for the MAX1776.

Specialty Parts
• MAX6037A voltage reference for XADC built-in A/D converter in 7 Series FPGAs
• MAX1510 DDR termination power regulator that can sink current
• MAX34440 multirail PMBus controller used to control many regulators, fans, and log faults
• Maxim also provides the entire range of supporting power functions such as isolated power regulators, sequencers,
supervisors, temperature monitors, and PMBus system monitors

18
www.maximintegrated.com/xilinx Analog Solutions for Xilinx FPGAs Product Guide

Signal Conversion Solutions for FPGAs

Overview A Practical Signal Chain Table 3. Parameters Measured in Many Systems

We live in an analog world. Human sight, The analog input portion of the Dimension Pitch Position
hearing, smell, taste, and touch are analog circuit accepts analog signals from a Intensity Energy Pressure
senses. And since real-world signals are variety of sensors through factory or Impedance Temperature Humidity
analog, they need to be converted into the field wiring. These sensors are used
Density Speed Frequency
digital domain by ADCs before they can to convert physical phenomena
as shown in Table 3 into electrical Viscosity Time of flight Phase
be processed by an FPGA. After digital
processing is completed, digital signals representations. Many sensors Velocity Distance Time
often need to be converted back to the do not create their own signals, Acceleration Pressure Salinity
analog domain by DACs. But the analog but require an external source Water purity Torque Volume
story does not begin or end with data for excitation. Once excited, they
Weight State of charge Gases
conversion. Op amps, instrumentation generate the signal of interest.
Mass Conductivity Ph
amplifiers (IAs), and programmable
The signal chain in Figure 13 starts Resistance Dissolved oxygen Voltage
gain amplifiers (PGAs) come into play to
on the left side with a signal from
preprocess analog signals for the ADCs Capacitance Ion concentration Current
a sensor entering the analog
and postprocess analog signals after Inductance Chemicals Level
signal conditioning block. Before
the DACs. Rotation Charge (electrons)
the signal is ready to be sampled
Maxim makes highly integrated analog and by the ADC, its gain needs to
mixed-signal interface semiconductors be matched to the ADC’s input
that serve as the analog interfaces required requirements. Table 4. Actions That Devices Can Control
by FPGAs to make practical systems. Our Valves Contrast Acceleration
An analog input module receives
precision SAR and delta-sigma ADCs and Motors Humidity Switches
many different signals in a tough
DACs combine with low-power, high- Pressure Force feedback Lights
industrial environment. It is,
performance, space-efficient op amps,
therefore, essential to filter out Velocity Room entry Weight
comparators, and precision references to
as much noise as possible while Flow Sequence Speed
deliver the ever-increasing accuracy and
retaining the signal of interest
speed needed for your next design. Volume Authorization Meters
before converting the signal from
the analog-to-digital domain. Torque Attenuation Displays
Signal Conversion and FPGAS Frequency Equalization Calibration
Working Together Various implementations of the
Voltage Communication Time
signal chain are possible:
Using FPGAs in control circuits is common Current Gain (offset) Tools
to many applications, including medical, • A mux at the first stage followed Solenoids Flux density Pitch
automotive, and consumer electronics. by a common amplifying signal
Position Temperature Filters
The signal-chain block diagram in Figure 13 path into an ADC
Power Galvanometers
shows a generic control system. We sense • Individual amplifying channels
a parameter, make decisions in the FPGA, Brightness Air fuel ratios
and a mux prior to the ADC
and act to produce a physical action.
• With simultaneous-sampling
Different parameters are measured as ADCs and independent conditioning fault conditions. For example, sensors can
shown in Table 3 and processed in the amplifiers be remotely located from the analog input
FPGA. Then the system interacts with the with large amounts of common-mode
environment by the controlling devices The input stage is commonly required voltage that must be rejected. Amplifiers
shown in Table 4. Although the parameters to cope with both positive and negative are often used to help condition the
measured and controlled can differ, Figure 13 high voltages (e.g., ±30V or higher) to signals before processing.
represents a typical system. protect the analog input from external

ANALOG INPUT ANALOG OUTPUT

SENSORS ADC FPGA (µP) DAC ACTUATORS
CONDITIONING CONDITIONING

Figure 13. Block Diagram Showing a Common Signal-Chain Flow

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Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

Operational amplifiers (op amps) are criteria. Table 5 presents typical ADC ways to maintain constant voltages at
an important part of the analog signal- selection criteria. many outputs, while the DAC serves other
conditioning block. They are used as outputs.
analog-front-ends (AFEs) controlling gain, An ADC that is not an ideal match
offset, and anti-alias filtering prior to ADCs. can be used, and analog blocks can be Producing discrete, selectable, voltage-
Op amps offer high-voltage protection or employed to augment its functionality output (bipolar and unipolar), or
current-to-voltage conversion. Depending to meet the requirements. Exercise current-output conditioning circuits can
on the application, some parameters care during selection to ensure that any be an involved task. This is especially
can be more important than others. DC additional specified components provide true as one begins to understand the
applications require precision with low similar performance as the ADC. Rather necessity of controlling full-scale gain
input offset voltage, low drift, and low than using discrete components, it is also variations, the multiple reset levels for
bias current if the source impedance common to use an integrated AFE to buffer bipolar and unipolar voltages, or the
is significant. AC applications require or even replace the ADC. different output-current levels necessary
bandwidth, low noise, and low distortion. to provide the system design with
Once the data is converted, it is the most flexible outputs. For more
When amplifiers are driving ADCs, settling processed digitally in the FPGA. In some
time becomes a very important parameter. information about designing with DACs
systems, this is the end of the process as and ADCs, refer to the application note
Low temperature drift and low noise the data is sent to other digital devices library (www.maximintegrated.com/
are also critical requirements for the in the system, such as a server or PC. In converter-app-notes).
analog signal path. Errors at +25°C are other cases, the system needs to drive an
typically calibrated in the software. analog output. What is Critical?
Drift over temperature might need to be The critical parts of the block diagram or
controlled through calibration routines
Criteria for DAC Selection chain depend on the specific application.
because it can become a critical Analog output signals are required for A clean power supply, good filters,
specification in environments where situations in which a compatible transducer and noise-free op amps for signal
temperature is not constant. or instrument needs to be driven. Examples conditioning are important for a good
include proportional valves and current- SNR. Accuracy is greatly dependent on
Analog-to-Digital Conversion loop-controlled actuators. It can be part ADC and DAC resolution, linearity, and
Next in the signal chain is the ADC. The of a simple open-loop control system or stable voltage references.
ADC takes the analog signal and converts a complex control loop in a proportional-
integral-derivative (PID) system. The result For precise systems, DACs (and ADCs)
it to a digital signal. Depending on the require an accurate voltage reference.
application, the ADC requirements vary. of this output is sensed and fed back for PID
processing. The voltage reference is internal or
For example, the bandwidth of the input external to the data converter. In addition
signal dictates the ADC’s maximum The analog output begins with digital to many ADCs and DACs with internal
sampling rate so the selected ADC must data from the FPGA (Figure 13). references, Maxim offers stand-alone
have a sufficiently high sampling rate This digital data is converted into an voltage references with temperature
(greater than twice the input bandwidth). analog voltage or current signal using coefficients as low as 1ppm/°C, output
There are some communications a digital-to-analog converter (DAC). voltage as accurate as ±0.02%, and
applications where this rule does not apply. Signal-conditioning circuitry then output noise as low as 1.3µVP-P that can
The signal-to-noise ratio (SNR) and provides reconstruction filtering, offset, be used externally to the data converter
spurious-free dynamic range (SFDR) gain, muxing, sample/hold, and drive for ultimate precision and accuracy.
specifications of the system dictate the amplification as necessary.
ADC’s resolution, filtering requirements, As with the analog inputs,
and gain stages. It is also important to various implementations Table 5. Typical ADC Selection Criteria Matrix
determine how the ADC interfaces to are possible when multiple Input range: Resolution: Interface:
the FPGA. High-bandwidth applications analog outputs are needed. Unipolar Dynamic range Serial (I2C, SPI),
perform better using a parallel or Biploar ENOB Parallel (4, 8, 16, N)
fast serial interface, while in systems Maxim has precision DACs
ranging from below 8 bits Input type:
requiring easy galvanic isolation, SPI with Speed:
Single-ended Channels
unidirectional signaling is preferred. up to 18 bits of resolution BW
Differential
and up to 32 channels.
Simultaneous Reference Power
Criteria for ADC Selection Calibration DACs are
available from 4 bits to 16 Filtering: Other:
When selecting the right ADC for the bits, and our sample/hold 50Hz/60Hz PGA GPIO
application, the engineer must consider, amplifiers provide additional Rejection FIFO
review, and compare very specific device
20
www.maximintegrated.com/xilinx Analog Solutions for Xilinx FPGAs Product Guide

Along with creating a circuit design Design requirements often change at the calculators). Choose a calculator
that achieves a specified performance, eleventh hour. Maxim products are up to and fine tune it, depending on your
the designer is also usually required to the task. particular requirements. For example,
complete the process in a limited amount use Steve’s Analog Design Calculator to
of time. Easy-to-use development tools, Four scenarios come to mind: pick the ideal converter. Then fine-tune
including FMC and plug-in module • The customer changes the the accuracy and sampling rate using
development cards that directly connect specification just before delivery. another calculator.
with many FPGA development boards,
• The sales department needs to add a Other great aids are available on the
help integrate Maxim products into FPGA
must-have feature at the last minute. tools, models, and software page (www.
designs. Along with our many EV kits,
calculators, and application notes, these maximintegrated.com/design/tools). From
• The design does not fit in the ASIC or
tools allow the designer to complete their here, you have access to the EE-Sim tool
FPGA without going to the next larger
work more quickly and accurately. (simulations), a constantly updated library
device, thereby increasing cost and
of models (SPICE, PSpice , and IBIS), a
M

requiring the designer to move some

FPGA Challenges Facing a selection of BSDL files, and software.
circuits outside the device.
System Designer • Murphy’s Law strikes. Maxim has long been revered for the
quality and variety of our products as well
Many FPGA designers are accomplished Problems that analog engineers as the ease of use of our evaluation kits (EV
digital engineers; Maxim’s expertise is experience are often caused by low signal- kits). Many of our parts have been tailored
analog interface. These complementary to-noise, crosstalk, gain (span), offset for specific purposes. Hundreds of Maxim
skills optimize system performance and (zero), and linearity. External integrated EV kits and reference boards are available
cost. FPGA design has a large affinity circuits (IC) that resolve these issues through Maxim distributors.
with digital designers because FPGAs are amplifiers, ADCs, DACs, digital
are configurable digital systems. From potentiometers, filters, multiplexers, and Maxim has a dedicated team of
simulation to synthesis, everything is voltage references. Other issues that arise applications engineers ready to answer
done in a digital domain. are impedance matching, translation of your questions through email or over the
analog voltages and currents, self-blocking phone. We strive to respond to every
However, much uncertainty is introduced customer inquiry within one business day.
(where a radio transmitter interferes with
when these digital systems are tied to You can find a selection of links to answer
its own receiver), backlight LED, and touch
the analog world. Some of the questions many common inquiries, such as pricing or
controls. Analog ICs can be employed to
that system designers face are: delivery questions, at our Support Center
manage these functions, add features, and
“How much gain should be applied to a offload the FPGA. page (support.maximintegrated.com/
signal? center.mvp). Finally, and most importantly,
Other analog ICs partnered with FPGAs Maxim and our distribution partners' FAEs
“What analog filters should be used? in real-world designs include power stand ready to assist you.
supplies, margining and calibration,
“How to drive the ADC? battery chargers, power supervisor,
interface devices, temperature controllers
Summary
“How much resolution is needed?
and monitors, real-time clocks (RTCs), When you partner with Maxim, you have
“What speed is needed? watchdog timers, and precision resistors. a full-service organization dedicated to
supplying everything you need to complete
“What specs are critical? Maxim offers all of these types of devices. your FPGA design. With a wide selection
Using such components can save designs of lower power, fast, and accurate products
“How much output drive is required?
from errors and complications due to last in small packages plus easy-to-use design
“How to lower the noise?” minute changes. It can also reduce time- tools and boards, Maxim simplifies your
to-market, avoid a spin or redo, and allow a FPGA development process. In addition,
Answering these questions is where a project to succeed where others might fail.
world-leading analog company such as Maxim and our distribution partners’ FAEs
Maxim excels. With our large product are here to assist you.
Maxim Makes It Easy
portfolio and expertise in system design,
FPGA designers can count on Maxim Maxim offers many tools to help the
to have the right solution for their designer create, develop, verify, and
application. complete their designs, including
Maxim’s very own online calculators
(www.maximintegrated.com/tools/

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Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

Trapped Between Precision and Noise

In some applications, the designer might feel trapped by noise, precision required, and cost. A good design is one that satisfies the
customer’s requirements at an affordable price. An FPGA with internal data converters is a great advancement. However, such
converters do not meet the requirements for every application.
There are some important considerations about noise to factor in when evaluating one’s ADC or DAC needs. By their nature, digital
designs add noise into the equation. FPGAs operate at faster speeds (GHz communications are now common), resulting in the creation
of more noise.
Let us look at some rules of thumb concerning orders of noise magnitude. Power supplies typically have millivolts (mV) of noise. Noise
sources range from switching power supplies, power line or mains, radio interference, motors, arc welders, and digital circuits. An ADC
or DAC with a 3V full scale has a least significant bit (LSB) at the levels shown in Table 6.
It becomes readily apparent why noise is at odds with precision. We recommend sketching the design in block form, as well as
estimating noise and signal levels with a fellow designer. Jot down what is known about the project, input and output signals and values,
power requirements, and known block contents. See Table 6. If the system needs 8 bits of resolution at the output, are 10 or 12 bits at the
input sufficient? If there is 5mV of noise present in the system (56dB down), is a 24-bit converter with a dynamic range of 144dB is viable
or overkill? See how quickly reality sets in? In just a few minutes, we have defined the parameters of the project. Now the decision to use
the internal converter or an external one with a clean power supply is obvious.
Digital noise in particular is typically addressed as follows. First, use an external data converter, meeting your requirements with
separate, clean analog supplies and ground to maximize precision and accuracy. Second, oversample and average the signal. You get
approximately one extra bit of resolution for each 4x of oversampling.
Not all bits are created equal. We should be wary of marketing bits, which are commonly listed front and center on data sheets. The
real bits of converters take into account all nonlinearities and can be extracted by looking at other key parameters. For example, SINAD
performance is commonly used to determine the effective number of bits for SAR converters, while noise distribution of captured signal
calculates the noise-free bits in sigma-delta converters.
You also need to understand the application’s requirement for voltage and temperature stability and construct an error budget for the
combination of the data converter and the voltage reference. Maxim has a tool to simplify the task. You can find it in application note
4300: Calculating the Error Budget in Precision Digital-to-Analog Converter (DAC) Applications.

Table 6. Data Converter Resolution and LSB Voltage for 3V Full Scale
No. of Bits Decimal No. of Levels LSB
8 256 11.7mV
10 1,024 2.9mV
12 4,096 0.73mV
14 16,384 0.18mV
16 65,536 45.8μV
18 262,144 11.4μV
24 16,777,216 0.18μV

22
www.maximintegrated.com/xilinx Analog Solutions for Xilinx FPGAs Product Guide

Featured Products
24-/16-Bit Sigma-Delta ADCs Enable 32 Benefits
Simultaneous Channels • Simplifies digital interface to an FPGA

MAX11040K • Eight MAX11040K ADCs can be

interfaced
The MAX11040K sigma-delta ADC offers 117dB SNR, four differential channels, and • 106dB SNR allows users to measure
simultaneous sampling that is expandable to 32 channels (eight MAX11040K ADCs both very small and large input
in parallel). A programmable phase and sampling rate make the MAX11040K ideal voltages
for high-precision, phase-critical measurements in noisy PLC environments. With a
single command, the MAX11040K’s SPI-compatible serial interface allows data to • Easily measures the phase relationship
be read from all the cascaded devices. Four modulators simultaneously convert each between multiple input channels
fully differential analog input with a 0.25ksps to 64ksps programmable data-output- ◦◦ Simultaneous sampling preserves
rate range. The device achieves 106dB SNR at 16ksps and 117dB SNR at 1ksps. phase integrity on multiple channels

PI CS
g le S
Sin
FPGA

AVDD DVDD

AIN0+
ADC DIGITAL FILTER SYNC
AIN0-
REF0 CASCIN
CASCOUT
AIN1+
ADC DIGITAL FILTER SPI/DSP
AIN1- SPI/DSP
REF1 SERIAL CS
AIN2+ INTERFACE SCLK
4-channel, fully ADC DIGITAL FILTER
AIN2- DIN
differential bipolar inputs REF2 DOUT
AIN3+
ADC DIGITAL FILTER INT
AIN3-
REF3
N=8
MAX11040K SAMPLING
PHASE/FREQ N=2
XTAL ADJUSTMENT
REF 2.5V
OSCILLATOR
N=1 Fine/coarse sample-
rate and phase adjustment
XIN XOUT
AGND DGND

  23
Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

High Integration and a Small Package Create the Benefits

Industry’s Smallest Solution • Reduces cost and simplifies
manufacturing
MAX5815, MAX5825 ◦◦ Complete single-chip solution
◦◦ Internal output buffer and integrated
The MAX5815 and MAX5825 are a 4- and 8-channel, ultra-small, 12-, 10-, and
voltage reference
8-bit family of voltage output, digital-to-analog converters (DACs) with internal
reference that are well-suited for process control, data acquisition, and portable • Eliminates need to stock multiple
instrumentation applications. They accept a wide supply voltage range of 2.7V voltage references
to 5.5V with extremely low power (3mW) consumption to accommodate most ◦◦ 3 precision selectable internal
low-voltage applications. A precision external reference input allows rail-to-rail references: 2.048V, 2.5V, or 4.096V
operation and presents a 100kΩ (typ) load to an external reference. A separate • Provides industry’s smallest PCB area
VDDIO pin eliminates the need for external voltage translators when connecting ◦◦ 4-channel available in 12-bump WLP
to an FPGA, ASIC, DSP, etc. and 14-pin TSSOP packages
◦◦ 8-channel available in 20-bump
WLP and 20-pin TSSOP packages
MAX5815
INTERNAL 2.048V, 2.5V, OR 4.096V
VREF REFOUT
REFERENCE

SCL
BUFFER 12-BIT VO1
SDA

LDAC BUFFER 12-BIT VO2

I2C
RAIL-TO-RAIL OUTPUT
INTERFACE
WITH EXTERNAL REF
AND
CLR BUFFER 12-BIT VO3
CONTROL

VDDIO
BUFFER 12-BIT VO4

MAX5825
INTERFACE 2.048V, 2.5V, OR 4.096V
VREF REFOUT
REFERENCE

SCL BUFFER 12-BIT VO1

SDA
I2C
LDAC
INTERFACE RAIL-TO-RAIL OUTPUT
AND WITH EXTERNAL REF
CLR CONTROL

VDDIO
BUFFER 12-BIT VO7

24
www.maximintegrated.com/xilinx Analog Solutions for Xilinx FPGAs Product Guide

Selector Guide and Tables

Signal Solutions for FPGAs
Part Description Features Benefit
Maintain system calibration
20V, ultra-precision, low-
5.9nV/√Hz input voltage noise; 6µV and accuracy over time and
MAX44251/MAX44252 noise, low-drift, dual and quad
(max) offset; 20nV/°C offset drift temperature; improve system
amplifiers
accuracy
0.94nV/√Hz (MAX9632) and Enable full performance from
36V, high-bandwidth, low-noise
MAX9632, MAX9633 3nV/√Hz (MAX9633) input voltage high-resolution ADCs for more
single and dual amplifiers
noise; less than 750ns settling time accurate measurement
Wide 6V to 38V supply range; low
38V, precision, single and dual Allow operation in a variety of
MAX9943/MAX9944 100µV (max) input offset voltage;
op amps conditions
drive 1nF loads
High voltage and low femto-amp
Wide 4.75V to 38V supply range; low
38V, CMOS-input precision op input-bias current enables easy
MAX9945 input-bias current; rail-to-rail output
amp interfacing with ultra-high omhic
swing
sensors
Ensure precision signal
Industry’s lowest offset, low- 2µV (max) offset; 25nV/√Hz; 6.5MHz
MAX4238/MAX4239 conditioning at low frequencies
noise rail-to-rail output op amps GBW; no 1/f input-noise component
over time and temperature
Internal output buffer and voltage
1-channel, 16- and 18-bit reference buffer; separate VDD I/O Guarantee full accuracy at the
MAX5316/MAX5318
precision DACs voltage; rail-to-rail output buffer; load for precision operation
force-sense output 
Complete single-chip solution; Eliminates the need for voltage
4-channel, 12-bit DAC with
MAX5815 internal output buffer; 3 precision translators and multiple voltage
internal reference
selectable internal references references
Low-power consumption (80µA max);
Single-channel, low-power, Provides better resolution and
3mm x 3mm, 8-pin µMAX package;
MAX5214/MAX5216 14- and 16-bit, buffered voltage- accuracy while conserving
±0.25 LSB INL (MAX5214, 14 bit) or ±1
output DACs power and saving space
LSB INL (MAX5216, 16 bit)
Complete single-chip solution with
independent voltage for digital I/O
8-channel, low-power, 12-bit, Eliminates voltage level
MAX5825 (1.8V to 5V); internal rail-to-rail
buffered voltage-output DACs translators to save PCB area
output buffers; 3 selectable internal
or external references
Supply current is virtually
Ultra-low 1.3µVP-P noise (0.1Hz
independent of supply voltage,
to 10Hz, 2.048V output); ultra-
Ultra-low-noise, high-precision, providing predictable power
MAX6126 low 3ppm/°C (max) temperature
low-dropout voltage reference budget; does not require an
coefficient; ±0.02% (max) initial
external resistor, saving board
accuracy
space and cost
Two simultaneous-sampling with two
12-bit, 4-channel, simultaneous- Provide a cost-sensitive, high-
multiplexed inputs (four single-ended
MAX1377, MAX1379, sampling ADCs (2 x 2 single- integration 12-bit solution for
inputs total); 1.25Msps per ADC dual
MAX1383 ended or 2 x 1 differential power system monitoring and
or single SPI port; supports ±10V
inputs) motor control applications
from 5V supply (MAX1383)
14-/16-bit, 8-/6-/4-channel
simultaneous sampling SAR ADCs
Industry’s first single-supply
with high-impedance I/O technology No external buffers simplifies
MAX11046 bipolar ADCs with high-
that eliminates external buffers; circuitry; saves cost and space
impedance input
bipolar input with only a single +5V
analog supply
(Continued on following page)

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Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

Signal Solutions for FPGAs (continued)

Part Description Features Benefit
Easily scalable for up to eight
24-/16-bit sigma-delta Four fully differential ADCs in parallel; allows
MAX11040K ADCs cascadable up to 32 simultaneously sampled monitoring 3 voltages: 3 current
simultaneous channels channels; 106dB SNR at 16ksps plus neutral pair to address
power applications
High integration and small
MAX11160/MAX11161,
> 93dB SNR; integrated 5ppm packages (state package
MAX11162/MAX11163, 16-bit, 1-channel 500ksps SAR
reference option; available size) give smaller form factor
MAX11164/MAX11165, ADCs with integrated reference
bipolar ±5V input range with and lower total system cost
MAX11166/MAX11167, and bipolar option
5V supply without compromising high
MAX11168
performance
Each channel is programmable
Allow multiple input sources to
16-bit, 4- and 8-channel SAR to be single-ended or
MAX1300/MAX1301, be supported in a single device,
ADCs with programmable input differential and unipolar or
MAX1302/MAX1303 increasing flexibility and saving
ranges up to 3 x VREF (4.096V) bipolar; integrated PGA (gain
cost
up to 4) and reference

Signal Solutions Evaluation Kits

Part Description Features

To evaluate MAX9632 and

MAX9632EVKIT, MAX9633 36V, high-bandwidth, Accommodates multiple op-amp configurations +4.5V to +36V
MAX9633EVKIT low-noise single and dual wide input supply range 0805 components
amplifiers

To evaluate the MAX9943 and

Flexible input and output configurations +6V to +38V single-
MAX9943EVKIT MAX9944 38V precision, single
supply range, ±3V to ±19V dual supply range
and dual op amps

To evaluate the MAX9945 38V Accommodates multiple op-amp configurations, wide input
MAX9945EVKIT
CMOS input precision op amp supply range 0805 components

Windows software provides a simple graphical user interface

M

To evaluate the MAX5316, the true

(GUI) for exercising the features of the MAX5316, includes a
accuracy 16-bit, voltage output
MAX5316EVSYS MAX5316EVKIT with a 16-bit MAX5316GTG+ precision DAC
DAC with digital gain and offset
installed (allows a PC to control the SPI interface and GPIOs
control
using its USB port)

Demonstrates the MAX5815,

Windows software provides a simple graphical user interface
the 12-bit, 4-channel, low-power
MAX5815AEVKIT (GUI) for exercising the device features, includes a USB-to-I2C
DAC with internal reference and
400kHz interface circuit
buffered voltage output

Demonstrates the MAX5216 16-bit

low-power, high-performance, Windows software, supports 14- and 16-bit DACs, on-board
MAX5216EVKIT
buffered digital-to-analog microcontroller to generate SPI commands, USB powered 
converter (DAC)

Demonstrates the MAX5825,

Windows software that provides a simple graphical user
the 12-bit, 8-channel, low-power
MAX5825AEVKIT interface (GUI) for exercising the device features, includes a
DAC with internal reference and
USB-to-I2C 400kHz interface circuit
buffered voltage output

Demonstrates the MAX5214 true

Includes on-board microcontroller to generate SPI commands,
resolution 14-bit low-power, high-
MAX5214DACLITE Windows software provides a simple graphical user interface
performance, buffered digital-to-
(GUI) for exercising the features of the MAX5214, USB powered
analog converter (DAC)
(Continued on following page)
26
www.maximintegrated.com/xilinx Analog Solutions for Xilinx FPGAs Product Guide

Signal Solutions Evaluation Kits (continued)

Part Description Features

Demonstrates the MAX1379 Complete evaluation system; convenient test points provided
MAX1379EVKIT 12-bit, 48-channel, on-board data-logging software with FFT capability; can also be
simultaneous-sampling ADCs used to evaluate the MAX1377

Provides a proven design Eight simultaneous ADC channel inputs; BNC connectors for all
to evaluate the MAX11046 signal input channels; 6V to 8V single power-supply operation
MAX11046EVKIT
8-channel, 16-bit, USB-to-PC connection compatible with five other MAX1104x
simultaneous-sampling ADC family members

Fully assembled and tested

Two MAX11040KGUU+s installed on the motherboard; up to three
MAX11040KEVKIT, PCB that evaluates the IC’s
more parts can be connected by cascading up to three daughter
MAX11040KDBEVKIT 4-channel, simultaneous-
boards
sampling ADC

Windows software provides a simple graphical user interface

(GUI) for exercising the features of the MAX11160; includes a
Proven design for 16-bit, high- companion MAXPRECADCMB serial interface board and the
MAX11160EVSYS
speed precision ADC MAX11160DBEVKIT with a 16-bit MAX11160 precision ADC
installed (allows a PC to control the SPI interface and GPIOs using
its USB port)

Proven design for 16-bit On-the-fly programmability of the input ranges based on multiples
MAX1300AEVKIT programmable input range of the voltage reference; support for single-ended and differential
precision ADC as well as bipolar and unipolar inputs

Demonstrates the industry’s

4-channel, 12-bit I2C SAR ADC with USB connection to a PC; self-
smallest SAR ADC in a tiny
MAXADCLITE powered from the USB port; complete data acquisition system on
12-bump WLP packaging
a tiny EV kit
solution

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Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

Design Protection Solutions for FPGAs

Overview SRAM FPGAs, however, have fewer

safeguards to protect that IP (i.e., the
The MAC is then attached to the
message. The recipient of the message
Maxim’s secure information and configuration data) against illegal copying performs the same computation and
authentication (SIA) products offer and theft. The configuration data is stored compares its version of the MAC to the
low-cost, secure memory solutions in a separate memory chip and is read one received with the message. If both
that incorporate robust, crypto- by the FPGA at power-up. The read data MACs match, the message is authentic.
industry vetted authentication and is held in the SRAM memory cells in the To prevent replay of an intercepted
encryption schemes with best-in-class FPGA. This arrangement compromises (nonauthentic) message, the MAC
countermeasures against invasive (die- the security of the configuration data at computation incorporates a random
level) and side-channel (noninvasive) two stages: challenge chosen by the MAC recipient.
attacks. These solutions are ideal for
protecting design intellectual property, The configuration data bit stream is Figure 14 illustrates the general
managing licensing, controlling software exposed to eavesdropping during the concept. The longer the challenge, the
feature set upgrade in field-deployed power-up phase. more difficult it is to record all possible
equipment. responses for a potential replay.
Configuration data stored in SRAM
memory cells can easily be probed. To prove the authenticity of the
Identifying the Problem MAC originator, the MAC recipient
Today, designers can select FPGAs A potential cloner can easily gain generates a random number and sends
that employ various technologies to access to the configuration data using it as a challenge to the originator. The
hold the design configuration data these techniques and clone the original MAC originator must then compute
such as one-time programmable (OTP) design, thereby compromising the IP and a new MAC based on the secret key,
antifuses, reprogrammable flash-based profitability associated with the genuine the message, and the recipient’s
storage cells, and reprogrammable product. challenge. The originator then sends
SRAM-based configurable logic cells. the computed result back to the
The configuration data essentially Facing the Challenge recipient. If the originator proves
contains the IP related to the design or Higher-end FPGAs address these capable of generating a valid MAC for
the end product. security concerns with built-in any challenge, it is very certain that it
encryption schemes and identification knows the secret key and, therefore,
Both antifuse- and flash-based solutions
mechanisms, but these solutions are not can be considered authentic. This
provide relatively secure solutions
cost-efficient for high volume applications process is called challenge-and-
since the configuration data is stored
such as consumer electronics. However, response authentication. See Figure 14.
on the FPGA chip and there are
these applications still require a way to
mechanisms that prevent the stored Numerous algorithms are used to
protect their IP from piracy. Furthermore,
data from being read out. Moreover, compute MACs, such as Gost-Hash,
the security scheme should be robust,
unless very sophisticated schemes such HAS-160, HAVAL, MDC-2, MD2, MD4,
easy to implement, and have minimal
as depacking, microprobing, voltage MD5, RIPEMD, SHA family, Tiger, and
impact on FPGA resources (i.e., the
contrast electron-beam microscopy, WHIRLPOOL. A thoroughly scrutinized
number of pins and logic elements), power
and focused-ion-beam (FIB) probing are and internationally-certified, one-way
consumption, and the cost of the overall
used to pry into the silicon and to disable hash algorithm is SHA-1, developed by
design.
security mechanisms, it is very unlikely the National Institute of Standards and
that the data can be compromised. Technology (NIST). SHA-1 has evolved
However, OEMs need to exercise
Presenting the Solution:
into the international standard ISO/IEC
strict control on licensing as contract Authentication 10118-3:2004. Distinctive characteristics
manufacturers tasked with FPGA The objective of the authentication of the SHA-1 algorithm are:
programming can produce more units process is to establish proof of identity
than authorized and sell them on the • Irreversibility: It is computationally
between two or more entities. Key-based
gray market. Such unauthorized devices infeasible to determine the input
authentication takes a secret key and
are indistinguishable from the authorized corresponding to a MAC.
the to-be-authenticated data (i.e.,
devices and can significantly impact an the message) as input to compute a • Collision resistance: It is impractical to
OEM’s profitability. message authentication code (MAC). find more than one input message that
produces a given MAC.

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www.maximintegrated.com/xilinx Analog Solutions for Xilinx FPGAs Product Guide

• High avalanche effect: Any change in for open-drain communication. Maxim’s the SHA-1 engine and other functions
input produces a significant change in DS28E01-100 1Kb protected 1-Wire in a small ASIC or CPLD. However, if
the MAC result. EEPROM with a SHA-1 engine is a good security is the device's only function,
For these reasons, as well as the fit for this scheme. The device contains a using an ASIC approach would probably
international scrutiny of the algorithm, SHA-1 engine, 128 bytes of user memory, cost more.
SHA-1 is an excellent choice for a secret key that can be used for chip-
internal operations, but cannot be read To leverage the security features of the
challenge-and-response authentication DS28E01-100, a reference authentication
of secure memories. from an outside source, and a unique,
unchangeable identification number. core enables the FPGA to do the following
steps:
Implementing the Solution The 1-Wire interface of the DS28E01-100
reduces the communications channel to 1. Generate random numbers for
A challenge-and-response authentication
just a single FPGA pin for the challenge- the challenge. On-chip random
scheme can be implemented inexpen-
and-response authentication. That number generators usually create
sively as part of an SRAM-based FPGA
minimizes the impact of the security pseudorandom numbers, which
system design (Figure 15). In this
solution since FPGAs are often I/O-pin are not as secure as real random
example, the secure memory device
limited. Alternate implementations can numbers.
uses only a single pin to connect to an
FPGA pin configured for bidirectional be constructed using a more generic I2C 2. Know a secret key that can be used
(open-drain) communication. A resistive interface implemented on the FPGA and for internal operations, but cannot
connection to VDD delivers power to the using the DS28CN01 (an I2C equivalent be discovered from an outside
secure memory and provides the bias of the DS28E01-100) or by implementing source.
3. Compute a SHA-1 MAC that involves
the secret key, a random number,
SYSTEM SECRET MICROCONTROLLER IMPLEMENTED IN FPGA
(FROM PROTECTED MEMORY) (MAC RECIPIENT) and additional data, just like the
secure memory.
CALCULATE SLAVE 4. Compare data byte for byte, using
SECRET
the XOR function of the CPU
MESSAGE DATA FROM
ACCESSORY DEVICE ALGORITHM RESULT
implemented in the FPGA.
COMPARISON
RANDOM CHALLENGE
For detailed information on the SHA-1
MAC computation, review the Secure
Hash Standard. Application note 3675:
1-Wire® INTERFACE
Protecting the R&D Investment with
SECURE MEMORY CHIP Secure Authentication provides technical
DEVICE DATA (MAC ORIGINATOR) details on the concept of authentication
ALGORITHM
SLAVE SECRET KEY
and the architecture of a secure memory.
(FROM SECURE MEMORY)
Microcontroller-like functionality is
typically available as a free macro
Figure 14. The Challenge-and-Response Authentication Process Proves the Authenticity of
a MAC Originator
from major FPGA vendors. The Xilinx
microcontroller function occupies 192
logic cells, which represents just 11% of a
VDD
Spartan-3 XC3S50 device.

DS28E01-100 SRAM-BASED FPGA

How It Works
SECURE 8-BIT MICROCONTROLLER USER DESIGN The DS28E01-100 is programmed
MEMORY AUTHENTICATION CORE CONFIGURATION
MEMORY
with an OEM-specific secret key and
1-Wire SIO TEST IFF TEST data. Programming can be done by the
OEM, or prior to shipment, by Maxim.
PASS ENABLE
The DS28E01-100 is effectively the
GND
ignition key for the FPGA design. The
OEM-specific secret key also resides in
the scrambled configuration data that
is programmed into the configuration
Figure 15. In This Simplified Schematic, a Secure 1-Wire Memory is Used for FPGA Protection (external) memory.

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Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

When power is applied, the FPGA predictable challenge (i.e., a constant) memory could set up a SHA-1 secret key
configures itself from its configuration causes a predictable response that can and EEPROM-array preprogramming
memory. Now the FPGA’s microcontroller be recorded once and then replayed service for the OEM. Maxim provides
function activates and performs the later by a microcontroller emulating such a service, where secure memory
challenge-and-response authentication, the secure memory. With a predictable devices are registered and configured
also known as identification friend or challenge, the microcontroller can at the factory according to OEM input
foe (IFF). This identification involves the effectively deceive the FPGA in and then shipped directly to the CM. Key
following steps: considering the environment as friendly. benefits of this service include:
The randomness of the challenge in this
1. The FPGA generates a random IFF approach alleviates this concern. • Eliminates the need for the OEM to
number and sends it as a challenge
disclose the secret key to the CM.
(Q) to the secure memory. Security can be improved further if the
secret key in each secure memory is • Eliminates the need for the OEM to
2. The FPGA instructs the secure device-specific: an individual secret key implement its own preprogramming
memory to compute a SHA-1 MAC computed from a master secret, the system.
based on its secret key, the challenge SHA-1 memory’s unique identification
sent, its unique identification • Only OEM-authorized third parties
number, and application-specific
number, and other fixed data, and have access to registered devices.
constants. If an individual key becomes
to transmit the response (MAC2) to public, only a single device is affected • The vendor maintains records of shipped
the FPGA. and not the security of the entire system. quantities, if needed for OEM auditing.
3. The FPGA computes a SHA-1 MAC To support individual secret keys, the
(MAC1) based on the same input FPGA needs to know the master secret Providing Proof of Concept
and constants used by the secure key and compute the 1-Wire SHA-1 The FPGA security method featured
memory and the FPGA’s secret key. memory chip’s secret key first before in Configuration Application Note
computing the expected response. XAPP780: FPGA IFF Copy Protection
4. The FPGA compares MAC1 with Using Dallas Semiconductor/Maxim
MAC2. If the MACs match, the For every unit to be built, the owner
DS2432 Secure EEPROMs has been
FPGA determines that it is working of the design (OEM) must provide
tested with Xilinx products. Xilinx
in a licensed environment. The FPGA one properly preprogrammed secure
states: “The system’s security is
transitions to normal operation, memory to the contract manufacturer
fundamentally based on the secrecy of
enabling/performing all of the (CM) that makes the product with
the secret key and loading of the key
functions defined in its configuration the embedded FPGA. This one-to-
in a secure environment. This entire
code. If the MACs differ, however, one relationship limits the number of
reference design, except the secret key,
the environment is considered authorized units that the CM can build.
is public abiding by the widely accepted
hostile. In this case, the FPGA takes To prevent the CM from tampering with
Kerckhoffs’ law.” The simple interface
application-specific actions rather the secure memory (e.g., claiming that
to programming and authentication
than continue with normal operation. additional memories are needed because
provided in this application note make
some were not programmed properly),
this copy protection scheme very easy
Why the Process Is Secure OEMs are advised to write-protect the
to implement. In this article on military
Besides the inherent security provided secret key.
cryptography, the Flemish linguist
by SHA-1, the principal security element There is no need to worry about the Auguste Kerckhoffs argues that instead
for the above IFF authentication process security of the 1-Wire EEPROM data of relying on obscurity, security should
is the secret key, which is not readable memory, even if it is not write-protected. depend on the strength of keys. He
from the secure memory or the FPGA. By design, this memory data can only contends that in the event of a breach,
Furthermore, because the data in the bit be changed by individuals who know only the keys would need to be replaced
stream is scrambled, eavesdropping on the the secret key. As a welcome addition, instead of the whole system.
configuration bit stream when the FPGA this characteristic lets the application
configures itself does not reveal the secret designer implement soft-feature Conclusion
key. Due to its size, reverse-engineering management—the FPGA can enable/ IP in FPGA designs can easily be
the bit stream to determine the design with disable functions depending on data that protected by adding just one low-cost
the intent of removing the authentication it reads from the SHA-1 secured memory. chip such as the DS28E01-100 and
step is very time-consuming, and thus, is a
It is not always practical for the OEM uploading the FPGA with the free
prohibitively difficult task.
to preprogram memory devices before reference core. The 1-Wire interface
Another critical security component delivery to the CM. To address this enables implementation of the security
is the randomness of the challenge. A situation, the manufacturer of the secure scheme over a single FPGA pin.

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Selector Guide and Tables

Secure Information and Authentication Solution for FPGAs
Part Description Features Benefit
Communicate and control over
User-customizable read/write/
1-Wire 1Kb SHA-1 secure a single dedicated contact,
DS28E01-100 OTP page modes; ±8kV HBM
EEPROM minimizing space and pin
with ±15kV IEC ESD protection
impact

Secure Information and Authentication Evaluation Kit

Part Description Features
Battery-powered single cell Li-ion 18650
AES-S6EV-LX16-G Avnet Spartan 6 Evaluation Board
(~2500 mAh)
DS28E01-100 plug-in module to drive test Interfaces to Avnet-made Xilinx Spartan-6 LX16
DS28E01-100 Plug-In Module
PicoBlaze™ SHA-1 authentication design evaluation kit (AES-S6EV-LX16-G)
Starter kit board includes Maxim’s DS2460,
DSAUTHSK Maxim secure memory evaluation kit DS2482-100, DS28CN01, and DS28E01-100
devices for rapid development

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Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

Interfacing High-Speed DACs and ADCs to FPGAs

Introduction Data Converter-to-FPGA provide simplified design and increased

robustness. Maxim offers octal (eight)
As the speed and channel count of Digital Interface Solutions channel, high-speed ADCs with serial
data converters increase with each new Maxim has added features to its LVDS outputs for high-density/low-power
generation, timing and data integrity RF-DACs to simplify the interface to applications such as ultrasound. On
between these devices and FPGAs FPGAs. Maxim develops RF-DACs with some dual-channel, high-speed ADCs
become more challenging. Maxim 2:1 or 4:1 multiplexed LVDS inputs to and DACs, Maxim offers selectable dual
works closely with industry-leading reduce the RF-DAC input data rate to parallel CMOS or single multiplexed
FPGA suppliers to define requirements a level compatible with current FPGA parallel CMOS interfaces as a trade-off
for digital interfaces between the technology. Using the 2:1 multiplexed for I/O pin count and interface speed.
FPGAs and high-speed data converters. input mode, one can reduce the I/O pin
This collaboration to overcome these count requirements, routing complexity, Integrated DLL Simplifies
challenges ensures compatibility, thye and board space. Alternatively, the
efficient use of resources, and ease of FPGA-to-RF-DAC
4:1 multiplexed input mode can be
design. employed to increase the timing margins Synchronization
for a more robust design and possible A functional diagram of the MAX5879
FPGA/Data Conversion Trends use of slower FPGA. 14-bit, 2.3Gsps RF-DAC is shown in
Data conversion and FPGA technology Figure 16. The RF-DAC is updated on
Newer generations of RF-DAC products
continue to evolve. Advancements in the rising edge of the clock (CLKP/
include an on-chip delayed-lock loop
performance and operating speeds have CLKN) and contains selectable 2:1 or
(DLL) to ease input data synchronization
led many applications to move signal 4:1 multiplexed input ports to reduce
with FPGAs, and a parity function to
processing from the analog domain to the I/O pin count or the input data rate
provide interface failure monitoring.
the digital domain. For example, instead of the RF-DAC to either 1150Mwps or
The RF-DAC data interfaces are system
of designing wireless transmitters with 575Mwps on each port.
synchronous to guarantee deterministic
a dual baseband I/Q DAC, an analog
latency. A source synchronous interface The integrated MAX5879 DLL circuit
quadrature modulator, and a frequency
generally has a one-clock-cycle latency ensures robust timing in the interface to
synthesizer, designers use a fast FPGA
uncertainty. Maxim’s RF-DACs offer a the FPGA. This is especially important
and a RF digital-to-analog converter
data scrambling feature to whiten the as the speed of the devices increases
(RF-DAC). A digital quadrature
spectral content of the incoming data to and the data window becomes smaller
modulator is implemented in the FPGA
eliminate potential data-dependent spurs. (i.e.,data transitions occur more
to upconvert the signal digitally, which
is then synthesized by the RF-DAC at frequently). A simplified block diagram
A final consideration in interfacing
the required frequency. Benefits of a of the clocking scheme using an FPGA
a data converter to an FPGA is data
digital RF transmitter over an analog and the DLL of the MAX5879 is shown
clock speed. Maxim’s RF-DACs and
RF transmitter include eliminating I/Q in Figure 17. The DLL circuit ensures
RF-sampling ADCs support a wide
imbalance, increased carrier or channel data synchronization between the FPGA
variety of interface formats including
capacity, and the ability to support and the DAC by adjusting the phase of
single data rate (SDR), double date
multiple frequency bands using a the incoming data so the data eye is
rate (DDR), and quad data rate (QDR)
common hardware platform. However, centered on the internal clock (RCLK)
to match the maximum clock rate
to realize these benefits, ensure data edge that latches the data into the
specifications of different classes of
integrity and proper timing across the DAC. The DLL adjusts the phase of the
FPGAs.
digital interface between the RF-DAC incoming data (DATA) to the internal
and the FPGA. To meet the high-channel count data clock (RCLK), making it immune
conversion demands of applications to temperature and power-supply
Similarly, instead of designing wireless such as medical imaging, the interface variations.
receivers with a baseband ADC, an between high-speed ADCs and FPGAs
analog quadrature demodulator (or If a DLL is not present, the designer
has evolved from parallel to high-speed
mixer), and a frequency synthesizer, needs to ensure the digital data being
serial. Benefits of a serial interface
designers use a fast FPGA and a RF presented to the DAC is stable for a time
include fewer lines that provide a density
sampling analog-to-digital converter prior to the DCLK transition (tSETUP)
and cost advantage, as well as relaxed
(RF-ADC). and is held for a period of time after
delay-matching specifications that
the transition (tHOLD). After factoring

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SO/LOCK SE MUX RF RZ

DAP[13:0]
FREQUENCY
DAN[13:0] 14 x 2 RESPONSE
DBP[13:0] SELECT
DBN[13:0] 14 x 2
DCP[13:0]
DCN[13:0] 14 x 2 DATA 2:1 OR 4:1 14 OUTP
DDP[13:0] SYNC REGISTERED
MUX DAC
DDN[13:0] 14 x 2 OUTN
SYNCP
SYNCN 2 PARITY
XORP CHECK
XORN 2
MAX5879
PARP
PARN 2
DLL
PERR REFIO
DCLKP FSADJ
DCLKN 2 VOLTAGE DACREF
DCLKRSTP REFERENCE CREF
DCLKRSTN 2 REFRES

DCLKDIV DELAY DLLOFF CLKP/CLKN GND VDD1.8 AVCLK AVDD3.3

Figure 16. MAX5879 Functional Diagram

Dx[3:0][13:0]
PARP/N OUTPUT 575Mbps MAX5879
XORP/N SerDes x 4 t2 DATA REGs
4:1
MUX
ICLK OCLK RCLK

MATCH t3
DELAYS
PRBS OUTPUT
575MHz
PATTERN SerDes
PRBS SYNC
DLL
t2
ICLK OCLK

DCLK OPTIONAL
DIVIDE-
t0 CLOCK
BY-2
CLOCK DIVIDE-
MANAGEMENT OPTIONAL BY-2
LOGIC CIRCUIT CLOCK
DIVIDE-BY-2
CLKO DIVIDE-
t1
BY-2
CLKIN 575MHz
CLKP/CLKN
FPGA 2300MHz

t0 t 1

DCLK DCLK = OUTPUT DATA CLOCK FROM DAC TO FPGA. DLL ADJUSTS DELAY OF
t2 DCLK WHICH IN TURN ADJUSTS THE PHASE OF THE DATA WINDOW
(AND SYNC) SO IT IS CENTERED AROUND RCLK.

DATA DATA WINDOW DATA = (2 OR 4) x 14-BIT LVDS LINES + PARITY AND XOR LINES FROM FPGA

t3

SYNC SYNC = PSEUDORANDOM BIT SEQUENCE (PRBS) FROM FPGA THAT IS

SYNCHRONIZED WITH DATA AND CLOSES THE DLL LOOP

RCLK RCLK = INTERNAL DAC CLOCK TO LATCH INCOMING DATA FROM FPGA

Figure 17. Digital Interface Between the FPGA and the MAX5879 RF-DAC (in 4:1 Mux Mode)
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in temperature variation, the setup and compared to the parity received from the clock (FRAME). The ADC clock input
hold times in the product data sheet can FPGA. When the received and calculated (CLKIN) or sample clock is multiplied by
consume a large percentage of the valid parity bits do not match, a parity error 6 to derive the serial LVDS output clock
data window, making it challenging to flag is set high so the FPGA can detect (CLKOUT). Serial data on each 12-bit
design a robust high-speed FPGA-to- the fault and trigger a corrective action. channel is clocked on both the rising and
DAC interface. falling edges of CLKOUT. The rising edge
High-Speed Octal ADC of the frame-alignment clock (FRAME)
Data Scrambling and Parity has Serial FPGA Interface corresponds to the first bit of the 12-bit
Check Ensure Reliable System serial data stream on each of the eight
that Slashes Pin Count and channels.
Performance Complexity Implementing an octal 12-bit, 50Msps
In some cases, periodic data patterns For high-channel count applications, a ADC with parallel CMOS outputs would
generated by the FPGA can create high-speed serial interface between the require 97 pins for the high-speed digital
data-dependent spurs that affect the data converter and the FPGA is preferred interface to the FPGA (approximately 5
overall performance of the system. The over a parallel interface because it times that of the serial LVDS interface).
MAX5879 RF-DAC contains an XOR simplifies the design and provides a The significantly higher pin count for a
data function that can be used to whiten denser and more cost-effective solution. parallel interface implementation would
the spectral content of the data bits and A functional diagram of the MAX19527 require significantly more FPGA I/O
prevent this situation from occurring. octal 12-bit, 50Msps ADC is shown in resources to capture the data. Larger
In addition, this DAC contains a parity Figure 18. The high-speed interface to packages for both the FPGA and the ADC
function that is used to detect bits errors the FPGA consists of 10 LVDS pairs (20 would also be required, which increase
between the FPGA data source and DAC pins): 8 high-speed serial outputs (1 the routing complexity and number of
and can be used for system monitoring. for each channel), 1 serial LVDS output printed circuit board layers needed for
The parity calculated by the RF-DAC is clock (CLKOUT), and 1 frame-alignment the design.

REFIO REFH REFL CS SCLK SDIO SHDN

CMOUT REFERENCE AND SPI, REGISTERS,

BIAS GENERATION AND CONTROL

IN1+ OUT1+
12-BIT
DIGITAL SERIALIZER LVDS OUT1-
IN1- ADC

IN2+ OUT2+
12-BIT
DIGITAL SERIALIZER LVDS OUT2-
IN2- ADC

IN8+ OUT8+
12-BIT
DIGITAL SERIALIZER LVDS OUT8-
IN8- ADC

CLKOUT+
6x
LVDS CLKOUT-
CLKIN+
CLOCK MAX19527
PLL
CIRCUITRY
CLKIN- FRAME+
1x
LVDS FRAME-

AVDD OVDD GND

Figure 18. MAX19527 Functional Diagram

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Selector Guide and Tables

High-Speed DACs and ADCs

Part Description Features Benefit
2:1 or 4:1 multiplexed LVDS Inputs Optimizes pin count or timing margin
Ensures data synchronization between the
Delayed-lock loop (DLL)
FPGA and the DAC
Parity check and error flag More easily ensures data integrity
MAX5879 14-bit, 2.3Gsps RF-DAC
Whitens spectral content to eliminate
Data scrambling
data-dependent spurs
Increased flexibility to interface to
SDR, DDR data interface
broader set of FPGAs
1:4 demultiplexed LVDS outputs Increased timing margin
MAX109 8-bit, 2.2Gsps RF-ADC Increased flexibility to interface to
SDR, DDR, QDR data interface
broader set of FPGAs
Serial LVDS outputs with programmable Compact ADC/FPGA interface; ensures
12-bit, octal 12-bit 50Msps test patterns data timing alignment
MAX19527 ADCs with serial LVDS
outputs Output drivers with programmable current Eliminates reflections to ensure data
drive and internal termination integrity (open eye diagram)
Simplifies high-speed FPGA/ADC
Programmable data output timing;
interface; eliminates reflections to ensure
MAX19517, 10-/8-bit, dual 130Msps programmable internal termination
data integrity (open eye diagram)
MAX19507 ADCs
Selectable data bus (dual CMOS or single Trade-off I/O and interface speed to
multiplexed CMOS) optimize FPGA resources

Selector Guide (FPGA Support Collateral)

Part Description Features
High-speed data converter Data source-based on Xilinx Virtex-5 FPGA, directly compatible with Maxim RF-DACs
HSDCEP
evaluation platform ( > 1500Msps) evaluation kits
Data converter evaluation Data source-based on Xilinx Virtex-4 FPGA, compatible with Maxim high-speed ADC and DAC
DCEP
platform evaluation kits

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Analog Solutions for Xilinx FPGAs Product Guide www.maximintegrated.com/xilinx

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© 2012 Maxim Integrated Products, Inc. All rights reserved. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated
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respective owners.
Rev. 1; November 2012