J Sign Process Syst (2017) 87:269–270

DOI 10.1007/s11265-017-1242-x

Guest Editorial: Implementation Issues in System-on-Chip

Published online: 6 April 2017

We are delighted to present this special issue of the Journal of Nurmi, the authors present a self-aware heterogeneous archi-
Signal Processing Systems on Implementation Issues in tecture for dynamically managing power and energy consump-
System-on-Chip. tion of the computing platform. Martin Broich and Tobias G.
During the past two decades, System-on-Chip (SoC) has Noll tackle energy efficiency and design complexity of com-
grown from a futuristic idea to a stabilized mainstream para- munications SoCs in their paper BOptimal Datapath Widths
digm for electronic system design and implementation. within Turbo and Viterbi Decoders for High Area- and
However, it keeps posing challenges to the designers and re- Energy-Efficiency^ (10.1007/s11265–016–1140-7).
searchers on multiple levels and in multiple disciplines. The In the article BA Customized Many-Core Hardware
aim of this special issue is to provide samples on quality re- Acceleration Platform for Short Read Mapping Problems
search targeting to solve implementation issues and investigate Using Distributed Memory Interface with 3D-stacked
design case studies from different points of view in SoC design. Architecture,^ (10.1007/s11265–016–1204-8) the authors
The issues addressed include power efficiency, complexity Pei Liu, Ahmed Hemani, Kolin Paul, Christian Weis,
management and security in embedded integrated systems. Mattias Jung and Norbert When apply advanced architecture
This issue consists of seven papers that are briefly and implementation techniques to a DNA sequencing
discussed as follows: problem. Essentially, it is an approach to improve the
The first article, by Feriel Ben Abdallah, Chiraz Trabelsi, performance of hash-index based short read mapping algo-
Rabie Ben Atitallah, and Mourad Abed on BModel-Driven rithm using a hardware acceleration platform. The paper
Approach for Early Power-Aware Design Space Exploration BDesign of a Residue Number System Based Linear System
of Embedded Systems^ (10.1007/s11265–016–1144-3) Solver in Hardware^ (10.1007/s11265–016–1146-1) by Jiri
discusses a model-driven engineering approach for SoC Bucek, Pavel Kubalik, Robert Lorencz and Tomas
design-space exploration. In BPower Mitigation by Zahradnicky is focused on error-free solution of dense linear
Performance Equalization in a Heterogeneous Reconfigurable systems using residual arithmetic in hardware. Their imple-
Multicore Architecture^ (10.1007/s11265–016–1142-5) by M. mentation is useful for solving large nonsingular systems of
Waqar Hussain, Henry Hoffmann, Tapani Ahonen and Jari linear equations with integer, rational or floating-point coeffi-
cients with arbitrary precision.
Christoforos Kachris, Dionysios Diamantopoulos,
* Peeter Ellervee Georgios Syrakoulis and Dimitrios Soudris present an
[email protected]
energy-efficient scheme for MapReduce that is a program-
Jari Nurmi
ming framework for distributed systems that is used for auto-
[email protected] matically parallelizing and scheduling the tasks to distributed
resources, in their paper BAn FPGA-based Integrated
1
Tallinn University of Technology, Ehitajate tee 5, MapReduce Accelerator Platform^(10.1007/s11265–016–
19086 Tallinn, Estonia 1108-7). And finally, security issues are addressed by Elena
2
Tampere University of Technology, Korkeakoulunkatu 1, Dubrova, Mats Näslund, Gunnar Carlsson, John Fornehed
33720 Tampere, Finland and Ben Smeets in the paper BTwo Countermeasures
270 J Sign Process Syst (2017) 87:269–270

Against Hardware Trojans Exploiting Non-Zero Aliasing He is head of Computer and Systems Engineering study programs at
bachelor and master levels. His research interests include behavioral
Probability of BIST^ (10.1007/s11265–016–1127-4).
and system level syntheses, hardware-software co-design, hardware de-
The special issue was preceded by the International scription languages. He has published over 100 internationally reviewed
Symposium on System-on-Chip, held in Tampere, Finland papers in these areas and holds one patent. Member of IEEE from year
in October 2014. The articles, hand-picked among the top 2000. He has been SP/CAS/SSC Chapter Chair of Estonia Section (2005-
2008) and is currently IEEE Estonia Section Chair.
contributions in the symposium, have been substantially ex-
tended and thereafter undergone two rounds of rigorous peer-
review according to the journal’s high standards. We would
like to thank all the reviewers involved for their invaluable
input, and to express our appreciation to the authors for their D.Sc. (Tech) Jari Nurmi works
contributions. as a P rofe ssor at Tampe re
U n i ve r s i t y o f Te c h n ol og y,
We sincerely hope that you enjoy this special issue and can Finland since 1999, in the
find useful takeaways for your own future research. Faculty of Computing and
Peeter Ellervee, Jari Nurmi March 24, 2017. Electrical Engineering. He is
working on embedded computing
systems, System-on-Chip, wire-
less localization, positioning re-
ceiver prototyping, and software-
Prof. Peeter Ellervee received defined radio. He held various re-
his Diploma Engineer degree in search, education and manage-
computer engineering from the ment positions at TUT since
Tallinn University of Technology 1987 (e.g. Acting Associate
(TTU, Estonia) in 1984, and his Professor 1991-1994) and was
Ph.D. degree in electronic sys- the Vice President of the SME VLSI Solution Oy 1995-1998. Since
tems design from Royal Institute 2013 he is also a partner and co-founder of Ekin Labs Oy, a research
of Technology (KTH, Stockholm, spin-off company, now headquartered in Silicon Valley as Radiomaze,
Sweden), in 2000. He has been Inc. He has supervised 19 PhD and over 130 MSc theses at TUT, and
working as an engineer and re- been the opponent or reviewer of 33 PhD theses for other universities
searcher at TUT (1984-1992), a worldwide. He is a senior member of IEEE, and member of the technical
guest researcher and Ph.D. stu- committee on VLSI Systems and Applications at IEEE CAS. In 2004, he
dent at KTH (1993-2000). Since was one of the recipients of Nokia Educational Award, and the recipient
spring 2000 he works at TTU - of Tampere Congress Award in 2005. In 2011 he received IIDA
researcher and Associate Innovation Award, and in 2013 the Scientific Congress Award and
Professor until fall 2004. Today he is a full Professor in digital systems HiPEAC Technology Transfer Award. He is a steering committee mem-
design at Department of Computer Systems. His has taught or is teaching ber of four international conferences (chairman in two). He has edited 5
courses about Digital Systems, Computer Hardware, Hardware Springer books, and has published over 350 international conference and
Description Languages and Modeling, and VLSI Synthesis and CAD. journal articles and book chapters.