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Hosur Road, Bommanahalli, Bengaluru-560 068: The Oxford College of Engineering

The document is an internal test from the Department of Mechatronics Engineering at The Oxford College of Engineering. It covers ARM based system design and contains 10 multiple choice questions testing concepts related to ARM processor exceptions, interrupt handling schemes, and assigning interrupts. The test is worth a total of 30 marks and students are instructed to answer any 5 questions. It lists the course outcomes which include gaining knowledge of ARM design philosophy, instruction sets, assembly code, memory hierarchy, and understanding exception and interrupt handling schemes.

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1232023
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87 views2 pages

Hosur Road, Bommanahalli, Bengaluru-560 068: The Oxford College of Engineering

The document is an internal test from the Department of Mechatronics Engineering at The Oxford College of Engineering. It covers ARM based system design and contains 10 multiple choice questions testing concepts related to ARM processor exceptions, interrupt handling schemes, and assigning interrupts. The test is worth a total of 30 marks and students are instructed to answer any 5 questions. It lists the course outcomes which include gaining knowledge of ARM design philosophy, instruction sets, assembly code, memory hierarchy, and understanding exception and interrupt handling schemes.

Uploaded by

1232023
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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DEPARTMENT OF MECHATRONICS ENGINEERING

THE OXFORD COLLEGE OF ENGINEERING


Hosur Road, Bommanahalli, Bengaluru-560 068
Website:www.theoxford.edu Email : [email protected]
(Approved by AICTE, New Delhi, Accredited by NBA, New Delhi & Affiliated to VTU, Belgaum)
Academic Year: FEB2020 – JUNE2020
INTERNAL TEST – III
SUB CODE: 17MT62 DATE: 21.05.2020
SUB NAME: ARM BASED SYSTEM DESIGN MAX MARK: 30M
SEM: VI DURATION: 1Hr 30Mins
Answer any 5 questions5x6 =30 marks
Q. Question Mark COs,POs
No. s
PART-1
Q1. With neat diagram explain Basic Interrupt Stack Design and Implementation. 6M CO5,PO1
OR
Q2. With a neat diagram explain Prioritized Simple Interrupt Handler. 6M CO5,PO2
PART-2
Q3. With a neat diagram explain Reentrant Interrupt Handler. 6M CO5,PO1
OR
Q4.
Explain Exception Priorities. 6M CO5,PO2
PART-3
Q5 Explain IRQ and FIQ Exceptions. 6M CO5,PO2
OR
Q6. Enabling and Disabling FIQ and IRQ Exceptions. 6M CO5,PO2

PART-4
Q7. Explain nested interrupt handling scheme. 6M CO5,PO2
OR
Q8. 6M CO5,PO2
Explain interrupt latency.
PART-5
Q9. Explain non nested interrupt handling scheme. 6M CO5,PO1
OR

Q10. Explain the following. 6M CO5,PO2


i)assigning interrupts
ii)ARM processor exceptions and modes.

Course Outcomes

Students will be able to


1. Gain the knowledge of RISC and ARM design philosophy and embedded system software
and hardware and ARM processor fundamentals
2.
Know the different register usage in processor core
3. Know the various instruction set of ARM and THUMB
4.
Have the knowledge about ARM assembly code and optimization of assembly code
5.
Understand the concept of memory hierarchy and the cache memory
6.
Understand the concept of exception and interrupt handling schemes

Faculty Signature PEC Signature HOD Signature

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