TMS320LF2407 Introduction
TMS320LF2407 Introduction
The C2xx has three 32-bit shifters that allow for scaling, bit
extraction, extended arithmetic, and overflow-prevention
operations.
For example,
“ADD 300h, 5”, the input shifter is responsible for first
shifting the data in memory address “300h” to the left by five
places before it is added to the contents of the accumulator.
2. Output data-scaling shifter(output shifter)
This shifter left-shifts data from the accumulator by 0 to 7 bits
before the output is stored to data memory.
For example,
“SACL 300h, 4”, the output shifter is responsible for first
shifting the contents of the accumulator to the left by four
places before it is stored to the memory address “300h”.
0 0 0 4x Fin
0 0 1 2x Fin
0 1 0 1.33x Fin
0 1 1 1x Fin
1 0 0 0.8x Fin
1 0 1 0.66x Fin
1 1 0 0.57x Fin
1 1 1 0.5x Fin
After RESET, this bit gives the user the ability to disable the
WD function through software (by setting the WDDIS bit = 1
in the WDCR). This bit is a clear-only bit and defaults to a 1
after reset.
Note: This bit is cleared by writing a 1 to it.
This bit reflects the state of the MP/MC pin at time of reset.
After reset, this bit can be changed in software to allow
dynamic mapping of memory on and off chip.
0 Set to Microcontroller mode — Program Address range
0000 — 7FFF is mapped internally (i.e., Flash)
1 Set to Microprocessor mode — Program Address range
0000 — 7FFF is mapped externally (i.e., customer
provides external memory device).