IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 321

Design of sequential circuit using reversible logic

Prashant R. Yelekar Prof. Sujata S. Chiwande

Department of Electronics & Telecommunications, Department of Electronics & Telecommunications,
Yeshwantrao Chavan College of Engineering, Yeshwantrao Chavan College of Engineering,
Nagpur, India Nagpur, India
[email protected] Sujata [email protected]
_

Abstract- The reversible logic design in today's era is running the system both forward and backward. This
attracting more interest due to its low power consumption. means that reversible computations can generate inputs
Reversible logic has g row ing importantance in low­ from outputs and can stop and go back to any point in the
power circuit design and high processing com puting. This
computation history.
paper provides synthesizing reversible counter which is the new
approach in designing four bit reversible asynchronous II. THE CONCEPT
sequential circuit. This paper also proposed a reversible D flip­
flop and Tflip-f1op. The important reversible gates used for Reversibility in computing implies that no
reversible logic synthesis a r e Fe y n m a n gate, Fr e d k i n g a t e , information about the computational states can ever be lost,
TSG gate and sayem gate etc. This p a p e r presents a basic so we can recover any earlier stage by computing
reversible gate to build more complicated circuits. The backwards or lDl-computing the results. This is termed as
transistorized implementation of reversible gate presented in this
logical reversibility. The benefits of logical reversibility can
paper are completely reversible in nature i.e. it can perform both
be gained only after employing physical reversibility.
fonvard and backward computation.
Physical reversibility is a process that dissipates no energy
to heat. Absolutely perfect physical reversibility is
Keywords- Low-power VLSJ, Low-power CMOS design, reversible practically unachievable. Computing systems give off heat
logic, reversible counters. when voltage levels change from positive to negative: bits
from zero to one. Most of the energy needed to make that
I. INTRODUCTION
change i s g i v e n o f f i n t h e f o r m o f h e a t . Rather t h a n
Energy loss is an important consideration in digital circuit changing voltages to new levels, reversible circuit elements
design, also known as circuit synthesis. Part of the problem of will gradually move charge from one node to the next. This
energy dissipation is related to technological non- ideality of way, one can only expect to lose a minute amount of
switches and materials. Higher levels of integration and the energy on each transition. Reversible computing strongly
use of new fabrication processes have dramatically reduced affects digital logic designs. Reversible logic elements are
the heat loss over the last decades. Reversible logic has needed to recover the state of inputs from the outputs. It
received great attention in the recent years due to their will impact instruction sets and high-level programming
ability to reduce the power dissipation which is the main languages as well. Eventually, these will also have to be
requirement in low power VLSI design. It has wide reversible to provide optimal efficiency.
applications in low power CMOS and Optical information
processing, quantum computation and nanotechnology. III. NEED OF REVERSffiLE COMPUTING
Irreversible hardware computation results in energy Reversible computing provide Reliable and low
dissipation due to information l o s s . According to Landauer power design, high performance circuits synchronous with
research, the amount of energy d i s s i p a t e d for e v e r y speed and processing power. Reversible circuits that
irrepressible bit Operation is at least KTln2 joules, where
conserve information, by uncomputing bits instead of
K=1.3S06505*1023 m2kg2KlUoule/Kelvin-l) is the throwing them away, will soon offer the only physically
Boltzmann's constant and T is the temperature at which possible way to keep improving performance. It again
operation is performed [1]. In 1973, Bennett showed that Improve computational efficiency this can be done by
KTln2 energy would not dissipate from a system as long building circuits which reduce energy from state will save
as the system allows the reproduction 0 f t h e i n p u t s energy. Reversible computing will also lead to improvement
from 0 b s e r v e d 0 u t p u t s [ 2]. Energy dissipation can be in energy efficiency. It Increase portability of device to
reduced or even eliminated if computation becomes reduce element size to atomic size. It has incurred more
Information-lossless Reversible logic supports the process of hardware cost, but power cost and performance are dominant

ISBN: 978-S1-909042-2-3 ©2012 IEEE

 IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 322

than hardware cost. Hence need of reversible computing

cannot be ignored in computing era,
Some factor regarding reversible logic are given below

The number of garbage outputs (GO): This refers to

the number of unused outputs p-esent in a
reversible logic circuit. One cannot avoid the
garbage outputs as these are very essential to
achieve reversibility.
• Quantum cost (QC): This refers to the cost of the
circuit in terms of the cost of a primitive gate. It
is calculated knowing the number of primitive
reversible logic gates (1 * 1 or 2*2) required to Figure 2: Reversible Transistor Implementation of the Feynman gate

realize the circuit. of reversible gates used in

circuit. As shown in design in Fig.2, only four transistors are
• The number of constant inputs (CI): This refers to needed to design the fully reversible Feynman gate.
the number of inputs that are to be maintained
constant at either 0 or 1 in order to synthesize B. FREDKlN GATE
the given logical function
Figure 3 shows a 3*3 Fredkin gate. The input vector is
I (A, B, C) and the output vector is 0 (P, Q, R). The output is
IV. REVERSIBLE LOGIC GATES
defined by P=A, Q=A'B EB AC and R=A'C EB AB. Quantum
A reversible logic gate has equal number of input and cost of a Fredkin gate is 5
output terminals and there is one to one mapping between
them. again we can say, gate is reversible if we can determine
input vector from output vector and vice-versa.revrsible gate A - r- P=A
should practically loose very little amount of energy. Fan-out F REDKIN
is not allowed in reversible circuits however fan-out can be B -
GATE
achieved using additional gate. In this paper we have discuss
c - r R=A'C AlB
basic reversible gate like Feynman gate, fredkin gate, TSG
gate and Sayem gate Which we have used in implementing
reversible sequential circuits.
Figure 3: Fredkin gate
A. FEYNMAN GATE
i) TRANSISTOR iMPLEMENTATION
Feynman gate is a 2*2 one through reversible gate
Figure 4 shows the transistor implementation of the
as shown in figure l. The input vector is I(A, B) and the Fredkin Gate that need only four transistors. In the
output vector is O(P, Q). The outputs are defined by P=A, implementation, the output P is directly taken from input A as
Q=A B. Quantum cost of a Feynman gate is l. Feynman output P is same as input A. The proposed transistor
Gate (FG) can be used as a copying gate. Since a fan-out implementation is suitable both for forward as well as
is not allowed in reversible logic, this gate is useful for backward computation, i.e., completely reversible in nature.
duplication of the required outputs. The forward and backward computations for Fredkin gate are
explained below.

A P=A
Feynman
gate
B Q=AEi7B
o

Figure I: Feynman gate c D-.-t--+----!;

i) TRANSiSTOR iMPLEMENTATiON
Figure 2 shows the transistor implementation of the
Feynman gate. The transistor implementation is fully
reversible, that is, the given circuit can also work for forward
as well as reverse operation.

Figure 4: Transistor Implementation of Fredkin Gate

ISBN: 978-81-909042-2-3 ©2012 IEEE

 IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 323

C. TSG GATE D. SAYEM GATE

Fig 5 shows a 4*4 TSG gate. The input vector is I (A,

Sayem gate (SG) is a 1 trough 4x4 reversible
B, C, D) and the output vector is 0 (P, Q, R, S). The output is
gate. The input and output vector of this gate are, Iv = (A,
defined by P = A, Q = A'C'EBB', R = (A'C'EBB')EB D and S =
B, C, D) and Ov = (A, A'B EB AC, A'B EB ACEB D, AB EB
(A'C'EBB').DEB (ABEBC) The proposed TSG gate is capable of
A'C EB D). The block diagram of this gate is shown in Fig
implementing all Boolean functions and can also work singly
8. The sayem gate can be used to build reversible T flip­
as a reversible Full adder as shown in figure 6
flop along with Feynman gate.

A P A

A A
B-
-SG Gle - Q=A'C'(I)B'
B A'BffiAC
C R (A'C'(I) B') $D SG
A'B ffi AC ffi D
C
0- --- 5 (A'C'@ B').D$(AS$C )
D AB ffi A'Cffi D

Figure 5: TSG gate

Figure 8: Sayem gate
A- P=A

B
TSG Q= AEDB I) TRANSISTOR IMPLEMENTATION
Gate
Transistorized implementation of sayem gate (SG) is
0- R = AED BED c. .. = sum
shown in figure. The sayem gate is extension of Feynman
S -C A ED B ) c,,,EJ)o.:a - Cout gate. The implementation of sayem gate requires four
transistors with two buffers and two Feynman (FG) gate as
Figure 6: TSG Gate Working As Reversible Full Adder
shown in figure. The buffer is introduced so as maintain
proper voltage level. The given implementation is completely
1) TRANSISTOR IMPLEMENTATION reversible i.e. it works for both forward and backward
The transistorized implementation of TSG gate is as computation.
shown in figure

EIj------�--�

....
r u'
U�
. .
Figure 9: Transistor Implementation of Sayem Gate

E. LATCHES

Here we can use D-Latch or T-Latch depending upon

choice that can be used in implementing reversible sequential
circuit (counter)

I) D-LATCH
The D flip-flop is a circuit that needs only a single
input and clock pulses. The action of the D flip-flop is
straightforward. When the clock pulse transitions from low to
high, the value of D is transferred to Q. The characteristic
equation of D-Latch is Q+ =DE+E'Q. Realization can be done
using single SG gat by giving E, Q, D and 0 respectively in
Figure 7: Transistor Implementation of TSG Gate 1st, 2nd, 3rd and 4th input of SG. Fig lO(a) shows the design

ISBN: 978-81-909042-2-3 ©2012 IEEE

 IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 324

of D-Latch with only Q output and Fig 10(b) shows the design F FOUR BfT ASYNCHRONOUS UP/DOWN COUNTER
of reversible D-Latch with both the output present Q and next The implementation of reversible asynchronous Up/Down
Q+ .One FG is needed to copy and produce the complement of Counter is shown in Fig. 13 [6]. The Up/Down operation of
Q from SG for the design of Fig lOeb) this reversible circuits is controlled by the control input
UP/DOWN. For UP operation, the control input should be 1
E g,
and for down operation, the control input should be O.
Q
SG
D -
Q Ql QI
0_ - g2

c,w
Fuh.
imrilli

Fig IO(a): Proposed design of D-Latch with only output Q JI1i)4I�

Q
E----t

SG Cowluilf
D
IJ,�r! ....__
... -+_--1___+-_...1.__
... -+__-"

o UI :OOUX ---.....I-----...I..--I
Figure 13: Four-bit Reversible Asynchronous Up/Down­
Counter

Fig IO(b): Proposed design of D-Latch with output Q and Q+

V. SIMULATION ANALYSIS

2) T-Flip Flop Simulation is based on "TANNER TOOL V13".model file

As the name suggests, this flip-flop circuit used to used is "0.35J.!"technology file. Graph presented below are
toggle the output when input is high (1) and retains the output input and output signal at respective input and output terminal
when input is low (0), thus it does two operation, it either at each gate.
holds the last state or toggles the output. Essentially, it has a
logical symmetry with Controlled NOT kind operation. f) FEYNMAN GATE

: -r�-�T--:-:--- ---- - +--------- -1--- :� -- + i ip

-- - --- ,-----
- i
----- -- ---- -----

� -r-----r------- --------r------ - ---- --------- ------ -------

--r -------l
T-- ----r- - --- -------r---- - -------T------
r
--------T------,------T------T
� .. T--------r-------- - ---------r--------- --------T------- --------r-----T-------r-----T

t :� __r:__;___:::____:1_I-_ _=::___ �__·� _ _________ __ ________J=r=I

_ _ _ _ _:· ]___ �_:_____:: __L__.::_ ___L ______ _ _____ ________�J
__
u 1
___ _______ _ _ _ __ _ ___ ____ _ _ _ _
I
L
.L
L
L
L
·
1.. L
,
.1 1

....
- "-
:: :; ::::;: : : : : ------------ ---------
I 1: :=: r= :=
: ---- 1 ----- ::::::=:r:=�p;;.
.
. )
-" "--------- "-----------
1 -----------1---------- -----------1---------- -----------l----------l
Table I: Truth table of T flip-flop .. -
r ----- ---- , ------------ --- -------- 1 ""----------- ---------l----- -------r----1-

The reversible realization of T Flip-flop has two SG gates i ::r:-�=:_l-=-:::- ��-:;

.. T-----------r---------
.. "[-----r----
-----r----- ----l-----�---r::=-i
-------T--------- ---- ---- r------- ------T-----T
---- ------ -----r---- ---- -"[-----T
_
and one Feynman Gate is shown in fig 11 [6]. T
:: T-- --r---- -----T---=:-T::=-:::- ---T---,:
·
....

"c'
:: ;---�-�----
- :-
--
; ----t----- 1 1 -----:�-----i-F-
l
------ '----- --- - ------
1-- --- -r ,,---- ------
r.:;---
"1---, --;:-l----r:---:l..
" -r--- 1 -. -.- r----- -1
1 1
•• --·----- ---·-------- -

- T- --- T
� " r--- ------r----------r-----·--r- - ------- r---- - r------T - -
u --r--------T------------r---------r------------ --------T-- -- ---r-------r-

" r--- ----- --- -- ----- --r-

-------------T------1"
;
� T T -- --- r- r--"1 -- "["-- -T

r
.. -r-----r----T----T---- -----,-- -- r - ---r---- ------
,. --[---------1--------"[--------T------------ --r ---------- ----------""["-------1"
- T-- - --T

: :::: :::::::::l:::::::::::i::::::::::::::::::::: :::F::::fT ::::�=�:

-------- --------- -----

:::=:F:=::l
Fig II: Reversible Positive Edge Triggered T Flip-flop ·
..

-n=
Q
avgyower = 1.196Ie-005
Figure 14: simulation of Feynman gate (forward direction)
CP
Q'

Figure 12: reversible T flip flop

ISBN: 978-81-909042-2-3 ©2012 IEEE

 IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 325

--

: T:::-r: ::=-:--·
·r-·-....·-·- ----·--· --·-+-·-···-·-t··-·--·-··t··-·-- - �:-:::::::=:==r:--:=�·:::�-=r-
I
" ··,-·-....·-·-1--·--.. ·- -.----.'1"--...--1'--.-.--'1"--.--.-. -·--·--·-I--- -·--·1-·---..·-r----·-·'1'
� -.-.---.'1""-...-.- 1 '--.-.--'1"..-.--.... - " '-'--' -r '--'-'--1 "'--'-"'-j "---'-'-1

" "1'-'-"'-"'1""''''''''-' "'''''''''-T-'''-'''- J'-'''-'''''' T-''''''''-' ,,···-""·-r·"-"-"· -""·".. "..·"·"..

" ··]-· .. ···--1-". ·-·-- ,,·-·-··- "·.. ·..-·- -"-·-,···--·-·.. -"'-"-'T"---'I--'T-'--"'1' I
T-'-"'--T---'--' ---"'-' -···-- ·-----l"·"-· "·---r
T T
.
..]--... ..-"1"-.--.--.
T
..[-...... ..-.-1'.".--...- ".-.-"... "1"".".-"..'1'-".-.--'1"..-.-...... -···,,·--···r·--·-·--·, ..·,,-·-..T
·"r....·"·-..'1'
' · 1: :
"'-'--'-
T r T

"1= . ,,+. · · · ·
�]��:�+::=:]:=:: :=::+�:"�T:::::: =:: ::: l
: :V····················· ····· ····· • • • • • • • • • • • • • • • • •I �� � : : :
.
:
: :�
. -
.
� ..
.... " ,. ". !
,

·'1'"·"........"1..•..""...."1"·"·"......·,........,,.. .."·"......1 ..·1......".... ·"1·....."." .....·......•..r ......"..·1·

',-'Ill
1
...·1·· ..·..--1· --...... 1.... ........ . ... '''1 ·,-.... •..-.. 1 .. ·-
H

" ··r-·-..···-·- ..· ..--.. ·..·t-·"·"--..r..-"·-"· '--'-"'-'1 ····1·-·····--·1""-·-·--· ..·..-·,,""'1"..,,·-·-"·1·

1 • •• • •• • • • •• • 1 :l:::::!.�
� "1" - -. '1'
I
"

" I '" ::: ::: : : : :

.. ,.-.-. ""-I"-"'-'--r---'-r'-"'--' --·-..·-· T ··-·--·-· ·-···-·--· -·-"--· '--'-" -'-'-"'1',
. -'1"-- -r"-'- 1 .. " ''1'" '' 1 ..."

'1'-'- ..·..· -·--· .. -·r---· ..· ...- - -'-"'-'1" "-'-"' T -'-'-"' T

T I
T ..···· . . -j-·-·--"-..T
T
"1'-'- ···..·-r· r·- .. -·- ·--·-···-'1"··"-······r-··········· ··-·"·-··· ·..-..·..·-r..·..·-·-..'1'
T" '-'-'-r"'--"T , ,

T
··I·-· I�i.:
ldi'lj
"r'" . '1 -T r T" T I T T
: L : C: :r:
• • • • • • 1 • • • • • • • • • • • • • • • • ·i ::l:
" . r·· "I" T T 1:
1'"
r" · .__._ : :. : _ __
:' ::�:::: ::::::::::::::::i:::

�: q::::
:: ::::::::::::�::::::::
� "j--'-'''--'-I''-'--'''-' ----.-"[-...-".-.-.
+ __ .. __
_____ : ::=:::
.
:::::: _____ ·
..-·-· .-..t..·-·-..·-· -..·---·-1------·
, ___ __ ..:::_..:::==:::r;.l
"'--"'- [--'-'-"' 1"

.t-·-....·-·-,..-·--·--· -.---.--,-.-...-.-. ..--..·-..t ..·--..·-· -...-. --.-1,..-----.

.
" 'I' "I " .- .. I , ., ·_-t
a . -'--"'-,-"'--"' 1 "

\� ·i�:�::�:�i::���=·I::::=:.:1:::::: :�:�¥�:::�::¥���: -::�f�:�:l

:: IT ..
.
"
1' . r " 1 I ,
',�

.
� ..

avgyower = 2.066Se-OOS
Figure IS: simulation of Feynman gate (backward direction) avgyower = -6.S332e-007
Figure 18: simulation of Fredkin gate (backward direction)

2) FREDKlN GATE
(;Hli

3) T FLIP-FLOP

·
-m

��:: : : : : : : : ::f : : r:
.. ..

1'"----,.1
l.i 7'·
l<7"

l<:

ll il [ i � r
l
;l.:.;.. ......................... .........

;:1::. . . . . . . ..... . .......

l�1.·....
ti+.
« .:...�=�='7."="""=""'";== i,---;;--..J..=""""==#.==;;-

I 1
) � t I: ;$ ) !i 0: ,

1!'l1�
· ···..
.
... j!,
== m m
•• m X. m.. mmm

�l_r r�
···

..
) � 1 Ii ::" .Ii � l;�
Ie';
........... .......................
____

..................................
::�
.. ........... .. ... ................................ � ...

............ ............................
.
lll]!(
{;.:. . ................................., ....• ....••....• ..........T....
"""'=""'i;,==;"'m"".......="'=
• ....••
(;Hll {�:,,,. ;=='i=='7."'= ..... ........�
.. ....=�=�=""";= . =.... .... == '=

li�._..

!l !l !l !l !"
lI�._..
J�';._..
�<.:..-..
:.i+_..
l� :
���.-..

jli=iili:j=r
ll�._..
,�.;.-..
((..:.. - ..

) I t 1/ ;$ J Ii ': &

1!l1�
avgyower = 2.9826e-004

avgyower = 1.2270e-006 Figure 17: simulation of T llip-llop

Figure 16: simulation of Fredkin gate (forward direction)

ISBN: 978-81-909042-2-3 ©2012 IEEE

 IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 326

4) COUNTER OUTPUT asynchronous counter design directly from reversible

gates. This work forms an important move in building large
and complex reversible sequential circuits.
.... .... .... , , ...

.. . ...• .. . REFERENCES

[1 ] Landauer, R., "Irreversibility and heat generation in the computing

process", IBM 1. Research and Development, 5(3): pp. 183-191, 1961.

[2] Bennett, C.H., "Logical reversibility of Computation", IBM J.Research

and Development, 17: pp. 525-532, 1973.

[3] Thapliyal H, Ranganathan N.," Design of Reversible Latches Optimized

for Quantum Cost, Delay and Garbage Outputs" Centre for VLSI and
Embedded System Technologies International Institute of Information
Technology, Hyderabad, 500019, India

[4) Mozammel H A Khan and Marek Perkowski" Synthesis of Reversible

Synchronous Counters" 2011 41st IEEE International Symposium on
Multiple-Valued Logic

[5] H. Thapliyal and A.P. Vinod, "Design of reversible sequential elements

with feasibility of transistor implementation," International Symposium on
Circuits and Systems (ISCAS 2007), 2007, pp. 625-628.
.. ....-:::;:-,;;;;-,�"'""':::;-,::::-:=-:::::-;;;
';;
� .--et.:;
;; ;;-, �=-:=-:=-:;;;-;;:;-:=-:
::::-::::;-;:::;-;::
_::-
: .l � fl:f:1B f1:O:HnflH Aqn B nnPj ELflfl •••••• [6) V.Rajmohan, V.Ranganathan,"Design of counter using reversible logic"
'·I::lJ IJ Ll:l1tIIJLI: t1 I[UtJIJIJI.1utJtIIJt11 978-1-4244-8679-3/11/$26.00 ©2011 IEEE

[7] Siva Kumar Sastry, Hari Shyam Shroff ,Sk.Noor Mahammad, V.

avgyower = 1.9988e-003 Kamakoti" Efficient Building Blocks for Reversible Sequential Circuit
Design" 1-4244-0173-9106/$20.00©2006IEEE
Figure 18: simulation analysis of counter output

Likewise we will get simulation of other reversible logic [8] M.-L. Chuang and c.- Y. Wang, "Synthesis of reversible sequential
elements," ACM journal of Engineering Technologies in Computing Systems
gates. (JETC), vol. 3, no. 4, 2008.

[9] S.K.S. Hari, S. Shroff, S.N. Mohammad, and V. Kamakoti, "Efficient

VI. APPLICATlON building blocks for reversible sequential circuit design," IEEE International
Midwest Symposium on Circuits and Systems (MWSCAS), 2006.
Reversible computing may have applications in computer
security and transaction processing, but the main long-term [10]Abu Sadat Md. Sayem, Masashi Veda "Optimization of reversible
benefit will be felt very well in those areas which require high sequential circuits" journal of computing, volume 2, issue 6, june 2010, issn
energy efficiency, speed and performance .it include the area 2151-9617

like [11] Thapliyal H, M. B.Sshrinivas "Novel Reversible Multiplier Architecture

1. Low power CMOS. Using Reversible TSG Gate" Computer Systems and Applications, 2006.
2. Quantum computer. IEEE International Conference on.
3. Nanotechnology
[12] Rangaraju H G, Venugopal V, Muralidhara K N, Raja K B "Low Power
4. Optical computing Reversible Parallel Binary AdderlSubtractor"lnternational journal of VLSI
5. Design of low power arithmetic and data path for digital design & Communication Systems (VLSICS) YoU, No.3, September 2010
signal processing (DSP).
6. Field Programmable Gate Arrays (FPGAs) in CMOS [13] h.r.bhagyalakshmi, m.k.venkatesha" an improved design of multiplier
using reversible logic gates" International Journal of Engineering Science and
technology for extremely low power, high testability and Technology Vol. 2(8), 20I0, 3838-3845
self-repair.
[14] Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, and John P. Hayes"
VII. CONCLUSION Reversible Logic Circuit Synthesis" ICCAD 2002 Nov 1014, 2002, San Jose,
California, USA Copyright 2002 ACM XXXXXXXXXlXXlXX ... $5.00.
This paper proposes designs of basic reversible sequential
elements such as latches, flip-flops and four bit reversible
asynchronous up/down counter. We have shown average
power dissipation in each gate in simulation part which
indicates negligible energy dissipation which in turn improves
performance of circuit. Basic reversible gate presented in this
paper can be used in regular circuits realizing Boolean
functions. The proposed asynchronous counter designs have
the applications in building reversible ALU, reversible
processor etc. In this paper, we present a method of

ISBN: 978-81-909042-2-3 ©2012 IEEE