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Digital Circuits: 2013-14 Monsoon Experiment 2

This document describes an experiment involving the implementation of simple logic circuits using gates. The experiment involves building circuits to verify De Morgan's laws, a binary to decimal decoder, a half adder, and a full adder. The circuits are built using CMOS gates including NOR, NAND, XOR, and AND gates. The inputs and outputs of the circuits are tested using switches and LED displays.

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Frank Martin
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35 views3 pages

Digital Circuits: 2013-14 Monsoon Experiment 2

This document describes an experiment involving the implementation of simple logic circuits using gates. The experiment involves building circuits to verify De Morgan's laws, a binary to decimal decoder, a half adder, and a full adder. The circuits are built using CMOS gates including NOR, NAND, XOR, and AND gates. The inputs and outputs of the circuits are tested using switches and LED displays.

Uploaded by

Frank Martin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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2013-14 Digital Circuits Monsoon

Experiment 2

Simple Logic Circuits using Gates

We will use various kinds of CMOS gates for the implementation of the
required logic. The pin connections of all the ICs are the same as given in Fig.
1(a) of the write-up for Experiment 1. Remember that for all future
experiments, the connection of the V CC/VDD and Gnd pins of each IC chip used
must be connected to the +5V and Gnd buses on the breadboard, using RED
and BLACK wires respectively. These buses are always connected by RED
and BLACK jumper wires to the d-c power supply.

Part A. De Morgan’s Laws

De Morgan’s laws state that (A + B)’ = A’  B’ and (A  B)’ = A’ + B’. Verify


these laws by proceeding step by step as follows:

1. Set up a circuit consisting of two NOR gates (CD4001) and one AND gate
(CD4081) to perform the function Y = A’  B’, using a NOR gate with its two
inputs connected together to perform the NOT function. Draw the circuit
diagram and mark the IC pin numbers on the diagram, by NOR-1, NOR-
2,....AND-1, AND-2...and so on.
2. Connect two Input Switches to the two inputs A and B, and the output Y to
an LED display by jumper wires. Apply the four possible combinations of
values (0/1) to the inputs A and B by means of the Input Switches and
tabulate the corresponding values of the output Y as observed on the LED
Display. Verify that the truth table so obtained is the same as that of a NOR
gate.
3. Repeat steps 1 and 2 using two NOR gates to perform the OR function
instead of an AND gate to verify that the truth table of the function Y = A’ +
B’ is the same as that of a NAND gate.

Part B. Binary to Decimal Decoder

Decimal numbers 0, 1, 2, 3 can be represented by the 2-bit binary codes 00,


01, 10 and 11 respectively. One can generate four outputs L 0, L1, L2, L3
indicating the four decimal values of the number from two inputs representing
the binary code (B1B0) by the following logic:
L0 = B1’B0’, L1 = B1’B0, L2 = B1B0’, L3 =
B1B0.
1. Set up the circuit of such a 2-bit binary to decimal Decoder using four 2-
input NOR gates (CD4001), using 2-input XOR gates (CD4070) to perform
the NOT function. Connect the two inputs B 1 and B0 from two Input Switches
and the four outputs L0, L1, L2, L3 to four LED Displays.
2. Tabulate the observed values of L 0, L1, L2, L3 for all possible combinations of
values of B1 and B0 and verify the logic of the Decoder.

Part C. Binary Half Adder

A binary Half Adder adds two bits A and B to generate SUM and CARRY bits
as output according to the following Boolean expressions for the outputs:
SUM = A’  B + A  B’ = A  B and CARRY = A  B.
1. Set up the circuit of a Half Adder using an XOR gate (CD4070) and an AND
gate (CD4081) and. Apply the inputs A and B from two Input Switches and
observe the outputs SUM and CARRY on two LED Displays for all
combinations of the inputs.
2. Tabulate these values and verify the operation of the Half Adder. Do not
dismantle this circuit as it will be used as part of the circuit to be used in the
next part.

Part D. Binary Full Adder

A binary Full Adder adds two bits A and B along with a carry-in bit C to
generate SUM and CARRY bits as output. It can be implemented with two Half
Adders and one AND gate. In this implementation, one Half Adder is used to
add the bits A and B to generate intermediate sum and carry bits S1 and C1.
Another Half Adder is then used to generate the final SUM by adding the carry-
in bit C to the S1 bit generated by the first Half Adder:
Note that the logic for the SUM output of a Full Adder is thus
SUM = S1  C = A  B  C.
The carry-out bits C1 (= A  B) and C2 (= S1  C) generated by the two Half
Adders are combined together to generate the final CARRY output given by
the expression:
CARRY = C1 + C2 = A  B + S1  C.
Verify theoretically that the logic for the CARRY output of a Full Adder can also
be written as
CARRY = A  B + A  C + B  C.
1. Set up a second Half Adder using another XOR and another AND gate out
of the same ICs used in step C.1, and connect the carry-in bit C, applied
from a third Input Switch, and the S1 output generated by the first Half
Adder as the inputs of the second Half Adder to generate the final SUM
output and the carry-out bit C2.
2. Verify theoretically that the logic for CARRY can also be implemented with
an XOR gate (i.e. CARRY = C1  C2), thereby eliminating the need for a
separate OR chip and making the complete realisation of the Full Adder
possible using two IC chips. Generate the final CARRY output from the
intermediate carry outputs C1 and C2, using one of the unused gates in the
XOR chip. Connect the S1, C1, C2, SUM and CARRY outputs to five LED
Displays.
3. Apply all possible combinations of values (0/1) of the inputs A, B and C from
the three Input Switches and tabulate the corresponding values of the S1,
C1, C2, SUM and CARRY outputs. Verify that the resulting Truth Table is
indeed that of a Full Adder.

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