Scribd
Upload
70 views

Gate Level Modeling: Prof. A. K. Swain Asst. Prof., ECE Dept., NIT Rourkela EC6203: Reconfigurable System Design

Gate level modeling in Verilog HDL uses primitive gates to describe hardware. The document describes the available built-in primitive gates in Verilog including: multiple-input gates (and, nand, etc.), multiple-output gates, tristate gates, pull gates, MOS switches, and bidirectional switches. It provides the syntax for declaring instances of these gates and specifies how delays can be included. Array instances of gates can also be declared using a range specification.

Uploaded by

Rashmi Singh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
70 views

Gate Level Modeling: Prof. A. K. Swain Asst. Prof., ECE Dept., NIT Rourkela EC6203: Reconfigurable System Design

Gate level modeling in Verilog HDL uses primitive gates to describe hardware. The document describes the available built-in primitive gates in Verilog including: multiple-input gates (and, nand, etc.), multiple-output gates, tristate gates, pull gates, MOS switches, and bidirectional switches. It provides the syntax for declaring instances of these gates and specifies how delays can be included. Array instances of gates can also be declared using a range specification.

Uploaded by

Rashmi Singh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 18

Gate Level Modeling

Prof. A. K. Swain
Asst. Prof., ECE Dept., NIT Rourkela

EC6203: Reconfigurable System Design


Built-in Primitive Gates
• It describes the available built-in primitive gates.
• How these can be used to describe hardware.

The following built-in primitive gates are available in Verilog HDL.


i. Multiple-input gates: and, nand, or, nor, xor, xnor
ii. Multiple-output gates: buf, not
iii. Tristate gates: bufif0, bufif1, notif0, notif1
iv. Pull gates: pullup, pulldown
v. MOS switches: cmos, nmos, pmos, rcmos, rnmos, rpmos
vi. Bidirectional switches: tran, tranif0, tranif1, rtran, rtranif0, rtranif1

Gate Level Modeling EC6203 Reconfigurable System Design


Built-in Primitive Gates
Syntax:
gate _ type [ delay ] [instance_name] ( term1, term2 ,... , termN ) ;

Gate type: Gates listed earlier.


termN: Nets and registers connected to the terminals of the gate.
The instance_name is optional;

Multiple instances of the same gate type can be specified in one construct.
Syntax:
gate_type
[ instance _ name 1 ] ( term 11 , term 12 , . . . , term1N ),
[ instance _name2 ] ( term21 , term22 , . . . , term2N ),
....
[ instance_nameM ] ( termM1 , termM2 , . . . , termMN) ;

Gate Level Modeling EC6203 Reconfigurable System Design


Multiple-input Gates
• The multiple-input built-in gates are: and, nand, nor, or, xor, xnor
• These logic gates have only one output and one or more inputs.

Syntax :
multiple _ input _ gate_type
[ instance_name] (OutputA , Input1 , Input2 , . . . , InputN );
• The first terminal is the output and all others are the inputs

Example:
and A1 (Outl, Ini, In2);
and RBX (Sty, Rib, Bro, Qit, Fix) ;
xor (Bar, Bud[0], Bud[l], Bud[2]),
(Car, Cut[0], Cut[l]),
(Sar, Sut[2], Sut[l], Sut[0], Sut[3]);

Gate Level Modeling EC6203 Reconfigurable System Design


Multiple-input Gates
• Notice that a value z at an input is handled like an x.
• The output of a multiple-input gate can never be a z.

Gate Level Modeling EC6203 Reconfigurable System Design


Multiple-Output Gates
• The multiple-output gates are: buf, not
• These gates have only one input and one or more outputs.

Syntax:
multiple_output_gate_type [ instance_name ] ( Out1, 0ut2 ,… , OutN, InputA );

Example:
buf B1 (Fan[0], Fan[1], Fan[2], Fan[3], Clk);
not N1 [PhA, PhB, Ready) ;

Gate Level Modeling EC6203 Reconfigurable System Design


Tristate Gates
• The tristate gates are: Bufif0, bufif1, notif0, notif1
• These gates model three-state drivers.
• These gates have one output, one data input and one control input.
Syntax:
tristate_gate [ instance_name ] (OutputA, InputB, ControlC);
Examples:
bufif1 BF1 {Dbus, MemData, Strobe);
notif0 NT2 {Addr, Abus, Probe);

Gate Level Modeling EC6203 Reconfigurable System Design


Tristate Gates

Gate Level Modeling EC6203 Reconfigurable System Design


Pull Gates
The pull gates are: pullup, pulldown
• These gates have only one output with no inputs.
• A pullup gate places a 1 on its output.
• A pulldown gate places a 0 on its output.

Syntax:
pull_gate [ instance_name ] ( OutputA );

• The terminal list of this gate instantiation contains only one output.

Example:
pullup PUP (Pwr);

• This pullup gate has instance name PUP with output Pwr tied to 1.

Gate Level Modeling EC6203 Reconfigurable System Design


MOS Switches
The MOS switches are: cmos, pmos, nmos, rcmos, rpmos, rnmos

• These gates model unidirectional switches.


• Data flows from input to output,
• Data flow can be turned off by appropriately setting the control input(s).
• The switches have one output, one input and one control input.

Syntax:
gate_type [ instance_name ] ( OutputA , InputB , ControlC );

Examples:
pmos P1 (BigBus, SmallBus, GateControl);
rnmos RN1 (ControlBit, ReadyBit, Hold);

Gate Level Modeling EC6203 Reconfigurable System Design


MOS Switches
The cmos (complimentary MOS) and rcmos (resistive version of cmos)
switches have one data output, one data input and two control inputs.

Syntax:
(r)cmos [ instance_name ] (OutputA , InputB , NControl , PControl );

• The first terminal is the output, the second is the input,


• The third is the n-channel control input and
• The fourth terminal is the p-channel control input.
• A cmos (rcmos) switch behaves exactly like a combination of a pmos (rpmos)
and an nmos (rnmos).

Gate Level Modeling EC6203 Reconfigurable System Design


Bidirectional Switches
The bidirectional switches are: tran, rtran, tranif0, rtranif0, tranif1, rtranif1
• These switches are bidirectional, that is, data flows both ways and there is no delay when data
propagates through the switches.
• The last four switches can be turned off by setting a control signal appropriately.
• The tran and rtran switches cannot be turned off.

Syntax:
(r)tran [ instance_name ] ( SignalA , SignalB );
• The terminal list has only two terminals and data flows unconditionally both ways, that is, from
SignalA to SignalB and vice versa.

Syntax :
gate__type [ instance_name ] ( SignalA , SignalB , ControlC );
• The first two terminals are the bidirectional terminals, that is, data flows from SignalA to SignalB
and vice versa. The third terminal is the control signal.
• If ControlC is 1 for tranif0 and rtranif0, and 0 for tranif1 and rtranif1, the bidirectional data flow
is disabled.
• For the resistive switches (rtran, rtranif1 and rtranif1), the strength of the signal reduces when it
passes through the switch.

Gate Level Modeling EC6203 Reconfigurable System Design


Gate Delays
Gate delay: Signal propagation delay from any gate input to the gate output .
• The gate delay can be specified in the gate instantiation itself.
Syntax:
gate_type [ delay ] [ instance_name ] ( terminal_list );
• The delay specifies the propagation delay of the gate.
• When no gate delay is specified, the default delay is zero.

A gate delay can be comprised of up to three values :


i. rise delay , ii. fall delay, iii. turn-off delay
• A delay specification may contain zero, one, two, or all three values specified.
The transition to x delay (To_x) cannot be explicitly specified but is determined from the other
specified values.

Gate Level Modeling EC6203 Reconfigurable System Design


Gate Delays

• To_x delay is determined from the other specified values.


Example:
not N1 (Qbar, Q) ; //delay =0
nand #6 (Out, In1, In2); // Trise =Tfall =6, no turn_off, To_x=6
and #(3, 5) (Out, In1, In2, In3) ; // Trise =3, Tfall =5, no turn_off,
//To_x=min(3,5) =3
Notif1 #(2, 8, 6) (Dout, Din1, Din2); //the Trise =2,Tfall =8,Turn_off=6,
//To_x=min(2,8,6) =2

Gate Level Modeling EC6203 Reconfigurable System Design


Min:typ:max Delays
• A delay for a gate can also be specified in a min:typ:max form.
• Delays such as in continuous assignments also supports min:typ:max delay.

Syntax:
minimum : typical : maximum
• The minimum, typical and maximum values must be constant expressions.

Example:
nand #(2:3:4, 5:6:7) (Pout, Pin1, Pin2);
• The selection of which delay to use is usually made as an option during a simulation
run.
• If maximum delay simulation is performed:
a rise delay of 4 and a fall delay of 7 is used for the nand gate instance.

Gate Level Modeling EC6203 Reconfigurable System Design


Array of Instances
• When repetitive instances are required, a range specification can optionally be specified in a gate
instantiation
• A range specification can also be used in a module instantiation.
Syntax:
gate_type [ delay ] instance_name [ leftbound : rightbound ] ( list _of_ terminal_names );
• The left bound and right bound values are any two constant expressions.

Example:
wire [3:0] Out, InA, InB;
nand G [3 : 0] (Out, InA, InB);
//same as:
Nand G3 (Out[3], InA[3], InB[3]),
G2 (Out[2], InA[2], JnB[2]),
G1 (Out[1], InA[1], InB[1]),
G0 (Out[0], InA[0], InB[0]);
*Note that the instance name is not optional when specifying an array of instances.

Gate Level Modeling EC6203 Reconfigurable System Design


Example
• When repetitive instances are required, a range specification can optionally be specified in a gate
instantiation
• A range specification can also be used in a module instantiation.
Syntax:
gate_type [ delay ] instance_name [ leftbound : rightbound ] ( list _of_ terminal_names );
• The left bound and right bound values are any two constant expressions.

Example:
wire [3:0] Out, InA, InB;
nand G [3 : 0] (Out, InA, InB);
//same as:
Nand G3 (Out[3], InA[3], InB[3]),
G2 (Out[2], InA[2], JnB[2]),
G1 (Out[1], InA[1], InB[1]),
G0 (Out[0], InA[0], InB[0]);
*Note that the instance name is not optional when specifying an array of instances.

Gate Level Modeling EC6203 Reconfigurable System Design


References
Books:
A Verilog HDL Primer: by J Bhasker.
Design Through Verilog HDL: T.R. Padmanavan, B. Bala Tripura Sundari
Verilog Digital Design Synthesis: Samir Palnitkar.

website:
asic-world.com
www.xilinx.com

You might also like