TMS320F2838x Microcontrollers

Technical Reference Manual

Literature Number: SPRUII0B

May 2019 – Revised May 2020
 Contents

Preface ..................................................................................................................................... 152

1 ► C28 SYSTEM RESOURCES ............................................................................................ 153
1.1 Technical Reference Manual Overview ................................................................................ 154
2 C2000 Software Support .................................................................................................... 155
2.1 Introduction ................................................................................................................ 156
2.2 C2000Ware Structure .................................................................................................... 156
2.3 Documentation ............................................................................................................ 156
2.4 Devices ..................................................................................................................... 156
2.5 Libraries .................................................................................................................... 156
2.6 Code Composer Studio™ Integrated Development Environment (IDE) ........................................... 157
2.7 PinMUX Tool .............................................................................................................. 157
3 C28x System Control ........................................................................................................ 158
3.1 C28x System Control Introduction ...................................................................................... 159
3.2 System Control Functional Description ................................................................................ 159
3.2.1 Device Identification ............................................................................................ 159
3.2.2 Device Configuration Registers ................................................................................ 160
3.3 Resets ...................................................................................................................... 160
3.3.1 Reset Sources.................................................................................................... 160
3.3.2 External Reset (XRSn) .......................................................................................... 161
3.3.3 Simulate External Reset ........................................................................................ 161
3.3.4 Power-On Reset (POR) ......................................................................................... 161
3.3.5 Debugger Reset (SYSRS) ...................................................................................... 162
3.3.6 Simulate CPU1 Reset ........................................................................................... 162
3.3.7 Watchdog Reset (WDRS) ...................................................................................... 162
3.3.8 NMI Watchdog Reset (NMIWDRS) ............................................................................ 162
3.3.9 Secure Code Copy Reset (SCCRESET) ..................................................................... 162
3.3.10 ESC Reset Output .............................................................................................. 163
3.3.11 Test Reset (TRST) ............................................................................................. 163
3.4 Peripheral Interrupts ...................................................................................................... 163
3.4.1 Interrupt Concepts ............................................................................................... 163
3.4.2 Interrupt Architecture ............................................................................................ 163
3.4.3 Interrupt Entry Sequence ....................................................................................... 165
3.4.4 Configuring and Using Interrupts .............................................................................. 166
3.4.5 PIE Channel Mapping ........................................................................................... 167
3.4.6 System Error and CM Status Interrupts ...................................................................... 169
3.4.7 Vector Tables..................................................................................................... 171
3.5 Exceptions and Non-Maskable Interrupts ............................................................................. 176
3.5.1 Configuring and Using NMIs ................................................................................... 176
3.5.2 Emulation Considerations ...................................................................................... 176
3.5.3 NMI Sources ...................................................................................................... 177
3.5.4 Illegal Instruction Trap (ITRAP) ................................................................................ 178
3.6 Safety Features ........................................................................................................... 178
3.6.1 Write Protection on Registers .................................................................................. 178
3.6.2 Missing Clock Detection Logic ................................................................................. 178
3.6.3 CPU1 and CPU2 ePIE Vector Address Validity Check ..................................................... 181

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3.6.4 NMIWDs .......................................................................................................... 181

3.6.5 ECC and Parity Enabled RAMs, Shared RAMs Protection ................................................ 181
3.6.6 ECC Enabled Flash Memory ................................................................................... 181
3.6.7 ERRORSTS Pin.................................................................................................. 182
3.7 Clocking ................................................................................................................... 182
3.7.1 Clock Sources .................................................................................................... 184
3.7.2 Derived Clocks ................................................................................................... 186
3.7.3 Device Clock Domains .......................................................................................... 187
3.7.4 External Clock Output (XCLKOUT)............................................................................ 188
3.7.5 Clock Connectivity ............................................................................................... 188
3.7.6 PLL/AUXPLL ..................................................................................................... 190
3.8 Clock Configuration Semaphore ........................................................................................ 193
3.9 32-Bit CPU Timers 0/1/2 ................................................................................................. 194
3.10 Watchdog Timers ......................................................................................................... 195
3.10.1 Servicing the Watchdog Timer ................................................................................ 196
3.10.2 Minimum Window Check ...................................................................................... 196
3.10.3 Watchdog Reset or Watchdog Interrupt Mode .............................................................. 197
3.10.4 Watchdog Operation in Low Power Modes ................................................................. 197
3.10.5 Emulation Considerations ..................................................................................... 197
3.11 Low Power Modes ........................................................................................................ 198
3.11.1 IDLE .............................................................................................................. 198
3.11.2 STANDBY ....................................................................................................... 198
3.12 Memory Controller Module .............................................................................................. 199
3.12.1 Functional Description ......................................................................................... 200
3.13 JTAG ....................................................................................................................... 209
3.14 System Control Registers................................................................................................ 210
3.14.1 System Control Base Addresses ............................................................................. 210
3.14.2 CLK_CFG_REGS Registers .................................................................................. 211
3.14.3 CM_CONF_REGS Registers.................................................................................. 242
3.14.4 ACCESS_PROTECTION_REGS Registers................................................................. 248
3.14.5 CPU_SYS_REGS Registers .................................................................................. 269
3.14.6 CPU_ID_REGS Registers ..................................................................................... 313
3.14.7 CPU1_PERIPH_AC_REGS Registers ....................................................................... 315
3.14.8 CPUTIMER_REGS Registers ................................................................................. 389
3.14.9 DEV_CFG_REGS Registers .................................................................................. 396
3.14.10 DMA_CLA_SRC_SEL_REGS Registers ................................................................... 452
3.14.11 MEM_CFG_REGS Registers ................................................................................ 459
3.14.12 MEMORY_ERROR_REGS Registers ...................................................................... 529
3.14.13 NMI_INTRUPT_REGS Registers ........................................................................... 549
3.14.14 PIE_CTRL_REGS Registers ................................................................................ 568
3.14.15 ROM_PREFETCH_REGS Registers ....................................................................... 608
3.14.16 ROM_WAIT_STATE_REGS Registers ..................................................................... 610
3.14.17 SYNC_SOC_REGS Registers............................................................................... 612
3.14.18 SYS_STATUS_REGS Registers ............................................................................ 618
3.14.19 TEST_ERROR_REGS Registers ........................................................................... 631
3.14.20 UID_REGS Registers ......................................................................................... 635
3.14.21 WD_REGS Registers ......................................................................................... 644
3.14.22 XINT_REGS Registers ....................................................................................... 651
3.14.23 Register to Driverlib Function Mapping..................................................................... 660
4 C28x Processor ................................................................................................................ 675
4.1 Introduction ................................................................................................................ 676
4.2 Features .................................................................................................................... 676
4.3 Floating-Point Unit ....................................................................................................... 676

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4.4 Trigonometric Math Unit ................................................................................................. 676

4.5 VCRC Unit ................................................................................................................. 677
5 ROM Code and Peripheral Booting ..................................................................................... 678
5.1 Introduction ................................................................................................................ 679
5.2 Device Boot Sequence ................................................................................................... 679
5.3 Device Boot Modes ....................................................................................................... 681
5.4 Device Boot Configurations ............................................................................................. 682
5.4.1 Configuring Boot Mode Pins for CPU1........................................................................ 682
5.4.2 Configuring Boot Mode Table Options for CPU1 ............................................................ 684
5.4.3 Boot Mode Example Use Cases ............................................................................... 685
5.5 Device Boot Flow Diagrams ............................................................................................. 687
5.5.1 CPU1 Boot Flow ................................................................................................. 687
5.5.2 CPU2 Boot Flow ................................................................................................. 690
5.5.3 Connectivity Manager (CM) Boot Flow ....................................................................... 691
5.6 Device Reset and Exception Handling ................................................................................. 692
5.6.1 Reset Causes and Handling.................................................................................... 692
5.6.2 Exceptions and Interrupts Handling ........................................................................... 692
5.7 Boot ROM Description ................................................................................................... 694
5.7.1 CPU1 Boot ROM Configuration Registers.................................................................... 694
5.7.2 Booting CPU2 and CM .......................................................................................... 695
5.7.3 Entry Points ....................................................................................................... 698
5.7.4 Wait Points........................................................................................................ 699
5.7.5 Memory Maps .................................................................................................... 700
5.7.6 ROM Tables ...................................................................................................... 702
5.7.7 Boot Modes and Loaders ....................................................................................... 703
5.7.8 GPIO Assignments for CPU1 .................................................................................. 721
5.7.9 Secure ROM Function APIs .................................................................................... 724
5.7.10 Clock Initializations ............................................................................................. 727
5.7.11 Boot Status information ........................................................................................ 727
5.7.12 ROM Version .................................................................................................... 731
5.8 Application Notes for Using the Bootloaders .......................................................................... 732
5.8.1 Boot Data Stream Structure .................................................................................... 732
5.8.2 The C2000 Hex Utility ........................................................................................... 734
6 Dual Code Security Module (DCSM) .................................................................................... 736
6.1 Introduction ................................................................................................................ 737
6.2 Functional Description.................................................................................................... 737
6.2.1 CSM Passwords ................................................................................................. 738
6.2.2 Emulation Code Security Logic (ECSL)....................................................................... 740
6.2.3 CPU Secure Logic ............................................................................................... 740
6.2.4 Execute-Only Protection ........................................................................................ 740
6.2.5 Password Lock ................................................................................................... 740
6.2.6 JTAGLOCK ....................................................................................................... 741
6.2.7 Link Pointer and Zone Select .................................................................................. 741
6.2.8 C Code Example to Get Zone Select Block Addr for Zone1 ............................................... 744
6.3 Flash and OTP Erase/Program ......................................................................................... 744
6.4 Secure Copy Code ....................................................................................................... 744
6.5 SecureCRC ................................................................................................................ 745
6.6 CSM Impact on Other On-Chip Resources ........................................................................... 745
6.7 Incorporating Code Security in User Applications .................................................................... 747
6.7.1 Environments That Require Security Unlocking ............................................................. 747
6.7.2 CSM Password Match Flow .................................................................................... 748
6.7.3 C Code Example to Unsecure C28x Zone1 .................................................................. 749
6.7.4 C Code Example to Resecure C28x Zone1 .................................................................. 749

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6.7.5 Environments That Require ECSL Unlocking ................................................................ 749

6.7.6 ECSL Password Match Flow ................................................................................... 750
6.7.7 ECSL Disable Considerations for any Zone.................................................................. 751
6.7.8 Device Unique ID ................................................................................................ 751
6.8 DCSM Registers .......................................................................................................... 752
6.8.1 DCSM Base Addresses ......................................................................................... 752
6.8.2 DCSM_COMMON_REGS Registers .......................................................................... 753
6.8.3 DCSM_Z1_OTP Registers ..................................................................................... 771
6.8.4 DCSM_Z1_REGS Registers ................................................................................... 788
6.8.5 DCSM_Z2_OTP Registers ..................................................................................... 838
6.8.6 DCSM_Z2_REGS Registers ................................................................................... 848
7 Background CRC-32 (BGCRC) ............................................................................................ 889
7.1 Introduction ................................................................................................................ 890
7.2 Features .................................................................................................................... 890
7.2.1 Memory Wait States and Memory Map ....................................................................... 890
7.3 Functional Description.................................................................................................... 891
7.3.1 Data Read Unit ................................................................................................... 892
7.3.2 CRC-32 Compute Unit .......................................................................................... 892
7.3.3 CRC Notification Unit ............................................................................................ 892
7.3.4 Operating Modes................................................................................................. 893
7.3.5 BGCRC Watchdog............................................................................................... 894
7.3.6 Hardware and Software Faults Protection .................................................................... 894
7.4 Application of the BGCRC ............................................................................................... 894
7.4.1 Software Configuration .......................................................................................... 894
7.4.2 Decision on Error Response Severity ......................................................................... 895
7.4.3 Decision of Master for CLA_CRC ............................................................................. 895
7.4.4 Execution of Time Critical Code from Wait-Stated Memories ............................................. 896
7.4.5 BGCRC Execution ............................................................................................... 896
7.4.6 Debug/Error Response for BGCRC Errors ................................................................... 896
7.4.7 BGCRC Golden CRC-32 Value Computation ................................................................ 897
7.5 BGCRC Registers ........................................................................................................ 898
7.5.1 BGCRC Base Addresses ....................................................................................... 898
7.5.2 BGCRC_REGS Registers ...................................................................................... 899
8 Control Law Accelerator (CLA) ........................................................................................... 925
8.1 Introduction ................................................................................................................ 926
8.2 Features .................................................................................................................... 926
8.3 CLA Interface .............................................................................................................. 928
8.3.1 CLA Memory ..................................................................................................... 928
8.3.2 CLA Memory Bus ................................................................................................ 929
8.3.3 Shared Peripherals and EALLOW Protection ................................................................ 929
8.3.4 CLA Tasks and Interrupt Vectors .............................................................................. 930
8.3.5 CLA Software Interrupt to CPU ................................................................................ 935
8.4 CLA, DMA, and CPU Arbitration ........................................................................................ 935
8.4.1 CLA Message RAM ............................................................................................. 935
8.5 CLA Configuration and Debug .......................................................................................... 936
8.5.1 Building a CLA Application ..................................................................................... 936
8.5.2 Typical CLA Initialization Sequence ........................................................................... 936
8.5.3 Debugging CLA Code ........................................................................................... 938
8.5.4 CLA Illegal Opcode Behavior .................................................................................. 940
8.5.5 Resetting the CLA ............................................................................................... 940
8.6 Pipeline ..................................................................................................................... 940
8.6.1 Pipeline Overview ................................................................................................ 940
8.6.2 CLA Pipeline Alignment ......................................................................................... 941

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8.6.3 Parallel Instructions .............................................................................................. 945

8.7 Instruction Set ............................................................................................................. 946
8.7.1 Instruction Descriptions ......................................................................................... 946
8.7.2 Addressing Modes and Encoding.............................................................................. 948
8.7.3 Instructions ....................................................................................................... 950
8.8 CLA Registers ........................................................................................................... 1063
8.8.1 CLA Base Addresses .......................................................................................... 1063
8.8.2 CLA_ONLY_REGS Registers ................................................................................ 1064
8.8.3 CLA_REGS Registers ......................................................................................... 1071
8.8.4 CLA_SOFTINT_REGS Registers ............................................................................ 1117
9 Configurable Logic Block (CLB)........................................................................................ 1120
9.1 Introduction ............................................................................................................... 1121
9.2 Features .................................................................................................................. 1121
9.2.1 CLB Clock ....................................................................................................... 1122
9.3 CLB Input/Output Connection ......................................................................................... 1123
9.3.1 Overview......................................................................................................... 1123
9.3.2 CLB Input Selection ............................................................................................ 1123
9.3.3 CLB Output Selection .......................................................................................... 1134
9.3.4 Peripheral Signal Multiplexer ................................................................................. 1135
9.4 CLB Tile .................................................................................................................. 1140
9.4.1 Static Switch Block ............................................................................................. 1142
9.4.2 Counter Block ................................................................................................... 1143
9.4.3 FSM Block ....................................................................................................... 1148
9.4.4 LUT4 Block ...................................................................................................... 1149
9.4.5 Output LUT Block .............................................................................................. 1150
9.4.6 Asynchronous Output Conditioning (AOC) Block .......................................................... 1150
9.4.7 High Level Controller (HLC) .................................................................................. 1153
9.5 CPU Interface ............................................................................................................ 1158
9.5.1 Register Description ........................................................................................... 1158
9.5.2 Non-Memory Mapped Registers ............................................................................. 1158
9.6 CLB Registers ........................................................................................................... 1160
9.6.1 CLB Base Addresses .......................................................................................... 1160
9.6.2 CLB_LOGIC_CONFIG_REGS Registers ................................................................... 1161
9.6.3 CLB_LOGIC_CONTROL_REGS Registers ................................................................. 1213
9.6.4 CLB_DATA_EXCHANGE_REGS Registers ................................................................ 1244
9.6.5 Register to Driverlib Function Mapping ...................................................................... 1247
10 Dual-Clock Comparator (DCC) .......................................................................................... 1250
10.1 Introduction ............................................................................................................... 1251
10.2 Features .................................................................................................................. 1251
10.2.1 Block Diagram ................................................................................................. 1251
10.3 Module Operation ....................................................................................................... 1251
10.3.1 Configuring DCC Counters .................................................................................. 1252
10.3.2 Single-Shot Measurement Mode ............................................................................ 1252
10.3.3 Continuous Monitoring Mode ................................................................................ 1254
10.3.4 Error Conditions ............................................................................................... 1254
10.4 Interrupts ................................................................................................................. 1257
10.5 DCC Registers ........................................................................................................... 1257
10.5.1 DCC Base Addresses ........................................................................................ 1257
10.5.2 DCC_REGS Registers........................................................................................ 1258
10.5.3 Register to Driverlib Function Mapping..................................................................... 1269
11 Direct Memory Access (DMA) ........................................................................................... 1270
11.1 Introduction ............................................................................................................... 1271
11.2 Features .................................................................................................................. 1271

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11.3 Architecture .............................................................................................................. 1272

11.3.1 Block Diagram ................................................................................................. 1272
11.3.2 Peripheral Interrupt Event Trigger Sources ................................................................ 1273
11.3.3 DMA Bus ....................................................................................................... 1278
11.4 Address Pointer and Transfer Control ................................................................................ 1278
11.5 Pipeline Timing and Throughput ...................................................................................... 1284
11.6 CPU and CLA Arbitration ............................................................................................... 1285
11.7 Channel Priority.......................................................................................................... 1285
11.7.1 Round-Robin Mode ........................................................................................... 1285
11.7.2 Channel 1 High Priority Mode ............................................................................... 1286
11.8 Overrun Detection Feature ............................................................................................. 1287
11.9 DMA Registers........................................................................................................... 1287
11.9.1 DMA Base Addresses ........................................................................................ 1287
11.9.2 DMA_REGS Registers ....................................................................................... 1288
11.9.3 DMA_CH_REGS Registers .................................................................................. 1293
11.9.4 Register to Driverlib Function Mapping..................................................................... 1321
12 External Memory Interface (EMIF) ..................................................................................... 1323
12.1 Introduction ............................................................................................................... 1324
12.1.1 Purpose of the Peripheral .................................................................................... 1325
12.2 Features .................................................................................................................. 1325
12.2.1 Asynchronous Memory Support ............................................................................. 1325
12.2.2 Synchronous DRAM Memory Support ..................................................................... 1325
12.3 Functional Block Diagram .............................................................................................. 1325
12.4 Configuring Device Pins ................................................................................................ 1326
12.5 EMIF Module Architecture ............................................................................................. 1326
12.5.1 EMIF Clock Control ........................................................................................... 1326
12.5.2 EMIF Requests ................................................................................................ 1326
12.5.3 EMIF Signal Descriptions .................................................................................... 1327
12.5.4 EMIF Signal Multiplexing Control ........................................................................... 1328
12.5.5 SDRAM Controller and Interface ............................................................................ 1328
12.5.6 Asynchronous Controller and Interface .................................................................... 1341
12.5.7 Data Bus Parking.............................................................................................. 1353
12.5.8 Reset and Initialization Considerations ..................................................................... 1353
12.5.9 Interrupt Support .............................................................................................. 1353
12.5.10 DMA Event Support ......................................................................................... 1354
12.5.11 EMIF Signal Multiplexing ................................................................................... 1354
12.5.12 Memory Map ................................................................................................. 1354
12.5.13 Priority and Arbitration ...................................................................................... 1355
12.5.14 System Considerations ..................................................................................... 1356
12.5.15 Power Management ......................................................................................... 1357
12.5.16 Emulation Considerations .................................................................................. 1357
12.6 Example Configuration ................................................................................................. 1358
12.6.1 Hardware Interface ............................................................................................ 1358
12.6.2 Software Configuration ....................................................................................... 1358
12.7 EMIF Registers .......................................................................................................... 1366
12.7.1 EMIF Base Addresses ........................................................................................ 1366
12.7.2 EMIF_REGS Registers ....................................................................................... 1367
12.7.3 EMIF1_CONFIG_REGS Registers ......................................................................... 1387
12.7.4 EMIF2_CONFIG_REGS Registers ......................................................................... 1392
12.7.5 Register to Driverlib Function Mapping..................................................................... 1396
13 Flash Module .................................................................................................................. 1397
13.1 Introduction to Flash and OTP Memory .............................................................................. 1398
13.1.1 Features ........................................................................................................ 1398

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13.1.2 Flash Tools ..................................................................................................... 1398

13.1.3 Default Flash Configuration .................................................................................. 1399
13.1.4 Flash Bank, OTP, and Pump ................................................................................ 1399
13.1.5 Flash Module Controller (FMC) ............................................................................. 1400
13.1.6 Flash and OTP Power-Down Modes and Wakeup ....................................................... 1401
13.1.7 Active Grace Period........................................................................................... 1402
13.1.8 Flash and OTP Performance ................................................................................ 1403
13.1.9 Flash Read Interface.......................................................................................... 1403
13.1.10 Erase/Program Flash ........................................................................................ 1408
13.1.11 Error Correction Code (ECC) Protection ................................................................. 1409
13.1.12 Reserved Locations Within Flash and OTP .............................................................. 1413
13.1.13 Procedure to Change the Flash Control Registers ...................................................... 1413
13.1.14 Flash Pump Ownership Semaphore ...................................................................... 1413
13.2 Flash Registers .......................................................................................................... 1415
13.2.1 Flash Base Addresses........................................................................................ 1415
13.2.2 FLASH_CTRL_REGS Registers ............................................................................ 1416
13.2.3 FLASH_ECC_REGS Registers ............................................................................. 1425
13.2.4 CM_FLASH_CTRL_REGS Registers ...................................................................... 1448
13.2.5 CM_FLASH_ECC_REGS Registers ........................................................................ 1458
13.2.6 FLASH_PUMP_SEMAPHORE_REGS Registers ......................................................... 1482
13.2.7 Register to Driverlib Function Mapping..................................................................... 1484
14 Embedded Real-time Analysis and Diagnostic (ERAD) ........................................................ 1486
14.1 Introduction ............................................................................................................... 1487
14.2 Enhanced Bus Comparator Unit....................................................................................... 1488
14.2.1 Enhanced Bus Comparator Unit Operations .............................................................. 1488
14.2.2 Event Masking and Exporting ............................................................................... 1489
14.3 System Event Counter Unit ............................................................................................ 1489
14.3.1 System Event Counter Modes .............................................................................. 1490
14.3.2 Reset on Event ................................................................................................ 1494
14.3.3 Operation Conditions ......................................................................................... 1494
14.4 ERAD Ownership, Initialization and Reset ........................................................................... 1494
14.5 ERAD Programming Sequence ....................................................................................... 1495
14.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence .......................... 1495
14.5.2 Timer and Counter Programming Sequence .............................................................. 1496
14.6 Cyclic Redundancy Check Unit........................................................................................ 1496
14.6.1 CRC Unit Qualifier ............................................................................................ 1497
14.6.2 CRC Unit Programming Sequence ......................................................................... 1498
14.7 ERAD Registers ......................................................................................................... 1499
14.7.1 ERAD Base Addresses ....................................................................................... 1499
14.7.2 ERAD_GLOBAL_REGS Registers.......................................................................... 1500
14.7.3 ERAD_HWBP_REGS Registers ............................................................................ 1521
14.7.4 ERAD_COUNTER_REGS Registers ....................................................................... 1528
14.7.5 ERAD_CRC_GLOBAL_REGS Registers .................................................................. 1539
14.7.6 ERAD_CRC_REGS Registers............................................................................... 1542
15 General-Purpose Input/Output (GPIO) ................................................................................ 1546
15.1 Introduction ............................................................................................................... 1547
15.2 Configuration Overview ................................................................................................. 1548
15.3 Digital General-Purpose I/O Control .................................................................................. 1549
15.4 Input Qualification ....................................................................................................... 1550
15.4.1 No Synchronization (Asynchronous Input) ................................................................. 1550
15.4.2 Synchronization to SYSCLKOUT Only ..................................................................... 1550
15.4.3 Qualification Using a Sampling Window ................................................................... 1550
15.5 USB Signals.............................................................................................................. 1554

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15.6 SPI Signals ............................................................................................................... 1554

15.7 GPIO and Peripheral Muxing .......................................................................................... 1555
15.8 Internal Pullup Configuration Requirements ......................................................................... 1563
15.9 GPIO Registers .......................................................................................................... 1563
15.9.1 GPIO Base Addresses ....................................................................................... 1563
15.9.2 GPIO_CTRL_REGS Registers .............................................................................. 1564
15.9.3 GPIO_DATA_REGS Registers .............................................................................. 1708
15.9.4 GPIO_DATA_READ_REGS Registers ..................................................................... 1754
15.9.5 Register to Driverlib Function Mapping..................................................................... 1761
16 Interprocessor Communication (IPC) ................................................................................. 1767
16.1 Introduction ............................................................................................................... 1768
16.2 Message RAMs .......................................................................................................... 1768
16.3 IPC Flags and Interrupts ............................................................................................... 1771
16.4 IPC Command Registers ............................................................................................... 1771
16.5 Free-Running Counter .................................................................................................. 1771
16.6 IPC Communication Protocol .......................................................................................... 1772
16.7 IPC Registers ............................................................................................................ 1773
16.7.1 IPC Base Addresses .......................................................................................... 1773
16.7.2 CPU1TOCPU2_IPC_REGS_CPU1VIEW Registers ...................................................... 1774
16.7.3 CPU1TOCPU2_IPC_REGS_CPU2VIEW Registers ...................................................... 1807
16.7.4 CPU1TOCM_IPC_REGS_CPU1VIEW Registers ......................................................... 1840
16.7.5 CPU1TOCM_IPC_REGS_CMVIEW Registers ............................................................ 1872
16.7.6 CPU2TOCM_IPC_REGS_CPU2VIEW Registers ......................................................... 1905
16.7.7 CPU2TOCM_IPC_REGS_CMVIEW Registers ............................................................ 1934
17 Crossbar (X-BAR)............................................................................................................ 1963
17.1 Input, and CLB Input X-BAR ........................................................................................... 1964
17.1.1 CLB Input X-BAR.............................................................................................. 1966
17.2 ePWM, CLB, and GPIO Output X-BAR .............................................................................. 1967
17.2.1 ePWM X-BAR.................................................................................................. 1967
17.2.2 CLB X-BAR .................................................................................................... 1969
17.2.3 GPIO Output X-BAR .......................................................................................... 1971
17.2.4 CLB Output X-BAR ........................................................................................... 1973
17.2.5 X-BAR Flags .................................................................................................. 1974
17.3 XBAR Registers ......................................................................................................... 1976
17.3.1 XBAR Base Addresses ....................................................................................... 1976
17.3.2 XBAR_REGS Registers ...................................................................................... 1977
17.3.3 INPUT_XBAR_REGS Registers ............................................................................ 2010
17.3.4 OUTPUT_XBAR_REGS Registers ......................................................................... 2029
17.3.5 EPWM_XBAR_REGS Registers ............................................................................ 2122
17.3.6 CLB_XBAR_REGS Registers ............................................................................... 2207
17.3.7 Register to Driverlib Function Mapping..................................................................... 2292
18 ► ANALOG PERIPHERALS .............................................................................................. 2297
18.1 Technical Reference Manual Overview .............................................................................. 2298
19 Analog Subsystem .......................................................................................................... 2299
19.1 Introduction ............................................................................................................... 2300
19.1.1 Features ....................................................................................................... 2300
19.1.2 Block Diagram ................................................................................................. 2300
19.1.3 Lock Registers ................................................................................................. 2303
19.2 Analog Subsystem Registers .......................................................................................... 2303
19.2.1 Analog Subsystem Base Addresses ........................................................................ 2303
19.2.2 ANALOG_SUBSYS_REGS Registers ...................................................................... 2304
20 Analog-to-Digital Converter (ADC)..................................................................................... 2313

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20.1 Introduction ............................................................................................................... 2314

20.2 ADC Features ............................................................................................................ 2314
20.3 ADC Block Diagram ..................................................................................................... 2315
20.4 ADC Configurability ..................................................................................................... 2315
20.4.1 Clock Configuration ........................................................................................... 2316
20.4.2 Resolution ...................................................................................................... 2316
20.4.3 Voltage Reference ............................................................................................ 2316
20.4.4 Signal Mode .................................................................................................... 2317
20.4.5 Expected Conversion Results ............................................................................... 2317
20.4.6 Interpreting Conversion Results ............................................................................. 2318
20.5 SOC Principle of Operation ............................................................................................ 2319
20.5.1 SOC Configuration ............................................................................................ 2319
20.5.2 Trigger Operation ............................................................................................. 2319
20.5.3 ADC Acquisition (Sample and Hold) Window ............................................................. 2320
20.5.4 ADC Input Models ............................................................................................. 2320
20.5.5 Channel Selection ............................................................................................. 2321
20.6 SOC Configuration Examples ......................................................................................... 2322
20.6.1 Single Conversion from ePWM Trigger .................................................................... 2322
20.6.2 Oversampled Conversion from ePWM Trigger ............................................................ 2322
20.6.3 Multiple Conversions from CPU Timer Trigger ............................................................ 2323
20.6.4 Software Triggering of SOCs ................................................................................ 2324
20.7 ADC Conversion Priority ............................................................................................... 2324
20.8 Burst Mode ............................................................................................................... 2327
20.8.1 Burst Mode Example.......................................................................................... 2327
20.8.2 Burst Mode Priority Example ................................................................................ 2327
20.9 EOC and Interrupt Operation .......................................................................................... 2329
20.9.1 Interrupt Overflow ............................................................................................ 2330
20.9.2 Continue to Interrupt Mode .................................................................................. 2330
20.9.3 Early Interrupt Configuration Mode ......................................................................... 2330
20.10 Post-Processing Blocks ................................................................................................ 2330
20.10.1 PPB Offset Correction....................................................................................... 2331
20.10.2 PPB Error Calculation ....................................................................................... 2332
20.10.3 PPB Limit Detection and Zero-Crossing Detection ...................................................... 2332
20.10.4 PPB Sample Delay Capture ............................................................................... 2333
20.11 Opens/Shorts Detection Circuit (OSDETECT) ...................................................................... 2334
20.11.1 Implementation ............................................................................................... 2335
20.11.2 Detecting an Open Input Pin ............................................................................... 2335
20.11.3 Detecting a Shorted Input Pin .............................................................................. 2335
20.12 Power-Up Sequence ................................................................................................... 2336
20.13 ADC Calibration ......................................................................................................... 2336
20.13.1 ADC Zero Offset Calibration ............................................................................... 2336
20.13.2 ADC Calibration Routines in OTP ......................................................................... 2337
20.14 ADC Timings ............................................................................................................ 2337
20.14.1 ADC Timing Diagrams ...................................................................................... 2337
20.15 Additional Information .................................................................................................. 2343
20.15.1 Ensuring Synchronous Operation ......................................................................... 2343
20.15.2 Choosing an Acquisition Window Duration ............................................................... 2347
20.15.3 Achieving Simultaneous Sampling ........................................................................ 2349
20.15.4 Designing an External Reference Circuit ................................................................. 2349
20.15.5 Internal Temperature Sensor............................................................................... 2349
20.16 ADC Registers........................................................................................................... 2352
20.16.1 ADC Base Addresses ....................................................................................... 2352
20.16.2 ADC_REGS Registers ...................................................................................... 2353

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20.16.3 ADC_RESULT_REGS Registers .......................................................................... 2485

20.16.4 Register to Driverlib Function Mapping ................................................................... 2506
21 Buffered Digital-to-Analog Converter (DAC) ....................................................................... 2510
21.1 Introduction ............................................................................................................... 2511
21.1.1 Features ........................................................................................................ 2511
21.1.2 Block Diagram ................................................................................................. 2511
21.2 Using the DAC ........................................................................................................... 2511
21.2.1 Initialization Sequence ........................................................................................ 2512
21.2.2 DAC Offset Adjustment ....................................................................................... 2512
21.2.3 EPWMSYNCPER Signal ..................................................................................... 2512
21.3 Lock Registers ........................................................................................................... 2512
21.4 DAC Registers ........................................................................................................... 2513
21.4.1 DAC Base Addresses ........................................................................................ 2513
21.4.2 DAC_REGS Registers ........................................................................................ 2514
21.4.3 Register to Driverlib Function Mapping..................................................................... 2522
22 Comparator Subsystem (CMPSS) ...................................................................................... 2523
22.1 Introduction ............................................................................................................... 2524
22.2 Features .................................................................................................................. 2524
22.2.1 Block Diagram ................................................................................................. 2524
22.3 Comparator............................................................................................................... 2525
22.4 Reference DAC .......................................................................................................... 2526
22.5 Ramp Generator ......................................................................................................... 2527
22.5.1 Ramp Generator Overview .................................................................................. 2527
22.5.2 Ramp Generator Behavior ................................................................................... 2528
22.5.3 Ramp Generator Behavior at Corner Cases............................................................... 2529
22.6 Digital Filter .............................................................................................................. 2530
22.6.1 Filter Initialization Sequence ................................................................................. 2530
22.7 Using the CMPSS ....................................................................................................... 2531
22.7.1 LATCHCLR, EPWMSYNCPER and EPWMBLANK Signals ............................................ 2531
22.7.2 Synchronizer, Digital Filter and Latch Delays ............................................................. 2531
22.7.3 Calibrating the CMPSS ....................................................................................... 2532
22.7.4 Enabling and Disabling the CMPSS Clock ................................................................ 2532
22.8 CMPSS Registers ....................................................................................................... 2533
22.8.1 CMPSS Base Addresses..................................................................................... 2533
22.8.2 CMPSS_REGS Registers .................................................................................... 2534
22.8.3 Register to Driverlib Function Mapping..................................................................... 2559
23 ► CONTROL PERIPHERALS ............................................................................................ 2561
23.1 Technical Reference Manual Overview .............................................................................. 2562
24 Enhanced Capture (eCAP) ................................................................................................ 2563
24.1 Introduction ............................................................................................................... 2564
24.2 Features .................................................................................................................. 2564
24.3 Description ............................................................................................................... 2565
24.4 Configuring Device Pins for the eCAP ............................................................................... 2565
24.5 Capture and APWM Operating Mode ................................................................................ 2568
24.6 Capture Mode Description ............................................................................................. 2570
24.6.1 Event Prescaler ................................................................................................ 2571
24.6.2 Edge Polarity Select and Qualifier .......................................................................... 2571
24.6.3 Continuous/One-Shot Control ............................................................................... 2572
24.6.4 32-Bit Counter and Phase Control .......................................................................... 2573
24.6.5 CAP1-CAP4 Registers ....................................................................................... 2573
24.6.6 eCAP Synchronization ........................................................................................ 2573
24.6.7 Interrupt Control ............................................................................................... 2574

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24.6.8 DMA Interrupt .................................................................................................. 2576

24.6.9 Shadow Load and Lockout Control ......................................................................... 2576
24.6.10 APWM Mode Operation..................................................................................... 2576
24.7 Application of the eCAP Module ...................................................................................... 2578
24.7.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger .................................... 2578
24.7.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger ...................... 2579
24.7.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger .................................. 2580
24.7.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger .................... 2581
24.8 Application of the APWM Mode ....................................................................................... 2582
24.8.1 Example 1 - Simple PWM Generation (Independent Channel/s) ....................................... 2582
24.9 eCAP Registers.......................................................................................................... 2583
24.9.1 eCAP Base Addresses ....................................................................................... 2583
24.9.2 ECAP_REGS Registers ...................................................................................... 2584
24.9.3 Register to Driverlib Function Mapping..................................................................... 2603
25 High Resolution Capture (HRCAP) .................................................................................... 2605
25.1 Introduction ............................................................................................................... 2606
25.2 Description ............................................................................................................... 2606
25.3 Operational Details ...................................................................................................... 2606
25.3.1 HRCAP Clocking .............................................................................................. 2608
25.3.2 HRCAP Initialization Sequence ............................................................................. 2608
25.3.3 HRCAP Interrupts ............................................................................................. 2608
25.3.4 HRCAP Calibration............................................................................................ 2609
25.4 Known Exceptions....................................................................................................... 2610
25.5 HRCAP Registers ....................................................................................................... 2610
25.5.1 HRCAP Base Addresses ..................................................................................... 2610
25.5.2 HRCAP_REGS Registers .................................................................................... 2611
26 Enhanced Pulse Width Modulator (ePWM) ......................................................................... 2622
26.1 Introduction ............................................................................................................... 2623
26.1.1 Submodule Overview ......................................................................................... 2625
26.2 Configuring Device Pins ................................................................................................ 2630
26.3 ePWM Modules Overview .............................................................................................. 2630
26.4 Time-Base (TB) Submodule ........................................................................................... 2632
26.4.1 Purpose of the Time-Base Submodule ..................................................................... 2632
26.4.2 Controlling and Monitoring the Time-Base Submodule .................................................. 2633
26.4.3 Calculating PWM Period and Frequency .................................................................. 2635
26.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules..................................... 2640
26.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules .................... 2640
26.4.6 Time-Base Counter Modes and Timing Waveforms ...................................................... 2640
26.4.7 Global Load .................................................................................................... 2644
26.5 Counter-Compare (CC) Submodule .................................................................................. 2645
26.5.1 Purpose of the Counter-Compare Submodule ............................................................ 2645
26.5.2 Controlling and Monitoring the Counter-Compare Submodule .......................................... 2646
26.5.3 Operational Highlights for the Counter-Compare Submodule ........................................... 2647
26.5.4 Count Mode Timing Waveforms ............................................................................ 2648
26.6 Action-Qualifier (AQ) Submodule ..................................................................................... 2651
26.6.1 Purpose of the Action-Qualifier Submodule ............................................................... 2651
26.6.2 Action-Qualifier Submodule Control and Status Register Definitions .................................. 2652
26.6.3 Action-Qualifier Event Priority ............................................................................... 2654
26.6.4 AQCTLA and AQCTLB Shadow Mode Operations ....................................................... 2655
26.6.5 Waveforms for Common Configurations ................................................................... 2657
26.7 Dead-Band Generator (DB) Submodule ............................................................................. 2664
26.7.1 Purpose of the Dead-Band Submodule .................................................................... 2664
26.7.2 Dead-band Submodule Additional Operating Modes ..................................................... 2664

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26.7.3 Operational Highlights for the Dead-Band Submodule ................................................... 2666

26.8 PWM Chopper (PC) Submodule ..................................................................................... 2670
26.8.1 Purpose of the PWM Chopper Submodule ................................................................ 2670
26.8.2 Operational Highlights for the PWM Chopper Submodule............................................... 2670
26.8.3 Waveforms ..................................................................................................... 2671
26.9 Trip-Zone (TZ) Submodule ............................................................................................. 2674
26.9.1 Purpose of the Trip-Zone Submodule ...................................................................... 2674
26.9.2 Operational Highlights for the Trip-Zone Submodule ..................................................... 2675
26.9.3 Generating Trip Event Interrupts ............................................................................ 2678
26.10 Event-Trigger (ET) Submodule........................................................................................ 2680
26.10.1 Operational Overview of the ePWM Type 4 Event-Trigger Submodule .............................. 2680
26.11 Digital Compare (DC) Submodule .................................................................................... 2685
26.11.1 Purpose of the Digital Compare Submodule ............................................................. 2686
26.11.2 Enhanced Trip Action Using CMPSS ..................................................................... 2687
26.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis ......................................... 2687
26.11.4 Operation Highlights of the Digital Compare Submodule .............................................. 2687
26.12 ePWM X-BAR ........................................................................................................... 2693
26.13 Applications to Power Topologies .................................................................................... 2694
26.13.1 Overview of Multiple Modules ............................................................................. 2694
26.13.2 Key Configuration Capabilities ............................................................................. 2695
26.13.3 Controlling Multiple Buck Converters With Independent Frequencies ................................ 2696
26.13.4 Controlling Multiple Buck Converters With Same Frequencies ........................................ 2698
26.13.5 Controlling Multiple Half H-Bridge (HHB) Converters ................................................... 2700
26.13.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ..................................... 2702
26.13.7 Practical Applications Using Phase Control Between PWM Modules ................................ 2704
26.13.8 Controlling a 3-Phase Interleaved DC/DC Converter ................................................... 2705
26.13.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter................................... 2708
26.13.10 Controlling a Peak Current Mode Controlled Buck Module ........................................... 2710
26.13.11 Controlling H-Bridge LLC Resonant Converter......................................................... 2711
26.14 Register Lock Protection ............................................................................................... 2712
26.15 High-Resolution Pulse Width Modulator (HRPWM) ................................................................ 2713
26.15.1 Operational Description of HRPWM....................................................................... 2715
26.15.2 SFO Library Software - SFO_TI_Build_V8.lib ........................................................... 2736
26.16 ePWM Registers ........................................................................................................ 2739
26.16.1 ePWM Base Addresses..................................................................................... 2739
26.16.2 EPWM_REGS Registers ................................................................................... 2740
26.16.3 SYNC_SOC_REGS Registers ............................................................................. 2859
26.16.4 Register to Driverlib Function Mapping ................................................................... 2865
27 Enhanced Quadrature Encoder Pulse (eQEP) ..................................................................... 2873
27.1 Introduction ............................................................................................................... 2874
27.2 Configuring Device Pins ................................................................................................ 2876
27.3 Description ............................................................................................................... 2876
27.3.1 EQEP Inputs ................................................................................................... 2876
27.3.2 Functional Description ........................................................................................ 2878
27.3.3 eQEP Memory Map ........................................................................................... 2880
27.4 Quadrature Decoder Unit (QDU) ...................................................................................... 2881
27.4.1 Position Counter Input Modes ............................................................................... 2881
27.4.2 eQEP Input Polarity Selection ............................................................................... 2884
27.4.3 Position-Compare Sync Output ............................................................................. 2884
27.5 Position Counter and Control Unit (PCCU) .......................................................................... 2884
27.5.1 Position Counter Operating Modes ......................................................................... 2884
27.5.2 Position Counter Latch ....................................................................................... 2886
27.5.3 Position Counter Initialization ................................................................................ 2889

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27.5.4 eQEP Position-compare Unit ................................................................................ 2889

27.6 eQEP Edge Capture Unit .............................................................................................. 2891
27.7 eQEP Watchdog ......................................................................................................... 2894
27.8 Unit Timer Base ......................................................................................................... 2895
27.9 QMA Module ............................................................................................................. 2896
27.9.1 Modes of Operation ........................................................................................... 2897
27.9.2 Interrupt and Error Generation .............................................................................. 2898
27.10 eQEP Interrupt Structure ............................................................................................... 2899
27.11 eQEP Registers ......................................................................................................... 2899
27.11.1 eQEP Base Addresses ..................................................................................... 2899
27.11.2 EQEP_REGS Registers .................................................................................... 2900
27.11.3 Register to Driverlib Function Mapping ................................................................... 2939
28 Sigma Delta Filter Module (SDFM) ..................................................................................... 2941
28.1 Introduction ............................................................................................................... 2942
28.1.1 SDFM Features ................................................................................................ 2942
28.1.2 Block Diagram ................................................................................................. 2943
28.2 Configuring Device Pins ................................................................................................ 2945
28.3 Input Qualification ...................................................................................................... 2946
28.4 Input Control Unit ........................................................................................................ 2947
28.5 SDFM Clock Control .................................................................................................... 2947
28.6 Sinc Filter ................................................................................................................. 2948
28.6.1 Data Rate and Latency of the Sinc Filter .................................................................. 2950
28.7 Data (Primary) Filter Unit ............................................................................................... 2950
28.7.1 32-bit or 16-bit Data Filter Output Representation ........................................................ 2951
28.7.2 Data FIFO ...................................................................................................... 2951
28.7.3 SDSYNC Event ................................................................................................ 2953
28.8 Comparator (Secondary) Filter Unit ................................................................................... 2955
28.8.1 Higher Threshold (HLT) Comparators ...................................................................... 2957
28.8.2 Lower Threshold (LLT) Comparators ....................................................................... 2957
28.8.3 Digital Filter .................................................................................................... 2958
28.9 Interrupt Unit ............................................................................................................. 2959
28.9.1 SDFM (SDyERR) Interrupt Sources ........................................................................ 2959
28.9.2 Data Ready (DRINT) Interrupt Sources .................................................................... 2960
28.10 SDFM Registers ......................................................................................................... 2962
28.10.1 SDFM Base Addesses ...................................................................................... 2962
28.10.2 SDFM_REGS Registers .................................................................................... 2963
28.10.3 Register to Driverlib Function Mapping ................................................................... 3053
29 ► COMMUNICATION PERIPHERALS ................................................................................. 3056
29.1 Technical Reference Manual Overview .............................................................................. 3057
30 Controller Area Network (CAN) ......................................................................................... 3058
30.1 Introduction ............................................................................................................... 3059
30.1.1 Features ....................................................................................................... 3059
30.1.2 Functional Description ....................................................................................... 3059
30.1.3 Block Diagram ................................................................................................ 3060
30.2 Configuring Device Pins ................................................................................................ 3061
30.3 Address/Data Bus Bridge .............................................................................................. 3061
30.4 Operating Modes ........................................................................................................ 3063
30.4.1 Initialization .................................................................................................... 3063
30.4.2 CAN Message Transfer (Normal Operation) .............................................................. 3064
30.4.3 Test Modes .................................................................................................... 3064
30.5 Multiple Clock Source .................................................................................................. 3068
30.6 Interrupt Functionality .................................................................................................. 3068
30.6.1 Message Object Interrupts .................................................................................. 3068

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30.6.2 Status Change Interrupts .................................................................................... 3068

30.6.3 Error Interrupts ................................................................................................ 3069
30.6.4 PIE Nomenclature for DCAN Interrupts .................................................................... 3069
30.6.5 Interrupt Topologies .......................................................................................... 3069
30.7 DMA Functionality ...................................................................................................... 3070
30.8 Parity Check Mechanism .............................................................................................. 3070
30.8.1 Behavior on Parity Error ..................................................................................... 3071
30.9 Debug Mode ............................................................................................................ 3071
30.10 Module Initialization .................................................................................................... 3071
30.11 Configuration of Message Objects ................................................................................... 3072
30.11.1 Configuration of a Transmit Object for Data Frames ................................................... 3072
30.11.2 Configuration of a Transmit Object for Remote Frames ............................................... 3072
30.11.3 Configuration of a Single Receive Object for Data Frames ........................................... 3072
30.11.4 Configuration of a Single Receive Object for Remote Frames ....................................... 3073
30.11.5 Configuration of a FIFO Buffer ............................................................................ 3073
30.12 Message Handling ..................................................................................................... 3073
30.12.1 Message Handler Overview ............................................................................... 3074
30.12.2 Receive/Transmit Priority .................................................................................. 3074
30.12.3 Transmission of Messages in Event Driven CAN Communication ................................... 3074
30.12.4 Updating a Transmit Object ............................................................................... 3075
30.12.5 Changing a Transmit Object ............................................................................... 3075
30.12.6 Acceptance Filtering of Received Messages ............................................................ 3076
30.12.7 Reception of Data Frames ................................................................................. 3076
30.12.8 Reception of Remote Frames ............................................................................. 3076
30.12.9 Reading Received Messages ............................................................................. 3076
30.12.10 Requesting New Data for a Receive Object ........................................................... 3077
30.12.11 Storing Received Messages in FIFO Buffers .......................................................... 3077
30.12.12 Reading from a FIFO Buffer ............................................................................. 3077
30.13 CAN Bit Timing ......................................................................................................... 3079
30.13.1 Bit Time and Bit Rate ....................................................................................... 3079
30.13.2 Configuration of the CAN Bit Timing ..................................................................... 3084
30.14 Message Interface Register Sets .................................................................................... 3088
30.14.1 Message Interface Register Sets 1 and 2 ............................................................... 3088
30.14.2 IF3 Register Set ............................................................................................. 3088
30.15 Message RAM .......................................................................................................... 3090
30.15.1 Structure of Message Objects ............................................................................. 3090
30.15.2 Addressing Message Objects in RAM ................................................................... 3092
30.15.3 Message RAM Representation in Debug Mode ........................................................ 3093
30.16 CAN Registers........................................................................................................... 3094
30.16.1 CAN Base Addresses ....................................................................................... 3094
30.16.2 CAN_REGS Registers ...................................................................................... 3095
30.16.3 Register to Driverlib Function Mapping ................................................................... 3150
31 EtherCAT™ Slave Controller (ESC) ................................................................................... 3152
31.1 Introduction ............................................................................................................... 3153
31.1.1 ESC Features .................................................................................................. 3153
31.1.2 ESC Subsystem Integrated Features....................................................................... 3154
31.1.3 F2838x ESC vs Beckhoff ET1100 .......................................................................... 3154
31.1.4 EtherCAT IP Block Diagram ................................................................................. 3155
31.1.5 ESC Functional Blocks ....................................................................................... 3155
31.1.6 EtherCAT Physical Layer .................................................................................... 3158
31.1.7 EtherCAT Protocol ............................................................................................ 3161
31.1.8 EtherCAT State Machine ..................................................................................... 3161
31.1.9 More Information on EtherCAT .............................................................................. 3162

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31.1.10 Beckhoff Automation™ EtherCAT IP Errata ............................................................. 3162

31.2 ESC and ESCSS Description .......................................................................................... 3162
31.2.1 ESC RAM Parity and Memory Maps ....................................................................... 3164
31.2.2 Local Host Communication .................................................................................. 3165
31.2.3 Debug Emulation Mode Operation .......................................................................... 3166
31.2.4 ESC SubSystem............................................................................................... 3166
31.2.5 Interrupts and Interrupt Mapping ............................................................................ 3168
31.2.6 Power, Clocks, and Resets .................................................................................. 3168
31.2.7 LED Controls ................................................................................................... 3170
31.2.8 Slave Node Configuration and EEPROM ................................................................. 3171
31.2.9 General Purpose Inputs and Outputs....................................................................... 3172
31.2.10 Distributed Clocks – Sync and Latch...................................................................... 3173
31.3 Software Initialization Sequence and Allocating Ownership ....................................................... 3182
31.4 ESC Configuration Constants ......................................................................................... 3183
31.5 EtherCAT IP Registers ................................................................................................. 3184
31.6 EtherCAT Subsystem Registers....................................................................................... 3184
31.6.1 EtherCAT Subsystem Base Addresses .................................................................... 3184
31.6.2 ESCSS_CONFIG_REGS Registers ........................................................................ 3185
31.6.3 ESCSS_REGS Registers .................................................................................... 3198
32 Fast Serial Interface (FSI) ................................................................................................. 3222
32.1 Introduction ............................................................................................................... 3223
32.2 Features ................................................................................................................. 3223
32.3 System-level Integration ................................................................................................ 3223
32.3.1 CPU Interface .................................................................................................. 3223
32.3.2 Signal Description ............................................................................................ 3225
32.3.3 Interrupts ....................................................................................................... 3226
32.3.4 CLA Task Triggering .......................................................................................... 3228
32.3.5 DMA Interface ................................................................................................. 3229
32.3.6 External Frame Trigger Mux ................................................................................. 3229
32.4 FSI Operation ............................................................................................................ 3230
32.4.1 Introduction to Operation ..................................................................................... 3230
32.4.2 FSI Transmitter Module ...................................................................................... 3231
32.4.3 FSI Receiver Module ......................................................................................... 3237
32.4.4 Frame Format.................................................................................................. 3243
32.4.5 The Flush Sequence .......................................................................................... 3246
32.4.6 Internal Loopback ............................................................................................. 3247
32.4.7 CRC Generation ............................................................................................... 3247
32.4.8 ECC Module ................................................................................................... 3248
32.4.9 Tag Matching .................................................................................................. 3249
32.4.10 Multi-Slave Configurations .................................................................................. 3249
32.4.11 FSI-SPI Compatibility Mode ................................................................................ 3252
32.5 Programmer's Model .................................................................................................... 3256
32.5.1 Establishing the Communication Link ..................................................................... 3256
32.5.2 Register Protection ............................................................................................ 3258
32.5.3 Emulation Mode ............................................................................................... 3258
32.6 FSI Registers ............................................................................................................ 3259
32.6.1 FSI Base Addresses .......................................................................................... 3259
32.6.2 FSI_RX_REGS Registers .................................................................................... 3260
32.6.3 FSI_TX_REGS Registers .................................................................................... 3300
32.7 Register to Driverlib Function Mapping ............................................................................... 3326
33 Inter-Integrated Circuit Module (I2C) .................................................................................. 3330
33.1 Introduction ............................................................................................................... 3331
33.1.1 Features ........................................................................................................ 3331

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33.1.2 Features Not Supported ...................................................................................... 3332

33.1.3 Functional Overview .......................................................................................... 3332
33.1.4 Clock Generation .............................................................................................. 3333
33.1.5 I2C Clock Divider Registers (I2CCLKL and I2CCLKH) .................................................. 3334
33.2 Configuring Device Pins ................................................................................................ 3335
33.3 I2C Module Operational Details ....................................................................................... 3335
33.3.1 Input and Output Voltage Levels ............................................................................ 3335
33.3.2 Data Validity ................................................................................................... 3335
33.3.3 Operating Modes .............................................................................................. 3335
33.3.4 I2C Module START and STOP Conditions ................................................................ 3337
33.3.5 Serial Data Formats........................................................................................... 3338
33.3.6 NACK Bit Generation ......................................................................................... 3340
33.3.7 Clock Synchronization ........................................................................................ 3341
33.3.8 Arbitration ...................................................................................................... 3342
33.3.9 Digital Loopback Mode ....................................................................................... 3343
33.4 Interrupt Requests Generated by the I2C Module .................................................................. 3344
33.4.1 Basic I2C Interrupt Requests ................................................................................ 3344
33.4.2 I2C FIFO Interrupts ........................................................................................... 3347
33.5 Resetting or Disabling the I2C Module ............................................................................... 3347
33.6 I2C Registers ............................................................................................................ 3348
33.6.1 I2C Base Addresses .......................................................................................... 3348
33.6.2 I2C_REGS Registers ......................................................................................... 3349
33.6.3 Register to Driverlib Function Mapping..................................................................... 3372
34 Multichannel Buffered Serial Port (McBSP) ........................................................................ 3374
34.1 Overview.................................................................................................................. 3375
34.1.1 Features of the McBSPs ..................................................................................... 3375
34.1.2 McBSP Pins/Signals .......................................................................................... 3376
34.2 Configuring Device Pins ................................................................................................ 3377
34.3 McBSP Operation ....................................................................................................... 3377
34.3.1 Data Transfer Process of McBSPs ......................................................................... 3378
34.3.2 Companding (Compressing and Expanding) Data........................................................ 3379
34.3.3 Clocking and Framing Data .................................................................................. 3380
34.3.4 Frame Phases ................................................................................................. 3383
34.3.5 McBSP Reception ............................................................................................. 3385
34.3.6 McBSP Transmission ......................................................................................... 3386
34.3.7 Interrupts and DMA Events Generated by a McBSP ..................................................... 3387
34.4 McBSP Sample Rate Generator ...................................................................................... 3387
34.4.1 Block Diagram ................................................................................................. 3388
34.4.2 Frame Synchronization Generation in the Sample Rate Generator .................................... 3391
34.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock ................................. 3391
34.4.4 Reset and Initialization Procedure for the Sample Rate Generator .................................... 3393
34.5 McBSP Exception/Error Conditions ................................................................................... 3394
34.5.1 Types of Errors ................................................................................................ 3394
34.5.2 Overrun in the Receiver ...................................................................................... 3394
34.5.3 Unexpected Receive Frame-Synchronization Pulse ..................................................... 3396
34.5.4 Overwrite in the Transmitter ................................................................................. 3398
34.5.5 Underflow in the Transmitter ................................................................................. 3399
34.5.6 Unexpected Transmit Frame-Synchronization Pulse ..................................................... 3400
34.6 Multichannel Selection Modes ......................................................................................... 3402
34.6.1 Channels, Blocks, and Partitions ............................................................................ 3402
34.6.2 Multichannel Selection ........................................................................................ 3403
34.6.3 Configuring a Frame for Multichannel Selection .......................................................... 3403
34.6.4 Using Two Partitions .......................................................................................... 3403

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34.6.5 Using Eight Partitions ......................................................................................... 3405

34.6.6 Receive Multichannel Selection Mode...................................................................... 3406
34.6.7 Transmit Multichannel Selection Modes ................................................................... 3406
34.6.8 Using Interrupts Between Block Transfers ................................................................. 3408
34.7 SPI Operation Using the Clock Stop Mode .......................................................................... 3409
34.7.1 SPI Protocol .................................................................................................... 3409
34.7.2 Clock Stop Mode .............................................................................................. 3410
34.7.3 Enable and Configure the Clock Stop Mode .............................................................. 3410
34.7.4 Clock Stop Mode Timing Diagrams ......................................................................... 3411
34.7.5 Procedure for Configuring a McBSP for SPI Operation .................................................. 3413
34.7.6 McBSP as the SPI Master ................................................................................... 3413
34.7.7 McBSP as an SPI Slave...................................................................................... 3415
34.8 Receiver Configuration ................................................................................................. 3416
34.8.1 Programming the McBSP Registers for the Desired Receiver Operation ............................. 3416
34.8.2 Resetting and Enabling the Receiver ....................................................................... 3417
34.8.3 Set the Receiver Pins to Operate as McBSP Pins ....................................................... 3417
34.8.4 Digital Loopback Mode ....................................................................................... 3418
34.8.5 Clock Stop Mode .............................................................................................. 3418
34.8.6 Receive Multichannel Selection Mode...................................................................... 3419
34.8.7 Receive Frame Phases....................................................................................... 3419
34.8.8 Receive Word Length(s) ..................................................................................... 3420
34.8.9 Receive Frame Length ....................................................................................... 3420
34.8.10 Receive Frame-Synchronization Ignore Function ....................................................... 3421
34.8.11 Receive Companding Mode ................................................................................ 3422
34.8.12 Receive Data Delay ......................................................................................... 3423
34.8.13 Receive Sign-Extension and Justification Mode ......................................................... 3425
34.8.14 Receive Interrupt Mode ..................................................................................... 3426
34.8.15 Receive Frame-Synchronization Mode ................................................................... 3426
34.8.16 Receive Frame-Synchronization Polarity ................................................................. 3428
34.8.17 Receive Clock Mode ........................................................................................ 3430
34.8.18 Receive Clock Polarity ...................................................................................... 3431
34.8.19 SRG Clock Divide-Down Value ............................................................................ 3433
34.8.20 SRG Clock Synchronization Mode ........................................................................ 3433
34.8.21 SRG Clock Mode (Choose an Input Clock) .............................................................. 3434
34.8.22 SRG Input Clock Polarity ................................................................................... 3435
34.9 Transmitter Configuration .............................................................................................. 3435
34.9.1 Programming the McBSP Registers for the Desired Transmitter Operation .......................... 3435
34.9.2 Resetting and Enabling the Transmitter .................................................................... 3436
34.9.3 Set the Transmitter Pins to Operate as McBSP Pins .................................................... 3437
34.9.4 Digital Loopback Mode ....................................................................................... 3437
34.9.5 Clock Stop Mode .............................................................................................. 3437
34.9.6 Transmit Multichannel Selection Mode ..................................................................... 3438
34.9.7 XCERs Used in the Transmit Multichannel Selection Mode............................................. 3439
34.9.8 Transmit Frame Phases ...................................................................................... 3442
34.9.9 Transmit Word Length(s) ..................................................................................... 3442
34.9.10 Transmit Frame Length ..................................................................................... 3443
34.9.11 Enable/Disable the Transmit Frame-Synchronization Ignore Function ............................... 3444
34.9.12 Transmit Companding Mode ............................................................................... 3445
34.9.13 Transmit Data Delay ........................................................................................ 3446
34.9.14 Transmit DXENA Mode ..................................................................................... 3448
34.9.15 Transmit Interrupt Mode .................................................................................... 3448
34.9.16 Transmit Frame-Synchronization Mode .................................................................. 3449
34.9.17 Transmit Frame-Synchronization Polarity ................................................................ 3450

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34.9.18 SRG Frame-Synchronization Period and Pulse Width ................................................. 3451

34.9.19 Transmit Clock Mode ........................................................................................ 3452
34.9.20 Transmit Clock Polarity ..................................................................................... 3452
34.10 Emulation and Reset Considerations ................................................................................ 3453
34.10.1 McBSP Emulation Mode .................................................................................... 3454
34.10.2 Resetting and Initializing McBSPs ......................................................................... 3454
34.11 Data Packing Examples ................................................................................................ 3456
34.11.1 Data Packing Using Frame Length and Word Length .................................................. 3456
34.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function ............... 3458
34.12 Interrupt Generation .................................................................................................... 3458
34.12.1 McBSP Receive Interrupt Generation ..................................................................... 3459
34.12.2 McBSP Transmit Interrupt Generation .................................................................... 3459
34.12.3 Error Flags ................................................................................................... 3460
34.13 McBSP Modes........................................................................................................... 3460
34.14 Special Case: External Device is the Transmit Frame Master .................................................... 3461
34.15 McBSP Registers ...................................................................................................... 3463
34.15.1 McBSP Base Addresses .................................................................................... 3463
34.15.2 Data Receive Registers (DRR[1,2]) ....................................................................... 3464
34.15.3 Data Transmit Registers (DXR[1,2]) ...................................................................... 3464
34.15.4 Serial Port Control Registers (SPCR[1,2]) ............................................................... 3465
34.15.5 Receive Control Registers (RCR[1, 2]) .................................................................. 3470
34.15.6 Transmit Control Registers (XCR1 and XCR2) .......................................................... 3472
34.15.7 Sample Rate Generator Registers (SRGR1 and SRGR2) ............................................. 3475
34.15.8 Multichannel Control Registers (MCR[1,2]) .............................................................. 3477
34.15.9 Pin Control Register (PCR) ................................................................................. 3482
34.15.10 Receive Channel Enable Registers (RCERA, RCERB, RCERC, RCERD, RCERE, RCERF,
RCERG, RCERH) .............................................................................................. 3484
34.15.11 Transmit Channel Enable Registers (XCERA, XCERB, XCERC, XCERD, XCERE, XCERF,
XCERG, XCERH) .............................................................................................. 3486
34.15.12 XCERs Used in a Transmit Multichannel Selection Mode ............................................ 3487
34.15.13 McBSP Interrupt Enable Register ........................................................................ 3488
34.16 Register to Driverlib Function Mapping .............................................................................. 3489
35 Power Management Bus Module (PMBus) .......................................................................... 3492
35.1 Introduction ............................................................................................................... 3493
35.1.1 Features ........................................................................................................ 3493
35.1.2 Functional Description ........................................................................................ 3493
35.2 Configuring Device Pins ................................................................................................ 3494
35.3 Slave Mode Operation .................................................................................................. 3494
35.3.1 Configuration ................................................................................................... 3495
35.3.2 Message Handling ............................................................................................ 3495
35.4 Master Mode Operation ................................................................................................ 3503
35.4.1 Configuration ................................................................................................... 3504
35.4.2 Message Handling ............................................................................................ 3504
35.5 PMBus Registers ........................................................................................................ 3512
35.5.1 PMBus Base Addresses ..................................................................................... 3512
35.5.2 PMBUS_REGS Registers .................................................................................... 3513
36 Serial Communications Interface (SCI) .............................................................................. 3533
36.1 Introduction ............................................................................................................... 3534
36.2 Architecture .............................................................................................................. 3535
36.3 SCI Module Signal Summary .......................................................................................... 3535
36.4 Configuring Device Pins ................................................................................................ 3535
36.5 Multiprocessor and Asynchronous Communication Modes........................................................ 3537
36.6 SCI Programmable Data Format ...................................................................................... 3537

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36.7 SCI Multiprocessor Communication .................................................................................. 3538

36.7.1 Recognizing the Address Byte .............................................................................. 3538
36.7.2 Controlling the SCI TX and RX Features .................................................................. 3538
36.7.3 Receipt Sequence............................................................................................. 3538
36.8 Idle-Line Multiprocessor Mode......................................................................................... 3539
36.8.1 Idle-Line Mode Steps ......................................................................................... 3539
36.8.2 Block Start Signal ............................................................................................. 3539
36.8.3 Wake-UP Temporary (WUT) Flag .......................................................................... 3540
36.8.4 Receiver Operation ........................................................................................... 3540
36.9 Address-Bit Multiprocessor Mode ..................................................................................... 3541
36.9.1 Sending an Address .......................................................................................... 3541
36.10 SCI Communication Format ........................................................................................... 3542
36.10.1 Receiver Signals in Communication Modes.............................................................. 3543
36.10.2 Transmitter Signals in Communication Modes........................................................... 3544
36.11 SCI Port Interrupts ...................................................................................................... 3545
36.12 SCI Baud Rate Calculations ........................................................................................... 3545
36.13 SCI Enhanced Features................................................................................................ 3546
36.13.1 SCI FIFO Description ....................................................................................... 3546
36.13.2 SCI Auto-Baud ............................................................................................... 3548
36.13.3 Autobaud-Detect Sequence ................................................................................ 3548
36.14 SCI Registers ............................................................................................................ 3548
36.14.1 SCI Base Addresses ........................................................................................ 3548
36.14.2 SCI_REGS Registers ....................................................................................... 3549
36.14.3 Register to Driverlib Function Mapping ................................................................... 3569
37 Serial Peripheral Interface (SPI) ........................................................................................ 3571
37.1 Introduction ............................................................................................................... 3572
37.1.1 Features ........................................................................................................ 3572
37.1.2 Block Diagram ................................................................................................ 3573
37.2 System-Level Integration ............................................................................................... 3573
37.2.1 SPI Module Signals ........................................................................................... 3573
37.2.2 Configuring Device Pins ...................................................................................... 3574
37.2.3 SPI Interrupts .................................................................................................. 3574
37.2.4 DMA Support .................................................................................................. 3576
37.3 SPI Operation ............................................................................................................ 3577
37.3.1 Introduction to Operation ..................................................................................... 3577
37.3.2 Master Mode ................................................................................................... 3577
37.3.3 Slave Mode .................................................................................................... 3579
37.3.4 Data Format .................................................................................................... 3581
37.3.5 Baud Rate Selection ......................................................................................... 3582
37.3.6 SPI Clocking Schemes ....................................................................................... 3583
37.3.7 SPI FIFO Description ......................................................................................... 3584
37.3.8 SPI DMA Transfers ........................................................................................... 3585
37.3.9 SPI High-Speed Mode ........................................................................................ 3586
37.3.10 SPI 3-Wire Mode Description .............................................................................. 3586
37.4 Programming Procedure ............................................................................................... 3588
37.4.1 Initialization Upon Reset ..................................................................................... 3588
37.4.2 Configuring the SPI ........................................................................................... 3588
37.4.3 Configuring the SPI for High-Speed Mode ................................................................. 3589
37.4.4 Data Transfer Example ....................................................................................... 3589
37.4.5 SPI 3-Wire Mode Code Examples .......................................................................... 3590
37.4.6 SPI STEINV Bit in Digital Audio Transfers ................................................................. 3592
37.5 SPI Registers ............................................................................................................ 3593
37.5.1 SPI Base Addresses .......................................................................................... 3593

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37.5.2 SPI_REGS Registers ......................................................................................... 3594

37.5.3 Register to Driverlib Function Mapping..................................................................... 3613
38 Universal Serial Bus (USB) Controller................................................................................ 3615
38.1 Introduction ............................................................................................................... 3616
38.2 Features .................................................................................................................. 3616
38.2.1 Block Diagram ................................................................................................. 3616
38.2.2 Signal Description ............................................................................................. 3617
38.2.3 VBus Recommendations ..................................................................................... 3617
38.3 Functional Description .................................................................................................. 3618
38.3.1 Operation as a Device ........................................................................................ 3618
38.3.2 Operation as a Host........................................................................................... 3622
38.3.3 DMA Operation ................................................................................................ 3625
38.3.4 Address/Data Bus Bridge .................................................................................... 3625
38.4 Initialization and Configuration......................................................................................... 3627
38.4.1 Pin Configuration .............................................................................................. 3627
38.4.2 Endpoint Configuration ....................................................................................... 3628
38.5 USB Global Interrupts .................................................................................................. 3628
38.6 USB Registers ........................................................................................................... 3629
38.6.1 USB Base Address ........................................................................................... 3629
38.6.2 USB Register Map ............................................................................................ 3630
38.6.3 USB Register Descriptions ................................................................................... 3640
39 ► CONNECTIVITY MANAGER (CM) ................................................................................... 3715
39.1 Technical Reference Manual Overview .............................................................................. 3716
40 Connectivity Manager Subsystem ..................................................................................... 3717
40.1 Connectivity Manager Overview....................................................................................... 3718
40.2 Connectivity Manager Functional Block Diagram ................................................................... 3719
40.3 Arm® Cortex®-M4 Processor Core Overview......................................................................... 3720
41 Connectivity Manager - System Control and Interrupts ........................................................ 3721
41.1 Introduction ............................................................................................................... 3722
41.2 Reset ...................................................................................................................... 3722
41.2.1 CPU1 SYSRS.................................................................................................. 3722
41.2.2 System Reset Request (CMSYSRESETREQ) ............................................................ 3722
41.2.3 CM NMI Watchdog Reset (CMNMIWDRSTn) ............................................................ 3722
41.2.4 CM Secure Code Copy Reset (CMSCCRESETn) ........................................................ 3722
41.3 CM Clocking ............................................................................................................. 3723
41.3.1 CM Clock Sources ............................................................................................ 3723
41.3.2 CM Derived Clocks ........................................................................................... 3723
41.3.3 CM Device Clock Domains .................................................................................. 3723
41.3.4 CM Clock Connectivity ....................................................................................... 3725
41.4 SysTick ................................................................................................................... 3725
41.5 Watchdog Timer ......................................................................................................... 3726
41.6 Exceptions and NMI..................................................................................................... 3726
41.6.1 CM Subsystem Nested Vectored Interrupt Controller .................................................... 3726
41.6.2 CM Subsystem Exceptions Handling ....................................................................... 3727
41.6.3 CM Subsystem Non-Maskable Interrupt (CMNMI) Module .............................................. 3729
41.6.4 CM Interrupts/NMI to CPU1/CPU2.......................................................................... 3731
41.7 Nested Vectored Interrupt Controller (NVIC) ........................................................................ 3731
41.7.1 Level-Sensitive and Pulse Interrupts ....................................................................... 3734
41.7.2 Hardware and Software Control of Interrupts ............................................................. 3735
41.7.3 NVIC Registers Access....................................................................................... 3735
41.8 32-Bit CM CPU Timers 0/1/2 .......................................................................................... 3736
41.9 Memory Controller Module ............................................................................................. 3737

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41.9.1 Functional Description ........................................................................................ 3737

41.10 Memory Protection Unit (MPU)........................................................................................ 3743
41.10.1 Functional Description ...................................................................................... 3744
41.10.2 Overlapping Regions ........................................................................................ 3744
41.10.3 Sub-Regions .................................................................................................. 3745
41.10.4 Programmers Model ......................................................................................... 3745
41.11 Debug and Trace ....................................................................................................... 3746
41.11.1 Trace Port Interface Unit .................................................................................... 3746
41.12 CM-SysCtrl Registers .................................................................................................. 3747
41.12.1 CM-SysCtrl Base Addresses ............................................................................... 3747
41.12.2 CM_MEMCFG_REGS Registers .......................................................................... 3748
41.12.3 CM_MEMORYDIAGERROR_REGS Registers .......................................................... 3768
41.12.4 CM_MEMORYERROR_REGS Registers ................................................................ 3772
41.12.5 CMSYSCTL_REGS Registers ............................................................................. 3800
41.12.6 CM_CPUTIMER_REGS Registers ........................................................................ 3825
41.12.7 MPU_REGS Registers ...................................................................................... 3831
41.12.8 CM_NMI_INTRUPT_REGS Registers .................................................................... 3863
41.12.9 NVIC Registers............................................................................................... 3875
41.12.10 SCB Registers .............................................................................................. 3945
41.12.11 CSFR Registers ............................................................................................ 3971
41.12.12 SYSTICK Registers ........................................................................................ 3978
41.12.13 MPU Registers ............................................................................................. 3983
41.12.14 CM_WD_REGS Registers ................................................................................ 4007
42 Advance Encryption Standard (AES) Accelerator ................................................................ 4014
42.1 Introduction ............................................................................................................... 4015
42.2 Features .................................................................................................................. 4016
42.2.1 AES Block Diagram ........................................................................................... 4016
42.2.2 AES Algorithm ................................................................................................. 4019
42.3 AES Operating Modes .................................................................................................. 4020
42.3.1 GCM Operation ................................................................................................ 4020
42.3.2 CCM Operation ................................................................................................ 4021
42.3.3 XTS Operation ................................................................................................. 4022
42.3.4 ECB Feedback Mode ......................................................................................... 4023
42.3.5 CBC Feedback Mode ......................................................................................... 4024
42.3.6 CTR and ICM Feedback Modes ............................................................................ 4025
42.3.7 CFB Mode ...................................................................................................... 4026
42.3.8 F8 Mode ........................................................................................................ 4027
42.3.9 F9 Operation ................................................................................................... 4028
42.3.10 CBC-MAC Operation ........................................................................................ 4029
42.4 Extended and Combined Modes of Operations ..................................................................... 4030
42.4.1 GCM Protocol Operation ..................................................................................... 4030
42.4.2 CCM Protocol Operation ..................................................................................... 4030
42.4.3 Hardware Requests ........................................................................................... 4030
42.5 AES Module Programming Guide ..................................................................................... 4031
42.5.1 AES Low-Level Programming Models ...................................................................... 4031
42.6 AES Registers ........................................................................................................... 4036
42.6.1 AES Base Addresses ......................................................................................... 4036
42.6.2 AES_SS_REGS Registers ................................................................................... 4037
42.6.3 AES_REGS Registers ........................................................................................ 4041
43 Ethernet Media Access Controller (EMAC) ......................................................................... 4084
43.1 Introduction ............................................................................................................... 4085
43.1.1 Standard Compliance ......................................................................................... 4085
43.1.2 MAC Features ................................................................................................. 4085

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43.2 System Level Integration ............................................................................................... 4086

43.2.1 Ethernet Signal Connection and Description .............................................................. 4086
43.2.2 Configuring Device Pins ...................................................................................... 4091
43.2.3 MAC Interface Selection ..................................................................................... 4092
43.2.4 Clocks for Ethernet Module .................................................................................. 4092
43.2.5 RMII Mode Clocking .......................................................................................... 4092
43.2.6 RevMII Mode Clocking ....................................................................................... 4093
43.2.7 Configuring Trigger Sources for Time Stamping .......................................................... 4093
43.2.8 Ethernet Interrupts ............................................................................................ 4094
43.3 Features .................................................................................................................. 4096
43.3.1 Multiple Channels and Queues Support ................................................................... 4096
43.3.2 IEEE 1588 Timestamp Support ............................................................................. 4101
43.3.3 Packet Filtering ................................................................................................ 4115
43.3.4 VLAN Support ................................................................................................. 4123
43.3.5 TCP/IP Offloading Features ................................................................................. 4126
43.3.6 Loopback Mode ............................................................................................... 4142
43.3.7 Reverse Media Independent Interface (RevMII) .......................................................... 4143
43.4 Descriptors ............................................................................................................... 4150
43.4.1 Descriptor Structure ........................................................................................... 4151
43.4.2 Transmit Descriptor .......................................................................................... 4152
43.5 Programming............................................................................................................. 4174
43.5.1 Initializing DMA ................................................................................................ 4174
43.5.2 Initializing MTL Registers .................................................................................... 4175
43.5.3 Initializing MAC ................................................................................................ 4175
43.5.4 Performing Normal Receive and Transmit Operation .................................................... 4176
43.5.5 Stopping and Starting Transmission ........................................................................ 4176
43.5.6 Programming Guidelines for Multi-Channel Multi-Queuing .............................................. 4177
43.6 Ethernet Registers ...................................................................................................... 4185
43.6.1 Ethernet Base Addresses .................................................................................... 4185
43.6.2 ETHERNETSS_REGS Registers ........................................................................... 4186
43.6.3 EMAC_REGS Registers...................................................................................... 4201
44 Generic Cyclic Redundancy Check (GCRC) ........................................................................ 4605
44.1 Generic CRC Overview ................................................................................................. 4606
44.1.1 GCRC Features ............................................................................................... 4606
44.1.2 GCRC Block Diagram ........................................................................................ 4607
44.2 GCRC Functional Description ......................................................................................... 4607
44.2.1 GCRC Polynomials ........................................................................................... 4607
44.2.2 Fixed Polynomial .............................................................................................. 4607
44.2.3 GCRC Data Input ............................................................................................. 4608
44.2.4 GCRC Execution Sequence Flow ........................................................................... 4608
44.2.5 GCRC Transformations ...................................................................................... 4609
44.3 GCRC Registers ......................................................................................................... 4611
44.3.1 GCRC Base Addresses ...................................................................................... 4611
44.3.2 GCRC_REGS Registers ..................................................................................... 4612
45 Modular Controller Area Network (MCAN) .......................................................................... 4619
45.1 MCAN Overview ......................................................................................................... 4620
45.1.1 MCAN Features ............................................................................................... 4620
45.2 MCAN Environment ..................................................................................................... 4622
45.3 CAN Network Basics .................................................................................................... 4622
45.4 MCAN Integration ....................................................................................................... 4624
45.5 MCAN Functional Description ......................................................................................... 4626
45.5.1 Module Clocking Requirements ............................................................................. 4627
45.5.2 Interrupt Requests ............................................................................................ 4627

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45.5.3 Operating Modes .............................................................................................. 4627

45.5.4 Transmitter Delay Compensation ........................................................................... 4631
45.5.5 Restricted Operation Mode .................................................................................. 4632
45.5.6 Bus Monitoring Mode ......................................................................................... 4632
45.5.7 Disabled Automatic Retransmission (DAR) Mode ........................................................ 4633
45.5.8 Clock Stop Mode .............................................................................................. 4633
45.5.9 Test Modes..................................................................................................... 4635
45.5.10 Timestamp Generation ...................................................................................... 4635
45.5.11 Timeout Counter ............................................................................................. 4637
45.5.12 Safety.......................................................................................................... 4637
45.5.13 Rx Handling .................................................................................................. 4638
45.5.14 Rx FIFOs ...................................................................................................... 4642
45.5.15 Dedicated Rx Buffers........................................................................................ 4644
45.5.16 Message RAM ............................................................................................... 4645
45.6 MCAN Registers ......................................................................................................... 4655
45.6.1 MCAN Base Addresses ...................................................................................... 4655
45.6.2 MCAN_REGS Registers ..................................................................................... 4656
45.6.3 MCANSS_REGS Registers .................................................................................. 4733
45.6.4 MCAN_ERROR_REGS Registers .......................................................................... 4745
46 CM Inter-Integrated Circuit (I2C) Interface .......................................................................... 4771
46.1 Introduction ............................................................................................................... 4772
46.2 Features .................................................................................................................. 4772
46.2.1 Block Diagram ................................................................................................. 4773
46.3 Functional Description .................................................................................................. 4773
46.3.1 I2C Bus Functional Overview ................................................................................ 4774
46.3.2 Available Speed Modes ...................................................................................... 4778
46.3.3 Interrupts ....................................................................................................... 4781
46.3.4 Loopback Operation .......................................................................................... 4781
46.3.5 FIFO and µDMA Operation .................................................................................. 4782
46.3.6 Command Sequence Flow Charts .......................................................................... 4784
46.4 Initialization and Configuration......................................................................................... 4791
46.4.1 Configure the I2C Module to Transmit a Single Byte as a Master...................................... 4791
46.4.2 Configure the I2C Master to High Speed Mode ........................................................... 4792
46.5 CM I2C Registers ....................................................................................................... 4792
46.5.1 CM I2C Base Addresses ..................................................................................... 4792
46.5.2 CM_I2C_REGS Registers ................................................................................... 4793
46.5.3 CM_I2C_WRITE_REGS Registers ......................................................................... 4833
47 M3 Synchronous Serial Interface (SSI) ............................................................................... 4838
47.1 Introduction ............................................................................................................... 4839
47.2 Features .................................................................................................................. 4839
47.2.1 SSI Block Diagram ............................................................................................ 4839
47.3 Functional Description .................................................................................................. 4840
47.3.1 Bit Rate Generation ........................................................................................... 4841
47.3.2 FIFO Operation ................................................................................................ 4841
47.3.3 SSInFSS Function ............................................................................................ 4841
47.3.4 Interrupts ....................................................................................................... 4842
47.3.5 Frame Formats ................................................................................................ 4842
47.3.6 DMA Operation ................................................................................................ 4847
47.4 Initialization and Configuration......................................................................................... 4847
47.5 SSI Registers ............................................................................................................ 4849
47.5.1 SSI Base Addresses .......................................................................................... 4849
47.5.2 SSI_REGS Registers ......................................................................................... 4850
48 Universal Asynchronous Receiver/Transmitter (UART) ........................................................ 4881
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48.1 Introduction ............................................................................................................... 4882

48.2 Features .................................................................................................................. 4882
48.2.1 Block Diagram ................................................................................................. 4882
48.3 Functional Description .................................................................................................. 4883
48.3.1 Transmit and Receive Logic ................................................................................. 4883
48.3.2 Baud-Rate Generation ........................................................................................ 4884
48.3.3 Data Transmission ............................................................................................ 4884
48.3.4 Serial IR (SIR) ................................................................................................. 4885
48.3.5 9-Bit UART Mode ............................................................................................. 4886
48.3.6 FIFO Operation ................................................................................................ 4886
48.3.7 Interrupts ....................................................................................................... 4886
48.3.8 Loopback Operation .......................................................................................... 4887
48.3.9 DMA Operation ................................................................................................ 4887
48.4 Initialization and Configuration......................................................................................... 4888
48.5 UART Registers ......................................................................................................... 4889
48.5.1 UART Base Addresses ....................................................................................... 4889
48.5.2 UART_REGS Registers ...................................................................................... 4890
48.5.3 UART_REGS_WRITE Registers ............................................................................ 4929
49 Micro Direct Memory Access (µDMA) ................................................................................ 4931
49.1 Introduction ............................................................................................................... 4932
49.2 µDMA Block Diagram ................................................................................................... 4933
49.3 Functional Description .................................................................................................. 4933
49.3.1 Channel Assignments ........................................................................................ 4934
49.3.2 Priority .......................................................................................................... 4935
49.3.3 Arbitration Size ................................................................................................ 4935
49.3.4 Request Types ................................................................................................ 4935
49.3.5 Channel Configuration ........................................................................................ 4936
49.3.6 Transfer Modes ................................................................................................ 4938
49.3.7 Transfer Size and Increment ................................................................................ 4945
49.3.8 Peripheral Interface ........................................................................................... 4945
49.3.9 Software Request ............................................................................................. 4946
49.3.10 Interrupts and Errors ........................................................................................ 4946
49.4 Initialization and Configuration......................................................................................... 4946
49.4.1 Module Initialization ........................................................................................... 4946
49.4.2 Configuring a Memory-to-Memory Transfer ............................................................... 4947
49.4.3 Configuring a Peripheral for Simple Transmit ............................................................. 4948
49.4.4 Configuring a Peripheral for Ping-Pong Receive.......................................................... 4950
49.4.5 Configuring Channel Assignments .......................................................................... 4952
49.5 µDMA Registers ......................................................................................................... 4952
49.5.1 µDMA Base Addresses ....................................................................................... 4952
49.5.2 UDMAREGS Registers ....................................................................................... 4953
49.5.3 UDMACHDES Registers ..................................................................................... 4984
Revision History ...................................................................................................................... 4990

SPRUII0B – May 2019 – Revised May 2020 Contents 25

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List of Figures
1-1. F2838x Block Diagram ................................................................................................... 154
3-1. Device Interrupt Architecture ............................................................................................ 164
3-2. Interrupt Propagation Path............................................................................................... 165
3-3. System Error and CM Status Interrupt Sources ...................................................................... 170
3-4. Missing Clock Detection Logic .......................................................................................... 180
3-5. ERRORSTS Pin Diagram ............................................................................................... 182
3-6. Clocking System .......................................................................................................... 183
3-7. Single-ended 3.3V External Clock ...................................................................................... 184
3-8. External Crystal ........................................................................................................... 185
3-9. External Resonator ....................................................................................................... 185
3-10. AUXCLKIN ................................................................................................................. 186
3-11. PLL/AUXPLL .............................................................................................................. 190
3-12. Clock Configuration Semaphore (CLKSEM) State Transitions ..................................................... 193
3-13. CPU-Timers ............................................................................................................... 194
3-14. CPU-Timer Interrupts Signals and Output Signal .................................................................... 194
3-15. CPU Watchdog Timer Module ......................................................................................... 195
3-16. Memory Architecture ..................................................................................................... 199
3-17. Arbitration Scheme on Global Shared Memories ..................................................................... 202
3-18. Arbitration Scheme on Local Shared Memories ...................................................................... 202
3-19. ROM Parity Checking Logic ............................................................................................. 208
3-20. CLKSEM Register ........................................................................................................ 213
3-21. CLKCFGLOCK1 Register ................................................................................................ 214
3-22. CLKSRCCTL1 Register .................................................................................................. 217
3-23. CLKSRCCTL2 Register .................................................................................................. 219
3-24. CLKSRCCTL3 Register .................................................................................................. 221
3-25. SYSPLLCTL1 Register ................................................................................................... 222
3-26. SYSPLLMULT Register .................................................................................................. 223
3-27. SYSPLLSTS Register .................................................................................................... 225
3-28. AUXPLLCTL1 Register .................................................................................................. 226
3-29. AUXPLLMULT Register .................................................................................................. 227
3-30. AUXPLLSTS Register .................................................................................................... 229
3-31. SYSCLKDIVSEL Register ............................................................................................... 230
3-32. AUXCLKDIVSEL Register ............................................................................................... 231
3-33. PERCLKDIVSEL Register ............................................................................................... 232
3-34. XCLKOUTDIVSEL Register ............................................................................................. 233
3-35. CLBCLKCTL Register .................................................................................................... 234
3-36. LOSPCP Register ........................................................................................................ 236
3-37. MCDCR Register ......................................................................................................... 237
3-38. X1CNT Register........................................................................................................... 238
3-39. XTALCR Register ......................................................................................................... 239
3-40. ETHERCATCLKCTL Register........................................................................................... 240
3-41. CMCLKCTL Register ..................................................................................................... 241
3-42. CMRESCTL Register..................................................................................................... 243
3-43. CMTOCPU1NMICTL Register .......................................................................................... 244
3-44. CMTOCPU1INTCTL Register ........................................................................................... 245
3-45. PALLOCATE0 Register .................................................................................................. 246
3-46. CM_CONF_REGS_LOCK Register .................................................................................... 247

26 List of Figures SPRUII0B – May 2019 – Revised May 2020

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3-47. NMAVFLG Register ...................................................................................................... 250

3-48. NMAVSET Register ...................................................................................................... 251
3-49. NMAVCLR Register ...................................................................................................... 252
3-50. NMAVINTEN Register.................................................................................................... 253
3-51. NMCPURDAVADDR Register .......................................................................................... 254
3-52. NMCPUWRAVADDR Register .......................................................................................... 255
3-53. NMCPUFAVADDR Register ............................................................................................. 256
3-54. NMDMAWRAVADDR Register ......................................................................................... 257
3-55. NMCLA1RDAVADDR Register ......................................................................................... 258
3-56. NMCLA1WRAVADDR Register ......................................................................................... 259
3-57. NMCLA1FAVADDR Register............................................................................................ 260
3-58. NMDMARDAVADDR Register .......................................................................................... 261
3-59. MAVFLG Register ........................................................................................................ 262
3-60. MAVSET Register ........................................................................................................ 263
3-61. MAVCLR Register ........................................................................................................ 264
3-62. MAVINTEN Register ..................................................................................................... 265
3-63. MCPUFAVADDR Register............................................................................................... 266
3-64. MCPUWRAVADDR Register ............................................................................................ 267
3-65. MDMAWRAVADDR Register ........................................................................................... 268
3-66. CPUSYSLOCK1 Register ............................................................................................... 271
3-67. CPUSYSLOCK2 Register ............................................................................................... 274
3-68. PIEVERRADDR Register ................................................................................................ 275
3-69. PCLKCR0 Register ....................................................................................................... 276
3-70. PCLKCR1 Register ....................................................................................................... 278
3-71. PCLKCR2 Register ....................................................................................................... 279
3-72. PCLKCR3 Register ....................................................................................................... 281
3-73. PCLKCR4 Register ....................................................................................................... 282
3-74. PCLKCR6 Register ....................................................................................................... 283
3-75. PCLKCR7 Register ....................................................................................................... 284
3-76. PCLKCR8 Register ....................................................................................................... 285
3-77. PCLKCR9 Register ....................................................................................................... 286
3-78. PCLKCR10 Register ..................................................................................................... 287
3-79. PCLKCR11 Register ..................................................................................................... 288
3-80. PCLKCR13 Register ..................................................................................................... 289
3-81. PCLKCR14 Register ..................................................................................................... 290
3-82. PCLKCR16 Register ..................................................................................................... 292
3-83. PCLKCR17 Register ..................................................................................................... 293
3-84. PCLKCR18 Register ..................................................................................................... 294
3-85. PCLKCR20 Register ..................................................................................................... 296
3-86. PCLKCR21 Register ..................................................................................................... 297
3-87. PCLKCR22 Register ..................................................................................................... 298
3-88. PCLKCR23 Register ..................................................................................................... 299
3-89. SIMRESET Register ...................................................................................................... 300
3-90. LPMCR Register .......................................................................................................... 301
3-91. GPIOLPMSEL0 Register................................................................................................. 302
3-92. GPIOLPMSEL1 Register................................................................................................. 305
3-93. TMR2CLKCTL Register .................................................................................................. 308
3-94. RESCCLR Register....................................................................................................... 309
3-95. RESC Register ............................................................................................................ 311

SPRUII0B – May 2019 – Revised May 2020 List of Figures 27

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3-96. CPUID Register ........................................................................................................... 314

3-97. ADCA_AC Register ....................................................................................................... 318
3-98. ADCB_AC Register ....................................................................................................... 319
3-99. ADCC_AC Register....................................................................................................... 320
3-100. ADCD_AC Register....................................................................................................... 321
3-101. CMPSS1_AC Register ................................................................................................... 322
3-102. CMPSS2_AC Register ................................................................................................... 323
3-103. CMPSS3_AC Register ................................................................................................... 324
3-104. CMPSS4_AC Register ................................................................................................... 325
3-105. CMPSS5_AC Register ................................................................................................... 326
3-106. CMPSS6_AC Register ................................................................................................... 327
3-107. CMPSS7_AC Register ................................................................................................... 328
3-108. CMPSS8_AC Register ................................................................................................... 329
3-109. DACA_AC Register ....................................................................................................... 330
3-110. DACB_AC Register ....................................................................................................... 331
3-111. DACC_AC Register....................................................................................................... 332
3-112. EPWM1_AC Register .................................................................................................... 333
3-113. EPWM2_AC Register .................................................................................................... 334
3-114. EPWM3_AC Register .................................................................................................... 335
3-115. EPWM4_AC Register .................................................................................................... 336
3-116. EPWM5_AC Register .................................................................................................... 337
3-117. EPWM6_AC Register .................................................................................................... 338
3-118. EPWM7_AC Register .................................................................................................... 339
3-119. EPWM8_AC Register .................................................................................................... 340
3-120. EPWM9_AC Register .................................................................................................... 341
3-121. EPWM10_AC Register ................................................................................................... 342
3-122. EPWM11_AC Register ................................................................................................... 343
3-123. EPWM12_AC Register ................................................................................................... 344
3-124. EPWM13_AC Register ................................................................................................... 345
3-125. EPWM14_AC Register ................................................................................................... 346
3-126. EPWM15_AC Register ................................................................................................... 347
3-127. EPWM16_AC Register ................................................................................................... 348
3-128. EQEP1_AC Register ..................................................................................................... 349
3-129. EQEP2_AC Register ..................................................................................................... 350
3-130. EQEP3_AC Register ..................................................................................................... 351
3-131. ECAP1_AC Register ..................................................................................................... 352
3-132. ECAP2_AC Register ..................................................................................................... 353
3-133. ECAP3_AC Register ..................................................................................................... 354
3-134. ECAP4_AC Register ..................................................................................................... 355
3-135. ECAP5_AC Register ..................................................................................................... 356
3-136. ECAP6_AC Register ..................................................................................................... 357
3-137. ECAP7_AC Register ..................................................................................................... 358
3-138. SDFM1_AC Register ..................................................................................................... 359
3-139. SDFM2_AC Register ..................................................................................................... 360
3-140. CLB1_AC Register ....................................................................................................... 361
3-141. CLB2_AC Register ....................................................................................................... 362
3-142. CLB3_AC Register ....................................................................................................... 363
3-143. CLB4_AC Register ....................................................................................................... 364
3-144. SPIA_AC Register ........................................................................................................ 365

28 List of Figures SPRUII0B – May 2019 – Revised May 2020

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3-145. SPIB_AC Register ........................................................................................................ 366

3-146. SPIC_AC Register ........................................................................................................ 367
3-147. SPID_AC Register ........................................................................................................ 368
3-148. PMBUS_A_AC Register ................................................................................................. 369
3-149. CAN_A_AC Register ..................................................................................................... 370
3-150. CAN_B_AC Register ..................................................................................................... 371
3-151. MCBSPA_AC Register ................................................................................................... 372
3-152. MCBSPB_AC Register ................................................................................................... 373
3-153. USBA_AC Register ....................................................................................................... 374
3-154. HRPWM_AC Register .................................................................................................... 375
3-155. ETHERCAT_AC Register ................................................................................................ 377
3-156. FSIATX_AC Register ..................................................................................................... 378
3-157. FSIARX_AC Register .................................................................................................... 379
3-158. FSIBTX_AC Register ..................................................................................................... 380
3-159. FSIBRX_AC Register .................................................................................................... 381
3-160. FSICRX_AC Register .................................................................................................... 382
3-161. FSIDRX_AC Register .................................................................................................... 383
3-162. FSIERX_AC Register .................................................................................................... 384
3-163. FSIFRX_AC Register..................................................................................................... 385
3-164. FSIGRX_AC Register .................................................................................................... 386
3-165. FSIHRX_AC Register .................................................................................................... 387
3-166. PERIPH_AC_LOCK Register ........................................................................................... 388
3-167. TIM Register ............................................................................................................... 390
3-168. PRD Register .............................................................................................................. 391
3-169. TCR Register .............................................................................................................. 392
3-170. TPR Register .............................................................................................................. 394
3-171. TPRH Register ............................................................................................................ 395
3-172. DEVCFGLOCK1 Register ............................................................................................... 398
3-173. DEVCFGLOCK2 Register ............................................................................................... 400
3-174. PARTIDL Register ........................................................................................................ 401
3-175. PARTIDH Register........................................................................................................ 402
3-176. REVID Register ........................................................................................................... 403
3-177. PERCNF1 Register ....................................................................................................... 404
3-178. FUSEERR Register....................................................................................................... 405
3-179. SOFTPRES0 Register ................................................................................................... 406
3-180. SOFTPRES1 Register ................................................................................................... 407
3-181. SOFTPRES2 Register ................................................................................................... 408
3-182. SOFTPRES3 Register ................................................................................................... 410
3-183. SOFTPRES4 Register ................................................................................................... 411
3-184. SOFTPRES6 Register ................................................................................................... 412
3-185. SOFTPRES7 Register ................................................................................................... 413
3-186. SOFTPRES8 Register ................................................................................................... 414
3-187. SOFTPRES9 Register ................................................................................................... 415
3-188. SOFTPRES10 Register .................................................................................................. 416
3-189. SOFTPRES11 Register .................................................................................................. 417
3-190. SOFTPRES13 Register .................................................................................................. 418
3-191. SOFTPRES14 Register .................................................................................................. 419
3-192. SOFTPRES16 Register .................................................................................................. 420
3-193. SOFTPRES17 Register .................................................................................................. 421

SPRUII0B – May 2019 – Revised May 2020 List of Figures 29

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3-194. SOFTPRES18 Register .................................................................................................. 422

3-195. SOFTPRES20 Register .................................................................................................. 424
3-196. SOFTPRES21 Register .................................................................................................. 425
3-197. SOFTPRES23 Register .................................................................................................. 426
3-198. CPUSEL0 Register ....................................................................................................... 427
3-199. CPUSEL1 Register ....................................................................................................... 429
3-200. CPUSEL2 Register ....................................................................................................... 430
3-201. CPUSEL4 Register ....................................................................................................... 431
3-202. CPUSEL5 Register ....................................................................................................... 432
3-203. CPUSEL6 Register ....................................................................................................... 433
3-204. CPUSEL7 Register ....................................................................................................... 434
3-205. CPUSEL8 Register ....................................................................................................... 435
3-206. CPUSEL9 Register ....................................................................................................... 436
3-207. CPUSEL11 Register ...................................................................................................... 437
3-208. CPUSEL12 Register ...................................................................................................... 438
3-209. CPUSEL14 Register ...................................................................................................... 439
3-210. CPUSEL15 Register ...................................................................................................... 440
3-211. CPUSEL16 Register ...................................................................................................... 441
3-212. CPUSEL18 Register ...................................................................................................... 443
3-213. CPUSEL25 Register ...................................................................................................... 444
3-214. CPU2RESCTL Register.................................................................................................. 445
3-215. RSTSTAT Register ....................................................................................................... 446
3-216. LPMSTAT Register ....................................................................................................... 447
3-217. USBTYPE Register ....................................................................................................... 448
3-218. ECAPTYPE Register ..................................................................................................... 449
3-219. SDFMTYPE Register ..................................................................................................... 450
3-220. MEMMAPTYPE Register ................................................................................................ 451
3-221. CLA1TASKSRCSELLOCK Register ................................................................................... 453
3-222. DMACHSRCSELLOCK Register ....................................................................................... 454
3-223. CLA1TASKSRCSEL1 Register ......................................................................................... 455
3-224. CLA1TASKSRCSEL2 Register ......................................................................................... 456
3-225. DMACHSRCSEL1 Register ............................................................................................. 457
3-226. DMACHSRCSEL2 Register ............................................................................................. 458
3-227. DxLOCK Register ......................................................................................................... 461
3-228. DxCOMMIT Register ..................................................................................................... 462
3-229. DxACCPROT0 Register ................................................................................................. 463
3-230. DxTEST Register ......................................................................................................... 465
3-231. DxINIT Register ........................................................................................................... 466
3-232. DxINITDONE Register ................................................................................................... 467
3-233. DxRAMTEST_LOCK Register .......................................................................................... 468
3-234. LSxLOCK Register ....................................................................................................... 469
3-235. LSxCOMMIT Register .................................................................................................... 471
3-236. LSxMSEL Register ....................................................................................................... 473
3-237. LSxCLAPGM Register ................................................................................................... 475
3-238. LSxACCPROT0 Register ................................................................................................ 476
3-239. LSxACCPROT1 Register ................................................................................................ 478
3-240. LSxTEST Register ........................................................................................................ 480
3-241. LSxINIT Register .......................................................................................................... 482
3-242. LSxINITDONE Register .................................................................................................. 483

30 List of Figures SPRUII0B – May 2019 – Revised May 2020

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3-243. LSxRAMTEST_LOCK Register ......................................................................................... 484

3-244. GSxLOCK Register ....................................................................................................... 485
3-245. GSxCOMMIT Register ................................................................................................... 487
3-246. GSxMSEL Register ....................................................................................................... 490
3-247. GSxACCPROT0 Register ............................................................................................... 492
3-248. GSxACCPROT1 Register ............................................................................................... 494
3-249. GSxACCPROT2 Register ............................................................................................... 496
3-250. GSxACCPROT3 Register ............................................................................................... 498
3-251. GSxTEST Register ....................................................................................................... 500
3-252. GSxINIT Register ......................................................................................................... 504
3-253. GSxINITDONE Register ................................................................................................. 506
3-254. GSxRAMTEST_LOCK Register ........................................................................................ 508
3-255. MSGxLOCK Register..................................................................................................... 510
3-256. MSGxCOMMIT Register ................................................................................................. 512
3-257. MSGxACCPROT0 Register ............................................................................................. 514
3-258. MSGxACCPROT1 Register ............................................................................................. 515
3-259. MSGxACCPROT2 Register ............................................................................................. 516
3-260. MSGxTEST Register ..................................................................................................... 517
3-261. MSGxINIT Register ....................................................................................................... 519
3-262. MSGxINITDONE Register ............................................................................................... 520
3-263. MSGxRAMTEST_LOCK Register ...................................................................................... 522
3-264. ROM_LOCK Register .................................................................................................... 524
3-265. ROM_TEST Register ..................................................................................................... 525
3-266. ROM_FORCE_ERROR Register ....................................................................................... 526
3-267. PERI_MEM_TEST_LOCK Register .................................................................................... 527
3-268. PERI_MEM_TEST_CONTROL Register .............................................................................. 528
3-269. UCERRFLG Register..................................................................................................... 531
3-270. UCERRSET Register..................................................................................................... 532
3-271. UCERRCLR Register .................................................................................................... 533
3-272. UCCPUREADDR Register .............................................................................................. 534
3-273. UCDMAREADDR Register .............................................................................................. 535
3-274. UCCLA1READDR Register ............................................................................................. 536
3-275. UCECATRAMADDR Register ........................................................................................... 537
3-276. CERRFLG Register....................................................................................................... 538
3-277. CERRSET Register....................................................................................................... 539
3-278. CERRCLR Register ...................................................................................................... 540
3-279. CCPUREADDR Register ................................................................................................ 541
3-280. CCLA1READDR Register ............................................................................................... 542
3-281. CERRCNT Register ...................................................................................................... 543
3-282. CERRTHRES Register ................................................................................................... 544
3-283. CEINTFLG Register ...................................................................................................... 545
3-284. CEINTCLR Register ...................................................................................................... 546
3-285. CEINTSET Register ...................................................................................................... 547
3-286. CEINTEN Register........................................................................................................ 548
3-287. NMICFG Register ......................................................................................................... 550
3-288. NMIFLG Register ......................................................................................................... 551
3-289. NMIFLGCLR Register .................................................................................................... 553
3-290. NMIFLGFRC Register .................................................................................................... 556
3-291. NMIWDCNT Register .................................................................................................... 558

SPRUII0B – May 2019 – Revised May 2020 List of Figures 31

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3-292. NMIWDPRD Register .................................................................................................... 559

3-293. NMISHDFLG Register.................................................................................................... 560
3-294. ERRORSTS Register .................................................................................................... 563
3-295. ERRORSTSCLR Register ............................................................................................... 564
3-296. ERRORSTSFRC Register ............................................................................................... 565
3-297. ERRORCTL Register..................................................................................................... 566
3-298. ERRORLOCK Register .................................................................................................. 567
3-299. PIECTRL Register ........................................................................................................ 570
3-300. PIEACK Register.......................................................................................................... 571
3-301. PIEIER1 Register ......................................................................................................... 572
3-302. PIEIFR1 Register ......................................................................................................... 573
3-303. PIEIER2 Register ......................................................................................................... 575
3-304. PIEIFR2 Register ......................................................................................................... 576
3-305. PIEIER3 Register ......................................................................................................... 578
3-306. PIEIFR3 Register ......................................................................................................... 579
3-307. PIEIER4 Register ......................................................................................................... 581
3-308. PIEIFR4 Register ......................................................................................................... 582
3-309. PIEIER5 Register ......................................................................................................... 584
3-310. PIEIFR5 Register ......................................................................................................... 585
3-311. PIEIER6 Register ......................................................................................................... 587
3-312. PIEIFR6 Register ......................................................................................................... 588
3-313. PIEIER7 Register ......................................................................................................... 590
3-314. PIEIFR7 Register ......................................................................................................... 591
3-315. PIEIER8 Register ......................................................................................................... 593
3-316. PIEIFR8 Register ......................................................................................................... 594
3-317. PIEIER9 Register ......................................................................................................... 596
3-318. PIEIFR9 Register ......................................................................................................... 597
3-319. PIEIER10 Register........................................................................................................ 599
3-320. PIEIFR10 Register ........................................................................................................ 600
3-321. PIEIER11 Register........................................................................................................ 602
3-322. PIEIFR11 Register ........................................................................................................ 603
3-323. PIEIER12 Register........................................................................................................ 605
3-324. PIEIFR12 Register ........................................................................................................ 606
3-325. ROMPREFETCH Register............................................................................................... 609
3-326. ROMWAITSTATE Register .............................................................................................. 611
3-327. SYNCSELECT Register ................................................................................................. 613
3-328. ADCSOCOUTSELECT Register ........................................................................................ 614
3-329. SYNCSOCLOCK Register ............................................................................................... 617
3-330. CM_STATUS_INT_FLG Register ...................................................................................... 619
3-331. CM_STATUS_INT_CLR Register ...................................................................................... 620
3-332. CM_STATUS_INT_SET Register ...................................................................................... 621
3-333. CM_STATUS_MASK Register .......................................................................................... 622
3-334. SYS_ERR_INT_FLG Register .......................................................................................... 623
3-335. SYS_ERR_INT_CLR Register .......................................................................................... 625
3-336. SYS_ERR_INT_SET Register .......................................................................................... 627
3-337. SYS_ERR_MASK Register .............................................................................................. 629
3-338. CPU_RAM_TEST_ERROR_STS Register ............................................................................ 632
3-339. CPU_RAM_TEST_ERROR_STS_CLR Register ..................................................................... 633
3-340. CPU_RAM_TEST_ERROR_ADDR Register ......................................................................... 634

32 List of Figures SPRUII0B – May 2019 – Revised May 2020

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3-341. UID_PSRAND0 Register................................................................................................. 636

3-342. UID_PSRAND1 Register................................................................................................. 637
3-343. UID_PSRAND2 Register................................................................................................. 638
3-344. UID_PSRAND3 Register................................................................................................. 639
3-345. UID_PSRAND4 Register................................................................................................. 640
3-346. UID_PSRAND5 Register................................................................................................. 641
3-347. UID_UNIQUE Register ................................................................................................... 642
3-348. UID_CHECKSUM Register .............................................................................................. 643
3-349. SCSR Register ............................................................................................................ 645
3-350. WDCNTR Register ....................................................................................................... 646
3-351. WDKEY Register.......................................................................................................... 647
3-352. WDCR Register ........................................................................................................... 648
3-353. WDWCR Register ........................................................................................................ 650
3-354. XINT1CR Register ........................................................................................................ 652
3-355. XINT2CR Register ........................................................................................................ 653
3-356. XINT3CR Register ........................................................................................................ 654
3-357. XINT4CR Register ........................................................................................................ 655
3-358. XINT5CR Register ........................................................................................................ 656
3-359. XINT1CTR Register ...................................................................................................... 657
3-360. XINT2CTR Register ...................................................................................................... 658
3-361. XINT3CTR Register ...................................................................................................... 659
5-1. CPU1 Device Boot Flow ................................................................................................. 687
5-2. CPU1 Emulation Boot Flow ............................................................................................. 688
5-3. CPU1 Standalone Boot Flow ............................................................................................ 689
5-4. CPU2 Boot Flow .......................................................................................................... 690
5-5. CM Boot Flow ............................................................................................................. 691
5-6. Overview of SCI Bootloader Operation ................................................................................ 706
5-7. Overview of SCI Boot Function ......................................................................................... 707
5-8. SPI Loader ................................................................................................................. 708
5-9. Data Transfer From EEPROM Flow .................................................................................... 710
5-10. EEPROM Device at Address 0x50 ..................................................................................... 710
5-11. Overview of I2C Boot Function ......................................................................................... 711
5-12. Random Read ............................................................................................................. 712
5-13. Sequential Read .......................................................................................................... 712
5-14. Overview of Parallel GPIO Bootloader Operation .................................................................... 713
5-15. Parallel GPIO Bootloader Handshake Protocol ....................................................................... 714
5-16. Parallel GPIO Mode Overview .......................................................................................... 714
5-17. Parallel GPIO Mode - Host Transfer Flow ............................................................................. 715
5-18. 8-Bit Parallel GetWord Function ........................................................................................ 716
5-19. Overview of CAN-A Bootloader Operation ............................................................................ 717
5-20. USB Boot Flow ............................................................................................................ 719
6-1. Storage of Zone-Select Bits in OTP .................................................................................... 742
6-2. Location of Zone-Select Block Based on Link-Pointer ............................................................... 743
6-3. CSM Password Match Flow (PMF) ..................................................................................... 748
6-4. ECSL Password Match Flow (PMF) .................................................................................... 750
6-5. ..........................................................................................................
FLSEM Register 754
6-6. SECTSTAT1 Register .................................................................................................... 755
6-7. SECTSTAT2 Register .................................................................................................... 757
6-8. SECTSTAT3 Register .................................................................................................... 759

SPRUII0B – May 2019 – Revised May 2020 List of Figures 33

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6-9. RAMSTAT1 Register ..................................................................................................... 761

6-10. RAMSTAT2 Register ..................................................................................................... 763
6-11. RAMSTAT3 Register ..................................................................................................... 766
6-12. SECERRSTAT Register ................................................................................................. 768
6-13. SECERRCLR Register ................................................................................................... 769
6-14. SECERRFRC Register ................................................................................................... 770
6-15. Z1OTP_LINKPOINTER1 Register ...................................................................................... 772
6-16. Z1OTP_LINKPOINTER2 Register ...................................................................................... 773
6-17. Z1OTP_LINKPOINTER3 Register ...................................................................................... 774
6-18. Z1OTP_JLM_ENABLE Register ........................................................................................ 775
6-19. Z1OTP_GPREG1 Register .............................................................................................. 776
6-20. Z1OTP_GPREG2 Register .............................................................................................. 777
6-21. Z1OTP_GPREG3 Register .............................................................................................. 778
6-22. Z1OTP_GPREG4 Register .............................................................................................. 779
6-23. Z1OTP_PSWDLOCK Register .......................................................................................... 780
6-24. Z1OTP_CRCLOCK Register ............................................................................................ 781
6-25. Z1OTP_JTAGPSWDH0 Register ....................................................................................... 782
6-26. Z1OTP_JTAGPSWDH1 Register ....................................................................................... 783
6-27. Z1OTP_CMACKEY0 Register .......................................................................................... 784
6-28. Z1OTP_CMACKEY1 Register .......................................................................................... 785
6-29. Z1OTP_CMACKEY2 Register .......................................................................................... 786
6-30. Z1OTP_CMACKEY3 Register .......................................................................................... 787
6-31. Z1_LINKPOINTER Register ............................................................................................. 790
6-32. Z1_OTPSECLOCK Register ............................................................................................ 791
6-33. Z1_JLM_ENABLE Register.............................................................................................. 792
6-34. Z1_LINKPOINTERERR Register ....................................................................................... 793
6-35. Z1_GPREG1 Register.................................................................................................... 794
6-36. Z1_GPREG2 Register.................................................................................................... 795
6-37. Z1_GPREG3 Register.................................................................................................... 796
6-38. Z1_GPREG4 Register.................................................................................................... 797
6-39. Z1_CSMKEY0 Register .................................................................................................. 798
6-40. Z1_CSMKEY1 Register .................................................................................................. 799
6-41. Z1_CSMKEY2 Register .................................................................................................. 800
6-42. Z1_CSMKEY3 Register .................................................................................................. 801
6-43. Z1_CR Register ........................................................................................................... 802
6-44. Z1_GRABSECT1R Register ............................................................................................ 803
6-45. Z1_GRABSECT2R Register ............................................................................................ 806
6-46. Z1_GRABSECT3R Register ............................................................................................ 809
6-47. Z1_GRABRAM1R Register .............................................................................................. 812
6-48. Z1_GRABRAM2R Register .............................................................................................. 814
6-49. Z1_GRABRAM3R Register .............................................................................................. 817
6-50. Z1_EXEONLYSECT1R Register ....................................................................................... 819
6-51. Z1_EXEONLYSECT2R Register ....................................................................................... 823
6-52. Z1_EXEONLYRAM1R Register......................................................................................... 826
6-53. Z1_JTAGKEY0 Register ................................................................................................. 830
6-54. Z1_JTAGKEY1 Register ................................................................................................. 831
6-55. Z1_JTAGKEY2 Register ................................................................................................. 832
6-56. Z1_JTAGKEY3 Register ................................................................................................. 833
6-57. Z1_CMACKEY0 Register ................................................................................................ 834

34 List of Figures SPRUII0B – May 2019 – Revised May 2020

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6-58. Z1_CMACKEY1 Register ................................................................................................ 835

6-59. Z1_CMACKEY2 Register ................................................................................................ 836
6-60. Z1_CMACKEY3 Register ................................................................................................ 837
6-61. Z2OTP_LINKPOINTER1 Register ...................................................................................... 839
6-62. Z2OTP_LINKPOINTER2 Register ...................................................................................... 840
6-63. Z2OTP_LINKPOINTER3 Register ...................................................................................... 841
6-64. Z2OTP_GPREG1 Register .............................................................................................. 842
6-65. Z2OTP_GPREG2 Register .............................................................................................. 843
6-66. Z2OTP_GPREG3 Register .............................................................................................. 844
6-67. Z2OTP_GPREG4 Register .............................................................................................. 845
6-68. Z2OTP_PSWDLOCK Register .......................................................................................... 846
6-69. Z2OTP_CRCLOCK Register ............................................................................................ 847
6-70. Z2_LINKPOINTER Register ............................................................................................. 850
6-71. Z2_OTPSECLOCK Register ............................................................................................ 851
6-72. Z2_LINKPOINTERERR Register ....................................................................................... 852
6-73. Z2_GPREG1 Register.................................................................................................... 853
6-74. Z2_GPREG2 Register.................................................................................................... 854
6-75. Z2_GPREG3 Register.................................................................................................... 855
6-76. Z2_GPREG4 Register.................................................................................................... 856
6-77. Z2_CSMKEY0 Register .................................................................................................. 857
6-78. Z2_CSMKEY1 Register .................................................................................................. 858
6-79. Z2_CSMKEY2 Register .................................................................................................. 859
6-80. Z2_CSMKEY3 Register .................................................................................................. 860
6-81. Z2_CR Register ........................................................................................................... 861
6-82. Z2_GRABSECT1R Register ............................................................................................ 862
6-83. Z2_GRABSECT2R Register ............................................................................................ 865
6-84. Z2_GRABSECT3R Register ............................................................................................ 868
6-85. Z2_GRABRAM1R Register .............................................................................................. 871
6-86. Z2_GRABRAM2R Register .............................................................................................. 873
6-87. Z2_GRABRAM3R Register .............................................................................................. 876
6-88. Z2_EXEONLYSECT1R Register ....................................................................................... 878
6-89. Z2_EXEONLYSECT2R Register ....................................................................................... 882
6-90. Z2_EXEONLYRAM1R Register......................................................................................... 885
7-1. BGCRC Memory Map .................................................................................................... 891
7-2. BGCRC Block Diagram .................................................................................................. 891
7-3. BGCRC NMI ............................................................................................................... 893
7-4. BGCRC Interrupt .......................................................................................................... 893
7-5. BGCRC Execution Sequence Flow .................................................................................... 895
7-6. BGCRC Execution Sequence Example ................................................................................ 896
7-7. BGCRC Golden Value ................................................................................................... 897
7-8. BGCRC_EN Register .................................................................................................... 901
7-9. BGCRC_CTRL1 Register ................................................................................................ 902
7-10. BGCRC_CTRL2 Register ................................................................................................ 903
7-11. BGCRC_START_ADDR Register ...................................................................................... 904
7-12. BGCRC_SEED Register ................................................................................................. 905
7-13. BGCRC_GOLDEN Register ............................................................................................. 906
7-14. BGCRC_RESULT Register.............................................................................................. 907
7-15. BGCRC_CURR_ADDR Register ....................................................................................... 908
7-16. BGCRC_WD_CFG Register ............................................................................................ 909

SPRUII0B – May 2019 – Revised May 2020 List of Figures 35

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7-17. BGCRC_WD_MIN Register ............................................................................................. 910

7-18. BGCRC_WD_MAX Register ............................................................................................ 911
7-19. BGCRC_WD_CNT Register ............................................................................................. 912
7-20. BGCRC_NMIFLG Register .............................................................................................. 913
7-21. BGCRC_NMICLR Register .............................................................................................. 914
7-22. BGCRC_NMIFRC Register .............................................................................................. 915
7-23. BGCRC_INTEN Register ................................................................................................ 916
7-24. BGCRC_INTFLG Register............................................................................................... 917
7-25. BGCRC_INTCLR Register .............................................................................................. 919
7-26. BGCRC_INTFRC Register .............................................................................................. 920
7-27. BGCRC_LOCK Register ................................................................................................. 921
7-28. BGCRC_COMMIT Register ............................................................................................. 923
8-1. CLA (Type 2) Block Diagram ............................................................................................ 927
8-2. _MVECTBGRNDACTIVE Register ................................................................................... 1065
8-3. _MPSACTL Register .................................................................................................... 1066
8-4. _MPSA1 Register ....................................................................................................... 1067
8-5. _MPSA2 Register ....................................................................................................... 1068
8-6. SOFTINTEN Register ................................................................................................... 1069
8-7. SOFTINTFRC Register ................................................................................................. 1070
8-8. MVECT1 Register ....................................................................................................... 1073
8-9. MVECT2 Register ....................................................................................................... 1074
8-10. MVECT3 Register ....................................................................................................... 1075
8-11. MVECT4 Register ....................................................................................................... 1076
8-12. MVECT5 Register ....................................................................................................... 1077
8-13. MVECT6 Register ....................................................................................................... 1078
8-14. MVECT7 Register ....................................................................................................... 1079
8-15. MVECT8 Register ....................................................................................................... 1080
8-16. MCTL Register........................................................................................................... 1081
8-17. _MVECTBGRNDACTIVE Register ................................................................................... 1082
8-18. SOFTINTEN Register ................................................................................................... 1083
8-19. _MSTSBGRND Register ............................................................................................... 1084
8-20. _MCTLBGRND Register ............................................................................................... 1085
8-21. _MVECTBGRND Register ............................................................................................. 1086
8-22. MIFR Register ........................................................................................................... 1087
8-23. MIOVF Register ......................................................................................................... 1091
8-24. MIFRC Register ......................................................................................................... 1094
8-25. MICLR Register.......................................................................................................... 1096
8-26. MICLROVF Register .................................................................................................... 1098
8-27. MIER Register ........................................................................................................... 1100
8-28. MIRUN Register ......................................................................................................... 1103
8-29. _MPC Register .......................................................................................................... 1105
8-30. _MAR0 Register ......................................................................................................... 1106
8-31. _MAR1 Register ......................................................................................................... 1107
8-32. _MSTF Register ......................................................................................................... 1108
8-33. _MR0 Register ........................................................................................................... 1110
8-34. _MR1 Register ........................................................................................................... 1111
8-35. _MR2 Register ........................................................................................................... 1112
8-36. _MR3 Register ........................................................................................................... 1113
8-37. _MPSACTL Register .................................................................................................... 1114

36 List of Figures SPRUII0B – May 2019 – Revised May 2020

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8-38. _MPSA1 Register ....................................................................................................... 1115

8-39. _MPSA2 Register ....................................................................................................... 1116
8-40. SOFTINTEN Register ................................................................................................... 1118
8-41. SOFTINTFRC Register ................................................................................................. 1119
9-1. Block Diagram of the CLB Subsystem in the Device ............................................................... 1121
9-2. Block Diagram of a CLB Tile and CPU Interface ................................................................... 1122
9-3. CLB Clock Prescalar .................................................................................................... 1123
9-4. CLB Input Mux and Filter ............................................................................................... 1124
9-5. GPIO to CLB Tile Connections ........................................................................................ 1133
9-6. CLB Outputs ............................................................................................................. 1134
9-7. Peripheral Signal Multiplexer .......................................................................................... 1140
9-8. CLB Tile Submodules................................................................................................... 1141
9-9. Counter Block ............................................................................................................ 1144
9-10. LFSR Modes ............................................................................................................. 1147
9-11. FSM Block ................................................................................................................ 1148
9-12. FSM LUT Block .......................................................................................................... 1149
9-13. LUT4 Block ............................................................................................................... 1149
9-14. Output LUT Block ....................................................................................................... 1150
9-15. AOC Block................................................................................................................ 1151
9-16. AOC Block and The CLB TILE ........................................................................................ 1152
9-17. High Level Controller Block ............................................................................................ 1153
9-18. CLB_COUNT_RESET Register ....................................................................................... 1163
9-19. CLB_COUNT_MODE_1 Register ..................................................................................... 1164
9-20. CLB_COUNT_MODE_0 Register ..................................................................................... 1165
9-21. CLB_COUNT_EVENT Register ....................................................................................... 1166
9-22. CLB_FSM_EXTRA_IN0 Register ..................................................................................... 1167
9-23. CLB_FSM_EXTERNAL_IN0 Register ................................................................................ 1168
9-24. CLB_FSM_EXTERNAL_IN1 Register ................................................................................ 1169
9-25. CLB_FSM_EXTRA_IN1 Register ..................................................................................... 1170
9-26. CLB_LUT4_IN0 Register ............................................................................................... 1171
9-27. CLB_LUT4_IN1 Register ............................................................................................... 1172
9-28. CLB_LUT4_IN2 Register ............................................................................................... 1173
9-29. CLB_LUT4_IN3 Register ............................................................................................... 1174
9-30. CLB_FSM_LUT_FN1_0 Register ..................................................................................... 1175
9-31. CLB_FSM_LUT_FN2 Register ........................................................................................ 1176
9-32. CLB_LUT4_FN1_0 Register ........................................................................................... 1177
9-33. CLB_LUT4_FN2 Register .............................................................................................. 1178
9-34. CLB_FSM_NEXT_STATE_0 Register................................................................................ 1179
9-35. CLB_FSM_NEXT_STATE_1 Register................................................................................ 1180
9-36. CLB_FSM_NEXT_STATE_2 Register................................................................................ 1181
9-37. CLB_MISC_CONTROL Register ...................................................................................... 1182
9-38. CLB_OUTPUT_LUT_0 Register ...................................................................................... 1185
9-39. CLB_OUTPUT_LUT_1 Register ...................................................................................... 1186
9-40. CLB_OUTPUT_LUT_2 Register ...................................................................................... 1187
9-41. CLB_OUTPUT_LUT_3 Register ...................................................................................... 1188
9-42. CLB_OUTPUT_LUT_4 Register ...................................................................................... 1189
9-43. CLB_OUTPUT_LUT_5 Register ...................................................................................... 1190
9-44. CLB_OUTPUT_LUT_6 Register ...................................................................................... 1191
9-45. CLB_OUTPUT_LUT_7 Register ...................................................................................... 1192

SPRUII0B – May 2019 – Revised May 2020 List of Figures 37

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9-46. CLB_HLC_EVENT_SEL Register ..................................................................................... 1193

9-47. CLB_COUNT_MATCH_TAP_SEL Register ......................................................................... 1194
9-48. CLB_OUTPUT_COND_CTRL_0 Register ........................................................................... 1195
9-49. CLB_OUTPUT_COND_CTRL_1 Register ........................................................................... 1197
9-50. CLB_OUTPUT_COND_CTRL_2 Register ........................................................................... 1199
9-51. CLB_OUTPUT_COND_CTRL_3 Register ........................................................................... 1201
9-52. CLB_OUTPUT_COND_CTRL_4 Register ........................................................................... 1203
9-53. CLB_OUTPUT_COND_CTRL_5 Register ........................................................................... 1205
9-54. CLB_OUTPUT_COND_CTRL_6 Register ........................................................................... 1207
9-55. CLB_OUTPUT_COND_CTRL_7 Register ........................................................................... 1209
9-56. CLB_MISC_ACCESS_CTRL Register ............................................................................... 1211
9-57. CLB_SPI_DATA_CTRL_HI Register ................................................................................. 1212
9-58. CLB_LOAD_EN Register............................................................................................... 1215
9-59. CLB_LOAD_ADDR Register ........................................................................................... 1216
9-60. CLB_LOAD_DATA Register ........................................................................................... 1217
9-61. CLB_INPUT_FILTER Register ........................................................................................ 1218
9-62. CLB_IN_MUX_SEL_0 Register ....................................................................................... 1220
9-63. CLB_LCL_MUX_SEL_1 Register ..................................................................................... 1222
9-64. CLB_LCL_MUX_SEL_2 Register ..................................................................................... 1223
9-65. CLB_BUF_PTR Register ............................................................................................... 1224
9-66. CLB_GP_REG Register ................................................................................................ 1225
9-67. CLB_OUT_EN Register ................................................................................................ 1226
9-68. CLB_GLBL_MUX_SEL_1 Register ................................................................................... 1227
9-69. CLB_GLBL_MUX_SEL_2 Register ................................................................................... 1228
9-70. CLB_PRESCALE_CTRL Register .................................................................................... 1229
9-71. CLB_INTR_TAG_REG Register ...................................................................................... 1230
9-72. CLB_LOCK Register .................................................................................................... 1231
9-73. CLB_HLC_INSTR_READ_PTR Register ............................................................................ 1232
9-74. CLB_HLC_INSTR_VALUE Register .................................................................................. 1233
9-75. CLB_DBG_OUT_2 Register ........................................................................................... 1234
9-76. CLB_DBG_R0 Register ................................................................................................ 1235
9-77. CLB_DBG_R1 Register ................................................................................................ 1236
9-78. CLB_DBG_R2 Register ................................................................................................ 1237
9-79. CLB_DBG_R3 Register ................................................................................................ 1238
9-80. CLB_DBG_C0 Register ................................................................................................ 1239
9-81. CLB_DBG_C1 Register ................................................................................................ 1240
9-82. CLB_DBG_C2 Register ................................................................................................ 1241
9-83. CLB_DBG_OUT Register .............................................................................................. 1242
9-84. CLB_PUSH_y Register ................................................................................................. 1245
9-85. CLB_PULL_y Register.................................................................................................. 1246
10-1. DCC Operation .......................................................................................................... 1251
10-2. Counter Relationship.................................................................................................... 1254
10-3. Clock1 Slower Than Clock0 - Results in an Error and Stops Counting .......................................... 1255
10-4. Clock1 Faster Than Clock0 - Results in an Error and Stops Counting .......................................... 1255
10-5. Clock1 Not Present - Results in an Error and Stops Counting .................................................... 1256
10-6. Clock0 Not Present - Results in an Error and Stops Counting .................................................... 1256
10-7. DCCGCTRL Register ................................................................................................... 1259
10-8. DCCCNTSEED0 Register .............................................................................................. 1260
10-9. DCCVALIDSEED0 Register ........................................................................................... 1261

38 List of Figures SPRUII0B – May 2019 – Revised May 2020

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10-10. DCCCNTSEED1 Register .............................................................................................. 1262

10-11. DCCSTATUS Register ................................................................................................. 1263
10-12. DCCCNT0 Register ..................................................................................................... 1264
10-13. DCCVALID0 Register ................................................................................................... 1265
10-14. DCCCNT1 Register ..................................................................................................... 1266
10-15. DCCCLKSRC1 Register ................................................................................................ 1267
10-16. DCCCLKSRC0 Register ................................................................................................ 1268
11-1. DMA Block Diagram .................................................................................................... 1272
11-2. DMA Trigger Architecture .............................................................................................. 1274
11-3. Peripheral Interrupt Trigger Input Diagram .......................................................................... 1275
11-4. DMA State Diagram ..................................................................................................... 1283
11-5. 3-Stage Pipeline DMA Transfer ....................................................................................... 1284
11-6. 3-stage Pipeline With One Read Stall ................................................................................ 1284
11-7. Overrun Detection Logic................................................................................................ 1287
11-8. DMACTRL Register ..................................................................................................... 1289
11-9. DEBUGCTRL Register ................................................................................................. 1290
11-10. PRIORITYCTRL1 Register ............................................................................................. 1291
11-11. PRIORITYSTAT Register .............................................................................................. 1292
11-12. MODE Register .......................................................................................................... 1295
11-13. CONTROL Register ..................................................................................................... 1297
11-14. BURST_SIZE Register ................................................................................................. 1299
11-15. BURST_COUNT Register .............................................................................................. 1300
11-16. SRC_BURST_STEP Register ......................................................................................... 1301
11-17. DST_BURST_STEP Register ......................................................................................... 1302
11-18. TRANSFER_SIZE Register ............................................................................................ 1303
11-19. TRANSFER_COUNT Register ........................................................................................ 1304
11-20. SRC_TRANSFER_STEP Register .................................................................................... 1305
11-21. DST_TRANSFER_STEP Register .................................................................................... 1306
11-22. SRC_WRAP_SIZE Register ........................................................................................... 1307
11-23. SRC_WRAP_COUNT Register........................................................................................ 1308
11-24. SRC_WRAP_STEP Register .......................................................................................... 1309
11-25. DST_WRAP_SIZE Register ........................................................................................... 1310
11-26. DST_WRAP_COUNT Register ........................................................................................ 1311
11-27. DST_WRAP_STEP Register .......................................................................................... 1312
11-28. SRC_BEG_ADDR_SHADOW Register .............................................................................. 1313
11-29. SRC_ADDR_SHADOW Register ..................................................................................... 1314
11-30. SRC_BEG_ADDR_ACTIVE Register ................................................................................. 1315
11-31. SRC_ADDR_ACTIVE Register ........................................................................................ 1316
11-32. DST_BEG_ADDR_SHADOW Register............................................................................... 1317
11-33. DST_ADDR_SHADOW Register ...................................................................................... 1318
11-34. DST_BEG_ADDR_ACTIVE Register ................................................................................. 1319
11-35. DST_ADDR_ACTIVE Register ........................................................................................ 1320
12-1. EMIF Module Overview ................................................................................................. 1324
12-2. EMIF Functional Block Diagram ....................................................................................... 1326
12-3. Timing Waveform of SDRAM PRE Command ...................................................................... 1330
12-4. EMIF to 2M × 16 × 4 bank SDRAM Interface ....................................................................... 1330
12-5. EMIF to 512K × 16 × 2 bank SDRAM Interface ..................................................................... 1331
12-6. Timing Waveform for Basic SDRAM Read Operation .............................................................. 1338
12-7. Timing Waveform for Basic SDRAM Write Operation .............................................................. 1339

SPRUII0B – May 2019 – Revised May 2020 List of Figures 39

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12-8. EMIF Asynchronous Interface ......................................................................................... 1341

12-9. EMIF to 8-bit/16-bit Memory Interface ................................................................................ 1342
12-10. Common Asynchronous Interface ..................................................................................... 1342
12-11. Timing Waveform of an Asynchronous Read Cycle in Normal Mode ............................................ 1346
12-12. Timing Waveform of an Asynchronous Write Cycle in Normal Mode ............................................ 1348
12-13. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode .................................... 1350
12-14. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode ..................................... 1352
12-15. Example Configuration Interface ...................................................................................... 1359
12-16. SDRAM Timing Register (SDRAM_TR) .............................................................................. 1360
12-17. SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) .................................................. 1361
12-18. SDRAM Refresh Control Register (SDRAM_RCR) ................................................................. 1362
12-19. SDRAM Configuration Register (SDRAM_CR)...................................................................... 1362
12-20. LH28F800BJE-PTTL90 to EMIF Read Timing Waveforms ........................................................ 1363
12-21. LH28F800BJE-PTTL90 to EMIF Write Timing Waveforms ........................................................ 1364
12-22. Asynchronous m Configuration Register (m = 1, 2) (ASYNC_CSn_CR(n = 2, 3)) ............................. 1365
12-23. RCSR Register .......................................................................................................... 1368
12-24. ASYNC_WCCR Register ............................................................................................... 1369
12-25. SDRAM_CR Register ................................................................................................... 1370
12-26. SDRAM_RCR Register ................................................................................................. 1372
12-27. ASYNC_CS2_CR Register ............................................................................................ 1373
12-28. ASYNC_CS3_CR Register ............................................................................................ 1375
12-29. ASYNC_CS4_CR Register ............................................................................................ 1377
12-30. SDRAM_TR Register ................................................................................................... 1379
12-31. TOTAL_SDRAM_AR Register ......................................................................................... 1380
12-32. TOTAL_SDRAM_ACTR Register ..................................................................................... 1381
12-33. SDR_EXT_TMNG Register ............................................................................................ 1382
12-34. INT_RAW Register ...................................................................................................... 1383
12-35. INT_MSK Register ...................................................................................................... 1384
12-36. INT_MSK_SET Register ............................................................................................... 1385
12-37. INT_MSK_CLR Register ............................................................................................... 1386
12-38. EMIF1LOCK Register ................................................................................................... 1388
12-39. EMIF1COMMIT Register ............................................................................................... 1389
12-40. EMIF1MSEL Register ................................................................................................... 1390
12-41. EMIF1ACCPROT0 Register ........................................................................................... 1391
12-42. EMIF2LOCK Register ................................................................................................... 1393
12-43. EMIF2COMMIT Register ............................................................................................... 1394
12-44. EMIF2ACCPROT0 Register ........................................................................................... 1395
13-1. FMC Interface with Core, Bank and Pump .......................................................................... 1400
13-2. Flash Prefetch Mode .................................................................................................... 1404
13-3. Flash Cache Mode ...................................................................................................... 1407
13-4. ECC Logic Inputs and Outputs ........................................................................................ 1410
13-5. Flash Pump Semaphore (PUMPREQUEST) States and State Transitions ..................................... 1414
13-6. FRDCNTL Register ..................................................................................................... 1417
13-7. FBAC Register ........................................................................................................... 1418
13-8. FBFALLBACK Register ................................................................................................. 1419
13-9. FBPRDY Register ....................................................................................................... 1420
13-10. FPAC1 Register ......................................................................................................... 1421
13-11. FMSTAT Register ....................................................................................................... 1422
13-12. FRD_INTF_CTRL Register ............................................................................................ 1424

40 List of Figures SPRUII0B – May 2019 – Revised May 2020

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13-13. ECC_ENABLE Register ................................................................................................ 1427

13-14. SINGLE_ERR_ADDR_LOW Register ................................................................................ 1428
13-15. SINGLE_ERR_ADDR_HIGH Register ............................................................................... 1429
13-16. UNC_ERR_ADDR_LOW Register .................................................................................... 1430
13-17. UNC_ERR_ADDR_HIGH Register ................................................................................... 1431
13-18. ERR_STATUS Register ................................................................................................ 1432
13-19. ERR_POS Register ..................................................................................................... 1434
13-20. ERR_STATUS_CLR Register ......................................................................................... 1435
13-21. ERR_CNT Register ..................................................................................................... 1436
13-22. ERR_THRESHOLD Register .......................................................................................... 1437
13-23. ERR_INTFLG Register ................................................................................................. 1438
13-24. ERR_INTCLR Register ................................................................................................. 1439
13-25. FDATAH_TEST Register ............................................................................................... 1440
13-26. FDATAL_TEST Register ............................................................................................... 1441
13-27. FADDR_TEST Register ................................................................................................ 1442
13-28. FECC_TEST Register .................................................................................................. 1443
13-29. FECC_CTRL Register .................................................................................................. 1444
13-30. FOUTH_TEST Register ................................................................................................ 1445
13-31. FOUTL_TEST Register ................................................................................................. 1446
13-32. FECC_STATUS Register .............................................................................................. 1447
13-33. FRDCNTL Register ..................................................................................................... 1449
13-34. FBAC Register ........................................................................................................... 1450
13-35. FBFALLBACK Register ................................................................................................. 1451
13-36. FBPRDY Register ....................................................................................................... 1452
13-37. FPAC1 Register ......................................................................................................... 1453
13-38. FMSTAT Register ....................................................................................................... 1454
13-39. FRD_INTF_CTRL_LOCK Register ................................................................................... 1456
13-40. FRD_INTF_CTRL Register ............................................................................................ 1457
13-41. ECC_ENABLE Register ................................................................................................ 1460
13-42. SINGLE_ERR_ADDR_LOW Register ................................................................................ 1461
13-43. SINGLE_ERR_ADDR_HIGH Register ............................................................................... 1462
13-44. UNC_ERR_ADDR_LOW Register .................................................................................... 1463
13-45. UNC_ERR_ADDR_HIGH Register ................................................................................... 1464
13-46. ERR_STATUS Register ................................................................................................ 1465
13-47. ERR_POS Register ..................................................................................................... 1467
13-48. ERR_STATUS_CLR Register ......................................................................................... 1468
13-49. ERR_CNT Register ..................................................................................................... 1469
13-50. ERR_THRESHOLD Register .......................................................................................... 1470
13-51. ERR_INTFLG Register ................................................................................................. 1471
13-52. ERR_INTCLR Register ................................................................................................. 1472
13-53. FDATAH_TEST Register ............................................................................................... 1473
13-54. FDATAL_TEST Register ............................................................................................... 1474
13-55. FADDR_TEST Register ................................................................................................ 1475
13-56. FECC_TEST Register .................................................................................................. 1476
13-57. FECC_CTRL Register .................................................................................................. 1477
13-58. FOUTH_TEST Register ................................................................................................ 1478
13-59. FOUTL_TEST Register ................................................................................................. 1479
13-60. FECC_STATUS Register .............................................................................................. 1480
13-61. FLASH_ECC_REGS_LOCK Register ................................................................................ 1481

SPRUII0B – May 2019 – Revised May 2020 List of Figures 41

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13-62. PUMPREQUEST Register ............................................................................................. 1483

14-1. ERAD Overview ......................................................................................................... 1487
14-2. EBC Units Event Masking .............................................................................................. 1489
14-3. System Event Counter Inputs ......................................................................................... 1491
14-4. Event Masking and Exporting for CRC Qualifiers ................................................................... 1497
14-5. GLBL_EVENT_STAT Register ........................................................................................ 1501
14-6. GLBL_HALT_STAT Register .......................................................................................... 1503
14-7. GLBL_ENABLE Register ............................................................................................... 1505
14-8. GLBL_CTM_RESET Register ......................................................................................... 1507
14-9. GLBL_NMI_CTL Register .............................................................................................. 1508
14-10. GLBL_OWNER Register ............................................................................................... 1510
14-11. GLBL_EVENT_AND_MASK Register ................................................................................ 1511
14-12. GLBL_EVENT_OR_MASK Register .................................................................................. 1515
14-13. GLBL_AND_EVENT_INT_MASK Register .......................................................................... 1519
14-14. GLBL_OR_EVENT_INT_MASK Register ............................................................................ 1520
14-15. HWBP_MASK Register ................................................................................................. 1522
14-16. HWBP_REF Register ................................................................................................... 1523
14-17. HWBP_CLEAR Register ............................................................................................... 1524
14-18. HWBP_CNTL Register ................................................................................................. 1525
14-19. HWBP_STATUS Register .............................................................................................. 1527
14-20. CTM_CNTL Register.................................................................................................... 1529
14-21. CTM_STATUS Register ................................................................................................ 1531
14-22. CTM_REF Register ..................................................................................................... 1532
14-23. CTM_COUNT Register ................................................................................................. 1533
14-24. CTM_MAX_COUNT Register .......................................................................................... 1534
14-25. CTM_INPUT_SEL Register ............................................................................................ 1535
14-26. CTM_CLEAR Register.................................................................................................. 1536
14-27. CTM_INPUT_SEL_2 Register ......................................................................................... 1537
14-28. CTM_INPUT_COND Register ......................................................................................... 1538
14-29. CRC_GLOBAL_CTRL Register ....................................................................................... 1540
14-30. CRC_CURRENT Register ............................................................................................. 1543
14-31. CRC_SEED Register ................................................................................................... 1544
14-32. CRC_QUALIFIER Register ............................................................................................ 1545
15-1. GPIO Logic for a Single Pin ........................................................................................... 1547
15-2. Input Qualification Using a Sampling Window ....................................................................... 1551
15-3. Input Qualifier Clock Cycles ........................................................................................... 1553
15-4. GPACTRL Register ..................................................................................................... 1568
15-5. GPAQSEL1 Register.................................................................................................... 1569
15-6. GPAQSEL2 Register.................................................................................................... 1570
15-7. GPAMUX1 Register ..................................................................................................... 1571
15-8. GPAMUX2 Register ..................................................................................................... 1572
15-9. GPADIR Register........................................................................................................ 1573
15-10. GPAPUD Register....................................................................................................... 1575
15-11. GPAINV Register ........................................................................................................ 1577
15-12. GPAODR Register ...................................................................................................... 1579
15-13. GPAGMUX1 Register ................................................................................................... 1581
15-14. GPAGMUX2 Register ................................................................................................... 1582
15-15. GPACSEL1 Register .................................................................................................... 1583
15-16. GPACSEL2 Register .................................................................................................... 1584

42 List of Figures SPRUII0B – May 2019 – Revised May 2020

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15-17. GPACSEL3 Register .................................................................................................... 1585

15-18. GPACSEL4 Register .................................................................................................... 1586
15-19. GPALOCK Register ..................................................................................................... 1587
15-20. GPACR Register ........................................................................................................ 1589
15-21. GPBCTRL Register ..................................................................................................... 1591
15-22. GPBQSEL1 Register.................................................................................................... 1592
15-23. GPBQSEL2 Register.................................................................................................... 1593
15-24. GPBMUX1 Register ..................................................................................................... 1594
15-25. GPBMUX2 Register ..................................................................................................... 1595
15-26. GPBDIR Register........................................................................................................ 1596
15-27. GPBPUD Register....................................................................................................... 1598
15-28. GPBINV Register ........................................................................................................ 1600
15-29. GPBODR Register ...................................................................................................... 1602
15-30. GPBAMSEL Register ................................................................................................... 1604
15-31. GPBGMUX1 Register ................................................................................................... 1605
15-32. GPBGMUX2 Register ................................................................................................... 1606
15-33. GPBCSEL1 Register .................................................................................................... 1607
15-34. GPBCSEL2 Register .................................................................................................... 1608
15-35. GPBCSEL3 Register .................................................................................................... 1609
15-36. GPBCSEL4 Register .................................................................................................... 1610
15-37. GPBLOCK Register ..................................................................................................... 1611
15-38. GPBCR Register ........................................................................................................ 1613
15-39. GPCCTRL Register ..................................................................................................... 1615
15-40. GPCQSEL1 Register ................................................................................................... 1616
15-41. GPCQSEL2 Register ................................................................................................... 1617
15-42. GPCMUX1 Register..................................................................................................... 1618
15-43. GPCMUX2 Register..................................................................................................... 1619
15-44. GPCDIR Register ....................................................................................................... 1620
15-45. GPCPUD Register ...................................................................................................... 1622
15-46. GPCINV Register........................................................................................................ 1624
15-47. GPCODR Register ...................................................................................................... 1626
15-48. GPCGMUX1 Register .................................................................................................. 1628
15-49. GPCGMUX2 Register .................................................................................................. 1629
15-50. GPCCSEL1 Register.................................................................................................... 1630
15-51. GPCCSEL2 Register.................................................................................................... 1631
15-52. GPCCSEL3 Register.................................................................................................... 1632
15-53. GPCCSEL4 Register.................................................................................................... 1633
15-54. GPCLOCK Register ..................................................................................................... 1634
15-55. GPCCR Register ........................................................................................................ 1636
15-56. GPDCTRL Register ..................................................................................................... 1638
15-57. GPDQSEL1 Register ................................................................................................... 1639
15-58. GPDQSEL2 Register ................................................................................................... 1641
15-59. GPDMUX1 Register..................................................................................................... 1643
15-60. GPDMUX2 Register..................................................................................................... 1645
15-61. GPDDIR Register ....................................................................................................... 1647
15-62. GPDPUD Register ...................................................................................................... 1649
15-63. GPDINV Register........................................................................................................ 1651
15-64. GPDODR Register ...................................................................................................... 1653
15-65. GPDGMUX1 Register .................................................................................................. 1655

SPRUII0B – May 2019 – Revised May 2020 List of Figures 43

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15-66. GPDGMUX2 Register .................................................................................................. 1657

15-67. GPDCSEL1 Register.................................................................................................... 1659
15-68. GPDCSEL2 Register.................................................................................................... 1660
15-69. GPDCSEL3 Register.................................................................................................... 1661
15-70. GPDCSEL4 Register.................................................................................................... 1662
15-71. GPDLOCK Register ..................................................................................................... 1663
15-72. GPDCR Register ........................................................................................................ 1665
15-73. GPECTRL Register ..................................................................................................... 1667
15-74. GPEQSEL1 Register.................................................................................................... 1668
15-75. GPEQSEL2 Register.................................................................................................... 1670
15-76. GPEMUX1 Register ..................................................................................................... 1672
15-77. GPEMUX2 Register ..................................................................................................... 1674
15-78. GPEDIR Register........................................................................................................ 1676
15-79. GPEPUD Register....................................................................................................... 1678
15-80. GPEINV Register ........................................................................................................ 1680
15-81. GPEODR Register ...................................................................................................... 1682
15-82. GPEGMUX1 Register ................................................................................................... 1684
15-83. GPEGMUX2 Register ................................................................................................... 1686
15-84. GPECSEL1 Register .................................................................................................... 1688
15-85. GPECSEL2 Register .................................................................................................... 1689
15-86. GPECSEL3 Register .................................................................................................... 1690
15-87. GPECSEL4 Register .................................................................................................... 1691
15-88. GPELOCK Register ..................................................................................................... 1692
15-89. GPECR Register ........................................................................................................ 1694
15-90. GPFCTRL Register ..................................................................................................... 1696
15-91. GPFQSEL1 Register .................................................................................................... 1697
15-92. GPFMUX1 Register ..................................................................................................... 1698
15-93. GPFDIR Register ........................................................................................................ 1699
15-94. GPFPUD Register ....................................................................................................... 1700
15-95. GPFINV Register ........................................................................................................ 1701
15-96. GPFODR Register ...................................................................................................... 1702
15-97. GPFGMUX1 Register ................................................................................................... 1703
15-98. GPFCSEL1 Register .................................................................................................... 1704
15-99. GPFCSEL2 Register .................................................................................................... 1705
15-100. GPFLOCK Register .................................................................................................... 1706
15-101. GPFCR Register ....................................................................................................... 1707
15-102. GPADAT Register ..................................................................................................... 1710
15-103. GPASET Register...................................................................................................... 1712
15-104. GPACLEAR Register .................................................................................................. 1714
15-105. GPATOGGLE Register ................................................................................................ 1716
15-106. GPBDAT Register ..................................................................................................... 1718
15-107. GPBSET Register...................................................................................................... 1720
15-108. GPBCLEAR Register .................................................................................................. 1722
15-109. GPBTOGGLE Register ................................................................................................ 1724
15-110. GPCDAT Register ..................................................................................................... 1726
15-111. GPCSET Register ..................................................................................................... 1728
15-112. GPCCLEAR Register .................................................................................................. 1730
15-113. GPCTOGGLE Register ............................................................................................... 1732
15-114. GPDDAT Register ..................................................................................................... 1734

44 List of Figures SPRUII0B – May 2019 – Revised May 2020

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15-115. GPDSET Register ..................................................................................................... 1736

15-116. GPDCLEAR Register .................................................................................................. 1738
15-117. GPDTOGGLE Register ............................................................................................... 1740
15-118. GPEDAT Register ..................................................................................................... 1742
15-119. GPESET Register...................................................................................................... 1744
15-120. GPECLEAR Register .................................................................................................. 1746
15-121. GPETOGGLE Register ................................................................................................ 1748
15-122. GPFDAT Register ...................................................................................................... 1750
15-123. GPFSET Register ...................................................................................................... 1751
15-124. GPFCLEAR Register .................................................................................................. 1752
15-125. GPFTOGGLE Register ................................................................................................ 1753
15-126. GPADAT_R Register .................................................................................................. 1755
15-127. GPBDAT_R Register .................................................................................................. 1756
15-128. GPCDAT_R Register .................................................................................................. 1757
15-129. GPDDAT_R Register .................................................................................................. 1758
15-130. GPEDAT_R Register .................................................................................................. 1759
15-131. GPFDAT_R Register .................................................................................................. 1760
16-1. CPU1_TO_CPU2 IPC Module ......................................................................................... 1769
16-2. CPUx_to_CM IPC Module ............................................................................................. 1770
16-3. CPU1TOCPU2IPCACK Register ...................................................................................... 1776
16-4. CPU2TOCPU1IPCSTS Register ...................................................................................... 1778
16-5. CPU1TOCPU2IPCSET Register ...................................................................................... 1782
16-6. CPU1TOCPU2IPCCLR Register ...................................................................................... 1786
16-7. CPU1TOCPU2IPCFLG Register ...................................................................................... 1790
16-8. IPCCOUNTERL Register............................................................................................... 1794
16-9. IPCCOUNTERH Register .............................................................................................. 1795
16-10. CPU1TOCPU2IPCSENDCOM Register ............................................................................. 1796
16-11. CPU1TOCPU2IPCSENDADDR Register ............................................................................ 1797
16-12. CPU1TOCPU2IPCSENDDATA Register............................................................................. 1798
16-13. CPU2TOCPU1IPCREPLY Register .................................................................................. 1799
16-14. CPU2TOCPU1IPCRECVCOM Register ............................................................................. 1800
16-15. CPU2TOCPU1IPCRECVADDR Register ............................................................................ 1801
16-16. CPU2TOCPU1IPCRECVDATA Register............................................................................. 1802
16-17. CPU1TOCPU2IPCREPLY Register .................................................................................. 1803
16-18. CPU2TOCPU1IPCBOOTSTS Register .............................................................................. 1804
16-19. CPU1TOCPU2IPCBOOTMODE Register............................................................................ 1805
16-20. PUMPREQUEST Register ............................................................................................. 1806
16-21. CPU2TOCPU1IPCACK Register ...................................................................................... 1809
16-22. CPU1TOCPU2IPCSTS Register ...................................................................................... 1811
16-23. CPU2TOCPU1IPCSET Register ...................................................................................... 1815
16-24. CPU2TOCPU1IPCCLR Register ...................................................................................... 1819
16-25. CPU2TOCPU1IPCFLG Register ...................................................................................... 1823
16-26. IPCCOUNTERL Register............................................................................................... 1827
16-27. IPCCOUNTERH Register .............................................................................................. 1828
16-28. CPU1TOCPU2IPCRECVCOM Register ............................................................................. 1829
16-29. CPU1TOCPU2IPCRECVADDR Register ............................................................................ 1830
16-30. CPU1TOCPU2IPCRECVDATA Register............................................................................. 1831
16-31. CPU2TOCPU1IPCREPLY Register .................................................................................. 1832
16-32. CPU2TOCPU1IPCSENDCOM Register ............................................................................. 1833

SPRUII0B – May 2019 – Revised May 2020 List of Figures 45

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16-33. CPU2TOCPU1IPCSENDADDR Register ............................................................................ 1834

16-34. CPU2TOCPU1IPCSENDDATA Register............................................................................. 1835
16-35. CPU1TOCPU2IPCREPLY Register .................................................................................. 1836
16-36. CPU2TOCPU1IPCBOOTSTS Register .............................................................................. 1837
16-37. CPU1TOCPU2IPCBOOTMODE Register............................................................................ 1838
16-38. PUMPREQUEST Register ............................................................................................. 1839
16-39. CPU1TOCMIPCACK Register ......................................................................................... 1842
16-40. CMTOCPU1IPCSTS Register ......................................................................................... 1844
16-41. CPU1TOCMIPCSET Register ......................................................................................... 1848
16-42. CPU1TOCMIPCCLR Register ......................................................................................... 1852
16-43. CPU1TOCMIPCFLG Register ......................................................................................... 1856
16-44. IPCCOUNTERL Register............................................................................................... 1860
16-45. IPCCOUNTERH Register .............................................................................................. 1861
16-46. CPU1TOCMIPCSENDCOM Register ................................................................................ 1862
16-47. CPU1TOCMIPCSENDADDR Register ............................................................................... 1863
16-48. CPU1TOCMIPCSENDDATA Register................................................................................ 1864
16-49. CMTOCPU1IPCREPLY Register ..................................................................................... 1865
16-50. CMTOCPU1IPCRECVCOM Register ................................................................................ 1866
16-51. CMTOCPU1IPCRECVADDR Register ............................................................................... 1867
16-52. CMTOCPU1IPCRECVDATA Register................................................................................ 1868
16-53. CPU1TOCMIPCREPLY Register ..................................................................................... 1869
16-54. CMTOCPU1IPCBOOTSTS Register ................................................................................. 1870
16-55. CPU1TOCMIPCBOOTMODE Register............................................................................... 1871
16-56. CMTOCPU1IPCACK Register ......................................................................................... 1874
16-57. CPU1TOCMIPCSTS Register ......................................................................................... 1876
16-58. CMTOCPU1IPCSET Register ......................................................................................... 1880
16-59. CMTOCPU1IPCCLR Register ......................................................................................... 1884
16-60. CMTOCPU1IPCFLG Register ......................................................................................... 1888
16-61. IPCCOUNTERL Register............................................................................................... 1892
16-62. IPCCOUNTERH Register .............................................................................................. 1893
16-63. CPU1TOCMIPCRECVCOM Register ................................................................................ 1894
16-64. CPU1TOCMIPCRECVADDR Register ............................................................................... 1895
16-65. CPU1TOCMIPCRECVDATA Register................................................................................ 1896
16-66. CMTOCPU1IPCREPLY Register ..................................................................................... 1897
16-67. CMTOCPU1IPCSENDCOM Register ................................................................................ 1898
16-68. CMTOCPU1IPCSENDADDR Register ............................................................................... 1899
16-69. CMTOCPU1IPCSENDDATA Register................................................................................ 1900
16-70. CPU1TOCMIPCREPLY Register ..................................................................................... 1901
16-71. CMTOCPU1IPCBOOTSTS Register ................................................................................. 1902
16-72. CPU1TOCMIPCBOOTMODE Register............................................................................... 1903
16-73. PUMPREQUEST Register ............................................................................................. 1904
16-74. CPU2TOCMIPCACK Register ......................................................................................... 1906
16-75. CMTOCPU2IPCSTS Register ......................................................................................... 1908
16-76. CPU2TOCMIPCSET Register ......................................................................................... 1912
16-77. CPU2TOCMIPCCLR Register ......................................................................................... 1916
16-78. CPU2TOCMIPCFLG Register ......................................................................................... 1920
16-79. IPCCOUNTERL Register............................................................................................... 1924
16-80. IPCCOUNTERH Register .............................................................................................. 1925
16-81. CPU2TOCMIPCSENDCOM Register ................................................................................ 1926

46 List of Figures SPRUII0B – May 2019 – Revised May 2020

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16-82. CPU2TOCMIPCSENDADDR Register ............................................................................... 1927

16-83. CPU2TOCMIPCSENDDATA Register................................................................................ 1928
16-84. CMTOCPU2IPCREPLY Register ..................................................................................... 1929
16-85. CMTOCPU2IPCRECVCOM Register ................................................................................ 1930
16-86. CMTOCPU2IPCRECVADDR Register ............................................................................... 1931
16-87. CMTOCPU2IPCRECVDATA Register................................................................................ 1932
16-88. CPU2TOCMIPCREPLY Register ..................................................................................... 1933
16-89. CMTOCPU2IPCACK Register ......................................................................................... 1935
16-90. CPU2TOCMIPCSTS Register ......................................................................................... 1937
16-91. CMTOCPU2IPCSET Register ......................................................................................... 1941
16-92. CMTOCPU2IPCCLR Register ......................................................................................... 1945
16-93. CMTOCPU2IPCFLG Register ......................................................................................... 1949
16-94. IPCCOUNTERL Register............................................................................................... 1953
16-95. IPCCOUNTERH Register .............................................................................................. 1954
16-96. CPU2TOCMIPCRECVCOM Register ................................................................................ 1955
16-97. CPU2TOCMIPCRECVADDR Register ............................................................................... 1956
16-98. CPU2TOCMIPCRECVDATA Register................................................................................ 1957
16-99. CMTOCPU2IPCREPLY Register ..................................................................................... 1958
16-100. CMTOCPU2IPCSENDCOM Register ............................................................................... 1959
16-101. CMTOCPU2IPCSENDADDR Register .............................................................................. 1960
16-102. CMTOCPU2IPCSENDDATA Register .............................................................................. 1961
16-103. CPU2TOCMIPCREPLY Register .................................................................................... 1962
17-1. Input X-BAR .............................................................................................................. 1965
17-2. ePWM X-BAR Architecture - Single Output ......................................................................... 1967
17-3. CLB X-BAR Architecture - Single Output ............................................................................ 1969
17-4. GPIO Output X-BAR Architecture ..................................................................................... 1971
17-5. ePWM and Output X-BARs Sources ................................................................................. 1975
17-6. XBARFLG1 Register .................................................................................................... 1978
17-7. XBARFLG2 Register .................................................................................................... 1983
17-8. XBARFLG3 Register .................................................................................................... 1988
17-9. XBARFLG4 Register .................................................................................................... 1993
17-10. XBARCLR1 Register .................................................................................................... 1998
17-11. XBARCLR2 Register .................................................................................................... 2001
17-12. XBARCLR3 Register .................................................................................................... 2004
17-13. XBARCLR4 Register .................................................................................................... 2007
17-14. INPUT1SELECT Register .............................................................................................. 2011
17-15. INPUT2SELECT Register .............................................................................................. 2012
17-16. INPUT3SELECT Register .............................................................................................. 2013
17-17. INPUT4SELECT Register .............................................................................................. 2014
17-18. INPUT5SELECT Register .............................................................................................. 2015
17-19. INPUT6SELECT Register .............................................................................................. 2016
17-20. INPUT7SELECT Register .............................................................................................. 2017
17-21. INPUT8SELECT Register .............................................................................................. 2018
17-22. INPUT9SELECT Register .............................................................................................. 2019
17-23. INPUT10SELECT Register ............................................................................................ 2020
17-24. INPUT11SELECT Register ............................................................................................ 2021
17-25. INPUT12SELECT Register ............................................................................................ 2022
17-26. INPUT13SELECT Register ............................................................................................ 2023
17-27. INPUT14SELECT Register ............................................................................................ 2024

SPRUII0B – May 2019 – Revised May 2020 List of Figures 47

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17-28. INPUT15SELECT Register ............................................................................................ 2025

17-29. INPUT16SELECT Register ............................................................................................ 2026
17-30. INPUTSELECTLOCK Register ........................................................................................ 2027
17-31. OUTPUT1MUX0TO15CFG Register ................................................................................. 2031
17-32. OUTPUT1MUX16TO31CFG Register ................................................................................ 2034
17-33. OUTPUT2MUX0TO15CFG Register ................................................................................. 2037
17-34. OUTPUT2MUX16TO31CFG Register ................................................................................ 2040
17-35. OUTPUT3MUX0TO15CFG Register ................................................................................. 2043
17-36. OUTPUT3MUX16TO31CFG Register ................................................................................ 2046
17-37. OUTPUT4MUX0TO15CFG Register ................................................................................. 2049
17-38. OUTPUT4MUX16TO31CFG Register ................................................................................ 2052
17-39. OUTPUT5MUX0TO15CFG Register ................................................................................. 2055
17-40. OUTPUT5MUX16TO31CFG Register ................................................................................ 2058
17-41. OUTPUT6MUX0TO15CFG Register ................................................................................. 2061
17-42. OUTPUT6MUX16TO31CFG Register ................................................................................ 2064
17-43. OUTPUT7MUX0TO15CFG Register ................................................................................. 2067
17-44. OUTPUT7MUX16TO31CFG Register ................................................................................ 2070
17-45. OUTPUT8MUX0TO15CFG Register ................................................................................. 2073
17-46. OUTPUT8MUX16TO31CFG Register ................................................................................ 2076
17-47. OUTPUT1MUXENABLE Register ..................................................................................... 2079
17-48. OUTPUT2MUXENABLE Register ..................................................................................... 2083
17-49. OUTPUT3MUXENABLE Register ..................................................................................... 2087
17-50. OUTPUT4MUXENABLE Register ..................................................................................... 2091
17-51. OUTPUT5MUXENABLE Register ..................................................................................... 2095
17-52. OUTPUT6MUXENABLE Register ..................................................................................... 2099
17-53. OUTPUT7MUXENABLE Register ..................................................................................... 2103
17-54. OUTPUT8MUXENABLE Register ..................................................................................... 2107
17-55. OUTPUTLATCH Register .............................................................................................. 2111
17-56. OUTPUTLATCHCLR Register......................................................................................... 2113
17-57. OUTPUTLATCHFRC Register ........................................................................................ 2115
17-58. OUTPUTLATCHENABLE Register ................................................................................... 2117
17-59. OUTPUTINV Register .................................................................................................. 2119
17-60. OUTPUTLOCK Register ............................................................................................... 2121
17-61. TRIP4MUX0TO15CFG Register ...................................................................................... 2124
17-62. TRIP4MUX16TO31CFG Register ..................................................................................... 2127
17-63. TRIP5MUX0TO15CFG Register ...................................................................................... 2130
17-64. TRIP5MUX16TO31CFG Register ..................................................................................... 2133
17-65. TRIP7MUX0TO15CFG Register ...................................................................................... 2136
17-66. TRIP7MUX16TO31CFG Register ..................................................................................... 2139
17-67. TRIP8MUX0TO15CFG Register ...................................................................................... 2142
17-68. TRIP8MUX16TO31CFG Register ..................................................................................... 2145
17-69. TRIP9MUX0TO15CFG Register ...................................................................................... 2148
17-70. TRIP9MUX16TO31CFG Register ..................................................................................... 2151
17-71. TRIP10MUX0TO15CFG Register ..................................................................................... 2154
17-72. TRIP10MUX16TO31CFG Register ................................................................................... 2157
17-73. TRIP11MUX0TO15CFG Register ..................................................................................... 2160
17-74. TRIP11MUX16TO31CFG Register ................................................................................... 2163
17-75. TRIP12MUX0TO15CFG Register ..................................................................................... 2166
17-76. TRIP12MUX16TO31CFG Register ................................................................................... 2169

48 List of Figures SPRUII0B – May 2019 – Revised May 2020

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17-77. TRIP4MUXENABLE Register .......................................................................................... 2172

17-78. TRIP5MUXENABLE Register .......................................................................................... 2176
17-79. TRIP7MUXENABLE Register .......................................................................................... 2180
17-80. TRIP8MUXENABLE Register .......................................................................................... 2184
17-81. TRIP9MUXENABLE Register .......................................................................................... 2188
17-82. TRIP10MUXENABLE Register ........................................................................................ 2192
17-83. TRIP11MUXENABLE Register ........................................................................................ 2196
17-84. TRIP12MUXENABLE Register ........................................................................................ 2200
17-85. TRIPOUTINV Register.................................................................................................. 2204
17-86. TRIPLOCK Register .................................................................................................... 2206
17-87. AUXSIG0MUX0TO15CFG Register .................................................................................. 2209
17-88. AUXSIG0MUX16TO31CFG Register ................................................................................. 2212
17-89. AUXSIG1MUX0TO15CFG Register .................................................................................. 2215
17-90. AUXSIG1MUX16TO31CFG Register ................................................................................. 2218
17-91. AUXSIG2MUX0TO15CFG Register .................................................................................. 2221
17-92. AUXSIG2MUX16TO31CFG Register ................................................................................. 2224
17-93. AUXSIG3MUX0TO15CFG Register .................................................................................. 2227
17-94. AUXSIG3MUX16TO31CFG Register ................................................................................. 2230
17-95. AUXSIG4MUX0TO15CFG Register .................................................................................. 2233
17-96. AUXSIG4MUX16TO31CFG Register ................................................................................. 2236
17-97. AUXSIG5MUX0TO15CFG Register .................................................................................. 2239
17-98. AUXSIG5MUX16TO31CFG Register ................................................................................. 2242
17-99. AUXSIG6MUX0TO15CFG Register .................................................................................. 2245
17-100. AUXSIG6MUX16TO31CFG Register ............................................................................... 2248
17-101. AUXSIG7MUX0TO15CFG Register ................................................................................. 2251
17-102. AUXSIG7MUX16TO31CFG Register ............................................................................... 2254
17-103. AUXSIG0MUXENABLE Register .................................................................................... 2257
17-104. AUXSIG1MUXENABLE Register .................................................................................... 2261
17-105. AUXSIG2MUXENABLE Register .................................................................................... 2265
17-106. AUXSIG3MUXENABLE Register .................................................................................... 2269
17-107. AUXSIG4MUXENABLE Register .................................................................................... 2273
17-108. AUXSIG5MUXENABLE Register .................................................................................... 2277
17-109. AUXSIG6MUXENABLE Register .................................................................................... 2281
17-110. AUXSIG7MUXENABLE Register .................................................................................... 2285
17-111. AUXSIGOUTINV Register ............................................................................................ 2289
17-112. AUXSIGLOCK Register ............................................................................................... 2291
18-1. F2838x Block Diagram ................................................................................................. 2298
19-1. Analog Subsystem Block Diagram (337-Ball ZWT) ................................................................. 2301
19-2. Analog Subsystem Block Diagram (176-Pin PTP) .................................................................. 2302
19-3. INTOSC1TRIM Register ................................................................................................ 2305
19-4. INTOSC2TRIM Register ................................................................................................ 2306
19-5. TSNSCTL Register ...................................................................................................... 2307
19-6. LOCK Register........................................................................................................... 2308
19-7. ANAREFTRIMA Register............................................................................................... 2309
19-8. ANAREFTRIMB Register............................................................................................... 2310
19-9. ANAREFTRIMC Register .............................................................................................. 2311
19-10. ANAREFTRIMD Register .............................................................................................. 2312
20-1. ADC Module Block Diagram ........................................................................................... 2315
20-2. SOC Block Diagram..................................................................................................... 2319

SPRUII0B – May 2019 – Revised May 2020 List of Figures 49

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20-3. Single-Ended Input Model .............................................................................................. 2320

20-4. Differential Input Model ................................................................................................. 2320
20-5. Round Robin Priority Example ........................................................................................ 2325
20-6. High Priority Example ................................................................................................... 2326
20-7. Burst Priority Example .................................................................................................. 2328
20-8. ADC EOC Interrupts .................................................................................................... 2329
20-9. ADC PPB Block Diagram .............................................................................................. 2331
20-10. ADC PPB Interrupt Event .............................................................................................. 2333
20-11. Opens/Shorts Detection Circuit ........................................................................................ 2334
20-12. Input Circuit Equivalent with OSDETECT Enabled ................................................................. 2335
20-13. ADC Timings for 12-bit Mode in Early Interrupt Mode ............................................................. 2338
20-14. ADC Timings for 12-bit Mode in Late Interrupt Mode .............................................................. 2339
20-15. ADC Timings for 16-bit Mode in Early Interrupt Mode ............................................................. 2340
20-16. ADC Timings for 16-bit Mode in Late Interrupt Mode (SYSCLK Cycles) ........................................ 2341
20-17. Example: Basic Synchronous Operation ............................................................................. 2343
20-18. Example: Synchronous Operation with Multiple Trigger Sources................................................. 2344
20-19. Example: Synchronous Operation with Uneven SOC Numbers .................................................. 2345
20-20. Example: Asynchronous Operation with Uneven SOC Numbers – Trigger Overflow .......................... 2345
20-21. Example: Asynchronous Operation with Different Resolutions ................................................... 2346
20-22. Example: Synchronous Operation with Different Resolutions ..................................................... 2346
20-23. Example: Synchronous Equivalent Operation with Non-Overlapping Conversions ............................ 2347
20-24. ADC Reference System ................................................................................................ 2350
20-25. ADC Shared Reference System....................................................................................... 2351
20-26. ADCCTL1 Register ...................................................................................................... 2356
20-27. ADCCTL2 Register ...................................................................................................... 2357
20-28. ADCBURSTCTL Register .............................................................................................. 2358
20-29. ADCINTFLG Register ................................................................................................... 2360
20-30. ADCINTFLGCLR Register ............................................................................................. 2362
20-31. ADCINTOVF Register .................................................................................................. 2364
20-32. ADCINTOVFCLR Register ............................................................................................. 2365
20-33. ADCINTSEL1N2 Register .............................................................................................. 2366
20-34. ADCINTSEL3N4 Register .............................................................................................. 2368
20-35. ADCSOCPRICTL Register ............................................................................................. 2370
20-36. ADCINTSOCSEL1 Register ........................................................................................... 2372
20-37. ADCINTSOCSEL2 Register ........................................................................................... 2374
20-38. ADCSOCFLG1 Register ................................................................................................ 2376
20-39. ADCSOCFRC1 Register ............................................................................................... 2380
20-40. ADCSOCOVF1 Register ............................................................................................... 2385
20-41. ADCSOCOVFCLR1 Register .......................................................................................... 2388
20-42. ADCSOC0CTL Register ................................................................................................ 2391
20-43. ADCSOC1CTL Register ................................................................................................ 2394
20-44. ADCSOC2CTL Register ................................................................................................ 2397
20-45. ADCSOC3CTL Register ................................................................................................ 2400
20-46. ADCSOC4CTL Register ................................................................................................ 2403
20-47. ADCSOC5CTL Register ................................................................................................ 2406
20-48. ADCSOC6CTL Register ................................................................................................ 2409
20-49. ADCSOC7CTL Register ................................................................................................ 2412
20-50. ADCSOC8CTL Register ................................................................................................ 2415
20-51. ADCSOC9CTL Register ................................................................................................ 2418

50 List of Figures SPRUII0B – May 2019 – Revised May 2020

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20-52. ADCSOC10CTL Register .............................................................................................. 2421

20-53. ADCSOC11CTL Register .............................................................................................. 2424
20-54. ADCSOC12CTL Register .............................................................................................. 2427
20-55. ADCSOC13CTL Register .............................................................................................. 2430
20-56. ADCSOC14CTL Register .............................................................................................. 2433
20-57. ADCSOC15CTL Register .............................................................................................. 2436
20-58. ADCEVTSTAT Register ................................................................................................ 2439
20-59. ADCEVTCLR Register.................................................................................................. 2441
20-60. ADCEVTSEL Register .................................................................................................. 2442
20-61. ADCEVTINTSEL Register.............................................................................................. 2444
20-62. ADCCOUNTER Register ............................................................................................... 2446
20-63. ADCREV Register ....................................................................................................... 2447
20-64. ADCOFFTRIM Register ................................................................................................ 2448
20-65. ADCPPB1CONFIG Register ........................................................................................... 2449
20-66. ADCPPB1STAMP Register ............................................................................................ 2451
20-67. ADCPPB1OFFCAL Register ........................................................................................... 2452
20-68. ADCPPB1OFFREF Register........................................................................................... 2453
20-69. ADCPPB1TRIPHI Register ............................................................................................ 2454
20-70. ADCPPB1TRIPLO Register............................................................................................ 2455
20-71. ADCPPB2CONFIG Register ........................................................................................... 2456
20-72. ADCPPB2STAMP Register ............................................................................................ 2458
20-73. ADCPPB2OFFCAL Register ........................................................................................... 2459
20-74. ADCPPB2OFFREF Register........................................................................................... 2460
20-75. ADCPPB2TRIPHI Register ............................................................................................ 2461
20-76. ADCPPB2TRIPLO Register............................................................................................ 2462
20-77. ADCPPB3CONFIG Register ........................................................................................... 2463
20-78. ADCPPB3STAMP Register ............................................................................................ 2465
20-79. ADCPPB3OFFCAL Register ........................................................................................... 2466
20-80. ADCPPB3OFFREF Register........................................................................................... 2467
20-81. ADCPPB3TRIPHI Register ............................................................................................ 2468
20-82. ADCPPB3TRIPLO Register............................................................................................ 2469
20-83. ADCPPB4CONFIG Register ........................................................................................... 2470
20-84. ADCPPB4STAMP Register ............................................................................................ 2472
20-85. ADCPPB4OFFCAL Register ........................................................................................... 2473
20-86. ADCPPB4OFFREF Register........................................................................................... 2474
20-87. ADCPPB4TRIPHI Register ............................................................................................ 2475
20-88. ADCPPB4TRIPLO Register............................................................................................ 2476
20-89. ADCINTCYCLE Register ............................................................................................... 2477
20-90. ADCINLTRIM1 Register ................................................................................................ 2478
20-91. ADCINLTRIM2 Register ................................................................................................ 2479
20-92. ADCINLTRIM3 Register ................................................................................................ 2480
20-93. ADCINLTRIM4 Register ................................................................................................ 2481
20-94. ADCINLTRIM5 Register ................................................................................................ 2482
20-95. ADCINLTRIM6 Register ................................................................................................ 2483
20-96. ADCRESULT0 Register ................................................................................................ 2486
20-97. ADCRESULT1 Register ................................................................................................ 2487
20-98. ADCRESULT2 Register ................................................................................................ 2488
20-99. ADCRESULT3 Register ................................................................................................ 2489
20-100. ADCRESULT4 Register ............................................................................................... 2490

SPRUII0B – May 2019 – Revised May 2020 List of Figures 51

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20-101. ADCRESULT5 Register ............................................................................................... 2491

20-102. ADCRESULT6 Register ............................................................................................... 2492
20-103. ADCRESULT7 Register ............................................................................................... 2493
20-104. ADCRESULT8 Register ............................................................................................... 2494
20-105. ADCRESULT9 Register ............................................................................................... 2495
20-106. ADCRESULT10 Register ............................................................................................. 2496
20-107. ADCRESULT11 Register ............................................................................................. 2497
20-108. ADCRESULT12 Register ............................................................................................. 2498
20-109. ADCRESULT13 Register ............................................................................................. 2499
20-110. ADCRESULT14 Register ............................................................................................. 2500
20-111. ADCRESULT15 Register ............................................................................................. 2501
20-112. ADCPPB1RESULT Register ......................................................................................... 2502
20-113. ADCPPB2RESULT Register ......................................................................................... 2503
20-114. ADCPPB3RESULT Register ......................................................................................... 2504
20-115. ADCPPB4RESULT Register ......................................................................................... 2505
21-1. DAC Module Block Diagram ........................................................................................... 2511
21-2. DACREV Register ....................................................................................................... 2515
21-3. DACCTL Register ....................................................................................................... 2516
21-4. DACVALA Register ..................................................................................................... 2517
21-5. DACVALS Register ..................................................................................................... 2518
21-6. DACOUTEN Register ................................................................................................... 2519
21-7. DACLOCK Register ..................................................................................................... 2520
21-8. DACTRIM Register ...................................................................................................... 2521
22-1. CMPSS Module Block Diagram ....................................................................................... 2525
22-2. Comparator Block Diagram ............................................................................................ 2525
22-3. Reference DAC Block Diagram ....................................................................................... 2526
22-4. Output Voltage Calculation............................................................................................. 2526
22-5. Ramp Generator Block Diagram ...................................................................................... 2528
22-6. Ramp Generator Behavior ............................................................................................. 2529
22-7. Digital Filter Behavior ................................................................................................... 2530
22-8. COMPCTL Register ..................................................................................................... 2536
22-9. COMPHYSCTL Register ............................................................................................... 2538
22-10. COMPSTS Register..................................................................................................... 2539
22-11. COMPSTSCLR Register ............................................................................................... 2540
22-12. COMPDACCTL Register ............................................................................................... 2541
22-13. DACHVALS Register ................................................................................................... 2543
22-14. DACHVALA Register ................................................................................................... 2544
22-15. RAMPMAXREFA Register ............................................................................................. 2545
22-16. RAMPMAXREFS Register ............................................................................................. 2546
22-17. RAMPDECVALA Register.............................................................................................. 2547
22-18. RAMPDECVALS Register.............................................................................................. 2548
22-19. RAMPSTS Register ..................................................................................................... 2549
22-20. DACLVALS Register .................................................................................................... 2550
22-21. DACLVALA Register .................................................................................................... 2551
22-22. RAMPDLYA Register ................................................................................................... 2552
22-23. RAMPDLYS Register ................................................................................................... 2553
22-24. CTRIPLFILCTL Register ............................................................................................... 2554
22-25. CTRIPLFILCLKCTL Register .......................................................................................... 2555
22-26. CTRIPHFILCTL Register ............................................................................................... 2556

52 List of Figures SPRUII0B – May 2019 – Revised May 2020

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22-27. CTRIPHFILCLKCTL Register .......................................................................................... 2557

22-28. COMPLOCK Register .................................................................................................. 2558
23-1. F2838x Block Diagram ................................................................................................. 2562
24-1. Capture and APWM Modes of Operation ............................................................................ 2568
24-2. Counter Compare and PRD Effects on the eCAP Output in APWM Mode ...................................... 2569
24-3. eCAP Block Diagram ................................................................................................... 2570
24-4. Event Prescale Control ................................................................................................. 2571
24-5. Prescale Function Waveforms ......................................................................................... 2571
24-6. Details of the Continuous/One-shot Block ........................................................................... 2572
24-7. Details of the Counter and Synchronization Block .................................................................. 2573
24-8. eCAP Synchronization Scheme ....................................................................................... 2574
24-9. Interrupts in eCAP Module ............................................................................................. 2575
24-10. PWM Waveform Details Of APWM Mode Operation ............................................................... 2576
24-11. Time-Base Frequency and Period Calculation ...................................................................... 2577
24-12. Capture Sequence for Absolute Time-stamp and Rising Edge Detect........................................... 2578
24-13. Capture Sequence for Absolute Time-stamp With Rising and Falling Edge Detect ............................ 2579
24-14. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect ....................................... 2580
24-15. Capture Sequence for Delta Mode Time-stamp With Rising and Falling Edge Detect ........................ 2581
24-16. PWM Waveform Details of APWM Mode Operation................................................................ 2582
24-17. TSCTR Register ......................................................................................................... 2585
24-18. CTRPHS Register ....................................................................................................... 2586
24-19. CAP1 Register ........................................................................................................... 2587
24-20. CAP2 Register ........................................................................................................... 2588
24-21. CAP3 Register ........................................................................................................... 2589
24-22. CAP4 Register ........................................................................................................... 2590
24-23. ECCTL0 Register........................................................................................................ 2591
24-24. ECCTL1 Register........................................................................................................ 2592
24-25. ECCTL2 Register........................................................................................................ 2594
24-26. ECEINT Register ........................................................................................................ 2597
24-27. ECFLG Register ......................................................................................................... 2599
24-28. ECCLR Register ......................................................................................................... 2600
24-29. ECFRC Register ......................................................................................................... 2601
24-30. ECAPSYNCINSEL Register ........................................................................................... 2602
25-1. HRCAP Operations Block Diagram ................................................................................... 2607
25-2. HRCAP Calibration ...................................................................................................... 2608
25-3. HRCTL Register ......................................................................................................... 2612
25-4. HRINTEN Register ...................................................................................................... 2613
25-5. HRFLG Register ......................................................................................................... 2614
25-6. HRCLR Register ......................................................................................................... 2615
25-7. HRFRC Register ........................................................................................................ 2616
25-8. HRCALPRD Register ................................................................................................... 2617
25-9. HRSYSCLKCTR Register .............................................................................................. 2618
25-10. HRSYSCLKCAP Register .............................................................................................. 2619
25-11. HRCLKCTR Register ................................................................................................... 2620
25-12. HRCLKCAP Register ................................................................................................... 2621
26-1. Multiple ePWM Modules................................................................................................ 2626
26-2. Submodules and Signal Connections for an ePWM Module ...................................................... 2627
26-3. ePWM modules and Critical Internal Signal Interconnects ........................................................ 2629
26-4. Time-Base Submodule ................................................................................................. 2632

SPRUII0B – May 2019 – Revised May 2020 List of Figures 53

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26-5. Time-Base Submodule Signals and Registers ...................................................................... 2633

26-6. Time-Base Frequency and Period .................................................................................... 2635
26-7. Time-Base Counter Synchronization Scheme ....................................................................... 2637
26-8. ePWM External SYNC Output ......................................................................................... 2638
26-9. Time-Base Up-Count Mode Waveforms ............................................................................. 2641
26-10. Time-Base Down-Count Mode Waveforms .......................................................................... 2642
26-11. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event ... 2642
26-12. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event ...... 2643
26-13. Global Load: Signals and Registers .................................................................................. 2644
26-14. Counter-Compare Submodule ......................................................................................... 2645
26-15. Detailed View of the Counter-Compare Submodule ................................................................ 2646
26-16. Counter-Compare Event Waveforms in Up-Count Mode .......................................................... 2649
26-17. Counter-Compare Events in Down-Count Mode .................................................................... 2649
26-18. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event ................................................................................................. 2650
26-19. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event ..................................................................................................................... 2650
26-20. Action-Qualifier Submodule ............................................................................................ 2651
26-21. Action-Qualifier Submodule Inputs and Outputs .................................................................... 2652
26-22. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs ......................................... 2653
26-23. AQCTL[SHDWAQAMODE] ........................................................................................... 2656
26-24. AQCTL[SHDWAQBMODE] ............................................................................................ 2656
26-25. Up-Down-Count Mode Symmetrical Waveform ..................................................................... 2658
26-26. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High ................................................................................................. 2659
26-27. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low ................................................................................................. 2660
26-28. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ........... 2661
26-29. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................ 2661
26-30. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary .......................................................................................... 2662
26-31. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ........................................................................................................................ 2663
26-32. Up-Down-Count, PWM Waveform Generation Utilizing T1 and T2 Events ..................................... 2663
26-33. Dead_Band Submodule ................................................................................................ 2664
26-34. Configuration Options for the Dead-Band Submodule ............................................................. 2666
26-35. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%).................................................. 2668
26-36. PWM Chopper Submodule............................................................................................. 2670
26-37. PWM Chopper Submodule Operational Details ..................................................................... 2671
26-38. Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only ............................... 2671
26-39. PWM Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ...... 2672
26-40. PWM Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ..................................................................................................................... 2673
26-41. Trip-Zone Submodule ................................................................................................... 2674
26-42. Trip-Zone Submodule Mode Control Logic .......................................................................... 2678
26-43. Trip-Zone Submodule Interrupt Logic................................................................................. 2679
26-44. Event-Trigger Submodule .............................................................................................. 2680
26-45. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs....................................... 2681
26-46. Event-Trigger Interrupt Generator ..................................................................................... 2683
26-47. Event-Trigger SOCA Pulse Generator ............................................................................... 2684

54 List of Figures SPRUII0B – May 2019 – Revised May 2020

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26-48. Event-Trigger SOCB Pulse Generator ............................................................................... 2684

26-49. Digital-Compare Submodule High-Level Block Diagram ........................................................... 2685
26-50. GPIO MUX-to-Trip Input Connectivity ................................................................................ 2686
26-51. DCxEVT1 Event Triggering ............................................................................................ 2689
26-52. DCxEVT2 Event Triggering ............................................................................................ 2689
26-53. Event Filtering ........................................................................................................... 2690
26-54. Blanking Window Timing Diagram .................................................................................... 2691
26-55. Valley Switching ......................................................................................................... 2692
26-56. ePWM X-BAR ........................................................................................................... 2693
26-57. Simplified ePWM Module............................................................................................... 2694
26-58. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave ..................................... 2695
26-59. Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 .................................................. 2696
26-60. Buck Waveforms for (Note: Only three bucks shown here) ....................................................... 2697
26-61. Control of Four Buck Stages. (Note: FPWM2 = N x FPWM1) ............................................................ 2698
26-62. Buck Waveforms for (Note: FPWM2 = FPWM1))........................................................................... 2699
26-63. Control of Two Half-H Bridge Stages (FPWM2 = N x FPWM1) .......................................................... 2700
26-64. Half-H Bridge Waveforms for (Note: Here FPWM2 = FPWM1 ) .......................................................... 2701
26-65. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control ............................. 2702
26-66. 3-Phase Inverter Waveforms for (Only One Inverter Shown) ..................................................... 2703
26-67. Configuring Two PWM Modules for Phase Control ................................................................. 2704
26-68. Timing Waveforms Associated With Phase Control Between Two Modules .................................... 2705
26-69. Control of a 3-Phase Interleaved DC/DC Converter ................................................................ 2706
26-70. 3-Phase Interleaved DC/DC Converter Waveforms for ........................................................... 2707
26-71. Controlling a Full-H Bridge Stage (FPWM2 = FPWM1) ................................................................... 2708
26-72. ZVS Full-H Bridge Waveforms ........................................................................................ 2709
26-73. Peak Current Mode Control of a Buck Converter ................................................................... 2710
26-74. Peak Current Mode Control Waveforms for ......................................................................... 2710
26-75. Control of Two Resonant Converter Stages ......................................................................... 2711
26-76. H-Bridge LLC Resonant Converter PWM Waveforms.............................................................. 2711
26-77. Resolution Calculations for Conventionally Generated PWM ..................................................... 2713
26-78. Operating Logic Using MEP ........................................................................................... 2715
26-79. HRPWM Extension Registers and Memory Configuration ......................................................... 2716
26-80. HRPWM System Interface ............................................................................................. 2717
26-81. HRPWM Block Diagram ................................................................................................ 2718
26-82. HRPWM and HRCAL Source Clock .................................................................................. 2718
26-83. Required PWM Waveform for a Requested Duty = 40.5% ........................................................ 2721
26-84. Low % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0) ........................................... 2725
26-85. High % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0) .......................................... 2725
26-86. Up-Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1) ......................................... 2726
26-87. Up-Down Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1) .................................. 2726
26-88. Simple Buck Controlled Converter Using a Single PWM .......................................................... 2731
26-89. PWM Waveform Generated for Simple Buck Controlled Converter .............................................. 2731
26-90. Simple Reconstruction Filter for a PWM-based DAC .............................................................. 2733
26-91. PWM Waveform Generated for the PWM DAC Function .......................................................... 2733
26-92. TBCTL Register ......................................................................................................... 2743
26-93. TBCTL2 Register ........................................................................................................ 2745
26-94. EPWMSYNCINSEL Register .......................................................................................... 2746
26-95. TBCTR Register ......................................................................................................... 2747
26-96. TBSTS Register ......................................................................................................... 2748

SPRUII0B – May 2019 – Revised May 2020 List of Figures 55

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26-97. EPWMSYNCOUTEN Register......................................................................................... 2749

26-98. TBCTL3 Register ........................................................................................................ 2751
26-99. CMPCTL Register ....................................................................................................... 2752
26-100. CMPCTL2 Register .................................................................................................... 2754
26-101. DBCTL Register ........................................................................................................ 2756
26-102. DBCTL2 Register ...................................................................................................... 2759
26-103. AQCTL Register........................................................................................................ 2760
26-104. AQTSRCSEL Register ................................................................................................ 2762
26-105. PCCTL Register ........................................................................................................ 2763
26-106. VCAPCTL Register .................................................................................................... 2764
26-107. VCNTCFG Register ................................................................................................... 2766
26-108. HRCNFG Register ..................................................................................................... 2768
26-109. HRPWR Register ...................................................................................................... 2770
26-110. HRMSTEP Register ................................................................................................... 2771
26-111. HRCNFG2 Register ................................................................................................... 2772
26-112. HRPCTL Register ...................................................................................................... 2773
26-113. TRREM Register ....................................................................................................... 2775
26-114. GLDCTL Register ...................................................................................................... 2776
26-115. GLDCFG Register ..................................................................................................... 2778
26-116. EPWMXLINK Register ................................................................................................ 2780
26-117. AQCTLA Register ...................................................................................................... 2783
26-118. AQCTLA2 Register .................................................................................................... 2785
26-119. AQCTLB Register ...................................................................................................... 2786
26-120. AQCTLB2 Register .................................................................................................... 2788
26-121. AQSFRC Register ..................................................................................................... 2789
26-122. AQCSFRC Register ................................................................................................... 2790
26-123. DBREDHR Register ................................................................................................... 2791
26-124. DBRED Register ....................................................................................................... 2792
26-125. DBFEDHR Register ................................................................................................... 2793
26-126. DBFED Register ....................................................................................................... 2794
26-127. TBPHS Register........................................................................................................ 2795
26-128. TBPRDHR Register ................................................................................................... 2796
26-129. TBPRD Register ....................................................................................................... 2797
26-130. CMPA Register ......................................................................................................... 2798
26-131. CMPB Register ......................................................................................................... 2799
26-132. CMPC Register ......................................................................................................... 2800
26-133. CMPD Register ......................................................................................................... 2801
26-134. GLDCTL2 Register .................................................................................................... 2802
26-135. SWVDELVAL Register ................................................................................................ 2803
26-136. TZSEL Register ........................................................................................................ 2804
26-137. TZDCSEL Register .................................................................................................... 2806
26-138. TZCTL Register ........................................................................................................ 2807
26-139. TZCTL2 Register ....................................................................................................... 2808
26-140. TZCTLDCA Register .................................................................................................. 2810
26-141. TZCTLDCB Register .................................................................................................. 2811
26-142. TZEINT Register ....................................................................................................... 2812
26-143. TZFLG Register ........................................................................................................ 2813
26-144. TZCBCFLG Register .................................................................................................. 2815
26-145. TZOSTFLG Register .................................................................................................. 2816

56 List of Figures SPRUII0B – May 2019 – Revised May 2020

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26-146. TZCLR Register ........................................................................................................ 2817

26-147. TZCBCCLR Register .................................................................................................. 2818
26-148. TZOSTCLR Register .................................................................................................. 2819
26-149. TZFRC Register ........................................................................................................ 2820
26-150. ETSEL Register ........................................................................................................ 2821
26-151. ETPS Register ......................................................................................................... 2823
26-152. ETFLG Register ........................................................................................................ 2826
26-153. ETCLR Register ........................................................................................................ 2827
26-154. ETFRC Register........................................................................................................ 2828
26-155. ETINTPS Register ..................................................................................................... 2829
26-156. ETSOCPS Register .................................................................................................... 2830
26-157. ETCNTINITCTL Register ............................................................................................. 2831
26-158. ETCNTINIT Register .................................................................................................. 2832
26-159. DCTRIPSEL Register ................................................................................................. 2833
26-160. DCACTL Register ...................................................................................................... 2835
26-161. DCBCTL Register ...................................................................................................... 2837
26-162. DCFCTL Register ...................................................................................................... 2839
26-163. DCCAPCTL Register .................................................................................................. 2841
26-164. DCFOFFSET Register ................................................................................................ 2843
26-165. DCFOFFSETCNT Register ........................................................................................... 2844
26-166. DCFWINDOW Register ............................................................................................... 2845
26-167. DCFWINDOWCNT Register .......................................................................................... 2846
26-168. DCCAP Register ....................................................................................................... 2847
26-169. DCAHTRIPSEL Register .............................................................................................. 2848
26-170. DCALTRIPSEL Register .............................................................................................. 2850
26-171. DCBHTRIPSEL Register .............................................................................................. 2852
26-172. DCBLTRIPSEL Register .............................................................................................. 2854
26-173. EPWMLOCK Register ................................................................................................. 2856
26-174. HWVDELVAL Register ................................................................................................ 2857
26-175. VCNTVAL Register .................................................................................................... 2858
26-176. SYNCSELECT Register............................................................................................... 2860
26-177. ADCSOCOUTSELECT Register ..................................................................................... 2861
26-178. SYNCSOCLOCK Register ............................................................................................ 2864
27-1. Optical Encoder Disk ................................................................................................... 2874
27-2. QEP Encoder Output Signal for Forward/Reverse Movement .................................................... 2874
27-3. Index Pulse Example ................................................................................................... 2875
27-4. Using eQEP to decode signals from SinCos Transducer .......................................................... 2877
27-5. Functional Block Diagram of the eQEP Peripheral ................................................................. 2879
27-6. Functional Block Diagram of Decoder Unit .......................................................................... 2881
27-7. Quadrature Decoder State Machine .................................................................................. 2882
27-8. Quadrature-clock and Direction Decoding ........................................................................... 2883
27-9. Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or 0xF9F) .............. 2885
27-10. Position Counter Underflow/Overflow (QPOSMAX = 4) ........................................................... 2886
27-11. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1) ............................................... 2887
27-12. Strobe Event Latch (QEPCTL[SEL] = 1) ............................................................................. 2888
27-13. Latching Position Counter on ADCSOCA/ADCSOCB event ...................................................... 2889
27-14. eQEP Position-compare Unit .......................................................................................... 2890
27-15. eQEP Position-compare Event Generation Points .................................................................. 2890
27-16. eQEP Position-compare Sync Output Pulse Stretcher ............................................................. 2891

SPRUII0B – May 2019 – Revised May 2020 List of Figures 57

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27-17. eQEP Edge Capture Unit .............................................................................................. 2892

27-18. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010) ................................. 2893
27-19. eQEP Edge Capture Unit - Timing Details ........................................................................... 2893
27-20. eQEP Watchdog Timer ................................................................................................. 2894
27-21. eQEP Unit Time Base .................................................................................................. 2895
27-22. QMA Module Block Diagram........................................................................................... 2896
27-23. QMA Mode-1 ............................................................................................................. 2897
27-24. QMA Mode-2 ............................................................................................................. 2898
27-25. EQEP Interrupt Generation ............................................................................................ 2899
27-26. QPOSCNT Register..................................................................................................... 2902
27-27. QPOSINIT Register ..................................................................................................... 2903
27-28. QPOSMAX Register .................................................................................................... 2904
27-29. QPOSCMP Register .................................................................................................... 2905
27-30. QPOSILAT Register .................................................................................................... 2906
27-31. QPOSSLAT Register ................................................................................................... 2907
27-32. QPOSLAT Register ..................................................................................................... 2908
27-33. QUTMR Register ........................................................................................................ 2909
27-34. QUPRD Register ........................................................................................................ 2910
27-35. QWDTMR Register ..................................................................................................... 2911
27-36. QWDPRD Register ...................................................................................................... 2912
27-37. QDECCTL Register ..................................................................................................... 2913
27-38. QEPCTL Register ....................................................................................................... 2915
27-39. QCAPCTL Register ..................................................................................................... 2918
27-40. QPOSCTL Register ..................................................................................................... 2919
27-41. QEINT Register .......................................................................................................... 2920
27-42. QFLG Register........................................................................................................... 2922
27-43. QCLR Register .......................................................................................................... 2924
27-44. QFRC Register .......................................................................................................... 2926
27-45. QEPSTS Register ....................................................................................................... 2928
27-46. QCTMR Register ........................................................................................................ 2930
27-47. QCPRD Register ........................................................................................................ 2931
27-48. QCTMRLAT Register ................................................................................................... 2932
27-49. QCPRDLAT Register ................................................................................................... 2933
27-50. REV Register ............................................................................................................ 2934
27-51. QEPSTROBESEL Register ............................................................................................ 2935
27-52. QMACTRL Register ..................................................................................................... 2936
27-53. QEPSRCSEL Register ................................................................................................. 2937
28-1. Sigma Delta Filter Module (SDFM) CPU Interface ................................................................. 2942
28-2. Sigma Delta Filter Module (SDFM) Block Diagram ................................................................. 2944
28-3. Block Diagram of One Filter Module .................................................................................. 2945
28-4. Input Qualification on SD-Cx and SD-Dx ............................................................................ 2946
28-5. Different Modulator Modes Supported ................................................................................ 2947
28-6. SDFM Clock Control .................................................................................................... 2948
28-7. Simplified Sinc Filter Architecture ..................................................................................... 2948
28-8. Z-Transform of Sinc Filter of Order N ................................................................................ 2949
28-9. Frequency Response of Different Sinc Filters ....................................................................... 2949
28-10. SDSYNC Event .......................................................................................................... 2954
28-11. Comparator Unit Structure ............................................................................................. 2956
28-12. Digital Filter .............................................................................................................. 2958

58 List of Figures SPRUII0B – May 2019 – Revised May 2020

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28-13. SDFM Error (SD_ERR) Interrupt Sources ........................................................................... 2959

28-14. SDFM Data Ready (SDy_DRINTx) Interrupt ........................................................................ 2960
28-15. SDIFLG Register ........................................................................................................ 2966
28-16. SDIFLGCLR Register ................................................................................................... 2968
28-17. SDCTL Register ......................................................................................................... 2970
28-18. SDMFILEN Register .................................................................................................... 2971
28-19. SDSTATUS Register.................................................................................................... 2972
28-20. SDCTLPARM1 Register ................................................................................................ 2973
28-21. SDDFPARM1 Register ................................................................................................. 2974
28-22. SDDPARM1 Register ................................................................................................... 2975
28-23. SDFLT1CMPH1 Register .............................................................................................. 2976
28-24. SDFLT1CMPL1 Register ............................................................................................... 2977
28-25. SDCPARM1 Register ................................................................................................... 2978
28-26. SDDATA1 Register ..................................................................................................... 2979
28-27. SDDATFIFO1 Register ................................................................................................. 2980
28-28. SDCDATA1 Register.................................................................................................... 2981
28-29. SDFLT1CMPH2 Register .............................................................................................. 2982
28-30. SDFLT1CMPHZ Register .............................................................................................. 2983
28-31. SDFIFOCTL1 Register ................................................................................................. 2984
28-32. SDSYNC1 Register ..................................................................................................... 2985
28-33. SDFLT1CMPL2 Register ............................................................................................... 2986
28-34. SDCTLPARM2 Register ................................................................................................ 2987
28-35. SDDFPARM2 Register ................................................................................................. 2988
28-36. SDDPARM2 Register ................................................................................................... 2989
28-37. SDFLT2CMPH1 Register .............................................................................................. 2990
28-38. SDFLT2CMPL1 Register ............................................................................................... 2991
28-39. SDCPARM2 Register ................................................................................................... 2992
28-40. SDDATA2 Register ..................................................................................................... 2993
28-41. SDDATFIFO2 Register ................................................................................................. 2994
28-42. SDCDATA2 Register.................................................................................................... 2995
28-43. SDFLT2CMPH2 Register .............................................................................................. 2996
28-44. SDFLT2CMPHZ Register .............................................................................................. 2997
28-45. SDFIFOCTL2 Register ................................................................................................. 2998
28-46. SDSYNC2 Register ..................................................................................................... 2999
28-47. SDFLT2CMPL2 Register ............................................................................................... 3000
28-48. SDCTLPARM3 Register ................................................................................................ 3001
28-49. SDDFPARM3 Register ................................................................................................. 3002
28-50. SDDPARM3 Register ................................................................................................... 3003
28-51. SDFLT3CMPH1 Register .............................................................................................. 3004
28-52. SDFLT3CMPL1 Register ............................................................................................... 3005
28-53. SDCPARM3 Register ................................................................................................... 3006
28-54. SDDATA3 Register ..................................................................................................... 3007
28-55. SDDATFIFO3 Register ................................................................................................. 3008
28-56. SDCDATA3 Register.................................................................................................... 3009
28-57. SDFLT3CMPH2 Register .............................................................................................. 3010
28-58. SDFLT3CMPHZ Register .............................................................................................. 3011
28-59. SDFIFOCTL3 Register ................................................................................................. 3012
28-60. SDSYNC3 Register ..................................................................................................... 3013
28-61. SDFLT3CMPL2 Register ............................................................................................... 3014

SPRUII0B – May 2019 – Revised May 2020 List of Figures 59

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28-62. SDCTLPARM4 Register ................................................................................................ 3015

28-63. SDDFPARM4 Register ................................................................................................. 3016
28-64. SDDPARM4 Register ................................................................................................... 3017
28-65. SDFLT4CMPH1 Register .............................................................................................. 3018
28-66. SDFLT4CMPL1 Register ............................................................................................... 3019
28-67. SDCPARM4 Register ................................................................................................... 3020
28-68. SDDATA4 Register ..................................................................................................... 3021
28-69. SDDATFIFO4 Register ................................................................................................. 3022
28-70. SDCDATA4 Register.................................................................................................... 3023
28-71. SDFLT4CMPH2 Register .............................................................................................. 3024
28-72. SDFLT4CMPHZ Register .............................................................................................. 3025
28-73. SDFIFOCTL4 Register ................................................................................................. 3026
28-74. SDSYNC4 Register ..................................................................................................... 3027
28-75. SDFLT4CMPL2 Register ............................................................................................... 3028
28-76. SDCOMP1CTL Register ............................................................................................... 3029
28-77. SDCOMP1EVT2FLTCTL Register .................................................................................... 3030
28-78. SDCOMP1EVT2FLTCLKCTL Register ............................................................................... 3031
28-79. SDCOMP1EVT1FLTCTL Register .................................................................................... 3032
28-80. SDCOMP1EVT1FLTCLKCTL Register ............................................................................... 3033
28-81. SDCOMP1LOCK Register ............................................................................................. 3034
28-82. SDCOMP2CTL Register ............................................................................................... 3035
28-83. SDCOMP2EVT2FLTCTL Register .................................................................................... 3036
28-84. SDCOMP2EVT2FLTCLKCTL Register ............................................................................... 3037
28-85. SDCOMP2EVT1FLTCTL Register .................................................................................... 3038
28-86. SDCOMP2EVT1FLTCLKCTL Register ............................................................................... 3039
28-87. SDCOMP2LOCK Register ............................................................................................. 3040
28-88. SDCOMP3CTL Register ............................................................................................... 3041
28-89. SDCOMP3EVT2FLTCTL Register .................................................................................... 3042
28-90. SDCOMP3EVT2FLTCLKCTL Register ............................................................................... 3043
28-91. SDCOMP3EVT1FLTCTL Register .................................................................................... 3044
28-92. SDCOMP3EVT1FLTCLKCTL Register ............................................................................... 3045
28-93. SDCOMP3LOCK Register ............................................................................................. 3046
28-94. SDCOMP4CTL Register ............................................................................................... 3047
28-95. SDCOMP4EVT2FLTCTL Register .................................................................................... 3048
28-96. SDCOMP4EVT2FLTCLKCTL Register ............................................................................... 3049
28-97. SDCOMP4EVT1FLTCTL Register .................................................................................... 3050
28-98. SDCOMP4EVT1FLTCLKCTL Register ............................................................................... 3051
28-99. SDCOMP4LOCK Register ............................................................................................. 3052
29-1. F2838x Block Diagram ................................................................................................. 3057
30-1. CAN Block Diagram ..................................................................................................... 3060
30-2. CAN_MUX................................................................................................................ 3065
30-3. CAN Core in Silent Mode .............................................................................................. 3065
30-4. CAN Core in Loopback Mode ......................................................................................... 3066
30-5. CAN Core in External Loopback Mode ............................................................................... 3067
30-6. CAN Core in Loopback Combined with Silent Mode ............................................................... 3067
30-7. CAN Interrupt Topology 1 .............................................................................................. 3069
30-8. CAN Interrupt Topology 2 .............................................................................................. 3070
30-9. Initialization of a Transmit Object ..................................................................................... 3072
30-10. Initialization of a Single Receive Object for Data Frames ......................................................... 3072

60 List of Figures SPRUII0B – May 2019 – Revised May 2020

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30-11. Initialization of a single Receive Object for Remote Frames ...................................................... 3073
30-12. CPU Handling of a FIFO Buffer (Interrupt Driven) .................................................................. 3078
30-13. Bit Timing ................................................................................................................. 3079
30-14. The Propagation Time Segment ...................................................................................... 3080
30-15. Synchronization on Late and Early Edges ........................................................................... 3082
30-16. Filtering of Short Dominant Spikes .................................................................................... 3083
30-17. Structure of the CAN Core's CAN Protocol Controller ............................................................. 3085
30-18. Data Transfer Between IF1 / IF2 Registers and Message RAM .................................................. 3089
30-19. Structure of a Message Object ........................................................................................ 3090
30-20. Message RAM Representation in Debug Mode ..................................................................... 3093
30-21. CAN_CTL Register ...................................................................................................... 3097
30-22. CAN_ES Register ....................................................................................................... 3100
30-23. CAN_ERRC Register ................................................................................................... 3102
30-24. CAN_BTR Register ..................................................................................................... 3103
30-25. CAN_INT Register ...................................................................................................... 3104
30-26. CAN_TEST Register .................................................................................................... 3105
30-27. CAN_PERR Register ................................................................................................... 3106
30-28. CAN_RAM_INIT Register .............................................................................................. 3107
30-29. CAN_GLB_INT_EN Register .......................................................................................... 3108
30-30. CAN_GLB_INT_FLG Register ......................................................................................... 3109
30-31. CAN_GLB_INT_CLR Register......................................................................................... 3110
30-32. CAN_ABOTR Register ................................................................................................. 3111
30-33. CAN_TXRQ_X Register ................................................................................................ 3112
30-34. CAN_TXRQ_21 Register ............................................................................................... 3113
30-35. CAN_NDAT_X Register ................................................................................................ 3114
30-36. CAN_NDAT_21 Register ............................................................................................... 3115
30-37. CAN_IPEN_X Register ................................................................................................. 3116
30-38. CAN_IPEN_21 Register ................................................................................................ 3117
30-39. CAN_MVAL_X Register ................................................................................................ 3118
30-40. CAN_MVAL_21 Register ............................................................................................... 3119
30-41. CAN_IP_MUX21 Register .............................................................................................. 3120
30-42. CAN_IF1CMD Register ................................................................................................. 3121
30-43. CAN_IF1MSK Register ................................................................................................. 3124
30-44. CAN_IF1ARB Register ................................................................................................. 3125
30-45. CAN_IF1MCTL Register ............................................................................................... 3127
30-46. CAN_IF1DATA Register ................................................................................................ 3129
30-47. CAN_IF1DATB Register ................................................................................................ 3130
30-48. CAN_IF2CMD Register ................................................................................................. 3131
30-49. CAN_IF2MSK Register ................................................................................................. 3134
30-50. CAN_IF2ARB Register ................................................................................................. 3135
30-51. CAN_IF2MCTL Register ............................................................................................... 3137
30-52. CAN_IF2DATA Register ................................................................................................ 3139
30-53. CAN_IF2DATB Register ................................................................................................ 3140
30-54. CAN_IF3OBS Register ................................................................................................. 3141
30-55. CAN_IF3MSK Register ................................................................................................. 3143
30-56. CAN_IF3ARB Register ................................................................................................. 3144
30-57. CAN_IF3MCTL Register ............................................................................................... 3145
30-58. CAN_IF3DATA Register ................................................................................................ 3147
30-59. CAN_IF3DATB Register ................................................................................................ 3148

SPRUII0B – May 2019 – Revised May 2020 List of Figures 61

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30-60. CAN_IF3UPD Register ................................................................................................. 3149

31-1. EtherCAT IP Block Diagram ........................................................................................... 3155
31-2. Two-port ESC Description ............................................................................................. 3156
31-3. Two-port Block Diagram in EtherCAT Topology .................................................................... 3157
31-4. ESC PHY Interface Diagram........................................................................................... 3159
31-5. PHY Management Interface Connectivity ............................................................................ 3160
31-6. EtherCAT State Machine ............................................................................................... 3161
31-7. ESC Integration on MCU ............................................................................................... 3163
31-8. Interaction of ESCSS with the CPU Subsystem .................................................................... 3165
31-9. ESCSS Wrapper ........................................................................................................ 3167
31-10. Clocking of ESC ......................................................................................................... 3169
31-11. ESC SS General Purpose Inputs Integration ........................................................................ 3172
31-12. ESC SS General Purpose Output Integration ....................................................................... 3173
31-13. ESC SYNC and LATCH ................................................................................................ 3174
31-14. SYNC0 Signal Modes................................................................................................... 3175
31-15. SYNC Integration for the HOST Intervention ........................................................................ 3176
31-16. SYNC Event Muxing for Different Host DMA Triggers ............................................................. 3177
31-17. ESC Latch Input Integration ........................................................................................... 3178
31-18. SYNC Integration for Control Functions - PWM SYNC ............................................................ 3181
31-19. SYNC Integration for Control Functions – ECAP ................................................................... 3181
31-20. SYNC Integration for Signal Conditioning – CLB ................................................................... 3182
31-21. ESCSS_CONFIG_LOCK Register .................................................................................... 3186
31-22. ESCSS_MISC_IO_CONFIG Register ................................................................................ 3187
31-23. ESCSS_PHY_IO_CONFIG Register ................................................................................. 3188
31-24. ESCSS_SYNC_IO_CONFIG Register ............................................................................... 3189
31-25. ESCSS_LATCH_IO_CONFIG Register .............................................................................. 3190
31-26. ESCSS_GPIN_SEL Register .......................................................................................... 3191
31-27. ESCSS_GPIN_IOPAD_SEL Register ................................................................................ 3192
31-28. ESCSS_GPOUT_SEL Register ....................................................................................... 3193
31-29. ESCSS_GPOUT_IOPAD_SEL Register ............................................................................. 3194
31-30. ESCSS_LED_CONFIG Register ...................................................................................... 3195
31-31. ESCSS_MISC_CONFIG Register..................................................................................... 3197
31-32. ESCSS_IPREVNUM Register ......................................................................................... 3200
31-33. ESCSS_INTR_RIS Register ........................................................................................... 3201
31-34. ESCSS_INTR_MASK Register ........................................................................................ 3203
31-35. ESCSS_INTR_MIS Register ........................................................................................... 3204
31-36. ESCSS_INTR_CLR Register .......................................................................................... 3206
31-37. ESCSS_INTR_SET Register .......................................................................................... 3207
31-38. ESCSS_LATCH_SEL Register ........................................................................................ 3209
31-39. ESCSS_ACCESS_CTRL Register .................................................................................... 3210
31-40. ESCSS_GPIN_DAT Register .......................................................................................... 3211
31-41. ESCSS_GPIN_PIPE Register ......................................................................................... 3212
31-42. ESCSS_GPIN_GRP_CAP_SEL Register ............................................................................ 3213
31-43. ESCSS_GPOUT_DAT Register ....................................................................................... 3215
31-44. ESCSS_GPOUT_PIPE Register ...................................................................................... 3216
31-45. ESCSS_GPOUT_GRP_CAP_SEL Register ......................................................................... 3217
31-46. ESCSS_MEM_TEST Register......................................................................................... 3218
31-47. ESCSS_RESET_DEST_CONFIG Register.......................................................................... 3219
31-48. ESCSS_SYNC0_CONFIG Register .................................................................................. 3220

62 List of Figures SPRUII0B – May 2019 – Revised May 2020

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31-49. ESCSS_SYNC1_CONFIG Register .................................................................................. 3221

32-1. FSI Transmitter (FSITX) CPU Interface .............................................................................. 3224
32-2. FSI Receiver (FSIRX) CPU Interface ................................................................................. 3224
32-3. FSI Receiver (FSIRX) CPU Interface with CLB ..................................................................... 3225
32-4. FSI Transmitter Block Diagram ........................................................................................ 3231
32-5. FSI Transmitter Core Block Diagram ................................................................................. 3232
32-6. FSI Receiver Block Diagram ........................................................................................... 3237
32-7. FSI Receiver Core Block Diagram .................................................................................... 3238
32-8. Delay Line Control Circuit .............................................................................................. 3241
32-9. Flush Sequence Signals................................................................................................ 3246
32-10. FSI with Internal Loopback ............................................................................................. 3247
32-11. FSI Multi-Slave Configuration.......................................................................................... 3250
32-12. FSI Transmitter Multi-Slave Multiplexing ............................................................................. 3250
32-13. CLB Generated Signals for FSI Multi-Slave Configuration ........................................................ 3251
32-14. FSI and CLB Multi-Slave Connections ............................................................................... 3252
32-15. FSITX as SPI Master, Transmit Only ................................................................................. 3253
32-16. FSIRX as SPI Slave, Receive Only ................................................................................... 3254
32-17. FSITX and FSIRX as SPI Master, Full Duplex ...................................................................... 3255
32-18. Point to Point Connection .............................................................................................. 3256
32-19. RX_MASTER_CTRL Register ......................................................................................... 3262
32-20. RX_OPER_CTRL Register ............................................................................................ 3263
32-21. RX_FRAME_INFO Register ........................................................................................... 3264
32-22. RX_FRAME_TAG_UDATA Register.................................................................................. 3265
32-23. RX_DMA_CTRL Register .............................................................................................. 3266
32-24. RX_EVT_STS Register ................................................................................................. 3267
32-25. RX_CRC_INFO Register ............................................................................................... 3270
32-26. RX_EVT_CLR Register................................................................................................. 3271
32-27. RX_EVT_FRC Register ................................................................................................ 3273
32-28. RX_BUF_PTR_LOAD Register........................................................................................ 3275
32-29. RX_BUF_PTR_STS Register .......................................................................................... 3276
32-30. RX_FRAME_WD_CTRL Register ..................................................................................... 3277
32-31. RX_FRAME_WD_REF Register ...................................................................................... 3278
32-32. RX_FRAME_WD_CNT Register ...................................................................................... 3279
32-33. RX_PING_WD_CTRL Register........................................................................................ 3280
32-34. RX_PING_TAG Register ............................................................................................... 3281
32-35. RX_PING_WD_REF Register ......................................................................................... 3282
32-36. RX_PING_WD_CNT Register ......................................................................................... 3283
32-37. RX_INT1_CTRL Register .............................................................................................. 3284
32-38. RX_INT2_CTRL Register .............................................................................................. 3287
32-39. RX_LOCK_CTRL Register ............................................................................................. 3290
32-40. RX_ECC_DATA Register .............................................................................................. 3291
32-41. RX_ECC_VAL Register ................................................................................................ 3292
32-42. RX_ECC_SEC_DATA Register ....................................................................................... 3293
32-43. RX_ECC_LOG Register ................................................................................................ 3294
32-44. RX_FRAME_TAG_CMP Register ..................................................................................... 3295
32-45. RX_PING_TAG_CMP Register........................................................................................ 3296
32-46. RX_DLYLINE_CTRL Register ......................................................................................... 3297
32-47. RX_VIS_1 Register ..................................................................................................... 3298
32-48. RX_BUF_BASE_y Register ............................................................................................ 3299

SPRUII0B – May 2019 – Revised May 2020 List of Figures 63

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32-49. TX_MASTER_CTRL Register ......................................................................................... 3302

32-50. TX_CLK_CTRL Register ............................................................................................... 3303
32-51. TX_OPER_CTRL_LO Register ........................................................................................ 3304
32-52. TX_OPER_CTRL_HI Register......................................................................................... 3306
32-53. TX_FRAME_CTRL Register ........................................................................................... 3307
32-54. TX_FRAME_TAG_UDATA Register .................................................................................. 3308
32-55. TX_BUF_PTR_LOAD Register ........................................................................................ 3309
32-56. TX_BUF_PTR_STS Register .......................................................................................... 3310
32-57. TX_PING_CTRL Register .............................................................................................. 3311
32-58. TX_PING_TAG Register ............................................................................................... 3312
32-59. TX_PING_TO_REF Register .......................................................................................... 3313
32-60. TX_PING_TO_CNT Register .......................................................................................... 3314
32-61. TX_INT_CTRL Register ................................................................................................ 3315
32-62. TX_DMA_CTRL Register .............................................................................................. 3317
32-63. TX_LOCK_CTRL Register ............................................................................................. 3318
32-64. TX_EVT_STS Register ................................................................................................. 3319
32-65. TX_EVT_CLR Register ................................................................................................. 3320
32-66. TX_EVT_FRC Register ................................................................................................. 3321
32-67. TX_USER_CRC Register .............................................................................................. 3322
32-68. TX_ECC_DATA Register............................................................................................... 3323
32-69. TX_ECC_VAL Register ................................................................................................. 3324
32-70. TX_BUF_BASE_y Register ............................................................................................ 3325
33-1. Multiple I2C Modules Connected ...................................................................................... 3331
33-2. I2C Module Conceptual Block Diagram .............................................................................. 3333
33-3. Clocking Diagram for the I2C Module ................................................................................ 3333
33-4. The Roles of the Clock Divide-Down Values (ICCL and ICCH) ................................................... 3334
33-5. Bit Transfer on the I2C bus ............................................................................................ 3335
33-6. I2C Module START and STOP Conditions .......................................................................... 3337
33-7. I2C Module Data Transfer (7-Bit Addressing with 8-bit Data Configuration Shown) ........................... 3338
33-8. I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR) ............................................ 3338
33-9. I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR) ........................................... 3339
33-10. I2C Module Free Data Format (FDF = 1 in I2CMDR) .............................................................. 3339
33-11. Repeated START Condition (in This Case, 7-Bit Addressing Format) ........................................... 3340
33-12. Synchronization of Two I2C Clock Generators During Arbitration ................................................ 3341
33-13. Arbitration Procedure Between Two Master-Transmitters ......................................................... 3342
33-14. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit ..................................... 3343
33-15. Enable Paths of the I2C Interrupt Requests ......................................................................... 3345
33-16. Backwards Compatibility Mode Bit, Slave Transmitter ............................................................. 3346
33-17. I2C_FIFO_interrupt...................................................................................................... 3347
33-18. I2COAR Register ........................................................................................................ 3350
33-19. I2CIER Register ......................................................................................................... 3351
33-20. I2CSTR Register ........................................................................................................ 3352
33-21. I2CCLKL Register ....................................................................................................... 3356
33-22. I2CCLKH Register....................................................................................................... 3357
33-23. I2CCNT Register ........................................................................................................ 3358
33-24. I2CDRR Register ........................................................................................................ 3359
33-25. I2CSAR Register ........................................................................................................ 3360
33-26. I2CDXR Register ........................................................................................................ 3361
33-27. I2CMDR Register........................................................................................................ 3362

64 List of Figures SPRUII0B – May 2019 – Revised May 2020

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33-28. I2CISRC Register ....................................................................................................... 3366

33-29. I2CEMDR Register ...................................................................................................... 3367
33-30. I2CPSC Register ........................................................................................................ 3368
33-31. I2CFFTX Register ....................................................................................................... 3369
33-32. I2CFFRX Register ....................................................................................................... 3371
34-1. Conceptual Block Diagram of the McBSP ........................................................................... 3377
34-2. McBSP Data Transfer Paths ........................................................................................... 3378
34-3. Companding Processes ................................................................................................ 3379
34-4. μ-Law Transmit Data Companding Format .......................................................................... 3379
34-5. A-Law Transmit Data Companding Format .......................................................................... 3379
34-6. Two Methods by Which the McBSP Can Compand Internal Data ................................................ 3380
34-7. Example - Clock Signal Control of Bit Transfer Timing ............................................................ 3380
34-8. McBSP Operating at Maximum Packet Frequency ................................................................. 3382
34-9. Single-Phase Frame for a McBSP Data Transfer ................................................................... 3383
34-10. Dual-Phase Frame for a McBSP Data Transfer ..................................................................... 3384
34-11. Implementing the AC97 Standard With a Dual-Phase Frame ..................................................... 3384
34-12. Timing of an AC97-Standard Data Transfer Near Frame Synchronization ...................................... 3385
34-13. McBSP Reception Physical Data Path ............................................................................... 3385
34-14. McBSP Reception Signal Activity ..................................................................................... 3385
34-15. McBSP Transmission Physical Data Path ........................................................................... 3386
34-16. McBSP Transmission Signal Activity ................................................................................. 3386
34-17. Conceptual Block Diagram of the Sample Rate Generator ........................................................ 3388
34-18. Possible Inputs to the Sample Rate Generator and the Polarity Bits ............................................ 3390
34-19. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 ........................... 3392
34-20. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3 ........................... 3393
34-21. Overrun in the McBSP Receiver ...................................................................................... 3395
34-22. Overrun Prevented in the McBSP Receiver ......................................................................... 3396
34-23. Possible Responses to Receive Frame-Synchronization Pulses ................................................. 3396
34-24. An Unexpected Frame-Synchronization Pulse During a McBSP Reception .................................... 3397
34-25. Proper Positioning of Frame-Synchronization Pulses .............................................................. 3398
34-26. Data in the McBSP Transmitter Overwritten and Thus Not Transmitted......................................... 3398
34-27. Underflow During McBSP Transmission ............................................................................. 3399
34-28. Underflow Prevented in the McBSP Transmitter .................................................................... 3400
34-29. Possible Responses to Transmit Frame-Synchronization Pulses ................................................ 3400
34-30. An Unexpected Frame-Synchronization Pulse During a McBSP Transmission ................................ 3401
34-31. Proper Positioning of Frame-Synchronization Pulses .............................................................. 3402
34-32. Alternating Between the Channels of Partition A and the Channels of Partition B ............................. 3404
34-33. Reassigning Channel Blocks Throughout a McBSP Data Transfer .............................................. 3405
34-34. McBSP Data Transfer in the 8-Partition Mode ...................................................................... 3406
34-35. Activity on McBSP Pins for the Possible Values of XMCM ........................................................ 3409
34-36. Typical SPI Interface .................................................................................................... 3410
34-37. SPI Transfer With CLKSTP = 10b (No Clock Delay), CLKXP = 0, and CLKRP = 0 ........................... 3412
34-38. SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 0, CLKRP = 1 ..................................... 3412
34-39. SPI Transfer With CLKSTP = 10b (No Clock Delay), CLKXP = 1, and CLKRP = 0 ........................... 3412
34-40. SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 1, CLKRP = 1 ..................................... 3412
34-41. SPI Interface with McBSP Used as Master .......................................................................... 3414
34-42. SPI Interface With McBSP Used as Slave ........................................................................... 3415
34-43. Unexpected Frame-Synchronization Pulse With (R/X)FIG = 0 .................................................... 3422
34-44. Unexpected Frame-Synchronization Pulse With (R/X)FIG = 1 .................................................... 3422

SPRUII0B – May 2019 – Revised May 2020 List of Figures 65

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34-45. Companding Processes for Reception and for Transmission ..................................................... 3423
34-46. Range of Programmable Data Delay ................................................................................. 3424
34-47. 2-Bit Data Delay Used to Skip a Framing Bit ........................................................................ 3424
34-48. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge .. 3429
34-49. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods ....................................... 3430
34-50. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge .. 3432
34-51. Unexpected Frame-Synchronization Pulse With (R/X) FIG = 0 ................................................... 3444
34-52. Unexpected Frame-Synchronization Pulse With (R/X) FIG = 1 ................................................... 3445
34-53. Companding Processes for Reception and for Transmission ..................................................... 3445
34-54. μ-Law Transmit Data Companding Format .......................................................................... 3446
34-55. A-Law Transmit Data Companding Format .......................................................................... 3446
34-56. Range of Programmable Data Delay ................................................................................. 3447
34-57. 2-Bit Data Delay Used to Skip a Framing Bit ........................................................................ 3447
34-58. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge .. 3451
34-59. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods ....................................... 3451
34-60. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge .. 3453
34-61. Four 8-Bit Data Words Transferred To/From the McBSP .......................................................... 3457
34-62. One 32-Bit Data Word Transferred To/From the McBSP .......................................................... 3457
34-63. 8-Bit Data Words Transferred at Maximum Packet Frequency ................................................... 3458
34-64. Configuring the Data Stream of as a Continuous 32-Bit Word .................................................... 3458
34-65. Receive Interrupt Generation .......................................................................................... 3459
34-66. Transmit Interrupt Generation ......................................................................................... 3459
34-67. Data Receive Registers (DRR2 and DRR1) ......................................................................... 3464
34-68. Data Transmit Registers (DXR2 and DXR1) ........................................................................ 3465
34-69. Serial Port Control 1 Register (SPCR1) ............................................................................. 3465
34-70. Serial Port Control 2 Register (SPCR2) ............................................................................. 3468
34-71. Receive Control Register 1 (RCR1) .................................................................................. 3470
34-72. Receive Control Register 2 (RCR2) .................................................................................. 3471
34-73. Transmit Control 1 Register (XCR1) .................................................................................. 3473
34-74. Transmit Control 2 Register (XCR2) ................................................................................. 3474
34-75. Sample Rate Generator 1 Register (SRGR1) ....................................................................... 3476
34-76. Sample Rate Generator 2 Register (SRGR2) ....................................................................... 3476
34-77. Multichannel Control 1 Register (MCR1) ............................................................................ 3478
34-78. Multichannel Control 2 Register (MCR2) ............................................................................. 3480
34-79. Pin Control Register (PCR) ........................................................................................... 3482
34-80. Receive Channel Enable Registers (RCERA...RCERH) ........................................................... 3484
34-81. Transmit Channel Enable Registers (XCERA...XCERH) .......................................................... 3486
34-82. McBSP Interrupt Enable Register (MFFINT) ........................................................................ 3488
35-1. PMBus Module Conceptual Block Diagram.......................................................................... 3494
35-2. Quick Command Message ............................................................................................. 3495
35-3. Send Byte Message with and without PEC ......................................................................... 3496
35-4. Receive Byte Message with and without PEC ...................................................................... 3496
35-5. Write Byte and Write Word Messages with and without PEC ..................................................... 3497
35-6. Read Byte and Read Word Messages with and without PEC..................................................... 3498
35-7. Process Call Message with and without PEC ....................................................................... 3499
35-8. Block Write Message with and without PEC ......................................................................... 3499
35-9. Block Read Message with and without PEC......................................................................... 3500
35-10. Block Write-Block Read Process Call Message with and without PEC .......................................... 3501
35-11. Alert Response Message............................................................................................... 3501

66 List of Figures SPRUII0B – May 2019 – Revised May 2020

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35-12. Extended Command Write Byte and Write Word Messages with and without PEC ........................... 3502
35-13. Extended Command Write Byte and Write Word Messages with and without PEC ........................... 3502
35-14. Group Command Message with and without PEC .................................................................. 3503
35-15. Quick Command Message ............................................................................................. 3504
35-16. Send Byte Message with and without PEC .......................................................................... 3504
35-17. Receive Byte Message with and without PEC ...................................................................... 3505
35-18. Write Byte and Write Word Messages with and without PEC ..................................................... 3505
35-19. Read Byte and Read Word Messages with and without PEC..................................................... 3506
35-20. Process Call Message with and without PEC ....................................................................... 3507
35-21. Block Write Message with and without PEC ......................................................................... 3507
35-22. Block Read Message with and without PEC......................................................................... 3508
35-23. Block Write-Block Read Process Call Message with and without PEC .......................................... 3509
35-24. Alert Response Message............................................................................................... 3509
35-25. Extended Command Write Message with and without PEC ....................................................... 3510
35-26. Extended Command Read Message with and without PEC ...................................................... 3510
35-27. Group Command Message with and without PEC .................................................................. 3511
35-28. PMBMC Register ........................................................................................................ 3514
35-29. PMBTXBUF Register ................................................................................................... 3515
35-30. PMBRXBUF Register ................................................................................................... 3516
35-31. PMBACK Register....................................................................................................... 3517
35-32. PMBSTS Register ....................................................................................................... 3518
35-33. PMBINTM Register ..................................................................................................... 3520
35-34. PMBSC Register ........................................................................................................ 3522
35-35. PMBHSA Register....................................................................................................... 3524
35-36. PMBCTRL Register ..................................................................................................... 3525
35-37. PMBTIMCTL Register .................................................................................................. 3527
35-38. PMBTIMCLK Register .................................................................................................. 3528
35-39. PMBTIMSTSETUP Register ........................................................................................... 3529
35-40. PMBTIMBIDLE Register ................................................................................................ 3530
35-41. PMBTIMLOWTIMOUT Register ....................................................................................... 3531
35-42. PMBTIMHIGHTIMOUT Register ...................................................................................... 3532
36-1. SCI CPU Interface ...................................................................................................... 3534
36-2. Serial Communications Interface (SCI) Module Block Diagram .................................................. 3536
36-3. Typical SCI Data Frame Formats ..................................................................................... 3537
36-4. Idle-Line Multiprocessor Communication Format ................................................................... 3539
36-5. Double-Buffered WUT and TXSHF ................................................................................... 3540
36-6. Address-Bit Multiprocessor Communication Format................................................................ 3541
36-7. SCI Asynchronous Communications Format ........................................................................ 3542
36-8. SCI RX Signals in Communication Modes ........................................................................... 3543
36-9. SCI TX Signals in Communications Mode ........................................................................... 3544
36-10. SCI FIFO Interrupt Flags and Enable Logic ......................................................................... 3547
36-11. SCICCR Register........................................................................................................ 3550
36-12. SCICTL1 Register ....................................................................................................... 3552
36-13. SCIHBAUD Register .................................................................................................... 3554
36-14. SCILBAUD Register .................................................................................................... 3555
36-15. SCICTL2 Register ....................................................................................................... 3556
36-16. SCIRXST Register ...................................................................................................... 3558
36-17. SCIRXEMU Register .................................................................................................... 3560
36-18. SCIRXBUF Register .................................................................................................... 3561

SPRUII0B – May 2019 – Revised May 2020 List of Figures 67

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36-19. SCITXBUF Register..................................................................................................... 3562

36-20. SCIFFTX Register ....................................................................................................... 3563
36-21. SCIFFRX Register ...................................................................................................... 3565
36-22. SCIFFCT Register....................................................................................................... 3567
36-23. SCIPRI Register ......................................................................................................... 3568
37-1. SPI CPU Interface ....................................................................................................... 3573
37-2. SPI Interrupt Flags and Enable Logic Generation .................................................................. 3575
37-3. SPI DMA Trigger Diagram ............................................................................................. 3576
37-4. SPI Master/Slave Connection ......................................................................................... 3577
37-5. SPI Module Master Configuration ..................................................................................... 3578
37-6. SPI Module Slave Configuration ...................................................................................... 3580
37-7. SPICLK Signal Options ................................................................................................. 3583
37-8. SPI: SPICLK-LSPCLK Characteristic When (BRR + 1) is Odd, BRR > 3, and CLKPOLARITY = 1 ......... 3584
37-9. SPI 3-wire Master Mode ................................................................................................ 3586
37-10. SPI 3-wire Slave Mode ................................................................................................. 3587
37-11. Five Bits per Character ................................................................................................. 3590
37-12. SPI Digital Audio Receiver Configuration Using Two SPIs ........................................................ 3592
37-13. Standard Right-Justified Digital Audio Data Format ................................................................ 3592
37-14. SPICCR Register ........................................................................................................ 3595
37-15. SPICTL Register ........................................................................................................ 3597
37-16. SPISTS Register ........................................................................................................ 3599
37-17. SPIBRR Register ........................................................................................................ 3601
37-18. SPIRXEMU Register .................................................................................................... 3602
37-19. SPIRXBUF Register .................................................................................................... 3603
37-20. SPITXBUF Register ..................................................................................................... 3604
37-21. SPIDAT Register ........................................................................................................ 3605
37-22. SPIFFTX Register ....................................................................................................... 3606
37-23. SPIFFRX Register....................................................................................................... 3608
37-24. SPIFFCT Register ....................................................................................................... 3610
37-25. SPIPRI Register ......................................................................................................... 3611
38-1. USB Block Diagram ..................................................................................................... 3616
38-2. USB Scheme............................................................................................................. 3617
38-3. Function Address Register (USBFADDR) ........................................................................... 3640
38-4. Power Management Register (USBPOWER) in Host Mode....................................................... 3641
38-5. Power Management Register (USBPOWER) in Device Mode .................................................... 3641
38-6. USB Transmit Interrupt Status Register (USBTXIS) ................................................................ 3643
38-7. USB Transmit Interrupt Status Register (USBRXIS) ............................................................... 3645
38-8. USB Transmit Interrupt Status Enable Register (USBTXIE) ...................................................... 3647
38-9. USB Transmit Interrupt Status Enable Register (USBRXIE) ...................................................... 3649
38-10. USB General Interrupt Status Register (USBIS) in Host Mode ................................................... 3651
38-11. USB General Interrupt Status Register (USBIS) in Device Mode ................................................ 3652
38-12. USB Interrupt Enable Register (USBIE) in Host Mode ............................................................. 3653
38-13. USB Interrupt Enable Register (USBIE) in Device Mode .......................................................... 3654
38-14. Frame Number Register (FRAME) .................................................................................... 3655
38-15. USB Endpoint Index Register (USBEPIDX) ......................................................................... 3655
38-16. USB Test Mode Register (USBTEST) in Host Mode ............................................................... 3656
38-17. USB Test Mode Register (USBTEST) in Device Mode ............................................................ 3656
38-18. USB FIFO Endpoint n Register (USBFIFO[n]) ...................................................................... 3658
38-19. USB Device Control Register (USBDEVCTL) ....................................................................... 3659

68 List of Figures SPRUII0B – May 2019 – Revised May 2020

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38-20. USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ) ................................................. 3661
38-21. USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ) .................................................. 3662
38-22. USB Transmit FIFO Start Address Register (USBTXFIFOADDR]) ............................................... 3663
38-23. USB Receive FIFO Start Address Register (USBRXFIFOADDR) ................................................ 3664
38-24. USB Connect Timing Register (USBCONTIM) ...................................................................... 3665
38-25. USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF) ........................... 3666
38-26. USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF) ........................... 3666
38-27. USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[n]) ............................ 3667
38-28. USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[n])...................................... 3668
38-29. USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[n]) ........................................... 3669
38-30. USB Receive Functional Address Endpoint n Registers (USBFIFO[n]) ......................................... 3670
38-31. USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[n]) ...................................... 3671
38-32. USB Transmit Hub Port Endpoint n Registers (USBRXHUBPORT[n]) .......................................... 3672
38-33. USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[n]) ......................................... 3673
38-34. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Host Mode ................................ 3674
38-35. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Device Mode ............................. 3675
38-36. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Host Mode ............................... 3676
38-37. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Device Mode ............................ 3676
38-38. USB Receive Byte Count Endpoint 0 Register (USBCOUNT0)................................................... 3677
38-39. USB Type Endpoint 0 Register (USBTYPE0) ....................................................................... 3677
38-40. USB NAK Limit Register (USBNAKLMT) ............................................................................ 3678
38-41. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Host Mode ................ 3679
38-42. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Device Mode ............. 3680
38-43. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Host Mode ............... 3682
38-44. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Device Mode ............ 3683
38-45. USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[n]) ......................................... 3684
38-46. USB Receive Control and Status Endpoint n Low Register (USBCSRL[n]) in Host Mode .................... 3685
38-47. USB Control and Status Endpoint n Low Register (USBCSRL[n]) in Device Mode ............................ 3686
38-48. USB Receive Control and Status Endpoint n High Register (USBCSRH[n]) in Host Mode ................... 3687
38-49. USB Control and Status Endpoint n High Register (USBCSRH[n]) in Device Mode ........................... 3688
38-50. USB Maximum Receive Data Endpoint n Registers (USBRXCOUNT[n]) ....................................... 3689
38-51. USB Host Transmit Configure Type Endpoint n Register (USBTXTYPE[n]) .................................... 3690
38-52. USB Host Transmit Interval Endpoint n Register (USBTXINTERVAL[n]) ....................................... 3691
38-53. USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[n]) .................................... 3692
38-54. USB Host Receive Polling Interval Endpoint n Register (USBRXINTERVAL[n]) ............................... 3693
38-55. USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[n]) .............. 3694
38-56. USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS) ................................. 3695
38-57. USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS) ................................ 3697
38-58. USB External Power Control Register (USBEPC) .................................................................. 3698
38-59. USB External Power Control Raw Interrupt Status Register (USBEPCRIS) .................................... 3700
38-60. USB External Power Control Interrupt Mask Register (USBEPCIM) ............................................. 3701
38-61. USB External Power Control Interrupt Status and Clear Register (USBEPCISC) .............................. 3702
38-62. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) ............................................. 3703
38-63. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) ............................................. 3704
38-64. USB Device RESUME Interrupt Status and Clear Register (USBDRISC)....................................... 3705
38-65. USB General-Purpose Control and Status Register (USBGPCS) ................................................ 3706
38-66. USB DMA Select Register (USBDMASEL) .......................................................................... 3707
38-67. USB Global Interrupt Enable (USBGLBINTEN) ..................................................................... 3709
38-68. USB Global Interrupt Flag (USBGLBINTFLG)....................................................................... 3710

SPRUII0B – May 2019 – Revised May 2020 List of Figures 69

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38-69. USB Global Interrupt Flag Clear (USBGLBINTFLGCLR) .......................................................... 3711

38-70. USBDMARIS Register .................................................................................................. 3712
38-71. USBDMAIM Register ................................................................................................... 3713
38-72. USBDMAISC Register .................................................................................................. 3714
39-1. F2838x Block Diagram ................................................................................................. 3716
40-1. Connectivity Manager Block Diagram ................................................................................ 3719
41-1. CM Clocking System .................................................................................................... 3724
41-2. CM Subsystem NMI Sources and NMIWD .......................................................................... 3729
41-3. CM CPU-Timers ......................................................................................................... 3736
41-4. CM CPU-Timers Interrupt Signals .................................................................................... 3736
41-5. CM Memory Block Diagram ............................................................................................ 3737
41-6. Mem allocate logic ...................................................................................................... 3738
41-7. Interleaving ............................................................................................................... 3739
41-8. Content of Each Memory Location for ECC Memories ............................................................. 3740
41-9. Content of Each Memory Location for Parity Memories ........................................................... 3740
41-10. ROM Parity Checking Logic ........................................................................................... 3742
41-11. CM Block Diagram ...................................................................................................... 3743
41-12. Unaligned Start Address ............................................................................................... 3744
41-13. Overlapping Regions.................................................................................................... 3744
41-14. Sub-Regions ............................................................................................................. 3745
41-15. Programmers Model Memory Map .................................................................................... 3745
41-16. Debug Trace ............................................................................................................. 3746
41-17. CxLOCK Register ....................................................................................................... 3749
41-18. CxTEST Register ........................................................................................................ 3750
41-19. CxINIT Register.......................................................................................................... 3751
41-20. CxINITDONE Register .................................................................................................. 3752
41-21. CMMSGxLOCK Register ............................................................................................... 3753
41-22. CMMSGxTEST Register ............................................................................................... 3754
41-23. CMMSGxINIT Register ................................................................................................. 3756
41-24. CMMSGxINITDONE Register ......................................................................................... 3757
41-25. SxGROUP1_LOCK Register........................................................................................... 3758
41-26. SxGROUP1_TEST Register ........................................................................................... 3759
41-27. SxGROUP1_INIT Register ............................................................................................. 3761
41-28. SxGROUP1_INITDONE Register ..................................................................................... 3762
41-29. ROM_LOCK Register ................................................................................................... 3763
41-30. ROM_TEST Register ................................................................................................... 3764
41-31. ROM_FORCE_ERROR Register ..................................................................................... 3765
41-32. PERI_MEM_TEST_LOCK Register................................................................................... 3766
41-33. PERI_MEM_TEST_CONTROL Register ............................................................................. 3767
41-34. DIAGERRFLG Register ................................................................................................ 3769
41-35. DIAGERRCLR Register ................................................................................................ 3770
41-36. DIAGERRADDR Register .............................................................................................. 3771
41-37. UCERRFLG Register ................................................................................................... 3774
41-38. UCERRSET Register ................................................................................................... 3776
41-39. UCERRCLR Register ................................................................................................... 3777
41-40. UCM4EADDR Register ................................................................................................. 3778
41-41. UCEMACEADDR Register ............................................................................................. 3779
41-42. UCuDMAEADDR Register ............................................................................................. 3780
41-43. UCEtherCATMEMREADDR Register ................................................................................ 3781

70 List of Figures SPRUII0B – May 2019 – Revised May 2020

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41-44. UCEMACMEMREADDR Register..................................................................................... 3782

41-45. BUSFAULTFLG Register............................................................................................... 3783
41-46. BUSFAULTCLR Register .............................................................................................. 3784
41-47. M4BUSFAULTADDR Register ........................................................................................ 3785
41-48. uDMABUSFAULTADDR Register ..................................................................................... 3786
41-49. EMACBUSFAULTADDR Register .................................................................................... 3787
41-50. CERRFLG Register ..................................................................................................... 3788
41-51. CERRSET Register ..................................................................................................... 3789
41-52. CERRCLR Register ..................................................................................................... 3790
41-53. CM4EADDR Register ................................................................................................... 3791
41-54. CEMACEADDR Register ............................................................................................... 3792
41-55. CuDMAEADDR Register ............................................................................................... 3793
41-56. CERRCNT Register ..................................................................................................... 3794
41-57. CERRTHRES Register ................................................................................................. 3795
41-58. CEINTFLG Register..................................................................................................... 3796
41-59. CEINTSET Register..................................................................................................... 3797
41-60. CEINTCLR Register .................................................................................................... 3798
41-61. CEINTEN Register ...................................................................................................... 3799
41-62. CMPCLKCR0 Register ................................................................................................. 3802
41-63. CMPCLKCR1 Register ................................................................................................. 3803
41-64. CMPCLKCR2 Register ................................................................................................. 3805
41-65. CMSOFTPRESET0 Register .......................................................................................... 3807
41-66. CMSOFTPRESET1 Register .......................................................................................... 3808
41-67. CMSOFTPRESET2 Register .......................................................................................... 3810
41-68. CMCLKSTOPREQ0 Register .......................................................................................... 3811
41-69. CMCLKSTOPREQ1 Register .......................................................................................... 3812
41-70. CMCLKSTOPREQ2 Register .......................................................................................... 3813
41-71. CMCLKSTOPACK0 Register .......................................................................................... 3814
41-72. CMCLKSTOPACK1 Register .......................................................................................... 3815
41-73. CMCLKSTOPACK2 Register .......................................................................................... 3816
41-74. MCANWAKESTATUS Register ....................................................................................... 3817
41-75. MCANWAKESTATUSCLR Register .................................................................................. 3818
41-76. PALLOCATESTS Register ............................................................................................. 3819
41-77. CMRESCCLR Register ................................................................................................. 3820
41-78. CMRESC Register ...................................................................................................... 3822
41-79. CMSYSCTLLOCK Register ............................................................................................ 3824
41-80. TIM Register ............................................................................................................. 3826
41-81. PRD Register ............................................................................................................ 3827
41-82. TCR Register ............................................................................................................ 3828
41-83. TPR Register............................................................................................................. 3830
41-84. MPU_CONTROL_REG Register ...................................................................................... 3833
41-85. ACC_VIO_INTEN Register ............................................................................................ 3834
41-86. ACC_VIO_FLAGS Register ............................................................................................ 3835
41-87. ACC_VIO_FLAGS_SET Register ..................................................................................... 3836
41-88. ACC_VIO_FLAGS_CLR Register ..................................................................................... 3837
41-89. ACC_VIO_ADDR_REG Register...................................................................................... 3838
41-90. REGION0_STARTADDRESSS Register............................................................................. 3839
41-91. REGION0_CONFIG Register .......................................................................................... 3840
41-92. REGION1_STARTADDRESSS Register............................................................................. 3842

SPRUII0B – May 2019 – Revised May 2020 List of Figures 71

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41-93. REGION1_CONFIG Register .......................................................................................... 3843

41-94. REGION2_STARTADDRESSS Register............................................................................. 3845
41-95. REGION2_CONFIG Register .......................................................................................... 3846
41-96. REGION3_STARTADDRESSS Register............................................................................. 3848
41-97. REGION3_CONFIG Register .......................................................................................... 3849
41-98. REGION4_STARTADDRESSS Register............................................................................. 3851
41-99. REGION4_CONFIG Register .......................................................................................... 3852
41-100. REGION5_STARTADDRESSS Register ........................................................................... 3854
41-101. REGION5_CONFIG Register ........................................................................................ 3855
41-102. REGION6_STARTADDRESSS Register ........................................................................... 3857
41-103. REGION6_CONFIG Register ........................................................................................ 3858
41-104. REGION7_STARTADDRESSS Register ........................................................................... 3860
41-105. REGION7_CONFIG Register ........................................................................................ 3861
41-106. CMNMICFG Register .................................................................................................. 3864
41-107. CMNMIFLG Register .................................................................................................. 3865
41-108. CMNMIFLGCLR Register ............................................................................................. 3867
41-109. CMNMIFLGFRC Register ............................................................................................. 3869
41-110. CMNMIWDCNT Register ............................................................................................. 3871
41-111. CMNMIWDPRD Register ............................................................................................. 3872
41-112. CMNMISHDWFLG Register .......................................................................................... 3873
41-113. NVIC_ISER0 Register ................................................................................................. 3877
41-114. NVIC_ISER1 Register ................................................................................................. 3882
41-115. NVIC_ICER0 Register ................................................................................................. 3887
41-116. NVIC_ICER1 Register ................................................................................................. 3892
41-117. NVIC_ISPR0 Register ................................................................................................. 3897
41-118. NVIC_ISPR1 Register ................................................................................................. 3902
41-119. NVIC_ISPR2 Register ................................................................................................. 3907
41-120. NVIC_ICPR0 Register ................................................................................................. 3912
41-121. NVIC_ICPR1 Register ................................................................................................. 3917
41-122. NVIC_IABR0 Register ................................................................................................. 3922
41-123. NVIC_IABR1 Register ................................................................................................. 3925
41-124. NVIC_IPR0 Register ................................................................................................... 3928
41-125. NVIC_IPR1 Register ................................................................................................... 3929
41-126. NVIC_IPR2 Register ................................................................................................... 3930
41-127. NVIC_IPR3 Register ................................................................................................... 3931
41-128. NVIC_IPR4 Register ................................................................................................... 3932
41-129. NVIC_IPR5 Register ................................................................................................... 3933
41-130. NVIC_IPR6 Register ................................................................................................... 3934
41-131. NVIC_IPR7 Register ................................................................................................... 3935
41-132. NVIC_IPR8 Register ................................................................................................... 3936
41-133. NVIC_IPR9 Register ................................................................................................... 3937
41-134. NVIC_IPR10 Register ................................................................................................. 3938
41-135. NVIC_IPR11 Register ................................................................................................. 3939
41-136. NVIC_IPR12 Register ................................................................................................. 3940
41-137. NVIC_IPR13 Register ................................................................................................. 3941
41-138. NVIC_IPR14 Register ................................................................................................. 3942
41-139. NVIC_IPR15 Register ................................................................................................. 3943
41-140. STIR Register .......................................................................................................... 3944
41-141. ACTLR Register ........................................................................................................ 3946

72 List of Figures SPRUII0B – May 2019 – Revised May 2020

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41-142. CPUID Register ........................................................................................................ 3947

41-143. ICSR Register .......................................................................................................... 3948
41-144. VTOR Register ......................................................................................................... 3950
41-145. AIRCR Register ........................................................................................................ 3951
41-146. SCR Register ........................................................................................................... 3953
41-147. CCR Register ........................................................................................................... 3954
41-148. SHPR1 Register........................................................................................................ 3956
41-149. SHPR2 Register........................................................................................................ 3957
41-150. SHPR3 Register........................................................................................................ 3958
41-151. SHCSRS Register ..................................................................................................... 3959
41-152. CFSR Register ......................................................................................................... 3963
41-153. HFSR Register ......................................................................................................... 3967
41-154. MMFAR Register ....................................................................................................... 3968
41-155. BFAR Register ......................................................................................................... 3969
41-156. AFSR Register ......................................................................................................... 3970
41-157. MMSR Register ........................................................................................................ 3972
41-158. BFSR Register ......................................................................................................... 3974
41-159. UFSR Register ......................................................................................................... 3976
41-160. SYST_CSR Register .................................................................................................. 3979
41-161. SYST_RVR Register .................................................................................................. 3980
41-162. SYST_CVR Register .................................................................................................. 3981
41-163. SYST_CALIB Register ................................................................................................ 3982
41-164. MPU_TYPE Register .................................................................................................. 3984
41-165. MPU_CTRL Register .................................................................................................. 3985
41-166. MPU_RNR Register ................................................................................................... 3986
41-167. MPU_RBAR Register.................................................................................................. 3987
41-168. MPU_RASR Register.................................................................................................. 3988
41-169. MPU_RBAR_A1 Register ............................................................................................. 3992
41-170. MPU_RASR_A1 Register ............................................................................................. 3993
41-171. MPU_RBAR_A2 Register ............................................................................................. 3997
41-172. MPU_RASR_A2 Register ............................................................................................. 3998
41-173. MPU_RBAR_A3 Register ............................................................................................. 4002
41-174. MPU_RASR_A3 Register ............................................................................................. 4003
41-175. SCSR Register ......................................................................................................... 4008
41-176. WDCNTR Register..................................................................................................... 4009
41-177. WDKEY Register ....................................................................................................... 4010
41-178. WDCR Register ........................................................................................................ 4011
41-179. WDWCR Register ...................................................................................................... 4013
42-1. AES Block Diagram ..................................................................................................... 4016
42-2. AES - GCM Operation .................................................................................................. 4020
42-3. AES - CCM Operation .................................................................................................. 4021
42-4. AES - XTS Operation ................................................................................................... 4022
42-5. AES - ECB Feedback Mode ........................................................................................... 4023
42-6. AES - CBC Feedback Mode ........................................................................................... 4024
42-7. AES Encryption With CTR/ICM Mode ................................................................................ 4025
42-8. AES - CFB Feedback Mode ........................................................................................... 4026
42-9. AES - F8 Mode .......................................................................................................... 4027
42-10. AES - F9 Operation ..................................................................................................... 4028
42-11. AES - CBC-MAC Authentication Mode ............................................................................... 4029

SPRUII0B – May 2019 – Revised May 2020 List of Figures 73

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42-12. AES Polling Mode ....................................................................................................... 4033

42-13. AES Interrupt Service ................................................................................................... 4035
42-14. AESDMAINTEN Register .............................................................................................. 4038
42-15. AESDMASTATUS Register ............................................................................................ 4039
42-16. AESDMASTATUSCLR Register ...................................................................................... 4040
42-17. AES_KEY2_6 Register ................................................................................................. 4043
42-18. AES_KEY2_7 Register ................................................................................................. 4044
42-19. AES_KEY2_4 Register ................................................................................................. 4045
42-20. AES_KEY2_5 Register ................................................................................................. 4046
42-21. AES_KEY2_2 Register ................................................................................................. 4047
42-22. AES_KEY2_3 Register ................................................................................................. 4048
42-23. AES_KEY2_0 Register ................................................................................................. 4049
42-24. AES_KEY2_1 Register ................................................................................................. 4050
42-25. AES_KEY1_6 Register ................................................................................................. 4051
42-26. AES_KEY1_7 Register ................................................................................................. 4052
42-27. AES_KEY1_4 Register ................................................................................................. 4053
42-28. AES_KEY1_5 Register ................................................................................................. 4054
42-29. AES_KEY1_2 Register ................................................................................................. 4055
42-30. AES_KEY1_3 Register ................................................................................................. 4056
42-31. AES_KEY1_0 Register ................................................................................................. 4057
42-32. AES_KEY1_1 Register ................................................................................................. 4058
42-33. AES_IV_IN_OUT_0 Register .......................................................................................... 4059
42-34. AES_IV_IN_OUT_1 Register .......................................................................................... 4060
42-35. AES_IV_IN_OUT_2 Register .......................................................................................... 4061
42-36. AES_IV_IN_OUT_3 Register .......................................................................................... 4062
42-37. AES_CTRL Register .................................................................................................... 4063
42-38. AES_C_LENGTH_0 Register .......................................................................................... 4066
42-39. AES_C_LENGTH_1 Register .......................................................................................... 4067
42-40. AES_AUTH_LENGTH Register ....................................................................................... 4068
42-41. AES_DATA_IN_OUT_0 Register ..................................................................................... 4069
42-42. AES_DATA_IN_OUT_1 Register ..................................................................................... 4070
42-43. AES_DATA_IN_OUT_2 Register ..................................................................................... 4071
42-44. AES_DATA_IN_OUT_3 Register ..................................................................................... 4072
42-45. AES_TAG_OUT_0 Register ........................................................................................... 4073
42-46. AES_TAG_OUT_1 Register ........................................................................................... 4074
42-47. AES_TAG_OUT_2 Register ........................................................................................... 4075
42-48. AES_TAG_OUT_3 Register ........................................................................................... 4076
42-49. AES_REV Register ..................................................................................................... 4077
42-50. AES_SYSCONFIG Register ........................................................................................... 4078
42-51. AES_SYSSTATUS Register ........................................................................................... 4080
42-52. AES_IRQSTATUS Register............................................................................................ 4081
42-53. AES_IRQENABLE Register............................................................................................ 4082
42-54. AES_DIRTY_BITS Register ........................................................................................... 4083
43-1. MII Mode Signals ........................................................................................................ 4088
43-2. RMII Mode Signals ...................................................................................................... 4089
43-3. RevMII Mode Signals ................................................................................................... 4091
43-4. Ethernet Clocking ....................................................................................................... 4092
43-5. RMII Clocking ............................................................................................................ 4093
43-6. RevMII Clocking ......................................................................................................... 4093

74 List of Figures SPRUII0B – May 2019 – Revised May 2020

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43-7. Trigger Sources for Auxiliary Timestamping ......................................................................... 4094

43-8. MAC Interrupt Sources ................................................................................................. 4095
43-9. Combined SBD_Intr Sources .......................................................................................... 4096
43-10. Networked Time Synchronization ..................................................................................... 4103
43-11. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path Correction ........................... 4104
43-12. System Time Update Using Fine Method ............................................................................ 4112
43-13. Packet Filtering .......................................................................................................... 4116
43-14. TCP Segmentation Overview .......................................................................................... 4130
43-15. Header and Payload Fields of Segmented Packets ................................................................ 4132
43-16. Wakeup Filter Register Layout ........................................................................................ 4137
43-17. LPI Transitions on Transmit ............................................................................................ 4140
43-18. LPI Transitions on Receive ............................................................................................ 4142
43-19. Descriptor Ring Structure .............................................................................................. 4151
43-20. DMA Descriptor Ring ................................................................................................... 4152
43-21. Transmit Normal Read Format ........................................................................................ 4153
43-22. Transmit Write Back Format ........................................................................................... 4157
43-23. Transmit Context Descriptor Format .................................................................................. 4161
43-24. Receive Descriptor Read Format ..................................................................................... 4164
43-25. Receive Normal Write Back Format .................................................................................. 4166
43-26. Receive Context Descriptor Format .................................................................................. 4173
43-27. ETHERNETSS_IPREVNUM Register ................................................................................ 4187
43-28. ETHERNETSS_CTRLSTS Register .................................................................................. 4188
43-29. ETHERNETSS_PTPTSTRIGSEL0 Register......................................................................... 4190
43-30. ETHERNETSS_PTPTSTRIGSEL1 Register......................................................................... 4191
43-31. ETHERNETSS_PTPTSSWTRIG0 Register ......................................................................... 4192
43-32. ETHERNETSS_PTPTSSWTRIG1 Register ......................................................................... 4193
43-33. ETHERNETSS_PTPPPSR0 Register ................................................................................ 4194
43-34. ETHERNETSS_PTPPPSR1 Register ................................................................................ 4195
43-35. ETHERNETSS_PTP_TSRL Register ................................................................................. 4196
43-36. ETHERNETSS_PTP_TSRH Register ................................................................................ 4197
43-37. ETHERNETSS_PTP_TSWL Register ................................................................................ 4198
43-38. ETHERNETSS_PTP_TSWH Register................................................................................ 4199
43-39. ETHERNETSS_REVMII_CTRL Register ............................................................................ 4200
43-40. MAC_Configuration Register .......................................................................................... 4226
43-41. MAC_Ext_Configuration Register ..................................................................................... 4232
43-42. MAC_Packet_Filter Register ........................................................................................... 4234
43-43. MAC_Watchdog_Timeout Register ................................................................................... 4237
43-44. MAC_Hash_Table_Reg0 Register .................................................................................... 4238
43-45. MAC_Hash_Table_Reg1 Register .................................................................................... 4239
43-46. MAC_VLAN_Tag_Ctrl Register........................................................................................ 4240
43-47. MAC_VLAN_Tag_Data Register ...................................................................................... 4242
43-48. MAC_VLAN_Hash_Table Register ................................................................................... 4244
43-49. MAC_VLAN_Incl Register .............................................................................................. 4245
43-50. MAC_Inner_VLAN_Incl Register ...................................................................................... 4247
43-51. MAC_Q0_Tx_Flow_Ctrl Register ..................................................................................... 4249
43-52. MAC_Rx_Flow_Ctrl Register .......................................................................................... 4251
43-53. MAC_RxQ_Ctrl4 Register .............................................................................................. 4252
43-54. MAC_RxQ_Ctrl0 Register .............................................................................................. 4254
43-55. MAC_RxQ_Ctrl1 Register .............................................................................................. 4255

SPRUII0B – May 2019 – Revised May 2020 List of Figures 75

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43-56. MAC_RxQ_Ctrl2 Register .............................................................................................. 4257

43-57. MAC_Interrupt_Status Register ....................................................................................... 4258
43-58. MAC_Interrupt_Enable Register ...................................................................................... 4261
43-59. MAC_Rx_Tx_Status Register ......................................................................................... 4263
43-60. MAC_PMT_Control_Status Register ................................................................................. 4265
43-61. MAC_RWK_Packet_Filter Register ................................................................................... 4269
43-62. MAC_LPI_Control_Status Register ................................................................................... 4270
43-63. MAC_LPI_Timers_Control Register .................................................................................. 4273
43-64. MAC_LPI_Entry_Timer Register ...................................................................................... 4274
43-65. MAC_1US_Tic_Counter Register ..................................................................................... 4275
43-66. MAC_Version Register ................................................................................................. 4276
43-67. MAC_Debug Register .................................................................................................. 4277
43-68. MAC_HW_Feature0 Register .......................................................................................... 4278
43-69. MAC_HW_Feature1 Register .......................................................................................... 4281
43-70. MAC_HW_Feature2 Register .......................................................................................... 4284
43-71. MAC_HW_Feature3 Register .......................................................................................... 4286
43-72. MAC_MDIO_Address Register ........................................................................................ 4288
43-73. MAC_MDIO_Data Register ............................................................................................ 4291
43-74. MAC_ARP_Address Register ......................................................................................... 4292
43-75. MAC_CSR_SW_Ctrl Register ......................................................................................... 4293
43-76. MAC_Ext_Cfg1 Register ............................................................................................... 4294
43-77. MAC_Address0_High Register ........................................................................................ 4295
43-78. MAC_Address0_Low Register......................................................................................... 4296
43-79. MAC_Address1_High Register ........................................................................................ 4297
43-80. MAC_Address1_Low Register......................................................................................... 4299
43-81. MAC_Address2_High Register ........................................................................................ 4300
43-82. MAC_Address2_Low Register......................................................................................... 4302
43-83. MAC_Address3_High Register ........................................................................................ 4303
43-84. MAC_Address3_Low Register......................................................................................... 4305
43-85. MAC_Address4_High Register ........................................................................................ 4306
43-86. MAC_Address4_Low Register......................................................................................... 4308
43-87. MAC_Address5_High Register ........................................................................................ 4309
43-88. MAC_Address5_Low Register......................................................................................... 4311
43-89. MAC_Address6_High Register ........................................................................................ 4312
43-90. MAC_Address6_Low Register......................................................................................... 4314
43-91. MAC_Address7_High Register ........................................................................................ 4315
43-92. MAC_Address7_Low Register......................................................................................... 4317
43-93. MMC_Control Register ................................................................................................. 4318
43-94. MMC_Rx_Interrupt Register ........................................................................................... 4320
43-95. MMC_Tx_Interrupt Register ........................................................................................... 4325
43-96. MMC_Rx_Interrupt_Mask Register ................................................................................... 4331
43-97. MMC_Tx_Interrupt_Mask Register ................................................................................... 4335
43-98. Tx_Octet_Count_Good_Bad Register ................................................................................ 4339
43-99. Tx_Packet_Count_Good_Bad Register .............................................................................. 4340
43-100. Tx_Broadcast_Packets_Good Register ............................................................................. 4341
43-101. Tx_Multicast_Packets_Good Register .............................................................................. 4342
43-102. Tx_64Octets_Packets_Good_Bad Register ........................................................................ 4343
43-103. Tx_65To127Octets_Packets_Good_Bad Register ................................................................ 4344
43-104. Tx_128To255Octets_Packets_Good_Bad Register ............................................................... 4345

76 List of Figures SPRUII0B – May 2019 – Revised May 2020

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43-105. Tx_256To511Octets_Packets_Good_Bad Register ............................................................... 4346

43-106. Tx_512To1023Octets_Packets_Good_Bad Register ............................................................. 4347
43-107. Tx_1024ToMaxOctets_Packets_Good_Bad Register ............................................................ 4348
43-108. Tx_Unicast_Packets_Good_Bad Register.......................................................................... 4349
43-109. Tx_Multicast_Packets_Good_Bad Register ........................................................................ 4350
43-110. Tx_Broadcast_Packets_Good_Bad Register ...................................................................... 4351
43-111. Tx_Underflow_Error_Packets Register ............................................................................. 4352
43-112. Tx_Single_Collision_Good_Packets Register ...................................................................... 4353
43-113. Tx_Multiple_Collision_Good_Packets Register .................................................................... 4354
43-114. Tx_Deferred_Packets Register ...................................................................................... 4355
43-115. Tx_Late_Collision_Packets Register ................................................................................ 4356
43-116. Tx_Excessive_Collision_Packets Register ......................................................................... 4357
43-117. Tx_Carrier_Error_Packets Register ................................................................................. 4358
43-118. Tx_Octet_Count_Good Register ..................................................................................... 4359
43-119. Tx_Packet_Count_Good Register ................................................................................... 4360
43-120. Tx_Excessive_Deferral_Error Register ............................................................................. 4361
43-121. Tx_Pause_Packets Register ......................................................................................... 4362
43-122. Tx_VLAN_Packets_Good Register .................................................................................. 4363
43-123. Tx_OSize_Packets_Good Register ................................................................................. 4364
43-124. Rx_Packets_Count_Good_Bad Register ........................................................................... 4365
43-125. Rx_Octet_Count_Good_Bad Register .............................................................................. 4366
43-126. Rx_Octet_Count_Good Register .................................................................................... 4367
43-127. Rx_Broadcast_Packets_Good Register ............................................................................ 4368
43-128. Rx_Multicast_Packets_Good Register .............................................................................. 4369
43-129. Rx_CRC_Error_Packets Register ................................................................................... 4370
43-130. Rx_Alignment_Error_Packets Register ............................................................................. 4371
43-131. Rx_Runt_Error_Packets Register ................................................................................... 4372
43-132. Rx_Jabber_Error_Packets Register ................................................................................. 4373
43-133. Rx_Undersize_Packets_Good Register ............................................................................ 4374
43-134. Rx_Oversize_Packets_Good Register .............................................................................. 4375
43-135. Rx_64Octets_Packets_Good_Bad Register ....................................................................... 4376
43-136. Rx_65To127Octets_Packets_Good_Bad Register ................................................................ 4377
43-137. Rx_128To255Octets_Packets_Good_Bad Register .............................................................. 4378
43-138. Rx_256To511Octets_Packets_Good_Bad Register .............................................................. 4379
43-139. Rx_512To1023Octets_Packets_Good_Bad Register ............................................................. 4380
43-140. Rx_1024ToMaxOctets_Packets_Good_Bad Register ............................................................ 4381
43-141. Rx_Unicast_Packets_Good Register................................................................................ 4382
43-142. Rx_Length_Error_Packets Register ................................................................................. 4383
43-143. Rx_Out_Of_Range_Type_Packets Register ....................................................................... 4384
43-144. Rx_Pause_Packets Register ......................................................................................... 4385
43-145. Rx_FIFO_Overflow_Packets Register .............................................................................. 4386
43-146. Rx_VLAN_Packets_Good_Bad Register ........................................................................... 4387
43-147. Rx_Watchdog_Error_Packets Register ............................................................................. 4388
43-148. Rx_Receive_Error_Packets Register ............................................................................... 4389
43-149. Rx_Control_Packets_Good Register ................................................................................ 4390
43-150. Tx_LPI_USEC_Cntr Register ........................................................................................ 4391
43-151. Tx_LPI_Tran_Cntr Register .......................................................................................... 4392
43-152. Rx_LPI_USEC_Cntr Register ........................................................................................ 4393
43-153. Rx_LPI_Tran_Cntr Register .......................................................................................... 4394

SPRUII0B – May 2019 – Revised May 2020 List of Figures 77

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43-154. MMC_IPC_Rx_Interrupt_Mask Register ............................................................................ 4395

43-155. MMC_IPC_Rx_Interrupt Register .................................................................................... 4399
43-156. RxIPv4_Good_Packets Register ..................................................................................... 4404
43-157. RxIPv4_Header_Error_Packets Register ........................................................................... 4405
43-158. RxIPv4_No_Payload_Packets Register............................................................................. 4406
43-159. RxIPv4_Fragmented_Packets Register ............................................................................. 4407
43-160. RxIPv4_UDP_Checksum_Disabled_Packets Register ........................................................... 4408
43-161. RxIPv6_Good_Packets Register ..................................................................................... 4409
43-162. RxIPv6_Header_Error_Packets Register ........................................................................... 4410
43-163. RxIPv6_No_Payload_Packets Register............................................................................. 4411
43-164. RxUDP_Good_Packets Register .................................................................................... 4412
43-165. RxUDP_Error_Packets Register ..................................................................................... 4413
43-166. RxTCP_Good_Packets Register ..................................................................................... 4414
43-167. RxTCP_Error_Packets Register ..................................................................................... 4415
43-168. RxICMP_Good_Packets Register ................................................................................... 4416
43-169. RxICMP_Error_Packets Register .................................................................................... 4417
43-170. RxIPv4_Good_Octets Register ...................................................................................... 4418
43-171. RxIPv4_Header_Error_Octets Register ............................................................................. 4419
43-172. RxIPv4_No_Payload_Octets Register .............................................................................. 4420
43-173. RxIPv4_Fragmented_Octets Register .............................................................................. 4421
43-174. RxIPv4_UDP_Checksum_Disable_Octets Register ............................................................... 4422
43-175. RxIPv6_Good_Octets Register ...................................................................................... 4423
43-176. RxIPv6_Header_Error_Octets Register ............................................................................. 4424
43-177. RxIPv6_No_Payload_Octets Register .............................................................................. 4425
43-178. RxUDP_Good_Octets Register ...................................................................................... 4426
43-179. RxUDP_Error_Octets Register ....................................................................................... 4427
43-180. RxTCP_Good_Octets Register ...................................................................................... 4428
43-181. RxTCP_Error_Octets Register ....................................................................................... 4429
43-182. RxICMP_Good_Octets Register ..................................................................................... 4430
43-183. RxICMP_Error_Octets Register ...................................................................................... 4431
43-184. MAC_L3_L4_Control0 Register ...................................................................................... 4432
43-185. MAC_Layer4_Address0 Register .................................................................................... 4435
43-186. MAC_Layer3_Addr0_Reg0 Register ................................................................................ 4436
43-187. MAC_Layer3_Addr1_Reg0 Register ................................................................................ 4437
43-188. MAC_Layer3_Addr2_Reg0 Register ................................................................................ 4438
43-189. MAC_Layer3_Addr3_Reg0 Register ................................................................................ 4439
43-190. MAC_L3_L4_Control1 Register ...................................................................................... 4440
43-191. MAC_Layer4_Address1 Register .................................................................................... 4443
43-192. MAC_Layer3_Addr0_Reg1 Register ................................................................................ 4444
43-193. MAC_Layer3_Addr1_Reg1 Register ................................................................................ 4445
43-194. MAC_Layer3_Addr2_Reg1 Register ................................................................................ 4446
43-195. MAC_Layer3_Addr3_Reg1 Register ................................................................................ 4447
43-196. MAC_L3_L4_Control2 Register ...................................................................................... 4448
43-197. MAC_Layer4_Address2 Register .................................................................................... 4451
43-198. MAC_Layer3_Addr0_Reg2 Register ................................................................................ 4452
43-199. MAC_Layer3_Addr1_Reg2 Register ................................................................................ 4453
43-200. MAC_Layer3_Addr2_Reg2 Register ................................................................................ 4454
43-201. MAC_Layer3_Addr3_Reg2 Register ................................................................................ 4455
43-202. MAC_L3_L4_Control3 Register ...................................................................................... 4456

78 List of Figures SPRUII0B – May 2019 – Revised May 2020

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43-203. MAC_Layer4_Address3 Register .................................................................................... 4459

43-204. MAC_Layer3_Addr0_Reg3 Register ................................................................................ 4460
43-205. MAC_Layer3_Addr1_Reg3 Register ................................................................................ 4461
43-206. MAC_Layer3_Addr2_Reg3 Register ................................................................................ 4462
43-207. MAC_Layer3_Addr3_Reg3 Register ................................................................................ 4463
43-208. MAC_Timestamp_Control Register.................................................................................. 4464
43-209. MAC_Sub_Second_Increment Register ............................................................................ 4468
43-210. MAC_System_Time_Seconds Register............................................................................. 4469
43-211. MAC_System_Time_Nanoseconds Register....................................................................... 4470
43-212. MAC_System_Time_Seconds_Update Register .................................................................. 4471
43-213. MAC_System_Time_Nanoseconds_Update Register ............................................................ 4472
43-214. MAC_Timestamp_Addend Register ................................................................................. 4473
43-215. MAC_System_Time_Higher_Word_Seconds Register ........................................................... 4474
43-216. MAC_Timestamp_Status Register................................................................................... 4475
43-217. MAC_Tx_Timestamp_Status_Nanoseconds Register ............................................................ 4478
43-218. MAC_Tx_Timestamp_Status_Seconds Register .................................................................. 4479
43-219. MAC_Auxiliary_Control Register ..................................................................................... 4480
43-220. MAC_Auxiliary_Timestamp_Nanoseconds Register .............................................................. 4481
43-221. MAC_Auxiliary_Timestamp_Seconds Register .................................................................... 4482
43-222. MAC_Timestamp_Ingress_Asym_Corr Register .................................................................. 4483
43-223. MAC_Timestamp_Egress_Asym_Corr Register ................................................................... 4484
43-224. MAC_Timestamp_Ingress_Corr_Nanosecond Register .......................................................... 4485
43-225. MAC_Timestamp_Egress_Corr_Nanosecond Register .......................................................... 4486
43-226. MAC_Timestamp_Ingress_Corr_Subnanosec Register .......................................................... 4487
43-227. MAC_Timestamp_Egress_Corr_Subnanosec Register........................................................... 4488
43-228. MAC_PPS_Control Register ......................................................................................... 4489
43-229. MAC_PPS0_Target_Time_Seconds Register ..................................................................... 4492
43-230. MAC_PPS0_Target_Time_Nanoseconds Register ............................................................... 4493
43-231. MAC_PPS0_Interval Register ........................................................................................ 4494
43-232. MAC_PPS0_Width Register .......................................................................................... 4495
43-233. MAC_PPS1_Target_Time_Seconds Register ..................................................................... 4496
43-234. MAC_PPS1_Target_Time_Nanoseconds Register ............................................................... 4497
43-235. MAC_PPS1_Interval Register ........................................................................................ 4498
43-236. MAC_PPS1_Width Register .......................................................................................... 4499
43-237. MAC_PTO_Control Register ......................................................................................... 4500
43-238. MAC_Source_Port_Identity0 Register .............................................................................. 4502
43-239. MAC_Source_Port_Identity1 Register .............................................................................. 4503
43-240. MAC_Source_Port_Identity2 Register .............................................................................. 4504
43-241. MAC_Log_Message_Interval Register .............................................................................. 4505
43-242. MTL_Operation_Mode Register...................................................................................... 4506
43-243. MTL_DBG_CTL Register ............................................................................................. 4508
43-244. MTL_DBG_STS Register ............................................................................................. 4511
43-245. MTL_FIFO_Debug_Data Register ................................................................................... 4513
43-246. MTL_Interrupt_Status Register ...................................................................................... 4514
43-247. MTL_RxQ_DMA_Map0 Register .................................................................................... 4515
43-248. MTL_TxQ0_Operation_Mode Register ............................................................................. 4517
43-249. MTL_TxQ0_Underflow Register ..................................................................................... 4519
43-250. MTL_TxQ0_Debug Register .......................................................................................... 4520
43-251. MTL_TxQ0_ETS_Status Register ................................................................................... 4522

SPRUII0B – May 2019 – Revised May 2020 List of Figures 79

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43-252. MTL_TxQ0_Quantum_Weight Register............................................................................. 4523

43-253. MTL_Q0_Interrupt_Control_Status Register ....................................................................... 4524
43-254. MTL_RxQ0_Operation_Mode Register ............................................................................. 4526
43-255. MTL_RxQ0_Missed_Packet_Overflow_Cnt Register ............................................................. 4529
43-256. MTL_RxQ0_Debug Register ......................................................................................... 4530
43-257. MTL_RxQ0_Control Register......................................................................................... 4531
43-258. MTL_TxQ1_Operation_Mode Register ............................................................................. 4532
43-259. MTL_TxQ1_Underflow Register ..................................................................................... 4534
43-260. MTL_TxQ1_Debug Register .......................................................................................... 4535
43-261. MTL_TxQ1_ETS_Status Register ................................................................................... 4537
43-262. MTL_TxQ1_Quantum_Weight Register............................................................................. 4538
43-263. MTL_Q1_Interrupt_Control_Status Register ....................................................................... 4539
43-264. MTL_RxQ1_Operation_Mode Register ............................................................................. 4541
43-265. MTL_RxQ1_Missed_Packet_Overflow_Cnt Register ............................................................. 4544
43-266. MTL_RxQ1_Debug Register ......................................................................................... 4545
43-267. MTL_RxQ1_Control Register......................................................................................... 4546
43-268. DMA_Mode Register .................................................................................................. 4547
43-269. DMA_SysBus_Mode Register ........................................................................................ 4549
43-270. DMA_Interrupt_Status Register ...................................................................................... 4551
43-271. DMA_Debug_Status0 Register ...................................................................................... 4553
43-272. DMA_CH0_Control Register ......................................................................................... 4555
43-273. DMA_CH0_Tx_Control Register ..................................................................................... 4557
43-274. DMA_CH0_Rx_Control Register ..................................................................................... 4559
43-275. DMA_CH0_TxDesc_List_Address Register ........................................................................ 4561
43-276. DMA_CH0_RxDesc_List_Address Register ........................................................................ 4562
43-277. DMA_CH0_TxDesc_Tail_Pointer Register ......................................................................... 4563
43-278. DMA_CH0_RxDesc_Tail_Pointer Register ......................................................................... 4564
43-279. DMA_CH0_TxDesc_Ring_Length Register ........................................................................ 4565
43-280. DMA_CH0_RxDesc_Ring_Length Register ........................................................................ 4566
43-281. DMA_CH0_Interrupt_Enable Register .............................................................................. 4567
43-282. DMA_CH0_Rx_Interrupt_Watchdog_Timer Register ............................................................. 4569
43-283. DMA_CH0_Current_App_TxDesc Register ........................................................................ 4570
43-284. DMA_CH0_Current_App_RxDesc Register ........................................................................ 4571
43-285. DMA_CH0_Current_App_TxBuffer Register ....................................................................... 4572
43-286. DMA_CH0_Current_App_RxBuffer Register ....................................................................... 4573
43-287. DMA_CH0_Status Register .......................................................................................... 4574
43-288. DMA_CH0_Miss_Frame_Cnt Register .............................................................................. 4578
43-289. DMA_CH0_RX_ERI_Cnt Register ................................................................................... 4579
43-290. DMA_CH1_Control Register ......................................................................................... 4580
43-291. DMA_CH1_Tx_Control Register ..................................................................................... 4582
43-292. DMA_CH1_Rx_Control Register ..................................................................................... 4584
43-293. DMA_CH1_TxDesc_List_Address Register ........................................................................ 4586
43-294. DMA_CH1_RxDesc_List_Address Register ........................................................................ 4587
43-295. DMA_CH1_TxDesc_Tail_Pointer Register ......................................................................... 4588
43-296. DMA_CH1_RxDesc_Tail_Pointer Register ......................................................................... 4589
43-297. DMA_CH1_TxDesc_Ring_Length Register ........................................................................ 4590
43-298. DMA_CH1_RxDesc_Ring_Length Register ........................................................................ 4591
43-299. DMA_CH1_Interrupt_Enable Register .............................................................................. 4592
43-300. DMA_CH1_Rx_Interrupt_Watchdog_Timer Register ............................................................. 4594

80 List of Figures SPRUII0B – May 2019 – Revised May 2020

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43-301. DMA_CH1_Current_App_TxDesc Register ........................................................................ 4595

43-302. DMA_CH1_Current_App_RxDesc Register ........................................................................ 4596
43-303. DMA_CH1_Current_App_TxBuffer Register ....................................................................... 4597
43-304. DMA_CH1_Current_App_RxBuffer Register ....................................................................... 4598
43-305. DMA_CH1_Status Register .......................................................................................... 4599
43-306. DMA_CH1_Miss_Frame_Cnt Register .............................................................................. 4603
43-307. DMA_CH1_RX_ERI_Cnt Register ................................................................................... 4604
44-1. GCRC Block Diagram .................................................................................................. 4607
44-2. CRC Sequence Flow ................................................................................................... 4608
44-3. CRCCTRL Register ..................................................................................................... 4613
44-4. CRCPOLY Register ..................................................................................................... 4614
44-5. CRCDATAMASK Register ............................................................................................. 4615
44-6. CRCDATAIN Register .................................................................................................. 4616
44-7. CRCDATAOUT Register ............................................................................................... 4617
44-8. CRCDATATRANS Register ............................................................................................ 4618
45-1. MCAN Module Overview ............................................................................................... 4620
45-2. MCAN Typical Application ............................................................................................. 4622
45-3. MCAN Integration ....................................................................................................... 4624
45-4. MCAN Block Diagram .................................................................................................. 4626
45-5. CAN FD Frame .......................................................................................................... 4629
45-6. CAN Bit Timing .......................................................................................................... 4630
45-7. Transmitter Delay Measurement ...................................................................................... 4631
45-8. Connection of Signals in Bus Monitoring Mode ..................................................................... 4633
45-9. Internal Loop Back Mode ............................................................................................... 4635
45-10. External Timestamp Counter Interrupt ............................................................................... 4636
45-11. Standard Message ID Filter Path ..................................................................................... 4641
45-12. Extended Message ID Filter Path ..................................................................................... 4642
45-13. Rx FIFO Status .......................................................................................................... 4643
45-14. Rx FIFO Overflow Handling ............................................................................................ 4644
45-15. Message RAM Configuration .......................................................................................... 4646
45-16. Rx Buffer/Rx FIFO Element Structure ................................................................................ 4646
45-17. Tx Buffer Element Structure ........................................................................................... 4648
45-18. Tx Event FIFO Element Structure ..................................................................................... 4650
45-19. Standard Message ID Filter Element Structure ..................................................................... 4651
45-20. Extended Message ID Filter Element Structure ..................................................................... 4653
45-21. MCAN_CREL Register ................................................................................................. 4658
45-22. MCAN_ENDN Register ................................................................................................. 4659
45-23. MCAN_DBTP Register ................................................................................................. 4660
45-24. MCAN_TEST Register.................................................................................................. 4662
45-25. MCAN_RWD Register .................................................................................................. 4663
45-26. MCAN_CCCR Register ................................................................................................. 4664
45-27. MCAN_NBTP Register ................................................................................................. 4667
45-28. MCAN_TSCC Register ................................................................................................. 4669
45-29. MCAN_TSCV Register ................................................................................................. 4670
45-30. MCAN_TOCC Register ................................................................................................. 4671
45-31. MCAN_TOCV Register ................................................................................................. 4672
45-32. MCAN_ECR Register ................................................................................................... 4673
45-33. MCAN_PSR Register ................................................................................................... 4674
45-34. MCAN_TDCR Register ................................................................................................. 4677

SPRUII0B – May 2019 – Revised May 2020 List of Figures 81

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45-35. MCAN_IR Register ...................................................................................................... 4678

45-36. MCAN_IE Register ...................................................................................................... 4681
45-37. MCAN_ILS Register .................................................................................................... 4683
45-38. MCAN_ILE Register .................................................................................................... 4686
45-39. MCAN_GFC Register ................................................................................................... 4687
45-40. MCAN_SIDFC Register ................................................................................................ 4688
45-41. MCAN_XIDFC Register ................................................................................................ 4689
45-42. MCAN_XIDAM Register ................................................................................................ 4690
45-43. MCAN_HPMS Register ................................................................................................. 4691
45-44. MCAN_NDAT1 Register ................................................................................................ 4692
45-45. MCAN_NDAT2 Register ................................................................................................ 4695
45-46. MCAN_RXF0C Register ................................................................................................ 4698
45-47. MCAN_RXF0S Register ................................................................................................ 4699
45-48. MCAN_RXF0A Register ................................................................................................ 4700
45-49. MCAN_RXBC Register ................................................................................................. 4701
45-50. MCAN_RXF1C Register ................................................................................................ 4702
45-51. MCAN_RXF1S Register ................................................................................................ 4703
45-52. MCAN_RXF1A Register ................................................................................................ 4704
45-53. MCAN_RXESC Register ............................................................................................... 4705
45-54. MCAN_TXBC Register ................................................................................................. 4707
45-55. MCAN_TXFQS Register ............................................................................................... 4709
45-56. MCAN_TXESC Register ............................................................................................... 4710
45-57. MCAN_TXBRP Register ............................................................................................... 4711
45-58. MCAN_TXBAR Register ............................................................................................... 4714
45-59. MCAN_TXBCR Register ............................................................................................... 4716
45-60. MCAN_TXBTO Register ............................................................................................... 4718
45-61. MCAN_TXBCF Register ................................................................................................ 4720
45-62. MCAN_TXBTIE Register ............................................................................................... 4722
45-63. MCAN_TXBCIE Register ............................................................................................... 4726
45-64. MCAN_TXEFC Register ................................................................................................ 4730
45-65. MCAN_TXEFS Register ................................................................................................ 4731
45-66. MCAN_TXEFA Register ................................................................................................ 4732
45-67. MCANSS_PID Register ................................................................................................ 4734
45-68. MCANSS_CTRL Register .............................................................................................. 4735
45-69. MCANSS_STAT Register .............................................................................................. 4736
45-70. MCANSS_ICS Register ................................................................................................ 4737
45-71. MCANSS_IRS Register ................................................................................................ 4738
45-72. MCANSS_IECS Register............................................................................................... 4739
45-73. MCANSS_IE Register .................................................................................................. 4740
45-74. MCANSS_IES Register................................................................................................. 4741
45-75. MCANSS_EOI Register ................................................................................................ 4742
45-76. MCANSS_EXT_TS_PRESCALER Register ......................................................................... 4743
45-77. MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Register ....................................................... 4744
45-78. MCANERR_REV Register ............................................................................................. 4747
45-79. MCANERR_VECTOR Register........................................................................................ 4748
45-80. MCANERR_STAT Register ............................................................................................ 4749
45-81. MCANERR_WRAP_REV Register .................................................................................... 4750
45-82. MCANERR_CTRL Register ............................................................................................ 4751
45-83. MCANERR_ERR_CTRL1 Register ................................................................................... 4753

82 List of Figures SPRUII0B – May 2019 – Revised May 2020

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45-84. MCANERR_ERR_CTRL2 Register ................................................................................... 4754

45-85. MCANERR_ERR_STAT1 Register ................................................................................... 4755
45-86. MCANERR_ERR_STAT2 Register ................................................................................... 4757
45-87. MCANERR_ERR_STAT3 Register ................................................................................... 4758
45-88. MCANERR_SEC_EOI Register ....................................................................................... 4759
45-89. MCANERR_SEC_STATUS Register ................................................................................. 4760
45-90. MCANERR_SEC_ENABLE_SET Register .......................................................................... 4761
45-91. MCANERR_SEC_ENABLE_CLR Register .......................................................................... 4762
45-92. MCANERR_DED_EOI Register ....................................................................................... 4763
45-93. MCANERR_DED_STATUS Register ................................................................................. 4764
45-94. MCANERR_DED_ENABLE_SET Register .......................................................................... 4765
45-95. MCANERR_DED_ENABLE_CLR Register .......................................................................... 4766
45-96. MCANERR_AGGR_ENABLE_SET Register ........................................................................ 4767
45-97. MCANERR_AGGR_ENABLE_CLR Register ........................................................................ 4768
45-98. MCANERR_AGGR_STATUS_SET Register ........................................................................ 4769
45-99. MCANERR_AGGR_STATUS_CLR Register ........................................................................ 4770
46-1. I2C Block Diagram ...................................................................................................... 4773
46-2. I2C Bus Configuration .................................................................................................. 4774
46-3. START and STOP Conditions ......................................................................................... 4774
46-4. Complete Data Transfer With a 7-Bit Address ...................................................................... 4775
46-5. R/S Bit in First Byte ..................................................................................................... 4775
46-6. Data Validity During Bit Transfer on the I2C Bus ................................................................... 4775
46-7. High-Speed Data Format ............................................................................................... 4780
46-8. Master Single Transmit ................................................................................................. 4784
46-9. Master Single Receive .................................................................................................. 4785
46-10. Master Transmit of Multiple Data Bytes .............................................................................. 4786
46-11. Master Receive of Multiple Data Bytes ............................................................................... 4787
46-12. Master Receive With Repeated START After Master Transmit ................................................... 4788
46-13. Master Transmit With Repeated START After Master Receive ................................................... 4788
46-14. Standard High-Speed Mode Master Transmit ....................................................................... 4789
46-15. Slave Command Sequence ............................................................................................ 4790
46-16. I2CMSA Register ........................................................................................................ 4795
46-17. I2CMCS Register ........................................................................................................ 4796
46-18. I2CMDR Register........................................................................................................ 4798
46-19. I2CMTPR Register ...................................................................................................... 4799
46-20. I2CMIMR Register....................................................................................................... 4800
46-21. I2CMRIS Register ....................................................................................................... 4802
46-22. I2CMMIS Register ....................................................................................................... 4804
46-23. I2CMICR Register ....................................................................................................... 4806
46-24. I2CMCR Register........................................................................................................ 4808
46-25. I2CMCLKOCNT Register............................................................................................... 4809
46-26. I2CMBMON Register ................................................................................................... 4810
46-27. I2CMBLEN Register .................................................................................................... 4811
46-28. I2CMBCNT Register .................................................................................................... 4812
46-29. I2CSOAR Register ...................................................................................................... 4813
46-30. I2CSCSR Register ...................................................................................................... 4814
46-31. I2CSDR Register ........................................................................................................ 4816
46-32. I2CSIMR Register ....................................................................................................... 4817
46-33. I2CSRIS Register ....................................................................................................... 4819

SPRUII0B – May 2019 – Revised May 2020 List of Figures 83

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46-34. I2CSMIS Register ....................................................................................................... 4821

46-35. I2CSICR Register ....................................................................................................... 4823
46-36. I2CSOAR2 Register..................................................................................................... 4825
46-37. I2CSACKCTL Register ................................................................................................. 4826
46-38. I2CFIFODATARX Register ............................................................................................. 4827
46-39. I2CFIFOCTL Register .................................................................................................. 4828
46-40. I2CFIFOSTATUS Register ............................................................................................. 4830
46-41. I2CPP Register .......................................................................................................... 4831
46-42. I2CPC Register .......................................................................................................... 4832
46-43. I2CMCS_WRITE Register.............................................................................................. 4834
46-44. I2CSCSR_WRITE Register ............................................................................................ 4836
46-45. I2CFIFODATATX Register ............................................................................................. 4837
47-1. SSI Block Diagram ...................................................................................................... 4840
47-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................................... 4843
47-3. TI Synchronous Serial Frame Format (Continuous Transfer) ..................................................... 4843
47-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ............................................... 4844
47-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ......................................... 4844
47-6. Freescale SPI Frame Format with SPO =0 and SPH=1 .......................................................... 4845
47-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ....................................... 4845
47-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ................................. 4845
47-9. Freescale SPI Frame Format with SPO =1 and SPH =1 .......................................................... 4846
47-10. SSICR0 Register ........................................................................................................ 4852
47-11. SSICR1 Register ........................................................................................................ 4854
47-12. SSIDR Register .......................................................................................................... 4856
47-13. SSISR Register .......................................................................................................... 4857
47-14. SSICPSR Register ...................................................................................................... 4858
47-15. SSIIM Register........................................................................................................... 4859
47-16. SSIRIS Register ......................................................................................................... 4860
47-17. SSIMIS Register ......................................................................................................... 4862
47-18. SSIICR Register ......................................................................................................... 4864
47-19. SSIDMACTL Register .................................................................................................. 4865
47-20. SSIPV Register .......................................................................................................... 4866
47-21. SSIPP Register .......................................................................................................... 4867
47-22. SSIPC Register .......................................................................................................... 4868
47-23. SSIPeriphID4 Register.................................................................................................. 4869
47-24. SSIPeriphID5 Register.................................................................................................. 4870
47-25. SSIPeriphID6 Register.................................................................................................. 4871
47-26. SSIPeriphID7 Register.................................................................................................. 4872
47-27. SSIPeriphID0 Register.................................................................................................. 4873
47-28. SSIPeriphID1 Register.................................................................................................. 4874
47-29. SSIPeriphID2 Register.................................................................................................. 4875
47-30. SSIPeriphID3 Register.................................................................................................. 4876
47-31. SSIPCellID0 Register ................................................................................................... 4877
47-32. SSIPCellID1 Register ................................................................................................... 4878
47-33. SSIPCellID2 Register ................................................................................................... 4879
47-34. SSIPCellID3 Register ................................................................................................... 4880
48-1. UART Module Block Diagram ......................................................................................... 4883
48-2. UART Character Frame ................................................................................................ 4884
48-3. IrDA Data Modulation ................................................................................................... 4885

84 List of Figures SPRUII0B – May 2019 – Revised May 2020

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48-4. UARTDR Register ....................................................................................................... 4892

48-5. UARTRSR Register ..................................................................................................... 4894
48-6. UARTFR Register ....................................................................................................... 4895
48-7. UARTILPR Register..................................................................................................... 4897
48-8. UARTIBRD Register .................................................................................................... 4898
48-9. UARTFBRD Register ................................................................................................... 4899
48-10. UARTLCRH Register ................................................................................................... 4900
48-11. UARTCTL Register ..................................................................................................... 4902
48-12. UARTIFLS Register ..................................................................................................... 4904
48-13. UARTIM Register........................................................................................................ 4905
48-14. UARTRIS Register ...................................................................................................... 4907
48-15. UARTMIS Register ...................................................................................................... 4909
48-16. UARTICR Register ...................................................................................................... 4911
48-17. UARTDMACTL Register ............................................................................................... 4913
48-18. UART9BITADDR Register ............................................................................................. 4914
48-19. UART9BITAMASK Register ........................................................................................... 4915
48-20. UARTPP Register ....................................................................................................... 4916
48-21. UARTPeriphID4 Register............................................................................................... 4917
48-22. UARTPeriphID5 Register............................................................................................... 4918
48-23. UARTPeriphID6 Register............................................................................................... 4919
48-24. UARTPeriphID7 Register............................................................................................... 4920
48-25. UARTPeriphID0 Register............................................................................................... 4921
48-26. UARTPeriphID1 Register............................................................................................... 4922
48-27. UARTPeriphID2 Register............................................................................................... 4923
48-28. UARTPeriphID3 Register............................................................................................... 4924
48-29. UARTPCellID0 Register ................................................................................................ 4925
48-30. UARTPCellID1 Register ................................................................................................ 4926
48-31. UARTPCellID2 Register ................................................................................................ 4927
48-32. UARTPCellID3 Register ................................................................................................ 4928
48-33. UARTECR Register ..................................................................................................... 4930
49-1. µDMA Block Diagram ................................................................................................... 4933
49-2. Example of Ping-Pong µDMA Transaction........................................................................... 4939
49-3. Memory Scatter-Gather, Setup and Configuration .................................................................. 4941
49-4. Memory Scatter-Gather, µDMA Copy Sequence ................................................................... 4942
49-5. Peripheral Scatter-Gather, Setup and Configuration ............................................................... 4943
49-6. Peripheral Scatter-Gather, µDMA Copy Sequence ................................................................. 4944
49-7. DMASTAT Register ..................................................................................................... 4955
49-8. DMACFG Register ...................................................................................................... 4956
49-9. DMACTLBASE Register ................................................................................................ 4957
49-10. DMAALTBASE Register ................................................................................................ 4958
49-11. DMASWREQ Register .................................................................................................. 4959
49-12. DMAUSEBURSTSET Register ........................................................................................ 4960
49-13. DMAUSEBURSTCLR Register ........................................................................................ 4961
49-14. DMAREQMASKSET Register ......................................................................................... 4962
49-15. DMAREQMASKCLR Register ......................................................................................... 4963
49-16. DMAENASET Register ................................................................................................. 4964
49-17. DMAENACLR Register ................................................................................................. 4965
49-18. DMAALTSET Register .................................................................................................. 4966
49-19. DMAALTCLR Register.................................................................................................. 4967

SPRUII0B – May 2019 – Revised May 2020 List of Figures 85

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49-20. DMAPRIOSET Register ................................................................................................ 4968

49-21. DMAPRIOCLR Register ................................................................................................ 4969
49-22. DMAERRCLR Register ................................................................................................. 4970
49-23. DMACHMAP0 Register ................................................................................................. 4971
49-24. DMACHMAP1 Register ................................................................................................. 4972
49-25. DMACHMAP2 Register ................................................................................................. 4973
49-26. DMACHMAP3 Register ................................................................................................. 4974
49-27. DMAPeriphID4 Register ................................................................................................ 4975
49-28. DMAPeriphID0 Register ................................................................................................ 4976
49-29. DMAPeriphID1 Register ................................................................................................ 4977
49-30. DMAPeriphID2 Register ................................................................................................ 4978
49-31. DMAPeriphID3 Register ................................................................................................ 4979
49-32. DMAPCellID0 Register ................................................................................................. 4980
49-33. DMAPCellID1 Register ................................................................................................. 4981
49-34. DMAPCellID2 Register ................................................................................................. 4982
49-35. DMAPCellID3 Register ................................................................................................. 4983
49-36. DMASRCENDP Register ............................................................................................... 4985
49-37. DMADSTENDP Register ............................................................................................... 4986
49-38. DMACHCTL Register ................................................................................................... 4987

86 List of Figures SPRUII0B – May 2019 – Revised May 2020

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List of Tables
2-1. C2000Ware Root Directories ............................................................................................ 156
3-1. Reset Signals.............................................................................................................. 160
3-2. PIE Channel Mapping .................................................................................................... 168
3-3. CPU Interrupt Vectors .................................................................................................... 171
3-4. PIE Interrupt Vectors ..................................................................................................... 172
3-5. Access to EALLOW-Protected Registers .............................................................................. 178
3-6. Clock Connections Sorted by Clock Domain .......................................................................... 188
3-7. Example Watchdog Key Sequences ................................................................................... 196
3-8. Local Shared RAM........................................................................................................ 200
3-9. Global Shared RAM ...................................................................................................... 200
3-10. Error Handling in Different Scenarios .................................................................................. 206
3-11. Mapping of ECC Bits in Read Data from ECC/Parity Address Map ............................................... 207
3-12. Mapping of Parity Bits in Read Data from ECC/Parity Address Map .............................................. 207
3-13. SYSCTRL Base Address Table (C28) ................................................................................. 210
3-14. CLK_CFG_REGS Registers ............................................................................................ 211
3-15. CLK_CFG_REGS Access Type Codes ................................................................................ 211
3-16. CLKSEM Register Field Descriptions .................................................................................. 213
3-17. CLKCFGLOCK1 Register Field Descriptions ......................................................................... 214
3-18. CLKSRCCTL1 Register Field Descriptions............................................................................ 217
3-19. CLKSRCCTL2 Register Field Descriptions............................................................................ 219
3-20. CLKSRCCTL3 Register Field Descriptions............................................................................ 221
3-21. SYSPLLCTL1 Register Field Descriptions ............................................................................ 222
3-22. SYSPLLMULT Register Field Descriptions............................................................................ 223
3-23. SYSPLLSTS Register Field Descriptions .............................................................................. 225
3-24. AUXPLLCTL1 Register Field Descriptions ............................................................................ 226
3-25. AUXPLLMULT Register Field Descriptions ........................................................................... 227
3-26. AUXPLLSTS Register Field Descriptions.............................................................................. 229
3-27. SYSCLKDIVSEL Register Field Descriptions ......................................................................... 230
3-28. AUXCLKDIVSEL Register Field Descriptions ......................................................................... 231
3-29. PERCLKDIVSEL Register Field Descriptions ......................................................................... 232
3-30. XCLKOUTDIVSEL Register Field Descriptions ....................................................................... 233
3-31. CLBCLKCTL Register Field Descriptions.............................................................................. 234
3-32. LOSPCP Register Field Descriptions .................................................................................. 236
3-33. MCDCR Register Field Descriptions ................................................................................... 237
3-34. X1CNT Register Field Descriptions .................................................................................... 238
3-35. XTALCR Register Field Descriptions .................................................................................. 239
3-36. ETHERCATCLKCTL Register Field Descriptions .................................................................... 240
3-37. CMCLKCTL Register Field Descriptions............................................................................... 241
3-38. CM_CONF_REGS Registers............................................................................................ 242
3-39. CM_CONF_REGS Access Type Codes ............................................................................... 242
3-40. CMRESCTL Register Field Descriptions .............................................................................. 243
3-41. CMTOCPU1NMICTL Register Field Descriptions .................................................................... 244
3-42. CMTOCPU1INTCTL Register Field Descriptions..................................................................... 245
3-43. PALLOCATE0 Register Field Descriptions ............................................................................ 246
3-44. CM_CONF_REGS_LOCK Register Field Descriptions .............................................................. 247
3-45. ACCESS_PROTECTION_REGS Registers ........................................................................... 248
3-46. ACCESS_PROTECTION_REGS Access Type Codes .............................................................. 248

SPRUII0B – May 2019 – Revised May 2020 List of Tables 87

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3-47. NMAVFLG Register Field Descriptions ................................................................................ 250

3-48. NMAVSET Register Field Descriptions ................................................................................ 251
3-49. NMAVCLR Register Field Descriptions ................................................................................ 252
3-50. NMAVINTEN Register Field Descriptions ............................................................................. 253
3-51. NMCPURDAVADDR Register Field Descriptions .................................................................... 254
3-52. NMCPUWRAVADDR Register Field Descriptions ................................................................... 255
3-53. NMCPUFAVADDR Register Field Descriptions ...................................................................... 256
3-54. NMDMAWRAVADDR Register Field Descriptions ................................................................... 257
3-55. NMCLA1RDAVADDR Register Field Descriptions ................................................................... 258
3-56. NMCLA1WRAVADDR Register Field Descriptions .................................................................. 259
3-57. NMCLA1FAVADDR Register Field Descriptions ..................................................................... 260
3-58. NMDMARDAVADDR Register Field Descriptions .................................................................... 261
3-59. MAVFLG Register Field Descriptions .................................................................................. 262
3-60. MAVSET Register Field Descriptions .................................................................................. 263
3-61. MAVCLR Register Field Descriptions .................................................................................. 264
3-62. MAVINTEN Register Field Descriptions ............................................................................... 265
3-63. MCPUFAVADDR Register Field Descriptions ........................................................................ 266
3-64. MCPUWRAVADDR Register Field Descriptions ..................................................................... 267
3-65. MDMAWRAVADDR Register Field Descriptions ..................................................................... 268
3-66. CPU_SYS_REGS Registers ............................................................................................ 269
3-67. CPU_SYS_REGS Access Type Codes ................................................................................ 269
3-68. CPUSYSLOCK1 Register Field Descriptions ......................................................................... 271
3-69. CPUSYSLOCK2 Register Field Descriptions ......................................................................... 274
3-70. PIEVERRADDR Register Field Descriptions .......................................................................... 275
3-71. PCLKCR0 Register Field Descriptions ................................................................................. 276
3-72. PCLKCR1 Register Field Descriptions ................................................................................. 278
3-73. PCLKCR2 Register Field Descriptions ................................................................................. 279
3-74. PCLKCR3 Register Field Descriptions ................................................................................. 281
3-75. PCLKCR4 Register Field Descriptions ................................................................................. 282
3-76. PCLKCR6 Register Field Descriptions ................................................................................. 283
3-77. PCLKCR7 Register Field Descriptions ................................................................................. 284
3-78. PCLKCR8 Register Field Descriptions ................................................................................. 285
3-79. PCLKCR9 Register Field Descriptions ................................................................................. 286
3-80. PCLKCR10 Register Field Descriptions ............................................................................... 287
3-81. PCLKCR11 Register Field Descriptions ............................................................................... 288
3-82. PCLKCR13 Register Field Descriptions ............................................................................... 289
3-83. PCLKCR14 Register Field Descriptions ............................................................................... 290
3-84. PCLKCR16 Register Field Descriptions ............................................................................... 292
3-85. PCLKCR17 Register Field Descriptions ............................................................................... 293
3-86. PCLKCR18 Register Field Descriptions ............................................................................... 294
3-87. PCLKCR20 Register Field Descriptions ............................................................................... 296
3-88. PCLKCR21 Register Field Descriptions ............................................................................... 297
3-89. PCLKCR22 Register Field Descriptions ............................................................................... 298
3-90. PCLKCR23 Register Field Descriptions ............................................................................... 299
3-91. SIMRESET Register Field Descriptions ............................................................................... 300
3-92. LPMCR Register Field Descriptions .................................................................................... 301
3-93. GPIOLPMSEL0 Register Field Descriptions .......................................................................... 302
3-94. GPIOLPMSEL1 Register Field Descriptions .......................................................................... 305
3-95. TMR2CLKCTL Register Field Descriptions ........................................................................... 308

88 List of Tables SPRUII0B – May 2019 – Revised May 2020

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3-96. RESCCLR Register Field Descriptions ................................................................................ 309

3-97. RESC Register Field Descriptions ...................................................................................... 311
3-98. CPU_ID_REGS Registers ............................................................................................... 313
3-99. CPU_ID_REGS Access Type Codes .................................................................................. 313
3-100. CPUID Register Field Descriptions ..................................................................................... 314
3-101. CPU1_PERIPH_AC_REGS Registers ................................................................................. 315
3-102. CPU1_PERIPH_AC_REGS Access Type Codes .................................................................... 316
3-103. ADCA_AC Register Field Descriptions ................................................................................ 318
3-104. ADCB_AC Register Field Descriptions ................................................................................ 319
3-105. ADCC_AC Register Field Descriptions ................................................................................ 320
3-106. ADCD_AC Register Field Descriptions ................................................................................ 321
3-107. CMPSS1_AC Register Field Descriptions ............................................................................. 322
3-108. CMPSS2_AC Register Field Descriptions ............................................................................. 323
3-109. CMPSS3_AC Register Field Descriptions ............................................................................. 324
3-110. CMPSS4_AC Register Field Descriptions ............................................................................. 325
3-111. CMPSS5_AC Register Field Descriptions ............................................................................. 326
3-112. CMPSS6_AC Register Field Descriptions ............................................................................. 327
3-113. CMPSS7_AC Register Field Descriptions ............................................................................. 328
3-114. CMPSS8_AC Register Field Descriptions ............................................................................. 329
3-115. DACA_AC Register Field Descriptions ................................................................................ 330
3-116. DACB_AC Register Field Descriptions ................................................................................ 331
3-117. DACC_AC Register Field Descriptions ................................................................................ 332
3-118. EPWM1_AC Register Field Descriptions .............................................................................. 333
3-119. EPWM2_AC Register Field Descriptions .............................................................................. 334
3-120. EPWM3_AC Register Field Descriptions .............................................................................. 335
3-121. EPWM4_AC Register Field Descriptions .............................................................................. 336
3-122. EPWM5_AC Register Field Descriptions .............................................................................. 337
3-123. EPWM6_AC Register Field Descriptions .............................................................................. 338
3-124. EPWM7_AC Register Field Descriptions .............................................................................. 339
3-125. EPWM8_AC Register Field Descriptions .............................................................................. 340
3-126. EPWM9_AC Register Field Descriptions .............................................................................. 341
3-127. EPWM10_AC Register Field Descriptions ............................................................................ 342
3-128. EPWM11_AC Register Field Descriptions ............................................................................ 343
3-129. EPWM12_AC Register Field Descriptions ............................................................................ 344
3-130. EPWM13_AC Register Field Descriptions ............................................................................ 345
3-131. EPWM14_AC Register Field Descriptions ............................................................................ 346
3-132. EPWM15_AC Register Field Descriptions ............................................................................ 347
3-133. EPWM16_AC Register Field Descriptions ............................................................................ 348
3-134. EQEP1_AC Register Field Descriptions ............................................................................... 349
3-135. EQEP2_AC Register Field Descriptions ............................................................................... 350
3-136. EQEP3_AC Register Field Descriptions ............................................................................... 351
3-137. ECAP1_AC Register Field Descriptions ............................................................................... 352
3-138. ECAP2_AC Register Field Descriptions ............................................................................... 353
3-139. ECAP3_AC Register Field Descriptions ............................................................................... 354
3-140. ECAP4_AC Register Field Descriptions ............................................................................... 355
3-141. ECAP5_AC Register Field Descriptions ............................................................................... 356
3-142. ECAP6_AC Register Field Descriptions ............................................................................... 357
3-143. ECAP7_AC Register Field Descriptions ............................................................................... 358
3-144. SDFM1_AC Register Field Descriptions ............................................................................... 359

SPRUII0B – May 2019 – Revised May 2020 List of Tables 89

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3-145. SDFM2_AC Register Field Descriptions ............................................................................... 360

3-146. CLB1_AC Register Field Descriptions ................................................................................. 361
3-147. CLB2_AC Register Field Descriptions ................................................................................. 362
3-148. CLB3_AC Register Field Descriptions ................................................................................. 363
3-149. CLB4_AC Register Field Descriptions ................................................................................. 364
3-150. SPIA_AC Register Field Descriptions .................................................................................. 365
3-151. SPIB_AC Register Field Descriptions .................................................................................. 366
3-152. SPIC_AC Register Field Descriptions.................................................................................. 367
3-153. SPID_AC Register Field Descriptions.................................................................................. 368
3-154. PMBUS_A_AC Register Field Descriptions ........................................................................... 369
3-155. CAN_A_AC Register Field Descriptions ............................................................................... 370
3-156. CAN_B_AC Register Field Descriptions ............................................................................... 371
3-157. MCBSPA_AC Register Field Descriptions ............................................................................ 372
3-158. MCBSPB_AC Register Field Descriptions ............................................................................ 373
3-159. USBA_AC Register Field Descriptions................................................................................. 374
3-160. HRPWM_AC Register Field Descriptions ............................................................................. 375
3-161. ETHERCAT_AC Register Field Descriptions ......................................................................... 377
3-162. FSIATX_AC Register Field Descriptions .............................................................................. 378
3-163. FSIARX_AC Register Field Descriptions .............................................................................. 379
3-164. FSIBTX_AC Register Field Descriptions .............................................................................. 380
3-165. FSIBRX_AC Register Field Descriptions .............................................................................. 381
3-166. FSICRX_AC Register Field Descriptions .............................................................................. 382
3-167. FSIDRX_AC Register Field Descriptions .............................................................................. 383
3-168. FSIERX_AC Register Field Descriptions .............................................................................. 384
3-169. FSIFRX_AC Register Field Descriptions .............................................................................. 385
3-170. FSIGRX_AC Register Field Descriptions .............................................................................. 386
3-171. FSIHRX_AC Register Field Descriptions .............................................................................. 387
3-172. PERIPH_AC_LOCK Register Field Descriptions ..................................................................... 388
3-173. CPUTIMER_REGS Registers ........................................................................................... 389
3-174. CPUTIMER_REGS Access Type Codes .............................................................................. 389
3-175. TIM Register Field Descriptions ........................................................................................ 390
3-176. PRD Register Field Descriptions ....................................................................................... 391
3-177. TCR Register Field Descriptions........................................................................................ 392
3-178. TPR Register Field Descriptions ........................................................................................ 394
3-179. TPRH Register Field Descriptions ...................................................................................... 395
3-180. DEV_CFG_REGS Registers ............................................................................................ 396
3-181. DEV_CFG_REGS Access Type Codes ............................................................................... 397
3-182. DEVCFGLOCK1 Register Field Descriptions ......................................................................... 398
3-183. DEVCFGLOCK2 Register Field Descriptions ......................................................................... 400
3-184. PARTIDL Register Field Descriptions .................................................................................. 401
3-185. PARTIDH Register Field Descriptions ................................................................................. 402
3-186. REVID Register Field Descriptions ..................................................................................... 403
3-187. PERCNF1 Register Field Descriptions................................................................................. 404
3-188. FUSEERR Register Field Descriptions ................................................................................ 405
3-189. SOFTPRES0 Register Field Descriptions ............................................................................. 406
3-190. SOFTPRES1 Register Field Descriptions ............................................................................. 407
3-191. SOFTPRES2 Register Field Descriptions ............................................................................. 408
3-192. SOFTPRES3 Register Field Descriptions ............................................................................. 410
3-193. SOFTPRES4 Register Field Descriptions ............................................................................. 411

90 List of Tables SPRUII0B – May 2019 – Revised May 2020

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3-194. SOFTPRES6 Register Field Descriptions ............................................................................. 412

3-195. SOFTPRES7 Register Field Descriptions ............................................................................. 413
3-196. SOFTPRES8 Register Field Descriptions ............................................................................. 414
3-197. SOFTPRES9 Register Field Descriptions ............................................................................. 415
3-198. SOFTPRES10 Register Field Descriptions............................................................................ 416
3-199. SOFTPRES11 Register Field Descriptions............................................................................ 417
3-200. SOFTPRES13 Register Field Descriptions............................................................................ 418
3-201. SOFTPRES14 Register Field Descriptions............................................................................ 419
3-202. SOFTPRES16 Register Field Descriptions............................................................................ 420
3-203. SOFTPRES17 Register Field Descriptions............................................................................ 421
3-204. SOFTPRES18 Register Field Descriptions............................................................................ 422
3-205. SOFTPRES20 Register Field Descriptions............................................................................ 424
3-206. SOFTPRES21 Register Field Descriptions............................................................................ 425
3-207. SOFTPRES23 Register Field Descriptions............................................................................ 426
3-208. CPUSEL0 Register Field Descriptions ................................................................................. 427
3-209. CPUSEL1 Register Field Descriptions ................................................................................. 429
3-210. CPUSEL2 Register Field Descriptions ................................................................................. 430
3-211. CPUSEL4 Register Field Descriptions ................................................................................. 431
3-212. CPUSEL5 Register Field Descriptions ................................................................................. 432
3-213. CPUSEL6 Register Field Descriptions ................................................................................. 433
3-214. CPUSEL7 Register Field Descriptions ................................................................................. 434
3-215. CPUSEL8 Register Field Descriptions ................................................................................. 435
3-216. CPUSEL9 Register Field Descriptions ................................................................................. 436
3-217. CPUSEL11 Register Field Descriptions ............................................................................... 437
3-218. CPUSEL12 Register Field Descriptions ............................................................................... 438
3-219. CPUSEL14 Register Field Descriptions ............................................................................... 439
3-220. CPUSEL15 Register Field Descriptions ............................................................................... 440
3-221. CPUSEL16 Register Field Descriptions ............................................................................... 441
3-222. CPUSEL18 Register Field Descriptions ............................................................................... 443
3-223. CPUSEL25 Register Field Descriptions ............................................................................... 444
3-224. CPU2RESCTL Register Field Descriptions ........................................................................... 445
3-225. RSTSTAT Register Field Descriptions ................................................................................. 446
3-226. LPMSTAT Register Field Descriptions ................................................................................. 447
3-227. USBTYPE Register Field Descriptions................................................................................. 448
3-228. ECAPTYPE Register Field Descriptions ............................................................................... 449
3-229. SDFMTYPE Register Field Descriptions .............................................................................. 450
3-230. MEMMAPTYPE Register Field Descriptions .......................................................................... 451
3-231. DMA_CLA_SRC_SEL_REGS Registers .............................................................................. 452
3-232. DMA_CLA_SRC_SEL_REGS Access Type Codes .................................................................. 452
3-233. CLA1TASKSRCSELLOCK Register Field Descriptions ............................................................. 453
3-234. DMACHSRCSELLOCK Register Field Descriptions ................................................................. 454
3-235. CLA1TASKSRCSEL1 Register Field Descriptions ................................................................... 455
3-236. CLA1TASKSRCSEL2 Register Field Descriptions ................................................................... 456
3-237. DMACHSRCSEL1 Register Field Descriptions ....................................................................... 457
3-238. DMACHSRCSEL2 Register Field Descriptions ....................................................................... 458
3-239. MEM_CFG_REGS Registers ........................................................................................... 459
3-240. MEM_CFG_REGS Access Type Codes ............................................................................... 460
3-241. DxLOCK Register Field Descriptions .................................................................................. 461
3-242. DxCOMMIT Register Field Descriptions ............................................................................... 462

SPRUII0B – May 2019 – Revised May 2020 List of Tables 91

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3-243. DxACCPROT0 Register Field Descriptions ........................................................................... 463

3-244. DxTEST Register Field Descriptions ................................................................................... 465
3-245. DxINIT Register Field Descriptions ..................................................................................... 466
3-246. DxINITDONE Register Field Descriptions ............................................................................. 467
3-247. DxRAMTEST_LOCK Register Field Descriptions .................................................................... 468
3-248. LSxLOCK Register Field Descriptions ................................................................................. 469
3-249. LSxCOMMIT Register Field Descriptions.............................................................................. 471
3-250. LSxMSEL Register Field Descriptions ................................................................................. 473
3-251. LSxCLAPGM Register Field Descriptions ............................................................................. 475
3-252. LSxACCPROT0 Register Field Descriptions .......................................................................... 476
3-253. LSxACCPROT1 Register Field Descriptions .......................................................................... 478
3-254. LSxTEST Register Field Descriptions.................................................................................. 480
3-255. LSxINIT Register Field Descriptions ................................................................................... 482
3-256. LSxINITDONE Register Field Descriptions............................................................................ 483
3-257. LSxRAMTEST_LOCK Register Field Descriptions ................................................................... 484
3-258. GSxLOCK Register Field Descriptions................................................................................. 485
3-259. GSxCOMMIT Register Field Descriptions ............................................................................. 487
3-260. GSxMSEL Register Field Descriptions................................................................................. 490
3-261. GSxACCPROT0 Register Field Descriptions ......................................................................... 492
3-262. GSxACCPROT1 Register Field Descriptions ......................................................................... 494
3-263. GSxACCPROT2 Register Field Descriptions ......................................................................... 496
3-264. GSxACCPROT3 Register Field Descriptions ......................................................................... 498
3-265. GSxTEST Register Field Descriptions ................................................................................. 500
3-266. GSxINIT Register Field Descriptions ................................................................................... 504
3-267. GSxINITDONE Register Field Descriptions ........................................................................... 506
3-268. GSxRAMTEST_LOCK Register Field Descriptions .................................................................. 508
3-269. MSGxLOCK Register Field Descriptions .............................................................................. 510
3-270. MSGxCOMMIT Register Field Descriptions ........................................................................... 512
3-271. MSGxACCPROT0 Register Field Descriptions ....................................................................... 514
3-272. MSGxACCPROT1 Register Field Descriptions ....................................................................... 515
3-273. MSGxACCPROT2 Register Field Descriptions ....................................................................... 516
3-274. MSGxTEST Register Field Descriptions ............................................................................... 517
3-275. MSGxINIT Register Field Descriptions................................................................................. 519
3-276. MSGxINITDONE Register Field Descriptions ......................................................................... 520
3-277. MSGxRAMTEST_LOCK Register Field Descriptions ................................................................ 522
3-278. ROM_LOCK Register Field Descriptions .............................................................................. 524
3-279. ROM_TEST Register Field Descriptions .............................................................................. 525
3-280. ROM_FORCE_ERROR Register Field Descriptions ................................................................. 526
3-281. PERI_MEM_TEST_LOCK Register Field Descriptions .............................................................. 527
3-282. PERI_MEM_TEST_CONTROL Register Field Descriptions ........................................................ 528
3-283. MEMORY_ERROR_REGS Registers.................................................................................. 529
3-284. MEMORY_ERROR_REGS Access Type Codes ..................................................................... 529
3-285. UCERRFLG Register Field Descriptions .............................................................................. 531
3-286. UCERRSET Register Field Descriptions .............................................................................. 532
3-287. UCERRCLR Register Field Descriptions .............................................................................. 533
3-288. UCCPUREADDR Register Field Descriptions ........................................................................ 534
3-289. UCDMAREADDR Register Field Descriptions ........................................................................ 535
3-290. UCCLA1READDR Register Field Descriptions ....................................................................... 536
3-291. UCECATRAMADDR Register Field Descriptions .................................................................... 537

92 List of Tables SPRUII0B – May 2019 – Revised May 2020

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3-292. CERRFLG Register Field Descriptions ................................................................................ 538

3-293. CERRSET Register Field Descriptions ................................................................................ 539
3-294. CERRCLR Register Field Descriptions ................................................................................ 540
3-295. CCPUREADDR Register Field Descriptions .......................................................................... 541
3-296. CCLA1READDR Register Field Descriptions ......................................................................... 542
3-297. CERRCNT Register Field Descriptions ................................................................................ 543
3-298. CERRTHRES Register Field Descriptions ............................................................................ 544
3-299. CEINTFLG Register Field Descriptions ................................................................................ 545
3-300. CEINTCLR Register Field Descriptions ................................................................................ 546
3-301. CEINTSET Register Field Descriptions ................................................................................ 547
3-302. CEINTEN Register Field Descriptions ................................................................................. 548
3-303. NMI_INTRUPT_REGS Registers ....................................................................................... 549
3-304. NMI_INTRUPT_REGS Access Type Codes .......................................................................... 549
3-305. NMICFG Register Field Descriptions .................................................................................. 550
3-306. NMIFLG Register Field Descriptions ................................................................................... 551
3-307. NMIFLGCLR Register Field Descriptions.............................................................................. 553
3-308. NMIFLGFRC Register Field Descriptions ............................................................................. 556
3-309. NMIWDCNT Register Field Descriptions .............................................................................. 558
3-310. NMIWDPRD Register Field Descriptions .............................................................................. 559
3-311. NMISHDFLG Register Field Descriptions ............................................................................. 560
3-312. ERRORSTS Register Field Descriptions .............................................................................. 563
3-313. ERRORSTSCLR Register Field Descriptions ......................................................................... 564
3-314. ERRORSTSFRC Register Field Descriptions......................................................................... 565
3-315. ERRORCTL Register Field Descriptions .............................................................................. 566
3-316. ERRORLOCK Register Field Descriptions ............................................................................ 567
3-317. PIE_CTRL_REGS Registers ............................................................................................ 568
3-318. PIE_CTRL_REGS Access Type Codes ............................................................................... 568
3-319. PIECTRL Register Field Descriptions .................................................................................. 570
3-320. PIEACK Register Field Descriptions ................................................................................... 571
3-321. PIEIER1 Register Field Descriptions ................................................................................... 572
3-322. PIEIFR1 Register Field Descriptions ................................................................................... 573
3-323. PIEIER2 Register Field Descriptions ................................................................................... 575
3-324. PIEIFR2 Register Field Descriptions ................................................................................... 576
3-325. PIEIER3 Register Field Descriptions ................................................................................... 578
3-326. PIEIFR3 Register Field Descriptions ................................................................................... 579
3-327. PIEIER4 Register Field Descriptions ................................................................................... 581
3-328. PIEIFR4 Register Field Descriptions ................................................................................... 582
3-329. PIEIER5 Register Field Descriptions ................................................................................... 584
3-330. PIEIFR5 Register Field Descriptions ................................................................................... 585
3-331. PIEIER6 Register Field Descriptions ................................................................................... 587
3-332. PIEIFR6 Register Field Descriptions ................................................................................... 588
3-333. PIEIER7 Register Field Descriptions ................................................................................... 590
3-334. PIEIFR7 Register Field Descriptions ................................................................................... 591
3-335. PIEIER8 Register Field Descriptions ................................................................................... 593
3-336. PIEIFR8 Register Field Descriptions ................................................................................... 594
3-337. PIEIER9 Register Field Descriptions ................................................................................... 596
3-338. PIEIFR9 Register Field Descriptions ................................................................................... 597
3-339. PIEIER10 Register Field Descriptions ................................................................................. 599
3-340. PIEIFR10 Register Field Descriptions ................................................................................. 600

SPRUII0B – May 2019 – Revised May 2020 List of Tables 93

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3-341. PIEIER11 Register Field Descriptions ................................................................................. 602

3-342. PIEIFR11 Register Field Descriptions ................................................................................. 603
3-343. PIEIER12 Register Field Descriptions ................................................................................. 605
3-344. PIEIFR12 Register Field Descriptions ................................................................................. 606
3-345. ROM_PREFETCH_REGS Registers................................................................................... 608
3-346. ROM_PREFETCH_REGS Access Type Codes ...................................................................... 608
3-347. ROMPREFETCH Register Field Descriptions ........................................................................ 609
3-348. ROM_WAIT_STATE_REGS Registers ................................................................................ 610
3-349. ROM_WAIT_STATE_REGS Access Type Codes ................................................................... 610
3-350. ROMWAITSTATE Register Field Descriptions ....................................................................... 611
3-351. SYNC_SOC_REGS Registers .......................................................................................... 612
3-352. SYNC_SOC_REGS Access Type Codes ............................................................................. 612
3-353. SYNCSELECT Register Field Descriptions ........................................................................... 613
3-354. ADCSOCOUTSELECT Register Field Descriptions ................................................................. 614
3-355. SYNCSOCLOCK Register Field Descriptions ........................................................................ 617
3-356. SYS_STATUS_REGS Registers ....................................................................................... 618
3-357. SYS_STATUS_REGS Access Type Codes ........................................................................... 618
3-358. CM_STATUS_INT_FLG Register Field Descriptions ................................................................ 619
3-359. CM_STATUS_INT_CLR Register Field Descriptions ................................................................ 620
3-360. CM_STATUS_INT_SET Register Field Descriptions ................................................................ 621
3-361. CM_STATUS_MASK Register Field Descriptions .................................................................... 622
3-362. SYS_ERR_INT_FLG Register Field Descriptions .................................................................... 623
3-363. SYS_ERR_INT_CLR Register Field Descriptions .................................................................... 625
3-364. SYS_ERR_INT_SET Register Field Descriptions .................................................................... 627
3-365. SYS_ERR_MASK Register Field Descriptions ....................................................................... 629
3-366. TEST_ERROR_REGS Registers ....................................................................................... 631
3-367. TEST_ERROR_REGS Access Type Codes .......................................................................... 631
3-368. CPU_RAM_TEST_ERROR_STS Register Field Descriptions...................................................... 632
3-369. CPU_RAM_TEST_ERROR_STS_CLR Register Field Descriptions ............................................... 633
3-370. CPU_RAM_TEST_ERROR_ADDR Register Field Descriptions ................................................... 634
3-371. UID_REGS Registers .................................................................................................... 635
3-372. UID_REGS Access Type Codes........................................................................................ 635
3-373. UID_PSRAND0 Register Field Descriptions .......................................................................... 636
3-374. UID_PSRAND1 Register Field Descriptions .......................................................................... 637
3-375. UID_PSRAND2 Register Field Descriptions .......................................................................... 638
3-376. UID_PSRAND3 Register Field Descriptions .......................................................................... 639
3-377. UID_PSRAND4 Register Field Descriptions .......................................................................... 640
3-378. UID_PSRAND5 Register Field Descriptions .......................................................................... 641
3-379. UID_UNIQUE Register Field Descriptions ............................................................................ 642
3-380. UID_CHECKSUM Register Field Descriptions........................................................................ 643
3-381. WD_REGS Registers .................................................................................................... 644
3-382. WD_REGS Access Type Codes ........................................................................................ 644
3-383. SCSR Register Field Descriptions ...................................................................................... 645
3-384. WDCNTR Register Field Descriptions ................................................................................. 646
3-385. WDKEY Register Field Descriptions ................................................................................... 647
3-386. WDCR Register Field Descriptions ..................................................................................... 648
3-387. WDWCR Register Field Descriptions .................................................................................. 650
3-388. XINT_REGS Registers ................................................................................................... 651
3-389. XINT_REGS Access Type Codes ...................................................................................... 651

94 List of Tables SPRUII0B – May 2019 – Revised May 2020

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3-390. XINT1CR Register Field Descriptions.................................................................................. 652

3-391. XINT2CR Register Field Descriptions.................................................................................. 653
3-392. XINT3CR Register Field Descriptions.................................................................................. 654
3-393. XINT4CR Register Field Descriptions.................................................................................. 655
3-394. XINT5CR Register Field Descriptions.................................................................................. 656
3-395. XINT1CTR Register Field Descriptions ................................................................................ 657
3-396. XINT2CTR Register Field Descriptions ................................................................................ 658
3-397. XINT3CTR Register Field Descriptions ................................................................................ 659
3-398. CPUTIMER Registers to Driverlib Functions .......................................................................... 660
3-399. WWD Registers to Driverlib Functions ................................................................................. 660
3-400. ASYSCTL Registers to Driverlib Functions............................................................................ 660
3-401. PIE Registers to Driverlib Functions ................................................................................... 661
3-402. SYSCTL Registers to Driverlib Functions ............................................................................. 662
3-403. NMI Registers to Driverlib Functions ................................................................................... 668
3-404. XINT Registers to Driverlib Functions .................................................................................. 669
3-405. DCSM Registers to Driverlib Functions ................................................................................ 669
3-406. MEMCFG Registers to Driverlib Functions ............................................................................ 671
4-1. TMU Supported Instructions............................................................................................. 676
5-1. Boot System Overview ................................................................................................... 679
5-2. ROM Memory ............................................................................................................. 679
5-3. CPU1 Boot ROM Sequence ............................................................................................. 680
5-4. CPU2 Boot ROM Sequence ............................................................................................. 680
5-5. CM Boot ROM Sequence ................................................................................................ 680
5-6. Device Default Boot Modes for CPU1 ................................................................................. 681
5-7. CPU1 Flash-to-USB Boot Decision Table ............................................................................. 681
5-8. All Available Boot Modes ................................................................................................ 681
5-9. CPU1 BOOTPINCONFIG Bit Fields .................................................................................... 682
5-10. CPU1 Standalone Boot Mode Select Pin Decoding ................................................................. 683
5-11. CPU1 BOOTDEF Bit Fields ............................................................................................. 684
5-12. Zero Boot Pin Boot Table Result ....................................................................................... 685
5-13. One Boot Pin Boot Table Result ........................................................................................ 685
5-14. Three Boot Pins Boot Table Result .................................................................................... 686
5-15. Boot ROM Reset Causes and Actions ................................................................................. 692
5-16. Boot ROM Exceptions and Actions ..................................................................................... 693
5-17. CPU1 Boot ROM Registers ............................................................................................. 694
5-18. CPU1 DCSM Z1/Z2 GPREG2 Bit Fields .............................................................................. 694
5-19. CPU2 Boot Procedure ................................................................................................... 695
5-20. CM Boot Procedure ...................................................................................................... 695
5-21. CPU1TOCPU2IPCBOOTMODE Register Details .................................................................... 696
5-22. CPU1TOCMIPCBOOTMODE Register Details ....................................................................... 696
5-23. CPU2 to CPU1 Error IPC Commands ................................................................................. 697
5-24. CM to CPU1 Error IPC Commands .................................................................................... 697
5-25. Entry Point Addresses for CPU1 ....................................................................................... 698
5-26. Entry Point Addresses for CPU2 ....................................................................................... 698
5-27. Entry Point Addresses for CM .......................................................................................... 698
5-28. Wait Point Addresses for CPU1 ........................................................................................ 699
5-29. Wait Point Addresses for CPU2 ........................................................................................ 699
5-30. Wait Point Addresses for CM ........................................................................................... 699
5-31. CPU1 Boot ROM Memory Map ......................................................................................... 700

SPRUII0B – May 2019 – Revised May 2020 List of Tables 95

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5-32. CPU2 Boot ROM Memory Map ......................................................................................... 700

5-33. CM Boot ROM Memory Map ............................................................................................ 701
5-34. CPU1 CLA Data ROM Memory Map ................................................................................... 701
5-35. CPU2 CLA Data ROM Memory Map ................................................................................... 701
5-36. CPU1 Reserved RAM Memory Map ................................................................................... 702
5-37. CPU2 Reserved RAM Memory Map ................................................................................... 702
5-38. CM Reserved RAM Memory Map ...................................................................................... 702
5-39. ROM Symbol Tables ..................................................................................................... 702
5-40. Boot Mode Availability .................................................................................................... 703
5-41. Reasons for Entering Wait Boot ........................................................................................ 703
5-42. Secure Flash Tag and Key Details ..................................................................................... 704
5-43. Secure Flash Authentication Failure Actions .......................................................................... 705
5-44. Secure Flash on all CPUs Recommended Flow...................................................................... 705
5-45. IPC Message Copy Steps ............................................................................................... 706
5-46. IPC Message Copy Destination Address .............................................................................. 706
5-47. SPI 8-Bit Data Stream ................................................................................................... 708
5-48. I2C 8-Bit Data Stream ................................................................................................... 712
5-49. Parallel GPIO Boot 8-Bit Data Stream ................................................................................. 713
5-50. Bit-Rate Value for Internal Oscillators .................................................................................. 717
5-51. CAN 8-Bit Data Stream .................................................................................................. 718
5-52. USB 8-Bit Data Stream .................................................................................................. 720
5-53. SCI Boot Options ......................................................................................................... 721
5-54. CAN Boot Options ........................................................................................................ 721
5-55. I2C Boot Options .......................................................................................................... 721
5-56. USB Boot Options ........................................................................................................ 721
5-57. RAM Boot Options ........................................................................................................ 722
5-58. Flash Boot Options ....................................................................................................... 722
5-59. Secure Flash Boot Options .............................................................................................. 722
5-60. Wait Boot Options ........................................................................................................ 722
5-61. SPI Boot Options ......................................................................................................... 722
5-62. Parallel Boot Options ..................................................................................................... 723
5-63. Secure Copy Code Function ............................................................................................ 724
5-64. Secure CRC Calculation Function ...................................................................................... 724
5-65. Secure Flash CMAC Calculation Function ............................................................................ 725
5-66. CPU1 Boot Clock Sources .............................................................................................. 727
5-67. CPU1 Clock State After Boot............................................................................................ 727
5-68. CPU1 Boot Status Address.............................................................................................. 728
5-69. CPU1 Boot Status Bit Fields ............................................................................................ 728
5-70. CPU2 Boot ROM Status Address ...................................................................................... 729
5-71. CPU2 Boot Status Bit Fields ............................................................................................ 729
5-72. CM Boot ROM Status Address ......................................................................................... 730
5-73. CM Boot Status Bit Fields ............................................................................................... 730
5-74. Boot Mode and MPOST Status Addresses ........................................................................... 731
5-75. Boot ROM Version Information for CPU1 ............................................................................. 731
5-76. Boot ROM Version Information for CPU2 ............................................................................. 731
5-77. Boot ROM Version Information for CM ................................................................................ 731
5-78. LSB/MSB Loading Sequence in 8-Bit Data Stream .................................................................. 733
5-79. Boot Loader Options ..................................................................................................... 735
6-1. RAM/Flash Status ........................................................................................................ 738

96 List of Tables SPRUII0B – May 2019 – Revised May 2020

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6-2. Security Levels ............................................................................................................ 738

6-3. Default Value of ZxOTP (Programmed by TI)......................................................................... 739
6-4. DCSM Base Address Table (C28)...................................................................................... 752
6-5. CM DCSM Base Address Table (CM) ................................................................................. 752
6-6. DCSM_COMMON_REGS Registers ................................................................................... 753
6-7. DCSM_COMMON_REGS Access Type Codes ...................................................................... 753
6-8. FLSEM Register Field Descriptions .................................................................................... 754
6-9. SECTSTAT1 Register Field Descriptions.............................................................................. 755
6-10. SECTSTAT2 Register Field Descriptions.............................................................................. 757
6-11. SECTSTAT3 Register Field Descriptions.............................................................................. 759
6-12. RAMSTAT1 Register Field Descriptions ............................................................................... 761
6-13. RAMSTAT2 Register Field Descriptions ............................................................................... 763
6-14. RAMSTAT3 Register Field Descriptions ............................................................................... 766
6-15. SECERRSTAT Register Field Descriptions ........................................................................... 768
6-16. SECERRCLR Register Field Descriptions ............................................................................ 769
6-17. SECERRFRC Register Field Descriptions ............................................................................ 770
6-18. DCSM_Z1_OTP Registers .............................................................................................. 771
6-19. DCSM_Z1_OTP Access Type Codes .................................................................................. 771
6-20. Z1OTP_LINKPOINTER1 Register Field Descriptions ............................................................... 772
6-21. Z1OTP_LINKPOINTER2 Register Field Descriptions ............................................................... 773
6-22. Z1OTP_LINKPOINTER3 Register Field Descriptions ............................................................... 774
6-23. Z1OTP_JLM_ENABLE Register Field Descriptions .................................................................. 775
6-24. Z1OTP_GPREG1 Register Field Descriptions ........................................................................ 776
6-25. Z1OTP_GPREG2 Register Field Descriptions ........................................................................ 777
6-26. Z1OTP_GPREG3 Register Field Descriptions ........................................................................ 778
6-27. Z1OTP_GPREG4 Register Field Descriptions ........................................................................ 779
6-28. Z1OTP_PSWDLOCK Register Field Descriptions ................................................................... 780
6-29. Z1OTP_CRCLOCK Register Field Descriptions ...................................................................... 781
6-30. Z1OTP_JTAGPSWDH0 Register Field Descriptions ................................................................ 782
6-31. Z1OTP_JTAGPSWDH1 Register Field Descriptions ................................................................ 783
6-32. Z1OTP_CMACKEY0 Register Field Descriptions .................................................................... 784
6-33. Z1OTP_CMACKEY1 Register Field Descriptions .................................................................... 785
6-34. Z1OTP_CMACKEY2 Register Field Descriptions .................................................................... 786
6-35. Z1OTP_CMACKEY3 Register Field Descriptions .................................................................... 787
6-36. DCSM_Z1_REGS Registers ............................................................................................ 788
6-37. DCSM_Z1_REGS Access Type Codes ................................................................................ 788
6-38. Z1_LINKPOINTER Register Field Descriptions ...................................................................... 790
6-39. Z1_OTPSECLOCK Register Field Descriptions ...................................................................... 791
6-40. Z1_JLM_ENABLE Register Field Descriptions ....................................................................... 792
6-41. Z1_LINKPOINTERERR Register Field Descriptions ................................................................. 793
6-42. Z1_GPREG1 Register Field Descriptions ............................................................................. 794
6-43. Z1_GPREG2 Register Field Descriptions ............................................................................. 795
6-44. Z1_GPREG3 Register Field Descriptions ............................................................................. 796
6-45. Z1_GPREG4 Register Field Descriptions ............................................................................. 797
6-46. Z1_CSMKEY0 Register Field Descriptions............................................................................ 798
6-47. Z1_CSMKEY1 Register Field Descriptions............................................................................ 799
6-48. Z1_CSMKEY2 Register Field Descriptions............................................................................ 800
6-49. Z1_CSMKEY3 Register Field Descriptions............................................................................ 801
6-50. Z1_CR Register Field Descriptions..................................................................................... 802

SPRUII0B – May 2019 – Revised May 2020 List of Tables 97

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6-51. Z1_GRABSECT1R Register Field Descriptions ...................................................................... 803

6-52. Z1_GRABSECT2R Register Field Descriptions ...................................................................... 806
6-53. Z1_GRABSECT3R Register Field Descriptions ...................................................................... 809
6-54. Z1_GRABRAM1R Register Field Descriptions ....................................................................... 812
6-55. Z1_GRABRAM2R Register Field Descriptions ....................................................................... 814
6-56. Z1_GRABRAM3R Register Field Descriptions ....................................................................... 817
6-57. Z1_EXEONLYSECT1R Register Field Descriptions ................................................................. 819
6-58. Z1_EXEONLYSECT2R Register Field Descriptions ................................................................. 823
6-59. Z1_EXEONLYRAM1R Register Field Descriptions .................................................................. 826
6-60. Z1_JTAGKEY0 Register Field Descriptions ........................................................................... 830
6-61. Z1_JTAGKEY1 Register Field Descriptions ........................................................................... 831
6-62. Z1_JTAGKEY2 Register Field Descriptions ........................................................................... 832
6-63. Z1_JTAGKEY3 Register Field Descriptions ........................................................................... 833
6-64. Z1_CMACKEY0 Register Field Descriptions .......................................................................... 834
6-65. Z1_CMACKEY1 Register Field Descriptions .......................................................................... 835
6-66. Z1_CMACKEY2 Register Field Descriptions .......................................................................... 836
6-67. Z1_CMACKEY3 Register Field Descriptions .......................................................................... 837
6-68. DCSM_Z2_OTP Registers .............................................................................................. 838
6-69. DCSM_Z2_OTP Access Type Codes .................................................................................. 838
6-70. Z2OTP_LINKPOINTER1 Register Field Descriptions ............................................................... 839
6-71. Z2OTP_LINKPOINTER2 Register Field Descriptions ............................................................... 840
6-72. Z2OTP_LINKPOINTER3 Register Field Descriptions ............................................................... 841
6-73. Z2OTP_GPREG1 Register Field Descriptions ........................................................................ 842
6-74. Z2OTP_GPREG2 Register Field Descriptions ........................................................................ 843
6-75. Z2OTP_GPREG3 Register Field Descriptions ........................................................................ 844
6-76. Z2OTP_GPREG4 Register Field Descriptions ........................................................................ 845
6-77. Z2OTP_PSWDLOCK Register Field Descriptions ................................................................... 846
6-78. Z2OTP_CRCLOCK Register Field Descriptions ...................................................................... 847
6-79. DCSM_Z2_REGS Registers ............................................................................................ 848
6-80. DCSM_Z2_REGS Access Type Codes ................................................................................ 848
6-81. Z2_LINKPOINTER Register Field Descriptions ...................................................................... 850
6-82. Z2_OTPSECLOCK Register Field Descriptions ...................................................................... 851
6-83. Z2_LINKPOINTERERR Register Field Descriptions ................................................................. 852
6-84. Z2_GPREG1 Register Field Descriptions ............................................................................. 853
6-85. Z2_GPREG2 Register Field Descriptions ............................................................................. 854
6-86. Z2_GPREG3 Register Field Descriptions ............................................................................. 855
6-87. Z2_GPREG4 Register Field Descriptions ............................................................................. 856
6-88. Z2_CSMKEY0 Register Field Descriptions............................................................................ 857
6-89. Z2_CSMKEY1 Register Field Descriptions............................................................................ 858
6-90. Z2_CSMKEY2 Register Field Descriptions............................................................................ 859
6-91. Z2_CSMKEY3 Register Field Descriptions............................................................................ 860
6-92. Z2_CR Register Field Descriptions..................................................................................... 861
6-93. Z2_GRABSECT1R Register Field Descriptions ...................................................................... 862
6-94. Z2_GRABSECT2R Register Field Descriptions ...................................................................... 865
6-95. Z2_GRABSECT3R Register Field Descriptions ...................................................................... 868
6-96. Z2_GRABRAM1R Register Field Descriptions ....................................................................... 871
6-97. Z2_GRABRAM2R Register Field Descriptions ....................................................................... 873
6-98. Z2_GRABRAM3R Register Field Descriptions ....................................................................... 876
6-99. Z2_EXEONLYSECT1R Register Field Descriptions ................................................................. 878

98 List of Tables SPRUII0B – May 2019 – Revised May 2020

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6-100. Z2_EXEONLYSECT2R Register Field Descriptions ................................................................. 882

6-101. Z2_EXEONLYRAM1R Register Field Descriptions .................................................................. 885
7-1. BGCRC Register Groups ................................................................................................ 894
7-2. Data Address Location Example 1 ..................................................................................... 897
7-3. Data Address Location Example 2 ..................................................................................... 898
7-4. Data Address Location Example 3 ..................................................................................... 898
7-5. BGCRC Base Address Table (C28) .................................................................................... 898
7-6. BGCRC_REGS Registers ............................................................................................... 899
7-7. BGCRC_REGS Access Type Codes .................................................................................. 899
7-8. BGCRC_EN Register Field Descriptions .............................................................................. 901
7-9. BGCRC_CTRL1 Register Field Descriptions ......................................................................... 902
7-10. BGCRC_CTRL2 Register Field Descriptions ......................................................................... 903
7-11. BGCRC_START_ADDR Register Field Descriptions ................................................................ 904
7-12. BGCRC_SEED Register Field Descriptions........................................................................... 905
7-13. BGCRC_GOLDEN Register Field Descriptions ...................................................................... 906
7-14. BGCRC_RESULT Register Field Descriptions ....................................................................... 907
7-15. BGCRC_CURR_ADDR Register Field Descriptions ................................................................. 908
7-16. BGCRC_WD_CFG Register Field Descriptions ...................................................................... 909
7-17. BGCRC_WD_MIN Register Field Descriptions ....................................................................... 910
7-18. BGCRC_WD_MAX Register Field Descriptions ...................................................................... 911
7-19. BGCRC_WD_CNT Register Field Descriptions ...................................................................... 912
7-20. BGCRC_NMIFLG Register Field Descriptions ........................................................................ 913
7-21. BGCRC_NMICLR Register Field Descriptions........................................................................ 914
7-22. BGCRC_NMIFRC Register Field Descriptions ....................................................................... 915
7-23. BGCRC_INTEN Register Field Descriptions .......................................................................... 916
7-24. BGCRC_INTFLG Register Field Descriptions ........................................................................ 917
7-25. BGCRC_INTCLR Register Field Descriptions ........................................................................ 919
7-26. BGCRC_INTFRC Register Field Descriptions ........................................................................ 920
7-27. BGCRC_LOCK Register Field Descriptions........................................................................... 921
7-28. BGCRC_COMMIT Register Field Descriptions ....................................................................... 923
8-1. Configuration Options .................................................................................................... 930
8-2. Pipeline Behavior of the MDEBUGSTOP1 Instruction ............................................................... 938
8-3. Write Followed by Read - Read Occurs First ........................................................................ 941
8-4. Write Followed by Read - Write Occurs First ........................................................................ 941
8-5. ADC to CLA Early Interrupt Response ................................................................................ 944
8-6. Operand Nomenclature .................................................................................................. 946
8-7. INSTRUCTION dest, source1, source2 Short Description .......................................................... 947
8-8. Addressing Modes ........................................................................................................ 948
8-9. Shift Field Encoding ...................................................................................................... 949
8-10. Operand Encoding ........................................................................................................ 949
8-11. Condition Field Encoding ................................................................................................ 949
8-12. General Instructions ...................................................................................................... 950
8-13. Pipeline Activity For MBCNDD, Branch Not Taken .................................................................. 965
8-14. Pipeline Activity For MBCNDD, Branch Taken ....................................................................... 965
8-15. Pipeline Activity For MCCNDD, Call Not Taken ..................................................................... 971
8-16. Pipeline Activity For MCCNDD, Call Taken .......................................................................... 971
8-17. Pipeline Activity For MMOV16 MARx, MRa , #16I .................................................................. 1005
8-18. Pipeline Activity For MMOV16 MAR0/MAR1, mem16 .............................................................. 1008
8-19. Pipeline Activity For MMOVI16 MAR0/MAR1, #16I ................................................................. 1022

SPRUII0B – May 2019 – Revised May 2020 List of Tables 99

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8-20. Pipeline Activity For MRCNDD, Return Not Taken ................................................................ 1044
8-21. Pipeline Activity For MRCNDD, Return Taken ..................................................................... 1044
8-22. Pipeline Activity For MSTOP........................................................................................... 1049
8-23. CLA Base Address Table (C28 and CLA) ........................................................................... 1063
8-24. CLA_ONLY_REGS Registers ......................................................................................... 1064
8-25. CLA_ONLY_REGS Access Type Codes ............................................................................. 1064
8-26. _MVECTBGRNDACTIVE Register Field Descriptions ............................................................. 1065
8-27. _MPSACTL Register Field Descriptions ............................................................................. 1066
8-28. _MPSA1 Register Field Descriptions ................................................................................. 1067
8-29. _MPSA2 Register Field Descriptions ................................................................................. 1068
8-30. SOFTINTEN Register Field Descriptions ............................................................................ 1069
8-31. SOFTINTFRC Register Field Descriptions........................................................................... 1070
8-32. CLA_REGS Registers .................................................................................................. 1071
8-33. CLA_REGS Access Type Codes ..................................................................................... 1071
8-34. MVECT1 Register Field Descriptions ................................................................................. 1073
8-35. MVECT2 Register Field Descriptions ................................................................................. 1074
8-36. MVECT3 Register Field Descriptions ................................................................................. 1075
8-37. MVECT4 Register Field Descriptions ................................................................................. 1076
8-38. MVECT5 Register Field Descriptions ................................................................................. 1077
8-39. MVECT6 Register Field Descriptions ................................................................................. 1078
8-40. MVECT7 Register Field Descriptions ................................................................................. 1079
8-41. MVECT8 Register Field Descriptions ................................................................................. 1080
8-42. MCTL Register Field Descriptions .................................................................................... 1081
8-43. _MVECTBGRNDACTIVE Register Field Descriptions ............................................................. 1082
8-44. SOFTINTEN Register Field Descriptions ............................................................................ 1083
8-45. _MSTSBGRND Register Field Descriptions ......................................................................... 1084
8-46. _MCTLBGRND Register Field Descriptions ......................................................................... 1085
8-47. _MVECTBGRND Register Field Descriptions ....................................................................... 1086
8-48. MIFR Register Field Descriptions ..................................................................................... 1087
8-49. MIOVF Register Field Descriptions ................................................................................... 1091
8-50. MIFRC Register Field Descriptions ................................................................................... 1094
8-51. MICLR Register Field Descriptions ................................................................................... 1096
8-52. MICLROVF Register Field Descriptions .............................................................................. 1098
8-53. MIER Register Field Descriptions ..................................................................................... 1100
8-54. MIRUN Register Field Descriptions ................................................................................... 1103
8-55. _MPC Register Field Descriptions .................................................................................... 1105
8-56. _MAR0 Register Field Descriptions ................................................................................... 1106
8-57. _MAR1 Register Field Descriptions ................................................................................... 1107
8-58. _MSTF Register Field Descriptions ................................................................................... 1108
8-59. _MR0 Register Field Descriptions .................................................................................... 1110
8-60. _MR1 Register Field Descriptions .................................................................................... 1111
8-61. _MR2 Register Field Descriptions .................................................................................... 1112
8-62. _MR3 Register Field Descriptions .................................................................................... 1113
8-63. _MPSACTL Register Field Descriptions ............................................................................. 1114
8-64. _MPSA1 Register Field Descriptions ................................................................................. 1115
8-65. _MPSA2 Register Field Descriptions ................................................................................. 1116
8-66. CLA_SOFTINT_REGS Registers ..................................................................................... 1117
8-67. CLA_SOFTINT_REGS Access Type Codes ........................................................................ 1117
8-68. SOFTINTEN Register Field Descriptions ............................................................................ 1118

100 List of Tables SPRUII0B – May 2019 – Revised May 2020

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8-69. SOFTINTFRC Register Field Descriptions........................................................................... 1119

9-1. Global Signals and Mux Selection .................................................................................... 1124
9-2. Local Signals and Mux Selection...................................................................................... 1130
9-3. Peripheral Signal Multiplexer Table ................................................................................... 1135
9-4. Output Table ............................................................................................................. 1142
9-5. Input Table ............................................................................................................... 1143
9-6. Ports Tied Off to Prevent Combinatorial Loops ..................................................................... 1143
9-7. Counter Block Operating Modes ...................................................................................... 1145
9-8. HLC Event List ........................................................................................................... 1154
9-9. HLC ALT Event List ..................................................................................................... 1155
9-10. HLC Instruction Address Ranges ..................................................................................... 1156
9-11. Instruction Format ....................................................................................................... 1156
9-12. HLC Register Encoding ................................................................................................ 1157
9-13. Non-Memory Mapped Register Addresses .......................................................................... 1158
9-14. CLB Base Address Table (C28) ....................................................................................... 1160
9-15. CLB_LOGIC_CONFIG_REGS Registers ............................................................................ 1161
9-16. CLB_LOGIC_CONFIG_REGS Access Type Codes................................................................ 1162
9-17. CLB_COUNT_RESET Register Field Descriptions ................................................................. 1163
9-18. CLB_COUNT_MODE_1 Register Field Descriptions ............................................................... 1164
9-19. CLB_COUNT_MODE_0 Register Field Descriptions ............................................................... 1165
9-20. CLB_COUNT_EVENT Register Field Descriptions ................................................................. 1166
9-21. CLB_FSM_EXTRA_IN0 Register Field Descriptions ............................................................... 1167
9-22. CLB_FSM_EXTERNAL_IN0 Register Field Descriptions .......................................................... 1168
9-23. CLB_FSM_EXTERNAL_IN1 Register Field Descriptions .......................................................... 1169
9-24. CLB_FSM_EXTRA_IN1 Register Field Descriptions ............................................................... 1170
9-25. CLB_LUT4_IN0 Register Field Descriptions......................................................................... 1171
9-26. CLB_LUT4_IN1 Register Field Descriptions......................................................................... 1172
9-27. CLB_LUT4_IN2 Register Field Descriptions......................................................................... 1173
9-28. CLB_LUT4_IN3 Register Field Descriptions......................................................................... 1174
9-29. CLB_FSM_LUT_FN1_0 Register Field Descriptions ............................................................... 1175
9-30. CLB_FSM_LUT_FN2 Register Field Descriptions .................................................................. 1176
9-31. CLB_LUT4_FN1_0 Register Field Descriptions ..................................................................... 1177
9-32. CLB_LUT4_FN2 Register Field Descriptions ........................................................................ 1178
9-33. CLB_FSM_NEXT_STATE_0 Register Field Descriptions ......................................................... 1179
9-34. CLB_FSM_NEXT_STATE_1 Register Field Descriptions ......................................................... 1180
9-35. CLB_FSM_NEXT_STATE_2 Register Field Descriptions ......................................................... 1181
9-36. CLB_MISC_CONTROL Register Field Descriptions ............................................................... 1182
9-37. CLB_OUTPUT_LUT_0 Register Field Descriptions ................................................................ 1185
9-38. CLB_OUTPUT_LUT_1 Register Field Descriptions ................................................................ 1186
9-39. CLB_OUTPUT_LUT_2 Register Field Descriptions ................................................................ 1187
9-40. CLB_OUTPUT_LUT_3 Register Field Descriptions ................................................................ 1188
9-41. CLB_OUTPUT_LUT_4 Register Field Descriptions ................................................................ 1189
9-42. CLB_OUTPUT_LUT_5 Register Field Descriptions ................................................................ 1190
9-43. CLB_OUTPUT_LUT_6 Register Field Descriptions ................................................................ 1191
9-44. CLB_OUTPUT_LUT_7 Register Field Descriptions ................................................................ 1192
9-45. ..............................................................
CLB_HLC_EVENT_SEL Register Field Descriptions 1193
9-46. CLB_COUNT_MATCH_TAP_SEL Register Field Descriptions ................................................... 1194
9-47. CLB_OUTPUT_COND_CTRL_0 Register Field Descriptions ..................................................... 1195
9-48. CLB_OUTPUT_COND_CTRL_1 Register Field Descriptions ..................................................... 1197

SPRUII0B – May 2019 – Revised May 2020 List of Tables 101

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9-49. CLB_OUTPUT_COND_CTRL_2 Register Field Descriptions ..................................................... 1199

9-50. CLB_OUTPUT_COND_CTRL_3 Register Field Descriptions ..................................................... 1201
9-51. CLB_OUTPUT_COND_CTRL_4 Register Field Descriptions ..................................................... 1203
9-52. CLB_OUTPUT_COND_CTRL_5 Register Field Descriptions ..................................................... 1205
9-53. CLB_OUTPUT_COND_CTRL_6 Register Field Descriptions ..................................................... 1207
9-54. CLB_OUTPUT_COND_CTRL_7 Register Field Descriptions ..................................................... 1209
9-55. CLB_MISC_ACCESS_CTRL Register Field Descriptions ......................................................... 1211
9-56. CLB_SPI_DATA_CTRL_HI Register Field Descriptions ........................................................... 1212
9-57. CLB_LOGIC_CONTROL_REGS Registers.......................................................................... 1213
9-58. CLB_LOGIC_CONTROL_REGS Access Type Codes ............................................................. 1213
9-59. CLB_LOAD_EN Register Field Descriptions ........................................................................ 1215
9-60. CLB_LOAD_ADDR Register Field Descriptions .................................................................... 1216
9-61. CLB_LOAD_DATA Register Field Descriptions ..................................................................... 1217
9-62. CLB_INPUT_FILTER Register Field Descriptions .................................................................. 1218
9-63. CLB_IN_MUX_SEL_0 Register Field Descriptions ................................................................. 1220
9-64. CLB_LCL_MUX_SEL_1 Register Field Descriptions ............................................................... 1222
9-65. CLB_LCL_MUX_SEL_2 Register Field Descriptions ............................................................... 1223
9-66. CLB_BUF_PTR Register Field Descriptions......................................................................... 1224
9-67. CLB_GP_REG Register Field Descriptions .......................................................................... 1225
9-68. CLB_OUT_EN Register Field Descriptions .......................................................................... 1226
9-69. CLB_GLBL_MUX_SEL_1 Register Field Descriptions ............................................................. 1227
9-70. CLB_GLBL_MUX_SEL_2 Register Field Descriptions ............................................................. 1228
9-71. CLB_PRESCALE_CTRL Register Field Descriptions .............................................................. 1229
9-72. CLB_INTR_TAG_REG Register Field Descriptions ................................................................ 1230
9-73. CLB_LOCK Register Field Descriptions.............................................................................. 1231
9-74. CLB_HLC_INSTR_READ_PTR Register Field Descriptions ...................................................... 1232
9-75. CLB_HLC_INSTR_VALUE Register Field Descriptions............................................................ 1233
9-76. CLB_DBG_OUT_2 Register Field Descriptions ..................................................................... 1234
9-77. CLB_DBG_R0 Register Field Descriptions .......................................................................... 1235
9-78. CLB_DBG_R1 Register Field Descriptions .......................................................................... 1236
9-79. CLB_DBG_R2 Register Field Descriptions .......................................................................... 1237
9-80. CLB_DBG_R3 Register Field Descriptions .......................................................................... 1238
9-81. CLB_DBG_C0 Register Field Descriptions .......................................................................... 1239
9-82. CLB_DBG_C1 Register Field Descriptions .......................................................................... 1240
9-83. CLB_DBG_C2 Register Field Descriptions .......................................................................... 1241
9-84. CLB_DBG_OUT Register Field Descriptions ........................................................................ 1242
9-85. CLB_DATA_EXCHANGE_REGS Registers ......................................................................... 1244
9-86. CLB_DATA_EXCHANGE_REGS Access Type Codes ............................................................ 1244
9-87. CLB_PUSH_y Register Field Descriptions........................................................................... 1245
9-88. CLB_PULL_y Register Field Descriptions ........................................................................... 1246
9-89. CLB Registers to Driverlib Functions ................................................................................. 1247
10-1. DCC Base Address Table (C28) ...................................................................................... 1257
10-2. DCC_REGS Registers.................................................................................................. 1258
10-3. DCC_REGS Access Type Codes ..................................................................................... 1258
10-4. DCCGCTRL Register Field Descriptions ............................................................................. 1259
10-5. DCCCNTSEED0 Register Field Descriptions ....................................................................... 1260
10-6. DCCVALIDSEED0 Register Field Descriptions ..................................................................... 1261
10-7. DCCCNTSEED1 Register Field Descriptions ....................................................................... 1262
10-8. DCCSTATUS Register Field Descriptions ........................................................................... 1263

102 List of Tables SPRUII0B – May 2019 – Revised May 2020

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10-9. DCCCNT0 Register Field Descriptions ............................................................................... 1264

10-10. DCCVALID0 Register Field Descriptions ............................................................................ 1265
10-11. DCCCNT1 Register Field Descriptions ............................................................................... 1266
10-12. DCCCLKSRC1 Register Field Descriptions ......................................................................... 1267
10-13. DCCCLKSRC0 Register Field Descriptions ......................................................................... 1268
10-14. DCC Registers to Driverlib Functions ................................................................................ 1269
11-1. DMA Trigger Source Options .......................................................................................... 1275
11-2. BURSTSIZE vs DATASIZE Behavior ................................................................................. 1280
11-3. DMA Base Address Table (C28) ...................................................................................... 1287
11-4. DMA_REGS Registers ................................................................................................. 1288
11-5. DMA_REGS Access Type Codes ..................................................................................... 1288
11-6. DMACTRL Register Field Descriptions............................................................................... 1289
11-7. DEBUGCTRL Register Field Descriptions ........................................................................... 1290
11-8. PRIORITYCTRL1 Register Field Descriptions ...................................................................... 1291
11-9. PRIORITYSTAT Register Field Descriptions ........................................................................ 1292
11-10. DMA_CH_REGS Registers ............................................................................................ 1293
11-11. DMA_CH_REGS Access Type Codes ............................................................................... 1293
11-12. MODE Register Field Descriptions.................................................................................... 1295
11-13. CONTROL Register Field Descriptions .............................................................................. 1297
11-14. BURST_SIZE Register Field Descriptions ........................................................................... 1299
11-15. BURST_COUNT Register Field Descriptions ....................................................................... 1300
11-16. SRC_BURST_STEP Register Field Descriptions ................................................................... 1301
11-17. DST_BURST_STEP Register Field Descriptions ................................................................... 1302
11-18. TRANSFER_SIZE Register Field Descriptions...................................................................... 1303
11-19. TRANSFER_COUNT Register Field Descriptions .................................................................. 1304
11-20. SRC_TRANSFER_STEP Register Field Descriptions ............................................................. 1305
11-21. DST_TRANSFER_STEP Register Field Descriptions .............................................................. 1306
11-22. SRC_WRAP_SIZE Register Field Descriptions ..................................................................... 1307
11-23. SRC_WRAP_COUNT Register Field Descriptions ................................................................. 1308
11-24. SRC_WRAP_STEP Register Field Descriptions .................................................................... 1309
11-25. DST_WRAP_SIZE Register Field Descriptions ..................................................................... 1310
11-26. DST_WRAP_COUNT Register Field Descriptions.................................................................. 1311
11-27. DST_WRAP_STEP Register Field Descriptions .................................................................... 1312
11-28. SRC_BEG_ADDR_SHADOW Register Field Descriptions ........................................................ 1313
11-29. SRC_ADDR_SHADOW Register Field Descriptions ............................................................... 1314
11-30. SRC_BEG_ADDR_ACTIVE Register Field Descriptions .......................................................... 1315
11-31. SRC_ADDR_ACTIVE Register Field Descriptions.................................................................. 1316
11-32. DST_BEG_ADDR_SHADOW Register Field Descriptions ........................................................ 1317
11-33. DST_ADDR_SHADOW Register Field Descriptions ............................................................... 1318
11-34. DST_BEG_ADDR_ACTIVE Register Field Descriptions ........................................................... 1319
11-35. DST_ADDR_ACTIVE Register Field Descriptions .................................................................. 1320
11-36. DMA Registers to Driverlib Functions ................................................................................ 1321
12-1. Configuration for EMIF1 and EMIF2 Modules ....................................................................... 1324
12-2. EMIF Pins Used to Access Both SDRAM and Asynchronous Memories ........................................ 1327
12-3. EMIF Pins Specific to SDRAM ........................................................................................ 1327
12-4. EMIF Pins Specific to Asynchronous Memory ...................................................................... 1328
12-5. EMIF SDRAM Commands ............................................................................................. 1329
12-6. Truth Table for SDRAM Commands .................................................................................. 1329
12-7. 16-bit EMIF Address Pin Connections................................................................................ 1331

SPRUII0B – May 2019 – Revised May 2020 List of Tables 103

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12-8. Description of the SDRAM Configuration Register (SDRAM_CR) ................................................ 1332

12-9. Description of the SDRAM Refresh Control Register (SDRAM_RCR) ........................................... 1332
12-10. Description of the SDRAM Timing Register (SDRAM_TR) ........................................................ 1333
12-11. Description of the SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) ............................ 1333
12-12. SDRAM LOAD MODE REGISTER Command ...................................................................... 1334
12-13. Refresh Urgency Levels ................................................................................................ 1335
12-14. Mapping from Logical Address to EMIF Pins for 32-bit SDRAM .................................................. 1340
12-15. Mapping from Logical Address to EMIF Pins for 16-bit SDRAM .................................................. 1340
12-16. Normal Mode vs. Select Strobe Mode ................................................................................ 1341
12-17. Description of the Asynchronous m Configuration Register (ASYNC_CSn_CR) ............................... 1343
12-18. Description of the Asynchronous Wait Cycle Configuration Register (ASYNC_WCCR) ...................... 1344
12-19. Description of EMIF Interrupt Mask Set Register (INT_MSK_SET) .............................................. 1344
12-20. Description of EMIF Interrupt Mast Clear Register (INT_MSK_CLR) ............................................ 1345
12-21. Asynchronous Read Operation in Normal Mode .................................................................... 1345
12-22. Asynchronous Write Operation in Normal Mode .................................................................... 1347
12-23. Asynchronous Read Operation in Select Strobe Mode ............................................................ 1349
12-24. Asynchronous Write Operation in Select Strobe Mode ............................................................ 1351
12-25. Interrupt Monitor and Control Bit Fields .............................................................................. 1354
12-26. SR Field Value For EMIF to K4S641632H-TC(L)70 Interface..................................................... 1358
12-27. SDRAM_TR Field Calculations for EMIF to K4S641632H-TC(L)70 Interface................................... 1360
12-28. RR Calculation for EMIF to K4S641632H-TC(L)70 Interface ..................................................... 1361
12-29. RR Calculation for EMIF to K4S641632H-TC(L)70 Interface ..................................................... 1361
12-30. SDRAM_CR Field Values For EMIF to K4S641632H-TC(L)70 Interface ........................................ 1362
12-31. AC Characteristics for a Read Access ............................................................................... 1363
12-32. AC Characteristics for a Write Access ............................................................................... 1363
12-33. EMIF Base Address Table (C28)...................................................................................... 1366
12-34. EMIF_REGS Registers ................................................................................................. 1367
12-35. EMIF_REGS Access Type Codes .................................................................................... 1367
12-36. RCSR Register Field Descriptions .................................................................................... 1368
12-37. ASYNC_WCCR Register Field Descriptions ........................................................................ 1369
12-38. SDRAM_CR Register Field Descriptions ............................................................................ 1370
12-39. SDRAM_RCR Register Field Descriptions........................................................................... 1372
12-40. ASYNC_CS2_CR Register Field Descriptions ...................................................................... 1373
12-41. ASYNC_CS3_CR Register Field Descriptions ...................................................................... 1375
12-42. ASYNC_CS4_CR Register Field Descriptions ...................................................................... 1377
12-43. SDRAM_TR Register Field Descriptions ............................................................................. 1379
12-44. TOTAL_SDRAM_AR Register Field Descriptions .................................................................. 1380
12-45. TOTAL_SDRAM_ACTR Register Field Descriptions ............................................................... 1381
12-46. SDR_EXT_TMNG Register Field Descriptions ...................................................................... 1382
12-47. INT_RAW Register Field Descriptions ............................................................................... 1383
12-48. INT_MSK Register Field Descriptions ................................................................................ 1384
12-49. INT_MSK_SET Register Field Descriptions ......................................................................... 1385
12-50. INT_MSK_CLR Register Field Descriptions ......................................................................... 1386
12-51. EMIF1_CONFIG_REGS Registers ................................................................................... 1387
12-52. EMIF1_CONFIG_REGS Access Type Codes ....................................................................... 1387
12-53. EMIF1LOCK Register Field Descriptions ............................................................................ 1388
12-54. EMIF1COMMIT Register Field Descriptions ......................................................................... 1389
12-55. EMIF1MSEL Register Field Descriptions ............................................................................ 1390
12-56. EMIF1ACCPROT0 Register Field Descriptions ..................................................................... 1391

104 List of Tables SPRUII0B – May 2019 – Revised May 2020

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12-57. EMIF2_CONFIG_REGS Registers ................................................................................... 1392

12-58. EMIF2_CONFIG_REGS Access Type Codes ....................................................................... 1392
12-59. EMIF2LOCK Register Field Descriptions ............................................................................ 1393
12-60. EMIF2COMMIT Register Field Descriptions ......................................................................... 1394
12-61. EMIF2ACCPROT0 Register Field Descriptions ..................................................................... 1395
12-62. EMIF Registers to Driverlib Functions ................................................................................ 1396
13-1. FLASH Base Address Table (C28) ................................................................................... 1415
13-2. CM FLASH Base Address Table (CM) ............................................................................... 1415
13-3. FLASH_CTRL_REGS Registers ...................................................................................... 1416
13-4. FLASH_CTRL_REGS Access Type Codes ......................................................................... 1416
13-5. FRDCNTL Register Field Descriptions ............................................................................... 1417
13-6. FBAC Register Field Descriptions .................................................................................... 1418
13-7. FBFALLBACK Register Field Descriptions .......................................................................... 1419
13-8. FBPRDY Register Field Descriptions ................................................................................. 1420
13-9. FPAC1 Register Field Descriptions ................................................................................... 1421
13-10. FMSTAT Register Field Descriptions ................................................................................. 1422
13-11. FRD_INTF_CTRL Register Field Descriptions ...................................................................... 1424
13-12. FLASH_ECC_REGS Registers........................................................................................ 1425
13-13. FLASH_ECC_REGS Access Type Codes ........................................................................... 1425
13-14. ECC_ENABLE Register Field Descriptions .......................................................................... 1427
13-15. SINGLE_ERR_ADDR_LOW Register Field Descriptions .......................................................... 1428
13-16. SINGLE_ERR_ADDR_HIGH Register Field Descriptions ......................................................... 1429
13-17. UNC_ERR_ADDR_LOW Register Field Descriptions .............................................................. 1430
13-18. UNC_ERR_ADDR_HIGH Register Field Descriptions ............................................................. 1431
13-19. ERR_STATUS Register Field Descriptions .......................................................................... 1432
13-20. ERR_POS Register Field Descriptions ............................................................................... 1434
13-21. ERR_STATUS_CLR Register Field Descriptions ................................................................... 1435
13-22. ERR_CNT Register Field Descriptions ............................................................................... 1436
13-23. ERR_THRESHOLD Register Field Descriptions .................................................................... 1437
13-24. ERR_INTFLG Register Field Descriptions ........................................................................... 1438
13-25. ERR_INTCLR Register Field Descriptions ........................................................................... 1439
13-26. FDATAH_TEST Register Field Descriptions ........................................................................ 1440
13-27. FDATAL_TEST Register Field Descriptions ......................................................................... 1441
13-28. FADDR_TEST Register Field Descriptions .......................................................................... 1442
13-29. FECC_TEST Register Field Descriptions ............................................................................ 1443
13-30. FECC_CTRL Register Field Descriptions ............................................................................ 1444
13-31. FOUTH_TEST Register Field Descriptions .......................................................................... 1445
13-32. FOUTL_TEST Register Field Descriptions .......................................................................... 1446
13-33. FECC_STATUS Register Field Descriptions ........................................................................ 1447
13-34. CM_FLASH_CTRL_REGS Registers ................................................................................ 1448
13-35. CM_FLASH_CTRL_REGS Access Type Codes .................................................................... 1448
13-36. FRDCNTL Register Field Descriptions ............................................................................... 1449
13-37. FBAC Register Field Descriptions .................................................................................... 1450
13-38. FBFALLBACK Register Field Descriptions .......................................................................... 1451
13-39. FBPRDY Register Field Descriptions ................................................................................. 1452
13-40. FPAC1 Register Field Descriptions ................................................................................... 1453
13-41. FMSTAT Register Field Descriptions ................................................................................. 1454
13-42. FRD_INTF_CTRL_LOCK Register Field Descriptions ............................................................. 1456
13-43. FRD_INTF_CTRL Register Field Descriptions ...................................................................... 1457

SPRUII0B – May 2019 – Revised May 2020 List of Tables 105

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13-44. CM_FLASH_ECC_REGS Registers .................................................................................. 1458

13-45. CM_FLASH_ECC_REGS Access Type Codes ..................................................................... 1458
13-46. ECC_ENABLE Register Field Descriptions .......................................................................... 1460
13-47. SINGLE_ERR_ADDR_LOW Register Field Descriptions .......................................................... 1461
13-48. SINGLE_ERR_ADDR_HIGH Register Field Descriptions ......................................................... 1462
13-49. UNC_ERR_ADDR_LOW Register Field Descriptions .............................................................. 1463
13-50. UNC_ERR_ADDR_HIGH Register Field Descriptions ............................................................. 1464
13-51. ERR_STATUS Register Field Descriptions .......................................................................... 1465
13-52. ERR_POS Register Field Descriptions ............................................................................... 1467
13-53. ERR_STATUS_CLR Register Field Descriptions ................................................................... 1468
13-54. ERR_CNT Register Field Descriptions ............................................................................... 1469
13-55. ERR_THRESHOLD Register Field Descriptions .................................................................... 1470
13-56. ERR_INTFLG Register Field Descriptions ........................................................................... 1471
13-57. ERR_INTCLR Register Field Descriptions ........................................................................... 1472
13-58. FDATAH_TEST Register Field Descriptions ........................................................................ 1473
13-59. FDATAL_TEST Register Field Descriptions ......................................................................... 1474
13-60. FADDR_TEST Register Field Descriptions .......................................................................... 1475
13-61. FECC_TEST Register Field Descriptions ............................................................................ 1476
13-62. FECC_CTRL Register Field Descriptions ............................................................................ 1477
13-63. FOUTH_TEST Register Field Descriptions .......................................................................... 1478
13-64. FOUTL_TEST Register Field Descriptions .......................................................................... 1479
13-65. FECC_STATUS Register Field Descriptions ........................................................................ 1480
13-66. FLASH_ECC_REGS_LOCK Register Field Descriptions .......................................................... 1481
13-67. FLASH_PUMP_SEMAPHORE_REGS Registers ................................................................... 1482
13-68. FLASH_PUMP_SEMAPHORE_REGS Access Type Codes ...................................................... 1482
13-69. PUMPREQUEST Register Field Descriptions ....................................................................... 1483
13-70. FLASH Registers to Driverlib Functions .............................................................................. 1484
14-1. Event Selector Mux Signals ............................................................................................ 1491
14-2. CPU Interfaces Monitored by CRC Units ............................................................................ 1497
14-3. ERAD Base Address Table (C28) .................................................................................... 1499
14-4. ERAD_GLOBAL_REGS Registers .................................................................................... 1500
14-5. ERAD_GLOBAL_REGS Access Type Codes ....................................................................... 1500
14-6. GLBL_EVENT_STAT Register Field Descriptions .................................................................. 1501
14-7. GLBL_HALT_STAT Register Field Descriptions .................................................................... 1503
14-8. GLBL_ENABLE Register Field Descriptions......................................................................... 1505
14-9. GLBL_CTM_RESET Register Field Descriptions ................................................................... 1507
14-10. GLBL_NMI_CTL Register Field Descriptions ........................................................................ 1508
14-11. GLBL_OWNER Register Field Descriptions ......................................................................... 1510
14-12. GLBL_EVENT_AND_MASK Register Field Descriptions .......................................................... 1511
14-13. GLBL_EVENT_OR_MASK Register Field Descriptions............................................................ 1515
14-14. GLBL_AND_EVENT_INT_MASK Register Field Descriptions .................................................... 1519
14-15. GLBL_OR_EVENT_INT_MASK Register Field Descriptions ...................................................... 1520
14-16. ERAD_HWBP_REGS Registers ...................................................................................... 1521
14-17. ERAD_HWBP_REGS Access Type Codes .......................................................................... 1521
14-18. HWBP_MASK Register Field Descriptions .......................................................................... 1522
14-19. HWBP_REF Register Field Descriptions ............................................................................. 1523
14-20. HWBP_CLEAR Register Field Descriptions ......................................................................... 1524
14-21. HWBP_CNTL Register Field Descriptions ........................................................................... 1525
14-22. HWBP_STATUS Register Field Descriptions ....................................................................... 1527

106 List of Tables SPRUII0B – May 2019 – Revised May 2020

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14-23. ERAD_COUNTER_REGS Registers ................................................................................. 1528

14-24. ERAD_COUNTER_REGS Access Type Codes .................................................................... 1528
14-25. CTM_CNTL Register Field Descriptions ............................................................................. 1529
14-26. CTM_STATUS Register Field Descriptions .......................................................................... 1531
14-27. CTM_REF Register Field Descriptions ............................................................................... 1532
14-28. CTM_COUNT Register Field Descriptions ........................................................................... 1533
14-29. CTM_MAX_COUNT Register Field Descriptions ................................................................... 1534
14-30. CTM_INPUT_SEL Register Field Descriptions...................................................................... 1535
14-31. CTM_CLEAR Register Field Descriptions ........................................................................... 1536
14-32. CTM_INPUT_SEL_2 Register Field Descriptions................................................................... 1537
14-33. CTM_INPUT_COND Register Field Descriptions ................................................................... 1538
14-34. ERAD_CRC_GLOBAL_REGS Registers ............................................................................ 1539
14-35. ERAD_CRC_GLOBAL_REGS Access Type Codes................................................................ 1539
14-36. CRC_GLOBAL_CTRL Register Field Descriptions ................................................................. 1540
14-37. ERAD_CRC_REGS Registers......................................................................................... 1542
14-38. ERAD_CRC_REGS Access Type Codes ............................................................................ 1542
14-39. CRC_CURRENT Register Field Descriptions ....................................................................... 1543
14-40. CRC_SEED Register Field Descriptions ............................................................................. 1544
14-41. CRC_QUALIFIER Register Field Descriptions ...................................................................... 1545
15-1. Sampling Period ......................................................................................................... 1551
15-2. Sampling Frequency .................................................................................................... 1551
15-3. Case 1: Three-Sample Sampling Window Width ................................................................... 1552
15-4. Case 2: Six-Sample Sampling Window Width ....................................................................... 1552
15-5. USB I/O Signal Muxing ................................................................................................. 1554
15-6. GPIO Configuration for High-Speed SPI ............................................................................. 1554
15-7. GPIO and Peripheral Muxing .......................................................................................... 1555
15-8. Peripheral Muxing (Multiple Pins Assigned) ......................................................................... 1555
15-9. GPIO Muxed Pins ....................................................................................................... 1556
15-10. GPIO Base Address Table (C28) ..................................................................................... 1563
15-11. CM GPIO Base Address Table (CM) ................................................................................. 1563
15-12. GPIO_CTRL_REGS Registers ........................................................................................ 1564
15-13. GPIO_CTRL_REGS Access Type Codes ........................................................................... 1566
15-14. GPACTRL Register Field Descriptions ............................................................................... 1568
15-15. GPAQSEL1 Register Field Descriptions ............................................................................. 1569
15-16. GPAQSEL2 Register Field Descriptions ............................................................................. 1570
15-17. GPAMUX1 Register Field Descriptions .............................................................................. 1571
15-18. GPAMUX2 Register Field Descriptions .............................................................................. 1572
15-19. GPADIR Register Field Descriptions ................................................................................. 1573
15-20. GPAPUD Register Field Descriptions ................................................................................ 1575
15-21. GPAINV Register Field Descriptions ................................................................................. 1577
15-22. GPAODR Register Field Descriptions ................................................................................ 1579
15-23. GPAGMUX1 Register Field Descriptions ............................................................................ 1581
15-24. GPAGMUX2 Register Field Descriptions ............................................................................ 1582
15-25. GPACSEL1 Register Field Descriptions ............................................................................. 1583
15-26. GPACSEL2 Register Field Descriptions ............................................................................. 1584
15-27. GPACSEL3 Register Field Descriptions ............................................................................. 1585
15-28. GPACSEL4 Register Field Descriptions ............................................................................. 1586
15-29. GPALOCK Register Field Descriptions............................................................................... 1587
15-30. GPACR Register Field Descriptions .................................................................................. 1589

SPRUII0B – May 2019 – Revised May 2020 List of Tables 107

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15-31. GPBCTRL Register Field Descriptions ............................................................................... 1591

15-32. GPBQSEL1 Register Field Descriptions ............................................................................. 1592
15-33. GPBQSEL2 Register Field Descriptions ............................................................................. 1593
15-34. GPBMUX1 Register Field Descriptions .............................................................................. 1594
15-35. GPBMUX2 Register Field Descriptions .............................................................................. 1595
15-36. GPBDIR Register Field Descriptions ................................................................................. 1596
15-37. GPBPUD Register Field Descriptions ................................................................................ 1598
15-38. GPBINV Register Field Descriptions ................................................................................. 1600
15-39. GPBODR Register Field Descriptions ................................................................................ 1602
15-40. GPBAMSEL Register Field Descriptions ............................................................................. 1604
15-41. GPBGMUX1 Register Field Descriptions ............................................................................ 1605
15-42. GPBGMUX2 Register Field Descriptions ............................................................................ 1606
15-43. GPBCSEL1 Register Field Descriptions ............................................................................. 1607
15-44. GPBCSEL2 Register Field Descriptions ............................................................................. 1608
15-45. GPBCSEL3 Register Field Descriptions ............................................................................. 1609
15-46. GPBCSEL4 Register Field Descriptions ............................................................................. 1610
15-47. GPBLOCK Register Field Descriptions............................................................................... 1611
15-48. GPBCR Register Field Descriptions .................................................................................. 1613
15-49. GPCCTRL Register Field Descriptions ............................................................................... 1615
15-50. GPCQSEL1 Register Field Descriptions ............................................................................. 1616
15-51. GPCQSEL2 Register Field Descriptions ............................................................................. 1617
15-52. GPCMUX1 Register Field Descriptions .............................................................................. 1618
15-53. GPCMUX2 Register Field Descriptions .............................................................................. 1619
15-54. GPCDIR Register Field Descriptions ................................................................................. 1620
15-55. GPCPUD Register Field Descriptions ................................................................................ 1622
15-56. GPCINV Register Field Descriptions ................................................................................. 1624
15-57. GPCODR Register Field Descriptions ................................................................................ 1626
15-58. GPCGMUX1 Register Field Descriptions ............................................................................ 1628
15-59. GPCGMUX2 Register Field Descriptions ............................................................................ 1629
15-60. GPCCSEL1 Register Field Descriptions ............................................................................. 1630
15-61. GPCCSEL2 Register Field Descriptions ............................................................................. 1631
15-62. GPCCSEL3 Register Field Descriptions ............................................................................. 1632
15-63. GPCCSEL4 Register Field Descriptions ............................................................................. 1633
15-64. GPCLOCK Register Field Descriptions .............................................................................. 1634
15-65. GPCCR Register Field Descriptions .................................................................................. 1636
15-66. GPDCTRL Register Field Descriptions ............................................................................... 1638
15-67. GPDQSEL1 Register Field Descriptions ............................................................................. 1639
15-68. GPDQSEL2 Register Field Descriptions ............................................................................. 1641
15-69. GPDMUX1 Register Field Descriptions .............................................................................. 1643
15-70. GPDMUX2 Register Field Descriptions .............................................................................. 1645
15-71. GPDDIR Register Field Descriptions ................................................................................. 1647
15-72. GPDPUD Register Field Descriptions ................................................................................ 1649
15-73. GPDINV Register Field Descriptions ................................................................................. 1651
15-74. GPDODR Register Field Descriptions ................................................................................ 1653
15-75. GPDGMUX1 Register Field Descriptions ............................................................................ 1655
15-76. GPDGMUX2 Register Field Descriptions ............................................................................ 1657
15-77. GPDCSEL1 Register Field Descriptions ............................................................................. 1659
15-78. GPDCSEL2 Register Field Descriptions ............................................................................. 1660
15-79. GPDCSEL3 Register Field Descriptions ............................................................................. 1661

108 List of Tables SPRUII0B – May 2019 – Revised May 2020

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15-80. GPDCSEL4 Register Field Descriptions ............................................................................. 1662

15-81. GPDLOCK Register Field Descriptions .............................................................................. 1663
15-82. GPDCR Register Field Descriptions .................................................................................. 1665
15-83. GPECTRL Register Field Descriptions ............................................................................... 1667
15-84. GPEQSEL1 Register Field Descriptions ............................................................................. 1668
15-85. GPEQSEL2 Register Field Descriptions ............................................................................. 1670
15-86. GPEMUX1 Register Field Descriptions .............................................................................. 1672
15-87. GPEMUX2 Register Field Descriptions .............................................................................. 1674
15-88. GPEDIR Register Field Descriptions ................................................................................. 1676
15-89. GPEPUD Register Field Descriptions ................................................................................ 1678
15-90. GPEINV Register Field Descriptions ................................................................................. 1680
15-91. GPEODR Register Field Descriptions ................................................................................ 1682
15-92. GPEGMUX1 Register Field Descriptions ............................................................................ 1684
15-93. GPEGMUX2 Register Field Descriptions ............................................................................ 1686
15-94. GPECSEL1 Register Field Descriptions ............................................................................. 1688
15-95. GPECSEL2 Register Field Descriptions ............................................................................. 1689
15-96. GPECSEL3 Register Field Descriptions ............................................................................. 1690
15-97. GPECSEL4 Register Field Descriptions ............................................................................. 1691
15-98. GPELOCK Register Field Descriptions............................................................................... 1692
15-99. GPECR Register Field Descriptions .................................................................................. 1694
15-100. GPFCTRL Register Field Descriptions .............................................................................. 1696
15-101. GPFQSEL1 Register Field Descriptions ............................................................................ 1697
15-102. GPFMUX1 Register Field Descriptions ............................................................................. 1698
15-103. GPFDIR Register Field Descriptions ................................................................................ 1699
15-104. GPFPUD Register Field Descriptions ............................................................................... 1700
15-105. GPFINV Register Field Descriptions ................................................................................ 1701
15-106. GPFODR Register Field Descriptions ............................................................................... 1702
15-107. GPFGMUX1 Register Field Descriptions ........................................................................... 1703
15-108. GPFCSEL1 Register Field Descriptions ............................................................................ 1704
15-109. GPFCSEL2 Register Field Descriptions ............................................................................ 1705
15-110. GPFLOCK Register Field Descriptions ............................................................................. 1706
15-111. GPFCR Register Field Descriptions ................................................................................. 1707
15-112. GPIO_DATA_REGS Registers ....................................................................................... 1708
15-113. GPIO_DATA_REGS Access Type Codes .......................................................................... 1708
15-114. GPADAT Register Field Descriptions ............................................................................... 1710
15-115. GPASET Register Field Descriptions ............................................................................... 1712
15-116. GPACLEAR Register Field Descriptions............................................................................ 1714
15-117. GPATOGGLE Register Field Descriptions ......................................................................... 1716
15-118. GPBDAT Register Field Descriptions ............................................................................... 1718
15-119. GPBSET Register Field Descriptions ............................................................................... 1720
15-120. GPBCLEAR Register Field Descriptions............................................................................ 1722
15-121. GPBTOGGLE Register Field Descriptions ......................................................................... 1724
15-122. GPCDAT Register Field Descriptions ............................................................................... 1726
15-123. GPCSET Register Field Descriptions ............................................................................... 1728
15-124. GPCCLEAR Register Field Descriptions ........................................................................... 1730
15-125. GPCTOGGLE Register Field Descriptions ......................................................................... 1732
15-126. GPDDAT Register Field Descriptions ............................................................................... 1734
15-127. GPDSET Register Field Descriptions ............................................................................... 1736
15-128. GPDCLEAR Register Field Descriptions ........................................................................... 1738

SPRUII0B – May 2019 – Revised May 2020 List of Tables 109

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15-129. GPDTOGGLE Register Field Descriptions ......................................................................... 1740

15-130. GPEDAT Register Field Descriptions ............................................................................... 1742
15-131. GPESET Register Field Descriptions ............................................................................... 1744
15-132. GPECLEAR Register Field Descriptions............................................................................ 1746
15-133. GPETOGGLE Register Field Descriptions ......................................................................... 1748
15-134. GPFDAT Register Field Descriptions ............................................................................... 1750
15-135. GPFSET Register Field Descriptions ............................................................................... 1751
15-136. GPFCLEAR Register Field Descriptions ............................................................................ 1752
15-137. GPFTOGGLE Register Field Descriptions ......................................................................... 1753
15-138. GPIO_DATA_READ_REGS Registers .............................................................................. 1754
15-139. GPIO_DATA_READ_REGS Access Type Codes ................................................................. 1754
15-140. GPADAT_R Register Field Descriptions ............................................................................ 1755
15-141. GPBDAT_R Register Field Descriptions ............................................................................ 1756
15-142. GPCDAT_R Register Field Descriptions............................................................................ 1757
15-143. GPDDAT_R Register Field Descriptions............................................................................ 1758
15-144. GPEDAT_R Register Field Descriptions ............................................................................ 1759
15-145. GPFDAT_R Register Field Descriptions ............................................................................ 1760
15-146. GPIO Registers to Driverlib Functions .............................................................................. 1761
16-1. CPU1-CM IPC Message RAM Read / Write Access ............................................................... 1768
16-2. CPU2-CM IPC Message RAM Read / Write Access ............................................................... 1768
16-3. CPU1-CPU2 IPC Message RAM Read / Write Access ............................................................ 1768
16-4. IPC Command Registers ............................................................................................... 1771
16-5. IPC Base Address Table (C28) ....................................................................................... 1773
16-6. CM IPC Base Address Table (CM) ................................................................................... 1773
16-7. CPU1TOCPU2_IPC_REGS_CPU1VIEW Registers ................................................................ 1774
16-8. CPU1TOCPU2_IPC_REGS_CPU1VIEW Access Type Codes ................................................... 1774
16-9. CPU1TOCPU2IPCACK Register Field Descriptions ............................................................... 1776
16-10. CPU2TOCPU1IPCSTS Register Field Descriptions ................................................................ 1778
16-11. CPU1TOCPU2IPCSET Register Field Descriptions ................................................................ 1782
16-12. CPU1TOCPU2IPCCLR Register Field Descriptions................................................................ 1786
16-13. CPU1TOCPU2IPCFLG Register Field Descriptions ................................................................ 1790
16-14. IPCCOUNTERL Register Field Descriptions ........................................................................ 1794
16-15. IPCCOUNTERH Register Field Descriptions ........................................................................ 1795
16-16. CPU1TOCPU2IPCSENDCOM Register Field Descriptions ....................................................... 1796
16-17. CPU1TOCPU2IPCSENDADDR Register Field Descriptions ...................................................... 1797
16-18. CPU1TOCPU2IPCSENDDATA Register Field Descriptions ...................................................... 1798
16-19. CPU2TOCPU1IPCREPLY Register Field Descriptions ............................................................ 1799
16-20. CPU2TOCPU1IPCRECVCOM Register Field Descriptions ....................................................... 1800
16-21. CPU2TOCPU1IPCRECVADDR Register Field Descriptions ...................................................... 1801
16-22. CPU2TOCPU1IPCRECVDATA Register Field Descriptions ...................................................... 1802
16-23. CPU1TOCPU2IPCREPLY Register Field Descriptions ............................................................ 1803
16-24. CPU2TOCPU1IPCBOOTSTS Register Field Descriptions ........................................................ 1804
16-25. CPU1TOCPU2IPCBOOTMODE Register Field Descriptions ..................................................... 1805
16-26. PUMPREQUEST Register Field Descriptions ....................................................................... 1806
16-27. CPU1TOCPU2_IPC_REGS_CPU2VIEW Registers ................................................................ 1807
16-28. CPU1TOCPU2_IPC_REGS_CPU2VIEW Access Type Codes ................................................... 1807
16-29. CPU2TOCPU1IPCACK Register Field Descriptions ............................................................... 1809
16-30. CPU1TOCPU2IPCSTS Register Field Descriptions ................................................................ 1811
16-31. CPU2TOCPU1IPCSET Register Field Descriptions ................................................................ 1815

110 List of Tables SPRUII0B – May 2019 – Revised May 2020

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16-32. CPU2TOCPU1IPCCLR Register Field Descriptions................................................................ 1819

16-33. CPU2TOCPU1IPCFLG Register Field Descriptions ................................................................ 1823
16-34. IPCCOUNTERL Register Field Descriptions ........................................................................ 1827
16-35. IPCCOUNTERH Register Field Descriptions ........................................................................ 1828
16-36. CPU1TOCPU2IPCRECVCOM Register Field Descriptions ....................................................... 1829
16-37. CPU1TOCPU2IPCRECVADDR Register Field Descriptions ...................................................... 1830
16-38. CPU1TOCPU2IPCRECVDATA Register Field Descriptions ...................................................... 1831
16-39. CPU2TOCPU1IPCREPLY Register Field Descriptions ............................................................ 1832
16-40. CPU2TOCPU1IPCSENDCOM Register Field Descriptions ....................................................... 1833
16-41. CPU2TOCPU1IPCSENDADDR Register Field Descriptions ...................................................... 1834
16-42. CPU2TOCPU1IPCSENDDATA Register Field Descriptions ...................................................... 1835
16-43. CPU1TOCPU2IPCREPLY Register Field Descriptions ............................................................ 1836
16-44. CPU2TOCPU1IPCBOOTSTS Register Field Descriptions ........................................................ 1837
16-45. CPU1TOCPU2IPCBOOTMODE Register Field Descriptions ..................................................... 1838
16-46. PUMPREQUEST Register Field Descriptions ....................................................................... 1839
16-47. CPU1TOCM_IPC_REGS_CPU1VIEW Registers ................................................................... 1840
16-48. CPU1TOCM_IPC_REGS_CPU1VIEW Access Type Codes ...................................................... 1840
16-49. CPU1TOCMIPCACK Register Field Descriptions .................................................................. 1842
16-50. CMTOCPU1IPCSTS Register Field Descriptions ................................................................... 1844
16-51. CPU1TOCMIPCSET Register Field Descriptions ................................................................... 1848
16-52. CPU1TOCMIPCCLR Register Field Descriptions................................................................... 1852
16-53. CPU1TOCMIPCFLG Register Field Descriptions ................................................................... 1856
16-54. IPCCOUNTERL Register Field Descriptions ........................................................................ 1860
16-55. IPCCOUNTERH Register Field Descriptions ........................................................................ 1861
16-56. CPU1TOCMIPCSENDCOM Register Field Descriptions .......................................................... 1862
16-57. CPU1TOCMIPCSENDADDR Register Field Descriptions ......................................................... 1863
16-58. CPU1TOCMIPCSENDDATA Register Field Descriptions ......................................................... 1864
16-59. CMTOCPU1IPCREPLY Register Field Descriptions ............................................................... 1865
16-60. CMTOCPU1IPCRECVCOM Register Field Descriptions .......................................................... 1866
16-61. CMTOCPU1IPCRECVADDR Register Field Descriptions ......................................................... 1867
16-62. CMTOCPU1IPCRECVDATA Register Field Descriptions ......................................................... 1868
16-63. CPU1TOCMIPCREPLY Register Field Descriptions ............................................................... 1869
16-64. CMTOCPU1IPCBOOTSTS Register Field Descriptions ........................................................... 1870
16-65. CPU1TOCMIPCBOOTMODE Register Field Descriptions ........................................................ 1871
16-66. CPU1TOCM_IPC_REGS_CMVIEW Registers ...................................................................... 1872
16-67. CPU1TOCM_IPC_REGS_CMVIEW Access Type Codes ......................................................... 1872
16-68. CMTOCPU1IPCACK Register Field Descriptions .................................................................. 1874
16-69. CPU1TOCMIPCSTS Register Field Descriptions ................................................................... 1876
16-70. CMTOCPU1IPCSET Register Field Descriptions ................................................................... 1880
16-71. CMTOCPU1IPCCLR Register Field Descriptions................................................................... 1884
16-72. CMTOCPU1IPCFLG Register Field Descriptions ................................................................... 1888
16-73. IPCCOUNTERL Register Field Descriptions ........................................................................ 1892
16-74. IPCCOUNTERH Register Field Descriptions ........................................................................ 1893
16-75. CPU1TOCMIPCRECVCOM Register Field Descriptions .......................................................... 1894
16-76. CPU1TOCMIPCRECVADDR Register Field Descriptions ......................................................... 1895
16-77. CPU1TOCMIPCRECVDATA Register Field Descriptions ......................................................... 1896
16-78. CMTOCPU1IPCREPLY Register Field Descriptions ............................................................... 1897
16-79. CMTOCPU1IPCSENDCOM Register Field Descriptions .......................................................... 1898
16-80. CMTOCPU1IPCSENDADDR Register Field Descriptions ......................................................... 1899

SPRUII0B – May 2019 – Revised May 2020 List of Tables 111

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16-81. CMTOCPU1IPCSENDDATA Register Field Descriptions ......................................................... 1900

16-82. CPU1TOCMIPCREPLY Register Field Descriptions ............................................................... 1901
16-83. CMTOCPU1IPCBOOTSTS Register Field Descriptions ........................................................... 1902
16-84. CPU1TOCMIPCBOOTMODE Register Field Descriptions ........................................................ 1903
16-85. PUMPREQUEST Register Field Descriptions ....................................................................... 1904
16-86. CPU2TOCM_IPC_REGS_CPU2VIEW Registers ................................................................... 1905
16-87. CPU2TOCM_IPC_REGS_CPU2VIEW Access Type Codes ...................................................... 1905
16-88. CPU2TOCMIPCACK Register Field Descriptions .................................................................. 1906
16-89. CMTOCPU2IPCSTS Register Field Descriptions ................................................................... 1908
16-90. CPU2TOCMIPCSET Register Field Descriptions ................................................................... 1912
16-91. CPU2TOCMIPCCLR Register Field Descriptions................................................................... 1916
16-92. CPU2TOCMIPCFLG Register Field Descriptions ................................................................... 1920
16-93. IPCCOUNTERL Register Field Descriptions ........................................................................ 1924
16-94. IPCCOUNTERH Register Field Descriptions ........................................................................ 1925
16-95. CPU2TOCMIPCSENDCOM Register Field Descriptions .......................................................... 1926
16-96. CPU2TOCMIPCSENDADDR Register Field Descriptions ......................................................... 1927
16-97. CPU2TOCMIPCSENDDATA Register Field Descriptions ......................................................... 1928
16-98. CMTOCPU2IPCREPLY Register Field Descriptions ............................................................... 1929
16-99. CMTOCPU2IPCRECVCOM Register Field Descriptions .......................................................... 1930
16-100. CMTOCPU2IPCRECVADDR Register Field Descriptions ....................................................... 1931
16-101. CMTOCPU2IPCRECVDATA Register Field Descriptions ........................................................ 1932
16-102. CPU2TOCMIPCREPLY Register Field Descriptions .............................................................. 1933
16-103. CPU2TOCM_IPC_REGS_CMVIEW Registers .................................................................... 1934
16-104. CPU2TOCM_IPC_REGS_CMVIEW Access Type Codes ........................................................ 1934
16-105. CMTOCPU2IPCACK Register Field Descriptions ................................................................. 1935
16-106. CPU2TOCMIPCSTS Register Field Descriptions ................................................................. 1937
16-107. CMTOCPU2IPCSET Register Field Descriptions ................................................................. 1941
16-108. CMTOCPU2IPCCLR Register Field Descriptions ................................................................. 1945
16-109. CMTOCPU2IPCFLG Register Field Descriptions ................................................................. 1949
16-110. IPCCOUNTERL Register Field Descriptions ....................................................................... 1953
16-111. IPCCOUNTERH Register Field Descriptions ...................................................................... 1954
16-112. CPU2TOCMIPCRECVCOM Register Field Descriptions ......................................................... 1955
16-113. CPU2TOCMIPCRECVADDR Register Field Descriptions ....................................................... 1956
16-114. CPU2TOCMIPCRECVDATA Register Field Descriptions ........................................................ 1957
16-115. CMTOCPU2IPCREPLY Register Field Descriptions .............................................................. 1958
16-116. CMTOCPU2IPCSENDCOM Register Field Descriptions ......................................................... 1959
16-117. CMTOCPU2IPCSENDADDR Register Field Descriptions ....................................................... 1960
16-118. CMTOCPU2IPCSENDDATA Register Field Descriptions ........................................................ 1961
16-119. CPU2TOCMIPCREPLY Register Field Descriptions .............................................................. 1962
17-1. Input X-BAR Destinations .............................................................................................. 1964
17-2. CLB Input X-BAR Destinations ........................................................................................ 1966
17-3. ePWM X-BAR Mux Configuration Table ............................................................................. 1967
17-4. CLB X-BAR Mux Configuration Table ................................................................................ 1969
17-5. Output X-BAR Mux Configuration Table ............................................................................. 1971
17-6. CLB Output X-BAR Mux Configuration Table ....................................................................... 1973
17-7. XBAR Base Address Table (C28) ..................................................................................... 1976
17-8. XBAR_REGS Registers ................................................................................................ 1977
17-9. XBAR_REGS Access Type Codes ................................................................................... 1977
17-10. XBARFLG1 Register Field Descriptions.............................................................................. 1978

112 List of Tables SPRUII0B – May 2019 – Revised May 2020

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17-11. XBARFLG2 Register Field Descriptions.............................................................................. 1983

17-12. XBARFLG3 Register Field Descriptions.............................................................................. 1988
17-13. XBARFLG4 Register Field Descriptions.............................................................................. 1993
17-14. XBARCLR1 Register Field Descriptions ............................................................................. 1998
17-15. XBARCLR2 Register Field Descriptions ............................................................................. 2001
17-16. XBARCLR3 Register Field Descriptions ............................................................................. 2004
17-17. XBARCLR4 Register Field Descriptions ............................................................................. 2007
17-18. INPUT_XBAR_REGS Registers ...................................................................................... 2010
17-19. INPUT_XBAR_REGS Access Type Codes .......................................................................... 2010
17-20. INPUT1SELECT Register Field Descriptions........................................................................ 2011
17-21. INPUT2SELECT Register Field Descriptions........................................................................ 2012
17-22. INPUT3SELECT Register Field Descriptions........................................................................ 2013
17-23. INPUT4SELECT Register Field Descriptions........................................................................ 2014
17-24. INPUT5SELECT Register Field Descriptions........................................................................ 2015
17-25. INPUT6SELECT Register Field Descriptions........................................................................ 2016
17-26. INPUT7SELECT Register Field Descriptions........................................................................ 2017
17-27. INPUT8SELECT Register Field Descriptions........................................................................ 2018
17-28. INPUT9SELECT Register Field Descriptions........................................................................ 2019
17-29. INPUT10SELECT Register Field Descriptions ...................................................................... 2020
17-30. INPUT11SELECT Register Field Descriptions ...................................................................... 2021
17-31. INPUT12SELECT Register Field Descriptions ...................................................................... 2022
17-32. INPUT13SELECT Register Field Descriptions ...................................................................... 2023
17-33. INPUT14SELECT Register Field Descriptions ...................................................................... 2024
17-34. INPUT15SELECT Register Field Descriptions ...................................................................... 2025
17-35. INPUT16SELECT Register Field Descriptions ...................................................................... 2026
17-36. INPUTSELECTLOCK Register Field Descriptions .................................................................. 2027
17-37. OUTPUT_XBAR_REGS Registers ................................................................................... 2029
17-38. OUTPUT_XBAR_REGS Access Type Codes ....................................................................... 2029
17-39. OUTPUT1MUX0TO15CFG Register Field Descriptions ........................................................... 2031
17-40. OUTPUT1MUX16TO31CFG Register Field Descriptions.......................................................... 2034
17-41. OUTPUT2MUX0TO15CFG Register Field Descriptions ........................................................... 2037
17-42. OUTPUT2MUX16TO31CFG Register Field Descriptions.......................................................... 2040
17-43. OUTPUT3MUX0TO15CFG Register Field Descriptions ........................................................... 2043
17-44. OUTPUT3MUX16TO31CFG Register Field Descriptions.......................................................... 2046
17-45. OUTPUT4MUX0TO15CFG Register Field Descriptions ........................................................... 2049
17-46. OUTPUT4MUX16TO31CFG Register Field Descriptions.......................................................... 2052
17-47. OUTPUT5MUX0TO15CFG Register Field Descriptions ........................................................... 2055
17-48. OUTPUT5MUX16TO31CFG Register Field Descriptions.......................................................... 2058
17-49. OUTPUT6MUX0TO15CFG Register Field Descriptions ........................................................... 2061
17-50. OUTPUT6MUX16TO31CFG Register Field Descriptions.......................................................... 2064
17-51. OUTPUT7MUX0TO15CFG Register Field Descriptions ........................................................... 2067
17-52. OUTPUT7MUX16TO31CFG Register Field Descriptions.......................................................... 2070
17-53. OUTPUT8MUX0TO15CFG Register Field Descriptions ........................................................... 2073
17-54. OUTPUT8MUX16TO31CFG Register Field Descriptions.......................................................... 2076
17-55. OUTPUT1MUXENABLE Register Field Descriptions .............................................................. 2079
17-56. OUTPUT2MUXENABLE Register Field Descriptions .............................................................. 2083
17-57. OUTPUT3MUXENABLE Register Field Descriptions .............................................................. 2087
17-58. OUTPUT4MUXENABLE Register Field Descriptions .............................................................. 2091
17-59. OUTPUT5MUXENABLE Register Field Descriptions .............................................................. 2095

SPRUII0B – May 2019 – Revised May 2020 List of Tables 113

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17-60. OUTPUT6MUXENABLE Register Field Descriptions .............................................................. 2099

17-61. OUTPUT7MUXENABLE Register Field Descriptions .............................................................. 2103
17-62. OUTPUT8MUXENABLE Register Field Descriptions .............................................................. 2107
17-63. OUTPUTLATCH Register Field Descriptions ........................................................................ 2111
17-64. OUTPUTLATCHCLR Register Field Descriptions .................................................................. 2113
17-65. OUTPUTLATCHFRC Register Field Descriptions .................................................................. 2115
17-66. OUTPUTLATCHENABLE Register Field Descriptions ............................................................. 2117
17-67. OUTPUTINV Register Field Descriptions ............................................................................ 2119
17-68. OUTPUTLOCK Register Field Descriptions ......................................................................... 2121
17-69. EPWM_XBAR_REGS Registers ...................................................................................... 2122
17-70. EPWM_XBAR_REGS Access Type Codes ......................................................................... 2122
17-71. TRIP4MUX0TO15CFG Register Field Descriptions ................................................................ 2124
17-72. TRIP4MUX16TO31CFG Register Field Descriptions............................................................... 2127
17-73. TRIP5MUX0TO15CFG Register Field Descriptions ................................................................ 2130
17-74. TRIP5MUX16TO31CFG Register Field Descriptions............................................................... 2133
17-75. TRIP7MUX0TO15CFG Register Field Descriptions ................................................................ 2136
17-76. TRIP7MUX16TO31CFG Register Field Descriptions............................................................... 2139
17-77. TRIP8MUX0TO15CFG Register Field Descriptions ................................................................ 2142
17-78. TRIP8MUX16TO31CFG Register Field Descriptions............................................................... 2145
17-79. TRIP9MUX0TO15CFG Register Field Descriptions ................................................................ 2148
17-80. TRIP9MUX16TO31CFG Register Field Descriptions............................................................... 2151
17-81. TRIP10MUX0TO15CFG Register Field Descriptions............................................................... 2154
17-82. TRIP10MUX16TO31CFG Register Field Descriptions ............................................................. 2157
17-83. TRIP11MUX0TO15CFG Register Field Descriptions............................................................... 2160
17-84. TRIP11MUX16TO31CFG Register Field Descriptions ............................................................. 2163
17-85. TRIP12MUX0TO15CFG Register Field Descriptions............................................................... 2166
17-86. TRIP12MUX16TO31CFG Register Field Descriptions ............................................................. 2169
17-87. TRIP4MUXENABLE Register Field Descriptions ................................................................... 2172
17-88. TRIP5MUXENABLE Register Field Descriptions ................................................................... 2176
17-89. TRIP7MUXENABLE Register Field Descriptions ................................................................... 2180
17-90. TRIP8MUXENABLE Register Field Descriptions ................................................................... 2184
17-91. TRIP9MUXENABLE Register Field Descriptions ................................................................... 2188
17-92. TRIP10MUXENABLE Register Field Descriptions .................................................................. 2192
17-93. TRIP11MUXENABLE Register Field Descriptions .................................................................. 2196
17-94. TRIP12MUXENABLE Register Field Descriptions .................................................................. 2200
17-95. TRIPOUTINV Register Field Descriptions ........................................................................... 2204
17-96. TRIPLOCK Register Field Descriptions .............................................................................. 2206
17-97. CLB_XBAR_REGS Registers ......................................................................................... 2207
17-98. CLB_XBAR_REGS Access Type Codes ............................................................................. 2207
17-99. AUXSIG0MUX0TO15CFG Register Field Descriptions ............................................................ 2209
17-100. AUXSIG0MUX16TO31CFG Register Field Descriptions ......................................................... 2212
17-101. AUXSIG1MUX0TO15CFG Register Field Descriptions ........................................................... 2215
17-102. AUXSIG1MUX16TO31CFG Register Field Descriptions ......................................................... 2218
17-103. AUXSIG2MUX0TO15CFG Register Field Descriptions ........................................................... 2221
17-104. AUXSIG2MUX16TO31CFG Register Field Descriptions ......................................................... 2224
17-105. AUXSIG3MUX0TO15CFG Register Field Descriptions ........................................................... 2227
17-106. AUXSIG3MUX16TO31CFG Register Field Descriptions ......................................................... 2230
17-107. AUXSIG4MUX0TO15CFG Register Field Descriptions ........................................................... 2233
17-108. AUXSIG4MUX16TO31CFG Register Field Descriptions ......................................................... 2236

114 List of Tables SPRUII0B – May 2019 – Revised May 2020

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17-109. AUXSIG5MUX0TO15CFG Register Field Descriptions ........................................................... 2239

17-110. AUXSIG5MUX16TO31CFG Register Field Descriptions ......................................................... 2242
17-111. AUXSIG6MUX0TO15CFG Register Field Descriptions ........................................................... 2245
17-112. AUXSIG6MUX16TO31CFG Register Field Descriptions ......................................................... 2248
17-113. AUXSIG7MUX0TO15CFG Register Field Descriptions ........................................................... 2251
17-114. AUXSIG7MUX16TO31CFG Register Field Descriptions ......................................................... 2254
17-115. AUXSIG0MUXENABLE Register Field Descriptions .............................................................. 2257
17-116. AUXSIG1MUXENABLE Register Field Descriptions .............................................................. 2261
17-117. AUXSIG2MUXENABLE Register Field Descriptions .............................................................. 2265
17-118. AUXSIG3MUXENABLE Register Field Descriptions .............................................................. 2269
17-119. AUXSIG4MUXENABLE Register Field Descriptions .............................................................. 2273
17-120. AUXSIG5MUXENABLE Register Field Descriptions .............................................................. 2277
17-121. AUXSIG6MUXENABLE Register Field Descriptions .............................................................. 2281
17-122. AUXSIG7MUXENABLE Register Field Descriptions .............................................................. 2285
17-123. AUXSIGOUTINV Register Field Descriptions ...................................................................... 2289
17-124. AUXSIGLOCK Register Field Descriptions ......................................................................... 2291
17-125. EPWMXBAR Registers to Driverlib Functions ..................................................................... 2292
17-126. INPUTXBAR Registers to Driverlib Functions ..................................................................... 2293
17-127. OUTPUTXBAR Registers to Driverlib Functions .................................................................. 2294
17-128. XBAR Registers to Driverlib Functions.............................................................................. 2295
17-129. CLBXBAR Registers to Driverlib Functions ........................................................................ 2295
19-1. Analog Signal Descriptions ............................................................................................ 2303
19-2. Reference Summary .................................................................................................... 2303
19-3. ASBSYS Base Address Table (C28) ................................................................................. 2303
19-4. ANALOG_SUBSYS_REGS Registers ................................................................................ 2304
19-5. ANALOG_SUBSYS_REGS Access Type Codes ................................................................... 2304
19-6. INTOSC1TRIM Register Field Descriptions ......................................................................... 2305
19-7. INTOSC2TRIM Register Field Descriptions ......................................................................... 2306
19-8. TSNSCTL Register Field Descriptions ............................................................................... 2307
19-9. LOCK Register Field Descriptions .................................................................................... 2308
19-10. ANAREFTRIMA Register Field Descriptions ........................................................................ 2309
19-11. ANAREFTRIMB Register Field Descriptions ........................................................................ 2310
19-12. ANAREFTRIMC Register Field Descriptions ........................................................................ 2311
19-13. ANAREFTRIMD Register Field Descriptions ........................................................................ 2312
20-1. ADC Options and Configuration Levels .............................................................................. 2315
20-2. Analog to 12-bit Digital Formulas ..................................................................................... 2317
20-3. Analog to 16-bit Digital Formulas ..................................................................................... 2317
20-4. 12-Bit Digital-to-Analog Formulas .................................................................................... 2318
20-5. 16-Bit Digital-to-Analog Formulas .................................................................................... 2318
20-6. Channel Selection of Input Pins ....................................................................................... 2321
20-7. Example Requirements for Multiple Signal Sampling .............................................................. 2323
20-8. Example Connections for Multiple Signal Sampling ................................................................ 2323
20-9. DETECTCFG Settings .................................................................................................. 2334
20-10. ADC Timing Parameters ............................................................................................... 2338
20-11. ADC Timings in 12-bit Mode (SYSCLK Cycles) ..................................................................... 2342
20-12. ADC Timings in 16-bit Mode ........................................................................................... 2342
20-13. ADC Base Address Table (C28) ...................................................................................... 2352
20-14. ADC_REGS Registers .................................................................................................. 2353
20-15. ADC_REGS Access Type Codes ..................................................................................... 2354

SPRUII0B – May 2019 – Revised May 2020 List of Tables 115

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20-16. ADCCTL1 Register Field Descriptions ............................................................................... 2356

20-17. ADCCTL2 Register Field Descriptions ............................................................................... 2357
20-18. ADCBURSTCTL Register Field Descriptions ........................................................................ 2358
20-19. ADCINTFLG Register Field Descriptions ............................................................................ 2360
20-20. ADCINTFLGCLR Register Field Descriptions ....................................................................... 2362
20-21. ADCINTOVF Register Field Descriptions ............................................................................ 2364
20-22. ADCINTOVFCLR Register Field Descriptions ....................................................................... 2365
20-23. ADCINTSEL1N2 Register Field Descriptions........................................................................ 2366
20-24. ADCINTSEL3N4 Register Field Descriptions........................................................................ 2368
20-25. ADCSOCPRICTL Register Field Descriptions ...................................................................... 2370
20-26. ADCINTSOCSEL1 Register Field Descriptions ..................................................................... 2372
20-27. ADCINTSOCSEL2 Register Field Descriptions ..................................................................... 2374
20-28. ADCSOCFLG1 Register Field Descriptions ......................................................................... 2376
20-29. ADCSOCFRC1 Register Field Descriptions ......................................................................... 2380
20-30. ADCSOCOVF1 Register Field Descriptions ......................................................................... 2385
20-31. ADCSOCOVFCLR1 Register Field Descriptions .................................................................... 2388
20-32. ADCSOC0CTL Register Field Descriptions ......................................................................... 2392
20-33. ADCSOC1CTL Register Field Descriptions ......................................................................... 2395
20-34. ADCSOC2CTL Register Field Descriptions ......................................................................... 2398
20-35. ADCSOC3CTL Register Field Descriptions ......................................................................... 2401
20-36. ADCSOC4CTL Register Field Descriptions ......................................................................... 2404
20-37. ADCSOC5CTL Register Field Descriptions ......................................................................... 2407
20-38. ADCSOC6CTL Register Field Descriptions ......................................................................... 2410
20-39. ADCSOC7CTL Register Field Descriptions ......................................................................... 2413
20-40. ADCSOC8CTL Register Field Descriptions ......................................................................... 2416
20-41. ADCSOC9CTL Register Field Descriptions ......................................................................... 2419
20-42. ADCSOC10CTL Register Field Descriptions ........................................................................ 2422
20-43. ADCSOC11CTL Register Field Descriptions ........................................................................ 2425
20-44. ADCSOC12CTL Register Field Descriptions ........................................................................ 2428
20-45. ADCSOC13CTL Register Field Descriptions ........................................................................ 2431
20-46. ADCSOC14CTL Register Field Descriptions ........................................................................ 2434
20-47. ADCSOC15CTL Register Field Descriptions ........................................................................ 2437
20-48. ADCEVTSTAT Register Field Descriptions .......................................................................... 2439
20-49. ADCEVTCLR Register Field Descriptions ........................................................................... 2441
20-50. ADCEVTSEL Register Field Descriptions............................................................................ 2442
20-51. ADCEVTINTSEL Register Field Descriptions ....................................................................... 2444
20-52. ADCCOUNTER Register Field Descriptions......................................................................... 2446
20-53. ADCREV Register Field Descriptions ................................................................................ 2447
20-54. ADCOFFTRIM Register Field Descriptions .......................................................................... 2448
20-55. ADCPPB1CONFIG Register Field Descriptions..................................................................... 2449
20-56. ADCPPB1STAMP Register Field Descriptions ...................................................................... 2451
20-57. ADCPPB1OFFCAL Register Field Descriptions .................................................................... 2452
20-58. ADCPPB1OFFREF Register Field Descriptions .................................................................... 2453
20-59. ADCPPB1TRIPHI Register Field Descriptions ...................................................................... 2454
20-60. ADCPPB1TRIPLO Register Field Descriptions ..................................................................... 2455
20-61. ADCPPB2CONFIG Register Field Descriptions..................................................................... 2456
20-62. ADCPPB2STAMP Register Field Descriptions ...................................................................... 2458
20-63. ADCPPB2OFFCAL Register Field Descriptions .................................................................... 2459
20-64. ADCPPB2OFFREF Register Field Descriptions .................................................................... 2460

116 List of Tables SPRUII0B – May 2019 – Revised May 2020

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20-65. ADCPPB2TRIPHI Register Field Descriptions ...................................................................... 2461

20-66. ADCPPB2TRIPLO Register Field Descriptions ..................................................................... 2462
20-67. ADCPPB3CONFIG Register Field Descriptions..................................................................... 2463
20-68. ADCPPB3STAMP Register Field Descriptions ...................................................................... 2465
20-69. ADCPPB3OFFCAL Register Field Descriptions .................................................................... 2466
20-70. ADCPPB3OFFREF Register Field Descriptions .................................................................... 2467
20-71. ADCPPB3TRIPHI Register Field Descriptions ...................................................................... 2468
20-72. ADCPPB3TRIPLO Register Field Descriptions ..................................................................... 2469
20-73. ADCPPB4CONFIG Register Field Descriptions..................................................................... 2470
20-74. ADCPPB4STAMP Register Field Descriptions ...................................................................... 2472
20-75. ADCPPB4OFFCAL Register Field Descriptions .................................................................... 2473
20-76. ADCPPB4OFFREF Register Field Descriptions .................................................................... 2474
20-77. ADCPPB4TRIPHI Register Field Descriptions ...................................................................... 2475
20-78. ADCPPB4TRIPLO Register Field Descriptions ..................................................................... 2476
20-79. ADCINTCYCLE Register Field Descriptions......................................................................... 2477
20-80. ADCINLTRIM1 Register Field Descriptions .......................................................................... 2478
20-81. ADCINLTRIM2 Register Field Descriptions .......................................................................... 2479
20-82. ADCINLTRIM3 Register Field Descriptions .......................................................................... 2480
20-83. ADCINLTRIM4 Register Field Descriptions .......................................................................... 2481
20-84. ADCINLTRIM5 Register Field Descriptions .......................................................................... 2482
20-85. ADCINLTRIM6 Register Field Descriptions .......................................................................... 2483
20-86. ADC_RESULT_REGS Registers...................................................................................... 2485
20-87. ADC_RESULT_REGS Access Type Codes ......................................................................... 2485
20-88. ADCRESULT0 Register Field Descriptions .......................................................................... 2486
20-89. ADCRESULT1 Register Field Descriptions .......................................................................... 2487
20-90. ADCRESULT2 Register Field Descriptions .......................................................................... 2488
20-91. ADCRESULT3 Register Field Descriptions .......................................................................... 2489
20-92. ADCRESULT4 Register Field Descriptions .......................................................................... 2490
20-93. ADCRESULT5 Register Field Descriptions .......................................................................... 2491
20-94. ADCRESULT6 Register Field Descriptions .......................................................................... 2492
20-95. ADCRESULT7 Register Field Descriptions .......................................................................... 2493
20-96. ADCRESULT8 Register Field Descriptions .......................................................................... 2494
20-97. ADCRESULT9 Register Field Descriptions .......................................................................... 2495
20-98. ADCRESULT10 Register Field Descriptions ........................................................................ 2496
20-99. ADCRESULT11 Register Field Descriptions ........................................................................ 2497
20-100. ADCRESULT12 Register Field Descriptions ....................................................................... 2498
20-101. ADCRESULT13 Register Field Descriptions ....................................................................... 2499
20-102. ADCRESULT14 Register Field Descriptions ....................................................................... 2500
20-103. ADCRESULT15 Register Field Descriptions ....................................................................... 2501
20-104. ADCPPB1RESULT Register Field Descriptions ................................................................... 2502
20-105. ADCPPB2RESULT Register Field Descriptions ................................................................... 2503
20-106. ADCPPB3RESULT Register Field Descriptions ................................................................... 2504
20-107. ADCPPB4RESULT Register Field Descriptions ................................................................... 2505
20-108. ADC Registers to Driverlib Functions ............................................................................... 2506
21-1. DAC Base Address Table (C28) ...................................................................................... 2513
21-2. DAC_REGS Registers .................................................................................................. 2514
21-3. DAC_REGS Access Type Codes ..................................................................................... 2514
21-4. DACREV Register Field Descriptions ................................................................................ 2515
21-5. DACCTL Register Field Descriptions ................................................................................. 2516

SPRUII0B – May 2019 – Revised May 2020 List of Tables 117

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21-6. DACVALA Register Field Descriptions ............................................................................... 2517

21-7. DACVALS Register Field Descriptions ............................................................................... 2518
21-8. DACOUTEN Register Field Descriptions ............................................................................ 2519
21-9. DACLOCK Register Field Descriptions............................................................................... 2520
21-10. DACTRIM Register Field Descriptions ............................................................................... 2521
21-11. DAC Registers to Driverlib Functions ................................................................................. 2522
22-1. CMPSS Base Address Table (C28) .................................................................................. 2533
22-2. CMPSS_REGS Registers .............................................................................................. 2534
22-3. CMPSS_REGS Access Type Codes ................................................................................. 2534
22-4. COMPCTL Register Field Descriptions .............................................................................. 2536
22-5. COMPHYSCTL Register Field Descriptions ......................................................................... 2538
22-6. COMPSTS Register Field Descriptions .............................................................................. 2539
22-7. COMPSTSCLR Register Field Descriptions ......................................................................... 2540
22-8. COMPDACCTL Register Field Descriptions ......................................................................... 2541
22-9. DACHVALS Register Field Descriptions ............................................................................. 2543
22-10. DACHVALA Register Field Descriptions ............................................................................. 2544
22-11. RAMPMAXREFA Register Field Descriptions ....................................................................... 2545
22-12. RAMPMAXREFS Register Field Descriptions ....................................................................... 2546
22-13. RAMPDECVALA Register Field Descriptions ....................................................................... 2547
22-14. RAMPDECVALS Register Field Descriptions ....................................................................... 2548
22-15. RAMPSTS Register Field Descriptions............................................................................... 2549
22-16. DACLVALS Register Field Descriptions.............................................................................. 2550
22-17. DACLVALA Register Field Descriptions.............................................................................. 2551
22-18. RAMPDLYA Register Field Descriptions ............................................................................. 2552
22-19. RAMPDLYS Register Field Descriptions ............................................................................. 2553
22-20. CTRIPLFILCTL Register Field Descriptions ......................................................................... 2554
22-21. CTRIPLFILCLKCTL Register Field Descriptions .................................................................... 2555
22-22. CTRIPHFILCTL Register Field Descriptions......................................................................... 2556
22-23. CTRIPHFILCLKCTL Register Field Descriptions ................................................................... 2557
22-24. COMPLOCK Register Field Descriptions ............................................................................ 2558
22-25. CMPSS Registers to Driverlib Functions ............................................................................. 2559
24-1. eCAP Input Selection ................................................................................................... 2565
24-2. ECAP Base Address Table (C28) ..................................................................................... 2583
24-3. ECAP_REGS Registers ................................................................................................ 2584
24-4. ECAP_REGS Access Type Codes ................................................................................... 2584
24-5. TSCTR Register Field Descriptions ................................................................................... 2585
24-6. CTRPHS Register Field Descriptions................................................................................. 2586
24-7. CAP1 Register Field Descriptions..................................................................................... 2587
24-8. CAP2 Register Field Descriptions..................................................................................... 2588
24-9. CAP3 Register Field Descriptions..................................................................................... 2589
24-10. CAP4 Register Field Descriptions..................................................................................... 2590
24-11. ECCTL0 Register Field Descriptions ................................................................................. 2591
24-12. ECCTL1 Register Field Descriptions ................................................................................. 2592
24-13. ECCTL2 Register Field Descriptions ................................................................................. 2594
24-14. ECEINT Register Field Descriptions .................................................................................. 2597
24-15. ECFLG Register Field Descriptions ................................................................................... 2599
..................................................................................
24-16. ECCLR Register Field Descriptions 2600
..................................................................................
24-17. ECFRC Register Field Descriptions 2601
24-18. ECAPSYNCINSEL Register Field Descriptions ..................................................................... 2602

118 List of Tables SPRUII0B – May 2019 – Revised May 2020

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24-19. ECAP Registers to Driverlib Functions ............................................................................... 2603

25-1. Scale Factor.............................................................................................................. 2610
25-2. HRCAP Base Address Table (C28)................................................................................... 2610
25-3. HRCAP_REGS Registers .............................................................................................. 2611
25-4. HRCAP_REGS Access Type Codes ................................................................................. 2611
25-5. HRCTL Register Field Descriptions ................................................................................... 2612
25-6. HRINTEN Register Field Descriptions ................................................................................ 2613
25-7. HRFLG Register Field Descriptions .................................................................................. 2614
25-8. HRCLR Register Field Descriptions .................................................................................. 2615
25-9. HRFRC Register Field Descriptions .................................................................................. 2616
25-10. HRCALPRD Register Field Descriptions ............................................................................. 2617
25-11. HRSYSCLKCTR Register Field Descriptions........................................................................ 2618
25-12. HRSYSCLKCAP Register Field Descriptions........................................................................ 2619
25-13. HRCLKCTR Register Field Descriptions ............................................................................. 2620
25-14. HRCLKCAP Register Field Descriptions ............................................................................. 2621
26-1. Submodule Configuration Parameters................................................................................ 2630
26-2. Key Time-Base Signals ................................................................................................. 2634
26-3. ePWM SYNC Selection ................................................................................................ 2639
26-4. Action-Qualifier Submodule Possible Input Events ................................................................. 2652
26-5. Action-Qualifier Event Priority for Up-Down-Count Mode .......................................................... 2654
26-6. Action-Qualifier Event Priority for Up-Count Mode.................................................................. 2654
26-7. Action-Qualifier Event Priority for Down-Count Mode .............................................................. 2654
26-8. Behavior if CMPA/CMPB is Greater than the Period ............................................................... 2655
26-9. Classical Dead-Band Operating Modes ............................................................................. 2667
26-10. Additional Dead-Band Operating Modes ............................................................................. 2667
26-11. Dead-Band Delay Values in μS as a Function of DBFED and DBRED ......................................... 2669
26-12. Possible Pulse Width Values for EPWMCLK = 80 MHz ........................................................... 2672
26-13. Possible Actions On a Trip Event ..................................................................................... 2676
26-14. Lock Bits and Corresponding Registers .............................................................................. 2712
26-15. Resolution for PWM and HRPWM .................................................................................... 2714
26-16. Relationship Between MEP Steps, PWM Frequency and Resolution ............................................ 2720
26-17. CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right)....................................................... 2722
26-18. Duty Cycle Range Limitation for Three EPWMCLK/TBCLK Cycles .............................................. 2725
26-19. SFO Library Features ................................................................................................... 2736
26-20. Factor Values ............................................................................................................ 2737
26-21. EPWM Base Address Table (C28) .................................................................................... 2739
26-22. EPWM_REGS Registers ............................................................................................... 2740
26-23. EPWM_REGS Access Type Codes .................................................................................. 2742
26-24. TBCTL Register Field Descriptions ................................................................................... 2743
26-25. TBCTL2 Register Field Descriptions.................................................................................. 2745
26-26. EPWMSYNCINSEL Register Field Descriptions .................................................................... 2746
26-27. TBCTR Register Field Descriptions ................................................................................... 2747
26-28. TBSTS Register Field Descriptions ................................................................................... 2748
26-29. EPWMSYNCOUTEN Register Field Descriptions .................................................................. 2749
26-30. TBCTL3 Register Field Descriptions.................................................................................. 2751
26-31. CMPCTL Register Field Descriptions................................................................................. 2752
26-32. CMPCTL2 Register Field Descriptions ............................................................................... 2754
26-33. DBCTL Register Field Descriptions ................................................................................... 2756
26-34. DBCTL2 Register Field Descriptions ................................................................................. 2759

SPRUII0B – May 2019 – Revised May 2020 List of Tables 119

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26-35. AQCTL Register Field Descriptions ................................................................................... 2760

26-36. AQTSRCSEL Register Field Descriptions ........................................................................... 2762
26-37. PCCTL Register Field Descriptions ................................................................................... 2763
26-38. VCAPCTL Register Field Descriptions ............................................................................... 2764
26-39. VCNTCFG Register Field Descriptions............................................................................... 2766
26-40. HRCNFG Register Field Descriptions ................................................................................ 2768
26-41. HRPWR Register Field Descriptions ................................................................................. 2770
26-42. HRMSTEP Register Field Descriptions .............................................................................. 2771
26-43. HRCNFG2 Register Field Descriptions............................................................................... 2772
26-44. HRPCTL Register Field Descriptions ................................................................................. 2773
26-45. TRREM Register Field Descriptions .................................................................................. 2775
26-46. GLDCTL Register Field Descriptions ................................................................................. 2776
26-47. GLDCFG Register Field Descriptions ................................................................................ 2778
26-48. EPWMXLINK Register Field Descriptions ........................................................................... 2780
26-49. AQCTLA Register Field Descriptions ................................................................................. 2783
26-50. AQCTLA2 Register Field Descriptions ............................................................................... 2785
26-51. AQCTLB Register Field Descriptions ................................................................................. 2786
26-52. AQCTLB2 Register Field Descriptions ............................................................................... 2788
26-53. AQSFRC Register Field Descriptions ................................................................................ 2789
26-54. AQCSFRC Register Field Descriptions .............................................................................. 2790
26-55. DBREDHR Register Field Descriptions .............................................................................. 2791
26-56. DBRED Register Field Descriptions .................................................................................. 2792
26-57. DBFEDHR Register Field Descriptions............................................................................... 2793
26-58. DBFED Register Field Descriptions .................................................................................. 2794
26-59. TBPHS Register Field Descriptions ................................................................................... 2795
26-60. TBPRDHR Register Field Descriptions............................................................................... 2796
26-61. TBPRD Register Field Descriptions .................................................................................. 2797
26-62. CMPA Register Field Descriptions .................................................................................... 2798
26-63. CMPB Register Field Descriptions .................................................................................... 2799
26-64. CMPC Register Field Descriptions .................................................................................... 2800
26-65. CMPD Register Field Descriptions .................................................................................... 2801
26-66. GLDCTL2 Register Field Descriptions ............................................................................... 2802
26-67. SWVDELVAL Register Field Descriptions ........................................................................... 2803
26-68. TZSEL Register Field Descriptions ................................................................................... 2804
26-69. TZDCSEL Register Field Descriptions ............................................................................... 2806
26-70. TZCTL Register Field Descriptions ................................................................................... 2807
26-71. TZCTL2 Register Field Descriptions .................................................................................. 2808
26-72. TZCTLDCA Register Field Descriptions.............................................................................. 2810
26-73. TZCTLDCB Register Field Descriptions.............................................................................. 2811
26-74. TZEINT Register Field Descriptions .................................................................................. 2812
26-75. TZFLG Register Field Descriptions ................................................................................... 2813
26-76. TZCBCFLG Register Field Descriptions ............................................................................. 2815
26-77. TZOSTFLG Register Field Descriptions.............................................................................. 2816
26-78. TZCLR Register Field Descriptions ................................................................................... 2817
26-79. TZCBCCLR Register Field Descriptions ............................................................................. 2818
26-80. TZOSTCLR Register Field Descriptions ............................................................................. 2819
26-81. TZFRC Register Field Descriptions ................................................................................... 2820
26-82. ETSEL Register Field Descriptions ................................................................................... 2821
26-83. ETPS Register Field Descriptions..................................................................................... 2823

120 List of Tables SPRUII0B – May 2019 – Revised May 2020

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26-84. ETFLG Register Field Descriptions ................................................................................... 2826

26-85. ETCLR Register Field Descriptions ................................................................................... 2827
26-86. ETFRC Register Field Descriptions ................................................................................... 2828
26-87. ETINTPS Register Field Descriptions ................................................................................ 2829
26-88. ETSOCPS Register Field Descriptions ............................................................................... 2830
26-89. ETCNTINITCTL Register Field Descriptions ........................................................................ 2831
26-90. ETCNTINIT Register Field Descriptions.............................................................................. 2832
26-91. DCTRIPSEL Register Field Descriptions ............................................................................ 2833
26-92. DCACTL Register Field Descriptions ................................................................................. 2835
26-93. DCBCTL Register Field Descriptions ................................................................................. 2837
26-94. DCFCTL Register Field Descriptions ................................................................................. 2839
26-95. DCCAPCTL Register Field Descriptions ............................................................................. 2841
26-96. DCFOFFSET Register Field Descriptions ........................................................................... 2843
26-97. DCFOFFSETCNT Register Field Descriptions ...................................................................... 2844
26-98. DCFWINDOW Register Field Descriptions .......................................................................... 2845
26-99. DCFWINDOWCNT Register Field Descriptions ..................................................................... 2846
26-100. DCCAP Register Field Descriptions ................................................................................. 2847
26-101. DCAHTRIPSEL Register Field Descriptions ....................................................................... 2848
26-102. DCALTRIPSEL Register Field Descriptions ........................................................................ 2850
26-103. DCBHTRIPSEL Register Field Descriptions ....................................................................... 2852
26-104. DCBLTRIPSEL Register Field Descriptions ........................................................................ 2854
26-105. EPWMLOCK Register Field Descriptions .......................................................................... 2856
26-106. HWVDELVAL Register Field Descriptions.......................................................................... 2857
26-107. VCNTVAL Register Field Descriptions .............................................................................. 2858
26-108. SYNC_SOC_REGS Registers ....................................................................................... 2859
26-109. SYNC_SOC_REGS Access Type Codes .......................................................................... 2859
26-110. SYNCSELECT Register Field Descriptions ........................................................................ 2860
26-111. ADCSOCOUTSELECT Register Field Descriptions .............................................................. 2861
26-112. SYNCSOCLOCK Register Field Descriptions...................................................................... 2864
26-113. EPWM Registers to Driverlib Functions............................................................................. 2865
26-114. HRPWM Registers to Driverlib Functions .......................................................................... 2871
27-1. EQEP Input Source Select Table ..................................................................................... 2878
27-2. EQEP Memory Map .................................................................................................... 2880
27-3. Quadrature Decoder Truth Table ..................................................................................... 2882
27-4. EQEP Base Address Table (C28) .................................................................................... 2899
27-5. EQEP_REGS Registers ................................................................................................ 2900
27-6. EQEP_REGS Access Type Codes ................................................................................... 2900
27-7. QPOSCNT Register Field Descriptions .............................................................................. 2902
27-8. QPOSINIT Register Field Descriptions ............................................................................... 2903
27-9. QPOSMAX Register Field Descriptions .............................................................................. 2904
27-10. QPOSCMP Register Field Descriptions .............................................................................. 2905
27-11. QPOSILAT Register Field Descriptions .............................................................................. 2906
27-12. QPOSSLAT Register Field Descriptions ............................................................................. 2907
27-13. QPOSLAT Register Field Descriptions ............................................................................... 2908
27-14. QUTMR Register Field Descriptions .................................................................................. 2909
27-15. QUPRD Register Field Descriptions .................................................................................. 2910
27-16. QWDTMR Register Field Descriptions ............................................................................... 2911
27-17. QWDPRD Register Field Descriptions ............................................................................... 2912
27-18. QDECCTL Register Field Descriptions ............................................................................... 2913

SPRUII0B – May 2019 – Revised May 2020 List of Tables 121

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27-19. QEPCTL Register Field Descriptions ................................................................................. 2915

27-20. QCAPCTL Register Field Descriptions ............................................................................... 2918
27-21. QPOSCTL Register Field Descriptions ............................................................................... 2919
27-22. QEINT Register Field Descriptions ................................................................................... 2920
27-23. QFLG Register Field Descriptions .................................................................................... 2922
27-24. QCLR Register Field Descriptions .................................................................................... 2924
27-25. QFRC Register Field Descriptions .................................................................................... 2926
27-26. QEPSTS Register Field Descriptions ................................................................................. 2928
27-27. QCTMR Register Field Descriptions .................................................................................. 2930
27-28. QCPRD Register Field Descriptions .................................................................................. 2931
27-29. QCTMRLAT Register Field Descriptions ............................................................................. 2932
27-30. QCPRDLAT Register Field Descriptions ............................................................................. 2933
27-31. REV Register Field Descriptions ...................................................................................... 2934
27-32. QEPSTROBESEL Register Field Descriptions ...................................................................... 2935
27-33. QMACTRL Register Field Descriptions .............................................................................. 2936
27-34. QEPSRCSEL Register Field Descriptions ........................................................................... 2937
27-35. EQEP Registers to Driverlib Functions ............................................................................... 2939
28-1. Modulator Clock Modes ................................................................................................ 2947
28-2. Order of Sinc Filter ...................................................................................................... 2949
28-3. Peak Data Values for Different DOSR/Filter Combinations ....................................................... 2950
28-4. Shift Control Bit Configuration Settings .............................................................................. 2951
28-5. SDSYNCx.SYNCSEL ................................................................................................... 2953
28-6. Number of Incorrect Samples Tabulated ............................................................................. 2954
28-7. Peak Data Values for Different OSR/Filter Combinations ......................................................... 2955
28-8. SDFM Data-Ready Interrupt (SDy_DRINTx) Output Selection ................................................... 2961
28-9. SDFM Base Address Table (C28) .................................................................................... 2962
28-10. SDFM_REGS Registers ................................................................................................ 2963
28-11. SDFM_REGS Access Type Codes ................................................................................... 2965
28-12. SDIFLG Register Field Descriptions .................................................................................. 2966
28-13. SDIFLGCLR Register Field Descriptions ............................................................................ 2968
28-14. SDCTL Register Field Descriptions ................................................................................... 2970
28-15. SDMFILEN Register Field Descriptions .............................................................................. 2971
28-16. SDSTATUS Register Field Descriptions ............................................................................. 2972
28-17. SDCTLPARM1 Register Field Descriptions ......................................................................... 2973
28-18. SDDFPARM1 Register Field Descriptions ........................................................................... 2974
28-19. SDDPARM1 Register Field Descriptions ............................................................................. 2975
28-20. SDFLT1CMPH1 Register Field Descriptions ........................................................................ 2976
28-21. SDFLT1CMPL1 Register Field Descriptions......................................................................... 2977
28-22. SDCPARM1 Register Field Descriptions ............................................................................. 2978
28-23. SDDATA1 Register Field Descriptions ............................................................................... 2979
28-24. SDDATFIFO1 Register Field Descriptions ........................................................................... 2980
28-25. SDCDATA1 Register Field Descriptions ............................................................................. 2981
28-26. SDFLT1CMPH2 Register Field Descriptions ........................................................................ 2982
28-27. SDFLT1CMPHZ Register Field Descriptions ........................................................................ 2983
28-28. SDFIFOCTL1 Register Field Descriptions ........................................................................... 2984
28-29. SDSYNC1 Register Field Descriptions ............................................................................... 2985
28-30. SDFLT1CMPL2 Register Field Descriptions......................................................................... 2986
28-31. SDCTLPARM2 Register Field Descriptions ......................................................................... 2987
28-32. SDDFPARM2 Register Field Descriptions ........................................................................... 2988

122 List of Tables SPRUII0B – May 2019 – Revised May 2020

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28-33. SDDPARM2 Register Field Descriptions ............................................................................. 2989

28-34. SDFLT2CMPH1 Register Field Descriptions ........................................................................ 2990
28-35. SDFLT2CMPL1 Register Field Descriptions......................................................................... 2991
28-36. SDCPARM2 Register Field Descriptions ............................................................................. 2992
28-37. SDDATA2 Register Field Descriptions ............................................................................... 2993
28-38. SDDATFIFO2 Register Field Descriptions ........................................................................... 2994
28-39. SDCDATA2 Register Field Descriptions ............................................................................. 2995
28-40. SDFLT2CMPH2 Register Field Descriptions ........................................................................ 2996
28-41. SDFLT2CMPHZ Register Field Descriptions ........................................................................ 2997
28-42. SDFIFOCTL2 Register Field Descriptions ........................................................................... 2998
28-43. SDSYNC2 Register Field Descriptions ............................................................................... 2999
28-44. SDFLT2CMPL2 Register Field Descriptions......................................................................... 3000
28-45. SDCTLPARM3 Register Field Descriptions ......................................................................... 3001
28-46. SDDFPARM3 Register Field Descriptions ........................................................................... 3002
28-47. SDDPARM3 Register Field Descriptions ............................................................................. 3003
28-48. SDFLT3CMPH1 Register Field Descriptions ........................................................................ 3004
28-49. SDFLT3CMPL1 Register Field Descriptions......................................................................... 3005
28-50. SDCPARM3 Register Field Descriptions ............................................................................. 3006
28-51. SDDATA3 Register Field Descriptions ............................................................................... 3007
28-52. SDDATFIFO3 Register Field Descriptions ........................................................................... 3008
28-53. SDCDATA3 Register Field Descriptions ............................................................................. 3009
28-54. SDFLT3CMPH2 Register Field Descriptions ........................................................................ 3010
28-55. SDFLT3CMPHZ Register Field Descriptions ........................................................................ 3011
28-56. SDFIFOCTL3 Register Field Descriptions ........................................................................... 3012
28-57. SDSYNC3 Register Field Descriptions ............................................................................... 3013
28-58. SDFLT3CMPL2 Register Field Descriptions......................................................................... 3014
28-59. SDCTLPARM4 Register Field Descriptions ......................................................................... 3015
28-60. SDDFPARM4 Register Field Descriptions ........................................................................... 3016
28-61. SDDPARM4 Register Field Descriptions ............................................................................. 3017
28-62. SDFLT4CMPH1 Register Field Descriptions ........................................................................ 3018
28-63. SDFLT4CMPL1 Register Field Descriptions......................................................................... 3019
28-64. SDCPARM4 Register Field Descriptions ............................................................................. 3020
28-65. SDDATA4 Register Field Descriptions ............................................................................... 3021
28-66. SDDATFIFO4 Register Field Descriptions ........................................................................... 3022
28-67. SDCDATA4 Register Field Descriptions ............................................................................. 3023
28-68. SDFLT4CMPH2 Register Field Descriptions ........................................................................ 3024
28-69. SDFLT4CMPHZ Register Field Descriptions ........................................................................ 3025
28-70. SDFIFOCTL4 Register Field Descriptions ........................................................................... 3026
28-71. SDSYNC4 Register Field Descriptions ............................................................................... 3027
28-72. SDFLT4CMPL2 Register Field Descriptions......................................................................... 3028
28-73. SDCOMP1CTL Register Field Descriptions ......................................................................... 3029
28-74. SDCOMP1EVT2FLTCTL Register Field Descriptions .............................................................. 3030
28-75. SDCOMP1EVT2FLTCLKCTL Register Field Descriptions ........................................................ 3031
28-76. SDCOMP1EVT1FLTCTL Register Field Descriptions .............................................................. 3032
28-77. SDCOMP1EVT1FLTCLKCTL Register Field Descriptions ........................................................ 3033
28-78. SDCOMP1LOCK Register Field Descriptions ....................................................................... 3034
28-79. SDCOMP2CTL Register Field Descriptions ......................................................................... 3035
28-80. SDCOMP2EVT2FLTCTL Register Field Descriptions .............................................................. 3036
28-81. SDCOMP2EVT2FLTCLKCTL Register Field Descriptions ........................................................ 3037

SPRUII0B – May 2019 – Revised May 2020 List of Tables 123

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28-82. SDCOMP2EVT1FLTCTL Register Field Descriptions .............................................................. 3038

28-83. SDCOMP2EVT1FLTCLKCTL Register Field Descriptions ........................................................ 3039
28-84. SDCOMP2LOCK Register Field Descriptions ....................................................................... 3040
28-85. SDCOMP3CTL Register Field Descriptions ......................................................................... 3041
28-86. SDCOMP3EVT2FLTCTL Register Field Descriptions .............................................................. 3042
28-87. SDCOMP3EVT2FLTCLKCTL Register Field Descriptions ........................................................ 3043
28-88. SDCOMP3EVT1FLTCTL Register Field Descriptions .............................................................. 3044
28-89. SDCOMP3EVT1FLTCLKCTL Register Field Descriptions ........................................................ 3045
28-90. SDCOMP3LOCK Register Field Descriptions ....................................................................... 3046
28-91. SDCOMP4CTL Register Field Descriptions ......................................................................... 3047
28-92. SDCOMP4EVT2FLTCTL Register Field Descriptions .............................................................. 3048
28-93. SDCOMP4EVT2FLTCLKCTL Register Field Descriptions ........................................................ 3049
28-94. SDCOMP4EVT1FLTCTL Register Field Descriptions .............................................................. 3050
28-95. SDCOMP4EVT1FLTCLKCTL Register Field Descriptions ........................................................ 3051
28-96. SDCOMP4LOCK Register Field Descriptions ....................................................................... 3052
28-97. SDFM Registers to Driverlib Functions ............................................................................... 3053
30-1. CAN Register Access From Software ................................................................................ 3062
30-2. CAN Register Access From Code Composer Studio™ ............................................................ 3063
30-3. PIE Nomenclature for Interrupts ....................................................................................... 3069
30-4. Programmable Ranges Required by CAN Protocol ................................................................ 3080
30-5. Message Object Field Descriptions ................................................................................... 3090
30-6. Message RAM Addressing in Debug Mode ......................................................................... 3092
30-7. CAN Base Address Table (C28) ...................................................................................... 3094
30-8. CAN Base Address Table (CM) ....................................................................................... 3094
30-9. CAN_REGS Registers .................................................................................................. 3095
30-10. CAN_REGS Access Type Codes ..................................................................................... 3096
30-11. CAN_CTL Register Field Descriptions ............................................................................... 3097
30-12. CAN_ES Register Field Descriptions ................................................................................. 3100
30-13. CAN_ERRC Register Field Descriptions ............................................................................. 3102
30-14. CAN_BTR Register Field Descriptions ............................................................................... 3103
30-15. CAN_INT Register Field Descriptions ................................................................................ 3104
30-16. CAN_TEST Register Field Descriptions.............................................................................. 3105
30-17. CAN_PERR Register Field Descriptions ............................................................................. 3106
30-18. CAN_RAM_INIT Register Field Descriptions ........................................................................ 3107
30-19. CAN_GLB_INT_EN Register Field Descriptions .................................................................... 3108
30-20. CAN_GLB_INT_FLG Register Field Descriptions .................................................................. 3109
30-21. CAN_GLB_INT_CLR Register Field Descriptions .................................................................. 3110
30-22. CAN_ABOTR Register Field Descriptions ........................................................................... 3111
30-23. CAN_TXRQ_X Register Field Descriptions .......................................................................... 3112
30-24. CAN_TXRQ_21 Register Field Descriptions ........................................................................ 3113
30-25. CAN_NDAT_X Register Field Descriptions .......................................................................... 3114
30-26. CAN_NDAT_21 Register Field Descriptions......................................................................... 3115
30-27. CAN_IPEN_X Register Field Descriptions ........................................................................... 3116
30-28. CAN_IPEN_21 Register Field Descriptions .......................................................................... 3117
30-29. CAN_MVAL_X Register Field Descriptions .......................................................................... 3118
30-30. CAN_MVAL_21 Register Field Descriptions......................................................................... 3119
30-31. CAN_IP_MUX21 Register Field Descriptions ....................................................................... 3120
30-32. CAN_IF1CMD Register Field Descriptions .......................................................................... 3121
30-33. CAN_IF1MSK Register Field Descriptions ........................................................................... 3124

124 List of Tables SPRUII0B – May 2019 – Revised May 2020

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30-34. CAN_IF1ARB Register Field Descriptions ........................................................................... 3125

30-35. CAN_IF1MCTL Register Field Descriptions ......................................................................... 3127
30-36. CAN_IF1DATA Register Field Descriptions ......................................................................... 3129
30-37. CAN_IF1DATB Register Field Descriptions ......................................................................... 3130
30-38. CAN_IF2CMD Register Field Descriptions .......................................................................... 3131
30-39. CAN_IF2MSK Register Field Descriptions ........................................................................... 3134
30-40. CAN_IF2ARB Register Field Descriptions ........................................................................... 3135
30-41. CAN_IF2MCTL Register Field Descriptions ......................................................................... 3137
30-42. CAN_IF2DATA Register Field Descriptions ......................................................................... 3139
30-43. CAN_IF2DATB Register Field Descriptions ......................................................................... 3140
30-44. CAN_IF3OBS Register Field Descriptions ........................................................................... 3141
30-45. CAN_IF3MSK Register Field Descriptions ........................................................................... 3143
30-46. CAN_IF3ARB Register Field Descriptions ........................................................................... 3144
30-47. CAN_IF3MCTL Register Field Descriptions ......................................................................... 3145
30-48. CAN_IF3DATA Register Field Descriptions ......................................................................... 3147
30-49. CAN_IF3DATB Register Field Descriptions ......................................................................... 3148
30-50. CAN_IF3UPD Register Field Descriptions ........................................................................... 3149
30-51. CAN Registers to Driverlib Functions ................................................................................. 3150
31-1. Abbreviations ............................................................................................................ 3153
31-2. F2838x ESC vs Beckhoff ET1100 .................................................................................... 3154
31-3. EtherCAT Physical Layer Signals ..................................................................................... 3158
31-4. EtherCAT IP Errata ..................................................................................................... 3162
31-5. ESC Integration Figure Sections ...................................................................................... 3164
31-6. ESC Address Map On CPU1 .......................................................................................... 3164
31-7. ESC Address Map on CM ............................................................................................. 3165
31-8. Service Request Generation Map ..................................................................................... 3168
31-9. Status LED Options and Priority ...................................................................................... 3171
31-10. ESC SYNC Integration Map ........................................................................................... 3176
31-11. ESC LATCH0/1 Trigger Table ......................................................................................... 3179
31-12. CPU1 Software Initialization Sequence .............................................................................. 3182
31-13. CM Software Initialization Sequence ................................................................................. 3183
31-14. ESC Configuration Constants Table .................................................................................. 3183
31-15. ESC IP Register Constants Table .................................................................................... 3183
31-16. EtherCAT IP Register Documentation ................................................................................ 3184
31-17. ECAT Base Address Table (C28) ..................................................................................... 3184
31-18. CM ECAT Base Address Table (CM)................................................................................. 3184
31-19. ESCSS_CONFIG_REGS Registers .................................................................................. 3185
31-20. ESCSS_CONFIG_REGS Access Type Codes...................................................................... 3185
31-21. ESCSS_CONFIG_LOCK Register Field Descriptions .............................................................. 3186
31-22. ESCSS_MISC_IO_CONFIG Register Field Descriptions .......................................................... 3187
31-23. ESCSS_PHY_IO_CONFIG Register Field Descriptions ........................................................... 3188
31-24. ESCSS_SYNC_IO_CONFIG Register Field Descriptions ......................................................... 3189
31-25. ESCSS_LATCH_IO_CONFIG Register Field Descriptions ........................................................ 3190
31-26. ESCSS_GPIN_SEL Register Field Descriptions .................................................................... 3191
31-27. ESCSS_GPIN_IOPAD_SEL Register Field Descriptions .......................................................... 3192
31-28. ESCSS_GPOUT_SEL Register Field Descriptions ................................................................. 3193
31-29. ESCSS_GPOUT_IOPAD_SEL Register Field Descriptions ....................................................... 3194
31-30. ESCSS_LED_CONFIG Register Field Descriptions ................................................................ 3195
31-31. ESCSS_MISC_CONFIG Register Field Descriptions .............................................................. 3197

SPRUII0B – May 2019 – Revised May 2020 List of Tables 125

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31-32. ESCSS_REGS Registers .............................................................................................. 3198

31-33. ESCSS_REGS Access Type Codes.................................................................................. 3198
31-34. ESCSS_IPREVNUM Register Field Descriptions ................................................................... 3200
31-35. ESCSS_INTR_RIS Register Field Descriptions ..................................................................... 3201
31-36. ESCSS_INTR_MASK Register Field Descriptions.................................................................. 3203
31-37. ESCSS_INTR_MIS Register Field Descriptions .................................................................... 3204
31-38. ESCSS_INTR_CLR Register Field Descriptions .................................................................... 3206
31-39. ESCSS_INTR_SET Register Field Descriptions .................................................................... 3207
31-40. ESCSS_LATCH_SEL Register Field Descriptions.................................................................. 3209
31-41. ESCSS_ACCESS_CTRL Register Field Descriptions ............................................................. 3210
31-42. ESCSS_GPIN_DAT Register Field Descriptions ................................................................... 3211
31-43. ESCSS_GPIN_PIPE Register Field Descriptions ................................................................... 3212
31-44. ESCSS_GPIN_GRP_CAP_SEL Register Field Descriptions ..................................................... 3213
31-45. ESCSS_GPOUT_DAT Register Field Descriptions ................................................................ 3215
31-46. ESCSS_GPOUT_PIPE Register Field Descriptions ................................................................ 3216
31-47. ESCSS_GPOUT_GRP_CAP_SEL Register Field Descriptions .................................................. 3217
31-48. ESCSS_MEM_TEST Register Field Descriptions .................................................................. 3218
31-49. ESCSS_RESET_DEST_CONFIG Register Field Descriptions ................................................... 3219
31-50. ESCSS_SYNC0_CONFIG Register Field Descriptions ............................................................ 3220
31-51. ESCSS_SYNC1_CONFIG Register Field Descriptions ............................................................ 3221
32-1. FSI Transmitter Core Signals .......................................................................................... 3225
32-2. FSI Receiver Core Signals ............................................................................................. 3226
32-3. External Trigger Sources and Their Index ........................................................................... 3229
32-4. Basic Frame Structure .................................................................................................. 3243
32-5. Frame Types and Their 4-bit Codes .................................................................................. 3244
32-6. Ping Frame ............................................................................................................... 3245
32-7. Error Frame .............................................................................................................. 3245
32-8. Data Frame .............................................................................................................. 3245
32-9. Multi-Lane Frame Format .............................................................................................. 3246
32-10. FSI TDM Inputs .......................................................................................................... 3251
32-11. FSI-SPI Compatibility Frame Structure ............................................................................... 3253
32-12. Contents of Data Received by a Standard SPI ..................................................................... 3253
32-13. FSI as Master Transmitter, SPI as Slave Receiver ................................................................. 3254
32-14. SPI as Master Transmitter, FSI as Slave Receiver ................................................................. 3254
32-15. FSI Base Address Table (C28) ........................................................................................ 3259
32-16. FSI_RX_REGS Registers .............................................................................................. 3260
32-17. FSI_RX_REGS Access Type Codes ................................................................................. 3261
32-18. RX_MASTER_CTRL Register Field Descriptions................................................................... 3262
32-19. RX_OPER_CTRL Register Field Descriptions ...................................................................... 3263
32-20. RX_FRAME_INFO Register Field Descriptions ..................................................................... 3264
32-21. RX_FRAME_TAG_UDATA Register Field Descriptions ........................................................... 3265
32-22. RX_DMA_CTRL Register Field Descriptions ........................................................................ 3266
32-23. RX_EVT_STS Register Field Descriptions .......................................................................... 3267
32-24. RX_CRC_INFO Register Field Descriptions......................................................................... 3270
32-25. RX_EVT_CLR Register Field Descriptions .......................................................................... 3271
32-26. RX_EVT_FRC Register Field Descriptions .......................................................................... 3273
32-27. RX_BUF_PTR_LOAD Register Field Descriptions ................................................................. 3275
32-28. RX_BUF_PTR_STS Register Field Descriptions ................................................................... 3276
32-29. RX_FRAME_WD_CTRL Register Field Descriptions .............................................................. 3277

126 List of Tables SPRUII0B – May 2019 – Revised May 2020

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32-30. RX_FRAME_WD_REF Register Field Descriptions ................................................................ 3278

32-31. RX_FRAME_WD_CNT Register Field Descriptions ................................................................ 3279
32-32. RX_PING_WD_CTRL Register Field Descriptions ................................................................. 3280
32-33. RX_PING_TAG Register Field Descriptions ......................................................................... 3281
32-34. RX_PING_WD_REF Register Field Descriptions ................................................................... 3282
32-35. RX_PING_WD_CNT Register Field Descriptions ................................................................... 3283
32-36. RX_INT1_CTRL Register Field Descriptions ........................................................................ 3284
32-37. RX_INT2_CTRL Register Field Descriptions ........................................................................ 3287
32-38. RX_LOCK_CTRL Register Field Descriptions ...................................................................... 3290
32-39. RX_ECC_DATA Register Field Descriptions ........................................................................ 3291
32-40. RX_ECC_VAL Register Field Descriptions .......................................................................... 3292
32-41. RX_ECC_SEC_DATA Register Field Descriptions ................................................................. 3293
32-42. RX_ECC_LOG Register Field Descriptions ......................................................................... 3294
32-43. RX_FRAME_TAG_CMP Register Field Descriptions .............................................................. 3295
32-44. RX_PING_TAG_CMP Register Field Descriptions ................................................................. 3296
32-45. RX_DLYLINE_CTRL Register Field Descriptions................................................................... 3297
32-46. RX_VIS_1 Register Field Descriptions ............................................................................... 3298
32-47. RX_BUF_BASE_y Register Field Descriptions ..................................................................... 3299
32-48. FSI_TX_REGS Registers .............................................................................................. 3300
32-49. FSI_TX_REGS Access Type Codes.................................................................................. 3300
32-50. TX_MASTER_CTRL Register Field Descriptions ................................................................... 3302
32-51. TX_CLK_CTRL Register Field Descriptions ......................................................................... 3303
32-52. TX_OPER_CTRL_LO Register Field Descriptions ................................................................. 3304
32-53. TX_OPER_CTRL_HI Register Field Descriptions .................................................................. 3306
32-54. TX_FRAME_CTRL Register Field Descriptions ..................................................................... 3307
32-55. TX_FRAME_TAG_UDATA Register Field Descriptions............................................................ 3308
32-56. TX_BUF_PTR_LOAD Register Field Descriptions.................................................................. 3309
32-57. TX_BUF_PTR_STS Register Field Descriptions .................................................................... 3310
32-58. TX_PING_CTRL Register Field Descriptions........................................................................ 3311
32-59. TX_PING_TAG Register Field Descriptions ......................................................................... 3312
32-60. TX_PING_TO_REF Register Field Descriptions .................................................................... 3313
32-61. TX_PING_TO_CNT Register Field Descriptions .................................................................... 3314
32-62. TX_INT_CTRL Register Field Descriptions .......................................................................... 3315
32-63. TX_DMA_CTRL Register Field Descriptions ........................................................................ 3317
32-64. TX_LOCK_CTRL Register Field Descriptions ....................................................................... 3318
32-65. TX_EVT_STS Register Field Descriptions ........................................................................... 3319
32-66. TX_EVT_CLR Register Field Descriptions........................................................................... 3320
32-67. TX_EVT_FRC Register Field Descriptions .......................................................................... 3321
32-68. TX_USER_CRC Register Field Descriptions ........................................................................ 3322
32-69. TX_ECC_DATA Register Field Descriptions ........................................................................ 3323
32-70. TX_ECC_VAL Register Field Descriptions .......................................................................... 3324
32-71. TX_BUF_BASE_y Register Field Descriptions ...................................................................... 3325
32-72. FSI Registers to Driverlib Functions .................................................................................. 3326
33-1. Dependency of Delay d on the Divide-Down Value IPSC ......................................................... 3334
33-2. Operating Modes of the I2C Module .................................................................................. 3336
33-3. Master-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits of I2CMDR .............. 3336
33-4. How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of I2CMDR ........................... 3339
33-5. Ways to Generate a NACK Bit ........................................................................................ 3340
33-6. Descriptions of the Basic I2C Interrupt Requests ................................................................... 3344

SPRUII0B – May 2019 – Revised May 2020 List of Tables 127

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33-7. I2C Base Address Table (C28) ........................................................................................ 3348

33-8. I2C_REGS Registers ................................................................................................... 3349
33-9. I2C_REGS Access Type Codes....................................................................................... 3349
33-10. I2COAR Register Field Descriptions.................................................................................. 3350
33-11. I2CIER Register Field Descriptions ................................................................................... 3351
33-12. I2CSTR Register Field Descriptions .................................................................................. 3352
33-13. I2CCLKL Register Field Descriptions ................................................................................. 3356
33-14. I2CCLKH Register Field Descriptions ................................................................................ 3357
33-15. I2CCNT Register Field Descriptions .................................................................................. 3358
33-16. I2CDRR Register Field Descriptions.................................................................................. 3359
33-17. I2CSAR Register Field Descriptions .................................................................................. 3360
33-18. I2CDXR Register Field Descriptions .................................................................................. 3361
33-19. I2CMDR Register Field Descriptions ................................................................................. 3362
33-20. I2CISRC Register Field Descriptions ................................................................................. 3366
33-21. I2CEMDR Register Field Descriptions ............................................................................... 3367
33-22. I2CPSC Register Field Descriptions .................................................................................. 3368
33-23. I2CFFTX Register Field Descriptions ................................................................................. 3369
33-24. I2CFFRX Register Field Descriptions ................................................................................ 3371
33-25. I2C Registers to Driverlib Functions .................................................................................. 3372
34-1. McBSP Interface Pins/Signals ......................................................................................... 3376
34-2. Register Bits That Determine the Number of Phases, Words, and Bits ......................................... 3383
34-3. Interrupts and DMA Events Generated by a McBSP ............................................................... 3387
34-4. Effects of DLB and CLKSTP on Clock Modes....................................................................... 3389
34-5. Choosing an Input Clock for the Sample Rate Generator with the SCLKME and CLKSM Bits .............. 3389
34-6. Polarity Options for the Input to the Sample Rate Generator ..................................................... 3390
34-7. Input Clock Selection for Sample Rate Generator .................................................................. 3393
34-8. Block - Channel Assignment ........................................................................................... 3402
34-9. 2-Partition Mode ......................................................................................................... 3403
34-10. 8-Partition mode ......................................................................................................... 3403
34-11. Receive Channel Assignment and Control With Eight Receive Partitions ....................................... 3405
34-12. Transmit Channel Assignment and Control When Eight Transmit Partitions Are Used ....................... 3406
34-13. Selecting a Transmit Multichannel Selection Mode With the XMCM Bits........................................ 3407
34-14. Bits Used to Enable and Configure the Clock Stop Mode ......................................................... 3410
34-15. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme ................................................. 3411
34-16. Bit Values Required to Configure the McBSP as an SPI Master ................................................ 3414
34-17. Bit Values Required to Configure the McBSP as an SPI Slave ................................................... 3415
34-18. Register Bits Used to Reset or Enable the McBSP Receiver Field Descriptions ............................... 3417
34-19. Reset State of Each McBSP Pin ...................................................................................... 3417
34-20. Register Bit Used to Enable/Disable the Digital Loopback Mode ................................................. 3418
34-21. Receive Signals Connected to Transmit Signals in Digital Loopback Mode .................................... 3418
34-22. Register Bits Used to Enable/Disable the Clock Stop Mode ...................................................... 3418
34-23. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme ................................................. 3419
34-24. Register Bit Used to Enable/Disable the Receive Multichannel Selection Mode ............................... 3419
34-25. Register Bit Used to Choose One or Two Phases for the Receive Frame ...................................... 3419
34-26. Register Bits Used to Set the Receive Word Length(s) ............................................................ 3420
34-27. Register Bits Used to Set the Receive Frame Length .............................................................. 3420
34-28. How to Calculate the Length of the Receive Frame ................................................................ 3421
34-29. Register Bit Used to Enable/Disable the Receive Frame-Synchronization Ignore Function .................. 3421
34-30. Register Bits Used to Set the Receive Companding Mode ........................................................ 3422

128 List of Tables SPRUII0B – May 2019 – Revised May 2020

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34-31. Register Bits Used to Set the Receive Data Delay ................................................................. 3423
34-32. Register Bits Used to Set the Receive Sign-Extension and Justification Mode................................. 3425
34-33. Example: Use of RJUST Field With 12-Bit Data Value ABCh..................................................... 3425
34-34. Example: Use of RJUST Field With 20-Bit Data Value ABCDEh ................................................. 3425
34-35. Register Bits Used to Set the Receive Interrupt Mode ............................................................. 3426
34-36. Register Bits Used to Set the Receive Frame Synchronization Mode .......................................... 3426
34-37. Select Sources to Provide the Receive Frame-Synchronization Signal and the Effect on the FSR Pin..... 3427
34-38. Register Bit Used to Set Receive Frame-Synchronization Polarity ............................................... 3428
34-39. Register Bits Used to Set the SRG Frame-Synchronization Period and Pulse Width ......................... 3429
34-40. Register Bits Used to Set the Receive Clock Mode ............................................................... 3430
34-41. Receive Clock Signal Source Selection .............................................................................. 3431
34-42. Register Bit Used to Set Receive Clock Polarity .................................................................... 3431
34-43. Register Bits Used to Set the Sample Rate Generator (SRG) Clock Divide-Down Value ..................... 3433
34-44. Register Bit Used to Set the SRG Clock Synchronization Mode ................................................. 3433
34-45. Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock) ...................................... 3434
34-46. Register Bits Used to Set the SRG Input Clock Polarity ........................................................... 3435
34-47. Register Bits Used to Place Transmitter in Reset Field Descriptions ............................................ 3436
34-48. Register Bit Used to Enable/Disable the Digital Loopback Mode ................................................. 3437
34-49. Receive Signals Connected to Transmit Signals in Digital Loopback Mode .................................... 3437
34-50. Register Bits Used to Enable/Disable the Clock Stop Mode ...................................................... 3437
34-51. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme ................................................. 3438
34-52. Register Bits Used to Enable/Disable Transmit Multichannel Selection ......................................... 3439
34-53. Use of the Transmit Channel Enable Registers .................................................................... 3439
34-54. Register Bit Used to Choose 1 or 2 Phases for the Transmit Frame ............................................ 3442
34-55. Register Bits Used to Set the Transmit Word Length(s) ........................................................... 3442
34-56. Register Bits Used to Set the Transmit Frame Length ............................................................. 3443
34-57. How to Calculate Frame Length ....................................................................................... 3443
34-58. Register Bit Used to Enable/Disable the Transmit Frame-Synchronization Ignore Function ................. 3444
34-59. Register Bits Used to Set the Transmit Companding Mode ....................................................... 3445
34-60. Register Bits Used to Set the Transmit Data Delay ................................................................ 3446
34-61. Register Bit Used to Set the Transmit DXENA (DX Delay Enabler) Mode ...................................... 3448
34-62. Register Bits Used to Set the Transmit Interrupt Mode ............................................................ 3448
34-63. Register Bits Used to Set the Transmit Frame-Synchronization Mode .......................................... 3449
34-64. How FSXM and FSGM Select the Source of Transmit Frame-Synchronization Pulses ....................... 3449
34-65. Register Bit Used to Set Transmit Frame-Synchronization Polarity .............................................. 3450
34-66. Register Bits Used to Set SRG Frame-Synchronization Period and Pulse Width .............................. 3451
34-67. Register Bit Used to Set the Transmit Clock Mode ................................................................. 3452
34-68. How the CLKXM Bit Selects the Transmit Clock and the Corresponding Status of the MCLKX pin ......... 3452
34-69. Register Bit Used to Set Transmit Clock Polarity ................................................................... 3452
34-70. McBSP Emulation Modes Selectable with FREE and SOFT Bits of SPCR2.................................... 3454
34-71. Reset State of Each McBSP Pin ...................................................................................... 3454
34-72. Receive Interrupt Sources and Signals .............................................................................. 3459
34-73. Transmit Interrupt Sources and Signals .............................................................................. 3459
34-74. Error Flags ............................................................................................................... 3460
34-75. McBSP Mode Selection ................................................................................................ 3460
34-76. MCBSP Base Address Table (C28) .................................................................................. 3463
34-77. McBSP Register Summary............................................................................................. 3463
34-78. Serial Port Control 1 Register (SPCR1) Field Descriptions ....................................................... 3466
34-79. Serial Port Control 2 Register (SPCR2) Field Descriptions........................................................ 3468

SPRUII0B – May 2019 – Revised May 2020 List of Tables 129

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34-80. Receive Control Register 1 (RCR1) Field Descriptions ............................................................ 3470

34-81. Frame Length Formula for Receive Control 1 Register (RCR1) .................................................. 3471
34-82. Receive Control Register 2 (RCR2) Field Descriptions ............................................................ 3471
34-83. Frame Length Formula for Receive Control 2 Register (RCR2) .................................................. 3472
34-84. Transmit Control 1 Register (XCR1) Field Descriptions ........................................................... 3473
34-85. Frame Length Formula for Transmit Control 1 Register (XCR1) ................................................. 3473
34-86. Transmit Control 2 Register (XCR2) Field Descriptions ........................................................... 3474
34-87. Frame Length Formula for Transmit Control 2 Register (XCR2) ................................................. 3475
34-88. Sample Rate Generator 1 Register (SRGR1) Field Descriptions ................................................. 3476
34-89. Sample Rate Generator 2 Register (SRGR2) Field Descriptions ................................................. 3477
34-90. Multichannel Control 1 Register (MCR1) Field Descriptions ...................................................... 3478
34-91. Multichannel Control 2 Register (MCR2) Field Descriptions ...................................................... 3480
34-92. Pin Control Register (PCR) Field Descriptions ...................................................................... 3482
34-93. Pin Configuration ....................................................................................................... 3484
34-94. Receive Channel Enable Registers (RCERA...RCERH) Field Descriptions..................................... 3484
34-95. Use of the Receive Channel Enable Registers ..................................................................... 3485
34-96. Transmit Channel Enable Registers (XCERA...XCERH) Field Descriptions .................................... 3486
34-97. Use of the Transmit Channel Enable Registers .................................................................... 3487
34-98. McBSP Interrupt Enable Register (MFFINT) Field Descriptions .................................................. 3488
34-99. MCBSP Registers to Driverlib Functions ............................................................................. 3489
35-1. PMBUS Base Address Table (C28) .................................................................................. 3512
35-2. PMBUS_REGS Registers .............................................................................................. 3513
35-3. PMBUS_REGS Access Type Codes ................................................................................. 3513
35-4. PMBMC Register Field Descriptions.................................................................................. 3514
35-5. PMBTXBUF Register Field Descriptions ............................................................................. 3515
35-6. PMBRXBUF Register Field Descriptions ............................................................................. 3516
35-7. PMBACK Register Field Descriptions ................................................................................ 3517
35-8. PMBSTS Register Field Descriptions................................................................................. 3518
35-9. PMBINTM Register Field Descriptions ............................................................................... 3520
35-10. PMBSC Register Field Descriptions .................................................................................. 3522
35-11. PMBHSA Register Field Descriptions ................................................................................ 3524
35-12. PMBCTRL Register Field Descriptions ............................................................................... 3525
35-13. PMBTIMCTL Register Field Descriptions ............................................................................ 3527
35-14. PMBTIMCLK Register Field Descriptions ............................................................................ 3528
35-15. PMBTIMSTSETUP Register Field Descriptions ..................................................................... 3529
35-16. PMBTIMBIDLE Register Field Descriptions ......................................................................... 3530
35-17. PMBTIMLOWTIMOUT Register Field Descriptions ................................................................. 3531
35-18. PMBTIMHIGHTIMOUT Register Field Descriptions ................................................................ 3532
36-1. SCI Module Signal Summary .......................................................................................... 3535
36-2. Programming the Data Format Using SCICCR ..................................................................... 3537
36-3. Asynchronous Baud Register Values for Common SCI Bit Rates ................................................ 3545
36-4. SCI Interrupt Flags ...................................................................................................... 3547
36-5. SCI Base Address Table (C28) ....................................................................................... 3548
36-6. SCI_REGS Registers ................................................................................................... 3549
36-7. SCI_REGS Access Type Codes ...................................................................................... 3549
36-8. SCICCR Register Field Descriptions ................................................................................. 3550
36-9. SCICTL1 Register Field Descriptions................................................................................. 3552
36-10. SCIHBAUD Register Field Descriptions .............................................................................. 3554
36-11. SCILBAUD Register Field Descriptions .............................................................................. 3555

130 List of Tables SPRUII0B – May 2019 – Revised May 2020

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36-12. SCICTL2 Register Field Descriptions................................................................................. 3556

36-13. SCIRXST Register Field Descriptions ................................................................................ 3558
36-14. SCIRXEMU Register Field Descriptions ............................................................................. 3560
36-15. SCIRXBUF Register Field Descriptions .............................................................................. 3561
36-16. SCITXBUF Register Field Descriptions .............................................................................. 3562
36-17. SCIFFTX Register Field Descriptions ................................................................................ 3563
36-18. SCIFFRX Register Field Descriptions ................................................................................ 3565
36-19. SCIFFCT Register Field Descriptions ................................................................................ 3567
36-20. SCIPRI Register Field Descriptions ................................................................................... 3568
36-21. SCI Registers to Driverlib Functions .................................................................................. 3569
37-1. SPI Module Signal Summary .......................................................................................... 3573
37-2. SPI Interrupt Flag Modes ............................................................................................... 3576
37-3. SPI Clocking Scheme Selection Guide ............................................................................... 3583
37-4. 4-wire vs. 3-wire SPI Pin Functions ................................................................................... 3586
37-5. 3-Wire SPI Pin Configuration .......................................................................................... 3587
37-6. SPI Base Address Table (C28) ........................................................................................ 3593
37-7. SPI_REGS Registers ................................................................................................... 3594
37-8. SPI_REGS Access Type Codes ...................................................................................... 3594
37-9. SPICCR Register Field Descriptions ................................................................................. 3595
37-10. SPICTL Register Field Descriptions .................................................................................. 3597
37-11. SPISTS Register Field Descriptions .................................................................................. 3599
37-12. SPIBRR Register Field Descriptions.................................................................................. 3601
37-13. SPIRXEMU Register Field Descriptions.............................................................................. 3602
37-14. SPIRXBUF Register Field Descriptions .............................................................................. 3603
37-15. SPITXBUF Register Field Descriptions .............................................................................. 3604
37-16. SPIDAT Register Field Descriptions .................................................................................. 3605
37-17. SPIFFTX Register Field Descriptions................................................................................. 3606
37-18. SPIFFRX Register Field Descriptions ................................................................................ 3608
37-19. SPIFFCT Register Field Descriptions ................................................................................ 3610
37-20. SPIPRI Register Field Descriptions ................................................................................... 3611
37-21. SPI Registers to Driverlib Functions .................................................................................. 3613
38-1. USB Memory Access From Software ................................................................................. 3626
38-2. USB Memory Access From CCS...................................................................................... 3627
38-3. USB Base Address Table (C28) ...................................................................................... 3629
38-4. USB Base Address Table (CM) ....................................................................................... 3629
38-5. Universal Serial Bus (USB) Controller Register Map .............................................................. 3630
38-6. Function Address Register (USBFADDR) Field Descriptions ..................................................... 3640
38-7. Power Management Register (USBPOWER) in Host Mode Field Descriptions ................................ 3641
38-8. Power Management Register (USBPOWER) in Device Mode Field Descriptions.............................. 3641
38-9. USB Transmit Interrupt Status Register (USBTXIS) Field Descriptions ......................................... 3643
38-10. USB Transmit Interrupt Status Register (USBRXIS) Field Descriptions ......................................... 3645
38-11. USB Transmit Interrupt Status Register (USBTXIE) Field Descriptions ......................................... 3647
38-12. USB Transmit Interrupt Status Register (USBRXIE) Field Descriptions ......................................... 3649
38-13. USB General Interrupt Status Register (USBIS) in Host Mode Field Descriptions ............................. 3651
38-14. USB General Interrupt Status Register (USBIS) in Device Mode Field Descriptions .......................... 3652
38-15. USB Interrupt Enable Register (USBIE) in Host Mode Field Descriptions ...................................... 3653
38-16. USB Interrupt Enable Register (USBIE) in Device Mode Field Descriptions .................................... 3654
38-17. Frame Number Register (FRAME) Field Descriptions ............................................................. 3655
38-18. USB Endpoint Index Register (USBEPIDX) Field Descriptions ................................................... 3655

SPRUII0B – May 2019 – Revised May 2020 List of Tables 131

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38-19. USB Test Mode Register (USBTEST) in Host Mode Field Descriptions......................................... 3656
38-20. USB Test Mode Register (USBTEST) in Device Mode Field Descriptions ...................................... 3656
38-21. USB FIFO Endpoint n Register (USBFIFO[n]) Field Descriptions ................................................ 3658
38-22. USB Device Control Register (USBDEVCTL) Field Descriptions ................................................. 3659
38-23. USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ) Field Descriptions ........................... 3661
38-24. USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ) Field Descriptions ............................ 3662
38-25. USB Transmit FIFO Start Address Register (USBTXFIFOADDR) Field Descriptions ......................... 3663
38-26. USB Receive FIFO Start Address Register (USBRXFIFOADDR) Field Descriptions .......................... 3664
38-27. USB Connect Timing Register (USBCONTIM) Field Descriptions................................................ 3665
38-28. USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF) Field Descriptions ..... 3666
38-29. USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF) Field Descriptions..... 3666
38-30. USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[n]) Field Descriptions ...... 3667
38-31. USB Transmit Hub Address Endpoint n Registers(USBTXHUBADDR[n]) Field Descriptions ................ 3668
38-32. USB Transmit Hub Port Endpoint n Registers(USBTXHUBPORT[n]) Field Descriptions ..................... 3669
38-33. USB Recieve Functional Address Endpoint n Registers(USBFIFO[n]) Field Descriptions .................... 3670
38-34. USB Receive Hub Address Endpoint n Registers(USBRXHUBADDR[n]) Field Descriptions ................ 3671
38-35. USB Transmit Hub Port Endpoint n Registers(USBRXHUBPORT[n]) Field Descriptions ..................... 3672
38-36. USB Maximum Transmit Data Endpoint n Registers(USBTXMAXP[n]) Field Descriptions ................... 3673
38-37. USB Control and Status Endpoint 0 Low Register(USBCSRL0) in Host Mode Field Descriptions .......... 3674
38-38. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Device Mode Field Descriptions ....... 3675
38-39. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Host Mode Field Descriptions......... 3676
38-40. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Device Mode Field Descriptions ...... 3676
38-41. USB Receive Byte Count Endpoint 0 Register (USBCOUNT0) Field Descriptions ............................ 3677
38-42. USB Type Endpoint 0 Register (USBTYPE0) Field Descriptions ................................................. 3677
38-43. USB NAK Limit Register (USBNAKLMT) Field Descriptions ...................................................... 3678
38-44. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Host Mode Field
Descriptions .............................................................................................................. 3679
38-45. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Device Mode Field
Descriptions .............................................................................................................. 3680
38-46. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Host Mode Field
Descriptions .............................................................................................................. 3682
38-47. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Device Mode Field
Descriptions .............................................................................................................. 3683
38-48. USB Maximum Receive Data Endpoint n Registers (USBTXMAXP[n]) Field Descriptions ................... 3684
38-49. USB Control and Status Endpoint n Low Register(USBCSRL[n]) in Host Mode Field Descriptions ......... 3685
38-50. USB Control and Status Endpoint 0 Low Register(USBCSRL[n]) in Device Mode Field Descriptions ...... 3686
38-51. USB Control and Status Endpoint n High Register (USBCSRH[n]) in Host Mode Field Descriptions ....... 3687
38-52. USB Control and Status Endpoint 0 High Register(USBCSRH[n]) in Device Mode Field Descriptions ..... 3688
38-53. USB Maximum Receive Data Endpoint n Registers (USBRXCOUNT[n]) Field Descriptions ................. 3689
38-54. USB Host Transmit Configure Type Endpoint n Register(USBTXTYPE[n]) Field Descriptions .............. 3690
38-55. USBTXINTERVAL[n] Frame Numbers ............................................................................... 3691
38-56. USB Host Transmit Interval Endpoint n Register(USBTXINTERVAL[n]) Field Descriptions .................. 3691
38-57. USB Host Configure Receive Type Endpoint n Register(USBRXTYPE[n]) Field Descriptions ............... 3692
38-58. USBRXINTERVAL[n] Frame Numbers ............................................................................... 3693
38-59. USB Host Receive Polling Interval Endpoint n Register(USBRXINTERVAL[n]) Field Descriptions.......... 3693
38-60. USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[n]) Field
Descriptions .............................................................................................................. 3694
38-61. USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS) Field Descriptions .......... 3695
38-62. USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS) Field Descriptions .......... 3697
38-63. USB External Power Control Register (USBEPC) Field Descriptions ............................................ 3698

132 List of Tables SPRUII0B – May 2019 – Revised May 2020

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38-64. USB External Power Control Raw Interrupt Status Register (USBEPCRIS) Field Descriptions .............. 3700
38-65. USB External Power Control Interrupt Mask Register (USBEPCIM) Field Descriptions....................... 3701
38-66. USB External Power Control Interrupt Status and Clear Register (USBEPCISC) Field Descriptions ....... 3702
38-67. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) Field Descriptions....................... 3703
38-68. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) Field Descriptions....................... 3704
38-69. USB Device RESUME Interrupt Status and Clear Register (USBDRISC) Field Descriptions ................ 3705
38-70. USB General-Purpose Control and Status Register (USBGPCS) Field Descriptions .......................... 3706
38-71. USB DMA Select Register (USBDMASEL) Field Descriptions .................................................... 3707
38-72. USB Global Interrupt Enable (USBGLBINTEN) Field Descriptions ............................................... 3709
38-73. USB Global Interrupt Flag (USBGLBINTFLG) Field Descriptions ................................................ 3710
38-74. USB Global Interrupt Flag (USBGLBINTFLGCLR) Field Descriptions ........................................... 3711
38-75. USBDMARIS Register Field Descriptions............................................................................ 3712
38-76. USBDMAIM Register Field Descriptions ............................................................................. 3713
38-77. USBDMAISC Register Field Descriptions............................................................................ 3714
40-1. Connectivity Manager Architectural Features ....................................................................... 3718
41-1. CM Clock Connections ................................................................................................. 3725
41-2. CM Subsystem Exceptions ............................................................................................ 3727
41-3. Interrupts and NMI From CM to CPU1 ............................................................................... 3731
41-4. Interrupts and NMI From CM to CPU2 ............................................................................... 3731
41-5. NVIC Interrupt Mapping ................................................................................................ 3732
41-6. CM Message RAM Accesses .......................................................................................... 3739
41-7. Error Handling of Memories ............................................................................................ 3741
41-8. Mapping of ECC Bits in Read Data From ECC/Parity Address Map ............................................. 3742
41-9. Mapping of Parity Bits in Read Data From ECC/Parity Address Map ............................................ 3742
41-10. Key Attributes of Trace Data Export .................................................................................. 3746
41-11. CM SYSCTRL Base Address Table (CM) ........................................................................... 3747
41-12. CM_MEMCFG_REGS Registers ...................................................................................... 3748
41-13. CM_MEMCFG_REGS Access Type Codes ......................................................................... 3748
41-14. CxLOCK Register Field Descriptions ................................................................................. 3749
41-15. CxTEST Register Field Descriptions ................................................................................. 3750
41-16. CxINIT Register Field Descriptions ................................................................................... 3751
41-17. CxINITDONE Register Field Descriptions ........................................................................... 3752
41-18. CMMSGxLOCK Register Field Descriptions......................................................................... 3753
41-19. CMMSGxTEST Register Field Descriptions ......................................................................... 3754
41-20. CMMSGxINIT Register Field Descriptions ........................................................................... 3756
41-21. CMMSGxINITDONE Register Field Descriptions ................................................................... 3757
41-22. SxGROUP1_LOCK Register Field Descriptions .................................................................... 3758
41-23. SxGROUP1_TEST Register Field Descriptions ..................................................................... 3759
41-24. SxGROUP1_INIT Register Field Descriptions ...................................................................... 3761
41-25. SxGROUP1_INITDONE Register Field Descriptions ............................................................... 3762
41-26. ROM_LOCK Register Field Descriptions ............................................................................ 3763
41-27. ROM_TEST Register Field Descriptions ............................................................................. 3764
41-28. ROM_FORCE_ERROR Register Field Descriptions ............................................................... 3765
41-29. PERI_MEM_TEST_LOCK Register Field Descriptions ............................................................ 3766
41-30. PERI_MEM_TEST_CONTROL Register Field Descriptions ...................................................... 3767
41-31. CM_MEMORYDIAGERROR_REGS Registers ..................................................................... 3768
41-32. CM_MEMORYDIAGERROR_REGS Access Type Codes......................................................... 3768
41-33. DIAGERRFLG Register Field Descriptions .......................................................................... 3769
41-34. DIAGERRCLR Register Field Descriptions .......................................................................... 3770

SPRUII0B – May 2019 – Revised May 2020 List of Tables 133

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41-35. DIAGERRADDR Register Field Descriptions ........................................................................ 3771

41-36. CM_MEMORYERROR_REGS Registers ............................................................................ 3772
41-37. CM_MEMORYERROR_REGS Access Type Codes ............................................................... 3772
41-38. UCERRFLG Register Field Descriptions ............................................................................. 3774
41-39. UCERRSET Register Field Descriptions ............................................................................. 3776
41-40. UCERRCLR Register Field Descriptions ............................................................................. 3777
41-41. UCM4EADDR Register Field Descriptions........................................................................... 3778
41-42. UCEMACEADDR Register Field Descriptions ...................................................................... 3779
41-43. UCuDMAEADDR Register Field Descriptions ....................................................................... 3780
41-44. UCEtherCATMEMREADDR Register Field Descriptions .......................................................... 3781
41-45. UCEMACMEMREADDR Register Field Descriptions .............................................................. 3782
41-46. BUSFAULTFLG Register Field Descriptions ........................................................................ 3783
41-47. BUSFAULTCLR Register Field Descriptions ........................................................................ 3784
41-48. M4BUSFAULTADDR Register Field Descriptions .................................................................. 3785
41-49. uDMABUSFAULTADDR Register Field Descriptions .............................................................. 3786
41-50. EMACBUSFAULTADDR Register Field Descriptions .............................................................. 3787
41-51. CERRFLG Register Field Descriptions ............................................................................... 3788
41-52. CERRSET Register Field Descriptions ............................................................................... 3789
41-53. CERRCLR Register Field Descriptions............................................................................... 3790
41-54. CM4EADDR Register Field Descriptions ............................................................................ 3791
41-55. CEMACEADDR Register Field Descriptions ........................................................................ 3792
41-56. CuDMAEADDR Register Field Descriptions ......................................................................... 3793
41-57. CERRCNT Register Field Descriptions .............................................................................. 3794
41-58. CERRTHRES Register Field Descriptions ........................................................................... 3795
41-59. CEINTFLG Register Field Descriptions .............................................................................. 3796
41-60. CEINTSET Register Field Descriptions .............................................................................. 3797
41-61. CEINTCLR Register Field Descriptions .............................................................................. 3798
41-62. CEINTEN Register Field Descriptions ................................................................................ 3799
41-63. CMSYSCTL_REGS Registers ......................................................................................... 3800
41-64. CMSYSCTL_REGS Access Type Codes ............................................................................ 3800
41-65. CMPCLKCR0 Register Field Descriptions ........................................................................... 3802
41-66. CMPCLKCR1 Register Field Descriptions ........................................................................... 3803
41-67. CMPCLKCR2 Register Field Descriptions ........................................................................... 3805
41-68. CMSOFTPRESET0 Register Field Descriptions .................................................................... 3807
41-69. CMSOFTPRESET1 Register Field Descriptions .................................................................... 3808
41-70. CMSOFTPRESET2 Register Field Descriptions .................................................................... 3810
41-71. CMCLKSTOPREQ0 Register Field Descriptions ................................................................... 3811
41-72. CMCLKSTOPREQ1 Register Field Descriptions ................................................................... 3812
41-73. CMCLKSTOPREQ2 Register Field Descriptions ................................................................... 3813
41-74. CMCLKSTOPACK0 Register Field Descriptions .................................................................... 3814
41-75. CMCLKSTOPACK1 Register Field Descriptions .................................................................... 3815
41-76. CMCLKSTOPACK2 Register Field Descriptions .................................................................... 3816
41-77. MCANWAKESTATUS Register Field Descriptions ................................................................. 3817
41-78. MCANWAKESTATUSCLR Register Field Descriptions ............................................................ 3818
41-79. PALLOCATESTS Register Field Descriptions ...................................................................... 3819
41-80. CMRESCCLR Register Field Descriptions........................................................................... 3820
41-81. CMRESC Register Field Descriptions ................................................................................ 3822
41-82. CMSYSCTLLOCK Register Field Descriptions...................................................................... 3824
41-83. CM_CPUTIMER_REGS Registers .................................................................................... 3825

134 List of Tables SPRUII0B – May 2019 – Revised May 2020

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41-84. CM_CPUTIMER_REGS Access Type Codes ....................................................................... 3825

41-85. TIM Register Field Descriptions ....................................................................................... 3826
41-86. PRD Register Field Descriptions ...................................................................................... 3827
41-87. TCR Register Field Descriptions ...................................................................................... 3828
41-88. TPR Register Field Descriptions ...................................................................................... 3830
41-89. MPU_REGS Registers ................................................................................................. 3831
41-90. MPU_REGS Access Type Codes ..................................................................................... 3831
41-91. MPU_CONTROL_REG Register Field Descriptions................................................................ 3833
41-92. ACC_VIO_INTEN Register Field Descriptions ...................................................................... 3834
41-93. ACC_VIO_FLAGS Register Field Descriptions ..................................................................... 3835
41-94. ACC_VIO_FLAGS_SET Register Field Descriptions ............................................................... 3836
41-95. ACC_VIO_FLAGS_CLR Register Field Descriptions............................................................... 3837
41-96. ACC_VIO_ADDR_REG Register Field Descriptions ............................................................... 3838
41-97. REGION0_STARTADDRESSS Register Field Descriptions ...................................................... 3839
41-98. REGION0_CONFIG Register Field Descriptions ................................................................... 3840
41-99. REGION1_STARTADDRESSS Register Field Descriptions ...................................................... 3842
41-100. REGION1_CONFIG Register Field Descriptions .................................................................. 3843
41-101. REGION2_STARTADDRESSS Register Field Descriptions ..................................................... 3845
41-102. REGION2_CONFIG Register Field Descriptions .................................................................. 3846
41-103. REGION3_STARTADDRESSS Register Field Descriptions ..................................................... 3848
41-104. REGION3_CONFIG Register Field Descriptions .................................................................. 3849
41-105. REGION4_STARTADDRESSS Register Field Descriptions ..................................................... 3851
41-106. REGION4_CONFIG Register Field Descriptions .................................................................. 3852
41-107. REGION5_STARTADDRESSS Register Field Descriptions ..................................................... 3854
41-108. REGION5_CONFIG Register Field Descriptions .................................................................. 3855
41-109. REGION6_STARTADDRESSS Register Field Descriptions ..................................................... 3857
41-110. REGION6_CONFIG Register Field Descriptions .................................................................. 3858
41-111. REGION7_STARTADDRESSS Register Field Descriptions ..................................................... 3860
41-112. REGION7_CONFIG Register Field Descriptions .................................................................. 3861
41-113. CM_NMI_INTRUPT_REGS Registers .............................................................................. 3863
41-114. CM_NMI_INTRUPT_REGS Access Type Codes ................................................................. 3863
41-115. CMNMICFG Register Field Descriptions ........................................................................... 3864
41-116. CMNMIFLG Register Field Descriptions ............................................................................ 3865
41-117. CMNMIFLGCLR Register Field Descriptions ...................................................................... 3867
41-118. CMNMIFLGFRC Register Field Descriptions ...................................................................... 3869
41-119. CMNMIWDCNT Register Field Descriptions ....................................................................... 3871
41-120. CMNMIWDPRD Register Field Descriptions ....................................................................... 3872
41-121. CMNMISHDWFLG Register Field Descriptions .................................................................... 3873
41-122. NVIC Registers ......................................................................................................... 3875
41-123. NVIC Access Type Codes ............................................................................................ 3875
41-124. NVIC_ISER0 Register Field Descriptions .......................................................................... 3877
41-125. NVIC_ISER1 Register Field Descriptions .......................................................................... 3882
41-126. NVIC_ICER0 Register Field Descriptions .......................................................................... 3887
41-127. NVIC_ICER1 Register Field Descriptions .......................................................................... 3892
41-128. NVIC_ISPR0 Register Field Descriptions .......................................................................... 3897
41-129. NVIC_ISPR1 Register Field Descriptions .......................................................................... 3902
41-130. NVIC_ISPR2 Register Field Descriptions .......................................................................... 3907
41-131. NVIC_ICPR0 Register Field Descriptions .......................................................................... 3912
41-132. NVIC_ICPR1 Register Field Descriptions .......................................................................... 3917

SPRUII0B – May 2019 – Revised May 2020 List of Tables 135

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41-133. NVIC_IABR0 Register Field Descriptions .......................................................................... 3922

41-134. NVIC_IABR1 Register Field Descriptions .......................................................................... 3925
41-135. NVIC_IPR0 Register Field Descriptions ............................................................................ 3928
41-136. NVIC_IPR1 Register Field Descriptions ............................................................................ 3929
41-137. NVIC_IPR2 Register Field Descriptions ............................................................................ 3930
41-138. NVIC_IPR3 Register Field Descriptions ............................................................................ 3931
41-139. NVIC_IPR4 Register Field Descriptions ............................................................................ 3932
41-140. NVIC_IPR5 Register Field Descriptions ............................................................................ 3933
41-141. NVIC_IPR6 Register Field Descriptions ............................................................................ 3934
41-142. NVIC_IPR7 Register Field Descriptions ............................................................................ 3935
41-143. NVIC_IPR8 Register Field Descriptions ............................................................................ 3936
41-144. NVIC_IPR9 Register Field Descriptions ............................................................................ 3937
41-145. NVIC_IPR10 Register Field Descriptions ........................................................................... 3938
41-146. NVIC_IPR11 Register Field Descriptions ........................................................................... 3939
41-147. NVIC_IPR12 Register Field Descriptions ........................................................................... 3940
41-148. NVIC_IPR13 Register Field Descriptions ........................................................................... 3941
41-149. NVIC_IPR14 Register Field Descriptions ........................................................................... 3942
41-150. NVIC_IPR15 Register Field Descriptions ........................................................................... 3943
41-151. STIR Register Field Descriptions .................................................................................... 3944
41-152. SCB Registers .......................................................................................................... 3945
41-153. SCB Access Type Codes ............................................................................................. 3945
41-154. ACTLR Register Field Descriptions ................................................................................. 3946
41-155. CPUID Register Field Descriptions .................................................................................. 3947
41-156. ICSR Register Field Descriptions .................................................................................... 3948
41-157. VTOR Register Field Descriptions ................................................................................... 3950
41-158. AIRCR Register Field Descriptions .................................................................................. 3951
41-159. SCR Register Field Descriptions..................................................................................... 3953
41-160. CCR Register Field Descriptions .................................................................................... 3954
41-161. SHPR1 Register Field Descriptions ................................................................................. 3956
41-162. SHPR2 Register Field Descriptions ................................................................................. 3957
41-163. SHPR3 Register Field Descriptions ................................................................................. 3958
41-164. SHCSRS Register Field Descriptions ............................................................................... 3959
41-165. CFSR Register Field Descriptions ................................................................................... 3963
41-166. HFSR Register Field Descriptions ................................................................................... 3967
41-167. MMFAR Register Field Descriptions ................................................................................ 3968
41-168. BFAR Register Field Descriptions ................................................................................... 3969
41-169. AFSR Register Field Descriptions ................................................................................... 3970
41-170. CSFR Registers ........................................................................................................ 3971
41-171. CSFR Access Type Codes ........................................................................................... 3971
41-172. MMSR Register Field Descriptions .................................................................................. 3972
41-173. BFSR Register Field Descriptions ................................................................................... 3974
41-174. UFSR Register Field Descriptions ................................................................................... 3976
41-175. SYSTICK Registers .................................................................................................... 3978
41-176. SYSTICK Access Type Codes ....................................................................................... 3978
41-177. SYST_CSR Register Field Descriptions ............................................................................ 3979
41-178. SYST_RVR Register Field Descriptions ............................................................................ 3980
41-179. SYST_CVR Register Field Descriptions ............................................................................ 3981
41-180. SYST_CALIB Register Field Descriptions .......................................................................... 3982
41-181. MPU Registers ......................................................................................................... 3983

136 List of Tables SPRUII0B – May 2019 – Revised May 2020

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41-182. MPU Access Type Codes ............................................................................................ 3983

41-183. MPU_TYPE Register Field Descriptions ............................................................................ 3984
41-184. MPU_CTRL Register Field Descriptions ............................................................................ 3985
41-185. MPU_RNR Register Field Descriptions ............................................................................. 3986
41-186. MPU_RBAR Register Field Descriptions ........................................................................... 3987
41-187. MPU_RASR Register Field Descriptions ........................................................................... 3988
41-188. MPU_RBAR_A1 Register Field Descriptions ...................................................................... 3992
41-189. MPU_RASR_A1 Register Field Descriptions ...................................................................... 3993
41-190. MPU_RBAR_A2 Register Field Descriptions ...................................................................... 3997
41-191. MPU_RASR_A2 Register Field Descriptions ...................................................................... 3998
41-192. MPU_RBAR_A3 Register Field Descriptions ...................................................................... 4002
41-193. MPU_RASR_A3 Register Field Descriptions ...................................................................... 4003
41-194. CM_WD_REGS Registers ............................................................................................ 4007
41-195. CM_WD_REGS Access Type Codes ............................................................................... 4007
41-196. SCSR Register Field Descriptions ................................................................................... 4008
41-197. WDCNTR Register Field Descriptions .............................................................................. 4009
41-198. WDKEY Register Field Descriptions ................................................................................ 4010
41-199. WDCR Register Field Descriptions .................................................................................. 4011
41-200. WDWCR Register Field Descriptions ............................................................................... 4013
42-1. AES Subsystem Interrupt Status ...................................................................................... 4017
42-2. Key-Block-Round Combinations ...................................................................................... 4019
42-3. Interrupts and Events ................................................................................................... 4030
42-4. AES Base Address Table (CM) ....................................................................................... 4036
42-5. AES_SS_REGS Registers ............................................................................................. 4037
42-6. AES_SS_REGS Access Type Codes ................................................................................ 4037
42-7. AESDMAINTEN Register Field Descriptions ........................................................................ 4038
42-8. AESDMASTATUS Register Field Descriptions...................................................................... 4039
42-9. AESDMASTATUSCLR Register Field Descriptions ................................................................ 4040
42-10. AES_REGS Registers .................................................................................................. 4041
42-11. AES_REGS Access Type Codes ..................................................................................... 4042
42-12. AES_KEY2_6 Register Field Descriptions ........................................................................... 4043
42-13. AES_KEY2_7 Register Field Descriptions ........................................................................... 4044
42-14. AES_KEY2_4 Register Field Descriptions ........................................................................... 4045
42-15. AES_KEY2_5 Register Field Descriptions ........................................................................... 4046
42-16. AES_KEY2_2 Register Field Descriptions ........................................................................... 4047
42-17. AES_KEY2_3 Register Field Descriptions ........................................................................... 4048
42-18. AES_KEY2_0 Register Field Descriptions ........................................................................... 4049
42-19. AES_KEY2_1 Register Field Descriptions ........................................................................... 4050
42-20. AES_KEY1_6 Register Field Descriptions ........................................................................... 4051
42-21. AES_KEY1_7 Register Field Descriptions ........................................................................... 4052
42-22. AES_KEY1_4 Register Field Descriptions ........................................................................... 4053
42-23. AES_KEY1_5 Register Field Descriptions ........................................................................... 4054
42-24. AES_KEY1_2 Register Field Descriptions ........................................................................... 4055
42-25. AES_KEY1_3 Register Field Descriptions ........................................................................... 4056
42-26. AES_KEY1_0 Register Field Descriptions ........................................................................... 4057
42-27. AES_KEY1_1 Register Field Descriptions ........................................................................... 4058
42-28. AES_IV_IN_OUT_0 Register Field Descriptions .................................................................... 4059
42-29. AES_IV_IN_OUT_1 Register Field Descriptions .................................................................... 4060
42-30. AES_IV_IN_OUT_2 Register Field Descriptions .................................................................... 4061

SPRUII0B – May 2019 – Revised May 2020 List of Tables 137

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42-31. AES_IV_IN_OUT_3 Register Field Descriptions .................................................................... 4062

42-32. AES_CTRL Register Field Descriptions .............................................................................. 4063
42-33. AES_C_LENGTH_0 Register Field Descriptions ................................................................... 4066
42-34. AES_C_LENGTH_1 Register Field Descriptions ................................................................... 4067
42-35. AES_AUTH_LENGTH Register Field Descriptions ................................................................. 4068
42-36. AES_DATA_IN_OUT_0 Register Field Descriptions ............................................................... 4069
42-37. AES_DATA_IN_OUT_1 Register Field Descriptions ............................................................... 4070
42-38. AES_DATA_IN_OUT_2 Register Field Descriptions ............................................................... 4071
42-39. AES_DATA_IN_OUT_3 Register Field Descriptions ............................................................... 4072
42-40. AES_TAG_OUT_0 Register Field Descriptions ..................................................................... 4073
42-41. AES_TAG_OUT_1 Register Field Descriptions ..................................................................... 4074
42-42. AES_TAG_OUT_2 Register Field Descriptions ..................................................................... 4075
42-43. AES_TAG_OUT_3 Register Field Descriptions ..................................................................... 4076
42-44. AES_REV Register Field Descriptions ............................................................................... 4077
42-45. AES_SYSCONFIG Register Field Descriptions ..................................................................... 4078
42-46. AES_SYSSTATUS Register Field Descriptions ..................................................................... 4080
42-47. AES_IRQSTATUS Register Field Descriptions ..................................................................... 4081
42-48. AES_IRQENABLE Register Field Descriptions ..................................................................... 4082
42-49. AES_DIRTY_BITS Register Field Descriptions ..................................................................... 4083
43-1. MII Interface Signals .................................................................................................... 4086
43-2. RMII Interface Signals .................................................................................................. 4088
43-3. RevMII Interface Signals ............................................................................................... 4090
43-4. Pulse Per Second Signals ............................................................................................. 4091
43-5. Auxiliary Trigger Sources............................................................................................... 4093
43-6. Fixed Priority Scheme for DMA Channels ........................................................................... 4097
43-7. Weight for DMA Channels ............................................................................................. 4097
43-8. Priority Scheme for Tx DMA and Rx DMA ........................................................................... 4098
43-9. Ordinary Clock PTM Messages for Snapshot ....................................................................... 4102
43-10. End to End Transparent Clock: PTP Messages for Snapshot .................................................... 4102
43-11. Peer to Peer Transparent Clock: PTP Messages for Snapshot................................................... 4102
43-12. Minimum PTP Clock Frequency Example ........................................................................... 4106
43-13. Message Format Defined in IEEE 1588-2008 ....................................................................... 4107
43-14. IPv4-UDP PTP Packet Fields Required for Control and Status ................................................... 4107
43-15. IPv6-UDP PTP Packet Fields Required for Control and Status ................................................... 4108
43-16. PTP Packets Over Ethernet ........................................................................................... 4109
43-17. Timestamp Snapshot Dependency on Register Bits ............................................................... 4110
43-18. Destination Address Filtering .......................................................................................... 4117
43-19. Source Address Filtering ............................................................................................... 4119
43-20. OTS and ITS Bit Values with At Least 1 Perfect Filter Enabled .................................................. 4121
43-21. OTS and ITS Bit Values with Only VLAN Hash Filter Enabled ................................................... 4121
43-22. Double VLAN Processing Features in Transmit Path .............................................................. 4124
43-23. Receive Path ............................................................................................................. 4124
43-24. VLAN Insertion or Replacement Based on VLTI Bit ................................................................ 4125
43-25. Transmit Checksum Offload Engine Functions for Different Packet Types ..................................... 4128
43-26. Receive Checksum Offload Engine Functions for Different Packet Types ...................................... 4129
43-27. TSO: TCP and IP Header Fields ...................................................................................... 4131
43-28. Details of IPv4 Fragmentation with UDP Checksum ............................................................... 4133
43-29. Details of IPv4 Fragmentation without UDP Checksum ............................................................ 4134
43-30. Segmentation Versus Fragmentation ................................................................................. 4134

138 List of Tables SPRUII0B – May 2019 – Revised May 2020

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43-31. RevMII Register Maps - MAC ......................................................................................... 4143

43-32. RevMII Register Map - Remote MAC................................................................................. 4143
43-33. MAC_RevMII_PHY_Control Register ................................................................................. 4144
43-34. MAC_RevMII_PHY_Control Register Description .................................................................. 4144
43-35. MAC_RevMII_Common_Status Register ............................................................................ 4145
43-36. MAC_RevMII_Common_Status Register Description .............................................................. 4145
43-37. MAC_RevMII_Common_Status Register ............................................................................ 4146
43-38. MAC_RevMII_Common_Status Register Description .............................................................. 4147
43-39. MAC_RevMII_Common_Ext_Status Register ....................................................................... 4148
43-40. MAC_RevMII_Common_Ext_Status Register Description......................................................... 4148
43-41. MAC_RevMII_Interrupt_Status_Mask Register ..................................................................... 4149
43-42. MAC_RevMII_Remote_PHY_Status Register ....................................................................... 4149
43-43. MAC_RevMII_Remote_PHY_Status Register Description ........................................................ 4149
43-44. MAC_RevMII_PHY_Status Register .................................................................................. 4150
43-45. MAC_RevMII_PHY_Status Register Description ................................................................... 4150
43-46. TDES0 Normal Descriptor (Read Format) Description ............................................................. 4153
43-47. TDES1 Normal Descriptor (Read Format) Description ............................................................. 4153
43-48. TDES2 Normal Descriptor (Read Format) Description ............................................................. 4153
43-49. TDES2 Normal Descriptor (Read Format) Description ............................................................. 4154
43-50. TDES3 Normal Descriptor (Read Format) ........................................................................... 4154
43-51. TDES3 Normal Descriptor (Read Format) Description ............................................................. 4155
43-52. TDES0 Normal Descriptor (Write-Back Format) Description ...................................................... 4157
43-53. TDES1 Normal Descriptor (Write-Back Format) Description ...................................................... 4158
43-54. TDES2 Normal Descriptor (Write-Back Format) Description ...................................................... 4158
43-55. TDES3 Normal Descriptor Layout (Write-Back Format) ........................................................... 4158
43-56. TDES3 Normal Descriptor (Write-Back Format) Description ...................................................... 4158
43-57. TDES0 Context Descriptor Description............................................................................... 4161
43-58. TDES1 Context Descriptor Description............................................................................... 4161
43-59. TDES2 Context Descriptor Description............................................................................... 4162
43-60. TDES3 Context Descriptor Layout .................................................................................... 4162
43-61. TDES3 Context Descriptor Description............................................................................... 4162
43-62. RDES0 Normal Descriptor (Read Format) Description ............................................................ 4164
43-63. RDES1 Normal Descriptor (Read Format) Description ............................................................ 4164
43-64. RDES2 Normal Descriptor (Read Format) Description ............................................................ 4165
43-65. RDES3 Normal Descriptor ............................................................................................ 4165
43-66. RDES3 Normal Descriptor (Read Format) Description ............................................................ 4165
43-67. RDES0 Normal Descriptor (Write-Back Format) Description ...................................................... 4166
43-68. RDES1 Normal Descriptor (Write-Back Format) .................................................................... 4166
43-69. RDES1 Normal Descriptor (Write-Back Format) Description ...................................................... 4166
43-70. RDES2 Normal Descriptor (Write-Back Format) .................................................................... 4168
43-71. RDES2 Normal Descriptor (Write-Back Format) Description ...................................................... 4168
43-72. RDES3 Normal Descriptor (Write-Back Format) .................................................................... 4170
43-73. RDES3 Normal Descriptor (Write-Back Format) Description ...................................................... 4170
43-74. RDES0 Context Descriptor............................................................................................. 4173
43-75. RDES1 Context Descriptor............................................................................................. 4173
43-76. RDES2 Context Descriptor............................................................................................. 4173
43-77. RDES3 Context Descriptor............................................................................................. 4174
43-78. RDES3 Context Descriptor Description .............................................................................. 4174
43-79. EMAC Base Address Table (CM) ..................................................................................... 4185

SPRUII0B – May 2019 – Revised May 2020 List of Tables 139

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43-80. ETHERNETSS_REGS Registers ..................................................................................... 4186

43-81. ETHERNETSS_REGS Access Type Codes......................................................................... 4186
43-82. ETHERNETSS_IPREVNUM Register Field Descriptions .......................................................... 4187
43-83. ETHERNETSS_CTRLSTS Register Field Descriptions ............................................................ 4188
43-84. ETHERNETSS_PTPTSTRIGSEL0 Register Field Descriptions .................................................. 4190
43-85. ETHERNETSS_PTPTSTRIGSEL1 Register Field Descriptions .................................................. 4191
43-86. ETHERNETSS_PTPTSSWTRIG0 Register Field Descriptions ................................................... 4192
43-87. ETHERNETSS_PTPTSSWTRIG1 Register Field Descriptions ................................................... 4193
43-88. ETHERNETSS_PTPPPSR0 Register Field Descriptions .......................................................... 4194
43-89. ETHERNETSS_PTPPPSR1 Register Field Descriptions .......................................................... 4195
43-90. ETHERNETSS_PTP_TSRL Register Field Descriptions .......................................................... 4196
43-91. ETHERNETSS_PTP_TSRH Register Field Descriptions .......................................................... 4197
43-92. ETHERNETSS_PTP_TSWL Register Field Descriptions .......................................................... 4198
43-93. ETHERNETSS_PTP_TSWH Register Field Descriptions ......................................................... 4199
43-94. ETHERNETSS_REVMII_CTRL Register Field Descriptions ...................................................... 4200
43-95. EMAC_REGS Registers ................................................................................................ 4201
43-96. EMAC_REGS Access Type Codes ................................................................................... 4225
43-97. MAC_Configuration Register Field Descriptions .................................................................... 4226
43-98. MAC_Ext_Configuration Register Field Descriptions ............................................................... 4232
43-99. MAC_Packet_Filter Register Field Descriptions .................................................................... 4234
43-100. MAC_Watchdog_Timeout Register Field Descriptions ........................................................... 4237
43-101. MAC_Hash_Table_Reg0 Register Field Descriptions ............................................................ 4238
43-102. MAC_Hash_Table_Reg1 Register Field Descriptions ............................................................ 4239
43-103. MAC_VLAN_Tag_Ctrl Register Field Descriptions ................................................................ 4240
43-104. MAC_VLAN_Tag_Data Register Field Descriptions .............................................................. 4242
43-105. MAC_VLAN_Hash_Table Register Field Descriptions ............................................................ 4244
43-106. MAC_VLAN_Incl Register Field Descriptions ...................................................................... 4245
43-107. MAC_Inner_VLAN_Incl Register Field Descriptions .............................................................. 4247
43-108. MAC_Q0_Tx_Flow_Ctrl Register Field Descriptions .............................................................. 4249
43-109. MAC_Rx_Flow_Ctrl Register Field Descriptions................................................................... 4251
43-110. MAC_RxQ_Ctrl4 Register Field Descriptions ...................................................................... 4252
43-111. MAC_RxQ_Ctrl0 Register Field Descriptions ...................................................................... 4254
43-112. MAC_RxQ_Ctrl1 Register Field Descriptions ...................................................................... 4255
43-113. MAC_RxQ_Ctrl2 Register Field Descriptions ...................................................................... 4257
43-114. MAC_Interrupt_Status Register Field Descriptions................................................................ 4258
43-115. MAC_Interrupt_Enable Register Field Descriptions ............................................................... 4261
43-116. MAC_Rx_Tx_Status Register Field Descriptions .................................................................. 4263
43-117. MAC_PMT_Control_Status Register Field Descriptions .......................................................... 4265
43-118. MAC_RWK_Packet_Filter Register Field Descriptions ........................................................... 4269
43-119. MAC_LPI_Control_Status Register Field Descriptions ........................................................... 4270
43-120. MAC_LPI_Timers_Control Register Field Descriptions ........................................................... 4273
43-121. MAC_LPI_Entry_Timer Register Field Descriptions .............................................................. 4274
43-122. MAC_1US_Tic_Counter Register Field Descriptions ............................................................. 4275
43-123. MAC_Version Register Field Descriptions.......................................................................... 4276
43-124. MAC_Debug Register Field Descriptions ........................................................................... 4277
43-125. MAC_HW_Feature0 Register Field Descriptions .................................................................. 4278
43-126. MAC_HW_Feature1 Register Field Descriptions .................................................................. 4281
43-127. MAC_HW_Feature2 Register Field Descriptions .................................................................. 4284
43-128. MAC_HW_Feature3 Register Field Descriptions .................................................................. 4286

140 List of Tables SPRUII0B – May 2019 – Revised May 2020

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43-129. MAC_MDIO_Address Register Field Descriptions ................................................................ 4288

43-130. MAC_MDIO_Data Register Field Descriptions .................................................................... 4291
43-131. MAC_ARP_Address Register Field Descriptions .................................................................. 4292
43-132. MAC_CSR_SW_Ctrl Register Field Descriptions ................................................................. 4293
43-133. MAC_Ext_Cfg1 Register Field Descriptions ........................................................................ 4294
43-134. MAC_Address0_High Register Field Descriptions ................................................................ 4295
43-135. MAC_Address0_Low Register Field Descriptions ................................................................. 4296
43-136. MAC_Address1_High Register Field Descriptions ................................................................ 4297
43-137. MAC_Address1_Low Register Field Descriptions ................................................................. 4299
43-138. MAC_Address2_High Register Field Descriptions ................................................................ 4300
43-139. MAC_Address2_Low Register Field Descriptions ................................................................. 4302
43-140. MAC_Address3_High Register Field Descriptions ................................................................ 4303
43-141. MAC_Address3_Low Register Field Descriptions ................................................................. 4305
43-142. MAC_Address4_High Register Field Descriptions ................................................................ 4306
43-143. MAC_Address4_Low Register Field Descriptions ................................................................. 4308
43-144. MAC_Address5_High Register Field Descriptions ................................................................ 4309
43-145. MAC_Address5_Low Register Field Descriptions ................................................................. 4311
43-146. MAC_Address6_High Register Field Descriptions ................................................................ 4312
43-147. MAC_Address6_Low Register Field Descriptions ................................................................. 4314
43-148. MAC_Address7_High Register Field Descriptions ................................................................ 4315
43-149. MAC_Address7_Low Register Field Descriptions ................................................................. 4317
43-150. MMC_Control Register Field Descriptions.......................................................................... 4318
43-151. MMC_Rx_Interrupt Register Field Descriptions ................................................................... 4320
43-152. MMC_Tx_Interrupt Register Field Descriptions .................................................................... 4325
43-153. MMC_Rx_Interrupt_Mask Register Field Descriptions ........................................................... 4331
43-154. MMC_Tx_Interrupt_Mask Register Field Descriptions ............................................................ 4335
43-155. Tx_Octet_Count_Good_Bad Register Field Descriptions ........................................................ 4339
43-156. Tx_Packet_Count_Good_Bad Register Field Descriptions ...................................................... 4340
43-157. Tx_Broadcast_Packets_Good Register Field Descriptions ...................................................... 4341
43-158. Tx_Multicast_Packets_Good Register Field Descriptions ........................................................ 4342
43-159. Tx_64Octets_Packets_Good_Bad Register Field Descriptions ................................................. 4343
43-160. Tx_65To127Octets_Packets_Good_Bad Register Field Descriptions .......................................... 4344
43-161. Tx_128To255Octets_Packets_Good_Bad Register Field Descriptions ........................................ 4345
43-162. Tx_256To511Octets_Packets_Good_Bad Register Field Descriptions ........................................ 4346
43-163. Tx_512To1023Octets_Packets_Good_Bad Register Field Descriptions ....................................... 4347
43-164. Tx_1024ToMaxOctets_Packets_Good_Bad Register Field Descriptions ...................................... 4348
43-165. Tx_Unicast_Packets_Good_Bad Register Field Descriptions ................................................... 4349
43-166. Tx_Multicast_Packets_Good_Bad Register Field Descriptions .................................................. 4350
43-167. Tx_Broadcast_Packets_Good_Bad Register Field Descriptions ................................................ 4351
43-168. Tx_Underflow_Error_Packets Register Field Descriptions ....................................................... 4352
43-169. Tx_Single_Collision_Good_Packets Register Field Descriptions ............................................... 4353
43-170. Tx_Multiple_Collision_Good_Packets Register Field Descriptions.............................................. 4354
43-171. Tx_Deferred_Packets Register Field Descriptions ................................................................ 4355
43-172. Tx_Late_Collision_Packets Register Field Descriptions .......................................................... 4356
43-173. Tx_Excessive_Collision_Packets Register Field Descriptions ................................................... 4357
43-174. Tx_Carrier_Error_Packets Register Field Descriptions ........................................................... 4358
43-175. Tx_Octet_Count_Good Register Field Descriptions .............................................................. 4359
43-176. Tx_Packet_Count_Good Register Field Descriptions ............................................................. 4360
43-177. Tx_Excessive_Deferral_Error Register Field Descriptions ....................................................... 4361

SPRUII0B – May 2019 – Revised May 2020 List of Tables 141

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43-178. Tx_Pause_Packets Register Field Descriptions ................................................................... 4362

43-179. Tx_VLAN_Packets_Good Register Field Descriptions ........................................................... 4363
43-180. Tx_OSize_Packets_Good Register Field Descriptions ........................................................... 4364
43-181. Rx_Packets_Count_Good_Bad Register Field Descriptions ..................................................... 4365
43-182. Rx_Octet_Count_Good_Bad Register Field Descriptions ........................................................ 4366
43-183. Rx_Octet_Count_Good Register Field Descriptions .............................................................. 4367
43-184. Rx_Broadcast_Packets_Good Register Field Descriptions ...................................................... 4368
43-185. Rx_Multicast_Packets_Good Register Field Descriptions ........................................................ 4369
43-186. Rx_CRC_Error_Packets Register Field Descriptions ............................................................. 4370
43-187. Rx_Alignment_Error_Packets Register Field Descriptions ....................................................... 4371
43-188. Rx_Runt_Error_Packets Register Field Descriptions ............................................................. 4372
43-189. Rx_Jabber_Error_Packets Register Field Descriptions ........................................................... 4373
43-190. Rx_Undersize_Packets_Good Register Field Descriptions ...................................................... 4374
43-191. Rx_Oversize_Packets_Good Register Field Descriptions ........................................................ 4375
43-192. Rx_64Octets_Packets_Good_Bad Register Field Descriptions ................................................. 4376
43-193. Rx_65To127Octets_Packets_Good_Bad Register Field Descriptions ......................................... 4377
43-194. Rx_128To255Octets_Packets_Good_Bad Register Field Descriptions ........................................ 4378
43-195. Rx_256To511Octets_Packets_Good_Bad Register Field Descriptions ........................................ 4379
43-196. Rx_512To1023Octets_Packets_Good_Bad Register Field Descriptions ...................................... 4380
43-197. Rx_1024ToMaxOctets_Packets_Good_Bad Register Field Descriptions ...................................... 4381
43-198. Rx_Unicast_Packets_Good Register Field Descriptions ......................................................... 4382
43-199. Rx_Length_Error_Packets Register Field Descriptions........................................................... 4383
43-200. Rx_Out_Of_Range_Type_Packets Register Field Descriptions ................................................. 4384
43-201. Rx_Pause_Packets Register Field Descriptions ................................................................... 4385
43-202. Rx_FIFO_Overflow_Packets Register Field Descriptions ........................................................ 4386
43-203. Rx_VLAN_Packets_Good_Bad Register Field Descriptions ..................................................... 4387
43-204. Rx_Watchdog_Error_Packets Register Field Descriptions ....................................................... 4388
43-205. Rx_Receive_Error_Packets Register Field Descriptions ......................................................... 4389
43-206. Rx_Control_Packets_Good Register Field Descriptions.......................................................... 4390
43-207. Tx_LPI_USEC_Cntr Register Field Descriptions .................................................................. 4391
43-208. Tx_LPI_Tran_Cntr Register Field Descriptions .................................................................... 4392
43-209. Rx_LPI_USEC_Cntr Register Field Descriptions .................................................................. 4393
43-210. Rx_LPI_Tran_Cntr Register Field Descriptions .................................................................... 4394
43-211. MMC_IPC_Rx_Interrupt_Mask Register Field Descriptions ..................................................... 4395
43-212. MMC_IPC_Rx_Interrupt Register Field Descriptions ............................................................. 4399
43-213. RxIPv4_Good_Packets Register Field Descriptions .............................................................. 4404
43-214. RxIPv4_Header_Error_Packets Register Field Descriptions ..................................................... 4405
43-215. RxIPv4_No_Payload_Packets Register Field Descriptions ...................................................... 4406
43-216. RxIPv4_Fragmented_Packets Register Field Descriptions ...................................................... 4407
43-217. RxIPv4_UDP_Checksum_Disabled_Packets Register Field Descriptions ..................................... 4408
43-218. RxIPv6_Good_Packets Register Field Descriptions .............................................................. 4409
43-219. RxIPv6_Header_Error_Packets Register Field Descriptions ..................................................... 4410
43-220. RxIPv6_No_Payload_Packets Register Field Descriptions ...................................................... 4411
43-221. RxUDP_Good_Packets Register Field Descriptions .............................................................. 4412
43-222. RxUDP_Error_Packets Register Field Descriptions ............................................................... 4413
43-223. RxTCP_Good_Packets Register Field Descriptions .............................................................. 4414
43-224. RxTCP_Error_Packets Register Field Descriptions ............................................................... 4415
43-225. RxICMP_Good_Packets Register Field Descriptions ............................................................. 4416
43-226. RxICMP_Error_Packets Register Field Descriptions .............................................................. 4417

142 List of Tables SPRUII0B – May 2019 – Revised May 2020

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43-227. RxIPv4_Good_Octets Register Field Descriptions ................................................................ 4418

43-228. RxIPv4_Header_Error_Octets Register Field Descriptions ...................................................... 4419
43-229. RxIPv4_No_Payload_Octets Register Field Descriptions ........................................................ 4420
43-230. RxIPv4_Fragmented_Octets Register Field Descriptions ........................................................ 4421
43-231. RxIPv4_UDP_Checksum_Disable_Octets Register Field Descriptions ........................................ 4422
43-232. RxIPv6_Good_Octets Register Field Descriptions ................................................................ 4423
43-233. RxIPv6_Header_Error_Octets Register Field Descriptions ...................................................... 4424
43-234. RxIPv6_No_Payload_Octets Register Field Descriptions ........................................................ 4425
43-235. RxUDP_Good_Octets Register Field Descriptions ................................................................ 4426
43-236. RxUDP_Error_Octets Register Field Descriptions ................................................................ 4427
43-237. RxTCP_Good_Octets Register Field Descriptions ................................................................ 4428
43-238. RxTCP_Error_Octets Register Field Descriptions ................................................................. 4429
43-239. RxICMP_Good_Octets Register Field Descriptions ............................................................... 4430
43-240. RxICMP_Error_Octets Register Field Descriptions ............................................................... 4431
43-241. MAC_L3_L4_Control0 Register Field Descriptions................................................................ 4432
43-242. MAC_Layer4_Address0 Register Field Descriptions.............................................................. 4435
43-243. MAC_Layer3_Addr0_Reg0 Register Field Descriptions .......................................................... 4436
43-244. MAC_Layer3_Addr1_Reg0 Register Field Descriptions .......................................................... 4437
43-245. MAC_Layer3_Addr2_Reg0 Register Field Descriptions .......................................................... 4438
43-246. MAC_Layer3_Addr3_Reg0 Register Field Descriptions .......................................................... 4439
43-247. MAC_L3_L4_Control1 Register Field Descriptions................................................................ 4440
43-248. MAC_Layer4_Address1 Register Field Descriptions.............................................................. 4443
43-249. MAC_Layer3_Addr0_Reg1 Register Field Descriptions .......................................................... 4444
43-250. MAC_Layer3_Addr1_Reg1 Register Field Descriptions .......................................................... 4445
43-251. MAC_Layer3_Addr2_Reg1 Register Field Descriptions .......................................................... 4446
43-252. MAC_Layer3_Addr3_Reg1 Register Field Descriptions .......................................................... 4447
43-253. MAC_L3_L4_Control2 Register Field Descriptions................................................................ 4448
43-254. MAC_Layer4_Address2 Register Field Descriptions.............................................................. 4451
43-255. MAC_Layer3_Addr0_Reg2 Register Field Descriptions .......................................................... 4452
43-256. MAC_Layer3_Addr1_Reg2 Register Field Descriptions .......................................................... 4453
43-257. MAC_Layer3_Addr2_Reg2 Register Field Descriptions .......................................................... 4454
43-258. MAC_Layer3_Addr3_Reg2 Register Field Descriptions .......................................................... 4455
43-259. MAC_L3_L4_Control3 Register Field Descriptions................................................................ 4456
43-260. MAC_Layer4_Address3 Register Field Descriptions.............................................................. 4459
43-261. MAC_Layer3_Addr0_Reg3 Register Field Descriptions .......................................................... 4460
43-262. MAC_Layer3_Addr1_Reg3 Register Field Descriptions .......................................................... 4461
43-263. MAC_Layer3_Addr2_Reg3 Register Field Descriptions .......................................................... 4462
43-264. MAC_Layer3_Addr3_Reg3 Register Field Descriptions .......................................................... 4463
43-265. MAC_Timestamp_Control Register Field Descriptions ........................................................... 4464
43-266. MAC_Sub_Second_Increment Register Field Descriptions ...................................................... 4468
43-267. MAC_System_Time_Seconds Register Field Descriptions ...................................................... 4469
43-268. MAC_System_Time_Nanoseconds Register Field Descriptions ................................................ 4470
43-269. MAC_System_Time_Seconds_Update Register Field Descriptions ............................................ 4471
43-270. MAC_System_Time_Nanoseconds_Update Register Field Descriptions ...................................... 4472
43-271. MAC_Timestamp_Addend Register Field Descriptions ........................................................... 4473
43-272. MAC_System_Time_Higher_Word_Seconds Register Field Descriptions ..................................... 4474
43-273. MAC_Timestamp_Status Register Field Descriptions ............................................................ 4475
43-274. MAC_Tx_Timestamp_Status_Nanoseconds Register Field Descriptions ...................................... 4478
43-275. MAC_Tx_Timestamp_Status_Seconds Register Field Descriptions ............................................ 4479

SPRUII0B – May 2019 – Revised May 2020 List of Tables 143

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43-276. MAC_Auxiliary_Control Register Field Descriptions .............................................................. 4480

43-277. MAC_Auxiliary_Timestamp_Nanoseconds Register Field Descriptions ........................................ 4481
43-278. MAC_Auxiliary_Timestamp_Seconds Register Field Descriptions .............................................. 4482
43-279. MAC_Timestamp_Ingress_Asym_Corr Register Field Descriptions ............................................ 4483
43-280. MAC_Timestamp_Egress_Asym_Corr Register Field Descriptions............................................. 4484
43-281. MAC_Timestamp_Ingress_Corr_Nanosecond Register Field Descriptions .................................... 4485
43-282. MAC_Timestamp_Egress_Corr_Nanosecond Register Field Descriptions .................................... 4486
43-283. MAC_Timestamp_Ingress_Corr_Subnanosec Register Field Descriptions .................................... 4487
43-284. MAC_Timestamp_Egress_Corr_Subnanosec Register Field Descriptions .................................... 4488
43-285. MAC_PPS_Control Register Field Descriptions ................................................................... 4489
43-286. MAC_PPS0_Target_Time_Seconds Register Field Descriptions ............................................... 4492
43-287. MAC_PPS0_Target_Time_Nanoseconds Register Field Descriptions ......................................... 4493
43-288. MAC_PPS0_Interval Register Field Descriptions ................................................................. 4494
43-289. MAC_PPS0_Width Register Field Descriptions ................................................................... 4495
43-290. MAC_PPS1_Target_Time_Seconds Register Field Descriptions ............................................... 4496
43-291. MAC_PPS1_Target_Time_Nanoseconds Register Field Descriptions ......................................... 4497
43-292. MAC_PPS1_Interval Register Field Descriptions ................................................................. 4498
43-293. MAC_PPS1_Width Register Field Descriptions ................................................................... 4499
43-294. MAC_PTO_Control Register Field Descriptions ................................................................... 4500
43-295. MAC_Source_Port_Identity0 Register Field Descriptions ........................................................ 4502
43-296. MAC_Source_Port_Identity1 Register Field Descriptions ........................................................ 4503
43-297. MAC_Source_Port_Identity2 Register Field Descriptions ........................................................ 4504
43-298. MAC_Log_Message_Interval Register Field Descriptions ....................................................... 4505
43-299. MTL_Operation_Mode Register Field Descriptions ............................................................... 4506
43-300. MTL_DBG_CTL Register Field Descriptions ....................................................................... 4508
43-301. MTL_DBG_STS Register Field Descriptions ....................................................................... 4511
43-302. MTL_FIFO_Debug_Data Register Field Descriptions............................................................. 4513
43-303. MTL_Interrupt_Status Register Field Descriptions ................................................................ 4514
43-304. MTL_RxQ_DMA_Map0 Register Field Descriptions .............................................................. 4515
43-305. MTL_TxQ0_Operation_Mode Register Field Descriptions ....................................................... 4517
43-306. MTL_TxQ0_Underflow Register Field Descriptions ............................................................... 4519
43-307. MTL_TxQ0_Debug Register Field Descriptions ................................................................... 4520
43-308. MTL_TxQ0_ETS_Status Register Field Descriptions ............................................................. 4522
43-309. MTL_TxQ0_Quantum_Weight Register Field Descriptions ...................................................... 4523
43-310. MTL_Q0_Interrupt_Control_Status Register Field Descriptions ................................................. 4524
43-311. MTL_RxQ0_Operation_Mode Register Field Descriptions ....................................................... 4526
43-312. MTL_RxQ0_Missed_Packet_Overflow_Cnt Register Field Descriptions ....................................... 4529
43-313. MTL_RxQ0_Debug Register Field Descriptions ................................................................... 4530
43-314. MTL_RxQ0_Control Register Field Descriptions .................................................................. 4531
43-315. MTL_TxQ1_Operation_Mode Register Field Descriptions ....................................................... 4532
43-316. MTL_TxQ1_Underflow Register Field Descriptions ............................................................... 4534
43-317. MTL_TxQ1_Debug Register Field Descriptions ................................................................... 4535
43-318. MTL_TxQ1_ETS_Status Register Field Descriptions ............................................................. 4537
43-319. MTL_TxQ1_Quantum_Weight Register Field Descriptions ...................................................... 4538
43-320. MTL_Q1_Interrupt_Control_Status Register Field Descriptions ................................................. 4539
43-321. MTL_RxQ1_Operation_Mode Register Field Descriptions ....................................................... 4541
43-322. MTL_RxQ1_Missed_Packet_Overflow_Cnt Register Field Descriptions ....................................... 4544
43-323. MTL_RxQ1_Debug Register Field Descriptions ................................................................... 4545
43-324. MTL_RxQ1_Control Register Field Descriptions .................................................................. 4546

144 List of Tables SPRUII0B – May 2019 – Revised May 2020

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43-325. DMA_Mode Register Field Descriptions ............................................................................ 4547

43-326. DMA_SysBus_Mode Register Field Descriptions ................................................................. 4549
43-327. DMA_Interrupt_Status Register Field Descriptions................................................................ 4551
43-328. DMA_Debug_Status0 Register Field Descriptions ................................................................ 4553
43-329. DMA_CH0_Control Register Field Descriptions ................................................................... 4555
43-330. DMA_CH0_Tx_Control Register Field Descriptions ............................................................... 4557
43-331. DMA_CH0_Rx_Control Register Field Descriptions .............................................................. 4559
43-332. DMA_CH0_TxDesc_List_Address Register Field Descriptions .................................................. 4561
43-333. DMA_CH0_RxDesc_List_Address Register Field Descriptions ................................................. 4562
43-334. DMA_CH0_TxDesc_Tail_Pointer Register Field Descriptions ................................................... 4563
43-335. DMA_CH0_RxDesc_Tail_Pointer Register Field Descriptions................................................... 4564
43-336. DMA_CH0_TxDesc_Ring_Length Register Field Descriptions .................................................. 4565
43-337. DMA_CH0_RxDesc_Ring_Length Register Field Descriptions .................................................. 4566
43-338. DMA_CH0_Interrupt_Enable Register Field Descriptions ........................................................ 4567
43-339. DMA_CH0_Rx_Interrupt_Watchdog_Timer Register Field Descriptions ....................................... 4569
43-340. DMA_CH0_Current_App_TxDesc Register Field Descriptions .................................................. 4570
43-341. DMA_CH0_Current_App_RxDesc Register Field Descriptions .................................................. 4571
43-342. DMA_CH0_Current_App_TxBuffer Register Field Descriptions ................................................. 4572
43-343. DMA_CH0_Current_App_RxBuffer Register Field Descriptions................................................. 4573
43-344. DMA_CH0_Status Register Field Descriptions .................................................................... 4574
43-345. DMA_CH0_Miss_Frame_Cnt Register Field Descriptions ....................................................... 4578
43-346. DMA_CH0_RX_ERI_Cnt Register Field Descriptions ............................................................ 4579
43-347. DMA_CH1_Control Register Field Descriptions ................................................................... 4580
43-348. DMA_CH1_Tx_Control Register Field Descriptions ............................................................... 4582
43-349. DMA_CH1_Rx_Control Register Field Descriptions .............................................................. 4584
43-350. DMA_CH1_TxDesc_List_Address Register Field Descriptions .................................................. 4586
43-351. DMA_CH1_RxDesc_List_Address Register Field Descriptions ................................................. 4587
43-352. DMA_CH1_TxDesc_Tail_Pointer Register Field Descriptions ................................................... 4588
43-353. DMA_CH1_RxDesc_Tail_Pointer Register Field Descriptions................................................... 4589
43-354. DMA_CH1_TxDesc_Ring_Length Register Field Descriptions .................................................. 4590
43-355. DMA_CH1_RxDesc_Ring_Length Register Field Descriptions .................................................. 4591
43-356. DMA_CH1_Interrupt_Enable Register Field Descriptions ........................................................ 4592
43-357. DMA_CH1_Rx_Interrupt_Watchdog_Timer Register Field Descriptions ....................................... 4594
43-358. DMA_CH1_Current_App_TxDesc Register Field Descriptions .................................................. 4595
43-359. DMA_CH1_Current_App_RxDesc Register Field Descriptions .................................................. 4596
43-360. DMA_CH1_Current_App_TxBuffer Register Field Descriptions ................................................. 4597
43-361. DMA_CH1_Current_App_RxBuffer Register Field Descriptions................................................. 4598
43-362. DMA_CH1_Status Register Field Descriptions .................................................................... 4599
43-363. DMA_CH1_Miss_Frame_Cnt Register Field Descriptions ....................................................... 4603
43-364. DMA_CH1_RX_ERI_Cnt Register Field Descriptions ............................................................ 4604
44-1. Fixed Polynomial Data Path Settings ................................................................................. 4608
44-2. Endianness Table ....................................................................................................... 4609
44-3. Data Mask Table ........................................................................................................ 4609
44-4. Bit Reverse Table ....................................................................................................... 4609
44-5. GCRC Base Address Table (CM) ..................................................................................... 4611
44-6. GCRC_REGS Registers ............................................................................................... 4612
44-7. GCRC_REGS Access Type Codes ................................................................................... 4612
44-8. CRCCTRL Register Field Descriptions ............................................................................... 4613
44-9. CRCPOLY Register Field Descriptions............................................................................... 4614

SPRUII0B – May 2019 – Revised May 2020 List of Tables 145

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44-10. CRCDATAMASK Register Field Descriptions ....................................................................... 4615

44-11. CRCDATAIN Register Field Descriptions ............................................................................ 4616
44-12. CRCDATAOUT Register Field Descriptions ......................................................................... 4617
44-13. CRCDATATRANS Register Field Descriptions ..................................................................... 4618
45-1. MCAN I/O Description .................................................................................................. 4622
45-2. MCAN Clocks and Resets ............................................................................................. 4624
45-3. MCAN Hardware Requests ............................................................................................ 4625
45-4. Steps to Configure MCAN Module .................................................................................... 4628
45-5. DLC Coding in CAN FD ................................................................................................ 4630
45-6. Rx Buffer/Rx FIFO Element Size ...................................................................................... 4643
45-7. Example Filter Configuration for Rx buffers ......................................................................... 4644
45-8. Rx Buffer/Rx FIFO Element Field Descriptions ..................................................................... 4647
45-9. Tx Buffer Element Field Descriptions ................................................................................. 4649
45-10. Tx Event FIFO Element Field Descriptions .......................................................................... 4650
45-11. Standard Message ID Filter Element Field Descriptions ........................................................... 4652
45-12. Extended Message ID Filter Element Field Descriptions .......................................................... 4653
45-13. MCAN Base Address Table (CM) ..................................................................................... 4655
45-14. MCAN_REGS Registers ............................................................................................... 4656
45-15. MCAN_REGS Access Type Codes ................................................................................... 4657
45-16. MCAN_CREL Register Field Descriptions ........................................................................... 4658
45-17. MCAN_ENDN Register Field Descriptions........................................................................... 4659
45-18. MCAN_DBTP Register Field Descriptions ........................................................................... 4660
45-19. MCAN_TEST Register Field Descriptions ........................................................................... 4662
45-20. MCAN_RWD Register Field Descriptions ............................................................................ 4663
45-21. MCAN_CCCR Register Field Descriptions .......................................................................... 4664
45-22. MCAN_NBTP Register Field Descriptions ........................................................................... 4667
45-23. MCAN_TSCC Register Field Descriptions ........................................................................... 4669
45-24. MCAN_TSCV Register Field Descriptions ........................................................................... 4670
45-25. MCAN_TOCC Register Field Descriptions........................................................................... 4671
45-26. MCAN_TOCV Register Field Descriptions ........................................................................... 4672
45-27. MCAN_ECR Register Field Descriptions ............................................................................ 4673
45-28. MCAN_PSR Register Field Descriptions ............................................................................. 4674
45-29. MCAN_TDCR Register Field Descriptions ........................................................................... 4677
45-30. MCAN_IR Register Field Descriptions ............................................................................... 4678
45-31. MCAN_IE Register Field Descriptions ................................................................................ 4681
45-32. MCAN_ILS Register Field Descriptions .............................................................................. 4683
45-33. MCAN_ILE Register Field Descriptions .............................................................................. 4686
45-34. MCAN_GFC Register Field Descriptions ............................................................................ 4687
45-35. MCAN_SIDFC Register Field Descriptions .......................................................................... 4688
45-36. MCAN_XIDFC Register Field Descriptions .......................................................................... 4689
45-37. MCAN_XIDAM Register Field Descriptions .......................................................................... 4690
45-38. MCAN_HPMS Register Field Descriptions .......................................................................... 4691
45-39. MCAN_NDAT1 Register Field Descriptions ......................................................................... 4692
45-40. MCAN_NDAT2 Register Field Descriptions ......................................................................... 4695
45-41. MCAN_RXF0C Register Field Descriptions ......................................................................... 4698
45-42. MCAN_RXF0S Register Field Descriptions ......................................................................... 4699
45-43. MCAN_RXF0A Register Field Descriptions ......................................................................... 4700
45-44. MCAN_RXBC Register Field Descriptions ........................................................................... 4701
45-45. MCAN_RXF1C Register Field Descriptions ......................................................................... 4702

146 List of Tables SPRUII0B – May 2019 – Revised May 2020

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45-46. MCAN_RXF1S Register Field Descriptions ......................................................................... 4703

45-47. MCAN_RXF1A Register Field Descriptions ......................................................................... 4704
45-48. MCAN_RXESC Register Field Descriptions ......................................................................... 4705
45-49. MCAN_TXBC Register Field Descriptions ........................................................................... 4707
45-50. MCAN_TXFQS Register Field Descriptions ......................................................................... 4709
45-51. MCAN_TXESC Register Field Descriptions ......................................................................... 4710
45-52. MCAN_TXBRP Register Field Descriptions ......................................................................... 4711
45-53. MCAN_TXBAR Register Field Descriptions ......................................................................... 4714
45-54. MCAN_TXBCR Register Field Descriptions ......................................................................... 4716
45-55. MCAN_TXBTO Register Field Descriptions ......................................................................... 4718
45-56. MCAN_TXBCF Register Field Descriptions ......................................................................... 4720
45-57. MCAN_TXBTIE Register Field Descriptions ......................................................................... 4722
45-58. MCAN_TXBCIE Register Field Descriptions ........................................................................ 4726
45-59. MCAN_TXEFC Register Field Descriptions ......................................................................... 4730
45-60. MCAN_TXEFS Register Field Descriptions ......................................................................... 4731
45-61. MCAN_TXEFA Register Field Descriptions ......................................................................... 4732
45-62. MCANSS_REGS Registers ............................................................................................ 4733
45-63. MCANSS_REGS Access Type Codes ............................................................................... 4733
45-64. MCANSS_PID Register Field Descriptions .......................................................................... 4734
45-65. MCANSS_CTRL Register Field Descriptions........................................................................ 4735
45-66. MCANSS_STAT Register Field Descriptions ........................................................................ 4736
45-67. MCANSS_ICS Register Field Descriptions .......................................................................... 4737
45-68. MCANSS_IRS Register Field Descriptions .......................................................................... 4738
45-69. MCANSS_IECS Register Field Descriptions ........................................................................ 4739
45-70. MCANSS_IE Register Field Descriptions ............................................................................ 4740
45-71. MCANSS_IES Register Field Descriptions .......................................................................... 4741
45-72. MCANSS_EOI Register Field Descriptions .......................................................................... 4742
45-73. MCANSS_EXT_TS_PRESCALER Register Field Descriptions................................................... 4743
45-74. MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Register Field Descriptions ................................ 4744
45-75. MCAN_ERROR_REGS Registers .................................................................................... 4745
45-76. MCAN_ERROR_REGS Access Type Codes........................................................................ 4745
45-77. MCANERR_REV Register Field Descriptions ....................................................................... 4747
45-78. MCANERR_VECTOR Register Field Descriptions ................................................................. 4748
45-79. MCANERR_STAT Register Field Descriptions...................................................................... 4749
45-80. MCANERR_WRAP_REV Register Field Descriptions ............................................................. 4750
45-81. MCANERR_CTRL Register Field Descriptions ..................................................................... 4751
45-82. MCANERR_ERR_CTRL1 Register Field Descriptions ............................................................. 4753
45-83. MCANERR_ERR_CTRL2 Register Field Descriptions ............................................................. 4754
45-84. MCANERR_ERR_STAT1 Register Field Descriptions ............................................................. 4755
45-85. MCANERR_ERR_STAT2 Register Field Descriptions ............................................................. 4757
45-86. MCANERR_ERR_STAT3 Register Field Descriptions ............................................................. 4758
45-87. MCANERR_SEC_EOI Register Field Descriptions ................................................................. 4759
45-88. MCANERR_SEC_STATUS Register Field Descriptions ........................................................... 4760
45-89. MCANERR_SEC_ENABLE_SET Register Field Descriptions .................................................... 4761
45-90. MCANERR_SEC_ENABLE_CLR Register Field Descriptions .................................................... 4762
45-91. MCANERR_DED_EOI Register Field Descriptions ................................................................. 4763
45-92. MCANERR_DED_STATUS Register Field Descriptions ........................................................... 4764
45-93. MCANERR_DED_ENABLE_SET Register Field Descriptions .................................................... 4765
45-94. MCANERR_DED_ENABLE_CLR Register Field Descriptions .................................................... 4766

SPRUII0B – May 2019 – Revised May 2020 List of Tables 147

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45-95. MCANERR_AGGR_ENABLE_SET Register Field Descriptions .................................................. 4767

45-96. MCANERR_AGGR_ENABLE_CLR Register Field Descriptions ................................................. 4768
45-97. MCANERR_AGGR_STATUS_SET Register Field Descriptions .................................................. 4769
45-98. MCANERR_AGGR_STATUS_CLR Register Field Descriptions ................................................. 4770
46-1. Examples of I2C Master Timer Period Versus Speed Mode ...................................................... 4779
46-2. Examples of I2C Master Timer Period in High-Speed Mode ...................................................... 4780
46-3. CM I2C Base Address Table (CM).................................................................................... 4792
46-4. CM_I2C_REGS Registers.............................................................................................. 4793
46-5. CM_I2C_REGS Access Type Codes ................................................................................. 4793
46-6. I2CMSA Register Field Descriptions.................................................................................. 4795
46-7. I2CMCS Register Field Descriptions ................................................................................. 4796
46-8. I2CMDR Register Field Descriptions ................................................................................. 4798
46-9. I2CMTPR Register Field Descriptions ................................................................................ 4799
46-10. I2CMIMR Register Field Descriptions ................................................................................ 4800
46-11. I2CMRIS Register Field Descriptions ................................................................................. 4802
46-12. I2CMMIS Register Field Descriptions ................................................................................ 4804
46-13. I2CMICR Register Field Descriptions................................................................................. 4806
46-14. I2CMCR Register Field Descriptions ................................................................................. 4808
46-15. I2CMCLKOCNT Register Field Descriptions ........................................................................ 4809
46-16. I2CMBMON Register Field Descriptions ............................................................................. 4810
46-17. I2CMBLEN Register Field Descriptions .............................................................................. 4811
46-18. I2CMBCNT Register Field Descriptions .............................................................................. 4812
46-19. I2CSOAR Register Field Descriptions ................................................................................ 4813
46-20. I2CSCSR Register Field Descriptions ................................................................................ 4814
46-21. I2CSDR Register Field Descriptions .................................................................................. 4816
46-22. I2CSIMR Register Field Descriptions ................................................................................. 4817
46-23. I2CSRIS Register Field Descriptions ................................................................................. 4819
46-24. I2CSMIS Register Field Descriptions ................................................................................. 4821
46-25. I2CSICR Register Field Descriptions ................................................................................. 4823
46-26. I2CSOAR2 Register Field Descriptions .............................................................................. 4825
46-27. I2CSACKCTL Register Field Descriptions ........................................................................... 4826
46-28. I2CFIFODATARX Register Field Descriptions ...................................................................... 4827
46-29. I2CFIFOCTL Register Field Descriptions ............................................................................ 4828
46-30. I2CFIFOSTATUS Register Field Descriptions ....................................................................... 4830
46-31. I2CPP Register Field Descriptions .................................................................................... 4831
46-32. I2CPC Register Field Descriptions .................................................................................... 4832
46-33. CM_I2C_WRITE_REGS Registers ................................................................................... 4833
46-34. CM_I2C_WRITE_REGS Access Type Codes ....................................................................... 4833
46-35. I2CMCS_WRITE Register Field Descriptions ....................................................................... 4834
46-36. I2CSCSR_WRITE Register Field Descriptions ...................................................................... 4836
46-37. I2CFIFODATATX Register Field Descriptions ....................................................................... 4837
47-1. SSInFss Functionality ................................................................................................... 4842
47-2. SSI Base Address Table (CM) ........................................................................................ 4849
47-3. SSI_REGS Registers ................................................................................................... 4850
47-4. SSI_REGS Access Type Codes ...................................................................................... 4850
47-5. SSICR0 Register Field Descriptions .................................................................................. 4852
47-6. SSICR1 Register Field Descriptions .................................................................................. 4854
47-7. SSIDR Register Field Descriptions ................................................................................... 4856
47-8. SSISR Register Field Descriptions.................................................................................... 4857

148 List of Tables SPRUII0B – May 2019 – Revised May 2020

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47-9. SSICPSR Register Field Descriptions ................................................................................ 4858

47-10. SSIIM Register Field Descriptions .................................................................................... 4859
47-11. SSIRIS Register Field Descriptions ................................................................................... 4860
47-12. SSIMIS Register Field Descriptions .................................................................................. 4862
47-13. SSIICR Register Field Descriptions ................................................................................... 4864
47-14. SSIDMACTL Register Field Descriptions ............................................................................ 4865
47-15. SSIPV Register Field Descriptions .................................................................................... 4866
47-16. SSIPP Register Field Descriptions .................................................................................... 4867
47-17. SSIPC Register Field Descriptions.................................................................................... 4868
47-18. SSIPeriphID4 Register Field Descriptions ........................................................................... 4869
47-19. SSIPeriphID5 Register Field Descriptions ........................................................................... 4870
47-20. SSIPeriphID6 Register Field Descriptions ........................................................................... 4871
47-21. SSIPeriphID7 Register Field Descriptions ........................................................................... 4872
47-22. SSIPeriphID0 Register Field Descriptions ........................................................................... 4873
47-23. SSIPeriphID1 Register Field Descriptions ........................................................................... 4874
47-24. SSIPeriphID2 Register Field Descriptions ........................................................................... 4875
47-25. SSIPeriphID3 Register Field Descriptions ........................................................................... 4876
47-26. SSIPCellID0 Register Field Descriptions ............................................................................. 4877
47-27. SSIPCellID1 Register Field Descriptions ............................................................................. 4878
47-28. SSIPCellID2 Register Field Descriptions ............................................................................. 4879
47-29. SSIPCellID3 Register Field Descriptions ............................................................................. 4880
48-1. UART Base Address Table (CM) ..................................................................................... 4889
48-2. UART_REGS Registers ................................................................................................ 4890
48-3. UART_REGS Access Type Codes ................................................................................... 4890
48-4. UARTDR Register Field Descriptions ................................................................................ 4892
48-5. UARTRSR Register Field Descriptions............................................................................... 4894
48-6. UARTFR Register Field Descriptions ................................................................................. 4895
48-7. UARTILPR Register Field Descriptions .............................................................................. 4897
48-8. UARTIBRD Register Field Descriptions .............................................................................. 4898
48-9. UARTFBRD Register Field Descriptions ............................................................................. 4899
48-10. UARTLCRH Register Field Descriptions ............................................................................. 4900
48-11. UARTCTL Register Field Descriptions ............................................................................... 4902
48-12. UARTIFLS Register Field Descriptions............................................................................... 4904
48-13. UARTIM Register Field Descriptions ................................................................................. 4905
48-14. UARTRIS Register Field Descriptions ................................................................................ 4907
48-15. UARTMIS Register Field Descriptions ............................................................................... 4909
48-16. UARTICR Register Field Descriptions ................................................................................ 4911
48-17. UARTDMACTL Register Field Descriptions ......................................................................... 4913
48-18. UART9BITADDR Register Field Descriptions ....................................................................... 4914
48-19. UART9BITAMASK Register Field Descriptions ..................................................................... 4915
48-20. UARTPP Register Field Descriptions ................................................................................. 4916
48-21. UARTPeriphID4 Register Field Descriptions ........................................................................ 4917
48-22. UARTPeriphID5 Register Field Descriptions ........................................................................ 4918
48-23. UARTPeriphID6 Register Field Descriptions ........................................................................ 4919
48-24. UARTPeriphID7 Register Field Descriptions ........................................................................ 4920
48-25. UARTPeriphID0 Register Field Descriptions ........................................................................ 4921
48-26. UARTPeriphID1 Register Field Descriptions ........................................................................ 4922
48-27. UARTPeriphID2 Register Field Descriptions ........................................................................ 4923
48-28. UARTPeriphID3 Register Field Descriptions ........................................................................ 4924

SPRUII0B – May 2019 – Revised May 2020 List of Tables 149

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48-29. UARTPCellID0 Register Field Descriptions .......................................................................... 4925

48-30. UARTPCellID1 Register Field Descriptions .......................................................................... 4926
48-31. UARTPCellID2 Register Field Descriptions .......................................................................... 4927
48-32. UARTPCellID3 Register Field Descriptions .......................................................................... 4928
48-33. UART_REGS_WRITE Registers ...................................................................................... 4929
48-34. UART_REGS_WRITE Access Type Codes ......................................................................... 4929
48-35. UARTECR Register Field Descriptions............................................................................... 4930
49-1. µDMA Channel Assignment Mapping ................................................................................ 4934
49-2. Request Type Support .................................................................................................. 4936
49-3. Control Structure Memory Map ........................................................................................ 4937
49-4. Channel Control Structure ............................................................................................. 4937
49-5. µDMA Read Example: 8-Bit Peripheral .............................................................................. 4945
49-6. µDMA Interrupt Assignments .......................................................................................... 4946
49-7. Channel Control Structure Offsets for Channel 30 ................................................................. 4947
49-8. Channel Control Word Configuration for Memory Transfer Example ............................................ 4947
49-9. Channel Control Structure Offsets for Channel 7 ................................................................... 4948
49-10. Channel Control Word Configuration for Peripheral Transmit Example ......................................... 4949
49-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ........................................ 4950
49-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive Example ............................. 4951
49-13. UDMA Base Address Table (CM) ..................................................................................... 4952
49-14. UDMAREGS Registers ................................................................................................. 4953
49-15. UDMAREGS Access Type Codes .................................................................................... 4953
49-16. DMASTAT Register Field Descriptions ............................................................................... 4955
49-17. DMACFG Register Field Descriptions ................................................................................ 4956
49-18. DMACTLBASE Register Field Descriptions ......................................................................... 4957
49-19. DMAALTBASE Register Field Descriptions ......................................................................... 4958
49-20. DMASWREQ Register Field Descriptions ........................................................................... 4959
49-21. DMAUSEBURSTSET Register Field Descriptions .................................................................. 4960
49-22. DMAUSEBURSTCLR Register Field Descriptions.................................................................. 4961
49-23. DMAREQMASKSET Register Field Descriptions ................................................................... 4962
49-24. DMAREQMASKCLR Register Field Descriptions ................................................................... 4963
49-25. DMAENASET Register Field Descriptions ........................................................................... 4964
49-26. DMAENACLR Register Field Descriptions ........................................................................... 4965
49-27. DMAALTSET Register Field Descriptions ........................................................................... 4966
49-28. DMAALTCLR Register Field Descriptions ........................................................................... 4967
49-29. DMAPRIOSET Register Field Descriptions .......................................................................... 4968
49-30. DMAPRIOCLR Register Field Descriptions .......................................................................... 4969
49-31. DMAERRCLR Register Field Descriptions........................................................................... 4970
49-32. DMACHMAP0 Register Field Descriptions .......................................................................... 4971
49-33. DMACHMAP1 Register Field Descriptions .......................................................................... 4972
49-34. DMACHMAP2 Register Field Descriptions .......................................................................... 4973
49-35. DMACHMAP3 Register Field Descriptions .......................................................................... 4974
49-36. DMAPeriphID4 Register Field Descriptions .......................................................................... 4975
49-37. DMAPeriphID0 Register Field Descriptions .......................................................................... 4976
49-38. DMAPeriphID1 Register Field Descriptions .......................................................................... 4977
49-39. DMAPeriphID2 Register Field Descriptions .......................................................................... 4978
49-40. DMAPeriphID3 Register Field Descriptions .......................................................................... 4979
49-41. DMAPCellID0 Register Field Descriptions ........................................................................... 4980
49-42. DMAPCellID1 Register Field Descriptions ........................................................................... 4981

150 List of Tables SPRUII0B – May 2019 – Revised May 2020

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49-43. DMAPCellID2 Register Field Descriptions ........................................................................... 4982

49-44. DMAPCellID3 Register Field Descriptions ........................................................................... 4983
49-45. UDMACHDES Registers ............................................................................................... 4984
49-46. UDMACHDES Access Type Codes .................................................................................. 4984
49-47. DMASRCENDP Register Field Descriptions ........................................................................ 4985
49-48. DMADSTENDP Register Field Descriptions ......................................................................... 4986
49-49. DMACHCTL Register Field Descriptions ............................................................................. 4987

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 Preface
SPRUII0B – May 2019 – Revised May 2020

Read This First

About This Manual

This Technical Reference Manual (TRM) details the integration, the environment, the functional
description, and the programming models for each peripheral and subsystem in the device.
The TRM should not be considered a substitute for the data manual, rather a companion guide that should
be used alongside the device-specific data manual to understand the details to program the device. The
primary purpose of the TRM is to abstract the programming details of the device from the data manual.
This allows the data manual to outline the high-level features of the device without unnecessary
information about register descriptions or programming models.

Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers may be shown with the suffix h or the prefix 0x. For example, the following
number is 40 hexadecimal (decimal 64): 40h or 0x40.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties with default reset value below. A legend explains the notation used for the
properties.
– Reserved bits in a register figure can have one of multiple meanings:
• Not implemented on the device
• Reserved for future device expansion
• Reserved for TI testing
• Reserved configurations of the device that are not supported
– Writing nondefault values to the Reserved bits could cause unexpected behavior and should be
avoided.

Glossary
TI Glossary — This glossary lists and explains terms, acronyms, and definitions.

Related Documentation From Texas Instruments

For a complete listing of related documentation and development-support tools for these devices, visit the
Texas Instruments website at http://www.ti.com. Additionally, the TMS320C28x CPU and Instruction Set
Reference Guide and TMS320C28x Floating Point Unit and Instruction Set Reference Guide must be used
in conjunction with this TRM.
Trademarks
C2000, Code Composer Studio are trademarks of Texas Instruments.
Arm7 is a trademark of Arm Limited.
Arm, Cortex, PrimeCell are registered trademarks of Arm Limited.
EtherCAT, Beckhoff Automation are trademarks of Beckhoff Automation GmbH.
USB Specification Revision 2.0 is a trademark of Compaq Computer Corp.

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 Chapter 1
SPRUII0B – May 2019 – Revised May 2020

► C28 SYSTEM RESOURCES

The following chapters describe the C28 Configuration and System Resources.

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Technical Reference Manual Overview www.ti.com

1.1 Technical Reference Manual Overview

The block diagram for the F2838x device is shown below below in Figure 39-1. This Technical Reference
Manual is organized into five major sections:
• C28 SYSTEM RESOURCES
These chapters describe the C28 CPU subsystem, C28 Boot ROM, device configuration, and other
system peripherals.
• ANALOG PERIPHERALS
These chapters describe the Analog-to-Digital Converter (ADC), Buffered Digital-to-Analog Converter
(DAC), Comparator Subsystem (CMPSS), and general analog subsystem configuration.
• CONTROL PERIPHERALS
These chapters describe the Enhanced Capture (eCAP), High Resolution Capture (HRCAP),
Enhanced Pulse Width Modulator (ePWM), Enhanced Quadrature Encoder Pulse (eQEP), and Sigma
Delta Filter Module (SDFM) peripherals.
• COMMUNICATION PERIPHERALS
These chapters describe the communication peripherals available to the C28 subsystem such as I2C,
SCI, FSI, McBSP, PMBUS, and SPI. The CAN, EtherCAT, and USB peripherals are also described in
this section and can be assigned to the CM subsystem.
• CONNECTIVITY MANAGER (CM)
These chapters describe the Connectivity Manager subsystem as well as the AES, GCRC, CM-I2C,
CM-UART, SSI, and Ethernet peripherals.

Figure 1-1. F2838x Block Diagram

C28 CPU1 CPU1 - CM C28 CPU2 Connectivity

IPC Manager (CM) CPU1
FPU64 FPU64 CPU1.CLA
FPU32 MSGRAM0 FPU32 CPU1.DMA
CPU1.CLA1 TMU TMU CPU2.CLA1 Arm Cortex-M4
MSGRAM1
VCRC VCRC CPU2
CPU2.CLA
CPU2.DMA
CPU2 - CM AES
BGCRC BGCRC IPC BGCRC BGCRC CPU Timers CM M4 CODE
CPU Timers CPU Timers GCRC CM M4 SYS
DCC MSGRAM0 NVIC CM µDMA
CPU - CLA ePIE ePIE CPU - CLA NMI WD CM Bus Matrix
MSGRAM MSGRAM1 MSGRAM Windowed WD
ERAD ERAD Ethernet DMA
NMI WD NMI WD
Windowed WD Windowed WD
CPU1 - CPU2 Boot ROM
IPC Secure
CLA ROM Boot ROM Boot ROM CLA ROM Secure ROM Memories
Secure ROM MSGRAM0 Secure ROM shown in Red
Flash (512KB)
MSGRAM1
Flash (512KB) Flash (512KB)
C0-C1 RAM (16KB)

M0-M1 RAM (4KB) M0-M1 RAM (4KB) E0 RAM (16KB)

LS0-LS7 RAM GS0-GS15 RAM LS0-LS7 RAM
(32KB) D0-D1 RAM (8KB) (128KB) D0-D1 RAM (8KB) (32KB) S0-S3 RAM (64KB)

DMA - CLA DMA - CLA

MSGRAM CPU1.DMA CPU2.DMA MSGRAM CM µDMA

CM Bus
Matrix

PF3 PF1 PF9 PF2 PF5 PF6 PF4 MUX MUX MUX

Result 8x CMPSS 2x I2C 8x FSIRX EMIF1 EMIF2 Data 2x CAN 1x USB 1x EtherCAT DMA
4x 16-bit / 12-bit ADC 3x DAC 4x SCI 2x FSITX 169x GPIO (2 Ports) 1x Ethernet
7x eCAP 2x McBSP Input XBAR 1x CM-I2C
(2 Hi-Res) 1x PMBUS Output XBAR 1x CM-UART
32x ePWM 4x SPI ePWM XBAR 1x SSI
Channels
(16 Hi-Res) 1x CAN-FD
3x eQEP
8x SD Filters

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 Chapter 2
SPRUII0B – May 2019 – Revised May 2020

C2000 Software Support

C2000Ware for C2000™ Microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device
peripheral examples, C2000Ware provides a solid foundation to begin development and evaluation of your
product.

Topic ........................................................................................................................... Page

2.1 Introduction ..................................................................................................... 156

2.2 C2000Ware Structure ........................................................................................ 156
2.3 Documentation ................................................................................................. 156
2.4 Devices ........................................................................................................... 156
2.5 Libraries .......................................................................................................... 156
2.6 Code Composer Studio™ Integrated Development Environment (IDE) .................... 157
2.7 PinMUX Tool .................................................................................................... 157

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2.1 Introduction
C2000Ware for C2000 Microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device
peripheral examples, C2000Ware provides a solid foundation to begin development and evaluation of your
product.
C2000Ware can be downloaded from: www.ti.com/tool/C2000WARE

2.2 C2000Ware Structure

The C2000Ware software package is organized into the following directory structure:

Table 2-1. C2000Ware Root Directories

Directory Name Description
boards Contains the hardware design schematics, BOM, gerber files, and documentation for
C2000 controlCARDS,
device_support Contains all device-specific support files, bit field headers and device development
user's guides.
docs Contains the C2000Ware package user's guides and the HTML index page of all
package documentation.
driverlib Contains the device-specific driver library and driver-based peripheral examples.
libraries Contains the device-specific and core libraries.

2.3 Documentation
Within C2000Ware, there is an extensive amount of development documentation ranging from board
design documentation, to library user's guides, to driver API documentation. The "boards" directory
contains all the hardware design, BOM, gerber files, and more for controlCARDs. To assist with locating
the necessary documentation, an HTML page is provided that contains a full list of all the documents in
the C2000Ware package. Locate this page in the "docs" directory.

2.4 Devices
C2000Ware contains the necessary software and documentation to jumpstart development for C2000
microcontrollers. Each device includes device-specific common source files, peripheral example projects,
bit field headers, and if available, a device peripheral driver library. Additionally, documentation is provided
for each device on how to set up a CCS project, as well as give an overview of all the included example
projects and assist with troubleshooting. For devices with a driver library, documentation is also included
that details all the peripheral APIs available.
To learn more about C2000 microcontrollers, visit www.ti.com/c2000.

2.5 Libraries
The libraries included in C2000Ware range from fixed point and floating point math libraries, to specialized
DSP libraries, as well as calibration libraries. Each library includes documentation and examples, where
applicable. Additionally, the flash API files and boot ROM source code are located in the "libraries"
directory.

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www.ti.com Code Composer Studio™ Integrated Development Environment (IDE)

2.6 Code Composer Studio™ Integrated Development Environment (IDE)

Code Composer Studio™ is an integrated development environment (IDE) that supports TI's
microcontroller and embedded processors portfolio. Code Composer Studio IDE comprises a suite of tools
used to develop and debug embedded applications. The latest version of Code Composer Studio IDE can
be obtained at the following link:
http://www.ti.com/ccstudio
All projects and examples in C2000Ware are built for and tested with TI’s Code Composer Studio IDE.
Although Code Composer Studio IDE is not included with the C2000Ware installer, it is easily obtainable
in a variety of versions.

2.7 PinMUX Tool

The Pin MUX Utility is a software tool which provides a Graphical User Interface for configuring pin
multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. Results are
output as C header/code files that can be imported into software development kits (SDKs) or used to
configure customer's custom software.
The latest version of the PinMux Tool can be obtained at the following link:http://dev.ti.com/

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 Chapter 3
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C28x System Control

This chapter explains system control and interrupts for the C28x cores found on this MCU. The system
control module configures and manages the overall operation of the device, and provides information
about the device status. Configurable features in system control include reset control, NMI operation,
peripheral interrupts, power control, clock control, and low-power modes.

Topic ........................................................................................................................... Page

3.1 C28x System Control Introduction ...................................................................... 159

3.2 System Control Functional Description ............................................................... 159
3.3 Resets ............................................................................................................. 160
3.4 Peripheral Interrupts ......................................................................................... 163
3.5 Exceptions and Non-Maskable Interrupts ............................................................ 176
3.6 Safety Features ................................................................................................ 178
3.7 Clocking ......................................................................................................... 182
3.8 Clock Configuration Semaphore ......................................................................... 193
3.9 32-Bit CPU Timers 0/1/2 ..................................................................................... 194
3.10 Watchdog Timers ............................................................................................. 195
3.11 Low Power Modes ............................................................................................ 198
3.12 Memory Controller Module ................................................................................ 199
3.13 JTAG............................................................................................................... 209
3.14 System Control Registers .................................................................................. 210

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3.1 C28x System Control Introduction

On this device, the CPU1 subsystem acts as a master, and by default (upon reset), it owns all the
configuration and control. Through software running on CPU1, peripherals and I/Os can be configured to
be accessible by the CPU2 subsystem or the CM subsystem and the chosen configurations can be
locked.
The PLL clock configuration is also owned by the CPU1 subsystem by default, but a clock control
semaphore is provided by which CPU2 can grab access to the clock configuration registers.
Each CPU can be independently configured to accept interrupts from different peripherals. The interrupt
path is divided into three stages – the peripheral, the PIE, and the CPU. All stages must be configured
and enabled for an interrupt to propagate to the CPU.
Each CPU has its own NMI module to handle different exceptions during run time. If the NMI was on
CPU1, any NMI exception that is unhandled before the NMI Watchdog (NMIWD) timer expiration will reset
the entire device. If the NMI was on the CPU2 subsystem, then the CPU2 subsystem alone will be reset,
in which case the CPU1 subsystem will be informed by another NMI that the CPU2 subsystem was reset
because of NMIWD timer expiration.
Each CPU subsystem has its own watchdog timer module for software to use. Watchdog timer expiration
on CPU2 will reset the CPU2 subsystem alone when configured to generate a reset, but watchdog timer
expiration on CPU1 will reset the entire device.
Except for a CPU2 standalone internal reset such as CPU2.NMIWD or CPU2.WD each time the device is
reset, the CPU2 subsystem will be held under reset until the CPU1 subsystem brings it out of reset. This
is done by the boot ROM software running on the CPU1 core.
The register space of the device system control module can be found in Section 3.14.1.
This chapter explains the system control module on both the CPU subsystems.

3.2 System Control Functional Description

The system control module provides the following capabilities:
• Device identification and configuration registers
• Reset control
• Exceptions and Interrupt control
• Safety and error handling features of the device
• Power control
• Clock control
• Low Power modes
• Security module
• Inter-Processor Communication (IPC)

3.2.1 Device Identification

Device identification registers provide information on device class, device family, revision, part number, pin
count, and device qualification status.
All of the device information is part of the DEV_CFG_REGS space and is accessible only by the software
running on the CPU1 subsystem.
The C28x device identification registers are: PARTIDL, PARTIDH, and REVID.
A 256-bit Unique ID (UID) is available in UID_REGS. The 256 bits are separated into these registers:
• UID_PSRAND0-5: 192 bits of pseudo-random data
• UID_UNIQUE: 32-bit unique data; the value in this register will be unique across all devices with the
same PARTIDH
• UID_CHECKSUM: 32-bit fletcher checksum of UID_PSRAND0-5 and UID_UNIQUE and calculated as
either little- or big-endian during factory testing

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• CPU ID: 16-bit location in OTP. The value at this location provides the information about CPU (CPU1
or CPU2).

3.2.2 Device Configuration Registers

Several registers provide users with configuration information for the C28x subsystems for debug and
identification purposes. This information includes the features of the peripherals and how much RAM and
FLASH memory is available on this part.
These registers are part of DEV_CFG_REGS space and are accessible only by the software running on
the CPU1 subsystem.
• DC0 – DC27: Device Configuration or Capabilities registers.
If a particular bit in these registers is set to ‘1’ then the associated/feature or module is available in the
device.
• PERCNF: Peripheral configuration register.
This register configures ADC capabilities, and enables or disables the USB internal PHY.
• CPUID: CPU identification register. This register is available for software to identify on which CPU it is
executing.

3.3 Resets
This section explains the types and effects of the different resets on this device.

3.3.1 Reset Sources

Table 3-1 summarizes the various reset signals and their effect on the device.

Table 3-1. Reset Signals (1)

Reset Source CPU1 CPU1 CPU2 CPU2 and CPU2 and JTAG / IOs XRSn
Core Peripheral Core CM CM Held Debug Output
Reset Reset Reset Peripheral In Reset Logic
(C28x, (C28x, Reset Reset
TMU, FPU, TMU, FPU,
VCU) VCU)
POR Yes Yes Yes Yes Yes Yes Hi-Z Yes
XRSn Pin Yes Yes Yes Yes Yes - Hi-Z -
CPU1.SIMRESET.XRSn Yes Yes Yes Yes Yes - Hi-Z Yes
CPU1.WDRS Yes Yes Yes Yes Yes - Hi-Z Yes
CPU1.NMIWDRS Yes Yes Yes Yes Yes - Hi-Z Yes
CPU1.SYSRS Yes Yes Yes Yes Yes - Hi-Z -
(Debugger Reset)
CPU1.SIMRESET.CPU1 Yes Yes Yes Yes Yes - Hi-Z -
RSn
CPU1.SCCRESET Yes Yes Yes Yes Yes - Hi-Z -
CPU1.HWBISTRS Yes - - - - - - -
CPU2.SYSRS - - Yes Yes - - - -
(Debugger Reset)
CPU2.WDRS - - Yes Yes - - - -
CPU2.NMIWDRS - - Yes Yes - - - -
CPU2.SCCRESET - - Yes Yes - - - -
CPU2.HWBISTRS - - Yes - - - - -
ECAT_RESET_OUT Yes Yes Yes Yes Yes - Hi-Z Yes
TRSTn - - - - - Yes - -
(1)
CM subsystem resets are described in Section 41.2

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NOTE: After a reset, the reset cause register (RESC) is updated with the reset cause. The bits in
this register maintain their state across multiple resets. These can only be cleared by a
power-on reset (POR) or by writing '1' to the corresponding bit in RESCCLR register (status
can be cleared by writing '1' to RESC register bits also). Each CPU has its own RESC
register, referred to as CPU1.RESC and CPU2.RESC.

The resets can be divided into a few groups:

• Chip-level resets (XRSn, POR, CPU1.WDRS, and CPU1.NMIWDRS, SIMRESET.XRSn,
ECAT_RESET_OUT (if enabled) ), which reset all or almost all of the device.
• System resets (CPU1.SYSRS and CPU1.SCCRESET, SIMRESET.CPU1RSn), which reset a large
subset of the device but maintain some system-level configuration.
• CPU2 subsystem resets (CPU2.SYSRS, CPU2.WDRS, CPU2.NMIWDRS, and CPU2.SCCRESET),
which reset only CPU2 and its peripherals.
• Special resets (CPU1.HWBISTRS, CPU2.HWBISTRS, and TRSTn), which enable specific device
functions.
Whenever the CPU1 subsystem is reset, CPU2 as well as CM and their peripherals also get reset and
held in reset until CPU1 brings it out of reset by writing to the CPU2RESCTL and CMRESCTL register.
This is done by user application code on CPU1.
Many peripheral modules have individual resets accessible through the system control registers. For
information about a module's reset state, refer to the appropriate chapter for that module.
Note: After a POR the boot ROMs will clear all of the system and message RAMs on both CPUs.

3.3.2 External Reset (XRSn)

The external reset (XRS) is the main chip-level reset for the device. It resets both C28x CPUs , the CM
subsystem, all peripherals and I/O pin configurations, and most of the system control registers. It also
holds CPU2 and the CM subystem in reset. There is a dedicated open-drain pin for XRSn. This pin may
be used to drive reset pins for other ICs in the application, and may itself be driven by an external source.
The XRSn is driven internally during watchdog, NMI, and power-on resets.
The XRSn bit in the RESC register will be set whenever XRS is driven low for any reason. This bit is then
cleared by the boot ROM.

3.3.3 Simulate External Reset

In some cases user may need to simulate the external reset (XRS) in software. This can be done by
setting XRSn bit to '1' in SIMRESET register by CPU1 software. This toggles XRS pin hence resets full
device (just like external reset).
After this reset SIMRESET_XRSn bit in the RESC register will be set. Software can read this bit to know
the cause of reset and clear the status by writing '1' into corresponding bit in RESCCLR register.

3.3.4 Power-On Reset (POR)

The power-on reset (POR) circuit creates a clean reset throughout the device during power-up,
suppressing glitches on the GPIOs. The XRS pin is held low for the duration of the POR. In most
applications, XRS is held low long enough to reset other system ICs, but some applications may require a
longer pulse. In these cases, XRS can be driven low externally to provide the correct reset duration. A
POR resets everything that XRS does, along with a few other registers – the reset cause register (RESC),
the NMI shadow flag register (NMISHDFLG).
After a POR, the POR and XRSn bits in RESC are set. These bits are then cleared by the boot ROM.

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3.3.5 Debugger Reset (SYSRS)

During development, it is sometimes necessary to reset the CPU and its peripherals without disconnecting
the debugger or disrupting the system-level configuration. To facilitate this, each CPU has its own
subsystem reset, which can be triggered by a debugger using Code Composer Studio. CPU2's subsystem
reset (CPU2.SYSRS) resets only CPU2, its peripherals, and its clock gating and LPM configuration. It
does not hold CPU2 in reset. CPU1's subsystem reset (CPU1.SYSRS) resets CPU1, its peripherals, many
system control registers (including its clock gating and LPM configuration and the peripherals' CPU
ownership), and all I/O pin configurations. It also produces a CPU2.SYSRS and CM.RESETn and holds
both, CPU2 and CM, in reset (CCS Gel file may have code to release CPU2 and CM out of reset on
CPU1 debug reset).
Neither SYSRS resets the ICEPick debug module, the device capability registers, the clock source and
PLL configurations, the missing clock detection state, the PIE vector fetch error handler address, the NMI
flags, the analog trims, or anything reset only by a POR (see Section 3.3.4).

3.3.6 Simulate CPU1 Reset

In some cases user may need to simulate the CPU1 reset (CPU1.SYSRS) in software. This can be done
by setting CPU1RSn bit to '1' in SIMRESET register by CPU1 software. This toggles CPU1.SYSRS
signals hence resetting CPU1 as well as CPU2 and CM subsystem (just like the debugger reset).
After this reset SIMRESET_CPU1RSn bit in the RESC register will be set. Software can read this bit to
know the cause of reset and clear the status by writing '1' into corresponding bit in RESCCLR register.

3.3.7 Watchdog Reset (WDRS)

Each CPU has a watchdog timer that can optionally trigger a reset that lasts for 512 INTOSC1 cycles.
CPU1's watchdog reset (CPU1.WDRS) produces an XRS. CPU2's watchdog reset (CPU2.WDRS)
produces a CPU2.SYSRS and triggers an NMI on CPU1.
After a watchdog reset, the WDRSn bit in RESC is set. Software can read this bit to know the cause of
reset and clear the status by writing '1' into corresponding bit in RESCCLR register.

3.3.8 NMI Watchdog Reset (NMIWDRS)

Each CPU has a non-maskable interrupt (NMI) module that detects hardware errors in the system. Each
NMI module has a watchdog timer that triggers a reset if the CPU does not respond to an error within a
user-specified amount of time. CPU1's NMI watchdog reset (CPU1.NMIWDRS) produces an XRS. CPU2's
NMI watchdog reset (CPU2.NMIWDRS) produces a CPU2.SYSRS and triggers an NMI on CPU1.
After an NMI watchdog reset, the NMIWDRSn bit in RESC is set.

3.3.9 Secure Code Copy Reset (SCCRESET)

Dual-zone Code Security Module (DCSM) on this device locks read access to secure memories of each
CPU subsystem. To facilitate CRC checks and copying of CLA code, TI provides ROM functions to
securely access those memory areas. To prevent security breaches, interrupts must be disabled before
calling these functions. If a vector fetch occurs in a secure copy or CRC function, the DCSM triggers a
reset. CPU1's security reset (CPU1.SCCRESET) is similar to a CPU1.SYSRS, and CPU2's security reset
(CPU2.SCCRESET) is similar to a CPU2.SYSRS. However, the security reset also resets the debug logic
to deny access to a potential attacker.
After a security reset, the SCCRESETn bit in RESC is set. Software can read this bit to know the cause of
reset and clear the status by writing '1' into corresponding bit in RESCCLR register.

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3.3.10 ESC Reset Output

The user can configure the EtherCAT Slave Controller module to drive the XRSn pin low whenever the
ESC module receives a reset. This is done by setting the DEVICE_RESET_EN bit to '1' in the
ECAT_RESET_DEST_CONFIG register of the ESC module (EtherCAT subsystem). By default this is not
enabled. Since this toggles the XRSn pin, all effects of an external XRSn reset take effect.
After an ECAT_RESET_OUT reset, the ECAT_RESET_OUT bit in RESC is set. Software can read this bit
to know the cause of reset and clear the status by writing '1' into corresponding bit in RESCCLR register.

3.3.11 Test Reset (TRST)

The ICEPick debug module and associated JTAG logic has its own reset (TRST) which is controlled by a
dedicated pin. This reset is normally active unless the user connects a debugger to the device. For more
information on the debug module, see the TI Processors Wiki page on ICEPick:
http://processors.wiki.ti.com/index.php/ICEPICK.
The TRST does not have a normal RESC bit, but the TRSTn_pin_status bit indicates the state of the pin.

3.4 Peripheral Interrupts

This section explains the peripheral interrupt handling on the device. Non-maskable interrupts are covered
in Section 3.5. Software interrupts and emulation interrupts are not covered in this document. For
information on those, see the TMS320C28x CPU and Instruction Set Reference Guide.

3.4.1 Interrupt Concepts

An interrupt is a signal that causes the CPU to pause its current execution and branch to a different piece
of code known as an interrupt service routine (ISR). This is a useful mechanism for handling peripheral
events, and involves less CPU overhead or program complexity than register polling. However, because
interrupts are asynchronous to the program flow, care must be taken to avoid conflicts over resources that
are accessed both in interrupts and in the main program code.
Interrupts propagate to the CPU through a series of flag and enable registers. The flag registers store the
interrupt until it is processed. The enable registers block the propagation of the interrupt. When an
interrupt signal reaches the CPU, the CPU fetches the appropriate ISR address from a list called the
vector table.

3.4.2 Interrupt Architecture

The C28x CPU has fourteen peripheral interrupt lines. Two of them (INT13 and INT14) are connected
directly to CPU timers 1 and 2, respectively. The remaining twelve are connected to peripheral interrupt
signals through the enhanced Peripheral Interrupt Expansion module (ePIE, or PIE as a shortened
version). The PIE multiplexes up to sixteen peripheral interrupts into each CPU interrupt line. It also
expands the vector table to allow each interrupt to have its own ISR. This allows the CPU to support a
large number of peripherals.
An interrupt path is divided into three stages – the peripheral, the PIE, and the CPU. Each stage has its
own enable and flag registers. This system allows the CPU to handle one interrupt while others are
pending, implement and prioritize nested interrupts in software, and disable interrupts during certain
critical tasks.
Figure 3-1 shows the interrupt architecture for this device.

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Figure 3-1. Device Interrupt Architecture

CM_STATUS

SYS_ERR

CPU1.CRC
CPU1.CLA1.CRC
CPU1.TINT0
CPU1.TIMER0
CPU1.LPMINT CPU1.NMIWD
LPM Logic CPU1.WAKEINT
CPU1.WD NMI
CPU1.WDINT CMNMIWDRSn CPU1
CPU1
ePIE

INPUTXBAR4 CPU1.XINT1 Control INT1

GPIO0
INPUTXBAR5 CPU1.XINT2 Control To
GPIO1 Input INT12
... INPUTXBAR6 CPU1.XINT3 Control
X-Bar
... INPUTXBAR13 CPU1.XINT4 Control
GPIOx
INPUTXBAR14 CPU1.XINT5 Control CPU1.TINT1
CPU1.TIMER1 INT13
CPU1.TINT2
IPC CPU1.TIMER2 INT14
4 CPU-to-CPU
8 CM-to-CPU
Interrupts

Peripherals

CPU2.NMIWD NMI

CPU2
CPU2.XINT1 Control
CPU2.XINT2 Control INT1
To
CPU2.XINT3 Control INT12
CPU2.XINT4 Control
CPU2.XINT5 Control CPU2
ePIE CPU2.TINT1
CPU2.LPMINT CPU2.TIMER1 INT13
LPM Logic CPU2.WAKEINT
CPU2.TINT2
CPU2.WD CPU2.TIMER2 INT14
CPU2.WDINT
CPU2.TINT0
CPU2.TIMER0

CPU2.CRC
CPU2.CLA1.CRC

SYS_ERR

3.4.2.1 Peripheral Stage

Each peripheral has its own unique interrupt configuration, which is described in that peripheral's chapter.
Some peripherals allow multiple events to trigger the same interrupt signal. For example, a
communications peripheral might use the same interrupt to indicate that data has been received or that
there has been a transmission error. The cause of the interrupt can be determined by reading the
peripheral's status register. Often, the bits in the status register must be cleared manually before another
interrupt will be generated.

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3.4.2.2 PIE Stage

The PIE provides individual flag and enable register bits for each of the peripheral interrupt signals, which
are sometimes called PIE channels. These channels are grouped according to their associated CPU
interrupt. Each PIE group has one 16-bit enable register (PIEIERx), one 16-bit flag register (PIEIFRx), and
one bit in the PIE acknowledge register (PIEACK). The PIEACK register bit acts as a common interrupt
mask for the entire PIE group.
When the CPU receives an interrupt, it fetches the address of the ISR from the PIE. The PIE returns the
vector for the lowest-numbered channel in the group that is both flagged and enabled. This gives lower-
numbered interrupts a higher priority when multiple interrupts are pending.
If no interrupt is both flagged and enabled, the PIE returns the vector for channel 1. This condition will not
happen unless software changes the state of the PIE while an interrupt is propagating. Section 3.4.4
contains procedures for safely modifying the PIE configuration once interrupts have been enabled.

3.4.2.3 CPU Stage

Like the PIE, the CPU provides flag and enable register bits for each of its interrupts. There is one enable
register (IER) and one flag register (IFR), both of which are internal CPU registers. There is also a global
interrupt mask, which is controlled by the INTM bit in the ST1 register. This mask can be set and cleared
using the CPU's SETC instruction. In C code, C2000Ware's DINT and EINT macros can be used for this
purpose.
Writes to IER and INTM are atomic operations. In particular, if INTM is cleared, the next instruction in the
pipeline will run with interrupts disabled. No software delays are needed.

3.4.2.4 Dual-CPU Interrupt Handling

Each CPU has its own PIE. Both PIEs must be configured independently.
Some interrupts come from shared peripherals that can be owned by either CPU, such as the ADCs and
SPIs. These interrupts are sent to both PIEs regardless of the ownership of the peripheral. Thus, a
peripheral owned by one CPU can cause an interrupt on the other CPU, if that interrupt is enabled in the
other CPU's PIE.

3.4.3 Interrupt Entry Sequence

Figure 3-2 shows how peripheral interrupts propagate to the CPU.

Figure 3-2. Interrupt Propagation Path

PIEIERx.1
0
Peripheral
PIEIFRx.1 1
Interrupt
Latch
A

PIEIERx.2
Peripheral 0 Set
PIEIFRx.2 1 PIEACK.x IER.x ST1.INTM
Interrupt
Latch 1 0 1
CPU
B 0 IFR.x 1 0
Interrupt
Latch
Logic

PIEIERx.16
0
Peripheral
PIEIFRx.16 1
Interrupt
Latch
P

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When a peripheral generates an interrupt (on PIE group x, channel y), it triggers the following sequence of
events:
1. The interrupt is latched in PIEIFRx.y.
2. If PIEIERx.y is set, the interrupt propagates.
3. If PIEACK.x is clear, the interrupt propagates and PIEACK.x is set.
4. The interrupt is latched in IFR.x.
5. If IER.x is set, the interrupt propagates.
6. If INTM is clear, the CPU receives the interrupt.
7. Any instructions in the D2 or later stage of the pipeline are run to completion. Instructions in earlier
stages are flushed.
8. The CPU saves its context on the stack.
9. IFR.x and IER.x are cleared. INTM is set. EALLOW is cleared.
10. The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared.
11. The CPU branches to the ISR.
The interrupt latency is the time between PIEIFRx.y latching the interrupt and the first ISR instruction
entering the execution stage of the CPU pipeline. The minimum interrupt latency is 14 SYSCLK cycles.
Wait states on the ISR or stack memories will add to the latency. External interrupts add a minimum of two
SYSCLK cycles for GPIO synchronization plus extra time for input qualification (if used). Loops created
using the C28x RPT instruction cannot be interrupted.

3.4.4 Configuring and Using Interrupts

At power-up, no interrupts are enabled by default. The PIEIER and IER registers are cleared and INTM is
set. The application code is responsible for configuring and enabling all peripheral interrupts.

3.4.4.1 Enabling Interrupts

To enable a peripheral interrupt, perform the following steps:
1. Disable interrupts globally (DINT or SETC INTM).
2. Enable the PIE by setting the ENPIE bit of the PIECTRL register.
3. Write the ISR vector for each interrupt to the appropriate location in the PIE vector table, which can be
found in Table 3-2.
4. Set the appropriate PIEIERx bit for each interrupt. The PIE group and channel assignments can be
found in Table 3-2.
5. Set the CPU IER bit for any PIE group containing enabled interrupts.
6. Enable the interrupt in the peripheral.
7. Enable interrupts globally (EINT or CLRC INTM).
Step 4 does not apply to the Timer1 and Timer2 interrupts, which connect directly to the CPU.

3.4.4.2 Handling Interrupts

ISRs are similar to normal functions, but must do the following:
1. Save and restore the state of certain CPU registers (if used).
2. Clear the PIEACK bit for the interrupt group.
3. Return using the IRET instruction.
Requirements 1 and 3 are handled automatically by the TMS320C28x C compiler if the function is defined
using the __interrupt keyword. For information on this keyword, see the Keywords section of the
TMS320C28x Optimizing C/C++ Compiler v6.2.4 User's Guide. For information on writing assembly code
to handle interrupts, see the Standard Operation for Maskable Interrupts section of the TMS320C28x CPU
and Instruction Set Reference Guide.

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The PIEACK bit for the interrupt group must be cleared manually in user code. This is normally done at
the end of the ISR. If the PIEACK bit is not cleared, the CPU will not receive any further interrupts from
that group. This does not apply to the Timer1 and Timer2 interrupts, which do not go through the PIE.

3.4.4.3 Disabling Interrupts

To disable all interrupts, set the CPU's global interrupt mask via DINT or SETC INTM. It is not necessary
to add NOPs after setting INTM or modifying IER – the next instruction will execute with interrupts
disabled.
Individual interrupts can be disabled using the PIEIERx registers, but care must be taken to avoid race
conditions. If an interrupt signal is already propagating when the PIEIER write completes, it may reach the
CPU and trigger a spurious interrupt condition. To avoid this, use the following procedure:
1. Disable interrupts globally (DINT or SETC INTM).
2. Clear the PIEIER bit for the interrupt.
3. Wait 5 cycles to make sure that any propagating interrupt has reached the CPU IFR register.
4. Clear the CPU IFR bit for the interrupt's PIE group.
5. Clear the PIEACK bit for the interrupt's PIE group.
6. Enable interrupts globally (EINT or CLRC INTM).
Interrupt groups can be disabled using the CPU IER register. This cannot cause a race condition, so no
special procedure is needed.
PIEIFR bits must never be cleared in software since the read/modify/write operation may cause incoming
interrupts to be lost. The only safe way to clear a PIEIFR bit is to have the CPU take the interrupt. The
following procedure can be used to bypass the normal ISR:
1. Disable interrupts globally (DINT or SETC INTM).
2. Modify the PIE vector table to map the PIEIFR bit's interrupt vector to an empty ISR. This ISR will only
contain a return from interrupt instruction (IRET).
3. Disable the interrupt in the peripheral registers.
4. Enable interrupts globally (EINT or CLRC INTM).
5. Wait for the pending interrupt to be serviced by the empty ISR.
6. Disable interrupts globally.
7. Modify the PIE vector table to map the interrupt vector back to its original ISR.
8. Clear the PIEACK bit for the interrupt's PIE group.
9. Enable interrupts globally.

3.4.4.4 Nesting Interrupts

By default, interrupts do not nest. It is possible to nest and prioritize interrupts via software control of the
IER and PIEIERx registers. Documentation and example code can be found in C2000Ware and on the TI
Processors wiki: http://processors.wiki.ti.com/index.php/Interrupt_Nesting_on_C28x

3.4.5 PIE Channel Mapping

Table 3-2 shows the PIE group and channel assignments for each peripheral interrupt. Each row is a
group, and each column is a channel within that group. When multiple interrupts are pending, the lowest-
numbered channel in the lowest-numbered group is serviced first. Thus, the interrupts at the top of the
table have the highest priority, and the interrupts at the bottom have the lowest priority.

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Table 3-2. PIE Channel Mapping

INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 INTx.9 INTx.10 INTx.11 INTx.12 INTx.13 INTx.14 INTx.15 INTx.16
INT1.y ADCA1 ADCB1 ADCC1 XINT1 XINT2 ADCD1 TIMER0 WAKE/ I2CA SYS_ ECAT ECAT CIPC0 CIPC1 CIPC2 CIPC3
WDINT ERR SYNC0 INTn
(CPU1 only) (CPU1 only)
INT2.y EPWM1_ EPWM2_ EPWM3_ EPWM4_ EPWM5_ EPWM6_ EPWM7_ EPWM8_ EPWM9_ EPWM10_ EPWM11_ EPWM12_ EPWM13_ EPWM14_ EPWM15_ EPWM16_
TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ
INT3.y EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 EPWM7 EPWM8 EPWM9 EPWM10 EPWM11 EPWM12 EPWM13 EPWM14 EPWM15 EPWM16
INT4.y ECAP1 ECAP2 ECAP3 ECAP4 ECAP5 ECAP6 ECAP7 - FSITXA_ FSITXA_ FSITXB_ FSITXB_ FSIRXA_ FSIRXA_ FSIRXB_ FSIRXB_
INT1 INT2 INT1 INT2 INT1 INT2 INT1 INT2
INT5.y EQEP1 EQEP2 EQEP3 - CLB1 CLB2 CLB3 CLB4 SDFM1 SDFM2 ECAT ECAT SDFM1 SDFM1 SDFM1 SDFM1
RSTINTn SYNC1 DR1 DR2 DR3 DR4
(CPU1 only) (CPU1 only)
INT6.y SPIA_RX SPIA_TX SPIB_RX SPIB_TX MCBSPA_ MCBSPA_ MCBSPB_ MCBSPB_ SPIC_RX SPIC_TX SPID_RX SPID_TX SDFM2 SDFM2 SDFM2 SDFM2
RX TX RX TX DR1 DR2 DR3 DR4
INT7.y DMA_CH1 DMA_CH2 DMA_CH3 DMA_CH4 DMA_CH5 DMA_CH6 - - FSIRXC_ FSIRXC_ FSIRXD_ FSIRXD_ FSIRXE_ FSIRXE_ FSIRXF_ FSIRXF_
INT1 INT2 INT1 INT2 INT1 INT2 INT1 INT2
INT8.y I2CA I2CA_ I2CB I2CB_ SCIC_RX SCIC_TX SCID_RX SCID_TX FSIRXG_ FSIRXG_ FSIRXH_ FSIRXH_ CLB5 CLB6 CLB7 CLB8
FIFO FIFO INT1 INT2 INT1 INT2
INT9.y SCIA_RX SCIA_TX SCIB_RX SCIB_TX CANA_0 CANA_1 CANB_0 CANB_1 - - - - PMBUSA CM_ USBA -
STATUS (CPU1 only)
(CPU1 only)
INT10.y ADCA_ ADCA2 ADCA3 ADCA4 ADCB_ ADCB2 ADCB3 ADCB4 ADCC_EVT ADCC2 ADCC3 ADCC4 ADCD_EVT ADCD2 ADCD3 ADCD4
EVT EVT
INT11.y CLA1_1 CLA1_2 CLA1_3 CLA1_4 CLA1_5 CLA1_6 CLA1_7 CLA1_8 CMTOCPUx CMTOCPUx CMTOCPUx CMTOCPUx CMTOCPUx CMTOCPUx CMTOCPUx CMTOCPUx
IPCINTR0 IPCINTR1 IPCINTR2 IPCINTR3 IPCINTR4 IPCINTR5 IPCINTR6 IPCINTR7
INT12.y XINT3 XINT4 XINT5 MPOST FMC. VCU FPU FPU - ECAP6 ECAP7 - CPUxCRC_ CLA1CRC_ CLA CLA
DONE OVER UNDER INT2 INT2 INT INT OVER UNDER
FLOW FLOW FLOW FLOW
Note: Cells marked "-" are Reserved. CPUx is CPU1 for CPU1 PIE and CPU2 for CPU2 PIE.

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3.4.5.1 PIE Interrupt Priority

3.4.5.1.1 Channel Priority

For every PIE group, the low number channels in the group have the highest priority. For instance in PIE
group 1, channel 1.1 has priority over channel 1.3. If those two enabled interrupts occurred
simultaneously, channel 1.1 will be serviced first with channel 1.3 left pending. Once the ISR for channel
1.1 completes and provided there are no other enabled and pending interrupts for PIE group 1, channel
1.3 will be serviced. However, for the CPU to service any more interrupts from a PIE group, PIEACK for
the group must be cleared. For this specific example, in order for channel 1.3 to be serviced, channel 1.1’s
ISR has to clear PIEACK for group 1.
The following example describes an alternative scenario: channel 1.1 is currently being serviced by the
CPU, channel 1.3 is pending and before channel 1.1’s ISR completes, channel 1.2 which is enabled also
comes in. Since channel 1.2 has a higher priority than channel 1.3, the CPU will service channel 1.2 and
channel 1.3 will still be left pending. Using the steps from the Interrupt Entry Sequence (Section 3.4.3),
channel 1.2 interrupt can happen as late as step 10 (The CPU fetches the ISR vector from the PIE.
PIEIFRx.y is cleared) and it will still be serviced ahead of channel 1.3.

3.4.5.1.2 Group Priority

Generally, the lowest channel in the lowest PIE group has the highest priority. An example of this is
channels 1.1 and 2.1. Those two channels have the highest priority in their respective groups. If the
interrupts for those two enabled channels happened simultaneously and provided there are no other
enabled and pending interrupts, channel 1.1 will be serviced first by the CPU with channel 2.1 left
pending.
However, there are cases where channel priority supersedes group priority. This special case happens
depending on which step the CPU is currently at in the Interrupt Entry Sequence (Section 3.4.3).
The following illustrates an example of this special case.
The CPU is about to service channel 2.3 and is currently going through the steps in the Interrupt Entry
Sequence (Section 3.4.3).
1. As the CPU reaches step 10 (The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared), two
enabled interrupts: channel 1.1 and channel 2.1 come in.
2. Due to channel priority, channel 2.1 will be serviced ahead of channel 2.3. However, group priority
dictates that channel 1.1 be serviced ahead of channels 2.1 and 2.3.
3. Channel priority supersedes here and channel 2.1 will be serviced ahead of 1.1 and 2.3.
4. After channel 2.1 completes, channel 1.1 is serviced followed by channel 2.3.
Group priority is only guaranteed if no interrupts are currently being serviced, that is, the Interrupt Entry
Sequence (Section 3.4.3) is not executing.

3.4.6 System Error and CM Status Interrupts

SYS_ERR and CM_STATUS consolidate several sources of interrupts. These sources set the respective
bit in the SYS_ERR_INT_FLG and CM_STATUS_INT_FLG registers. Any set bit in the
SYS_ERR_INT_FLG and CM_STATUS_INT_FLG registers will also set the GINT (Global Interrupt) bit.
GINT has to be cleared before anymore SYS_ERR or CM_STATUS interrupts are generated. If GINT is
cleared with the source flags still set, another SYS_ERR or CM_STATUS interrupt will be fired, therefore it
is recommended to clear the source flags before clearing GINT.
Figure 3-3 shows the sources for SYS_ERR and CM_STATUS interrupts.

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Figure 3-3. System Error and CM Status Interrupt Sources

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3.4.7 Vector Tables

Table 3-3 shows the CPU interrupt vector table. The vectors for INT1 – INT12 are not used in this device.
The reset vector is fetched from the boot ROM instead of from this table.

Table 3-3. CPU Interrupt Vectors

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
Priority
Reset 0 0x0000 0D00 2 Reset is always fetched from 1 (Highest) -
location 0x003F_FFC0 in Boot
ROM
INT1 1 0x0000 0D02 2 Not used. See PIE Group 1 5 -
INT2 2 0x0000 0D04 2 Not used. See PIE Group 2 6 -
INT3 3 0x0000 0D06 2 Not used. See PIE Group 3 7 -
INT4 4 0x0000 0D08 2 Not used. See PIE Group 4 8 -
INT5 5 0x0000 0D0A 2 Not used. See PIE Group 5 9 -
INT6 6 0x0000 0D0C 2 Not used. See PIE Group 6 10 -
INT7 7 0x0000 0D0E 2 Not used. See PIE Group 7 11 -
INT8 8 0x0000 0D10 2 Not used. See PIE Group 8 12 -
INT9 9 0x0000 0D12 2 Not used. See PIE Group 9 13 -
INT10 10 0x0000 0D14 2 Not used. See PIE Group 10 14 -
INT11 11 0x0000 0D16 2 Not used. See PIE Group 11 15 -
INT12 12 0x0000 0D18 2 Not used. See PIE Group 12 16 -
INT13 13 0x0000 0D1A 2 CPU TIMER1 Interrupt 17 -
INT14 14 0x0000 0D1C 2 CPU TIMER2 Interrupt 18 -
(for TI/RTOS use)
DATALOG 15 0x0000 0D1E 2 CPU Data Logging Interrupt 19 (lowest) -
RTOSINT 16 0x0000 0D20 2 CPU Real-Time OS Interrupt 4 -
EMUINT 17 0x0000 0D22 2 CPU Emulation Interrupt 2 -
NMI 18 0x0000 0D24 2 Non-Maskable Interrupt 3 -
ILLEGAL 19 0x0000 0D26 2 Illegal Instruction (ITRAP) - -
USER 1 20 0x0000 0D28 2 User-Defined Trap - -
USER 2 21 0x0000 0D2A 2 User-Defined Trap - -
USER 3 22 0x0000 0D2C 2 User-Defined Trap - -
USER 4 23 0x0000 0D2E 2 User-Defined Trap - -
USER 5 24 0x0000 0D30 2 User-Defined Trap - -
USER 6 25 0x0000 0D32 2 User-Defined Trap - -
USER 7 26 0x0000 0D34 2 User-Defined Trap - -
USER 8 27 0x0000 0D36 2 User-Defined Trap - -
USER 9 28 0x0000 0D38 2 User-Defined Trap - -
USER 10 29 0x0000 0D3A 2 User-Defined Trap - -
USER 11 30 0x0000 0D3C 2 User-Defined Trap - -
USER 12 31 0x0000 0D3E 2 User-Defined Trap - -

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Table 3-4 shows the PIE vector table.

Table 3-4. PIE Interrupt Vectors

Name Vector ID Address Size (x16) Description Core ePIE Group
Priority Priority
PIE Group 1 Vectors - Muxed into CPU INT1
INT1.1 32 0x0000 0D40 2 ADCA1 interrupt 5 1 (Highest)
INT1.2 33 0x0000 0D42 2 ADCB1 interrupt 5 2
INT1.3 34 0x0000 0D44 2 ADCC1 interrupt 5 3
INT1.4 35 0x0000 0D46 2 XINT1 interrupt 5 4
INT1.5 36 0x0000 0D48 2 XINT2 interrupt 5 5
INT1.6 37 0x0000 0D4A 2 ADCD1 interrupt 5 6
INT1.7 38 0x0000 0D4C 2 TIMER0 interrupt 5 7
INT1.8 39 0x0000 0D4E 2 WAKE/WD interrupt 5 8
INT1.9 128 0x0000 0E00 2 I2CA interrupt 5 9
INT1.10 129 0x0000 0E02 2 SYS_ERR interrupt 5 10
INT1.11 130 0x0000 0E04 2 ECAT SYNC0 interrupt 5 11
(CPU1 only)
INT1.12 131 0x0000 0E06 2 ECAT interrupt n 5 12
(CPU1 only)
INT1.13 132 0x0000 0E08 2 CIPC0 interrupt 5 13
INT1.14 133 0x0000 0E0A 2 CIPC1 interrupt 5 14
INT1.15 134 0x0000 0E0C 2 CIPC2 interrupt 5 15
INT1.16 135 0x0000 0E0E 2 CIPC3 interrupt 5 16 (Lowest)
PIE Group 2 Vectors - Muxed into CPU INT2
INT2.1 40 0x0000 0D50 2 EPWM1_TZ interrupt 6 1 (Highest)
INT2.2 41 0x0000 0D52 2 EPWM2_TZ interrupt 6 2
INT2.3 42 0x0000 0D54 2 EPWM3_TZ interrupt 6 3
INT2.4 43 0x0000 0D56 2 EPWM4_TZ interrupt 6 4
INT2.5 44 0x0000 0D58 2 EPWM5_TZ interrupt 6 5
INT2.6 45 0x0000 0D5A 2 EPWM6_TZ interrupt 6 6
INT2.7 46 0x0000 0D5C 2 EPWM7_TZ interrupt 6 7
INT2.8 47 0x0000 0D5E 2 EPWM8_TZ interrupt 6 8
INT2.9 136 0x0000 0E10 2 EPWM9_TZ interrupt 6 9
INT2.10 137 0x0000 0E12 2 EPWM10_TZ interrupt 6 10
INT2.11 138 0x0000 0E14 2 EPWM11_TZ interrupt 6 11
INT2.12 139 0x0000 0E16 2 EPWM12_TZ interrupt 6 12
INT2.13 140 0x0000 0E18 2 EPWM13_TZ interrupt 6 13
INT2.14 141 0x0000 0E1A 2 EPWM14_TZ interrupt 6 14
INT2.15 142 0x0000 0E1C 2 EPWM15_TZ interrupt 6 15
INT2.16 143 0x0000 0E1E 2 EPWM16_TZ interrupt 6 16 (Lowest)
PIE Group 3 Vectors - Muxed into CPU INT3
INT3.1 48 0x0000 0D60 2 EPWM1 interrupt 7 1 (Highest)
INT3.2 49 0x0000 0D62 2 EPWM2 interrupt 7 2
INT3.3 50 0x0000 0D64 2 EPWM3 interrupt 7 3
INT3.4 51 0x0000 0D66 2 EPWM4 interrupt 7 4
INT3.5 52 0x0000 0D68 2 EPWM5 interrupt 7 5
INT3.6 53 0x0000 0D6A 2 EPWM6 interrupt 7 6
INT3.7 54 0x0000 0D6C 2 EPWM7 interrupt 7 7
INT3.8 55 0x0000 0D6E 2 EPWM8 interrupt 7 8
INT3.9 144 0x0000 0E20 2 EPWM9 interrupt 7 9

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Table 3-4. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core ePIE Group
Priority Priority
INT3.10 145 0x0000 0E22 2 EPWM10 interrupt 7 10
INT3.11 146 0x0000 0E24 2 EPWM11 interrupt 7 11
INT3.12 147 0x0000 0E26 2 EPWM12 interrupt 7 12
INT3.13 148 0x0000 0E28 2 EPWM13 interrupt 7 13
INT3.14 149 0x0000 0E2A 2 EPWM14 interrupt 7 14
INT3.15 150 0x0000 0E2C 2 EPWM15 interrupt 7 15
INT3.16 151 0x0000 0E2E 2 EPWM16 interrupt 7 16 (Lowest)
PIE Group 4 Vectors - Muxed into CPU INT4
INT4.1 56 0x0000 0D70 2 ECAP1 interrupt 8 1 (Highest)
INT4.2 57 0x0000 0D72 2 ECAP2 interrupt 8 2
INT4.3 58 0x0000 0D74 2 ECAP3 interrupt 8 3
INT4.4 59 0x0000 0D76 2 ECAP4 interrupt 8 4
INT4.5 60 0x0000 0D78 2 ECAP5 interrupt 8 5
INT4.6 61 0x0000 0D7A 2 ECAP6 interrupt 8 6
INT4.7 62 0x0000 0D7C 2 ECAP7 interrupt 8 7
INT4.8 63 0x0000 0D7E 2 Reserved 8 8
INT4.9 152 0x0000 0E30 2 FSITXA interrupt 1 8 9
INT4.10 153 0x0000 0E32 2 FSITXA interrupt 2 8 10
INT4.11 154 0x0000 0E34 2 FSITXB interrupt 1 8 11
INT4.12 155 0x0000 0E36 2 FSITXB interrupt 2 8 12
INT4.13 156 0x0000 0E38 2 FSIRXA interrupt 1 8 13
INT4.14 157 0x0000 0E3A 2 FSIRXA interrupt 2 8 14
INT4.15 158 0x0000 0E3C 2 FSIRXB interrupt 1 8 15
INT4.16 159 0x0000 0E3E 2 FSIRXB interrupt 2 8 16 (Lowest)
PIE Group 5 Vectors - Muxed into CPU INT5
INT5.1 64 0x0000 0D80 2 EQEP1 interrupt 9 1 (Highest)
INT5.2 65 0x0000 0D82 2 EQEP2 interrupt 9 2
INT5.3 66 0x0000 0D84 2 EQEP3 interrupt 9 3
INT5.4 67 0x0000 0D86 2 Reserved 9 4
INT5.5 68 0x0000 0D88 2 CLB1 interrupt 9 5
INT5.6 69 0x0000 0D8A 2 CLB2 interrupt 9 6
INT5.7 70 0x0000 0D8C 2 CLB3 interrupt 9 7
INT5.8 71 0x0000 0D8E 2 CLB4 interrupt 9 8
INT5.9 160 0x0000 0E40 2 SDFM1 interrupt 9 9
INT5.10 161 0x0000 0E42 2 SDFM2 interrupt 9 10
INT5.11 162 0x0000 0E44 2 ECATRST interrupt n 9 11
(CPU1 only)
INT5.12 163 0x0000 0E46 2 ECATSYNC1 interrupt 9 12
(CPU1 only)
INT5.13 164 0x0000 0E48 2 SDFM1DR1 interrupt 9 13
INT5.14 165 0x0000 0E4A 2 SDFM1DR2 interrupt 9 14
INT5.15 166 0x0000 0E4C 2 SDFM1DR3 interrupt 9 15
INT5.16 167 0x0000 0E4E 2 SDFM1DR4 interrupt 9 16 (Lowest)
PIE Group 6 Vectors - Muxed into CPU INT6
INT6.1 72 0x0000 0D90 2 SPIA_RX interrupt 10 1 (Highest)
INT6.2 73 0x0000 0D92 2 SPIA_TX interrupt 10 2
INT6.3 74 0x0000 0D94 2 SPIB_RX interrupt 10 3

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Table 3-4. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core ePIE Group
Priority Priority
INT6.4 75 0x0000 0D96 2 SPIB_TX interrupt 10 4
INT6.5 76 0x0000 0D98 2 MCBSPA_RX interrupt 10 5
INT6.6 77 0x0000 0D9A 2 MCBSPA_TX interrupt 10 6
INT6.7 78 0x0000 0D9C 2 MCBSPB_RX interrupt 10 7
INT6.8 79 0x0000 0D9E 2 MCBSPB_TX interrupt 10 8
INT6.9 168 0x0000 0E50 2 SPIC_RX interrupt 10 9
INT6.10 169 0x0000 0E52 2 SPIC_TX interrupt 10 10
INT6.11 170 0x0000 0E54 2 SPID_RX interrupt 10 11
INT6.12 171 0x0000 0E56 2 SPID_TX interrupt 10 12
INT6.13 172 0x0000 0E58 2 SDFM2DR1 interrupt 10 13
INT6.14 173 0x0000 0E5A 2 SDFM2DR2 interrupt 10 14
INT6.15 174 0x0000 0E5C 2 SDFM2DR3 interrupt 10 15
INT6.16 175 0x0000 0E5E 2 SDFM2DR4 interrupt 10 16 (Lowest)
PIE Group 7 Vectors - Muxed into CPU INT7
INT7.1 80 0x0000 0DA0 2 DMA_CH1 interrupt 11 1 (Highest)
INT7.2 81 0x0000 0DA2 2 DMA_CH2 interrupt 11 2
INT7.3 82 0x0000 0DA4 2 DMA_CH3 interrupt 11 3
INT7.4 83 0x0000 0DA6 2 DMA_CH4 interrupt 11 4
INT7.5 84 0x0000 0DA8 2 DMA_CH5 interrupt 11 5
INT7.6 85 0x0000 0DAA 2 DMA_CH6 interrupt 11 6
INT7.7 86 0x0000 0DAC 2 Reserved 11 7
INT7.8 87 0x0000 0DAE 2 Reserved 11 8
INT7.9 176 0x0000 0E60 2 FSIRXC interrupt 1 11 9
INT7.10 177 0x0000 0E62 2 FSIRXC interrupt 2 11 10
INT7.11 178 0x0000 0E64 2 FSIRXD interrupt 1 11 11
INT7.12 179 0x0000 0E66 2 FSIRXD interrupt 2 11 12
INT7.13 180 0x0000 0E68 2 FSIRXE interrupt 1 11 13
INT7.14 181 0x0000 0E6A 2 FSIRXE interrupt 2 11 14
INT7.15 182 0x0000 0E6C 2 FSIRXF interrupt 1 11 15
INT7.16 183 0x0000 0E6E 2 FSIRXF interrupt 2 11 16 (Lowest)
PIE Group 8 Vectors - Muxed into CPU INT8
INT8.1 88 0x0000 0DB0 2 I2CA interrupt 12 1 (Highest)
INT8.2 89 0x0000 0DB2 2 I2CA_FIFO interrupt 12 2
INT8.3 90 0x0000 0DB4 2 I2CB interrupt 12 3
INT8.4 91 0x0000 0DB6 2 I2CB_FIFO interrupt 12 4
INT8.5 92 0x0000 0DB8 2 SCIC_RX interrupt 12 5
INT8.6 93 0x0000 0DBA 2 SCIC_TX interrupt 12 6
INT8.7 94 0x0000 0DBC 2 SCID_RX interrupt 12 7
INT8.8 95 0x0000 0DBE 2 SCID_TX interrupt 12 8
INT8.9 184 0x0000 0E70 2 FSIRXG interrupt 1 12 9
INT8.10 185 0x0000 0E72 2 FSIRXG interrupt 2 12 10
INT8.11 186 0x0000 0E74 2 FSIRXH interrupt 1 12 11
INT8.12 187 0x0000 0E76 2 FSIRXH interrupt 2 12 12
INT8.13 188 0x0000 0E78 2 CLB5 interrupt 12 13
INT8.14 189 0x0000 0E7A 2 CLB6 interrupt 12 14
INT8.15 190 0x0000 0E7C 2 CLB7 interrupt 12 15
INT8.16 191 0x0000 0E7E 2 CLB8 interrupt 12 16 (Lowest)

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Table 3-4. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core ePIE Group
Priority Priority
PIE Group 9 Vectors - Muxed into CPU INT9
INT9.1 96 0x0000 0DC0 2 SCIA_RX interrupt 13 1 (Highest)
INT9.2 97 0x0000 0DC2 2 SCIA_TX interrupt 13 2
INT9.3 98 0x0000 0DC4 2 SCIB_RX interrupt 13 3
INT9.4 99 0x0000 0DC6 2 SCIB_TX interrupt 13 4
INT9.5 100 0x0000 0DC8 2 CANA interrupt 0 13 5
INT9.6 101 0x0000 0DCA 2 CANA interrupt 1 13 6
INT9.7 102 0x0000 0DCC 2 CANB interrupt 0 13 7
INT9.8 103 0x0000 0DCE 2 CANB interrupt 1 13 8
INT9.9 192 0x0000 0E80 2 Reserved 13 9
INT9.10 193 0x0000 0E82 2 Reserved 13 10
INT9.11 194 0x0000 0E84 2 Reserved 13 11
INT9.12 195 0x0000 0E86 2 Reserved 13 12
INT9.13 196 0x0000 0E88 2 PMBUSA interrupt 13 13
INT9.14 197 0x0000 0E8A 2 CM_STATUS interrupt 13 14
(CPU1 only)
INT9.15 198 0x0000 0E8C 2 USBA interrupt 13 15
(CPU1 only)
INT9.16 199 0x0000 0E8E 2 Reserved 13 16 (Lowest)
PIE Group 10 Vectors - Muxed into CPU INT10
INT10.1 104 0x0000 0DD0 2 ADCA_EVT interrupt 14 1 (Highest)
INT10.2 105 0x0000 0DD2 2 ADCA2 interrupt 14 2
INT10.3 106 0x0000 0DD4 2 ADCA3 interrupt 14 3
INT10.4 107 0x0000 0DD6 2 ADCA4 interrupt 14 4
INT10.5 108 0x0000 0DD8 2 ADCB_EVT interrupt 14 5
INT10.6 109 0x0000 0DDA 2 ADCB2 interrupt 14 6
INT10.7 110 0x0000 0DDC 2 ADCB3 interrupt 14 7
INT10.8 111 0x0000 0DDE 2 ADCB4 interrupt 14 8
INT10.9 200 0x0000 0E90 2 ADCC_EVT interrupt 14 9
INT10.10 201 0x0000 0E92 2 ADCC2 interrupt 14 10
INT10.11 202 0x0000 0E94 2 ADCC3 interrupt 14 11
INT10.12 203 0x0000 0E96 2 ADCC4 interrupt 14 12
INT10.13 204 0x0000 0E98 2 ADCD_EVT interrupt 14 13
INT10.14 205 0x0000 0E9A 2 ADCD2 interrupt 14 14
INT10.15 206 0x0000 0E9C 2 ADCD3 interrupt 14 15
INT10.16 207 0x0000 0E9E 2 ADCD4 interrupt 14 16 (Lowest)
PIE Group 11 Vectors - Muxed into CPU INT11
INT11.1 112 0x0000 0DE0 2 CLA1_1 interrupt 15 1 (Highest)
INT11.2 113 0x0000 0DE2 2 CLA1_2 interrupt 15 2
INT11.3 114 0x0000 0DE4 2 CLA1_3 interrupt 15 3
INT11.4 115 0x0000 0DE6 2 CLA1_4 interrupt 15 4
INT11.5 116 0x0000 0DE8 2 CLA1_5 interrupt 15 5
INT11.6 117 0x0000 0DEA 2 CLA1_6 interrupt 15 6
INT11.7 118 0x0000 0DEC 2 CLA1_7 interrupt 15 7
INT11.8 119 0x0000 0DEE 2 CLA1_8 interrupt 15 8
INT11.9 208 0x0000 0EA0 2 CMTOCPUx IPC interrupt 0 15 9
INT11.10 209 0x0000 0EA2 2 CMTOCPUx IPC interrupt 1 15 10

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Table 3-4. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core ePIE Group
Priority Priority
INT11.11 210 0x0000 0EA4 2 CMTOCPUx IPC interrupt 2 15 11
INT11.12 211 0x0000 0EA6 2 CMTOCPUx IPC interrupt 3 15 12
INT11.13 212 0x0000 0EA8 2 CMTOCPUx IPC interrupt 4 15 13
INT11.14 213 0x0000 0EAA 2 CMTOCPUx IPC interrupt 5 15 14
INT11.15 214 0x0000 0EAC 2 CMTOCPUx IPC interrupt 6 15 15
INT11.16 215 0x0000 0EAE 2 CMTOCPUx IPC interrupt 7 15 16 (Lowest)
PIE Group 12 Vectors - Muxed into CPU INT12
INT12.1 120 0x0000 0DF0 2 XINT3 interrupt 16 1 (Highest)
INT12.2 121 0x0000 0DF2 2 XINT4 interrupt 16 2
INT12.3 122 0x0000 0DF4 2 XINT5 interrupt 16 3
INT12.4 123 0x0000 0DF6 2 MPOST interrupt 16 4
INT12.5 124 0x0000 0DF8 2 FMC.DONE interrupt 16 5
INT12.6 125 0x0000 0DFA 2 VCU interrupt 16 6
INT12.7 126 0x0000 0DFC 2 FPU OVERFLOW interrupt 16 7
INT12.8 127 0x0000 0DFE 2 FPU UNDERFLOW interrupt 16 8
INT12.9 216 0x0000 0EB0 2 Reserved 16 9
INT12.10 217 0x0000 0EB2 2 ECAP6 interrupt 16 10
INT12.11 218 0x0000 0EB4 2 ECAP7 interrupt 16 11
INT12.12 219 0x0000 0EB6 2 Reserved 16 12
INT12.13 220 0x0000 0EB8 2 CPUxCRC interrupt 16 13
INT12.14 221 0x0000 0EBA 2 CLA1CRC interrupt 16 14
INT12.15 222 0x0000 0EBC 2 CLA OVERFLOW interrupt 16 15
INT12.16 223 0x0000 0EBE 2 CLA UNDERFLOW interrupt 16 16 (Lowest)

3.5 Exceptions and Non-Maskable Interrupts

This section describes system-level error conditions that can trigger a non-maskable interrupt (NMI). The
interrupt allows the application to respond to the error.

3.5.1 Configuring and Using NMIs

Each CPU subsystem has its own NMI module. This section will provide detail of NMI on C28x
subsystems. An incoming NMI sets a status bit in the NMIFLG register and starts the NMI watchdog
counter. This counter is clocked by the SYSCLK, and if it reaches the value programmed in NMIWDPRD
register, it triggers an NMI watchdog reset (NMIWDRS). To prevent this, the NMI handler must clear the
flag bit using the NMIFLGCLR register. Once all flag bits are clear, the NMIINT bit in the NMIFLG register
should be cleared to allow future NMIs to be taken.
The NMI module is enabled by the boot ROM during the startup process. To respond to NMIs, an NMI
handler vector must be written to the PIE vector table.

3.5.2 Emulation Considerations

The NMI watchdog counter behaves as follows under debug conditions:

CPU Suspended When the CPU is suspended, the NMI watchdog counter will
be suspended.
Run-Free Mode When the CPU is placed in run-free mode, the NMI watchdog
counter will resume operation as normal.

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Real-Time Single-Step Mode When the CPU is in real-time single-step mode, the NMI
watchdog counter will be suspended. The counter remains
suspended even within real-time interrupts.
Real-Time Run-Free Mode When the CPU is in real-time run-free mode, the NMI
watchdog counter operates as normal.

3.5.3 NMI Sources

There are several types of hardware errors that can trigger an NMI. Additional information about the error
is usually available from the module that detects it.

3.5.3.1 Missing Clock Detection

The missing clock detection logic monitors OSCCLK for failure. If the OSCCLK source stops, the PLL is
bypassed, OSCCLK is connected to INTOSC1, and NMIs are fired to both CPUs. For more information on
missing clock detection, see Section 3.6.2.

3.5.3.2 RAM Uncorrectable Error

A single-bit parity error, double-bit ECC data error, or single-bit ECC address error in a RAM read will
trigger an NMI. This applies to CPU, CLA, and DMA reads. Single-bit ECC data errors do not trigger an
NMI, but can optionally trigger a normal peripheral interrupt. For more information on RAM error detection,
see Section 3.12.1.9.

3.5.3.3 Flash Uncorrectable ECC Error

A double-bit ECC data error or single-bit ECC address error in a flash read will trigger an NMI. Single-bit
ECC data errors do not trigger an NMI, but can optionally trigger a normal peripheral interrupt.

3.5.3.4 ROM Uncorrectable Error

On this device ROM has a parity feature and a parity mismatch during read or execution will trigger an
NMI.

3.5.3.5 NMI Vector Fetch Mismatch

Each CPU's Peripheral Interrupt Expansion module (PIE) has redundant vector tables. If a mismatch in
these tables is detected during a vector fetch, a user-specified error handler is run instead of the ISR. If
the vector fetch was caused by an NMI, a second NMI is fired to the other CPU. Mismatches for other
interrupts do not trigger an NMI. For more information about the vector address check, see Section 3.6.3.

3.5.3.6 CPU2 Watchdog or NMI Watchdog Reset

A watchdog reset or NMI watchdog reset on CPU2 will trigger an NMI on CPU1. Since a CPU1 reset also
resets CPU2, this NMI source is not available on CPU2. Watchdog interrupts do not trigger an NMI.

3.5.3.7 CM NMI Watchdog Reset

A NMI watchdog reset on CM can generate NMI on CPU1. To enable this feature user need to set
CMNMIWDRST configuration bit in CMTOCPU1NMICTL register.

3.5.3.8 EtherCAT Reset out

A reset out from EtherCAT module can generate NMI on CPU1. To enable this feature user need to set
CPU_NMI_EN configuration bit in ESCSS_RESET_DEST_CONFIG register.

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3.5.3.9 CRC Fail

A CRC fail result from BGCRC module can generate NMI to respective CPU. By default this NMI is
enable. To disable this feature user need to configure NMIDIS configuration field in BGCRC_CTRL1
register with value "1010".

3.5.3.10 ERAD NMI

ERAD module can generate NMI based on different events which user can configure in ERAD.

3.5.4 Illegal Instruction Trap (ITRAP)

If the CPU tries to execute an illegal instruction, it generates a special interrupt called an illegal instruction
trap (ITRAP). This interrupt is non-maskable and has its own vector in the PIE vector table. For more
information about ITRAPs, see the Illegal-Instruction Trap section of the TMS320C28x DSP CPU and
Instruction Set Reference Guide.

NOTE: A RAM fetch access violation will trigger an ITRAP in addition to the normal peripheral
interrupt for RAM access violations. The CPU will handle the ITRAP first.

3.6 Safety Features

This section gives details on features that monitor device operation during run-time to detect any error in
operation.

3.6.1 Write Protection on Registers

3.6.1.1 LOCK Protection on System Configuration Registers

Several system configuration registers are protected from spurious CPU writes by “LOCK” registers. Once
these associated LOCK register bits are set the respective locked registers can no longer be modified by
software. See specific register descriptions for details.

3.6.1.2 EALLOW Protection

Several control registers are protected from spurious CPU writes by the EALLOW protection mechanism.
The EALLOW bit in status register 1 (ST1) indicates the state of protection as shown in Table 3-5.

Table 3-5. Access to EALLOW-Protected Registers

EALLOW Bit CPU Writes CPU Reads JTAG Writes JTAG Reads
0 Ignored Allowed Allowed (1) Allowed
1 Allowed Allowed Allowed Allowed
(1)
The EALLOW bit is overridden via the JTAG port, allowing full access of protected registers during debug from the Code
Composer Studio interface.

At reset, the EALLOW bit is cleared, enabling EALLOW protection. While protected, all writes to protected
registers by the CPU are ignored and only CPU reads, JTAG reads, and JTAG writes are allowed. If this
bit is set, by executing the EALLOW instruction, the CPU is allowed to write freely to protected registers.
After modifying registers, they can once again be protected by executing the EDIS instruction to clear the
EALLOW bit.

3.6.2 Missing Clock Detection Logic

The missing clock detect (MCD) logic detects OSCCLK failure, using INTOSC1 as the reference clock
source. This circuit only detects complete loss of OSCCLK and doesn’t do any detection of frequency drift
on the OSCCLK.
This circuit monitors the OSCLK (primary clock) using the 10 MHz clock provided by the INTOSC1
(secondary clock) as a backup clock. This circuit functions as:
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1. The primary clock (OSCCLK) clock keeps ticking a 7-bit counter (named as MCDPCNT). This counter
is asynchronously reset with XRSn.
2. The secondary clock (INTOSC1) clock keeps ticking a 13-bit counter (named as MCDSCNT). This
counter is asynchronously reset with XRSn.
3. Each time MCDPCNT overflows, the MCDSCNT counter is reset. Thus, if OSCCLK is present or not
slower than INTOSC1 by a factor of 64, MCDSCNT will never overflow.
4. If OSCCLK stops for some reason, or is slower than INTOSC1 by at least a factor of 64, the
MCDSCNT will overflow and a missing clock condition will be detected on OSCCLK.
5. The above check is continuously active, unless the MCD is disabled using MCDCR register (by making
the MCLKOFF bit 1)
6. If the circuit ever detects a missing OSCCLK, the following occurs:
• The MCDSTS flag is set.
• The MCDSCNT counter is frozen to prevent further missing clock detection.
• The CLOCKFAIL signal goes high, which generates TRIP events to PWM modules and fires NMIs
to CPU1.NMIWD and CPU2.NMIWD.
• PLL is forcefully bypassed and OSCCLK source is switched to INTOSC1 (System Clock
Frequency = INTOSC1 Freq (10Mhz)/SYSDIV). PLLMULT is zeroed out automatically in this case.
• While the MCDSTS bit is set, the OSCCLKSRCSEL bits have no effect and OSCCLK is forcefully
connected to INTOSC1.
• PLLRAWCLK going to the system is switched to INTOSC1 automatically.
7. If the MCLKCLR bit is written (this is a W=1 bit), MCDSTS bit will be cleared and OSCCLK source will
be decided by the OSCCLKSRCSEL bits. Writing to MCLKCLR will also clear the MCDPCNT and
MCDSCNT counters to allow the circuit re-evaluate missing clock detection. If user wants to lock the
PLL after missing clock detection, he needs to first switch the clock source to INTOSC1 (using
OSCCLKSRCSEL register), do a MCLKCLR and re-lock the PLL.
8. The MCD is enabled at power up. There is no support for missing clock detection if INTOSC2 is failed
from the device power-up.
Figure 3-4 shows the missing clock logic functional flow.

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Figure 3-4. Missing Clock Detection Logic

Secondary Clock CLOCKFAIL

INTOSC1 Missing
Clock INTOSC1
Detect
Primary Clock (MCD)
Logic
Low
OSCCLK Power
INTOSC2 Source Mode
Select OSCCLK Ckt
Ckt
X1/X2

CLKSRCCTL1.OSCCLRSRCSEL /1,
Switch
SYSPLL /2,
Ckt
/4
Mux
PLLRAWCLK ..
(glitch- PLLSYSCLK
/124
PLL Locking free)
/126
Registers Control
Ckt

Clock Dividers

Clock Sources SYSPLLCTL1/2/3,

SYSPLLMULT,
SYSPLLSTS

NOTE: On a complete clock failure when OSCCLK is dead, it may take a maximum time of 8192
INTOSC1 cycles (that is, 0.8192 ms) before CLOCKFAIL signal goes high, after which:
• NMI is generated
• OSCCLK is switched to INTOSC1
• PWM Trip happens

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3.6.3 CPU1 and CPU2 ePIE Vector Address Validity Check

The ePIE vector table on each CPU is duplicated into these two parts:
• Main ePIE Vector Table mapped from 0xD00 to 0xEFF in the C28x memory space
• Redundant ePIE Vector Table mapped from 0x1000D00 to 0x1000EFF in the C28x memory space
Following is the behavior of accesses to the ePIE memories:
• Data Writes to Main Vector Table: Writes to both memories
• Data Writes to Redundant Vector Table: Writes only to the Redundant Vector Table
• Vector Fetch: Data from both the vector tables are compared
• Data Read: Can read the Main and Redundant vector table separately
On every vector fetch from the ePIE, a hardware comparison (no cycle penalty is incurred to do the
comparison) of both the vector table outputs is performed and if there is a mismatch between the two
vector table outputs, the following occurs:
1. If the PIEVERRADDR register (default value 0x3F FFFF) is not initialized, the default error handler at
address 0x3FFFBE gets executed.
But, when the PIEVERRADDR register is initialized to the address of the user-defined routine, the
user-defined routine is executed instead of the default error handler.
Note: Each CPU has its own copy of the PIE Vector Fetch Error Handler register
(CPU1.PIEVERRADDR and CPU2.PIEVERRADDR).
2. Hardware also generates EPWM Trip signals which will trip the PWM outputs using TRIPIN15.
3. An NMI to the other CPU is sent if the current mismatch is during a vector fetch. For example, on an
NMI vector fetch error for CPU2, an NMI is also fired to CPU1.NMIWD.
If there is no mismatch, the correct vector is jammed onto the C28 program control.

3.6.4 NMIWDs
Each CPU has user-programmable NMIWD period registers, in which users can set a limit on how much
time they want to allocate for the device to acknowledge the NMI. If the NMI is not acknowledged, it will
cause a device reset.

3.6.5 ECC and Parity Enabled RAMs, Shared RAMs Protection

Each CPU subsystem has different RAM blocks. Some RAM blocks are ECC-enabled and others are
parity-enabled. All single-bit errors in ECC RAM are auto-corrected and an error counter is incremented
every time a single bit error is detected. If the error counter reaches a predefined user configured limit, an
interrupt is generated to the corresponding CPU. Refer to Section 3.12 for more details on RAM errors.
All uncorrectable double-bit errors end up triggering an NMI to corresponding CPUs.

3.6.6 ECC Enabled Flash Memory

When ECC is programmed and enabled, flash single-bit errors are corrected automatically by ECC logic
before giving data to the CPU, but they are not corrected in flash memory. Flash memory will still contain
wrong data until another erase/program operation happens to correct the flash contents. Irrespective of
whether the error interrupt is enabled or disabled, single-bit errors are always corrected before giving data
to the CPU. When the interrupt is disabled, users can check the single-bit error counter register for any
single-bit error occurrences. The error counter stops incrementing once its value is equal to the
threshold+1. It is always suggested to set the threshold register to a non-zero value so that the error
counter can increment. It is up to the user to decide the threshold value at which they have to reprogram
the flash with the correct data.
When ECC is programmed and enabled, flash uncorrectable errors end up triggering an NMI to CPU1the
respective CPU. Refer to Section 3.12 for more details on flash error correction and error catching
mechanisms.

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3.6.7 ERRORSTS Pin

The ERRORSTS pin is an ‘always output’ pin and remains high until an error is detected inside the chip.
On an error, the ERRORSTS pin goes low (default polarity) until the corresponding internal error status
flag for that error source is cleared. Figure 3-5 shows the functionality of the ERRORSTS pin.
The ERRORSTS pin will be tri-stated until the chip power rails ramp up to the lower operational limit. As
the ERRORSTS pin is an active-low pin (default polarity), users who care about the state of this pin during
power-up should connect an external pull-down on this pin.
Following enhancement has been made on this device for ERRORSTS pin logic:
• Polarity of Error pin has been made configurable (default setting is active-low polarity).
• To enable testing of the Error pin, capability to force and clear the Error pin from software has been
provided.
• Additional sources of Error have been added to ERRORSTS:
– CPU1 Watchdog reset
– Error on a PIE vector fetch
– NMI on CM

Figure 3-5. ERRORSTS Pin Diagram

CPU1's NMIWD Shadow flags

CPU1.NMIWD.NMISHDFLG.Bit-0

CPU1.NMIWD.NMISHDFLG.Bit-1

CPU1.NMIWD.NMISHDFLG.Bit-15

CPU2's NMIWD Shadow flags

ERROR

CPU2.NMIWD.NMISHDFLG.Bit-0

CPU2.NMIWD.NMISHDFLG.Bit-1

CPU2.NMIWD.NMISHDFLG.Bit-15

3.7 Clocking
This section explains the clock sources and clock domains on this device, and how to configure them for
application use. Figure 3-6 provides an overview of the device's clocking system.

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Figure 3-6. Clocking System

AUXPLLCLKEN AUXCLKDIV

AUXOSCCLK AUX PLL

AUXCLK
SYSCLKDIVSEL Divider

AUXCLKSRCCEL
SYS
SYS PLL PLLRAWCLK Divider
AUXPLLRAWCLK
USBBITCLK

OSCCLKSRCSEL PLLCLKEN PLLSYSCLK

One per CMCLK peripheral

CMPCLKCRx.PERx
CMDIVSRCSEL
WDCLK PLLSYSCLK
CMCLK CMCLK
DIVSRCSEL
DIVIDER
NMIWDs
Watch Dog GSx RAMs
Timers GPIOs CPU1 CPU2 ETHERCATCLK
MSG RAMs CM.PERx.SYSCLK
IPC
XBARs ECATDIV ETHERCATCLK
CPU2.CPUCLK Divider
AnalogSubsys
SystemControl CM.PERx.SYSCLK
EMIF1 FPU
CPU1.CPUCLK TMU PHYCLKEN
VCRC
CPU1.SYSCLK Flash
FPU
DCSM /4
TMU
CPU2.SYSCLK MxRAM
VCRC CPUTIMERx DxRAM ETHERCAT PALLOCATE0
Flash DMA ETHERCATPHYCLK

CPU1.PERx.SYSCLK
CPUTIMERx BootROM .USB
DCSM CLA1
DMA HWBIST
HWBIST XINT CPU1.PCLKCRx
CLA1 USB
PIE
XINT
LSx RAM
PIE
MSG RAMs CPU1_CPU2_CM
LSx RAM
MxRAM .PERx.SYSCLK
MSG RAMs
DxRAM CPU2.PCLKCRx
BGCRC
BootROM
ERAD CPU2.PERx.SYSCLK
BGCRC
ERAD CANx
EMIF2 PALLOCATE0.CANx
WD
CPUSELx.CANx
CPU1.SYSCLK

CPU2.SYSCLK

X1 (XTAL)
One per SYSCLK peripheral
CPU2.PCLKCRx CPUSELx AUXCLKIN
One per LSPCLK peripheral
CANxBITCLK
CPUSELx CPU1.PCLKCRx

CANxBIT Clock
LSP CPU1.PCLKCRx
LSPCLKDIV PERx.SYSCLK
Divider
PLLSYSCLK

CPU2.PCLKCRx
PERx.SYSCLK
EPWMCLKDIV

/1 HRCAL
PERx.LSPCLK ECAPx
/2
EQEPx
One per ePWM peripheral SDFMx
McBSPx Bit CPU1.PCLKCRx SPIx
SPIx Bit Clock SCIx Bit Clock CPUSELx
Clock SCIx
McBSPx
EPWMCLK ADC
CMPSSx
DACx
CPU2.PCLKCRx ePWM FSIx
HRPWM I2C
HRCAL PMBUS
CPU1.PCLKCRx DCCx

HRCALCLK

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3.7.1 Clock Sources

The needs of the application are what ultimately determine the clock configuration. Specific concerns
such as application performance, power consumption, total system cost, and EMC are beyond the
scope of this document, but they should provide answers to the following questions:
1. What is the desired CPU frequency?
2. Are there any additional communication protocols or peripherals, such as CAN or USB, required?
3. What types of external oscillators or clock sources are available?
If CAN or USB is required, an external clock source with a precise frequency must be used as a
reference clock. Otherwise, it may be possible to use only INTOSC2 and avoid the need for more
external components.
All of the clocks in the device are derived from one of four clock sources.

3.7.1.1 Primary Internal Oscillator (INTOSC2)

At power-up, the device is clocked from an on-chip 10 MHz oscillator (INTOSC2). INTOSC2 is the primary
internal clock source, and is the default system clock at reset. It is used to run the boot ROM and can be
used as the system clock source for the application.

NOTE: INTOSC2's frequency tolerance is too loose to meet the timing requirements for some
peripherals such as CAN and USB, so an external clock must be used to support those
features.

3.7.1.2 Backup Internal Oscillator (INTOSC1)

The device also includes a redundant on-chip 10 MHz oscillator (INTOSC1). INTOSC1 is a backup clock
source that normally only clocks the watchdog timers and missing clock detection circuit (MCD). If MCD is
enabled and a missing system clock is detected, the system PLL is bypassed and all system clocks are
connected to INTOSC1 automatically. INTOSC1 may also be manually selected as the system and
auxiliary clock source for debug purposes.

3.7.1.3 External Oscillator (XTAL)

The dedicated X1 and X2 pins support an external clock source (XTAL), which can be used as the main
system and auxiliary clock source. Frequency limits and timing requirements can be found in the device
datasheet. Three types of external clock sources are supported:
• A single-ended 3.3V external clock. The clock signal should be connected to X1 while X2 is left
unconnected, as shown in Figure 3-7.

Figure 3-7. Single-ended 3.3V External Clock

VDDOSC X1 VSSOSC X2

3.3V NC
3.3V
Clk

VDD OUT

GND
3.3V Oscillator

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• An external crystal. The crystal should be connected across X1 and X2 with its load capacitors
connected to VSSOSC as shown in Figure 3-8.

Figure 3-8. External Crystal

VDDOSC X1 VSSOSC X2

3.3V
Crystal

RD CL2 CL1

• An external resonator. The resonator should be connected across X1 and X2 with its ground
connected to VSSOSC as shown in Figure 3-9.

Figure 3-9. External Resonator

VDDOSC X1 VSSOSC X2

3.3V

Resonator

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3.7.1.4 Auxiliary Clock Input (AUXCLKIN)

An additional external clock source is supported on GPIO133 (AUXCLKIN). This must be a single-ended
3.3V external clock. It can be used as the clock source for the USB, CAN, and Communication Manager
Subsystem. Frequency limits and timing requirements can be found in the device datasheet. The external
clock should be connected directly to the GPIO133 pin, as shown in Figure 3-10.

Figure 3-10. AUXCLKIN

Device

GPIO133_AUXCLKIN

CLK
3.3V

VDD OUT

GND
3.3V OSCILLATOR

3.7.2 Derived Clocks

The clock sources discussed in the previous section can be multiplied (via PLL) and divided down to
produce the desired clock frequencies for the application. This process produces a set of derived clocks,
which are described in this section.

3.7.2.1 Oscillator Clock (OSCCLK)

One of INTOSC2, XTAL, or INTOSC1 must be chosen to be the master reference clock (OSCCLK) for the
CPU and most of the peripherals. OSCCLK may be used directly or fed through the system PLL to reach
a higher frequency. At reset, OSCCLK is the default system clock, and is connected to INTOSC2.

3.7.2.2 System PLL Output Clock (PLLRAWCLK)

The system PLL allows the device to run at its maximum rated operating frequency, and in most
applications will generate the main system clock. This PLL uses OSCCLK as a reference, and features a
fractional multiplier and slip detection. For configuration instructions, see Section 3.7.6.

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3.7.2.3 Auxiliary Oscillator Clock (AUXOSCCLK)

One of INTOSC2, XTAL, or AUXCLKIN may be chosen to be the auxiliary reference clock (AUXOSCCLK)
for the USB module. (This selection does not affect the CAN bit clock, which uses AUXCLKIN directly).
AUXOSCCLK may be used directly or fed through the auxiliary PLL to reach a higher frequency. At reset,
AUXOSCCLK is connected to INTOSC2, but only an external oscillator can meet the USB timing
requirements.

3.7.2.4 Auxiliary PLL Output Clock (AUXPLLRAWCLK)

The auxiliary PLL is used to generate a clock for USB, CAN, EtherCAT, and the CM Subsystem. This PLL
uses AUXOSCCLK as a reference, and features slip detection. For configuration instructions, see
Section 3.7.6.

3.7.3 Device Clock Domains

The device clock domains feed the clock inputs of the various modules in the device. They are connected
to the derived clocks, either directly or through an additional divider.

3.7.3.1 System Clock (PLLSYSCLK)

The system control registers, GS RAMs, IPC module, GPIO qualification, and NMI watchdog timers have
their own clock domain (PLLSYSCLK). Despite the name, PLLSYSCLK may be connected to the system
PLL (PLLRAWCLK) or to OSCCLK. The chosen clock source is run through a frequency divider, which is
configured via the SYSCLKDIVSEL register.

3.7.3.2 CPU Clock (CPUCLK)

Each CPU has its own clock (CPU1.CPUCLK and CPU2.CPUCLK) which is used to clock the CPU, its
coprocessors, its private RAMs (M0, M1, D0, and D1), and its boot ROM and flash wrapper. This clock is
identical to PLLSYSCLK, but is gated when the CPU enters IDLE or STANDBY mode.

3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)

Each CPU provides a clock (CPU1.SYSCLK and CPU2.SYSCLK) to its CLA, DMA, and most owned
peripherals. This clock is identical to PLLSYSCLK, but is gated when the CPU enters STANDBY mode.
Each peripheral clock can be connected to either CPU1.SYSCLK or CPU2.SYSCLK. This selection is
made by CPU1 via the CPUSELx registers. Each peripheral clock also has its own independent clock
gating which is controlled by the CPU's PCLKCRx registers. By default, the ePWM, EMIF1, and EMIF2
clocks each have an additional /2 divider, which is required to support CPU frequencies over 100 MHz. At
slower CPU frequencies, these dividers can be disabled via the PERCLKDIVSEL register.

NOTE: Application needs to wait for 5 SYSCLK cycles after enabling clock to the peripherals when
using PCLKCRx.

3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)

The SCI, SPI, and McBSP modules can communicate at bit rates that are much slower than the CPU
frequency. These modules are connected to a shared clock divider, which generates a low-speed
peripheral clock (LSPCLK) derived from SYSCLK. LSPCLK uses a /4 divider by default, but the ratio can
be changed via the LOSPCP register. Each SCI, SPI, and McBSP module's clock (PERx.LSPCLK) can be
gated independently via the PCLKCRx registers.

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3.7.3.5 USB Auxiliary Clock (AUXPLLCLK)

The USB module requires a fixed 60 MHz clock for bit sampling. Since the main system clock is usually
not a multiple of 60 MHz, the correct frequency cannot be achieved with a simple divider. Instead, the
USB clock is provided through an auxiliary clock path (AUXPLLCLK), which can use an independent clock
source and PLL to generate the correct frequency.
USB clock tolerances are very tight. As stated in section 7.1.11 of the USB 2.0 specification, low-speed
devices (1.50 Mb/s) have a tolerance of +/- 1.5% , while high-speed devices (12.000 Mb/s) have a
tolerance of +/- 0.25%. Typically these tolerances are achieved by using an external crystal or resonator
as the source for AUXOSCCLK.

3.7.3.6 CAN Bit Clock

The required frequency tolerance for the CAN bit clock depends on the bit timing setup and network
configuration, and can be as tight as 0.1%. Since the main system clock (in the form of PERx.SYSCLK)
may not be precise enough, the bit clock can also be connected to XTAL or AUXCLKIN via the
CLKSRCCTL2 register. There is an independent selection for each CAN module.

3.7.3.7 CPU Timer2 Clock (TIMER2CLK)

CPU timers 0 and 1 are connected to PERx.SYSCLK. Timer 2 is connected to PERx.SYSCLK by default,
but may also be connected to INTOSC1, INTOSC2, XTAL, or AUXPLLCLK via the TMR2CLKCTL register.
This register also provides a separate pre-scale divider for timer 2. If a source other than SYSCLK is
used, the SYSCLK frequency must be at least twice the source frequency to ensure correct sampling.
Each CPU has its own independent CPU timers and TMR2CLKCTL register.
The main reason to use a non-SYSCLK source would be for internal frequency measurement. In most
applications, timer 2 will run off of the SYSCLK.

3.7.4 External Clock Output (XCLKOUT)

It is sometimes necessary to observe a clock directly for debug and testing purposes. The external clock
output (XCLKOUT) feature supports this by connecting a clock to an external pin, GPIO73. The available
clock sources are PLLSYSCLK, PLLRAWCLK, CPU1.SYSCLK, AUXPLLRAWCLK, CPU2.SYSCLK,
,INTOSC1, and INTOSC2.
To use XCLKOUT, first select the clock source via the CLKSRCCTL3 register. Next, select the desired
output divider via the XCLKOUTDIVSEL register. Finally, connect GPIO73 to mux channel 3 using the
GPIO configuration registers.

3.7.5 Clock Connectivity

Table 3-6 provide details on the clock connections of every module present in the device.

Table 3-6. Clock Connections Sorted by Clock Domain

Clock Domain CPU1 Subsystem CPU2 Subsystem Shared Modules
CPUx.CPUCLK CPU1 CPU2
CPU1VCU CPU2.VCU
CPU1.FPU CPU2.FPU
CPU1.TMU CPU2.TMU
CPU1.Flash CPU2.Flash
CPU1.DCSM CPU2.DCSM
CPU1.HWBIST CPU2.HWBIST

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Table 3-6. Clock Connections Sorted by Clock Domain (continued)

Clock Domain CPU1 Subsystem CPU2 Subsystem Shared Modules
CPUx.SYSCLK CPU1.ePIE CPU2.ePIE
CPU1.LS0 - LS7 RAMs CPU2.LS0 - LS7 RAMs
CPU1.M0 - M1 RAMs CPU2.M0 - M1 RAMs
CPU1.D0 - D1 RAMs CPU2.D0 - D1 RAMs
CPU1.BootROM CPU2.BootROM
CPU1.CLA1 Message RAMs CPU2.CLA1 Message RAMs
CPU1.Timer0-2 CPU2.Timer0-2
CPU1.DMA CPU2.DMA
CPU1.XINT CPU2.XINT
CPU1.CLA1 CPU2.CLA1
CPU1.BGCRC CPU2.BGCRC
CPU1.ERAD CPU2.ERAD
CPU1.CM Message RAMs CPU2.CM Message RAMs
EMIF2
PLLSYSCLK CPU1.NMIWD CPU2.NMIWD GS0 - GS15 RAMs
GPIO Input Sync and Qual
IPC
CPU1 & CPU2 MSG RAMs
XBARS
EMIF1
AnalogSubsys
EPWM
System Control Registers
PERx.SYSCLK USB ADC
CMPSS
DAC
ePWM & HRPWM
eCAP
eQEP
I2C
McBSP
SDFM
FSI
PMBUS
HRCAL
SPI
SCI
DCC
CAN
PERx.LSPCLK McBSP
SCI
SPI
CAN Bit Clock CAN
AUXPLLCLK USB
WDCLK (INTOSC1) CPU1.Watchdog CPU2.Watchdog

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3.7.6 PLL/AUXPLL
The PLL/AUXPLL is responsible for synthesizing an output frequency from the input clock (from the
oscillator); Figure 3-11 shows a simple block diagram of the PLL/AUXPLL. The PLL/AUXPLL divides the
reference input for a lower frequency input into the PLL/AUXPLL by (REFDIV+1). Then multiplies this
internal frequency by IMULT to get the VCO output clock. The PLL/AUXPLL output is divided by (ODIV+1)
to generate PLLRAWCLK/AUXPLLRAWCLK which is further divided by
SYSCLKDIVSEL.PLLSYSCLKDIV/AUXCLKDIVSEL.AUXPLLDIV to generate PLLSYSCLK/AUXCLK

Figure 3-11. PLL/AUXPLL

SYSPLL / AUXPLL

OSCCLK/ INTCLK/ VCOCLK/ PLLRAWCLK/

AUXOSCCLK ÷ AUXINTCLK AUXVCOCLK ÷ AUXPLLRAWCLK
VCO
(REFDIV+1) (ODIV+1)

÷
IMULT

B15%%.- +/7.6
fPLLRAWCLK = ×
(4'(&+8 +1) (1&+8 +1)

B#7: 15%%.- +/7.6

fAUXPLLRAWCLK = (4'(&+8 +1)
× (1&+8+1)

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3.7.6.1 Choosing PLL Settings

There are two PLLs (SYSPLL & AUXPLL) and equations shown in Figure 3-11 should be used to
configure respective PLL
IMULT is the integer value of the multiplier.
REFDIV is the reference divider for the OSCCLK/AUXOSCCLK.
ODIV is the output divider of the PLLRAWCLK/AUXPLLRAWCLK.
PLLSYSCLKDIV is the system clock divider.
AUXPLLDIV is the auxiliary clock divider.
For the permissible values of the multipliers and dividers, see the documentation for their respective
registers.
Many combinations of multiplier and divider can produce the same output frequency. However, the
product of the reference clock frequency and the multiplier (known as the VCO frequency) must be in the
range specified in the data manual.

NOTE: The system clock frequency (PLLSYSCLK) may not exceed the limit specified in the
datasheet. This limit does not allow for oscillator tolerance.

The clock source and PLL configuration registers are shared between the two CPUs (CPU1 and CPU2).
Register access is controlled by way of a semaphore, which is described in the Inter-Processor
Communication chapter.

3.7.6.2 System Clock Setup

Once the application requirements are understood, a specific clock configuration can be determined. The
default configuration is for INTOSC2 to be used as the system clock (PLLSYSCLK) with a divider of 1.
The following procedure should be used to set up the desired application configuration:
Refer to your device SysCtl_setClock() function inside C2000Ware installation for an example.
Recommended sequence to set up the system PLL:
a. Bypass the PLL by clearing SYSPLLCTL1[PLLCLKEN] and wait for at least 120 CPU clock cycles by
adding 120 NOP instructions.
b. Power down the PLL by writing to SYSPLLCTL1.PLLEN = 0 and wait for at least 60 CPU clock cycles
by adding 60 NOP instructions.
c. Select the reference clock source (OSCCLK) by writing to CLKSRCCTL1.OSCCLKSRCSEL and wait
for at least 300 CPU clock cycles by adding 300 NOP instructions.
d. Set the system clock divider to "/1" to ensure the fastest PLL configuration by clearing
SYSCLKDIVSEL[ PLLSYSCLKDIV].
e. Set the IMULT, REFDIV & ODIV simultaneously by writing 32-bit value in SYSPLLMULT at once. This
will automatically enable the PLL. Be sure the settings for multiplier and dividers do not violate the
frequency specifications as defined in the data sheet.
f. Wait for PLL to lock by polling for lock status bit to go high, that is, SYSPLLSTS.LOCKS = 1
g. Configure DCC with reference clock as OSCCLK and clock under measurement as PLLRAWCLK, and
verify the frequency of the PLL. If the frequency is out of range, do not enable PLLRAWCLK as
SYSCLK, stop here and troubleshoot. Refer to DCC chapter for more information on its configuration
and usage.
h. If the PLLRAWCLK is within the valid range, then set the system clock divider one setting higher than
the final desired value. For example ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1.
This limits the current increase when switching to the PLL.
i. Switch to the PLL as the system clock by setting SYSPLLCTL1[PLLCLKEN] and wait for
200 PLLSYSCLK cycles for current to stabilize by adding 200 NOP instructions.
j. Change the system clock divider (PLLSYSCLKDIV) to the appropriate value.

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NOTE:
1. SYSPLL must be bypassed and powered down manually before changing the OSCCLK
source.
2. At least 120 CPU clock cycles delay is needed after bypassing PLL, that is,
SYSPLLCTL1.PLLCLKEN=0.
3. At least 60 CPU clock cycles delay is needed after PLL is powered down, that is,
SYSPLLCTL1.PLLEN=0.
4. At least 300 CPU clock cycles delay is needed after OSSCLK source is changed.
5. PLL SLIP bit is not supported. DCC should be used to check the validity of the PLL
clock. This feature is included as part of SysCtl_setClock() function inside C2000Ware.

3.7.6.3 USB Auxiliary Clock Setup

Refer to your device SysCtl_setAuxClock() function inside C2000Ware installation for an example.
If USB functionality is needed, the auxiliary clock (AUXPLLCLK) must be configured to produce 60 MHz.
The procedure is similar to the system clock setup:
a. Bypass the PLL by clearing AUXPLLCTL1[PLLCLKEN] and wait for at least 120 CPU clock cycles by
adding 120 NOP instructions..
b. Powerdown the PLL by writing to AUXPLLCTL1.PLLEN=0 and wait for at least 60 CPU clock cycles by
adding 60 NOP instructions.
c. Select the reference clock source (AUXOSCCLK) by writing to CLKSRCCTL2.AUXOSCCLKSRCSEL
and wait for at least 60 CPU clock cycles by adding 60 NOP instructions.
d. Set the IMULT, REFDIV & ODIV simultaneously by writing 32-bit value in AUXPLLMULT at once. This
will automatically enable the PLL. Be sure the settings for multiplier and dividers do not violate the
frequency specifications as defined in the data sheet.
e. Wait for PLL to lock by polling for lock status bit to go high i.e. AUXPLLSTS.LOCKS=1
f. Configure DCC with reference clock as AUXOSCCLK and clock under measurement as
AUXPLLRAWCLK, and verify the frequency of the PLL. If the frequency is out of range, stop here and
troubleshoot. Refer to DCC chapter for more information on its configuration and usage.
g. Connect the auxiliary PLL output clock (AUXPLLRAWCLK) to AUXPLLCLK by writing a 1 to
AUXPLLCTL1.PLLCLKEN.
The auxiliary clock configuration can be changed at run time. Changing the AUXOSCCLK source will
automatically bypass the PLL and set the multiplier to zero. Changing the multiplier from one non-zero
value to another will temporarily bypass the PLL until it re-locks.

NOTE:
1. AUXPLL must be bypassed and powered down manually before changing the
AUXOSCCLK source.
2. At least 120 CPU clock cycles delay is needed after bypassing PLL, that is,
AUXPLLCTL1.PLLCLKEN=0.
3. At least 60 CPU clock cycles delay is needed after PLL is powered down, that is,
AUXPLLCTL1.PLLEN=0.
4. At least 60 CPU clock cycles delay is needed after AUXOSSCLK source is changed.
5. AUXPLL SLIP bit is not supported. DCC should be used to check the validity of the
AUXPLL clock. This feature is included as part of SysCtl_setAuxClock() function inside
C2000Ware.

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3.7.6.4 SYS PLL / AUX PLL Bypass

If application requires PLL clock to be bypassed from the system then it needs to configure
SYSPLLCTL1.PLLCLKEN=0 or AUXPLLCTL1.PLLCLKEN=0. It takes up to 120 CPU clock cycles before
the bypass is effective. In the meantime if PLLSYSCLKDIV / AUXPLLDIV is reduced to a lower value (for
example from /2 to /1 or /4 to /2 etc.) the device may be clocked above the maximum rated frequency and
can lead to unpredictable device behavior. Hence, delay of 120 CPU clock cycles is required after
bypassing the PLL from the enable state, that is, going from PLLCLKEN=1 to PLLCLKEN=0.

3.8 Clock Configuration Semaphore

Both CPUs can access the PLL and peripheral clock configuration registers. The clock configuration
semaphore allows one CPU to access the registers without being interrupted by the other CPU.
The clock configuration semaphore is implemented as a two-bit field in a register with special write
protections. This register requires a key field to be written at the same time as the semaphore bits. The
possible semaphore states are:

00 or 11 Either CPU may write to the semaphore. CPU1 has control of the clock
configuration registers by default. 00 is the reset state.
01 CPU2 has exclusive control of the clock configuration registers and exclusive write
access to the semaphore.
10 CPU1 has exclusive control of the clock configuration registers and exclusive write
access to the semaphore.

Each CPU is only allowed to take control of the clock configuration registers for itself. However, CPU1
may force both semaphores into the default state (00) at any time by putting CPU2 into reset. Figure 3-12
shows the allowed states and state transitions.

Figure 3-12. Clock Configuration Semaphore (CLKSEM) State Transitions

CPU1 should write 10 to gain CPU2 should write 01 to gain
mastership of the clock configuration Semaphore state 00 or 11 mastership of the clock configuration
registers. registers.
Clock configuration registers
are controlled by CPU1
CPU1 should write 00 to relinquish
Default at reset CPU2 should write 00 to relinquish
mastership once configuration is
mastership once configuration is
complete.
complete.

Semaphore state 10 Semaphore state 01

Not allowed
Clock configuration registers Clock configuration registers
are controlled by CPU1 Not allowed are controlled by CPU2

CPU2 cannot take control of the pump in this CPU1 cannot take control of the pump in this
state state

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3.9 32-Bit CPU Timers 0/1/2

This section describes the three 32-bit CPU-Timers (TIMER0/1/2) shown in Figure 3-13.
CPU-Timer2 is reserved for real-time operating system uses (for example, TI-RTOS) but if it is not used by
real-time operating systems then, CPU-Timer2 can also be used for other applications. The CPU-Timer0
and CPU-Timer1 run off of SYSCLK. The CPU-Timer2 normally runs off of SYSCLK, but can also use
INTOSC1, INTOSC2, XTAL, and AUXPLLCLK. The CPU-Timer interrupt signals (TINT0, TINT1, TINT2)
are connected as shown in Figure 3-14.

Figure 3-13. CPU-Timers

Reset
Timer reload

16-bit timer divide-down

32-bit timer period
TDDRH:TDDR
PRDH:PRD

16-bit prescale counter

SYSCLKOUT
PSCH:PSC
TCR.4 32-bit counter
(Timer start status) Borrow TIMH:TIM

Borrow

TINT

Figure 3-14. CPU-Timer Interrupts Signals and Output Signal

INT1 TINT0
to PIE TIMER0
INT12

28x
CPU
TINT1
INT13 TIMER1

TINT2
INT14 TIMER2

A The timer registers are connected to the memory bus of the C28x processor.
B The CPU Timers are synchronized to SYSCLKOUT.

The general operation of the CPU-Timer is as follows:

• The 32-bit counter register, TIMH:TIM, is loaded with the value in the period register PRDH:PRD.
• The counter decrements once every (TPR[TDDRH:TDDR]+1) SYSCLKOUT cycles, where
TDDRH:TDDR is the timer divider.
• When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse.
The registers listed in Section 6.8 are used to configure the timers.

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3.10 Watchdog Timers

The watchdog module generates an output pulse 512 watchdog clocks (WDCLKs) wide whenever the 8-
bit watchdog up counter has reached its maximum value. The watchdog clock source is INTOSC1.
Software must periodically write a 0x55 + 0xAA sequence into the watchdog key register to reset the
watchdog counter. The counter can also be disabled. Figure 3-15 shows the various functional blocks
within the watchdog module.

Figure 3-15. CPU Watchdog Timer Module

WDCR.WDPRECLKDIV WDCR.WDPS WDCR.WDDIS

WDCNTR

WDCLK 8-bit
(INTOSC1) WDCLK Watchdog Watchdog Overflow 1-count
Divider Prescaler Counter delay

SYSRSn
Clear
Count

WDWCR.MIN
WDKEY (7:0)
Out of Window Watchdog
Watchdog Good Key
Window
Key Detector Detector
WDCR(WDCHK(2:0))
55 + AA

Bad Key

WDRSTn Generate
1 0 1 512-WDCLK Watchdog Time-out
WDINTn Output Pulse

SCSR.WDENINT

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3.10.1 Servicing the Watchdog Timer

The watchdog counter (WDCNTR) is reset when the proper sequence is written to the WDKEY register
before the 8-bit watchdog counter overflows. The WDCNTR is reset-enabled when a value of 0x55 is
written to the WDKEY. When the next value written to the WDKEY register is 0xAA, then the WDCNTR is
reset. Any value written to the WDKEY other than 0x55 or 0xAA causes no action. Any sequence of 0x55
and 0xAA values can be written to the WDKEY without causing a system reset; only a write of 0x55
followed by a write of 0xAA to the WDKEY resets the WDCNTR.

Table 3-7. Example Watchdog Key Sequences

Step Value Written to WDKEY Result
1 0xAA No action
2 0xAA No action
3 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
4 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
5 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
6 0xAA WDCNTR is reset.
7 0xAA No action
8 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
9 0xAA WDCNTR is reset.
10 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
11 0x32 Improper value written to WDKEY.
No action, WDCNTR no longer enabled to be reset by next 0xAA.
12 0xAA No action due to previous invalid value.
13 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
14 0xAA WDCNTR is reset.

Step 3 in Table 3-7 is the first action that enables the WDCNTR to be reset. The WDCNTR is not actually
reset until step 6. Step 8 again re-enables the WDCNTR to be reset and step 9 resets the WDCNTR.
Step 10 again re-enables the WDCNTR to be reset. Writing the wrong key value to the WDKEY in step 11
causes no action, however the WDCNTR is no longer enabled to be reset and the 0xAA in step 12 now
has no effect.
If the watchdog is configured to reset the device, then a WDCNTR overflow or writing the incorrect value
to the WDCR[WDCHK] bits will reset the device and set the watchdog flag (WDRSn) in the reset cause
register (RESC). After a reset, the program can read the state of this flag to determine whether the reset
was caused by the watchdog. After doing this, the program should clear WDRSn to allow subsequent
watchdog resets to be detected. Watchdog resets are not prevented when the flag is set.

3.10.2 Minimum Window Check

To complement the timeout mechanism, the watchdog also contains an optional "windowing" feature that
requires a minimum delay between counter resets. This can help protect against error conditions that
bypass large parts of the normal program flow but still include watchdog handling.
To set the window minimum, write the desired minimum watchdog count to the WDWCR register. This
value will take effect after the next WDKEY sequence. From then on, any attempt to service the watchdog
when WDCNTR is less than WDWCR will trigger a watchdog interrupt or reset. When WDCNTR is greater
than or equal to WDWCR, the watchdog can be serviced normally.
At reset, the window minimum is zero, which disables the windowing feature.

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3.10.3 Watchdog Reset or Watchdog Interrupt Mode

The watchdog can be configured in the SCSR register to either reset the device (WDRST) or assert an
interrupt (WDINT) if the watchdog counter reaches its maximum value. The behavior of each condition is
described below:
• Reset mode:
If the watchdog is configured to reset the device, then the WDRST signal will pull the device reset
(XRS) pin low for 512 OSCCLK cycles when the watchdog counter reaches its maximum value.
• Interrupt mode:
When the watchdog counter expires, it will assert an interrupt by driving the WDINT signal low for 512
OSCCLK cycles. The falling edge of WDINT triggers a WAKEINT interrupt in the PIE if it is enabled.
Because the PIE is edge-triggered, re-enabling the WAKEINT while WDINT is active will not produce a
duplicate interrupt.
To avoid unexpected behavior, software should not change the configuration of the watchdog while
WDINT is active. For example, changing from interrupt mode to reset mode while WDINT is active will
immediately reset the device. Disabling the watchdog while WDINT is active will cause a duplicate
interrupt if the watchdog is later re-enabled. If a debug reset is issued while WDINT is active, the reset
cause register (RESC) will show a watchdog reset. The WDINTS bit in the SCSR register can be read
to determine the current state of WDINT.

3.10.4 Watchdog Operation in Low Power Modes

In IDLE mode, the watchdog interrupt (WDINT) signal can generate an interrupt to the CPU to take the
CPU out of IDLE mode. As with any other peripheral, the watchdog interrupt will trigger a WAKEINT
interrupt in the PIE during IDLE mode. User software must determine which peripheral caused the
interrupt.
In STANDBY mode, all of the clocks to the peripherals are turned off within the CPU subsystem. The only
peripheral that remains functional is the watchdog since the watchdog module runs off the oscillator clock
(OSCCLK). The WDINT signal is fed to the Low Power Modes (LPM) block so that it can be used to wake
the CPU from STANDBY low power mode. This feature is enabled by setting LPMCR.WDINTE = 1. See
Section 3.11 for details.
Note: If the watchdog interrupt is used to wake-up from an IDLE or STANDBY low power mode condition,
software must make sure that the WDINT signal goes back high before attempting to reenter the IDLE or
STANDBY mode. The WDINT signal will be held low for 512 OSCCLK cycles when the watchdog interrupt
is generated. The current state of WDINT can be determined by reading the watchdog interrupt status bit
(WDINTS) bit in the SCSR register. WDINTS follows the state of WDINT by two SYSCLKOUT cycles.

3.10.5 Emulation Considerations

The watchdog module behaves as follows under various debug conditions:

CPU Suspended: When the CPU is suspended, the watchdog clock (WDCLK) is
suspended
Run-Free Mode: When the CPU is placed in run-free mode, then the watchdog module
resumes operation as normal.
Real-Time Single-Step Mode: When the CPU is in real-time single-step mode, the watchdog clock
(WDCLK) is suspended. The watchdog remains suspended even
within real-time interrupts.
Real-Time Run-Free Mode: When the CPU is in real-time run-free mode, the watchdog operates
as normal.

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3.11 Low Power Modes

This device has two clock-gating, low-power modes. All low-power modes are entered by setting the
LPMCR register and executing the IDLE instruction. More information about this instruction can be found
in the TMS320C28x CPU and Instruction Set Reference Guide.
Low-power modes should not be entered into while a flash program or erase is ongoing.
The application should verify the following before entering STANDBY:
1. Check the value of the GPIODAT register of the pin selected for STANDBY(GPIOLPMSEL0/1) prior to
entering the Low-Power mode to ensure that the wake event has not already been asserted.
2. The LPMCR.QUALSTDBY register should be set to a value greater than the ratio of
INTOSC1/PLLSYSCLK to ensure proper wake up.

3.11.1 IDLE
IDLE is a standard feature of the C28x CPU. In this mode, the CPU clock is gated while all peripheral
clocks are left running. IDLE can thus be used to conserve power while a CPU is waiting for peripheral
events. When one CPU is in IDLE, there is no effect on the other CPU subsystem.
Any enabled interrupt will wake the CPU up from IDLE mode.
To enter IDLE mode, set LPMCR.LPM to 0x0 and execute the IDLE instruction.

3.11.2 STANDBY
STANDBY is a more aggressive low-power mode that gates both the CPU clock and any peripheral clocks
derived from the CPU's SYSCLK. The watchdog however, is left active. Like IDLE, this mode affects only
one CPU subsystem. The other CPU subsystem and all of its peripherals are unaffected. STANDBY is
best suited for an application where the wake-up signal will come from an external system (or CPU
subsystem) rather than a peripheral input.
An NMI (or optionally) a watchdog interrupt or a configured GPIO can wake the CPU from STANDBY
mode. Each GPIO from GPIO0-63 can be configured to wake the CPU when they are driven active low.
Upon wakeup, the CPU receives the WAKEINT interrupt if configured.
IPC interrupt 1 (flag 0), an NMI fired to the other CPU, or (optionally) a watchdog interrupt, will wake the
CPU subsystem up from STANDBY mode. Any of GPIO0-63 can also be configured to wake up the
subsystem when they are driven active low. Upon wakeup, the CPU receives a WAKEINT interrupt, even
if it was woken by an IPCINT1 signal.
To enter STANDBY mode:
1. Set LPMCR.LPM to 0x1.
2. Enable the WAKEINT interrupt in the PIE.
3. For watchdog interrupt wakeup, set LPMCR.WDINTE to 1 and configure the watchdog to generate
interrupts.
4. For GPIO wakeup, set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the LPM
module, and set LPMCR.QUALSTDBY to select the number of OSCCLK cycles for input qualification.
5. Execute the IDLE instruction to enter STANDBY.
To wake up from Standby mode:
1. Configure the desired GPIO to trigger the wakeup.
2. Drive the selected GPIO signal low; it must remain low for the number of OSCCLK cycles specified in
the QUALSTDBY bits in the LPMCR register. If the signal is sampled high during this period, the count
restarts.
At the end of the qualification period, the PLL enables the CLKIN to the CPU and the WAKEINT interrupt
is latched in the PIE block. The WAKEINT interrupt can also triggered by IPCINT1 sent from the other
CPU and a watchdog interrupt.
The CPU is now out of STANDBY mode and can resume normal execution.

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If CPU2 is in STANDBY mode, writing a 1 to the RESET bit of the CPU2RESCTL register will have no
effect. CPU2 may be reset by any Chip-level reset (POR, XRSn, CPU1.WDRSn, or CPU1.NMIWDRSn).
Alternately CPU2 may be woken up by any configured wake-up event.
If CPU2 is in STANDBY mode and the debugger is connected, executing a debug reset on CPU2 will
have no effect. In order to wake the CPU2 with the debugger, Click Run, Single Step, or Step over in the
Debug toolbar. CCS will prompt the user requesting to bring the CPU out of the low-power mode. Click
Yes. This will wake CPU2 from STANDBY and continue execution.

3.12 Memory Controller Module

This device has CPU1 subsystem, CPU2 subsystem and CM subsystem. This section will describe the
memory controller used for CPU1 and CPU2 subsystem.
The different RAMs available on CPU1 and CPU2 subsystem have different characteristics. Some are:
• Dedicated to each CPU (M0, M1, and Dx RAMs),
• Shared between the CPU and its own CLA (LSx RAM),
• Shared between the CPU and DMA of both subsystems (GSx RAM), and
• Used to send and receive messages between processors (MSGRAM).
• Used to exchange data between CLA and DMA
All these RAMs are highly configurable to achieve control for write access and fetch access from different
masters. There are also RAMs - called IPC MSGRAMs - that are used for interprocessor communication.
All RAMs are enabled with the ECC or parity feature (both data and address). Some of the dedicated
memories are secure memory as well. Refer to Section 6.1 for more details. Each RAM has its own
controller which takes care of the access protection/security related checks and ECC/Parity features for
that RAM. Figure 3-16 shows the configuration of these RAMs.

Figure 3-16. Memory Architecture

CPU1 LSx RAM GSx RAM CPU2 LSx RAM

CPU1 To CPU2 To
CPU1 CLA1 CPU1 CLA1 CPU2 CLA1 CPU2 CLA1
MSGRAM MSGRAM

CPU1 CLA1 To CPU2 CLA1 To

CPU1 MSGRAM CPU2 MSGRAM
CPU1 DMA CPU2 DMA
CPU1 CPU2

CPU1 M0 RAM CPU2 M0 RAM

CLA-DMA CPU2 TO CPU1 CLA-DMA

MSGRAM MSGRAM MSGRAM
CPU1 M1 RAM CPU2 M1 RAM

CPU1 TO CPU2
MSGRAM
CPU1 Dx RAM CPU2 Dx RAM

NOTE: All RAMs on these devices are SRAMs.

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3.12.1 Functional Description

This section further defines and discusses the dedicated RAMs, shared RAMs, and MSG RAMs on this
device.

3.12.1.1 Dedicated RAM (Dx RAM)

Each CPU subsystem has four dedicated RAM blocks: M0, M1, D0, and D1. M0/M1 memories are small
blocks of memory which are tightly coupled with the CPU. Only the CPU has access to these memories.
No other masters (including DMA) have any access to these memories.
All dedicated RAMs have the ECC feature. All dedicated memories are secure memory (except for
M0/M1) and have the access protection (CPU write protection/CPU fetch protection) feature. Each type of
access protection for each RAM block can be enabled/disabled by configuring the specific bit in the
access protection register, allocated to each subsystem (DxACCPROT).

3.12.1.2 Local Shared RAM (LSx RAM)

RAM blocks which are dedicated to each subsystem and are accessible to its CPU and CLA only, are
called local shared RAMs (LSx RAMs). All such memories are secure memory and have the ECC feature.
By default, these memories are dedicated to the CPU only, and the user could choose to share these
memories with the CLA by appropriately configuring the MSEL_LSx bit field in the LSxMSEL register.
Further, when these memories are shared between the CPU and CLA, the user could choose to use these
memories as CLA program memory by configuring the CLAPGM_LSx bit field in the LSxCLAPGM
registers. CPU access to all memory blocks, which are programmed as CLA program memory, are
blocked.
All these RAMs have the access protection (CPU write and CPU fetch) feature. Each type of access
protection for each RAM block can be enabled or disabled by configuring the specific bit in the local
shared RAM access protection registers, mapped to each CPU subsystem. Table 3-8 shows the LSx RAM
features.

Table 3-8. Local Shared RAM

MSEL_LSx CLAPGM_LSx CPUx Allowed CPUx.CLA1 Allowed Comment
Access Access
00 X All - LSx memory is configured as CPU dedicated RAM
01 0 All Data Read LSx memory is shared between CPU and CLA1
Data Write
01 1 Emulation Read Fetch Only LSx memory is CLA1 program memory
Emulation Write Emulation Read
Emulation Write

3.12.1.3 Global Shared RAM (GSx RAM)

RAM blocks that are accessible from both the CPU and their respective DMA are called global shared
RAMs (GSx RAMs). Each shared RAM can be owned by either CPU subsystem based on the
configuration of their respective bits (one bit for each GSx memory) in the GSxMSEL register. When a
particular GSx RAM block is owned by the CPU1 subsystem, CPU1 and CPU1.DMA have full access to
that RAM block, whereas CPU2 and CPU2.DMA have only read access to it (no fetch/write access).
Similarly, when a particular GSx RAM block is owned by the CPU2 subsystem, CPU1 and CPU1.DMA will
have only read access (no fetch/write access) to that RAM block, whereas CPU2 and CPU2.DMA will
have full access to it. Table 3-9 shows the features of the GSx RAM.

Table 3-9. Global Shared RAM

GSxMSEL CPU1 CPU1 CPU1 CPU1.DMA CPU1.DMA CPU2 CPU2 CPU2 CPU2.DMA CPU2.DMA
Fetch Read Write Read Write Fetch Read Write Read Write
0 Yes Yes Yes Yes Yes No Yes No Yes No
1 No Yes No Yes No Yes Yes Yes Yes Yes

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NOTE: Emulation/Debugger access is allowed from both the CPUs, irrespective of the GSxMSEL
setting.

Like other shared RAMs, these RAMs also have adifferent levels of access protection which can be
enabled or disabled by configuring specific bits in the GSxACCPROT registersmapped in each subsystem.
Master select and access protection configuration for each GSx RAM block can be individually locked by
the user to prevent further update to these bit fields. The user can also choose to permanently lock the
configuration to individual bit fields by setting the specific bit fields in the GSxCOMMIT register (refer to
the register description for more details). Once configuration is committed for a particular GSx RAM block,
it can not be changed further until CPUx.SYSRS is issued. Only the CPU1 SW can change the master
select configuration by writing into the GSxMSEL register, mapped on the CPU1. The GSxMSEL register,
which is mapped to the CPU2 subsystem, is a status register which can only be used by CPU2 SW to
know the master ownership for each GSx RAM block.

3.12.1.4 CPU Message RAM (CPU MSG RAM)

These RAM blocks can be used to share data between CPU1 and CPU2. Since these RAMs are used for
interprocessor communication, they are also called IPC RAMs. The CPU MSGRAMs have CPU and DMA
read and write access from its own CPU subsystem, and has CPU and DMA read only access from the
other subsystem.
This RAM has parity.

3.12.1.5 CLA Message RAM (CLA MSGRAM)

These RAM blocks can be used to share data between the CPU and CLA. The CLA has read and write
access to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA
MSGRAM." The CPU and CLA both have read access to both MSGRAMs.
This RAM has parity.

3.12.1.6 CLA-DMA MSG RAM

These RAMs blocks can be used to share data between CLA and DMA. The CLA has read and write
access to the "CLA to DMA MSGRAM." The DMA has read and write access to the "DMA to CLA
MSGRAM." The CLA and DMA both have read access to both MSGRAMs.

3.12.1.7 Access Arbitration

For a shared RAM, multiple accesses can happen at a given time. The maximum number of accesses to
any shared RAM at any given time depends on the type of shared RAM. On this device, a combination of
a fixed and round robin scheme is followed to arbitrate multiple access at any given time. Accesses from
the same masters are arbitrated in a fixed priority manner, but the accesses from different masters are
arbitrated using the round robin scheme.
The following is the order of fixed priority for CPU accesses:
1. Data Write/Program Write
2. Data Read
3. Program Read/Program Fetch
The following is the order of fixed priority for CLA accesses:
1. Data Write
2. Data Read/Program Fetch
Figure 3-17 represents the arbitration scheme on global shared memories:

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Figure 3-17. Arbitration Scheme on Global Shared Memories

Round Robin Arbitration

CPU1-DWRITE CPU1
Fixed Granted CPU1 Access
CPU1-DREAD Priority RR-CPU1
CPU1-PREAD/FETCH Arbiter

CPU1.DMA READ/WRITE

RR-CPU2.DMA RR-CPU1.DMA

CPU2-DWRITE
CPU2
CPU2-DREAD Fixed Granted CPU2 Access
Priority
CPU2-PREAD/FETCH Arbiter

RR-CPU2

CPU2.DMA READ/WRITE

Figure 3-18 represents the arbitration scheme on local shared memories.

Figure 3-18. Arbitration Scheme on Local Shared Memories

Round Robin Arbitration

CPU-DWRITE CPU
Fixed Granted CPU1 Access
CPU-DREAD
Priority
Arbiter RR-CPU
CPU-PREAD/FETCH

CLA-DWRITE CLA RR-CPU.CLA

Fixed
Priority Granted CLA Access
CLA-DREAD
Arbiter

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3.12.1.8 Access Protection

All RAM blocks on both subsystems have different levels of protection. This feature allows the user to
enable or disable specific access to individual RAM blocks from individual masters. There is no protection
for read accesses, hence reads are always allowed from all the masters which have access to that RAM
block.
The following sections describe the different kinds of protection available for RAM blocks on this device.
Note: For debug accesses, all the protections are disabled.

3.12.1.8.1 CPU Fetch Protection

A CPU has execution permission from a memory, only if that memory is dedicated to that CPU or its
respective subsystem is master for that memory (in case of GSx memory). When fetch accesses are
allowed based on the mastership, it can be further protected by setting the FETCHPROTx bit of the
specific register to ‘1.’ If fetch access is done by the CPU to a memory where CPU fetch protection is
enabled, a fetch protection violation occurs.
There are two types of fetch protection violations:
• Non-master CPU fetch protection violation
• Master CPU fetch protection violation
If a fetch access is made to a memory by a non-master CPU, it is called a non-master fetch protection
violation. If a fetch access is made to a dedicated or shared memory by the master CPU, and
FETCHPROTx is set to ‘1’ for that memory, the violation is called a master CPU fetch protection violation.
If a fetch protection violation occurs, it results in an ITRAP for CPU. A flag gets set into the appropriate
access violation flag register, and the memory address for which the access violation occurred, get
latched into the appropriate CPU fetch access violation address register.

3.12.1.8.2 CPU Write Protection

A CPU has write permission to a memory only if that memory is dedicated to that CPU, or if its respective
subsystem is the master for that memory (in case of GSx memory). When write accesses are allowed
based on the mastership, it can be further protected by setting the CPUWRPROTx bit of the specific
register to ‘1.’ If write access is done by a CPU to memory where it is protected, a write protection
violation occurs.
There are two types of CPU write protection violations:
• Non-master CPU write protection violation
• Master CPU write protection violation
If a write access is made to a dedicated or shared memory by the master CPU and CPUWRPROTx is
set to ‘1’ for that memory, it’s called a master CPU write protection violation.
If a write protection violation occurs, write gets ignored, a flag gets set into the appropriate access
violation flag register, and the memory address for which the access violation occurred, gets latched into
the appropriate CPU write access violation address register. Also, an access violation interrupt is
generated if enabled in the interrupt enable register.

3.12.1.8.3 CPU Read Protection

For local shared RAM, if memory is shared between the CPU and its CLA, the CPU will only have access
if the memory is configured as data RAM for the CLA. If it is programmed as program RAM, all the access
from the CPU, including a read, will be blocked and the violation will be considered as a non-master
access violation.
If a read protection violation occurs, a flag gets set into the appropriate access violation flag register, and
the memory address for which the access violation occurred, gets latched into the appropriate CPU read
access violation address register. Also, if enabled in the interrupt enable register, an access violation
interrupt is generated.

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3.12.1.8.4 CLA Fetch Protection

If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as data RAM for the
CLA, any fetch access from the CLA to that particular LSx RAM results in a CLA fetch protection violation,
which is a non-master access violation.
If a CLA fetch protection violation occurs, it results in a MSTOP, a flag gets set into the appropriate access
violation flag register, and the memory address for which the access violation occurred, gets latched into
the appropriate CLA fetch access violation address register. Also, an access violation interrupt is
generated to the master CPU if enabled in the interrupt enable register.

3.12.1.8.5 CLA Write Protection

If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as program RAM for
the CLA, any data write access from the CLA to that particular LSx RAM results in a CLA write protection
violation, which is a non-master access violation. Similarly any data write access from CLA to CPUTOCLA
or DMATOCLA MSGRAM will result in a CLA write protection violation, which is a non-master access
violation.
If a CLA write protection violation occurs, write gets ignored, a flag gets set into the appropriate access
violation flag register, and the memory address for which the access violation occurred, gets latched into
the appropriate CLA write access violation address register. Also, an access violation interrupt is
generated to the master CPU if enabled in the interrupt enable register.

3.12.1.8.6 CLA Read Protection

If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as program RAM for
the CLA, any data read access from the CLA to that particular LSx RAM results in a CLA read protection
violation, which is a non-master access violation.
If a CLA read protection violation occurs, a flag gets set into the appropriate access violation flag register,
and the memory address for which the access violation occurred, gets latched into the appropriate CLA
read access violation address register. Also, an access violation interrupt is generated to the master CPU
if enabled in the interrupt enable register.

3.12.1.8.7 DMA Write Protection

The CPU1 or CPU2 DMA has write permission to a GSx memory only if its respective subsystem is
master for that memory. When write accesses from a DMA are allowed based on the mastership, it can be
further protected by setting the DMAWRPROTx bit of a specific register to ‘1.’ If write access is done by
the DMA to protected memory, a write protection violation occurs.
There are two types of DMA write protection violations:
• Non-master DMA write protection violation (applicable to GSx RAMs and DMATOCLA MSGRAM)
• Master DMA write protection violation
If a write access is made to GSx memory by a non-master DMA, it is called a non-master write protection
violation. If a write access is made to a dedicated or shared memory by a master DMA, and
DMAWRPROTx is set to ‘1’ for that memory, it is called a master DMA write protection violation.
If a write protection violation occurs on CPU1, write is ignored and a DMAERR interrupt gets generated,
whereas in the case of CPU2, a write is ignored and an access violation interrupt is generated if enabled
in the interrupt enable register. A flag gets set in the DMA access violation flag register, and the memory
address where the violation happened gets latched in the DMA fetch access violation address register.
These are dedicated registers for each subsystem.

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Note 1: All access protections are ignored during debug accesses. Write access to a protected
memory will go through when it is done via the debugger, irrespective of the write protection
configuration for that memory.
Note 2: In the case of local shared RAM, if memory is shared between the CPU and its CLA, the
CPU will only have access if the memory is configured as data RAM for the CLA. If it is
programmed as program RAM, all the access from the CPU (including read) and data access
from the CLA will be blocked, and violation will be considered as a non-master access
violation. If the memory is configured as dedicated to the CPU, all access from the CLA will
be blocked and the violation will be considered a non-master access violation.

3.12.1.9 Memory Error Detection, Correction and Error Handling

These devices have memory error detection and correction features to satisfy safety standards
requirements. These requirements warrant the addition of detection mechanisms for finite dangerous
failures.
In this device, all dedicated RAMs and LSx RAMs support error correction code (ECC) protection and
other shared RAMs have parity protection. The ECC scheme used is Single Error Correction Double Error
Detection (SECDED). The parity scheme used is even parity. ECC/Parity will cover the data bits stored in
memory as well as address.
ECC/Parity calculation is done inside the memory controller module and then calculated. ECC/Parity is
written into the memory along with the data. ECC/Parity is computed for 16-bit data; hence, for each 32-bit
data, there will be three 7-bit ECC codes (or 3-bit parity), two of which are for data and a third one for the
address.

3.12.1.9.1 Error Detection and Correction

Error detection is done while reading the data from memory. The error detection is performed for data as
well as address. For parity memory, only a single-bit error gets detected, whereas in the case of ECC
memory, along with a single-bit error, a double-bit error also gets detected. These errors are called
correctable error and uncorrectable errors. The following are characteristics of these errors:
• Parity errors are always uncorrectable errors
• Single-bit ECC errors are correctable errors
• Double-bit ECC errors are uncorrectable errors
• Address ECC errors are also uncorrectable errors
Correctable errors get corrected by the memory controller module and then correct data is given back as
read data to the master. It is also written back into the memory to prevent double-bit error due to another
single-bit error at the same memory address.

NOTE: ECC/Parity for address is calculated for address offset only (based on RAM blocksize) of
corresponding 32bit aligned address. E.g. in case of LSx RAM which are 4KB RAM block,
only11 LSB of 32bit aligned address are used. So if address is 0x8F8F, address ECC (or
Parity) will becalculated for address 0x78E (11bit offset of 32bit aligned address). Similarly
for 8KB RAM block,12bit address offset will be used.

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3.12.1.9.2 Error Handling

For each correctable error, the count in the correctable error count register will increment by one. When
the value in this count register becomes equal to the value configured into the correctable error threshold
register, an interrupt is generated to the respective CPU, that is, if the interrupt is enabled in the
correctable interrupt enable register. The user needs to configure the correctable error threshold register
based on the system requirements. Also, the address for which the error occurred, gets latched into the
master-specific status register and a flag gets set. Each of these registers are dedicated for each CPU
subsystem.
If there are uncorrectable errors, an NMI gets generated for the respective CPU. In this case, the address
for which the error occurred, also gets latched into the master-specific address status register, and a flag
gets set.
Table 3-10 summarizes different error situations that can arise. These need to be handled appropriately in
the software, using the status and interrupt indications provided.

Table 3-10. Error Handling in Different Scenarios

Access Error Found In Error Type Status Indication Error Notification
Type
Reads Data read from Uncorrectable Yes -CPUx/CPUx.DMA/CPUx.CLA1 NMI for CPUx access
memory Error CPU/DMA/CLA Read Error Address NMI for CPUx.DMA access
(Single-bit error Register Data returned to NMI to CPU for CPUx.CLA1 access
for Parity RAMs CPUx/CPUx.DMA/CPUx.CLA1 is
OR incorrect
Double bit Error
for ECC RAMs)
Reads Data read from Single-bit error for Yes - CPUx/CPUx.DMA CPU/DMA Interrupt when error counter reaches
memory ECC RAMs Read Error Address Register the user programmable threshold for
Increment single error counter single errors
Reads Address Address error Yes - CPUx/CPUx.DMA/CPUx.CLA1 NMI to CPU for CPUx access
CPU/DMA/CLA Read Address Error NMI to CPU for CPUx.DMA access
Register Data returned to NMI to CPU for CPUx.CLA1 access
CPUx/CPUx.DMA/CPUx.CLA1 is
incorrect

NOTE: In the case of an uncorrectable error during fetch on the CPU, there is the possibility of
getting an ITRAP before an NMI exception, since garbage instructions enter into the CPU
pipeline before the NMI gets generated.
During debug accesses, correctable as well as uncorrectable errors are masked.

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3.12.1.10 Application Test Hooks for Error Detection and Correction

Since error detection and correction logic is part of safety critical logic, safety applications may need to
ensure that the logic is always working fine (during run time also). To enable this, different test modes are
provided to generate ecc/parity error in RAM locations. These test modes can be configured in RAM Test
registers of different RAM blocks. (e.g. For D0 RAM, TEST_D0 bit in DxTEST register). Different test
modes are for different usage. In test mode user can modify the data bits (without modifying the
ECC/Parity bits) or ECC/Parity bits directly. Using this feature, an ECC/Parity error could be injected into
data. Since uncorrectable error generates NMI, some user may want to avoid generating this during test
mode and one of the test mode ("11") is provided where NMI generation gets disabled. This mode is just
like functional mode except NMI generation on uncorrectable error.

NOTE: The memory map for ECC/Parity bits and data bits are the same. The user must choose a
different test mode ("10") to access ECC/Parity bits.

The following tables show the bit mapping for the ECC and Parity bits when they are read in RAMTEST
mode using their respective addresses.

Table 3-11. Mapping of ECC Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data Content (ECC Memory)
6:0 ECC Code for lower 16 bits of data
7 Not Used
14:8 ECC Code for upper 16 bits of data
15 Not Used
22:16 ECC Code for address
31:23 Not Used

Table 3-12. Mapping of Parity Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data Content (Parity Memory)
0 Parity for lower 16 bits of data
7:1 Not Used
8 Parity for upper 16 bits of data
15:9 Not Used
16 Parity for address
31:17 Not Used

Following is the sequence that should be followed to test the ecc/parity logic.
• Set the test mode to “01” or “10” depending on whether data field or ecc/parity field needs to be
written.
• Write the data pattern into the memory.
• Set the test mode to “11” to read from memory and exercise the ecc/parity logic.
• Check the test log registers to verify the correctness of the logic.
• The above sequence can be repeated for any number of data patterns.
• Once the test is complete, re-initialize the locations used in test, and set the test mode to “00” which
would change the RAM block back into functional mode.

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3.12.1.11 ROM Test

ROMs are read only memory, unlike RAMs, data or parity bits cannot be modified to introduce errors for
diagnostic coverage of parity checking logic. Following method is used to check health of parity checking
logic in ROMs.
• Added duplicate Parity check logic and feed the same data into duplicate parity checker
• Generate uncorrectable error if parity check status of these two separate parity checkers do not match
Probability of both circuits having fault is unlikely hence Parity Errors will be certainly detected.
To generate the error, a test bit FORCE_ERROR is added. When FORCE_ERROR bit is set, parity bit
going to one of party checker is inverted thereby introducing uncorrectable error. Uncorrectable error is
generated only if there is an error on all parity checkers that is. address, data [15:0] and data [31:16]. This
will ensure that all three parity checkers are working as expected.

Figure 3-19. ROM Parity Checking Logic

P3[0] Offset Addr P2[0] Data[31:16] P1[0] Data[15:0]

ForceError ForceError ForceError

Addr Parity Checker Addr Parity Checker Data[31:16] Parity Data[31:16] Parity Data[15:0] Parity Data[15:0] Parity
2 1 Checker 2 Checker 1 Checker 2 Checker 1
Parity Error Parity Error Parity Error Parity Error Parity Error Parity Error
p1
p1 p3 p5 p3
0
p5
p2 Uncorrectable error
p2 p4 p6 p4
1
p6

ForceError

3.12.1.12 RAM Initialization

To ensure that read/fetch from uninitialized RAM locations do not cause ECC or parity errors, the
RAM_INIT feature is provided for each memory block. Using this feature, any RAM block can be initialized
with 0x0 data and respective ECC/Parity bits accordingly. This can be initiated by setting the INIT bit to ‘1’
for the specific RAM block in INIT registers. To check the status of RAM initialization, SW should poll for
the INITDONE bit for that RAM block in the INITDONE register to be set. Unless this bit gets set, no
access should be made to that RAM memory block.
In the case of GSx memory, only the CPU of the subsystem that is configured as the master for the
particular GSx RAM block can initiate the RAM initialization.

NOTE: None of the masters should access the memory while initialization is taking place. If memory
is accessed before RAMINITDONE is set, the memory read/write as well as initialization will
not happen correctly.

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3.13 JTAG
Gel files perform certain initialization tasks. This helps the users in a debug environment. However, when
executed standalone (without the emulator connected) the application may not work as expected, since
there is no gel file to perform those initializations. For example, gel file disables watchdog. If user code
does not service the watchdog in the application (or fails to disable it), there will be a difference in how the
application behaves with the debugger and without.
Common tasks performed by the gel files (but not boot-ROM).
On Reset:
• Disable Flash ECC on some devices.
– Disabling ECC only when using Flash API functions, see the Flash API User Guide for details.
Otherwise, TI suggests to always program ECC and enable ECC-check.
• Disable Watchdog
• Enable CLA clock
• Select real-time mode or C28x mode

On Restart:
• Select real-time mode or C28x mode
• Clear IER and IFR

On Target Connect:
• Select real-time mode or C28x mode

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3.14 System Control Registers

This section describes the various System Control Registers.

3.14.1 System Control Base Addresses

Table 3-13. SYSCTRL Base Address Table (C28)

Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU2 DMA CLA
Instance Structure Protected

PIEVECTTABLE_BAS
- PIE_VECT_TABLE 0x0000_0D00 YES YES - - -
E
ACCESS_PROTECTI ACCESSPROTECTIO
AccessProtectionRegs 0x0005_F500 YES YES - - YES
ON_REGS N_BASE
ClkCfgRegs CLK_CFG_REGS CLKCFG_BASE 0x0005_D200 YES YES - - YES
CmCfgRegs CM_CFG_REGS CMCONF_BASE 0x0005_DC00 YES - - - YES
CpuIdRegs CPU_ID_REGS CPUID_BASE 0x0007_0223 YES YES - - -
CpuSysRegs CPU_SYS_REGS CPUSYS_BASE 0x0005_D300 YES YES - - YES
CpuTimer0Regs CPUTIMER_REGS CPUTIMER0_BASE 0x0000_0C00 YES YES - - -
CpuTimer1Regs CPUTIMER_REGS CPUTIMER1_BASE 0x0000_0C08 YES YES - - -
CpuTimer2Regs CPUTIMER_REGS CPUTIMER2_BASE 0x0000_0C10 YES YES - - -
DevCfgRegs DEV_CFG_REGS DEVCFG_BASE 0x0005_D000 YES - - - YES
DMACLASRCSEL_RE DMACLASRCSEL_BA
DmaClaSrcSelRegs 0x0000_7980 YES YES - - YES
GS SE
MemCfgRegs MEM_CFG_REGS MEMCFG_BASE 0x0005_F400 YES YES - - YES
MEMORY_ERROR_R MEMORYERROR_BA
MemoryErrorRegs 0x0005_F540 YES YES - - YES
EGS SE
NmiIntruptRegs NMI_INTRUPT_REGS NMI_BASE 0x0000_7060 YES YES - - YES
PieCtrlRegs PIECTRL_REGS PIECTRL_BASE 0x0000_0CE0 YES YES - - -
ROM_PRE_FETCH_R ROMPREFETCH_BAS
RomPrefetchRegs 0x0005_F588 YES YES - - YES
EGS E
ROM_WAIT_STATE_ ROMWAITSTATE_BA
RomWaitStateRegs 0x0005_F580 YES YES - - YES
REGS SE
SyncSocRegs SYNC_SOC_REGS SYNCSOC_BASE 0x0000_7940 YES - - - YES
SYSPERIPH_SAC_RE
SysPeriphAcRegs PERIPHAC_BASE 0x0005_D500 YES YES - - YES
GS
SysStsRegs SYS_STS_REGS SYSSTAT_BASE 0x0005_D400 YES YES - - YES
TestErrorRegs TEST_ERROR_REGS TEST_ERROR_BASE 0x0005_F590 YES YES - - YES
UidRegs UID_REGS UID_BASE 0x0007_020C YES YES - - -
WdRegs WD_REGS WD_BASE 0x0000_7000 YES YES - - YES
XintRegs XINT_REGS XINT_BASE 0x0000_7070 YES YES - - YES

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3.14.2 CLK_CFG_REGS Registers

Table 3-14 lists the CLK_CFG_REGS registers. All register offset addresses not listed in Table 3-14
should be considered as reserved locations and the register contents should not be modified.

Table 3-14. CLK_CFG_REGS Registers

Offset Acronym Register Name Write Protection Section
0h CLKSEM Clock Control Semaphore Register EALLOW Go
2h CLKCFGLOCK1 Lock bit for CLKCFG registers EALLOW Go
8h CLKSRCCTL1 Clock Source Control register-1 EALLOW Go
Ah CLKSRCCTL2 Clock Source Control register-2 EALLOW Go
Ch CLKSRCCTL3 Clock Source Control register-3 EALLOW Go
Eh SYSPLLCTL1 SYSPLL Control register-1 EALLOW Go
14h SYSPLLMULT SYSPLL Multiplier register EALLOW Go
16h SYSPLLSTS SYSPLL Status register Go
18h AUXPLLCTL1 AUXPLL Control register-1 EALLOW Go
1Eh AUXPLLMULT AUXPLL Multiplier register EALLOW Go
20h AUXPLLSTS AUXPLL Status register Go
22h SYSCLKDIVSEL System Clock Divider Select register EALLOW Go
24h AUXCLKDIVSEL Auxillary Clock Divider Select register EALLOW Go
26h PERCLKDIVSEL Peripheral Clock Divider Selet register EALLOW Go
28h XCLKOUTDIVSEL XCLKOUT Divider Select register EALLOW Go
2Ah CLBCLKCTL CLB Clocking Control Register EALLOW Go
2Ch LOSPCP Low Speed Clock Source Prescalar EALLOW Go
2Eh MCDCR Missing Clock Detect Control Register EALLOW Go
30h X1CNT 10-bit Counter on X1 Clock Go
32h XTALCR XTAL Control Register EALLOW Go
36h ETHERCATCLKCTL ETHERCATCLKCTL EALLOW Go
38h CMCLKCTL CMCLKCTL EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-15 shows the codes that are
used for access types in this section.

Table 3-15. CLK_CFG_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables

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Table 3-15. CLK_CFG_REGS Access Type

Codes (continued)
Access Type Code Description
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.2.1 CLKSEM Register (Offset = 0h) [reset = 0h]

CLKSEM is shown in Figure 3-20 and described in Table 3-16.
Return to the Summary Table.
Clock Control Semaphore Register

Figure 3-20. CLKSEM Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
R-0/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEM
R-0-0h R/W-0h

Table 3-16. CLKSEM Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h Writing the value 0xa5a5 will allow the writing of the SEM bits, else
writes are ignored. Reads will return 0.
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the
KEY matches). 16-bit writes to the upper or lower half of this register
will be ignored
Reset type: CPU1.SYSRSn
15-2 RESERVED R-0 0h Reserved
1-0 SEM R/W 0h This register provides a mechanism to acquire all the CLKCFG
registers (except this register) by CPU1 or CPU2. A CPU can
perform read/writes to any of the CLKCFG registers (except this
register) only if it owns the semaphore. Otherwise, writes are ignored
and reads will return 0x0.
Semaphore State Transitions:
A value of 00, 10, 11 gives ownership to CPU1
A value of 01 gives ownership to CPU2.
The following are the only state transitions allowed on these bits.
00,11 <-> 01 (allowed by CPU2)
00,11 <-> 10 (allowed by CPU1)
If a CPU doesn't own the CLK_CFG_REGS set of registers (as
defined by the state of this semaphore), reads from that CPU to all
those registers return 0x0 and writes are ignore. Note that this is not
true of CLKSEM register. The CLKSEM register's reads and writes
are always allowed from both CPU1 and CPU2.
Reset type: CPU1.SYSRSn

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3.14.2.2 CLKCFGLOCK1 Register (Offset = 2h) [reset = 0h]

CLKCFGLOCK1 is shown in Figure 3-21 and described in Table 3-17.
Return to the Summary Table.
Lock bit for CLKCFG registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of
this register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are
always allowed

Figure 3-21. CLKCFGLOCK1 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED CMCLKCTL ETHERCATCL XTALCR
KCTL
R-0-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h
15 14 13 12 11 10 9 8
LOSPCP CLBCLKCTL PERCLKDIVSE AUXCLKDIVSE SYSCLKDIVSE AUXPLLMULT RESERVED RESERVED
L L L
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R-0-0h R-0-0h
7 6 5 4 3 2 1 0
AUXPLLCTL1 SYSPLLMULT SYSPLLCTL3 SYSPLLCTL2 SYSPLLCTL1 CLKSRCCTL3 CLKSRCCTL2 CLKSRCCTL1
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-17. CLKCFGLOCK1 Register Field Descriptions

Bit Field Type Reset Description
31-19 RESERVED R-0 0h Reserved
18 CMCLKCTL R/WSonce 0h Lock bit for CMCLKCTL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
17 ETHERCATCLKCTL R/WSonce 0h Lock bit for ETHERCATCLKCTL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
16 XTALCR R/WSonce 0h Lock bit for XTALCR register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
15 LOSPCP R/WSonce 0h Lock bit for LOSPCP register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
14 CLBCLKCTL R/WSonce 0h Lock bit for CLBCLKCTL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
13 PERCLKDIVSEL R/WSonce 0h Lock bit for PERCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

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Table 3-17. CLKCFGLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
12 AUXCLKDIVSEL R/WSonce 0h Lock bit for AUXCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
11 SYSCLKDIVSEL R/WSonce 0h Lock bit for SYSCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
10 AUXPLLMULT R/WSonce 0h Lock bit for AUXPLLMULT register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
9 RESERVED R-0 0h Reserved
8 RESERVED R-0 0h Reserved
7 AUXPLLCTL1 R/WSonce 0h Lock bit for AUXPLLCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
6 SYSPLLMULT R/WSonce 0h Lock bit for SYSPLLMULT register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
5 SYSPLLCTL3 R/WSonce 0h Lock bit for SYSPLLCTL3 register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
4 SYSPLLCTL2 R/WSonce 0h Lock bit for SYSPLLCTL2 register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
3 SYSPLLCTL1 R/WSonce 0h Lock bit for SYSPLLCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn

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Table 3-17. CLKCFGLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 CLKSRCCTL3 R/WSonce 0h Lock bit for CLKSRCCTL3 register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
1 CLKSRCCTL2 R/WSonce 0h Lock bit for CLKSRCCTL2 register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
0 CLKSRCCTL1 R/WSonce 0h Lock bit for CLKSRCCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn

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3.14.2.3 CLKSRCCTL1 Register (Offset = 8h) [reset = 0h]

CLKSRCCTL1 is shown in Figure 3-22 and described in Table 3-18.
Return to the Summary Table.
Clock Source Control register-1

Figure 3-22. CLKSRCCTL1 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED XTALOFF INTOSC2OFF_ RESERVED OSCCLKSRCSEL
NOTSUPPORT
ED
R-0-0h R/W-0h R/W-0h R-0-0h R/W-0h

Table 3-18. CLKSRCCTL1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-6 RESERVED R-0 0h Reserved
4 XTALOFF R/W 0h Crystal (External) Oscillator Off Bit: This bit turns external oscillator
off:
0 = Crystal (External) Oscillator On (default on reset)
1 = Crystal (External) Oscillator Off
NOTE: Ensure no resources are using a clock source prior to
disabling it. For example OSCCLKSRCSEL (SYSPLL),
AUXOSCCLKSRCSEL (AUXPLL), CANxBCLKSEL (CAN Clock),
TMR2CLKSRCSEL (CPUTIMER2) and XCLKOUTSEL(XCLKOUT).
Reset type: XRSn
3 INTOSC2OFF_NOTSUPP R/W 0h RESERVED: This bit is not supported any more, and should not be
ORTED set to 1.
Note: If this bit is set to 1 it will turn OFF INTOSC2 and lead to PLL
failure
Reset type: XRSn
2 RESERVED R-0 0h Reserved

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Table 3-18. CLKSRCCTL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 OSCCLKSRCSEL R/W 0h Oscillator Clock Source Select Bit: This bit selects the source for
OSCCLK.
00 = INTOSC2 (default on reset)
01 = External Oscillator (XTAL)
10 = INTOSC1
11 = reserved (default to INTOSC1)
At power-up or after an XRSn, INTOSC2 is selected by default.
Whenever the user changes the clock source using these bits, the
SYSPLLMULT register will be forced to zero and the PLL will be
bypassed and powered down. This prevents potential PLL
overshoot. The user will then have to write to the SYSPLLMULT
register to configure the appropriate multiplier.
Notes:
[1] Reserved selection defaults to 00 configuration
[2] INTOSC1 is recommended to be used only after missing clock
detection. If user wants to re-lock the PLL with INTOSC1 (the back-
up clock source) after missing clock is detected, he can do a
MCLKCLR and lock the PLL.
[3] Any writes to this bit must be followed with at least 300 CPU
Cycles of wait time by adding at least 300 NOP instructions.
[4] Changing the OSCCLKSRC while PLL is running and used by
system (i.e. PLLCLKEN=1), can lead to dead System Clock. User
needs to first bypass the PLL clock from the system by
PLLCLKEN=0, and then change the OSCCLK source.
Reset type: XRSn

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3.14.2.4 CLKSRCCTL2 Register (Offset = Ah) [reset = 0h]

CLKSRCCTL2 is shown in Figure 3-23 and described in Table 3-19.
Return to the Summary Table.
Clock Source Control register-2

Figure 3-23. CLKSRCCTL2 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED MCANABITCLKSEL
R-0-0h R/W-0h
7 6 5 4 3 2 1 0
CANBBCLKSEL CANABCLKSEL AUXOSCCLKSRCSEL
R/W-0h R/W-0h R/W-0h

Table 3-19. CLKSRCCTL2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-12 RESERVED R-0 0h Reserved
11-10 MCANABITCLKSEL R/W 0h MCAN Bit Clock Source Select Bit:
00 = CMCLK/CPU1SYSCLK based on PALLOCATE setting.
01 = AUXPLLCLK
10 = AUXCLKIN
11 = Rsvd
If bit timing clock source has to change, then PCLKCR bit for the
corresponding MCAN instance has to be cleared to '0' first before
updating the values in thies field. Once the value is updated, the
corresponding PCLKCR bit of this instance can be set back to '1'.
Reset type: XRSn
5-4 CANBBCLKSEL R/W 0h CANB Bit Clock Source Select Bit:
00 = PERx.SYSCLK (default on reset),if PALLOCATE0.CANB is 0
else
CMCLK.
01 = External Oscillator (XTAL)
10 = AUXCLKIN (from GPIO)
11 = Reserved
Missing clock detect circuit doesnt have any impact on these bits.
If bit timing clock source has to change, then PCLKCR bit for the
corresponding DCAN instance has to be cleared to '0' first before
updating the values in thies field. Once the value is updated, the
corresponding PCLKCR bit of this instance can be set back to '1'.
Reset type: XRSn
3-2 CANABCLKSEL R/W 0h CANA Bit Clock Source Select Bit:
00 = PERx.SYSCLK (default on reset),if PALLOCATE0.CANA is 0
else
CMCLK.
01 = External Oscillator (XTAL)
10 = AUXCLKIN (from GPIO)
11 = Reserved
Missing clock detect circuit doesnt have any impact on these bits.
If bit timing clock source has to change, then PCLKCR bit for the
corresponding DCAN instance has to be cleared to '0' first before
updating the values in thies field. Once the value is updated, the
corresponding PCLKCR bit of this instance can be set back to '1'.
Reset type: XRSn

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Table 3-19. CLKSRCCTL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 AUXOSCCLKSRCSEL R/W 0h Oscillator Clock Source Select Bit: This bit selects the source for
AUXOSCCLK:
00 = INTOSC2 (default on reset)
01 = External Oscillator (XTAL)
10 = AUXCLKIN (from GPIO)
11 = Reserved(default to INTOSC2)
Whenever the user changes the clock source using these bits,
the AUXPLLMULT register will be forced to zero. The user will
then have to write to the AUXPLLMULT register to configure the
appropriate multiplier.
The user must wait 10 OSCCLK cycles before writing to
AUXPLLMULT
or disabling the previous clock source to allow the change to
complete.
The missing clock detection circuit does not affect these bits.
Notes:
[1] Changing the AUXOSCCLKSRC while PLL is running and
AUXPLLCLKEN=1, can lead to dead AUXPLLCLK. User needs to
first bypass the AUXPLL by AUXPLLCLKEN=0, and then change the
AUXOSCCLK source.
Reset type: XRSn

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3.14.2.5 CLKSRCCTL3 Register (Offset = Ch) [reset = 0h]

CLKSRCCTL3 is shown in Figure 3-24 and described in Table 3-20.
Return to the Summary Table.
Clock Source Control register-3

Figure 3-24. CLKSRCCTL3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED XCLKOUTSEL
R-0-0h R/W-0h

Table 3-20. CLKSRCCTL3 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3-0 XCLKOUTSEL R/W 0h XCLKOUT Source Select Bit: This bit selects the source for
XCLKOUT:
0000 = PLLSYSCLK (default on reset)
0001 = SYSPLLCLK
0010 = CPU1.SYSCLK
0011 = CPU2.SYSCLK
0100 = AUXPLLCLK
0101 = INTOSC1
0110 = INTOSC2
0111 = XTAL OSC o/p clock
1000 = CMCLK
1100 = PLLRAWCLK
1101 = AUXPLLRAWCLK
others = Reserved
Reset type: CPU1.SYSRSn

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3.14.2.6 SYSPLLCTL1 Register (Offset = Eh) [reset = 0h]

SYSPLLCTL1 is shown in Figure 3-25 and described in Table 3-21.
Return to the Summary Table.
SYSPLL Control register-1

Figure 3-25. SYSPLLCTL1 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED PLLCLKEN PLLEN
R-0-0h R/W-0h R/W-0h

Table 3-21. SYSPLLCTL1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-5 RESERVED R-0 0h Reserved
1 PLLCLKEN R/W 0h SYSPLL bypassed or included in the PLLSYSCLK path: This bit
decides if the SYSPLL is bypassed when PLLSYSCLK is generated
1 = PLLSYSCLK is fed from the SYSPLL clock output. Users need
to make sure that the PLL is locked before enabling this clock to the
system.
0 = SYSPLL is bypassed. Clock to system is direct feed from
OSCCLK
Note: Any writes to this bit must be followed with at least 120 CPU
Cycles of wait time by adding at least 120 NOP instructions.
Reset type: XRSn
0 PLLEN R/W 0h SYSPLL enabled or disabled: This bit decides if the SYSPLL is
enabled or not
1 = SYSPLL is enabled
0 = SYSPLL is powered off. Clock to system is direct feed from
OSCCLK
Note: Any writes to this bit must be followed with at least 60 CPU
Cycles of wait time by adding at least 60 NOP instructions.
Reset type: XRSn

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3.14.2.7 SYSPLLMULT Register (Offset = 14h) [reset = 0h]

SYSPLLMULT is shown in Figure 3-26 and described in Table 3-22.
Return to the Summary Table.
SYSPLL Multiplier register
NOTE:
IMULT and REFDIV fields in this register must be written at the same time and ONLY when
SYSPLLCTL1.PLLCLKEN=0 for correct PLL operation. If IMULT or REFDIV values are changed after
SYSPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation and cause system hangup.

Figure 3-26. SYSPLLMULT Register

31 30 29 28 27 26 25 24
RESERVED REFDIV
R-0-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED ODIV
R-0-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED RESERVED
R-0-0h R-0-0h
7 6 5 4 3 2 1 0
IMULT
R/W-0h

Table 3-22. SYSPLLMULT Register Field Descriptions

Bit Field Type Reset Description
31-29 RESERVED R-0 0h Reserved
28-24 REFDIV R/W 0h SYSPLL Reference Clock Divider
PLL Reference Divider = REFDIV + 1
NOTE:
IMULT and REFDIV fields in this register must be written at the
same time and ONLY when SYSPLLCTL1.PLLCLKEN=0 for correct
PLL operation. If IMULT or REFDIV values are changed after
SYSPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation and
cause system hangup.
Reset type: XRSn
23-21 RESERVED R-0 0h Reserved
20-16 ODIV R/W 0h SYSPLL Output Clock Divider
PLL Output Divider = ODIV + 1
NOTE:
If PLL is powered when SYSPLLCTL1.PLLCLKEN=0, then it is
recommended to write IMULT, REFDIV and ODIV at the same time.
This field can ALSO be programmed after
SYSPLLCTL1.PLLCLKEN=1 if application desires to change the
output divider of PLL clock, but proper care must be taken to make
sure values of IMULT and REFDIV are left unchanged when
SYSPLLCTL1.PLLCLKEN=1, if values of IMULT or REFDIV are
change after SYSPLLCTL1.PLLCLKEN=1 then it will disrupt PLL
operation and cause system hangup.
Reset type: XRSn
15-14 RESERVED R-0 0h Reserved
11-10 RESERVED R-0 0h Reserved

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Table 3-22. SYSPLLMULT Register Field Descriptions (continued)

Bit Field Type Reset Description
7-0 IMULT R/W 0h SYSPLL Integer Multiplier:
For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1
0000001 Integer Multiplier = 1
0000010 Integer Multiplier = 2
0000011 Integer Multiplier = 3
.......
1111111 Integer Multipler = 127
NOTE:
IMULT and REFDIV fields in this register must be written at the
same time and ONLY when SYSPLLCTL1.PLLCLKEN=0 for correct
PLL operation. If IMULT or REFDIV values are changed after
SYSPLLCTL1.PLLCLKEN=1 then it will disrupt PLL opeartion and
cause system hangup.
Reset type: XRSn

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3.14.2.8 SYSPLLSTS Register (Offset = 16h) [reset = 0h]

SYSPLLSTS is shown in Figure 3-27 and described in Table 3-23.
Return to the Summary Table.
SYSPLL Status register

Figure 3-27. SYSPLLSTS Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED SLIPS_NOTSU LOCKS
PPORTED
R-0-0h R-0h R-0h

Table 3-23. SYSPLLSTS Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
1 SLIPS_NOTSUPPORTED R 0h RESERVED: This bit is reserved and the value read should be
ignored. TI recommends using DCC to evaluate SYSPLL Slip status.
Refer to InitSysPll() or SysCtl_setClock() functions inside the latest
example software from C2000Ware for checking SYSPLL Slip status
using DCC.
Reset type: XRSn
0 LOCKS R 0h SYSPLL Lock Status Bit: This bit indicates whether the SYSPLL is
locked or not
0 = SYSPLL is not yet locked
1 = SYSPLL is locked
Reset type: XRSn

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3.14.2.9 AUXPLLCTL1 Register (Offset = 18h) [reset = 0h]

AUXPLLCTL1 is shown in Figure 3-28 and described in Table 3-24.
Return to the Summary Table.
AUXPLL Control register-1

Figure 3-28. AUXPLLCTL1 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED PLLCLKEN PLLEN
R-0-0h R/W-0h R/W-0h

Table 3-24. AUXPLLCTL1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-5 RESERVED R-0 0h Reserved
1 PLLCLKEN R/W 0h AUXPLL bypassed or included in the AUXPLLCLK path: This bit
decides if the AUXPLL is bypassed when AUXPLLCLK is generated
1 = AUXPLLCLK is fed from the AUXPLL clock output. Users need
to make sure that the PLL is locked before enabling this clock to the
AUXPLLCLK connected modules.
0 = AUXPLL is bypassed. Clock to modules connected to
AUXPLLCLK is direct feed from AUXOSCCLK
Reset type: XRSn
0 PLLEN R/W 0h AUXPLL enabled or disabled: This bit decides if the AUXPLL is
enabled or not
1 = AUXPLL is enabled
0 = AUXPLL is powered off. Clock to system is direct feed from
AUXOSCCLK
Reset type: XRSn

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3.14.2.10 AUXPLLMULT Register (Offset = 1Eh) [reset = 0h]

AUXPLLMULT is shown in Figure 3-29 and described in Table 3-25.
Return to the Summary Table.
AUXPLL Multiplier register
NOTE:
IMULT and REFDIV fields in this register must be written at the same time and ONLY when
AUXPLLCTL1.PLLCLKEN=0 for correct PLL operation. If IMULT or REFDIV values are changed after
AUXPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation.

Figure 3-29. AUXPLLMULT Register

31 30 29 28 27 26 25 24
RESERVED REFDIV
R-0-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED ODIV
R-0-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED RESERVED
R-0-0h R-0-0h
7 6 5 4 3 2 1 0
IMULT
R/W-0h

Table 3-25. AUXPLLMULT Register Field Descriptions

Bit Field Type Reset Description
31-29 RESERVED R-0 0h Reserved
28-24 REFDIV R/W 0h AUXPLL Reference Clock Divider
PLL Reference Divider = REFDIV + 1
NOTE:
IMULT and REFDIV fields in this register must be written at the
same time and ONLY when AUXPLLCTL1.PLLCLKEN=0 for correct
PLL operation. If IMULT or REFDIV values are changed after
AUXPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation.
Reset type: XRSn
23-21 RESERVED R-0 0h Reserved
20-16 ODIV R/W 0h AUXPLL Output Clock Divider
PLL Output Divider = ODIV + 1
NOTE:
If PLL is powered when AUXPLLCTL1.PLLCLKEN=0, then it is
recommended to write IMULT, REFDIV and ODIV at the same time.
This field can ALSO be programmed after
AUXPLLCTL1.PLLCLKEN=1 if application desires to change the
output divider of PLL clock, but proper care must be taken to make
sure values of IMULT and REFDIV are left unchanged when
AUXPLLCTL1.PLLCLKEN=1, if values of IMULT or REFDIV are
change after AUXPLLCTL1.PLLCLKEN=1 then it will disrupt PLL
operation.
Reset type: XRSn
15-14 RESERVED R-0 0h Reserved
11-10 RESERVED R-0 0h Reserved

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Table 3-25. AUXPLLMULT Register Field Descriptions (continued)

Bit Field Type Reset Description
7-0 IMULT R/W 0h AUXPLL Integer Multiplier:
For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1
0000001 Integer Multiplier = 1
0000010 Integer Multiplier = 2
0000011 Integer Multiplier = 3
.......
1111111 Integer Multipler = 127
NOTE:
IMULT and REFDIV fields in this register must be written at the
same time and ONLY when AUXPLLCTL1.PLLCLKEN=0 for correct
PLL operation. If IMULT or REFDIV values are changed after
AUXPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation.
Reset type: XRSn

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3.14.2.11 AUXPLLSTS Register (Offset = 20h) [reset = 0h]

AUXPLLSTS is shown in Figure 3-30 and described in Table 3-26.
Return to the Summary Table.
AUXPLL Status register

Figure 3-30. AUXPLLSTS Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED SLIPS_NOTSU LOCKS
PPORTED
R-0-0h R-0h R-0h

Table 3-26. AUXPLLSTS Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
1 SLIPS_NOTSUPPORTED R 0h RESERVED: This bit is reserved and the value read should be
ignored. TI recommends using DCC to evaluate AUXPLL Slip status.
Refer to InitAuxPll() or SysCtl_setAuxClock() functions inside the
latest example software from C2000Ware for checking AUXPLL Slip
status using DCC.
Reset type: XRSn
0 LOCKS R 0h AUXPLL Lock Status Bit: This bit indicates whether the AUXPLL is
locked or not
0 = AUXPLL is not yet locked
1 = AUXPLL is locked
Reset type: XRSn

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3.14.2.12 SYSCLKDIVSEL Register (Offset = 22h) [reset = 0h]

SYSCLKDIVSEL is shown in Figure 3-31 and described in Table 3-27.
Return to the Summary Table.
System Clock Divider Select register

Figure 3-31. SYSCLKDIVSEL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PLLSYSCLKDIV
R-0-0h R/W-0h

Table 3-27. SYSCLKDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-6 RESERVED R-0 0h Reserved
5-0 PLLSYSCLKDIV R/W 0h PLLSYSCLK Divide Select: This bit selects the divider setting for the
PLLSYSCLK.
0000 = /1
0001 = /2
0010 = /4
0011 = /6
0100 = /8
0101 = /10
0110 = /12
0111 = /14
1000 = /16
Others: Reserved
Reset type: XRSn

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3.14.2.13 AUXCLKDIVSEL Register (Offset = 24h) [reset = 1301h]

AUXCLKDIVSEL is shown in Figure 3-32 and described in Table 3-28.
Return to the Summary Table.
Auxillary Clock Divider Select register

Figure 3-32. AUXCLKDIVSEL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MCANCLKDIV RESERVED AUXPLLDIV
R-0-0h R/W-13h R-0-0h R/W-1h

Table 3-28. AUXCLKDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-13 RESERVED R-0 0h Reserved
12-8 MCANCLKDIV R/W 13h 00000 = /1
00001 = /2
...
10010 = /19
10011 = /20
101xx = Rsvd
11xxx = Rsvd
Reset type: XRSn
7-3 RESERVED R-0 0h Reserved
2-0 AUXPLLDIV R/W 1h AUXPLLCLK Divide Select: This bit selects the divider setting for the
AUXPLLCK.
000 = /1
001 = /2 (default on reset)
010 = /4
011 = /8
100 = /3
101 = /5
110 = /6
111 = /7
Reset type: XRSn

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3.14.2.14 PERCLKDIVSEL Register (Offset = 26h) [reset = 51h]

PERCLKDIVSEL is shown in Figure 3-33 and described in Table 3-29.
Return to the Summary Table.
Peripheral Clock Divider Selet register

Figure 3-33. PERCLKDIVSEL Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED EMIF2CLKDIV RESERVED EMIF1CLKDIV EPWMCLKDIV
R-0-0h R/W-1h R-0-0h R/W-1h R/W-1h

Table 3-29. PERCLKDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-7 RESERVED R-0 0h Reserved
6 EMIF2CLKDIV R/W 1h EMIF2 Clock Divide Select: This bit selects whether the EMIF2
module run with a /1 or /2 clock.
0: /1 of CPU1.SYSCLK is selected
1: /2 of CPU1.SYSCLK is selected
Reset type: CPU1.SYSRSn
5 RESERVED R-0 0h Reserved
4 EMIF1CLKDIV R/W 1h EMIF1 Clock Divide Select: This bit selects whether the EMIF1
module run with a /1 or /2 clock.
For single core device
0: /1 of CPU1.SYSCLK is selected
1: /2 of CPU1.SYSCLK is selected
For Dual core device
0: /1 of PLLSYSCLK is selected
1: /2 of PLLSYSCLK is selected
Reset type: CPU1.SYSRSn
1-0 EPWMCLKDIV R/W 1h EPWM Clock Divide Select: This bit selects whether the EPWM
modules run with a /1 or /2 clock. This divider sits in front of the
PLLSYSCLK
x0 = /1 of PLLSYSCLK
x1 = /2 of PLLSYSLCK (default on reset)
Note: Refer to the EPWM User Guide for maximum EPWM
Frequency
Reset type: CPU1.SYSRSn

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3.14.2.15 XCLKOUTDIVSEL Register (Offset = 28h) [reset = 3h]

XCLKOUTDIVSEL is shown in Figure 3-34 and described in Table 3-30.
Return to the Summary Table.
XCLKOUT Divider Select register

Figure 3-34. XCLKOUTDIVSEL Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED XCLKOUTDIV
R-0-0h R/W-3h

Table 3-30. XCLKOUTDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1-0 XCLKOUTDIV R/W 3h XCLKOUT Divide Select: This bit selects the divider setting for the
XCLKOUT.
00 = /1
01 = /2
10 = /4
11 = /8 (default on reset)
Reset type: CPU1.SYSRSn

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3.14.2.16 CLBCLKCTL Register (Offset = 2Ah) [reset = 7h]

CLBCLKCTL is shown in Figure 3-35 and described in Table 3-31.
Return to the Summary Table.
CLB Clocking Control Register

Figure 3-35. CLBCLKCTL Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
CLKMODECLB CLKMODECLB CLKMODECLB CLKMODECLB CLKMODECLB CLKMODECLB CLKMODECLB CLKMODECLB
8 7 6 5 4 3 2 1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED TILECLKDIV RESERVED CLBCLKDIV
R-0-0h R/W-0h R-0-0h R/W-7h

Table 3-31. CLBCLKCTL Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R-0 0h Reserved
23 CLKMODECLB8 R/W 0h 0 : CLB8 is synchronous to SYSCLK
1 : CLB8 runs of asynchronous clock
Reset type: SYSRSn
22 CLKMODECLB7 R/W 0h 0 : CLB7 is synchronous to SYSCLK
1 : CLB7 runs of asynchronous clock
Reset type: SYSRSn
21 CLKMODECLB6 R/W 0h 0 : CLB6 is synchronous to SYSCLK
1 : CLB6 runs of asynchronous clock
Reset type: SYSRSn
20 CLKMODECLB5 R/W 0h 0 : CLB5 is synchronous to SYSCLK
1 : CLB5 runs of asynchronous clock
Reset type: SYSRSn
19 CLKMODECLB4 R/W 0h 0 : CLB4 is synchronous to SYSCLK
1 : CLB4 runs of asynchronous clock
Reset type: SYSRSn
18 CLKMODECLB3 R/W 0h 0 : CLB3 is synchronous to SYSCLK
1 : CLB3 runs of asynchronous clock
Reset type: SYSRSn
17 CLKMODECLB2 R/W 0h 0 : CLB2 is synchronous to SYSCLK
1 : CLB2 runs of asynchronous clock
Reset type: SYSRSn
16 CLKMODECLB1 R/W 0h 0 : CLB1 is synchronous to SYSCLK
1 : CLB1 runs of asynchronous clock
Reset type: SYSRSn
15-5 RESERVED R-0 0h Reserved
4 TILECLKDIV R/W 0h 0: /1
1: /2
Reset type: SYSRSn
3 RESERVED R-0 0h Reserved

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Table 3-31. CLBCLKCTL Register Field Descriptions (continued)

Bit Field Type Reset Description
2-0 CLBCLKDIV R/W 7h 000: /1
001: /2
010: /3
011: /4
100: /5
101: /6
110: /7
111: /8
Reset type: SYSRSn

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3.14.2.17 LOSPCP Register (Offset = 2Ch) [reset = 2h]

LOSPCP is shown in Figure 3-36 and described in Table 3-32.
Return to the Summary Table.
Low Speed Clock Source Prescalar

Figure 3-36. LOSPCP Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LSPCLKDIV
R-0-0h R/W-2h

Table 3-32. LOSPCP Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-3 RESERVED R-0 0h Reserved
2-0 LSPCLKDIV R/W 2h These bits configure the low-speed peripheral clock (LSPCLK) rate
relative to SYSCLK of CPU1 and CPU2.
000,LSPCLK = / 1
001,LSPCLK = / 2
010,LSPCLK = / 4 (default on reset)
011,LSPCLK = / 6
100,LSPCLK = / 8
101,LSPCLK = / 10
110,LSPCLK = / 12
111,LSPCLK = / 14
Note:
[1] This clock is used as strobe for the SCI and SPI modules.
Reset type: CPU1.SYSRSn

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3.14.2.18 MCDCR Register (Offset = 2Eh) [reset = 0h]

MCDCR is shown in Figure 3-37 and described in Table 3-33.
Return to the Summary Table.
Missing Clock Detect Control Register

Figure 3-37. MCDCR Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED OSCOFF MCLKOFF MCLKCLR MCLKSTS
R-0-0h R/W-0h R/W-0h R-0/W1S-0h R-0h

Table 3-33. MCDCR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 OSCOFF R/W 0h Oscillator Clock Disconnect from MCD Bit:
0 = OSCCLK Connected to OSCCLK Counter in MCD module
1 = OSCCLK Disconnected to OSCCLK Counter in MCD module
Reset type: XRSn
2 MCLKOFF R/W 0h Missing Clock Detect Off Bit:
0 = Missing Clock Detect Circuit Enabled
1 = Missing Clock Detect Circuit Disabled
Reset type: XRSn
1 MCLKCLR R-0/W1S 0h Missing Clock Clear Bit:
Write 1" to this bit to clear MCLKSTS bit and reset the missing clock
detect circuit."
Reset type: XRSn
0 MCLKSTS R 0h Missing Clock Status Bit:
0 = OSCCLK Is OK
1 = OSCCLK Detected Missing, CLOCKFAILn Generated
Reset type: XRSn

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3.14.2.19 X1CNT Register (Offset = 30h) [reset = 0h]

X1CNT is shown in Figure 3-38 and described in Table 3-34.
Return to the Summary Table.
10-bit Counter on X1 Clock

Figure 3-38. X1CNT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED CLR
R-0-0h R/W-
0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED X1CNT
R-0-0h R-0h

Table 3-34. X1CNT Register Field Descriptions

Bit Field Type Reset Description
31-17 RESERVED R-0 0h Reserved
16 CLR R/W 0h X1 Counter clear:
1: X1CNT clear is asserted
0: X1CNT clear is de-asserted
Reset type: XRSn
15-10 RESERVED R-0 0h Reserved
9-0 X1CNT R 0h X1 Counter:
- This counter increments on every X1 CLOCKs positive-edge.
- Once it reaches the values of 0x3ff, it freezes
- Before switching from INTOSC2 to X1, application must check this
counter and make sure that it has saturated. This will ensure that the
Crystal connected to X1/X2 is oscillating.
Note: Before switching the OSCCCLKSRC to X1, X1CNT register
needs to be read at least 3 times for 0x3FF value. Refer C2000Ware
function "SysCtl_pollX1Counter" for SW implementation.
Reset type: XRSn

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3.14.2.20 XTALCR Register (Offset = 32h) [reset = 4h]

XTALCR is shown in Figure 3-39 and described in Table 3-35.
Return to the Summary Table.
XTAL Control Register

Figure 3-39. XTALCR Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED SE OSCOFF
R-0-0h R/W-0h R/W-0h

Table 3-35. XTALCR Register Field Descriptions

Bit Field Type Reset Description
31-3 RESERVED R-0 0h Reserved
1 SE R/W 0h Configures XTAL oscillator in single-ended or Crystal mode when
XTAL oscillator is powered (OFF = 0)
0 XTAL oscillator in Crystal mode
1 XTAL oscilator in single0ended mode (through X1)
Reset type: XRSn
0 OSCOFF R/W 0h This bit if '1', powers-down the XTAL oscillator macro and hence
doesn't let X2 to be driven by the XTAL oscillator. If a crystal is
connected to X1/X2, user needs to first clear this bit, wait for the
oscillator to power up (using X1CNT) and then only switch the clock
source to X1/X2
Reset type: XRSn

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3.14.2.21 ETHERCATCLKCTL Register (Offset = 36h) [reset = Eh]

ETHERCATCLKCTL is shown in Figure 3-40 and described in Table 3-36.
Return to the Summary Table.
ETHERCAT clock control register.

Figure 3-40. ETHERCATCLKCTL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED PHYCLKEN
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED ECATDIV DIVSRCSEL
R-0-0h R/W-7h R/W-0h

Table 3-36. ETHERCATCLKCTL Register Field Descriptions

Bit Field Type Reset Description
31-9 RESERVED R 0h Reserved
8 PHYCLKEN R/W 0h 0 : etherCAT phy clock disabled
1 : etherCAT phy clock enabled
Reset type: XRSn
7-4 RESERVED R-0 0h Reserved
3-1 ECATDIV R/W 7h 000: /1
001: /2
010: /3
011: /4
100: /5
101: /6
110: /7
111: /8
Reset type: XRSn
0 DIVSRCSEL R/W 0h 0: Auxillary PLL is the source for the etherCAT clock divider.
1: System PLL is the source for etherCAT clock divider.
Reset type: XRSn

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3.14.2.22 CMCLKCTL Register (Offset = 38h) [reset = E6h]

CMCLKCTL is shown in Figure 3-41 and described in Table 3-37.
Return to the Summary Table.
CM Clock control register

Figure 3-41. CMCLKCTL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
ETHDIV ETHDIVSRCSE CMCLKDIV CMDIVSRCSE
L L
R/W-7h R/W-0h R/W-3h R/W-0h

Table 3-37. CMCLKCTL Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R 0h Reserved
7-5 ETHDIV R/W 7h 000: /1
001: /2
010: /3
011: /4
100: /5
101: /6
110: /7
111: /8
Reset type: XRSn
4 ETHDIVSRCSEL R/W 0h 0: Auxillary PLL is the source for the etherNET clock divider.
1: System PLL is the source for etherNET clock divider.
Reset type: XRSn
3-1 CMCLKDIV R/W 3h 000: /1
001: /2
010: /3
011: /4
100: /5
101: /6
110: /7
111: /8
Note: CMCLKDIV should be configured prior or along with
CMCLKDIV configuration. If CMCLKDIV is configured after
CMDIVSRCSEL in the next cycle, the writes to this field gets
ignored.
Reset type: XRSn
0 CMDIVSRCSEL R/W 0h 0: Auxillary PLL is the source for the CM clock divider.
1: System PLL is the source for CM clock divider.
Reset type: XRSn

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3.14.3 CM_CONF_REGS Registers

Table 3-38 lists the CM_CONF_REGS registers. All register offset addresses not listed in Table 3-38
should be considered as reserved locations and the register contents should not be modified.

Table 3-38. CM_CONF_REGS Registers

Offset Acronym Register Name Write Protection Section
0h CMRESCTL CM Reset Control Register EALLOW Go
2h CMTOCPU1NMICTL CM To CPU1 NMI Control register EALLOW Go
4h CMTOCPU1INTCTL CM To CPU1 interrupt Control register EALLOW Go
20h PALLOCATE0 CM Peripheral Allocation Register. EALLOW Go
3FEh CM_CONF_REGS_LOCK CM Configuration Registers Lock EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-39 shows the codes that are
used for access types in this section.

Table 3-39. CM_CONF_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.3.1 CMRESCTL Register (Offset = 0h) [reset = 1h]

CMRESCTL is shown in Figure 3-42 and described in Table 3-40.
Return to the Summary Table.
Software reset of CM.

Figure 3-42. CMRESCTL Register

31 30 29 28 27 26 25 24
KEY
R-0/W-0h
23 22 21 20 19 18 17 16
KEY
R-0/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RESETSTS RESET
R-0h R-0h R/W-1h

Table 3-40. CMRESCTL Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h Write to this register succeeds only if this field is written with a value
of 0xa5a5
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the
KEY matches). 16-bit writes to the upper or lower half of this register
will be ignored
Reset type: CPU1.SYSRSn
15-2 RESERVED R 0h Reserved
1 RESETSTS R 0h 0: CM is under reset
1: CM is out of reset.
Reset type: CPU1.SYSRSn
0 RESET R/W 1h 1: Asserts reset to CM.
0: De-asserts reset to CM.
Software Note: This bit should be kept high until RESETSTS bit of
CMRSTCTL register goes low.
Reset type: CPU1.SYSRSn

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3.14.3.2 CMTOCPU1NMICTL Register (Offset = 2h) [reset = 0h]

CMTOCPU1NMICTL is shown in Figure 3-43 and described in Table 3-41.
Return to the Summary Table.
CM To CPU1 NMI Control register

Figure 3-43. CMTOCPU1NMICTL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CMNMIWDRST
R-0h R/W-0h

Table 3-41. CMTOCPU1NMICTL Register Field Descriptions

Bit Field Type Reset Description
31-3 RESERVED R 0h Reserved
2 CMNMIWDRST R/W 0h 0: NMI to CPU1 is not fired on a CMNMIWDRST to CM4.
1: NMI to CPU1 is fired on a CMNMIWDRST to CM4.
Reset type: XRSn

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3.14.3.3 CMTOCPU1INTCTL Register (Offset = 4h) [reset = 0h]

CMTOCPU1INTCTL is shown in Figure 3-44 and described in Table 3-42.
Return to the Summary Table.
CM To CPU1 interrupt Control register

Figure 3-44. CMTOCPU1INTCTL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CMNMIWDRST SYSRESETRE VECTRESET
Q
R-0h R/W-0h R/W-0h R/W-0h

Table 3-42. CMTOCPU1INTCTL Register Field Descriptions

Bit Field Type Reset Description
31-3 RESERVED R 0h Reserved
2 CMNMIWDRST R/W 0h 0: Interrupt to CPU1 is not fired on a CMNMIWDRST to CM4.
1: Interrupt to CPU1 is fired on a CMNMIWDRST to CM4.
Reset type: XRSn
1 SYSRESETREQ R/W 0h 0: Interrupt to CPU1 is not fired on a SYSRESETREQ to CM4.
1: Interrupt to CPU1 is fired on a SYSRESETREQ to CM4.
Reset type: XRSn
0 VECTRESET R/W 0h 0: Interrupt to CPU1 is not fired on a VECTRESET to CM4.
1: Interrupt to CPU1 is fired on a VECTRESET to CM4.
Reset type: XRSn

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3.14.3.4 PALLOCATE0 Register (Offset = 20h) [reset = 10h]

PALLOCATE0 is shown in Figure 3-45 and described in Table 3-43.
Return to the Summary Table.
CM Peripheral Allocation Register for shared peripherals.
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the PALLOCATEx register must be configured before the
PCLKCRx register.

Figure 3-45. PALLOCATE0 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CAN_B CAN_A ETHERCAT USB_A
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-43. PALLOCATE0 Register Field Descriptions

Bit Field Type Reset Description
31-5 RESERVED R 0h Reserved
3 CAN_B R/W 0h 0: CAN_B is allocated to C28x CPU1 or CPU2 (Mapping to CPU1 or
CPU2 is determined by CPUSELx.CAN_B bit setting), CM accesses
to CAN_B will be ignored and interrupts from CAN_B will not be
generated to CM.
1: CAN_B is allocated to CM, C28x CPU1/2 accesses to CAN_B will
be ignored and interrupts from CAN_B will not be generated to C28x
CPU1/2.
Reset type: XRSn
2 CAN_A R/W 0h 0: CAN_A is allocated to C28x CPU1 or CPU2 (Mapping to CPU1 or
CPU2 is determined by CPUSELx.CAN_A bit setting), CM accesses
to CAN_A will be ignored and interrupts from CAN_A will not be
generated to CM.
1: CAN_A is allocated to CM, C28x CPU1/2 accesses to CAN_A will
be ignored and interrupts from CAN_A will not be generated to C28x
CPU1/2.
Reset type: XRSn
1 ETHERCAT R/W 0h 0: ETHERCAT is allocated to C28x CPU1, CM accesses to
ETHERCAT will be ignored and interrupts from ETHERCAT will not
be generated to CM.
1: ETHERCAT is allocated to CM, C28x CPU1 accesses to
ETHERCAT will be ignored and interrupts from ETHERCAT will not
be generated to C28x CPU1.
Note:CPU2 does not have access to ETHERCAT.
Reset type: XRSn
0 USB_A R/W 0h 0: USB_A is allocated to C28x CPU1, CM accesses to USB_A will
be ignored and interrupts from USB_A will not be generated to CM.
1: USB_A is allocated to CM, C28x CPU1 accesses to USB_A will
be ignored and interrupts from USB_A will not be generated to C28x
CPU1.
Note:CPU2 does not have access to USB_A.
Reset type: XRSn

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3.14.3.5 CM_CONF_REGS_LOCK Register (Offset = 3FEh) [reset = 0h]

CM_CONF_REGS_LOCK is shown in Figure 3-46 and described in Table 3-44.
Return to the Summary Table.
CM Configuration Registers Lock

Figure 3-46. CM_CONF_REGS_LOCK Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED LOCK
R-0h R/WSonce-0h

Table 3-44. CM_CONF_REGS_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 LOCK R/WSonce 0h 0: Allows write to the following registers
1: Writes to following registers are ignored.
1. PALLOCATE0
2. RAMALLOCATE
3. CMTOCPU1NMICTL
4. CMTOCPU1INTCTL
Reset type: XRSn

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3.14.4 ACCESS_PROTECTION_REGS Registers

Table 3-45 lists the ACCESS_PROTECTION_REGS registers. All register offset addresses not listed in
Table 3-45 should be considered as reserved locations and the register contents should not be modified.

Table 3-45. ACCESS_PROTECTION_REGS Registers

Offset Acronym Register Name Write Protection Section
0h NMAVFLG Non-Master Access Violation Flag Register Go
2h NMAVSET Non-Master Access Violation Flag Set Register EALLOW Go
4h NMAVCLR Non-Master Access Violation Flag Clear Register EALLOW Go
6h NMAVINTEN Non-Master Access Violation Interrupt Enable EALLOW Go
Register
8h NMCPURDAVADDR Non-Master CPU Read Access Violation Go
Address
Ah NMCPUWRAVADDR Non-Master CPU Write Access Violation Address Go
Ch NMCPUFAVADDR Non-Master CPU Fetch Access Violation Go
Address
Eh NMDMAWRAVADDR Non-Master DMA Write Access Violation Go
Address
10h NMCLA1RDAVADDR Non-Master CLA1 Read Access Violation Go
Address
12h NMCLA1WRAVADDR Non-Master CLA1 Write Access Violation Go
Address
14h NMCLA1FAVADDR Non-Master CLA1 Fetch Access Violation Go
Address
1Ch NMDMARDAVADDR Non-Master DMA Read Access Violation Go
Address
20h MAVFLG Master Access Violation Flag Register Go
22h MAVSET Master Access Violation Flag Set Register EALLOW Go
24h MAVCLR Master Access Violation Flag Clear Register EALLOW Go
26h MAVINTEN Master Access Violation Interrupt Enable EALLOW Go
Register
28h MCPUFAVADDR Master CPU Fetch Access Violation Address Go
2Ah MCPUWRAVADDR Master CPU Write Access Violation Address Go
2Ch MDMAWRAVADDR Master DMA Write Access Violation Address Go

Complex bit access types are encoded to fit into small table cells. Table 3-46 shows the codes that are
used for access types in this section.

Table 3-46. ACCESS_PROTECTION_REGS Access

Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables

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Table 3-46. ACCESS_PROTECTION_REGS Access

Type Codes (continued)
Access Type Code Description
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.4.1 NMAVFLG Register (Offset = 0h) [reset = 0h]

NMAVFLG is shown in Figure 3-47 and described in Table 3-47.
Return to the Summary Table.
Non-Master Access Violation Flag Register

Figure 3-47. NMAVFLG Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED DMAREAD
R-0h R-0h
7 6 5 4 3 2 1 0
CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-47. NMAVFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-11 RESERVED R 0h Reserved
10 DMAREAD R 0h Non Master DMA Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
6 CLA1FETCH R 0h Non Master CLA1 Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
5 CLA1WRITE R 0h Non Master CLA1 Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
4 CLA1READ R 0h Non Master CLA1 Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
3 DMAWRITE R 0h Non Master DMA Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
2 CPUFETCH R 0h Non Master CPU Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
1 CPUWRITE R 0h Non Master CPU Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
0 CPUREAD R 0h Non Master CPU Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

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3.14.4.2 NMAVSET Register (Offset = 2h) [reset = 0h]

NMAVSET is shown in Figure 3-48 and described in Table 3-48.
Return to the Summary Table.
Non-Master Access Violation Flag Set Register

Figure 3-48. NMAVSET Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED DMAREAD
R-0h R-0/W1S-0h
7 6 5 4 3 2 1 0
CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-48. NMAVSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-11 RESERVED R 0h Reserved
10 DMAREAD R-0/W1S 0h 0: No action.
1: DMA Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn
6 CLA1FETCH R-0/W1S 0h 0: No action.
1: CLA1 Fetch Access Violation Flag in NMAVFLG register will be
set and interrupt will be generated if enabled.
Reset type: SYSRSn
5 CLA1WRITE R-0/W1S 0h 0: No action.
1: CLA1 Write Access Violation Flag in NMAVFLG register will be
set and interrupt will be generated if enabled.
Reset type: SYSRSn
4 CLA1READ R-0/W1S 0h 0: No action.
1: CLA1 Read Access Violation Flag in NMAVFLG register will be
set and interrupt will be generated if enabled.
Reset type: SYSRSn
3 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
2 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
0 CPUREAD R-0/W1S 0h 0: No action.
1: CPU Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn

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3.14.4.3 NMAVCLR Register (Offset = 4h) [reset = 0h]

NMAVCLR is shown in Figure 3-49 and described in Table 3-49.
Return to the Summary Table.
Non-Master Access Violation Flag Clear Register

Figure 3-49. NMAVCLR Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED DMAREAD
R-0h R-0/W1S-0h
7 6 5 4 3 2 1 0
CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-49. NMAVCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-11 RESERVED R 0h Reserved
10 DMAREAD R-0/W1S 0h 0: No action.
1: DMA Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
6 CLA1FETCH R-0/W1S 0h 0: No action.
1: CLA1 Fetch Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
5 CLA1WRITE R-0/W1S 0h 0: No action.
1: CLA1 Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
4 CLA1READ R-0/W1S 0h 0: No action.
1: CLA1 Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
3 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
2 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
0 CPUREAD R-0/W1S 0h 0: No action.
1: CPU Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

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3.14.4.4 NMAVINTEN Register (Offset = 6h) [reset = 0h]

NMAVINTEN is shown in Figure 3-50 and described in Table 3-50.
Return to the Summary Table.
Non-Master Access Violation Interrupt Enable Register

Figure 3-50. NMAVINTEN Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED DMAREAD
R-0h R/W-0h
7 6 5 4 3 2 1 0
CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-50. NMAVINTEN Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-11 RESERVED R 0h Reserved
10 DMAREAD R/W 0h 0: DMA Non Master Read Access Violation Interrupt is disabled.
1: DMA Non Master Read Access Violation Interrupt is enabled.
Reset type: SYSRSn
6 CLA1FETCH R/W 0h 0: CLA1 Non Master Fetch Access Violation Interrupt is disabled.
1: CLA1 Non Master Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn
5 CLA1WRITE R/W 0h 0: CLA1 Non Master Write Access Violation Interrupt is disabled.
1: CLA1 Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
4 CLA1READ R/W 0h 0: CLA1 Non Master Read Access Violation Interrupt is disabled.
1: CLA1 Non Master Read Access Violation Interrupt is enabled.
Reset type: SYSRSn
3 DMAWRITE R/W 0h 0: DMA Non Master Write Access Violation Interrupt is disabled.
1: DMA Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
2 CPUFETCH R/W 0h 0: CPU Non Master Fetch Access Violation Interrupt is disabled.
1: CPU Non Master Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn
1 CPUWRITE R/W 0h 0: CPU Non Master Write Access Violation Interrupt is disabled.
1: CPU Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
0 CPUREAD R/W 0h 0: CPU Non Master Read Access Violation Interrupt is disabled.
1: CPU Non Master Read Access Violation Interrupt is enabled.
Reset type: SYSRSn

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3.14.4.5 NMCPURDAVADDR Register (Offset = 8h) [reset = 0h]

NMCPURDAVADDR is shown in Figure 3-51 and described in Table 3-51.
Return to the Summary Table.
Non-Master CPU Read Access Violation Address

Figure 3-51. NMCPURDAVADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCPURDAVADDR
R-0h

Table 3-51. NMCPURDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCPURDAVADDR R 0h This register captures the address location for which non master
CPU read access vaiolation occurred.
Reset type: SYSRSn

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3.14.4.6 NMCPUWRAVADDR Register (Offset = Ah) [reset = 0h]

NMCPUWRAVADDR is shown in Figure 3-52 and described in Table 3-52.
Return to the Summary Table.
Non-Master CPU Write Access Violation Address

Figure 3-52. NMCPUWRAVADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCPUWRAVADDR
R-0h

Table 3-52. NMCPUWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCPUWRAVADDR R 0h This register captures the address location for which non master
CPU write access vaiolation occurred.
Reset type: SYSRSn

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3.14.4.7 NMCPUFAVADDR Register (Offset = Ch) [reset = 0h]

NMCPUFAVADDR is shown in Figure 3-53 and described in Table 3-53.
Return to the Summary Table.
Non-Master CPU Fetch Access Violation Address

Figure 3-53. NMCPUFAVADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCPUFAVADDR
R-0h

Table 3-53. NMCPUFAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCPUFAVADDR R 0h This register captures the address location for which non master
CPU fetch access vaiolation occurred.
Reset type: SYSRSn

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3.14.4.8 NMDMAWRAVADDR Register (Offset = Eh) [reset = 0h]

NMDMAWRAVADDR is shown in Figure 3-54 and described in Table 3-54.
Return to the Summary Table.
Non-Master DMA Write Access Violation Address

Figure 3-54. NMDMAWRAVADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMDMAWRAVADDR
R-0h

Table 3-54. NMDMAWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMDMAWRAVADDR R 0h This register captures the address location for which non master
DMA write access vaiolation occurred.
Reset type: SYSRSn

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3.14.4.9 NMCLA1RDAVADDR Register (Offset = 10h) [reset = 0h]

NMCLA1RDAVADDR is shown in Figure 3-55 and described in Table 3-55.
Return to the Summary Table.
Non-Master CLA1 Read Access Violation Address

Figure 3-55. NMCLA1RDAVADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCLA1RDAVADDR
R-0h

Table 3-55. NMCLA1RDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCLA1RDAVADDR R 0h This register captures the address location for which non master
CLA1 read access vaiolation occurred.
Reset type: SYSRSn

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3.14.4.10 NMCLA1WRAVADDR Register (Offset = 12h) [reset = 0h]

NMCLA1WRAVADDR is shown in Figure 3-56 and described in Table 3-56.
Return to the Summary Table.
Non-Master CLA1 Write Access Violation Address

Figure 3-56. NMCLA1WRAVADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCLA1WRAVADDR
R-0h

Table 3-56. NMCLA1WRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCLA1WRAVADDR R 0h This register captures the address location for which non master
CLA1 write access vaiolation occurred.
Reset type: SYSRSn

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3.14.4.11 NMCLA1FAVADDR Register (Offset = 14h) [reset = 0h]

NMCLA1FAVADDR is shown in Figure 3-57 and described in Table 3-57.
Return to the Summary Table.
Non-Master CLA1 Fetch Access Violation Address

Figure 3-57. NMCLA1FAVADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCLA1FAVADDR
R-0h

Table 3-57. NMCLA1FAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCLA1FAVADDR R 0h This register captures the address location for which non master
CLA1 fetch access vaiolation occurred.
Reset type: SYSRSn

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3.14.4.12 NMDMARDAVADDR Register (Offset = 1Ch) [reset = 0h]

NMDMARDAVADDR is shown in Figure 3-58 and described in Table 3-58.
Return to the Summary Table.
Non-Master DMA Read Access Violation Address

Figure 3-58. NMDMARDAVADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMDMARDAVADDR
R-0h

Table 3-58. NMDMARDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMDMARDAVADDR R 0h This register captures the address location for which non master
DMA read access vaiolation occurred.
Reset type: SYSRSn

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3.14.4.13 MAVFLG Register (Offset = 20h) [reset = 0h]

MAVFLG is shown in Figure 3-59 and described in Table 3-59.
Return to the Summary Table.
Master Access Violation Flag Register

Figure 3-59. MAVFLG Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R-0h R-0h R-0h

Table 3-59. MAVFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 DMAWRITE R 0h Master DMA Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
1 CPUWRITE R 0h Master CPU Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
0 CPUFETCH R 0h Master CPU Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

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3.14.4.14 MAVSET Register (Offset = 22h) [reset = 0h]

MAVSET is shown in Figure 3-60 and described in Table 3-60.
Return to the Summary Table.
Master Access Violation Flag Set Register

Figure 3-60. MAVSET Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-60. MAVSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
0 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn

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3.14.4.15 MAVCLR Register (Offset = 24h) [reset = 0h]

MAVCLR is shown in Figure 3-61 and described in Table 3-61.
Return to the Summary Table.
Master Access Violation Flag Clear Register

Figure 3-61. MAVCLR Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-61. MAVCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in MAVFLG register will be
cleared.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in MAVFLG register will be
cleared .
Reset type: SYSRSn
0 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in MAVFLG register will be
cleared.
Reset type: SYSRSn

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3.14.4.16 MAVINTEN Register (Offset = 26h) [reset = 0h]

MAVINTEN is shown in Figure 3-62 and described in Table 3-62.
Return to the Summary Table.
Master Access Violation Interrupt Enable Register

Figure 3-62. MAVINTEN Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R/W-0h R/W-0h R/W-0h

Table 3-62. MAVINTEN Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 DMAWRITE R/W 0h 0: DMA Write Access Violation Interrupt is disabled.
1: DMA Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
1 CPUWRITE R/W 0h 0: CPU Write Access Violation Interrupt is disabled.
1: CPU Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
0 CPUFETCH R/W 0h 0: CPU Fetch Access Violation Interrupt is disabled.
1: CPU Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn

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3.14.4.17 MCPUFAVADDR Register (Offset = 28h) [reset = 0h]

MCPUFAVADDR is shown in Figure 3-63 and described in Table 3-63.
Return to the Summary Table.
Master CPU Fetch Access Violation Address

Figure 3-63. MCPUFAVADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCPUFAVADDR
R-0h

Table 3-63. MCPUFAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 MCPUFAVADDR R 0h This register captures the address location for which master CPU
fetch access vaiolation occurred.
Reset type: SYSRSn

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3.14.4.18 MCPUWRAVADDR Register (Offset = 2Ah) [reset = 0h]

MCPUWRAVADDR is shown in Figure 3-64 and described in Table 3-64.
Return to the Summary Table.
Master CPU Write Access Violation Address

Figure 3-64. MCPUWRAVADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCPUWRAVADDR
R-0h

Table 3-64. MCPUWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 MCPUWRAVADDR R 0h This register captures the address location for which master CPU
write access vaiolation occurred.
Reset type: SYSRSn

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3.14.4.19 MDMAWRAVADDR Register (Offset = 2Ch) [reset = 0h]

MDMAWRAVADDR is shown in Figure 3-65 and described in Table 3-65.
Return to the Summary Table.
Master DMA Write Access Violation Address

Figure 3-65. MDMAWRAVADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMAWRAVADDR
R-0h

Table 3-65. MDMAWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 MDMAWRAVADDR R 0h This register captures the address location for which master DMA
write access vaiolation occurred.
Reset type: SYSRSn

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3.14.5 CPU_SYS_REGS Registers

Table 3-66 lists the CPU_SYS_REGS registers. All register offset addresses not listed in Table 3-66
should be considered as reserved locations and the register contents should not be modified.

Table 3-66. CPU_SYS_REGS Registers

Offset Acronym Register Name Write Protection Section
0h CPUSYSLOCK1 Lock bit for CPUSYS registers EALLOW Go
2h CPUSYSLOCK2 Lock bit for CPUSYS registers EALLOW Go
Ah PIEVERRADDR PIE Vector Fetch Error Address register EALLOW Go
22h PCLKCR0 Peripheral Clock Gating Registers EALLOW Go
24h PCLKCR1 Peripheral Clock Gating Registers EALLOW Go
26h PCLKCR2 Peripheral Clock Gating Registers EALLOW Go
28h PCLKCR3 Peripheral Clock Gating Registers EALLOW Go
2Ah PCLKCR4 Peripheral Clock Gating Registers EALLOW Go
2Eh PCLKCR6 Peripheral Clock Gating Registers EALLOW Go
30h PCLKCR7 Peripheral Clock Gating Registers EALLOW Go
32h PCLKCR8 Peripheral Clock Gating Registers EALLOW Go
34h PCLKCR9 Peripheral Clock Gating Registers EALLOW Go
36h PCLKCR10 Peripheral Clock Gating Registers EALLOW Go
38h PCLKCR11 Peripheral Clock Gating Registers EALLOW Go
3Ch PCLKCR13 Peripheral Clock Gating Registers EALLOW Go
3Eh PCLKCR14 Peripheral Clock Gating Registers EALLOW Go
42h PCLKCR16 Peripheral Clock Gating Registers EALLOW Go
44h PCLKCR17 Peripheral Clock Gating Registers EALLOW Go
46h PCLKCR18 Peripheral Clock Gating Registers EALLOW Go
4Ah PCLKCR20 Peripheral Clock Gating Registers EALLOW Go
4Ch PCLKCR21 Peripheral Clock Gating Registers EALLOW Go
4Eh PCLKCR22 Peripheral Clock Gating Registers EALLOW Go
50h PCLKCR23 Peripheral Clock Gating Registers EALLOW Go
70h SIMRESET Simulated Reset Register Go
76h LPMCR LPM Control Register EALLOW Go
78h GPIOLPMSEL0 GPIO LPM Wakeup select registers EALLOW Go
7Ah GPIOLPMSEL1 GPIO LPM Wakeup select registers EALLOW Go
7Ch TMR2CLKCTL Timer2 Clock Measurement functionality control EALLOW Go
register
7Eh RESCCLR Reset Cause Clear Register Go
80h RESC Reset Cause register Go

Complex bit access types are encoded to fit into small table cells. Table 3-67 shows the codes that are
used for access types in this section.

Table 3-67. CPU_SYS_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1C W Write
1C 1 to clear

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Table 3-67. CPU_SYS_REGS Access Type

Codes (continued)
Access Type Code Description
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.5.1 CPUSYSLOCK1 Register (Offset = 0h) [reset = 0h]

CPUSYSLOCK1 is shown in Figure 3-66 and described in Table 3-68.
Return to the Summary Table.
Lock bit for CPUSYS registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of
this register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are
always allowed

Figure 3-66. CPUSYSLOCK1 Register

31 30 29 28 27 26 25 24
PCLKCR23 PCLKCR22 PCLKCR21 PCLKCR20 PCLKCR18 PCLKCR17
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h
23 22 21 20 19 18 17 16
GPIOLPMSEL1 GPIOLPMSEL0 LPMCR PCLKCR16 PCLKCR14 PCLKCR13
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h
15 14 13 12 11 10 9 8
PCLKCR11 PCLKCR10 PCLKCR9 PCLKCR8 PCLKCR7 PCLKCR6
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h
7 6 5 4 3 2 1 0
PCLKCR4 PCLKCR3 PCLKCR2 PCLKCR1 PCLKCR0 PIEVERRADD
R
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-68. CPUSYSLOCK1 Register Field Descriptions

Bit Field Type Reset Description
30 PCLKCR23 R/WSonce 0h Lock bit for PCLKCR23 Register
0: Respective register is not locked
1: Respective register is locked.
Note: This bit will be reserved for CPU2.
Reset type: SYSRSn
29 PCLKCR22 R/WSonce 0h Lock bit for PCLKCR22 Register
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
28 PCLKCR21 R/WSonce 0h Lock bit for PCLKCR21 Register
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
27 PCLKCR20 R/WSonce 0h Lock bit for PCLKCR20 Register
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
25 PCLKCR18 R/WSonce 0h Lock bit for PCLKCR18 Register
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
24 PCLKCR17 R/WSonce 0h Lock bit for PCLKCR17 Register
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
23 GPIOLPMSEL1 R/WSonce 0h Lock bit for GPIOLPMSEL1 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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Table 3-68. CPUSYSLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
22 GPIOLPMSEL0 R/WSonce 0h Lock bit for GPIOLPMSEL0 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
21 LPMCR R/WSonce 0h Lock bit for LPMCR Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
19 PCLKCR16 R/WSonce 0h Lock bit for PCLKCR16 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
17 PCLKCR14 R/WSonce 0h Lock bit for PCLKCR14 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
16 PCLKCR13 R/WSonce 0h Lock bit for PCLKCR13 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
14 PCLKCR11 R/WSonce 0h Lock bit for PCLKCR11 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
13 PCLKCR10 R/WSonce 0h Lock bit for PCLKCR10 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
12 PCLKCR9 R/WSonce 0h Lock bit for PCLKCR9 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
11 PCLKCR8 R/WSonce 0h Lock bit for PCLKCR8 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
10 PCLKCR7 R/WSonce 0h Lock bit for PCLKCR7 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
9 PCLKCR6 R/WSonce 0h Lock bit for PCLKCR6 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
7 PCLKCR4 R/WSonce 0h Lock bit for PCLKCR4 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
6 PCLKCR3 R/WSonce 0h Lock bit for PCLKCR3 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
5 PCLKCR2 R/WSonce 0h Lock bit for PCLKCR2 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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Table 3-68. CPUSYSLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
4 PCLKCR1 R/WSonce 0h Lock bit for PCLKCR1 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
3 PCLKCR0 R/WSonce 0h Lock bit for PCLKCR0 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
2 PIEVERRADDR R/WSonce 0h Lock bit for PIEVERRADDR Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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3.14.5.2 CPUSYSLOCK2 Register (Offset = 2h) [reset = 0h]

CPUSYSLOCK2 is shown in Figure 3-67 and described in Table 3-69.
Return to the Summary Table.
Lock bit for CPUSYS registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of
this register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are
always allowed

Figure 3-67. CPUSYSLOCK2 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ETHERCATCT
L
R-0h R/WSonce-0h

Table 3-69. CPUSYSLOCK2 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 ETHERCATCTL R/WSonce 0h Lock bit for ETHERCATCTL register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
1 Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
2 The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
3 This bit is reserved for CPU2
Reset type: SYSRSn

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3.14.5.3 PIEVERRADDR Register (Offset = Ah) [reset = 003FFFFFh]

PIEVERRADDR is shown in Figure 3-68 and described in Table 3-70.
Return to the Summary Table.
PIE Vector Fetch Error Address register

Figure 3-68. PIEVERRADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ADDR
R-0-0h R/W-003FFFFFh

Table 3-70. PIEVERRADDR Register Field Descriptions

Bit Field Type Reset Description
31-22 RESERVED R-0 0h Reserved
21-0 ADDR R/W 003FFFFFh This register defines the address of the PIE Vector Fetch Error
handler routine. Its the responsibility of user to initialize this register.
If this register is not initialized, a default error handler at address
0x3fffbe will get executed. Refer to Device Boot ROM Spec for more
details on this register.
Reset type: XRSn

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3.14.5.4 PCLKCR0 Register (Offset = 22h) [reset = 38h]

PCLKCR0 is shown in Figure 3-69 and described in Table 3-71.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-69. PCLKCR0 Register

31 30 29 28 27 26 25 24
RESERVED ERAD
R-0-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED GTBCLKSYNC TBCLKSYNC RESERVED HRCAL
R-0-0h R/W-0h R/W-0h R-0-0h R/W-0h
15 14 13 12 11 10 9 8
CLA1BGCRC CPUBGCRC RESERVED
R/W-0h R/W-0h R-0-0h
7 6 5 4 3 2 1 0
RESERVED CPUTIMER2 CPUTIMER1 CPUTIMER0 DMA CLA1
R-0-0h R/W-1h R/W-1h R/W-1h R/W-0h R/W-0h

Table 3-71. PCLKCR0 Register Field Descriptions

Bit Field Type Reset Description
31-25 RESERVED R-0 0h Reserved
24 ERAD R/W 0h ERAD Clock Enable Bit: When set, this enables the clock to the
HRPWM module
1: ERAD clock is enabled
0: ERAD clock is disabled
Reset type: SYSRSn
23-20 RESERVED R-0 0h Reserved
19 GTBCLKSYNC R/W 0h EPWM Time Base Clock Global sync: When set by CPU1, PWM
time bases of all modules start counting. The effect of this bit is seen
on all the EPMW modules irrespective of their partitioning based on
CPUSEL
Notes:
1. This bit on the CPU2.PCLKCR0 register has no effect.
2. Writing '1' to this bit overrides the effect of write '1' to the
TBCLKSYNC bit at the same time
Reset type: SYSRSn
18 TBCLKSYNC R/W 0h EPWM Time Base Clock sync: When set PWM time bases of all the
PWM modules belonging to the same CPU-Subsystem (as
partitioned using their CPUSEL bits) start counting
Notes:
1. This bit from CPU1.PCLKCR0 or CPU2.PCLKCR0 is selected and
fed to the individual EPWM modules based on their respective
CPUSEL bit.
Reset type: SYSRSn
17 RESERVED R-0 0h Reserved
16 HRCAL R/W 0h HRCAL Clock Enable Bit: When set, this enables the clock to the
HRPWM module
1: HRCALclock is enabled
0: HRCAL clock is disabled
Reset type: SYSRSn
14 CLA1BGCRC R/W 0h CLA1BGCRC Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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Table 3-71. PCLKCR0 Register Field Descriptions (continued)

Bit Field Type Reset Description
13 CPUBGCRC R/W 0h CPUBGCRC Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
12-6 RESERVED R-0 0h Reserved
5 CPUTIMER2 R/W 1h CPUTIMER2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 CPUTIMER1 R/W 1h CPUTIMER1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 CPUTIMER0 R/W 1h CPUTIMER0 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 DMA R/W 0h DMA Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 CLA1 R/W 0h CLA1 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.5 PCLKCR1 Register (Offset = 24h) [reset = 0h]

PCLKCR1 is shown in Figure 3-70 and described in Table 3-72.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-70. PCLKCR1 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED EMIF2 EMIF1
R-0-0h R/W-0h R/W-0h

Table 3-72. PCLKCR1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 EMIF2 R/W 0h EMIF2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] These bits are not used (R/W) in CPU2.PCLKCR1 register.
EMIF1 & EMIF2 clock enabled are controlled only from
CPU1.PCLKCR1 register.
Reset type: SYSRSn
0 EMIF1 R/W 0h EMIF1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] These bits are not used (R/W) in CPU2.PCLKCR1 register.
EMIF1 & EMIF2 clock enabled are controlled only from
CPU1.PCLKCR1 register.
Reset type: SYSRSn

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3.14.5.6 PCLKCR2 Register (Offset = 26h) [reset = 0h]

PCLKCR2 is shown in Figure 3-71 and described in Table 3-73.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-71. PCLKCR2 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
EPWM16 EPWM15 EPWM14 EPWM13 EPWM12 EPWM11 EPWM10 EPWM9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-73. PCLKCR2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 EPWM16 R/W 0h EPWM16 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
14 EPWM15 R/W 0h EPWM15 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
13 EPWM14 R/W 0h EPWM14 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
12 EPWM13 R/W 0h EPWM13 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
11 EPWM12 R/W 0h EPWM12 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
10 EPWM11 R/W 0h EPWM11 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
9 EPWM10 R/W 0h EPWM10 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
8 EPWM9 R/W 0h EPWM9 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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Table 3-73. PCLKCR2 Register Field Descriptions (continued)

Bit Field Type Reset Description
7 EPWM8 R/W 0h EPWM8 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
6 EPWM7 R/W 0h EPWM7 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
5 EPWM6 R/W 0h EPWM6 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 EPWM5 R/W 0h EPWM5 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 EPWM4 R/W 0h EPWM4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 EPWM3 R/W 0h EPWM3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 EPWM2 R/W 0h EPWM2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 EPWM1 R/W 0h EPWM1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.7 PCLKCR3 Register (Offset = 28h) [reset = 0h]

PCLKCR3 is shown in Figure 3-72 and described in Table 3-74.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-72. PCLKCR3 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
ECAP7 ECAP6 ECAP5 ECAP4 ECAP3 ECAP2 ECAP1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-74. PCLKCR3 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
6 ECAP7 R/W 0h ECAP7 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
5 ECAP6 R/W 0h ECAP6 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 ECAP5 R/W 0h ECAP5 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 ECAP4 R/W 0h ECAP4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 ECAP3 R/W 0h ECAP3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 ECAP2 R/W 0h ECAP2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 ECAP1 R/W 0h ECAP1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.8 PCLKCR4 Register (Offset = 2Ah) [reset = 0h]

PCLKCR4 is shown in Figure 3-73 and described in Table 3-75.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-73. PCLKCR4 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED EQEP3 EQEP2 EQEP1
R-0-0h R/W-0h R/W-0h R/W-0h

Table 3-75. PCLKCR4 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
2 EQEP3 R/W 0h EQEP3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 EQEP2 R/W 0h EQEP2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 EQEP1 R/W 0h EQEP1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.9 PCLKCR6 Register (Offset = 2Eh) [reset = 0h]

PCLKCR6 is shown in Figure 3-74 and described in Table 3-76.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-74. PCLKCR6 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SD2 SD1
R-0-0h R/W- R/W-
0h 0h

Table 3-76. PCLKCR6 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
1 SD2 R/W 0h SD2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 SD1 R/W 0h SD1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.10 PCLKCR7 Register (Offset = 30h) [reset = 0h]

PCLKCR7 is shown in Figure 3-75 and described in Table 3-77.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-75. PCLKCR7 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED SCI_D SCI_C SCI_B SCI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-77. PCLKCR7 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SCI_D R/W 0h SCI_D Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 SCI_C R/W 0h SCI_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 SCI_B R/W 0h SCI_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 SCI_A R/W 0h SCI_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.11 PCLKCR8 Register (Offset = 32h) [reset = 0h]

PCLKCR8 is shown in Figure 3-76 and described in Table 3-78.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-76. PCLKCR8 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED SPI_D SPI_C SPI_B SPI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-78. PCLKCR8 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SPI_D R/W 0h SPI_D Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 SPI_C R/W 0h SPI_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 SPI_B R/W 0h SPI_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 SPI_A R/W 0h SPI_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.12 PCLKCR9 Register (Offset = 34h) [reset = 0h]

PCLKCR9 is shown in Figure 3-77 and described in Table 3-79.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-77. PCLKCR9 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED I2C_B I2C_A
R-0-0h R/W-0h R/W-0h

Table 3-79. PCLKCR9 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 I2C_B R/W 0h I2C_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 I2C_A R/W 0h I2C_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.13 PCLKCR10 Register (Offset = 36h) [reset = 0h]

PCLKCR10 is shown in Figure 3-78 and described in Table 3-80.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-78. PCLKCR10 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED CAN_B CAN_A
R-0-0h R-0-0h R-0-0h R/W-0h R/W-0h

Table 3-80. PCLKCR10 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R-0 0h Reserved
6 RESERVED R-0 0h Reserved
5 RESERVED R-0 0h Reserved
1 CAN_B R/W 0h CAN_B Clock Enable bit:
0: Module clock is gated-off i including module bit clock.
1: Module clock is turned-on
Reset type: SYSRSn
0 CAN_A R/W 0h CAN_A Clock Enable bit:
0: Module clock is gated-off including module bit clock.
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.14 PCLKCR11 Register (Offset = 38h) [reset = 0h]

PCLKCR11 is shown in Figure 3-79 and described in Table 3-81.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-79. PCLKCR11 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED USB_A
R-0-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED McBSP_B McBSP_A
R-0-0h R/W-0h R/W-0h

Table 3-81. PCLKCR11 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
16 USB_A R/W 0h USB_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] This bit is not used (R/W) in CPU2.PCLKCR11 register. USB_A
clock enabled is controlled only from CPU1.PCLKCR11 register
Reset type: SYSRSn
15-2 RESERVED R-0 0h Reserved
1 McBSP_B R/W 0h McBSP_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 McBSP_A R/W 0h McBSP_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.15 PCLKCR13 Register (Offset = 3Ch) [reset = 0h]

PCLKCR13 is shown in Figure 3-80 and described in Table 3-82.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-80. PCLKCR13 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED ADC_D ADC_C ADC_B ADC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-82. PCLKCR13 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 ADC_D R/W 0h ADC_D Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 ADC_C R/W 0h ADC_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 ADC_B R/W 0h ADC_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 ADC_A R/W 0h ADC_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.16 PCLKCR14 Register (Offset = 3Eh) [reset = 0h]

PCLKCR14 is shown in Figure 3-81 and described in Table 3-83.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-81. PCLKCR14 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
CMPSS8 CMPSS7 CMPSS6 CMPSS5 CMPSS4 CMPSS3 CMPSS2 CMPSS1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-83. PCLKCR14 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 CMPSS8 R/W 0h CMPSS8 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
6 CMPSS7 R/W 0h CMPSS7 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
5 CMPSS6 R/W 0h CMPSS6 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 CMPSS5 R/W 0h CMPSS5 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 CMPSS4 R/W 0h CMPSS4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 CMPSS3 R/W 0h CMPSS3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 CMPSS2 R/W 0h CMPSS2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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Table 3-83. PCLKCR14 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 CMPSS1 R/W 0h CMPSS1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.17 PCLKCR16 Register (Offset = 42h) [reset = 0h]

PCLKCR16 is shown in Figure 3-82 and described in Table 3-84.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-82. PCLKCR16 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED DAC_C DAC_B DAC_A
R-0-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED
R-0-0h

Table 3-84. PCLKCR16 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
18 DAC_C R/W 0h Buffered_DAC12_3 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
17 DAC_B R/W 0h Buffered_DAC12_2 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
16 DAC_A R/W 0h Buffered_DAC12_1 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
15-0 RESERVED R-0 0h Reserved

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3.14.5.18 PCLKCR17 Register (Offset = 44h) [reset = 0h]

PCLKCR17 is shown in Figure 3-83 and described in Table 3-85.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-83. PCLKCR17 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
CLB4 CLB3 CLB2 CLB1
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-85. PCLKCR17 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
3 CLB4 R/W 0h CLB4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 CLB3 R/W 0h CLB3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 CLB2 R/W 0h CLB2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 CLB1 R/W 0h CLB1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.19 PCLKCR18 Register (Offset = 46h) [reset = 0h]

PCLKCR18 is shown in Figure 3-84 and described in Table 3-86.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-84. PCLKCR18 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
FSIRX_H FSIRX_G FSIRX_F FSIRX_E FSIRX_D FSIRX_C FSIRX_B FSIRX_A
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
FSITX_B FSITX_A
R/W-0h R/W-0h

Table 3-86. PCLKCR18 Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R-0 0h Reserved
23 FSIRX_H R/W 0h FSIRX_H Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
22 FSIRX_G R/W 0h FSIRX_G Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
21 FSIRX_F R/W 0h FSIRX_F Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
20 FSIRX_E R/W 0h FSIRX_E Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
19 FSIRX_D R/W 0h FSIRX_D Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
18 FSIRX_C R/W 0h FSIRX_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
17 FSIRX_B R/W 0h FSIRX_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
16 FSIRX_A R/W 0h FSIRX_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
15-8 RESERVED R-0 0h Reserved

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Table 3-86. PCLKCR18 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 FSITX_B R/W 0h FSITX_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 FSITX_A R/W 0h FSITX_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.20 PCLKCR20 Register (Offset = 4Ah) [reset = 0h]

PCLKCR20 is shown in Figure 3-85 and described in Table 3-87.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-85. PCLKCR20 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED PMBUS_A
R-0-0h R/W-0h

Table 3-87. PCLKCR20 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
0 PMBUS_A R/W 0h PMBUS_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.21 PCLKCR21 Register (Offset = 4Ch) [reset = 0h]

PCLKCR21 is shown in Figure 3-86 and described in Table 3-88.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-86. PCLKCR21 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DCC2 DCC1 DCC0
R-0-0h R/W-0h R/W-0h R/W-0h

Table 3-88. PCLKCR21 Register Field Descriptions

Bit Field Type Reset Description
31-3 RESERVED R-0 0h Reserved
2 DCC2 R/W 0h DCC2 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 DCC1 R/W 0h DCC1 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 DCC0 R/W 0h DCC0 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.14.5.22 PCLKCR22 Register (Offset = 4Eh) [reset = 0h]

PCLKCR22 is shown in Figure 3-87 and described in Table 3-89.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-87. PCLKCR22 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED PBISTCLK
R-0-0h R/W-0h

Table 3-89. PCLKCR22 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 PBISTCLK R/W 0h PBIST Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Note: This bit is reserved on CPU2.
Reset type: SYSRSn

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3.14.5.23 PCLKCR23 Register (Offset = 50h) [reset = 0h]

PCLKCR23 is shown in Figure 3-88 and described in Table 3-90.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.

Figure 3-88. PCLKCR23 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED ETHERCAT
R-0-0h R/W-0h

Table 3-90. PCLKCR23 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 ETHERCAT R/W 0h ETHERCAT Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Note: This bit is reserved on CPU2.
Reset type: SYSRSn

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3.14.5.24 SIMRESET Register (Offset = 70h) [reset = 0h]

SIMRESET is shown in Figure 3-89 and described in Table 3-91.
Return to the Summary Table.
Simulated Reset Register
Note: This register exists only on CPU1

Figure 3-89. SIMRESET Register

31 30 29 28 27 26 25 24
KEY
R-0/W-0h
23 22 21 20 19 18 17 16
KEY
R-0/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED XRSn CPU1RSn
R-0h R-0/W1S-0h R-0/W1S-0h

Table 3-91. SIMRESET Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h Write to this register succeeds only if this field is written with a value
of 0xa5a5
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the
KEY matches). 16-bit writes to the upper or lower half of this register
will be ignored
Reset type: XRSn
15-2 RESERVED R 0h Reserved
1 XRSn R-0/W1S 0h Writing a 1 to this field generates a XRSn like reset.
Writing a 0 has no effect.
Note: Writing to this pin will pull the XRSn pin low for 512 INTOSC1
clock cycles.
Reset type: XRSn
0 CPU1RSn R-0/W1S 0h Writing a 1 to this field generates a reset to to CPU1.
Writing a 0 has no effect.
Reset type: XRSn

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3.14.5.25 LPMCR Register (Offset = 76h) [reset = FCh]

LPMCR is shown in Figure 3-90 and described in Table 3-92.
Return to the Summary Table.
LPM Control Register

Figure 3-90. LPMCR Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
WDINTE RESERVED
R/W-0h R-0-0h
7 6 5 4 3 2 1 0
QUALSTDBY LPM
R/W-3Fh R/W-0h

Table 3-92. LPMCR Register Field Descriptions

Bit Field Type Reset Description
30-18 RESERVED R-0 0h Reserved
15 WDINTE R/W 0h When this bit is set to 1, it enables the watchdog interrupt signal to
wake the device from STANDBY mode.
Note:
[1] To use this signal, the user must also enable the WDINTn signal
using the WDENINT bit in the SCSR register.
Reset type: SYSRSn
14-8 RESERVED R-0 0h Reserved
7-2 QUALSTDBY R/W 3Fh Select number of OSCCLK clock cycles to qualify the selected inputs
when waking the from STANDBY mode:
000000 = 2 OSCCLKs
000001 = 3 OSCCLKs
......
111111 = 65 OSCCLKs
Note: The LPMCR.QUALSTDBY register should be set to a value
greater than the ratio of INTOSC1/PLLSYSCLK to ensure proper
wake up.
Reset type: SYSRSn
1-0 LPM R/W 0h These bits set the low power mode for the device. Takes effect when
CPU executes the IDLE instruction (when IDLE instruction is out of
EXE Phase of the Pipeline)
00: IDLE Mode
01: STANDBY Mode
1x: Reserved
Reset type: SYSRSn

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3.14.5.26 GPIOLPMSEL0 Register (Offset = 78h) [reset = 0h]

GPIOLPMSEL0 is shown in Figure 3-91 and described in Table 3-93.
Return to the Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities
of the selected pin.

Figure 3-91. GPIOLPMSEL0 Register

31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-93. GPIOLPMSEL0 Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
30 GPIO30 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
29 GPIO29 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
28 GPIO28 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
27 GPIO27 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
26 GPIO26 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
25 GPIO25 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
24 GPIO24 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
23 GPIO23 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
22 GPIO22 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-93. GPIOLPMSEL0 Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO21 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
20 GPIO20 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
19 GPIO19 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
18 GPIO18 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
17 GPIO17 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
16 GPIO16 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
15 GPIO15 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
14 GPIO14 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
13 GPIO13 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
12 GPIO12 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
11 GPIO11 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
10 GPIO10 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
9 GPIO9 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
8 GPIO8 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
7 GPIO7 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
6 GPIO6 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
5 GPIO5 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
4 GPIO4 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-93. GPIOLPMSEL0 Register Field Descriptions (continued)

Bit Field Type Reset Description
3 GPIO3 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
2 GPIO2 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
1 GPIO1 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
0 GPIO0 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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3.14.5.27 GPIOLPMSEL1 Register (Offset = 7Ah) [reset = 0h]

GPIOLPMSEL1 is shown in Figure 3-92 and described in Table 3-94.
Return to the Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities
of the selected pin.

Figure 3-92. GPIOLPMSEL1 Register

31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-94. GPIOLPMSEL1 Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
30 GPIO62 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
29 GPIO61 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
28 GPIO60 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
27 GPIO59 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
26 GPIO58 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
25 GPIO57 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
24 GPIO56 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
23 GPIO55 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
22 GPIO54 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-94. GPIOLPMSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO53 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
20 GPIO52 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
19 GPIO51 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
18 GPIO50 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
17 GPIO49 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
16 GPIO48 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
15 GPIO47 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
14 GPIO46 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
13 GPIO45 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
12 GPIO44 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
11 GPIO43 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
10 GPIO42 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
9 GPIO41 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
8 GPIO40 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
7 GPIO39 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
6 GPIO38 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
5 GPIO37 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
4 GPIO36 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-94. GPIOLPMSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
3 GPIO35 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
2 GPIO34 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
1 GPIO33 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
0 GPIO32 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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3.14.5.28 TMR2CLKCTL Register (Offset = 7Ch) [reset = 0h]

TMR2CLKCTL is shown in Figure 3-93 and described in Table 3-95.
Return to the Summary Table.
Timer2 Clock Measurement functionality control register

Figure 3-93. TMR2CLKCTL Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED TMR2CLKPRESCALE TMR2CLKSRCSEL
R-0-0h R/W-0h R/W-0h

Table 3-95. TMR2CLKCTL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-6 RESERVED R-0 0h Reserved
5-3 TMR2CLKPRESCALE R/W 0h CPU Timer 2 Clock Pre-Scale Value: These bits select the pre-scale
value for the selected clock source for CPU Timer 2:
000: /1 (default on reset)
001: /2
010: /4
011: /8
100: /16
101: spare (defaults to : /16)
110: spare (defaults to : /16)
111: spare (defaults to : /16)
Reset type: SYSRSn
2-0 TMR2CLKSRCSEL R/W 0h CPU Timer 2 Clock Source Select Bit: This bit selects the source for
CPU Timer 2:
000 =SYSCLK Selected (default on reset, pre-scale is bypassed)
001 = INTOSC1
010 = INTOSC2
011 = XTAL
110 = AUXPLLCLK
other values are reserved
Reset type: SYSRSn

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3.14.5.29 RESCCLR Register (Offset = 7Eh) [reset = 0h]

RESCCLR is shown in Figure 3-94 and described in Table 3-96.
Return to the Summary Table.
Reset Cause Clear Register

Figure 3-94. RESCCLR Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED SIMRESET_XR SIMRESET_CP ECAT_RESET_ SCCRESETn
Sn U1RSn OUT
R-0-0h W1C-0h W1C-0h W1C-0h W1C-0h
7 6 5 4 3 2 1 0
RESERVED HWBISTn RESERVED NMIWDRSn WDRSn XRSn POR
R-0-0h W1C-0h R-0-0h W1C-0h W1C-0h W1C-0h W1C-0h

Table 3-96. RESCCLR Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R-0 0h Reserved
11 SIMRESET_XRSn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
10 SIMRESET_CPU1RSn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
9 ECAT_RESET_OUT W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
8 SCCRESETn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
7 RESERVED R-0 0h Reserved
5 HWBISTn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
4 RESERVED R-0 0h Reserved
3 NMIWDRSn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn

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Table 3-96. RESCCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
2 WDRSn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
1 XRSn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
0 POR W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn

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3.14.5.30 RESC Register (Offset = 80h) [reset = X]

RESC is shown in Figure 3-95 and described in Table 3-97.
Return to the Summary Table.
Reset Cause register

Figure 3-95. RESC Register

31 30 29 28 27 26 25 24
TRSTn_pin_sta XRSn_pin_stat RESERVED
tus us
R-X R-X R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED SIMRESET_XR SIMRESET_CP ECAT_RESET_ SCCRESETn
Sn U1RSn OUT
R-0-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h
7 6 5 4 3 2 1 0
RESERVED HWBISTn RESERVED NMIWDRSn WDRSn XRSn POR
R-0-0h R/W1S-0h R-0-0h R/W1S-0h R/W1S-0h R/W1S-1h R/W1S-1h

Table 3-97. RESC Register Field Descriptions

Bit Field Type Reset Description
31 TRSTn_pin_status R X Reading this bit provides the current status of TRSTn at the
respective C28x CPUs TRSTn input port. Reset value is reflective of
the pin status.
Reset type: PORESETn
30 XRSn_pin_status R X Reading this bit provides the current status of the XRSn pin. Reset
value is reflective of the pin status.
Reset type: PORESETn
29-12 RESERVED R-0 0h Reserved
11 SIMRESET_XRSn R/W1S 0h If this bit is set, indicates that the device was reset by
SIMRESET_XRSn
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn
10 SIMRESET_CPU1RSn R/W1S 0h If this bit is set, indicates that the device was reset by
SIMRESET_CPU1RSn
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn
9 ECAT_RESET_OUT R/W1S 0h If this bit is set, indicates that the device was reset by
ECAT_RESET_OUT
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn
8 SCCRESETn R/W1S 0h If this bit is set, indicates that the device was reset by SCCRESETn
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn
7 RESERVED R-0 0h Reserved
5 HWBISTn R/W1S 0h If this bit is set, indicates that the device was reset by HWBISTn
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn
4 RESERVED R-0 0h Reserved

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Table 3-97. RESC Register Field Descriptions (continued)

Bit Field Type Reset Description
3 NMIWDRSn R/W1S 0h If this bit is set, indicates that the device was reset by NMIWDRSn.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
To know the exact cause of NMI after the reset, software needs to
read CPU1/2.NMISHDFLG registers
Reset type: PORESETn
2 WDRSn R/W1S 0h If this bit is set, indicates that the device was reset by WDRSn
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn
1 XRSn R/W1S 1h If this bit is set, indicates that the device was reset by XRSn
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn
0 POR R/W1S 1h If this bit is set, indicates that the device was reset by POR
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn

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3.14.6 CPU_ID_REGS Registers

Table 3-98 lists the CPU_ID_REGS registers. All register offset addresses not listed in Table 3-98 should
be considered as reserved locations and the register contents should not be modified.

Table 3-98. CPU_ID_REGS Registers

Offset Acronym Register Name Write Protection Section
0h CPUID Indicates CPU1 or CPU2 Go

Complex bit access types are encoded to fit into small table cells. Table 3-99 shows the codes that are
used for access types in this section.

Table 3-99. CPU_ID_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.6.1 CPUID Register (Offset = 0h) [reset = X]

CPUID is shown in Figure 3-96 and described in Table 3-100.
Return to the Summary Table.
This register can be used to identify on which CPU the code is executing.

Figure 3-96. CPUID Register

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0
CPUID
R-X

Table 3-100. CPUID Register Field Descriptions

Bit Field Type Reset Description
7-0 CPUID R X CPUID = 1 for CPU1, 2 for CPU2
Reset type: N/A

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3.14.7 CPU1_PERIPH_AC_REGS Registers

Table 3-101 lists the CPU1_PERIPH_AC_REGS registers. All register offset addresses not listed in
Table 3-101 should be considered as reserved locations and the register contents should not be modified.

Table 3-101. CPU1_PERIPH_AC_REGS Registers

Offset Acronym Register Name Write Protection Section
0h ADCA_AC ADCA Master Access Control Register EALLOW Go
2h ADCB_AC ADCB Master Access Control Register EALLOW Go
4h ADCC_AC ADCC Master Access Control Register EALLOW Go
6h ADCD_AC ADCD Master Access Control Register EALLOW Go
10h CMPSS1_AC CMPSS1 Master Access Control Register EALLOW Go
12h CMPSS2_AC CMPSS2 Master Access Control Register EALLOW Go
14h CMPSS3_AC CMPSS3 Master Access Control Register EALLOW Go
16h CMPSS4_AC CMPSS4 Master Access Control Register EALLOW Go
18h CMPSS5_AC CMPSS5 Master Access Control Register EALLOW Go
1Ah CMPSS6_AC CMPSS6 Master Access Control Register EALLOW Go
1Ch CMPSS7_AC CMPSS7 Master Access Control Register EALLOW Go
1Eh CMPSS8_AC CMPSS8 Master Access Control Register EALLOW Go
28h DACA_AC DACA Master Access Control Register EALLOW Go
2Ah DACB_AC DACB Master Access Control Register EALLOW Go
2Ch DACC_AC DACC Master Access Control Register EALLOW Go
48h EPWM1_AC EPWM1 Master Access Control Register EALLOW Go
4Ah EPWM2_AC EPWM2 Master Access Control Register EALLOW Go
4Ch EPWM3_AC EPWM3 Master Access Control Register EALLOW Go
4Eh EPWM4_AC EPWM4 Master Access Control Register EALLOW Go
50h EPWM5_AC EPWM5 Master Access Control Register EALLOW Go
52h EPWM6_AC EPWM6 Master Access Control Register EALLOW Go
54h EPWM7_AC EPWM7 Master Access Control Register EALLOW Go
56h EPWM8_AC EPWM8 Master Access Control Register EALLOW Go
58h EPWM9_AC EPWM9 Master Access Control Register EALLOW Go
5Ah EPWM10_AC EPWM10 Master Access Control Register EALLOW Go
5Ch EPWM11_AC EPWM11 Master Access Control Register EALLOW Go
5Eh EPWM12_AC EPWM12 Master Access Control Register EALLOW Go
60h EPWM13_AC EPWM13 Master Access Control Register EALLOW Go
62h EPWM14_AC EPWM14 Master Access Control Register EALLOW Go
64h EPWM15_AC EPWM15 Master Access Control Register EALLOW Go
66h EPWM16_AC EPWM16 Master Access Control Register EALLOW Go
70h EQEP1_AC EQEP1 Master Access Control Register EALLOW Go
72h EQEP2_AC EQEP2 Master Access Control Register EALLOW Go
74h EQEP3_AC EQEP3 Master Access Control Register EALLOW Go
80h ECAP1_AC ECAP1 Master Access Control Register EALLOW Go
82h ECAP2_AC ECAP2 Master Access Control Register EALLOW Go
84h ECAP3_AC ECAP3 Master Access Control Register EALLOW Go
86h ECAP4_AC ECAP4 Master Access Control Register EALLOW Go
88h ECAP5_AC ECAP5 Master Access Control Register EALLOW Go
8Ah ECAP6_AC ECAP6 Master Access Control Register EALLOW Go
8Ch ECAP7_AC ECAP7 Master Access Control Register EALLOW Go
A8h SDFM1_AC SDFM1 Master Access Control Register EALLOW Go
AAh SDFM2_AC SDFM2 Master Access Control Register EALLOW Go
B0h CLB1_AC CLB1 Master Access Control Register EALLOW Go

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Table 3-101. CPU1_PERIPH_AC_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
B2h CLB2_AC CLB2 Master Access Control Register EALLOW Go
B4h CLB3_AC CLB3 Master Access Control Register EALLOW Go
B6h CLB4_AC CLB4 Master Access Control Register EALLOW Go
110h SPIA_AC SPIA Master Access Control Register EALLOW Go
112h SPIB_AC SPIB Master Access Control Register EALLOW Go
114h SPIC_AC SPIC Master Access Control Register EALLOW Go
116h SPID_AC SPID Master Access Control Register EALLOW Go
130h PMBUS_A_AC PMBUSA Master Access Control Register EALLOW Go
140h CAN_A_AC CAN_A Master Access Control Register EALLOW Go
142h CAN_B_AC CAN_B Master Access Control Register EALLOW Go
150h MCBSPA_AC MCBSPA Master Access Control Register EALLOW Go
152h MCBSPB_AC MCBSPB Master Access Control Register EALLOW Go
180h USBA_AC USBA Master Access Control Register EALLOW Go
1A8h HRPWM_AC HRPWM Master Access Control Register EALLOW Go
1AAh ETHERCAT_AC ETHERCAT Master Access Control Register EALLOW Go
1B0h FSIATX_AC FSIATX Master Access Control Register EALLOW Go
1B2h FSIARX_AC FSIARX Master Access Control Register EALLOW Go
1B4h FSIBTX_AC FSIBTX Master Access Control Register EALLOW Go
1B6h FSIBRX_AC FSIBRX Master Access Control Register EALLOW Go
1BAh FSICRX_AC FSICRX Master Access Control Register EALLOW Go
1BEh FSIDRX_AC FSIDRX Master Access Control Register EALLOW Go
1C2h FSIERX_AC FSIERX Master Access Control Register EALLOW Go
1C6h FSIFRX_AC FSIFRX Master Access Control Register EALLOW Go
1CAh FSIGRX_AC FSIGRX Master Access Control Register EALLOW Go
1CEh FSIHRX_AC FSIHRX Master Access Control Register EALLOW Go
1FEh PERIPH_AC_LOCK Lock Register to stop Write access to peripheral EALLOW Go
Access register.

Complex bit access types are encoded to fit into small table cells. Table 3-102 shows the codes that are
used for access types in this section.

Table 3-102. CPU1_PERIPH_AC_REGS Access Type

Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables

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Table 3-102. CPU1_PERIPH_AC_REGS Access Type

Codes (continued)
Access Type Code Description
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.7.1 ADCA_AC Register (Offset = 0h) [reset = 3Fh]

ADCA_AC is shown in Figure 3-97 and described in Table 3-103.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-97. ADCA_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-103. ADCA_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.2 ADCB_AC Register (Offset = 2h) [reset = 3Fh]

ADCB_AC is shown in Figure 3-98 and described in Table 3-104.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-98. ADCB_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-104. ADCB_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.3 ADCC_AC Register (Offset = 4h) [reset = 3Fh]

ADCC_AC is shown in Figure 3-99 and described in Table 3-105.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-99. ADCC_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-105. ADCC_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.4 ADCD_AC Register (Offset = 6h) [reset = 3Fh]

ADCD_AC is shown in Figure 3-100 and described in Table 3-106.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-100. ADCD_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-106. ADCD_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.5 CMPSS1_AC Register (Offset = 10h) [reset = 3Fh]

CMPSS1_AC is shown in Figure 3-101 and described in Table 3-107.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-101. CMPSS1_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-107. CMPSS1_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.6 CMPSS2_AC Register (Offset = 12h) [reset = 3Fh]

CMPSS2_AC is shown in Figure 3-102 and described in Table 3-108.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-102. CMPSS2_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-108. CMPSS2_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.7 CMPSS3_AC Register (Offset = 14h) [reset = 3Fh]

CMPSS3_AC is shown in Figure 3-103 and described in Table 3-109.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-103. CMPSS3_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-109. CMPSS3_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.8 CMPSS4_AC Register (Offset = 16h) [reset = 3Fh]

CMPSS4_AC is shown in Figure 3-104 and described in Table 3-110.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-104. CMPSS4_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-110. CMPSS4_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.9 CMPSS5_AC Register (Offset = 18h) [reset = 3Fh]

CMPSS5_AC is shown in Figure 3-105 and described in Table 3-111.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-105. CMPSS5_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-111. CMPSS5_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.10 CMPSS6_AC Register (Offset = 1Ah) [reset = 3Fh]

CMPSS6_AC is shown in Figure 3-106 and described in Table 3-112.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-106. CMPSS6_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-112. CMPSS6_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.11 CMPSS7_AC Register (Offset = 1Ch) [reset = 3Fh]

CMPSS7_AC is shown in Figure 3-107 and described in Table 3-113.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-107. CMPSS7_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-113. CMPSS7_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.12 CMPSS8_AC Register (Offset = 1Eh) [reset = 3Fh]

CMPSS8_AC is shown in Figure 3-108 and described in Table 3-114.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-108. CMPSS8_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-114. CMPSS8_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.13 DACA_AC Register (Offset = 28h) [reset = 3Fh]

DACA_AC is shown in Figure 3-109 and described in Table 3-115.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-109. DACA_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-115. DACA_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.14 DACB_AC Register (Offset = 2Ah) [reset = 3Fh]

DACB_AC is shown in Figure 3-110 and described in Table 3-116.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-110. DACB_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-116. DACB_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.15 DACC_AC Register (Offset = 2Ch) [reset = 3Fh]

DACC_AC is shown in Figure 3-111 and described in Table 3-117.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-111. DACC_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-117. DACC_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.16 EPWM1_AC Register (Offset = 48h) [reset = 3Fh]

EPWM1_AC is shown in Figure 3-112 and described in Table 3-118.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-112. EPWM1_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-118. EPWM1_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.17 EPWM2_AC Register (Offset = 4Ah) [reset = 3Fh]

EPWM2_AC is shown in Figure 3-113 and described in Table 3-119.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-113. EPWM2_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-119. EPWM2_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.18 EPWM3_AC Register (Offset = 4Ch) [reset = 3Fh]

EPWM3_AC is shown in Figure 3-114 and described in Table 3-120.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-114. EPWM3_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-120. EPWM3_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.19 EPWM4_AC Register (Offset = 4Eh) [reset = 3Fh]

EPWM4_AC is shown in Figure 3-115 and described in Table 3-121.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-115. EPWM4_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-121. EPWM4_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.20 EPWM5_AC Register (Offset = 50h) [reset = 3Fh]

EPWM5_AC is shown in Figure 3-116 and described in Table 3-122.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-116. EPWM5_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-122. EPWM5_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.21 EPWM6_AC Register (Offset = 52h) [reset = 3Fh]

EPWM6_AC is shown in Figure 3-117 and described in Table 3-123.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-117. EPWM6_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-123. EPWM6_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.22 EPWM7_AC Register (Offset = 54h) [reset = 3Fh]

EPWM7_AC is shown in Figure 3-118 and described in Table 3-124.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-118. EPWM7_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-124. EPWM7_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.23 EPWM8_AC Register (Offset = 56h) [reset = 3Fh]

EPWM8_AC is shown in Figure 3-119 and described in Table 3-125.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-119. EPWM8_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-125. EPWM8_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.24 EPWM9_AC Register (Offset = 58h) [reset = 3Fh]

EPWM9_AC is shown in Figure 3-120 and described in Table 3-126.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-120. EPWM9_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-126. EPWM9_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.25 EPWM10_AC Register (Offset = 5Ah) [reset = 3Fh]

EPWM10_AC is shown in Figure 3-121 and described in Table 3-127.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-121. EPWM10_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-127. EPWM10_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.26 EPWM11_AC Register (Offset = 5Ch) [reset = 3Fh]

EPWM11_AC is shown in Figure 3-122 and described in Table 3-128.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-122. EPWM11_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-128. EPWM11_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.27 EPWM12_AC Register (Offset = 5Eh) [reset = 3Fh]

EPWM12_AC is shown in Figure 3-123 and described in Table 3-129.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-123. EPWM12_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-129. EPWM12_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.28 EPWM13_AC Register (Offset = 60h) [reset = 3Fh]

EPWM13_AC is shown in Figure 3-124 and described in Table 3-130.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-124. EPWM13_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-130. EPWM13_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.29 EPWM14_AC Register (Offset = 62h) [reset = 3Fh]

EPWM14_AC is shown in Figure 3-125 and described in Table 3-131.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-125. EPWM14_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-131. EPWM14_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.30 EPWM15_AC Register (Offset = 64h) [reset = 3Fh]

EPWM15_AC is shown in Figure 3-126 and described in Table 3-132.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-126. EPWM15_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-132. EPWM15_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.31 EPWM16_AC Register (Offset = 66h) [reset = 3Fh]

EPWM16_AC is shown in Figure 3-127 and described in Table 3-133.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-127. EPWM16_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-133. EPWM16_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.32 EQEP1_AC Register (Offset = 70h) [reset = 3Fh]

EQEP1_AC is shown in Figure 3-128 and described in Table 3-134.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-128. EQEP1_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-134. EQEP1_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.33 EQEP2_AC Register (Offset = 72h) [reset = 3Fh]

EQEP2_AC is shown in Figure 3-129 and described in Table 3-135.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-129. EQEP2_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-135. EQEP2_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.34 EQEP3_AC Register (Offset = 74h) [reset = 3Fh]

EQEP3_AC is shown in Figure 3-130 and described in Table 3-136.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-130. EQEP3_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-136. EQEP3_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.35 ECAP1_AC Register (Offset = 80h) [reset = 3Fh]

ECAP1_AC is shown in Figure 3-131 and described in Table 3-137.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-131. ECAP1_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-137. ECAP1_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.36 ECAP2_AC Register (Offset = 82h) [reset = 3Fh]

ECAP2_AC is shown in Figure 3-132 and described in Table 3-138.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-132. ECAP2_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-138. ECAP2_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.37 ECAP3_AC Register (Offset = 84h) [reset = 3Fh]

ECAP3_AC is shown in Figure 3-133 and described in Table 3-139.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-133. ECAP3_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-139. ECAP3_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.38 ECAP4_AC Register (Offset = 86h) [reset = 3Fh]

ECAP4_AC is shown in Figure 3-134 and described in Table 3-140.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-134. ECAP4_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-140. ECAP4_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.39 ECAP5_AC Register (Offset = 88h) [reset = 3Fh]

ECAP5_AC is shown in Figure 3-135 and described in Table 3-141.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-135. ECAP5_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-141. ECAP5_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.40 ECAP6_AC Register (Offset = 8Ah) [reset = 3Fh]

ECAP6_AC is shown in Figure 3-136 and described in Table 3-142.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-136. ECAP6_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-142. ECAP6_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.41 ECAP7_AC Register (Offset = 8Ch) [reset = 3Fh]

ECAP7_AC is shown in Figure 3-137 and described in Table 3-143.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-137. ECAP7_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-143. ECAP7_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.42 SDFM1_AC Register (Offset = A8h) [reset = 3Fh]

SDFM1_AC is shown in Figure 3-138 and described in Table 3-144.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-138. SDFM1_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-144. SDFM1_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.43 SDFM2_AC Register (Offset = AAh) [reset = 3Fh]

SDFM2_AC is shown in Figure 3-139 and described in Table 3-145.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-139. SDFM2_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-145. SDFM2_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.44 CLB1_AC Register (Offset = B0h) [reset = 3Fh]

CLB1_AC is shown in Figure 3-140 and described in Table 3-146.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-140. CLB1_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h

Table 3-146. CLB1_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.45 CLB2_AC Register (Offset = B2h) [reset = 3Fh]

CLB2_AC is shown in Figure 3-141 and described in Table 3-147.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-141. CLB2_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h

Table 3-147. CLB2_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.46 CLB3_AC Register (Offset = B4h) [reset = 3Fh]

CLB3_AC is shown in Figure 3-142 and described in Table 3-148.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-142. CLB3_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h

Table 3-148. CLB3_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.47 CLB4_AC Register (Offset = B6h) [reset = 3Fh]

CLB4_AC is shown in Figure 3-143 and described in Table 3-149.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-143. CLB4_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h

Table 3-149. CLB4_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.48 SPIA_AC Register (Offset = 110h) [reset = 3Fh]

SPIA_AC is shown in Figure 3-144 and described in Table 3-150.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-144. SPIA_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-150. SPIA_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.49 SPIB_AC Register (Offset = 112h) [reset = 3Fh]

SPIB_AC is shown in Figure 3-145 and described in Table 3-151.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-145. SPIB_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-151. SPIB_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.50 SPIC_AC Register (Offset = 114h) [reset = 3Fh]

SPIC_AC is shown in Figure 3-146 and described in Table 3-152.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-146. SPIC_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-152. SPIC_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.51 SPID_AC Register (Offset = 116h) [reset = 3Fh]

SPID_AC is shown in Figure 3-147 and described in Table 3-153.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-147. SPID_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-153. SPID_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.52 PMBUS_A_AC Register (Offset = 130h) [reset = 3Fh]

PMBUS_A_AC is shown in Figure 3-148 and described in Table 3-154.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-148. PMBUS_A_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-154. PMBUS_A_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.53 CAN_A_AC Register (Offset = 140h) [reset = 3Fh]

CAN_A_AC is shown in Figure 3-149 and described in Table 3-155.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-149. CAN_A_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h

Table 3-155. CAN_A_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.54 CAN_B_AC Register (Offset = 142h) [reset = 3Fh]

CAN_B_AC is shown in Figure 3-150 and described in Table 3-156.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-150. CAN_B_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h

Table 3-156. CAN_B_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.55 MCBSPA_AC Register (Offset = 150h) [reset = 3Fh]

MCBSPA_AC is shown in Figure 3-151 and described in Table 3-157.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-151. MCBSPA_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-157. MCBSPA_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.56 MCBSPB_AC Register (Offset = 152h) [reset = 3Fh]

MCBSPB_AC is shown in Figure 3-152 and described in Table 3-158.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-152. MCBSPB_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-158. MCBSPB_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.57 USBA_AC Register (Offset = 180h) [reset = 3Fh]

USBA_AC is shown in Figure 3-153 and described in Table 3-159.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-153. USBA_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h

Table 3-159. USBA_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.58 HRPWM_AC Register (Offset = 1A8h) [reset = 3Fh]

HRPWM_AC is shown in Figure 3-154 and described in Table 3-160.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.
Note: Following registers are controlled by this register:
HRPWR
HRCAL
HRPRD
HRCNT0
HRCNT1
HRMSTEP

Figure 3-154. HRPWM_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-160. HRPWM_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Note: Following registers are covered by this register
HRPWR
HRCAL
HRPRD
HRCNT0
HRCNT1
HRMSTEP
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Note: Following registers are covered by this register
HRPWR
HRCAL
HRPRD
HRCNT0
HRCNT1
HRMSTEP
Reset type: XRSn

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Table 3-160. HRPWM_AC Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Note: Following registers are covered by this register
HRPWR
HRCAL
HRPRD
HRCNT0
HRCNT1
HRMSTEP
Reset type: XRSn

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3.14.7.59 ETHERCAT_AC Register (Offset = 1AAh) [reset = 3Fh]

ETHERCAT_AC is shown in Figure 3-155 and described in Table 3-161.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-155. ETHERCAT_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CPU1_ACC
R-0-0h R/W-3h R/W-3h

Table 3-161. ETHERCAT_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.60 FSIATX_AC Register (Offset = 1B0h) [reset = 3Fh]

FSIATX_AC is shown in Figure 3-156 and described in Table 3-162.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-156. FSIATX_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-162. FSIATX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.61 FSIARX_AC Register (Offset = 1B2h) [reset = 3Fh]

FSIARX_AC is shown in Figure 3-157 and described in Table 3-163.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-157. FSIARX_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-163. FSIARX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.62 FSIBTX_AC Register (Offset = 1B4h) [reset = 3Fh]

FSIBTX_AC is shown in Figure 3-158 and described in Table 3-164.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-158. FSIBTX_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-164. FSIBTX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.63 FSIBRX_AC Register (Offset = 1B6h) [reset = 3Fh]

FSIBRX_AC is shown in Figure 3-159 and described in Table 3-165.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-159. FSIBRX_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-165. FSIBRX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.64 FSICRX_AC Register (Offset = 1BAh) [reset = 3Fh]

FSICRX_AC is shown in Figure 3-160 and described in Table 3-166.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-160. FSICRX_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-166. FSICRX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.65 FSIDRX_AC Register (Offset = 1BEh) [reset = 3Fh]

FSIDRX_AC is shown in Figure 3-161 and described in Table 3-167.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-161. FSIDRX_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-167. FSIDRX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.66 FSIERX_AC Register (Offset = 1C2h) [reset = 3Fh]

FSIERX_AC is shown in Figure 3-162 and described in Table 3-168.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-162. FSIERX_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-168. FSIERX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.67 FSIFRX_AC Register (Offset = 1C6h) [reset = 3Fh]

FSIFRX_AC is shown in Figure 3-163 and described in Table 3-169.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-163. FSIFRX_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-169. FSIFRX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.68 FSIGRX_AC Register (Offset = 1CAh) [reset = 3Fh]

FSIGRX_AC is shown in Figure 3-164 and described in Table 3-170.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-164. FSIGRX_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-170. FSIGRX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.69 FSIHRX_AC Register (Offset = 1CEh) [reset = 3Fh]

FSIHRX_AC is shown in Figure 3-165 and described in Table 3-171.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding
connected master.

Figure 3-165. FSIHRX_AC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-171. FSIHRX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.14.7.70 PERIPH_AC_LOCK Register (Offset = 1FEh) [reset = 0h]

PERIPH_AC_LOCK is shown in Figure 3-166 and described in Table 3-172.
Return to the Summary Table.
Based on status bit control the Access registers are either RD/WR or RD only.

Figure 3-166. PERIPH_AC_LOCK Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED LOCK_AC_WR
R-0-0h R/WSonce-0h

Table 3-172. PERIPH_AC_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 LOCK_AC_WR R/WSonce 0h Defines Access control definition for the CPUx as:
1: Access Control registers are Read Only
0: Read/Write Access allowed to Access Control registers.
Writing '1' sets the bit, writing '0' has no effect.
Reset type: CPUx.SYSRSn

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3.14.8 CPUTIMER_REGS Registers

Table 3-173 lists the CPUTIMER_REGS registers. All register offset addresses not listed in Table 3-173
should be considered as reserved locations and the register contents should not be modified.

Table 3-173. CPUTIMER_REGS Registers

Offset Acronym Register Name Write Protection Section
0h TIM CPU-Timer, Counter Register Go
2h PRD CPU-Timer, Period Register Go
4h TCR CPU-Timer, Control Register Go
6h TPR CPU-Timer, Prescale Register Go
7h TPRH CPU-Timer, Prescale Register High Go

Complex bit access types are encoded to fit into small table cells. Table 3-174 shows the codes that are
used for access types in this section.

Table 3-174. CPUTIMER_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
Write Type
W W Write
W1C W Write
1C 1 to clear
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.8.1 TIM Register (Offset = 0h) [reset = FFFFh]

TIM is shown in Figure 3-167 and described in Table 3-175.
Return to the Summary Table.
CPU-Timer, Counter Register

Figure 3-167. TIM Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSW LSW
R/W-0h R/W-FFFFh

Table 3-175. TIM Register Field Descriptions

Bit Field Type Reset Description
31-16 MSW R/W 0h CPU-Timer Counter Registers
The TIMH register holds the high 16 bits of the current 32-bit count
of the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained in
the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn
15-0 LSW R/W FFFFh CPU-Timer Counter Registers
The TIM register holds the low 16 bits of the current 32-bit count of
the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained in
the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn

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3.14.8.2 PRD Register (Offset = 2h) [reset = 0001FFFFh]

PRD is shown in Figure 3-168 and described in Table 3-176.
Return to the Summary Table.
CPU-Timer, Period Register

Figure 3-168. PRD Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSW LSW
R/W-1h R/W-FFFFh

Table 3-176. PRD Register Field Descriptions

Bit Field Type Reset Description
31-16 MSW R/W 1h CPU-Timer Period Registers
The PRDH register holds the high 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn
15-0 LSW R/W FFFFh CPU-Timer Period Registers
The PRD register holds the low 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn

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3.14.8.3 TCR Register (Offset = 4h) [reset = 1h]

TCR is shown in Figure 3-169 and described in Table 3-177.
Return to the Summary Table.
CPU-Timer, Control Register

Figure 3-169. TCR Register

15 14 13 12 11 10 9 8
TIF TIE RESERVED FREE SOFT RESERVED
R/W1C-0h R/W-0h R-0h R/W-0h R/W-0h R-0h
7 6 5 4 3 2 1 0
RESERVED TRB TSS RESERVED
R-0h R/W-0h R/W-0h R-1h

Table 3-177. TCR Register Field Descriptions

Bit Field Type Reset Description
15 TIF R/W1C 0h CPU-Timer Overflow Flag.
TIF indicates whether a timer overflow has happened since TIF was
last cleared. TIF is not cleared automatically and does not need to
be cleared to enable the next timer interrupt.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer has not decremented to zero.
Writes of 0 are ignored.
1h (R/W) = This flag gets set when the CPU-timer decrements to
zero.
Writing a 1 to this bit clears the flag.
14 TIE R/W 0h CPU-Timer Interrupt Enable.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer interrupt is disabled.
1h (R/W) = The CPU-Timer interrupt is enabled. If the timer
decrements to zero, and TIE is set, the timer asserts its interrupt
request.
13-12 RESERVED R 0h Reserved
11 FREE R/W 0h If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run. If FREE is 0, then the SOFT bit controls the
emulation behavior.
Reset type: SYSRSn
0h (R/W) = Stop after the next decrement of the TIMH:TIM (hard
stop)
(SOFT bit controls the emulation behavior)
1h (R/W) = Free Run
(SOFT bit is don't care, counter is free running)
10 SOFT R/W 0h If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run (that is, free runs). In this case, SOFT is a
don't care. But if FREE is 0, then SOFT takes effect.
Reset type: SYSRSn
0h (R/W) = Stop after the next decrement of the TIMH:TIM (hard
stop).
(ONLY if FREE=0, if FREE=1 this bit is don't care)
1h (R/W) = Stop after the TIMH:TIM decrements to 0 (soft stop)

In the SOFT STOP mode, the timer generates an interrupt before

shutting down (since reaching 0 is the interrupt causing condition).
(ONLY if FREE=0, if FREE=1 this bit is don't care)
9-6 RESERVED R 0h Reserved

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Table 3-177. TCR Register Field Descriptions (continued)

Bit Field Type Reset Description
5 TRB R/W 0h Timer reload
Reset type: SYSRSn
0h (R/W) = The TRB bit is always read as zero. Writes of 0 are
ignored.
1h (R/W) = When you write a 1 to TRB, the TIMH:TIM is loaded with
the value in the PRDH:PRD,
and the prescaler counter (PSCH:PSC) is loaded with the value in
the timer dividedown
register (TDDRH:TDDR).
4 TSS R/W 0h CPU-Timer stop status bit.
TSS is a 1-bit flag that stops or starts the CPU-timer.
Reset type: SYSRSn
0h (R/W) = Reads of 0 indicate the CPU-timer is running.
To start or restart the CPU-timer, set TSS to 0. At reset, TSS is
cleared to 0 and the
CPU-timer immediately starts.
1h (R/W) = Reads of 1 indicate that the CPU-timer is stopped.
To stop the CPU-timer, set TSS to 1.
3-0 RESERVED R 1h Reserved

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3.14.8.4 TPR Register (Offset = 6h) [reset = 0h]

TPR is shown in Figure 3-170 and described in Table 3-178.
Return to the Summary Table.
CPU-Timer, Prescale Register

Figure 3-170. TPR Register

15 14 13 12 11 10 9 8
PSC
R-0h
7 6 5 4 3 2 1 0
TDDR
R/W-0h

Table 3-178. TPR Register Field Descriptions

Bit Field Type Reset Description
15-8 PSC R 0h CPU-Timer Prescale Counter.
These bits hold the current prescale count for the timer. For every
timer clock source cycle that the PSCH:PSC value is greater than 0,
the PSCH:PSC decrements by one. One timer clock (output of the
timer prescaler) cycle after the PSCH:PSC reaches 0, the
PSCH:PSC is loaded with the contents of the TDDRH:TDDR, and
the timer counter register (TIMH:TIM) decrements by one. The
PSCH:PSC is also reloaded whenever the timer reload bit (TRB) is
set by software. The PSCH:PSC can be checked by reading the
register, but it cannot be set directly. It must get its value from the
timer divide-down register
(TDDRH:TDDR). At reset, the PSCH:PSC is set to 0.
Reset type: SYSRSn
7-0 TDDR R/W 0h CPU-Timer Divide-Down.
Every (TDDRH:TDDR + 1) timer clock source cycles, the timer
counter register (TIMH:TIM) decrements by one. At reset, the
TDDRH:TDDR bits are cleared to 0. To increase the overall timer
count by an integer factor, write this factor minus one to the
TDDRH:TDDR bits. When the prescaler counter (PSCH:PSC) value
is 0, one timer clock source cycle later, the contents of the
TDDRH:TDDR reload the PSCH:PSC, and the TIMH:TIM
decrements by one. TDDRH:TDDR also reloads the PSCH:PSC
whenever the timer reload bit (TRB) is set by software.
Reset type: SYSRSn

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3.14.8.5 TPRH Register (Offset = 7h) [reset = 0h]

TPRH is shown in Figure 3-171 and described in Table 3-179.
Return to the Summary Table.
CPU-Timer, Prescale Register High

Figure 3-171. TPRH Register

15 14 13 12 11 10 9 8
PSCH
R-0h
7 6 5 4 3 2 1 0
TDDRH
R/W-0h

Table 3-179. TPRH Register Field Descriptions

Bit Field Type Reset Description
15-8 PSCH R 0h See description of TIMERxTPR.
Reset type: SYSRSn
7-0 TDDRH R/W 0h See description of TIMERxTPR.
Reset type: SYSRSn

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3.14.9 DEV_CFG_REGS Registers

Table 3-180 lists the DEV_CFG_REGS registers. All register offset addresses not listed in Table 3-180
should be considered as reserved locations and the register contents should not be modified.

Table 3-180. DEV_CFG_REGS Registers

Offset Acronym Register Name Write Protection Section
0h DEVCFGLOCK1 Lock bit for DEVCFG registers EALLOW Go
2h DEVCFGLOCK2 Lock bit for DEVCFG registers EALLOW Go
8h PARTIDL Lower 32-bit of Device PART Identification Go
Number
Ah PARTIDH Upper 32-bit of Device PART Identification Go
Number
Ch REVID Device Revision Number Go
60h PERCNF1 Peripheral Configuration register Go
74h FUSEERR e-Fuse error Status register Go
82h SOFTPRES0 Processing Block Software Reset register EALLOW Go
84h SOFTPRES1 EMIF Software Reset register EALLOW Go
86h SOFTPRES2 Peripheral Software Reset register EALLOW Go
88h SOFTPRES3 Peripheral Software Reset register EALLOW Go
8Ah SOFTPRES4 Peripheral Software Reset register EALLOW Go
8Eh SOFTPRES6 Peripheral Software Reset register EALLOW Go
90h SOFTPRES7 Peripheral Software Reset register EALLOW Go
92h SOFTPRES8 Peripheral Software Reset register EALLOW Go
94h SOFTPRES9 Peripheral Software Reset register EALLOW Go
96h SOFTPRES10 Peripheral Software Reset register EALLOW Go
98h SOFTPRES11 Peripheral Software Reset register EALLOW Go
9Ch SOFTPRES13 Peripheral Software Reset register EALLOW Go
9Eh SOFTPRES14 Peripheral Software Reset register EALLOW Go
A2h SOFTPRES16 Peripheral Software Reset register EALLOW Go
A4h SOFTPRES17 Reserved Peripheral Software Reset register EALLOW Go
A6h SOFTPRES18 Reserved Peripheral Software Reset register EALLOW Go
AAh SOFTPRES20 Peripheral Software Reset register EALLOW Go
ACh SOFTPRES21 Peripheral Software Reset register EALLOW Go
B0h SOFTPRES23 Peripheral Software Reset register EALLOW Go
D6h CPUSEL0 CPU Select register for common peripherals EALLOW Go
D8h CPUSEL1 CPU Select register for common peripherals EALLOW Go
DAh CPUSEL2 CPU Select register for common peripherals EALLOW Go
DEh CPUSEL4 CPU Select register for common peripherals EALLOW Go
E0h CPUSEL5 CPU Select register for common peripherals EALLOW Go
E2h CPUSEL6 CPU Select register for common peripherals EALLOW Go
E4h CPUSEL7 CPU Select register for common peripherals EALLOW Go
E6h CPUSEL8 CPU Select register for common peripherals EALLOW Go
E8h CPUSEL9 CPU Select register for common peripherals EALLOW Go
ECh CPUSEL11 CPU Select register for common peripherals EALLOW Go
EEh CPUSEL12 CPU Select register for common peripherals EALLOW Go
F2h CPUSEL14 CPU Select register for common peripherals EALLOW Go
F4h CPUSEL15 CPU Select register for common peripherals EALLOW Go
F6h CPUSEL16 CPU Select register for common peripherals EALLOW Go
FAh CPUSEL18 CPU Select register for common peripherals EALLOW Go
108h CPUSEL25 CPU Select register for common peripherals EALLOW Go

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Table 3-180. DEV_CFG_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
122h CPU2RESCTL CPU2 Reset Control Register EALLOW Go
124h RSTSTAT Reset Status register for secondary C28x CPUs Go
125h LPMSTAT LPM Status Register for secondary C28x CPUs Go
19Ah USBTYPE Configures USB Type for the device EALLOW Go
19Bh ECAPTYPE Configures ECAP Type for the device EALLOW Go
19Ch SDFMTYPE Configures SDFM Type for the device EALLOW Go
19Eh MEMMAPTYPE Configures Memory Map Type for the device EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-181 shows the codes that are
used for access types in this section.

Table 3-181. DEV_CFG_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WOnce W Write
Once Write once
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.9.1 DEVCFGLOCK1 Register (Offset = 0h) [reset = 0h]

DEVCFGLOCK1 is shown in Figure 3-172 and described in Table 3-182.
Return to the Summary Table.
Lock bit for DEVCFG registers
The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are
always allowed
Note:
Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any
bit of this register has no effect

Figure 3-172. DEVCFGLOCK1 Register

31 30 29 28 27 26 25 24
RESERVED CPUSEL25 RESERVED
R-0-0h R/WSonce-0h R-0-0h
23 22 21 20 19 18 17 16
RESERVED CPUSEL18 CPUSEL16
R-0-0h R/WSonce-0h R/WSonce-0h
15 14 13 12 11 10 9 8
CPUSEL15 CPUSEL14 CPUSEL12 CPUSEL11 CPUSEL9 CPUSEL8
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h
7 6 5 4 3 2 1 0
CPUSEL7 CPUSEL6 CPUSEL5 CPUSEL4 CPUSEL2 CPUSEL1 CPUSEL0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-182. DEVCFGLOCK1 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R-0 0h Reserved
25 CPUSEL25 R/WSonce 0h Lock bit for CPUSEL25 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
24-19 RESERVED R-0 0h Reserved
18 CPUSEL18 R/WSonce 0h Lock bit for CPUSEL18 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
16 CPUSEL16 R/WSonce 0h Lock bit for CPUSEL16 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
15 CPUSEL15 R/WSonce 0h Lock bit for CPUSEL15 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
14 CPUSEL14 R/WSonce 0h Lock bit for CPUSEL14 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
12 CPUSEL12 R/WSonce 0h Lock bit for CPUSEL12 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn

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Table 3-182. DEVCFGLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
11 CPUSEL11 R/WSonce 0h Lock bit for CPUSEL11 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
9 CPUSEL9 R/WSonce 0h Lock bit for CPUSEL9 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
8 CPUSEL8 R/WSonce 0h Lock bit for CPUSEL8 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
7 CPUSEL7 R/WSonce 0h Lock bit for CPUSEL7 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
6 CPUSEL6 R/WSonce 0h Lock bit for CPUSEL6 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
5 CPUSEL5 R/WSonce 0h Lock bit for CPUSEL5 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
4 CPUSEL4 R/WSonce 0h Lock bit for CPUSEL4 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
2 CPUSEL2 R/WSonce 0h Lock bit for CPUSEL2 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
1 CPUSEL1 R/WSonce 0h Lock bit for CPUSEL1 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
0 CPUSEL0 R/WSonce 0h Lock bit for CPUSEL0 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn

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3.14.9.2 DEVCFGLOCK2 Register (Offset = 2h) [reset = 0h]

DEVCFGLOCK2 is shown in Figure 3-173 and described in Table 3-183.
Return to the Summary Table.
Lock bit for DEVCFG registers
The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are
always allowed
Note:
Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any
bit of this register has no effect

Figure 3-173. DEVCFGLOCK2 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED
R-0-0h

Table 3-183. DEVCFGLOCK2 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved

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3.14.9.3 PARTIDL Register (Offset = 8h) [reset = X]

PARTIDL is shown in Figure 3-174 and described in Table 3-184.
Return to the Summary Table.
Lower 32-bit of Device PART Identification Number

Figure 3-174. PARTIDL Register

31 30 29 28 27 26 25 24
PARTID_FORMAT_REVISION RESERVED
R/W-2h R-0h
23 22 21 20 19 18 17 16
FLASH_SIZE
R/W-7h
15 14 13 12 11 10 9 8
RESERVED INSTASPIN PIN_COUNT
R-0h R/W-1h R/W-X
7 6 5 4 3 2 1 0
QUAL RESERVED RESERVED RESERVED
R/W-X R-0h R/W-0h R/W-0h

Table 3-184. PARTIDL Register Field Descriptions

Bit Field Type Reset Description
31-28 PARTID_FORMAT_REVI R/W 2h Loaded from OTP by boot ROM
SION 0xF = invalid PART ID (assume max config in flash tools)
0x0 = first revision of part id format
0x1 = second revision of format
0x2 = third revision of part id format
Reset type: PORESETn
27-24 RESERVED R 0h Reserved
23-16 FLASH_SIZE R/W 7h 0x8 - 1024KB
0x7 - 512KB
0x6 - 256KB
0x5 - 128KB
0x4 - 64KB
0x3 - 32KB
Reset type: PORESETn
15 RESERVED R 0h Reserved
14-13 INSTASPIN R/W 1h 0 = InstaSPIN Motion (Fast+Spin)
1 = InstaSPIN-FOC
2 = NONE
3 = NONE
Reset type: PORESETn
10-8 PIN_COUNT R/W X 0 = 56 pin (Reserved)
1 = 64 pin (Q100)
2 = 64 pin
3 = 80 pin
4 = 48 pin
5 = 100 pin (Reserved)
6 = 176 pin
7 = 337 pin
Reset type: PORESETn
7-6 QUAL R/W X 0 = Engineering sample.(TMX)
1 = Pilot production (TMP)
2 = Fully qualified (TMS)
Reset type: PORESETn
5 RESERVED R 0h Reserved
4-3 RESERVED R/W 0h Reserved
2-0 RESERVED R/W 0h Reserved

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3.14.9.4 PARTIDH Register (Offset = Ah) [reset = X]

PARTIDH is shown in Figure 3-175 and described in Table 3-185.
Return to the Summary Table.
Upper 32-bit of Device PART Identification Number

Figure 3-175. PARTIDH Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEVICE_CLASS_ID PARTNO
R-3h R/W-X
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAMILY RESERVED RESERVED
R/W-X R-0h R-0h

Table 3-185. PARTIDH Register Field Descriptions

Bit Field Type Reset Description
31-24 DEVICE_CLASS_ID R 3h Device Class ID
Reset type: PORESETn
23-16 PARTNO R/W X Part Number Designator
0xFF - F28388x
0xFD - F28386x
0xFB - F28384x
Reset type: PORESETn
15-8 FAMILY R/W X Device Family
0x3 - DUAL CORE
0x4 - SINGLE CORE
Other values Reserved
Reset type: PORESETn
Reset type: PORESETn
7-4 RESERVED R 0h Reserved
3-0 RESERVED R 0h Reserved

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3.14.9.5 REVID Register (Offset = Ch) [reset = 0h]

REVID is shown in Figure 3-176 and described in Table 3-186.
Return to the Summary Table.
Device Revision Number

Figure 3-176. REVID Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED REVID
R-0-0h R-0h

Table 3-186. REVID Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-0 REVID R 0h These 32-bits specify the silicon revision. See your device specific
datasheet for details.
Reset type: N/A

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3.14.9.6 PERCNF1 Register (Offset = 60h) [reset = 0h]

PERCNF1 is shown in Figure 3-177 and described in Table 3-187.
Return to the Summary Table.
Peripheral Configuration register

Figure 3-177. PERCNF1 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED USB_A_PHY
R-0-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED ADC_D_MODE ADC_C_MODE ADC_B_MODE ADC_A_MODE
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-187. PERCNF1 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
16 USB_A_PHY R/W 0h Internal PHY is present present or not for the USB_A module:
0: Internal USB PHY Module is not present
1: Internal USB PHY Module is present.
Reset type: PORESETn
15-4 RESERVED R-0 0h Reserved
3 ADC_D_MODE R/W 0h 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: PORESETn
2 ADC_C_MODE R/W 0h 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: PORESETn
1 ADC_B_MODE R/W 0h 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: PORESETn
0 ADC_A_MODE R/W 0h 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: PORESETn

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3.14.9.7 FUSEERR Register (Offset = 74h) [reset = 0h]

FUSEERR is shown in Figure 3-178 and described in Table 3-188.
Return to the Summary Table.
e-Fuse error Status register

Figure 3-178. FUSEERR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR ALERR
R-0-0h R-0h R-0h

Table 3-188. FUSEERR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-6 RESERVED R-0 0h Reserved
5 ERR R 0h Efuse Self Test Error Status set by hardware after fuse self test
completes, in case of self test error
0: No error during fuse self test
1: Fuse self test error
Reset type: XRSn
4-0 ALERR R 0h Efuse Autoload Error Status set by hardware after fuse auto load
completes
00000: No error in auto load
Other: Non zero value indicates error in autoload
Note:
[1] 10101 means a single-bit error during autoload. Since this gets
corrected by the ECC mechanism, this value shouldn't be treated as
an error condition.
Reset type: XRSn

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3.14.9.8 SOFTPRES0 Register (Offset = 82h) [reset = 0h]

SOFTPRES0 is shown in Figure 3-179 and described in Table 3-189.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-179. SOFTPRES0 Register

31 30 29 28 27 26 25 24
RESERVED CPU2_ERAD CPU1_ERAD
R-0-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED CPU2_CLA1B CPU2_CPUBG
GCRC CRC
R-0-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
CPU1_CLA1B CPU1_CPUBG RESERVED
GCRC CRC
R/W-0h R/W-0h R-0-0h
7 6 5 4 3 2 1 0
RESERVED CPU2_CLA1 CPU1_CLA1
R-0-0h R/W-0h R/W-0h

Table 3-189. SOFTPRES0 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R-0 0h Reserved
25 CPU2_ERAD R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
24 CPU1_ERAD R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
23-19 RESERVED R-0 0h Reserved
17 CPU2_CLA1BGCRC R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
16 CPU2_CPUBGCRC R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
14 CPU1_CLA1BGCRC R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
13 CPU1_CPUBGCRC R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
12-4 RESERVED R-0 0h Reserved
2 CPU2_CLA1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 CPU1_CLA1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.9 SOFTPRES1 Register (Offset = 84h) [reset = 0h]

SOFTPRES1 is shown in Figure 3-180 and described in Table 3-190.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-180. SOFTPRES1 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED EMIF2 EMIF1
R-0-0h R/W-0h R/W-0h

Table 3-190. SOFTPRES1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 EMIF2 R/W 0h When this bit is set, only the control logic of the respective EMIF2 is
reset. It does not reset the internal registers except the Total Access
register and the Total Activate register. Refer to EMIF spec for more
details on the EMIF SOFTRESET feature. This bit must be manually
cleared after being set.
1: EMIF2 is under SOFTRESET
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 EMIF1 R/W 0h When this bit is set, only the control logic of the respective EMIF1 is
reset. It does not reset the internal registers except the Total Access
register and the Total Activate register. Refer to EMIF spec for more
details on the EMIF SOFTRESET feature. This bit must be manually
cleared after being set.
1: EMIF1 is under SOFTRESET
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.10 SOFTPRES2 Register (Offset = 86h) [reset = 0h]

SOFTPRES2 is shown in Figure 3-181 and described in Table 3-191.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-181. SOFTPRES2 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
EPWM16 EPWM15 EPWM14 EPWM13 EPWM12 EPWM11 EPWM10 EPWM9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-191. SOFTPRES2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 EPWM16 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
14 EPWM15 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
13 EPWM14 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
12 EPWM13 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
11 EPWM12 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
10 EPWM11 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
9 EPWM10 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
8 EPWM9 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
7 EPWM8 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
6 EPWM7 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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Table 3-191. SOFTPRES2 Register Field Descriptions (continued)

Bit Field Type Reset Description
5 EPWM6 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
4 EPWM5 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
3 EPWM4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 EPWM3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 EPWM2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 EPWM1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.11 SOFTPRES3 Register (Offset = 88h) [reset = 0h]

SOFTPRES3 is shown in Figure 3-182 and described in Table 3-192.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-182. SOFTPRES3 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
ECAP7 ECAP6 ECAP5 ECAP4 ECAP3 ECAP2 ECAP1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-192. SOFTPRES3 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
6 ECAP7 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
5 ECAP6 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
4 ECAP5 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
3 ECAP4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 ECAP3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 ECAP2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 ECAP1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.12 SOFTPRES4 Register (Offset = 8Ah) [reset = 0h]

SOFTPRES4 is shown in Figure 3-183 and described in Table 3-193.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-183. SOFTPRES4 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED EQEP3 EQEP2 EQEP1
R-0-0h R/W-0h R/W-0h R/W-0h

Table 3-193. SOFTPRES4 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
2 EQEP3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 EQEP2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 EQEP1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.13 SOFTPRES6 Register (Offset = 8Eh) [reset = 0h]

SOFTPRES6 is shown in Figure 3-184 and described in Table 3-194.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-184. SOFTPRES6 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SD2 SD1
R-0-0h R/W- R/W-
0h 0h

Table 3-194. SOFTPRES6 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
1 SD2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 SD1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.14 SOFTPRES7 Register (Offset = 90h) [reset = 0h]

SOFTPRES7 is shown in Figure 3-185 and described in Table 3-195.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-185. SOFTPRES7 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED SCI_D SCI_C SCI_B SCI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-195. SOFTPRES7 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SCI_D R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 SCI_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 SCI_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 SCI_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.15 SOFTPRES8 Register (Offset = 92h) [reset = 0h]

SOFTPRES8 is shown in Figure 3-186 and described in Table 3-196.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-186. SOFTPRES8 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED SPI_D SPI_C SPI_B SPI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-196. SOFTPRES8 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SPI_D R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 SPI_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 SPI_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 SPI_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.16 SOFTPRES9 Register (Offset = 94h) [reset = 0h]

SOFTPRES9 is shown in Figure 3-187 and described in Table 3-197.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-187. SOFTPRES9 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED I2C_B I2C_A
R-0-0h R/W-0h R/W-0h

Table 3-197. SOFTPRES9 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 I2C_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 I2C_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.17 SOFTPRES10 Register (Offset = 96h) [reset = 0h]

SOFTPRES10 is shown in Figure 3-188 and described in Table 3-198.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-188. SOFTPRES10 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED CAN_B CAN_A
R-0-0h R/W-0h R/W-0h

Table 3-198. SOFTPRES10 Register Field Descriptions

Bit Field Type Reset Description
31-5 RESERVED R-0 0h Reserved
1 CAN_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 CAN_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.18 SOFTPRES11 Register (Offset = 98h) [reset = 0h]

SOFTPRES11 is shown in Figure 3-189 and described in Table 3-199.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-189. SOFTPRES11 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED USB_A
R-0-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED McBSP_B McBSP_A
R-0-0h R/W-0h R/W-0h

Table 3-199. SOFTPRES11 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
16 USB_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
15-2 RESERVED R-0 0h Reserved
1 McBSP_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 McBSP_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.19 SOFTPRES13 Register (Offset = 9Ch) [reset = 0h]

SOFTPRES13 is shown in Figure 3-190 and described in Table 3-200.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-190. SOFTPRES13 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED ADC_D ADC_C ADC_B ADC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-200. SOFTPRES13 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 ADC_D R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 ADC_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 ADC_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 ADC_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.20 SOFTPRES14 Register (Offset = 9Eh) [reset = 0h]

SOFTPRES14 is shown in Figure 3-191 and described in Table 3-201.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-191. SOFTPRES14 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
CMPSS8 CMPSS7 CMPSS6 CMPSS5 CMPSS4 CMPSS3 CMPSS2 CMPSS1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-201. SOFTPRES14 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 CMPSS8 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
6 CMPSS7 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
5 CMPSS6 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
4 CMPSS5 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
3 CMPSS4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 CMPSS3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 CMPSS2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 CMPSS1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.21 SOFTPRES16 Register (Offset = A2h) [reset = 0h]

SOFTPRES16 is shown in Figure 3-192 and described in Table 3-202.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-192. SOFTPRES16 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED DAC_C DAC_B DAC_A
R-0-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED
R-0-0h

Table 3-202. SOFTPRES16 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
18 DAC_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
17 DAC_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
16 DAC_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
15-0 RESERVED R-0 0h Reserved

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3.14.9.22 SOFTPRES17 Register (Offset = A4h) [reset = 0h]

SOFTPRES17 is shown in Figure 3-193 and described in Table 3-203.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-193. SOFTPRES17 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
CLB4 CLB3 CLB2 CLB1
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-203. SOFTPRES17 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
3 CLB4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 CLB3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 CLB2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 CLB1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.23 SOFTPRES18 Register (Offset = A6h) [reset = 0h]

SOFTPRES18 is shown in Figure 3-194 and described in Table 3-204.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-194. SOFTPRES18 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
FSIRX_H FSIRX_G FSIRX_F FSIRX_E FSIRX_D FSIRX_C FSIRX_B FSIRX_A
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
FSITX_B FSITX_A
R/W-0h R/W-0h

Table 3-204. SOFTPRES18 Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R-0 0h Reserved
23 FSIRX_H R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
22 FSIRX_G R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
21 FSIRX_F R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
20 FSIRX_E R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
19 FSIRX_D R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
18 FSIRX_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
17 FSIRX_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
16 FSIRX_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
15-8 RESERVED R/W 0h Reserved
1 FSITX_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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Table 3-204. SOFTPRES18 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 FSITX_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.24 SOFTPRES20 Register (Offset = AAh) [reset = 0h]

SOFTPRES20 is shown in Figure 3-195 and described in Table 3-205.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-195. SOFTPRES20 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED PMBUS_A
R-0-0h R/W-0h

Table 3-205. SOFTPRES20 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
0 PMBUS_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.25 SOFTPRES21 Register (Offset = ACh) [reset = 0h]

SOFTPRES21 is shown in Figure 3-196 and described in Table 3-206.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-196. SOFTPRES21 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DCC2 DCC1 DCC0
R-0-0h R/W-0h R/W-0h R/W-0h

Table 3-206. SOFTPRES21 Register Field Descriptions

Bit Field Type Reset Description
31-3 RESERVED R-0 0h Reserved
2 DCC2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 DCC1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 DCC0 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.26 SOFTPRES23 Register (Offset = B0h) [reset = 1h]

SOFTPRES23 is shown in Figure 3-197 and described in Table 3-207.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral
registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-197. SOFTPRES23 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ETHERCAT
R-0h R/W-1h

Table 3-207. SOFTPRES23 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 ETHERCAT R/W 1h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.14.9.27 CPUSEL0 Register (Offset = D6h) [reset = 0h]

CPUSEL0 is shown in Figure 3-198 and described in Table 3-208.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-198. CPUSEL0 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
EPWM16 EPWM15 EPWM14 EPWM13 EPWM12 EPWM11 EPWM10 EPWM9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-208. CPUSEL0 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 EPWM16 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
14 EPWM15 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
13 EPWM14 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
12 EPWM13 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
11 EPWM12 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
10 EPWM11 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
9 EPWM10 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
8 EPWM9 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
7 EPWM8 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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Table 3-208. CPUSEL0 Register Field Descriptions (continued)

Bit Field Type Reset Description
6 EPWM7 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
5 EPWM6 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
4 EPWM5 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
3 EPWM4 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 EPWM3 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 EPWM2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 EPWM1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.14.9.28 CPUSEL1 Register (Offset = D8h) [reset = 0h]

CPUSEL1 is shown in Figure 3-199 and described in Table 3-209.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-199. CPUSEL1 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
ECAP7 ECAP6 ECAP5 ECAP4 ECAP3 ECAP2 ECAP1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-209. CPUSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
6 ECAP7 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
5 ECAP6 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
4 ECAP5 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
3 ECAP4 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 ECAP3 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 ECAP2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 ECAP1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.14.9.29 CPUSEL2 Register (Offset = DAh) [reset = 0h]

CPUSEL2 is shown in Figure 3-200 and described in Table 3-210.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-200. CPUSEL2 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED EQEP3 EQEP2 EQEP1
R-0-0h R/W-0h R/W-0h R/W-0h

Table 3-210. CPUSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
2 EQEP3 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 EQEP2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 EQEP1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.14.9.30 CPUSEL4 Register (Offset = DEh) [reset = 0h]

CPUSEL4 is shown in Figure 3-201 and described in Table 3-211.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-201. CPUSEL4 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SD2 SD1
R-0-0h R/W- R/W-
0h 0h

Table 3-211. CPUSEL4 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
1 SD2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 SD1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.14.9.31 CPUSEL5 Register (Offset = E0h) [reset = 0h]

CPUSEL5 is shown in Figure 3-202 and described in Table 3-212.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-202. CPUSEL5 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED SCI_D SCI_C SCI_B SCI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-212. CPUSEL5 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SCI_D R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 SCI_C R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 SCI_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 SCI_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.14.9.32 CPUSEL6 Register (Offset = E2h) [reset = 0h]

CPUSEL6 is shown in Figure 3-203 and described in Table 3-213.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-203. CPUSEL6 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED SPI_D SPI_C SPI_B SPI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-213. CPUSEL6 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SPI_D R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 SPI_C R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 SPI_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 SPI_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.14.9.33 CPUSEL7 Register (Offset = E4h) [reset = 0h]

CPUSEL7 is shown in Figure 3-204 and described in Table 3-214.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-204. CPUSEL7 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED I2C_B I2C_A
R-0-0h R/W-0h R/W-0h

Table 3-214. CPUSEL7 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 I2C_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 I2C_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.14.9.34 CPUSEL8 Register (Offset = E6h) [reset = 0h]

CPUSEL8 is shown in Figure 3-205 and described in Table 3-215.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-205. CPUSEL8 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED CAN_B CAN_A
R-0-0h R/W-0h R/W-0h

Table 3-215. CPUSEL8 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-5 RESERVED R-0 0h Reserved
1 CAN_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 CAN_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.14.9.35 CPUSEL9 Register (Offset = E8h) [reset = 0h]

CPUSEL9 is shown in Figure 3-206 and described in Table 3-216.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-206. CPUSEL9 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED McBSP_B McBSP_A
R-0-0h R/W-0h R/W-0h

Table 3-216. CPUSEL9 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 McBSP_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 McBSP_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.14.9.36 CPUSEL11 Register (Offset = ECh) [reset = 0h]

CPUSEL11 is shown in Figure 3-207 and described in Table 3-217.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-207. CPUSEL11 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED ADC_D ADC_C ADC_B ADC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-217. CPUSEL11 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 ADC_D R/W 0h These CPUSEL bits affect the ownership of only ADC Configuration
registers by CPU1 or CPU2. ADC result registers are readable from
all masters without any CPUSEL dependency.
0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 ADC_C R/W 0h These CPUSEL bits affect the ownership of only ADC Configuration
registers by CPU1 or CPU2. ADC result registers are readable from
all masters without any CPUSEL dependency.
0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 ADC_B R/W 0h These CPUSEL bits affect the ownership of only ADC Configuration
registers by CPU1 or CPU2. ADC result registers are readable from
all masters without any CPUSEL dependency.
0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 ADC_A R/W 0h These CPUSEL bits affect the ownership of only ADC Configuration
registers by CPU1 or CPU2. ADC result registers are readable from
all masters without any CPUSEL dependency.
0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.14.9.37 CPUSEL12 Register (Offset = EEh) [reset = 0h]

CPUSEL12 is shown in Figure 3-208 and described in Table 3-218.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-208. CPUSEL12 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
CMPSS8 CMPSS7 CMPSS6 CMPSS5 CMPSS4 CMPSS3 CMPSS2 CMPSS1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-218. CPUSEL12 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 CMPSS8 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
6 CMPSS7 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
5 CMPSS6 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
4 CMPSS5 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
3 CMPSS4 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 CMPSS3 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 CMPSS2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 CMPSS1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.14.9.38 CPUSEL14 Register (Offset = F2h) [reset = 0h]

CPUSEL14 is shown in Figure 3-209 and described in Table 3-219.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-209. CPUSEL14 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED DAC_C DAC_B DAC_A
R-0-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED
R-0-0h

Table 3-219. CPUSEL14 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
18 DAC_C R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
17 DAC_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
16 DAC_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
15-0 RESERVED R-0 0h Reserved

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3.14.9.39 CPUSEL15 Register (Offset = F4h) [reset = 0h]

CPUSEL15 is shown in Figure 3-210 and described in Table 3-220.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-210. CPUSEL15 Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
CLB4 CLB3 CLB2 CLB1
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-220. CPUSEL15 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R/W 0h Reserved
3 CLB4 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 CLB3 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 CLB2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 CLB1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.14.9.40 CPUSEL16 Register (Offset = F6h) [reset = 0h]

CPUSEL16 is shown in Figure 3-211 and described in Table 3-221.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-211. CPUSEL16 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
FSIRX_H FSIRX_G FSIRX_F FSIRX_E FSIRX_D FSIRX_C FSIRX_B FSIRX_A
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
FSITX_B FSITX_A
R/W-0h R/W-0h

Table 3-221. CPUSEL16 Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R-0 0h Reserved
23 FSIRX_H R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
22 FSIRX_G R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
21 FSIRX_F R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
20 FSIRX_E R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
19 FSIRX_D R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
18 FSIRX_C R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
17 FSIRX_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
16 FSIRX_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
15-8 RESERVED R-0 0h Reserved

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Table 3-221. CPUSEL16 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 FSITX_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 FSITX_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.14.9.41 CPUSEL18 Register (Offset = FAh) [reset = 0h]

CPUSEL18 is shown in Figure 3-212 and described in Table 3-222.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-212. CPUSEL18 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED PMBUS_A
R-0h R/W-0h

Table 3-222. CPUSEL18 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
0 PMBUS_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.14.9.42 CPUSEL25 Register (Offset = 108h) [reset = 0h]

CPUSEL25 is shown in Figure 3-213 and described in Table 3-223.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.

Figure 3-213. CPUSEL25 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED HRCAL_A
R-0h R/W-0h

Table 3-223. CPUSEL25 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 HRCAL_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.14.9.43 CPU2RESCTL Register (Offset = 122h) [reset = 1h]

CPU2RESCTL is shown in Figure 3-214 and described in Table 3-224.
Return to the Summary Table.
CPU2 Reset Control Register

Figure 3-214. CPU2RESCTL Register

31 30 29 28 27 26 25 24
KEY
R-0/W-0h
23 22 21 20 19 18 17 16
KEY
R-0/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED RESET
R-0-0h R/W-1h

Table 3-224. CPU2RESCTL Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h Write to this register succeeds only if this field is written with a value
of 0xa5a5
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the
KEY matches). 16-bit writes to the upper or lower half of this register
will be ignored
Reset type: CPU1.SYSRSn
15-1 RESERVED R-0 0h Reserved
0 RESET R/W 1h This bit controls the reset input of CPU2 core.
1: CPU2 is held in reset (CPU2.RSn = 0)
0: CPU2 reset is deactivated (CPU2.RSn = 1)
Note:
[1] If CPU2 is not used at-all by an application, it's advisable to put
CPU2 in STANDBY mode rather than in reset to save on active
power component on the CPU2 subsystem. This is because, all
clocks keep toggling when reset is active on the CPU2 sub-system.
[2] Note: If CPU2 is in Standby mode, writing to this bit will have no
effect. CPU2 may be reset by any Chip-level reset (POR, XRSn,
CPU1.WDRSn, or CPU1.NMIWDRSn). Alternately CPU2 may be
woken up by any configured wake-up event.
Reset type: CPU1.SYSRSn

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3.14.9.44 RSTSTAT Register (Offset = 124h) [reset = 0h]

RSTSTAT is shown in Figure 3-215 and described in Table 3-225.
Return to the Summary Table.
Reset Status register for secondary C28x CPUs

Figure 3-215. RSTSTAT Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED CPU2HWBISTRST CPU2NMIWDR CPU2RES
ST
R-0-0h R/W1S-0h R/W1S-0h R-0h

Table 3-225. RSTSTAT Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 CPU2HWBISTRST R/W1S 0h CPU2HWBISTRST0 and CPU2HWBISTRST1 together tells whether
a HWBIST reset was issued to CPU2 or not
00: CPU2 was not reset by the CPU2 HWBIST
11: CPU2 was reset due to CPU2 HWBIST reset
This status bit is a latched flag. This flag can be cleared by the
CPU1 by writing a 1
Reset type: CPU1.SYSRSn
1 CPU2NMIWDRST R/W1S 0h Indicates whether a CPU2.NMIWD reset was issued to CPU2 or not
0: CPU2 was not reset by the CPU2.NMIWD
1: CPU2 was reset due to CPU2.NMIWD reset
Reset type: CPU1.SYSRSn
0 CPU2RES R 0h Reset status of CPU2 to CPU1
0: CPU2 core is in reset
1: CPU2 core is out of reset
Reset type: CPU1.SYSRSn

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3.14.9.45 LPMSTAT Register (Offset = 125h) [reset = 0h]

LPMSTAT is shown in Figure 3-216 and described in Table 3-226.
Return to the Summary Table.
LPM Status Register for secondary C28x CPUs

Figure 3-216. LPMSTAT Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED CPU2LPMSTAT
R-0-0h R-0h

Table 3-226. LPMSTAT Register Field Descriptions

Bit Field Type Reset Description
15-2 RESERVED R-0 0h Reserved
1-0 CPU2LPMSTAT R 0h These bits indicate the power mode CPU2
00: CPU2 is in ACTIVE mode
01: CPU2 is in IDLE mode
10: CPU2 is in STANDBY mode
11: Reserved
Reset type: CPU1.SYSRSn

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3.14.9.46 USBTYPE Register (Offset = 19Ah) [reset = 0h]

USBTYPE is shown in Figure 3-217 and described in Table 3-227.
Return to the Summary Table.
Based on the configuration enables disables features associated with the USB type.

Figure 3-217. USBTYPE Register

15 14 13 12 11 10 9 8
LOCK RESERVED
R/WSonce-0h R-0-0h
7 6 5 4 3 2 1 0
RESERVED TYPE
R-0-0h R/W-0h

Table 3-227. USBTYPE Register Field Descriptions

Bit Field Type Reset Description
15 LOCK R/WSonce 0h 1: Write to this register is not allowed.
0: Write to this register is allowed.
Reset type: CPU1.SYSRSn
14-2 RESERVED R-0 0h Reserved
1-0 TYPE R/W 0h "00,10,11" :
1. Global interrupt feature is not enabled, interrupts fired
unconditionally.
"01" :
1.Global interrupt feature is enabled, refer to the spec doc for more
details about global interrupt feature.
Reset type: CPU1.SYSRSn

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3.14.9.47 ECAPTYPE Register (Offset = 19Bh) [reset = 0h]

ECAPTYPE is shown in Figure 3-218 and described in Table 3-228.
Return to the Summary Table.
Based on the configuration enables disables features associated with the SDFM type.

Figure 3-218. ECAPTYPE Register

15 14 13 12 11 10 9 8
LOCK RESERVED
R/WSonce-0h R-0-0h
7 6 5 4 3 2 1 0
RESERVED TYPE
R-0-0h R/W-0h

Table 3-228. ECAPTYPE Register Field Descriptions

Bit Field Type Reset Description
15 LOCK R/WSonce 0h 1: Write to this register is not allowed.
0: Write to this register is allowed.
Reset type: CPU1.SYSRSn
14-2 RESERVED R-0 0h Reserved
1-0 TYPE R/W 0h "00,10,11" :
1. No EALLOW protection to ECAP registers.
"01" :
1. ECAP registers are EALLOW protected.
Reset type: CPU1.SYSRSn

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3.14.9.48 SDFMTYPE Register (Offset = 19Ch) [reset = 0h]

SDFMTYPE is shown in Figure 3-219 and described in Table 3-229.
Return to the Summary Table.
Based on the configuration enables disables features associated with the SDFM type.

Figure 3-219. SDFMTYPE Register

15 14 13 12 11 10 9 8
LOCK RESERVED
R/WSonce-0h R-0-0h
7 6 5 4 3 2 1 0
RESERVED TYPE
R-0-0h R/W-0h

Table 3-229. SDFMTYPE Register Field Descriptions

Bit Field Type Reset Description
15 LOCK R/WSonce 0h 1: Write to this register is not allowed.
0: Write to this register is allowed.
Reset type: CPU1.SYSRSn
14-2 RESERVED R-0 0h Reserved
1-0 TYPE R/W 0h "00,10,11" :
1. Data Ready conditions combined with the fault conditions on the
SDFM interrupt line.
2. Data ready interrupts from individual filters are not generated.
"01" :
1. Data Ready conditions do not generate the SDFMINT.
2. Each filter generates a separate data ready interrupts.
Reset type: CPU1.SYSRSn

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3.14.9.49 MEMMAPTYPE Register (Offset = 19Eh) [reset = 0h]

MEMMAPTYPE is shown in Figure 3-220 and described in Table 3-230.
Return to the Summary Table.
Based on the configuration enables modifies the memory map.

Figure 3-220. MEMMAPTYPE Register

15 14 13 12 11 10 9 8
LOCK RESERVED
R/WSonce-0h R-0-0h
7 6 5 4 3 2 1 0
RESERVED TYPE
R-0-0h R/W-0h

Table 3-230. MEMMAPTYPE Register Field Descriptions

Bit Field Type Reset Description
15 LOCK R/WSonce 0h 1: Write to this register is not allowed.
0: Write to this register is allowed.
Reset type: CPU1.SYSRSn
14-2 RESERVED R-0 0h Reserved
1-0 TYPE R/W 0h "00,10,11" :
1. Disables re-mapping SDRAM in lower 64kb of address space.
"01" :
1. Enables re-mapping SDRAM in lower 64kb of address space.
Reset type: CPU1.SYSRSn

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3.14.10 DMA_CLA_SRC_SEL_REGS Registers

Table 3-231 lists the DMA_CLA_SRC_SEL_REGS registers. All register offset addresses not listed in
Table 3-231 should be considered as reserved locations and the register contents should not be modified.

Table 3-231. DMA_CLA_SRC_SEL_REGS Registers

Offset Acronym Register Name Write Protection Section
0h CLA1TASKSRCSELLOCK CLA1 Task Trigger Source Select Lock Register EALLOW Go
4h DMACHSRCSELLOCK DMA Channel Triger Source Select Lock EALLOW Go
Register
6h CLA1TASKSRCSEL1 CLA1 Task Trigger Source Select Register-1 EALLOW Go
8h CLA1TASKSRCSEL2 CLA1 Task Trigger Source Select Register-2 EALLOW Go
16h DMACHSRCSEL1 DMA Channel Trigger Source Select Register-1 EALLOW Go
18h DMACHSRCSEL2 DMA Channel Trigger Source Select Register-2 EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-232 shows the codes that are
used for access types in this section.

Table 3-232. DMA_CLA_SRC_SEL_REGS Access Type

Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.10.1 CLA1TASKSRCSELLOCK Register (Offset = 0h) [reset = 0h]

CLA1TASKSRCSELLOCK is shown in Figure 3-221 and described in Table 3-233.
Return to the Summary Table.
CLA1 Task Trigger Source Select Lock Register

Figure 3-221. CLA1TASKSRCSELLOCK Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED CLA1TASKSR CLA1TASKSR
CSEL2 CSEL1
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-233. CLA1TASKSRCSELLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 CLA1TASKSRCSEL2 R/WSonce 0h CLA1TASKSRCSEL2 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn
0 CLA1TASKSRCSEL1 R/WSonce 0h CLA1TASKSRCSEL1 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn

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3.14.10.2 DMACHSRCSELLOCK Register (Offset = 4h) [reset = 0h]

DMACHSRCSELLOCK is shown in Figure 3-222 and described in Table 3-234.
Return to the Summary Table.
DMA Channel Triger Source Select Lock Register

Figure 3-222. DMACHSRCSELLOCK Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED DMACHSRCSE DMACHSRCSE
L2 L1
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-234. DMACHSRCSELLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 DMACHSRCSEL2 R/WSonce 0h DMACHSRCSEL2 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn
0 DMACHSRCSEL1 R/WSonce 0h DMACHSRCSEL1 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn

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3.14.10.3 CLA1TASKSRCSEL1 Register (Offset = 6h) [reset = 0h]

CLA1TASKSRCSEL1 is shown in Figure 3-223 and described in Table 3-235.
Return to the Summary Table.
CLA1 Task Trigger Source Select Register-1

Figure 3-223. CLA1TASKSRCSEL1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-235. CLA1TASKSRCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-24 TASK4 R/W 0h Selects the Trigger Source for TASK4 of CLA1
Reset type: SYSRSn
23-16 TASK3 R/W 0h Selects the Trigger Source for TASK3 of CLA1
Reset type: SYSRSn
15-8 TASK2 R/W 0h Selects the Trigger Source for TASK2 of CLA1
Reset type: SYSRSn
7-0 TASK1 R/W 0h Selects the Trigger Source for TASK1 of CLA1
Reset type: SYSRSn

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3.14.10.4 CLA1TASKSRCSEL2 Register (Offset = 8h) [reset = 0h]

CLA1TASKSRCSEL2 is shown in Figure 3-224 and described in Table 3-236.
Return to the Summary Table.
CLA1 Task Trigger Source Select Register-2

Figure 3-224. CLA1TASKSRCSEL2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-236. CLA1TASKSRCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-24 TASK8 R/W 0h Selects the Trigger Source for TASK8 of CLA1
Reset type: SYSRSn
23-16 TASK7 R/W 0h Selects the Trigger Source for TASK7 of CLA1
Reset type: SYSRSn
15-8 TASK6 R/W 0h Selects the Trigger Source for TASK6 of CLA1
Reset type: SYSRSn
7-0 TASK5 R/W 0h Selects the Trigger Source for TASK5 of CLA1
Reset type: SYSRSn

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3.14.10.5 DMACHSRCSEL1 Register (Offset = 16h) [reset = 0h]

DMACHSRCSEL1 is shown in Figure 3-225 and described in Table 3-237.
Return to the Summary Table.
DMA Channel Trigger Source Select Register-1

Figure 3-225. DMACHSRCSEL1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH4 CH3 CH2 CH1
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-237. DMACHSRCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-24 CH4 R/W 0h Selects the Trigger and Sync Source CH4 of DMA
Reset type: SYSRSn
23-16 CH3 R/W 0h Selects the Trigger and Sync Source CH3 of DMA
Reset type: SYSRSn
15-8 CH2 R/W 0h Selects the Trigger and Sync Source CH2 of DMA
Reset type: SYSRSn
7-0 CH1 R/W 0h Selects the Trigger and Sync Source CH1 of DMA
Reset type: SYSRSn

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3.14.10.6 DMACHSRCSEL2 Register (Offset = 18h) [reset = 0h]

DMACHSRCSEL2 is shown in Figure 3-226 and described in Table 3-238.
Return to the Summary Table.
DMA Channel Trigger Source Select Register-2

Figure 3-226. DMACHSRCSEL2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CH6 CH5
R-0-0h R/W-0h R/W-0h

Table 3-238. DMACHSRCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 CH6 R/W 0h Selects the Trigger and Sync Source CH6 of DMA
Reset type: SYSRSn
7-0 CH5 R/W 0h Selects the Trigger and Sync Source CH5 of DMA
Reset type: SYSRSn

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3.14.11 MEM_CFG_REGS Registers

Table 3-239 lists the MEM_CFG_REGS registers. All register offset addresses not listed in Table 3-239
should be considered as reserved locations and the register contents should not be modified.

Table 3-239. MEM_CFG_REGS Registers

Offset Acronym Register Name Write Protection Section
0h DxLOCK Dedicated RAM Config Lock Register EALLOW Go
2h DxCOMMIT Dedicated RAM Config Lock Commit Register EALLOW Go
8h DxACCPROT0 Dedicated RAM Config Register EALLOW Go
10h DxTEST Dedicated RAM TEST Register EALLOW Go
12h DxINIT Dedicated RAM Init Register EALLOW Go
14h DxINITDONE Dedicated RAM InitDone Status Register Go
16h DxRAMTEST_LOCK Lock register to Dx RAM TEST registers Go
20h LSxLOCK Local Shared RAM Config Lock Register EALLOW Go
22h LSxCOMMIT Local Shared RAM Config Lock Commit Register EALLOW Go
24h LSxMSEL Local Shared RAM Master Sel Register EALLOW Go
26h LSxCLAPGM Local Shared RAM Prog/Exe control Register EALLOW Go
28h LSxACCPROT0 Local Shared RAM Config Register 0 EALLOW Go
2Ah LSxACCPROT1 Local Shared RAM Config Register 1 EALLOW Go
30h LSxTEST Local Shared RAM TEST Register EALLOW Go
32h LSxINIT Local Shared RAM Init Register EALLOW Go
34h LSxINITDONE Local Shared RAM InitDone Status Register Go
36h LSxRAMTEST_LOCK Lock register to LSx RAM TEST registers Go
40h GSxLOCK Global Shared RAM Config Lock Register EALLOW Go
42h GSxCOMMIT Global Shared RAM Config Lock Commit EALLOW Go
Register
44h GSxMSEL Global Shared RAM Master Sel Register EALLOW Go
48h GSxACCPROT0 Global Shared RAM Access Protection Register EALLOW Go
0
4Ah GSxACCPROT1 Global Shared RAM Access Protection Register EALLOW Go
1
4Ch GSxACCPROT2 Global Shared RAM Access Protection Register EALLOW Go
2
4Eh GSxACCPROT3 Global Shared RAM Access Protection Register EALLOW Go
3
50h GSxTEST Global Shared RAM TEST Register EALLOW Go
52h GSxINIT Global Shared RAM Init Register EALLOW Go
54h GSxINITDONE Global Shared RAM InitDone Status Register Go
56h GSxRAMTEST_LOCK Lock register to GSx RAM TEST registers Go
60h MSGxLOCK Message RAM Config Lock Register Go
62h MSGxCOMMIT Message RAM Config Lock Commit Register Go
68h MSGxACCPROT0 Message RAM Access Protection Register 0 EALLOW Go
6Ah MSGxACCPROT1 Message RAM Access Protection Register 1 EALLOW Go
6Ch MSGxACCPROT2 Message RAM Access Protection Register 2 EALLOW Go
70h MSGxTEST Message RAM TEST Register EALLOW Go
72h MSGxINIT Message RAM Init Register EALLOW Go
74h MSGxINITDONE Message RAM InitDone Status Register Go
76h MSGxRAMTEST_LOCK Lock register to MSGx RAM TEST registers Go
A0h ROM_LOCK ROM Config Lock Register Go
A2h ROM_TEST ROM TEST Register Go
A4h ROM_FORCE_ERROR ROM Force Error register Go

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Table 3-239. MEM_CFG_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
AAh PERI_MEM_TEST_LOCK Peripheral Memory Test Lock Register Go
ACh PERI_MEM_TEST_CONTROL Peripheral Memory Test control Register Go

Complex bit access types are encoded to fit into small table cells. Table 3-240 shows the codes that are
used for access types in this section.

Table 3-240. MEM_CFG_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.11.1 DxLOCK Register (Offset = 0h) [reset = 0h]

DxLOCK is shown in Figure 3-227 and described in Table 3-241.
Return to the Summary Table.
Dedicated RAM Config Lock Register

Figure 3-227. DxLOCK Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED LOCK_D1 LOCK_D0 LOCK_M1 LOCK_M0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-241. DxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 LOCK_D1 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for D1 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
2 LOCK_D0 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for D0 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
1 LOCK_M1 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for M1 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
0 LOCK_M0 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for M0 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn

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3.14.11.2 DxCOMMIT Register (Offset = 2h) [reset = 0h]

DxCOMMIT is shown in Figure 3-228 and described in Table 3-242.
Return to the Summary Table.
Dedicated RAM Config Lock Commit Register

Figure 3-228. DxCOMMIT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED COMMIT_D1 COMMIT_D0 COMMIT_M1 COMMIT_M0
R-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-242. DxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 COMMIT_D1 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for D1 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in DxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
2 COMMIT_D0 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for D0 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in DxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
1 COMMIT_M1 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for M1 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in DxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
0 COMMIT_M0 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for M0 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in DxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn

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3.14.11.3 DxACCPROT0 Register (Offset = 8h) [reset = 0h]

DxACCPROT0 is shown in Figure 3-229 and described in Table 3-243.
Return to the Summary Table.
Dedicated RAM Config Register

Figure 3-229. DxACCPROT0 Register

31 30 29 28 27 26 25 24
RESERVED CPUWRPROT_ FETCHPROT_
D1 D1
R-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED CPUWRPROT_ FETCHPROT_
D0 D0
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED CPUWRPROT_ FETCHPROT_
M1 M1
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ FETCHPROT_
M0 M0
R-0h R/W-0h R/W-0h

Table 3-243. DxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R 0h Reserved
25 CPUWRPROT_D1 R/W 0h CPU Write Protection For D1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_D1 R/W 0h Fetch Protection For D1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-18 RESERVED R 0h Reserved
17 CPUWRPROT_D0 R/W 0h CPU Write Protection For D0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are block.
Reset type: SYSRSn
16 FETCHPROT_D0 R/W 0h Fetch Protection For D0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 CPUWRPROT_M1 R/W 0h CPU WR Protection For M1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are block.
Reset type: SYSRSn
8 FETCHPROT_M1 R/W 0h Fetch Protection For M1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved

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Table 3-243. DxACCPROT0 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 CPUWRPROT_M0 R/W 0h CPU WR Protection For M0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are block.
Reset type: SYSRSn
0 FETCHPROT_M0 R/W 0h Fetch Protection For M0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.14.11.4 DxTEST Register (Offset = 10h) [reset = 0h]

DxTEST is shown in Figure 3-230 and described in Table 3-244.
Return to the Summary Table.
Dedicated RAM TEST Register

Figure 3-230. DxTEST Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
TEST_D1 TEST_D0 TEST_M1 TEST_M0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-244. DxTEST Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7-6 TEST_D1 R/W 0h Selects the defferent modes for D1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Reset type: SYSRSn
5-4 TEST_D0 R/W 0h Selects the defferent modes for D0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Reset type: SYSRSn
3-2 TEST_M1 R/W 0h Selects the defferent modes for M1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Reset type: SYSRSn
1-0 TEST_M0 R/W 0h Selects the defferent modes for M0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Reset type: SYSRSn

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3.14.11.5 DxINIT Register (Offset = 12h) [reset = 0h]

DxINIT is shown in Figure 3-231 and described in Table 3-245.
Return to the Summary Table.
Dedicated RAM Init Register

Figure 3-231. DxINIT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED INIT_D1 INIT_D0 INIT_M1 INIT_M0
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-245. DxINIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 INIT_D1 R-0/W1S 0h RAM Initialization control for D1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
2 INIT_D0 R-0/W1S 0h RAM Initialization control for D0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_M1 R-0/W1S 0h RAM Initialization control for M1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 INIT_M0 R-0/W1S 0h RAM Initialization control for M0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.14.11.6 DxINITDONE Register (Offset = 14h) [reset = 0h]

DxINITDONE is shown in Figure 3-232 and described in Table 3-246.
Return to the Summary Table.
Dedicated RAM InitDone Status Register

Figure 3-232. DxINITDONE Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED INITDONE_D1 INITDONE_D0 INITDONE_M1 INITDONE_M0
R-0h R-0h R-0h R-0h R-0h

Table 3-246. DxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 INITDONE_D1 R 0h RAM Initialization status for D1 RAM:
0: RAM Initialization has completed.
1: RAM Initialization has completed.
Reset type: SYSRSn
2 INITDONE_D0 R 0h RAM Initialization status for D0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_M1 R 0h RAM Initialization status for M1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization has completed.
Reset type: SYSRSn
0 INITDONE_M0 R 0h RAM Initialization status for M0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.14.11.7 DxRAMTEST_LOCK Register (Offset = 16h) [reset = 0h]

DxRAMTEST_LOCK is shown in Figure 3-233 and described in Table 3-247.
Return to the Summary Table.
Lock register to Dx RAM TEST registers

Figure 3-233. DxRAMTEST_LOCK Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
R-0/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED D1 D0 M1 M0
R-0h R/W- R/W- R/W- R/W-
0h 0h 0h 0h

Table 3-247. DxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-4 RESERVED R 0h Reserved
3 D1 R/W 0h 0: Allows writes to DxTEST.TEST_D1 field.
1: Blocks writes to DxTEST.TEST_D1 field
Reset type: SYSRSn
2 D0 R/W 0h 0: Allows writes to DxTEST.TEST_D0 field.
1: Blocks writes to DxTEST.TEST_D0 field
Reset type: SYSRSn
1 M1 R/W 0h 0: Allows writes to DxTEST.TEST_M1 field.
1: Blocks writes to DxTEST.TEST_M1 field
Reset type: SYSRSn
0 M0 R/W 0h 0: Allows writes to DxTEST.TEST_M0 field.
1: Blocks writes to DxTEST.TEST_M0 field
Reset type: SYSRSn

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3.14.11.8 LSxLOCK Register (Offset = 20h) [reset = 0h]

LSxLOCK is shown in Figure 3-234 and described in Table 3-248.
Return to the Summary Table.
Local Shared RAM Config Lock Register

Figure 3-234. LSxLOCK Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
LOCK_LS7 LOCK_LS6 LOCK_LS5 LOCK_LS4 LOCK_LS3 LOCK_LS2 LOCK_LS1 LOCK_LS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-248. LSxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 LOCK_LS7 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and register fields test for LS7
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn
6 LOCK_LS6 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS6
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn
5 LOCK_LS5 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS5
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn
4 LOCK_LS4 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS4
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn

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Table 3-248. LSxLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
3 LOCK_LS3 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS3
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn
2 LOCK_LS2 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS2
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn
1 LOCK_LS1 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS1
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn
0 LOCK_LS0 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS0
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn

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3.14.11.9 LSxCOMMIT Register (Offset = 22h) [reset = 0h]

LSxCOMMIT is shown in Figure 3-235 and described in Table 3-249.
Return to the Summary Table.
Local Shared RAM Config Lock Commit Register

Figure 3-235. LSxCOMMIT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
COMMIT_LS7 COMMIT_LS6 COMMIT_LS5 COMMIT_LS4 COMMIT_LS3 COMMIT_LS2 COMMIT_LS1 COMMIT_LS0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-249. LSxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 COMMIT_LS7 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS7 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn
6 COMMIT_LS6 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS6 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn
5 COMMIT_LS5 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS5 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn
4 COMMIT_LS4 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS4 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn

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Table 3-249. LSxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
3 COMMIT_LS3 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS3 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn
2 COMMIT_LS2 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS2 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn
1 COMMIT_LS1 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS1 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn
0 COMMIT_LS0 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS0 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn

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3.14.11.10 LSxMSEL Register (Offset = 24h) [reset = 0h]

LSxMSEL is shown in Figure 3-236 and described in Table 3-250.
Return to the Summary Table.
Local Shared RAM Master Sel Register

Figure 3-236. LSxMSEL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
MSEL_LS7 MSEL_LS6 MSEL_LS5 MSEL_LS4
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
MSEL_LS3 MSEL_LS2 MSEL_LS1 MSEL_LS0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-250. LSxMSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-14 MSEL_LS7 R/W 0h Master Select for LS7 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
13-12 MSEL_LS6 R/W 0h Master Select for LS6 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
11-10 MSEL_LS5 R/W 0h Master Select for LS5 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
9-8 MSEL_LS4 R/W 0h Master Select for LS4 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
7-6 MSEL_LS3 R/W 0h Master Select for LS3 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

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Table 3-250. LSxMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
5-4 MSEL_LS2 R/W 0h Master Select for LS2 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
3-2 MSEL_LS1 R/W 0h Master Select for LS1 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
1-0 MSEL_LS0 R/W 0h Master Select for LS0 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

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3.14.11.11 LSxCLAPGM Register (Offset = 26h) [reset = 0h]

LSxCLAPGM is shown in Figure 3-237 and described in Table 3-251.
Return to the Summary Table.
Local Shared RAM Prog/Exe control Register

Figure 3-237. LSxCLAPGM Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
CLAPGM_LS7 CLAPGM_LS6 CLAPGM_LS5 CLAPGM_LS4 CLAPGM_LS3 CLAPGM_LS2 CLAPGM_LS1 CLAPGM_LS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-251. LSxCLAPGM Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 CLAPGM_LS7 R/W 0h Selects LS7 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
6 CLAPGM_LS6 R/W 0h Selects LS6 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
5 CLAPGM_LS5 R/W 0h Selects LS5 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
4 CLAPGM_LS4 R/W 0h Selects LS4 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
3 CLAPGM_LS3 R/W 0h Selects LS3 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
2 CLAPGM_LS2 R/W 0h Selects LS2 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
1 CLAPGM_LS1 R/W 0h Selects LS1 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
0 CLAPGM_LS0 R/W 0h Selects LS0 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn

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3.14.11.12 LSxACCPROT0 Register (Offset = 28h) [reset = 0h]

LSxACCPROT0 is shown in Figure 3-238 and described in Table 3-252.
Return to the Summary Table.
Local Shared RAM Config Register 0

Figure 3-238. LSxACCPROT0 Register

31 30 29 28 27 26 25 24
RESERVED CPUWRPROT_ FETCHPROT_
LS3 LS3
R-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED CPUWRPROT_ FETCHPROT_
LS2 LS2
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED CPUWRPROT_ FETCHPROT_
LS1 LS1
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ FETCHPROT_
LS0 LS0
R-0h R/W-0h R/W-0h

Table 3-252. LSxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R 0h Reserved
25 CPUWRPROT_LS3 R/W 0h CPU WR Protection For LS3 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_LS3 R/W 0h Fetch Protection For LS3 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-18 RESERVED R 0h Reserved
17 CPUWRPROT_LS2 R/W 0h CPU WR Protection For LS2 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_LS2 R/W 0h Fetch Protection For LS2 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 CPUWRPROT_LS1 R/W 0h CPU WR Protection For LS1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_LS1 R/W 0h Fetch Protection For LS1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved

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Table 3-252. LSxACCPROT0 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 CPUWRPROT_LS0 R/W 0h CPU WR Protection For LS0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_LS0 R/W 0h Fetch Protection For LS0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.14.11.13 LSxACCPROT1 Register (Offset = 2Ah) [reset = 0h]

LSxACCPROT1 is shown in Figure 3-239 and described in Table 3-253.
Return to the Summary Table.
Local Shared RAM Config Register 1

Figure 3-239. LSxACCPROT1 Register

31 30 29 28 27 26 25 24
RESERVED CPUWRPROT_ FETCHPROT_
LS7 LS7
R-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED CPUWRPROT_ FETCHPROT_
LS6 LS6
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED CPUWRPROT_ FETCHPROT_
LS5 LS5
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ FETCHPROT_
LS4 LS4
R-0h R/W-0h R/W-0h

Table 3-253. LSxACCPROT1 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R 0h Reserved
25 CPUWRPROT_LS7 R/W 0h CPU WR Protection For LS7 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_LS7 R/W 0h Fetch Protection For LS7 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-18 RESERVED R 0h Reserved
17 CPUWRPROT_LS6 R/W 0h CPU WR Protection For LS6 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_LS6 R/W 0h Fetch Protection For LS6 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 CPUWRPROT_LS5 R/W 0h CPU WR Protection For LS5 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_LS5 R/W 0h Fetch Protection For LS5 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved

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Table 3-253. LSxACCPROT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 CPUWRPROT_LS4 R/W 0h CPU WR Protection For LS4 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_LS4 R/W 0h Fetch Protection For LS4 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.14.11.14 LSxTEST Register (Offset = 30h) [reset = 0h]

LSxTEST is shown in Figure 3-240 and described in Table 3-254.
Return to the Summary Table.
Local Shared RAM TEST Register

Figure 3-240. LSxTEST Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
TEST_LS7 TEST_LS6 TEST_LS5 TEST_LS4
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
TEST_LS3 TEST_LS2 TEST_LS1 TEST_LS0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-254. LSxTEST Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-14 TEST_LS7 R/W 0h Selects the defferent modes for LS7 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
13-12 TEST_LS6 R/W 0h Selects the defferent modes for LS6 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
11-10 TEST_LS5 R/W 0h Selects the defferent modes for LS5 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
9-8 TEST_LS4 R/W 0h Selects the defferent modes for LS4 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
7-6 TEST_LS3 R/W 0h Selects the defferent modes for LS3 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
5-4 TEST_LS2 R/W 0h Selects the defferent modes for LS2 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

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Table 3-254. LSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 TEST_LS1 R/W 0h Selects the defferent modes for LS1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
1-0 TEST_LS0 R/W 0h Selects the defferent modes for LS0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

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3.14.11.15 LSxINIT Register (Offset = 32h) [reset = 0h]

LSxINIT is shown in Figure 3-241 and described in Table 3-255.
Return to the Summary Table.
Local Shared RAM Init Register

Figure 3-241. LSxINIT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
INIT_LS7 INIT_LS6 INIT_LS5 INIT_LS4 INIT_LS3 INIT_LS2 INIT_LS1 INIT_LS0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-255. LSxINIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 INIT_LS7 R-0/W1S 0h RAM Initialization control for LS7 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
6 INIT_LS6 R-0/W1S 0h RAM Initialization control for LS6 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
5 INIT_LS5 R-0/W1S 0h RAM Initialization control for LS5 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
4 INIT_LS4 R-0/W1S 0h RAM Initialization control for LS4 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
3 INIT_LS3 R-0/W1S 0h RAM Initialization control for LS3 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
2 INIT_LS2 R-0/W1S 0h RAM Initialization control for LS2 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_LS1 R-0/W1S 0h RAM Initialization control for LS1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 INIT_LS0 R-0/W1S 0h RAM Initialization control for LS0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.14.11.16 LSxINITDONE Register (Offset = 34h) [reset = 0h]

LSxINITDONE is shown in Figure 3-242 and described in Table 3-256.
Return to the Summary Table.
Local Shared RAM InitDone Status Register

Figure 3-242. LSxINITDONE Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
INITDONE_LS7 INITDONE_LS6 INITDONE_LS5 INITDONE_LS4 INITDONE_LS3 INITDONE_LS2 INITDONE_LS1 INITDONE_LS0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-256. LSxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 INITDONE_LS7 R 0h RAM Initialization status for LS7 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
6 INITDONE_LS6 R 0h RAM Initialization status for LS6 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
5 INITDONE_LS5 R 0h RAM Initialization status for LS5 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
4 INITDONE_LS4 R 0h RAM Initialization status for LS4 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
3 INITDONE_LS3 R 0h RAM Initialization status for LS3 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
2 INITDONE_LS2 R 0h RAM Initialization status for LS2 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_LS1 R 0h RAM Initialization status for LS1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
0 INITDONE_LS0 R 0h RAM Initialization status for LS0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.14.11.17 LSxRAMTEST_LOCK Register (Offset = 36h) [reset = 0h]

LSxRAMTEST_LOCK is shown in Figure 3-243 and described in Table 3-257.
Return to the Summary Table.
Lock register to LSx RAM TEST registers

Figure 3-243. LSxRAMTEST_LOCK Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
R-0/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LS7 LS6 LS5 LS4 LS3 LS2 LS1 LS0
R-0h R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W-
0h 0h 0h 0h 0h 0h 0h 0h

Table 3-257. LSxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-8 RESERVED R 0h Reserved
7 LS7 R/W 0h 0: Allows writes to LSxTEST.TEST_LS7 field.
1: Blocks writes to LSxTEST.TEST_LS7 field.
Reset type: SYSRSn
6 LS6 R/W 0h 0: Allows writes to LSxTEST.TEST_LS6 field.
1: Blocks writes to LSxTEST.TEST_LS6 field.
Reset type: SYSRSn
5 LS5 R/W 0h 0: Allows writes to LSxTEST.TEST_LS5 field.
1: Blocks writes to LSxTEST.TEST_LS5 field.
Reset type: SYSRSn
4 LS4 R/W 0h 0: Allows writes to LSxTEST.TEST_LS4 field.
1: Blocks writes to LSxTEST.TEST_LS4 field.
Reset type: SYSRSn
3 LS3 R/W 0h 0: Allows writes to LSxTEST.TEST_LS3 field.
1: Blocks writes to LSxTEST.TEST_LS3 field.
Reset type: SYSRSn
2 LS2 R/W 0h 0: Allows writes to LSxTEST.TEST_LS2 field.
1: Blocks writes to LSxTEST.TEST_LS2 field.
Reset type: SYSRSn
1 LS1 R/W 0h 0: Allows writes to LSxTEST.TEST_LS1 field.
1: Blocks writes to LSxTEST.TEST_LS1 field.
Reset type: SYSRSn
0 LS0 R/W 0h 0: Allows writes to LSxTEST.TEST_LS0 field.
1: Blocks writes to LSxTEST.TEST_LS0 field.
Reset type: SYSRSn

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3.14.11.18 GSxLOCK Register (Offset = 40h) [reset = 0h]

GSxLOCK is shown in Figure 3-244 and described in Table 3-258.
Return to the Summary Table.
Global Shared RAM Config Lock Register

Figure 3-244. GSxLOCK Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
LOCK_GS15 LOCK_GS14 LOCK_GS13 LOCK_GS12 LOCK_GS11 LOCK_GS10 LOCK_GS9 LOCK_GS8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
LOCK_GS7 LOCK_GS6 LOCK_GS5 LOCK_GS4 LOCK_GS3 LOCK_GS2 LOCK_GS1 LOCK_GS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-258. GSxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 LOCK_GS15 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS15 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
14 LOCK_GS14 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS14 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
13 LOCK_GS13 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS13 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
12 LOCK_GS12 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS12 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
11 LOCK_GS11 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS11 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
10 LOCK_GS10 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS10 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
9 LOCK_GS9 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS9 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn

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Table 3-258. GSxLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
8 LOCK_GS8 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS8 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
7 LOCK_GS7 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS7 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
6 LOCK_GS6 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS6 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
5 LOCK_GS5 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS5 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
4 LOCK_GS4 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS4 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
3 LOCK_GS3 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS3 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
2 LOCK_GS2 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS2 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
1 LOCK_GS1 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS1 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
0 LOCK_GS0 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS0 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn

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3.14.11.19 GSxCOMMIT Register (Offset = 42h) [reset = 0h]

GSxCOMMIT is shown in Figure 3-245 and described in Table 3-259.
Return to the Summary Table.
Global Shared RAM Config Lock Commit Register

Figure 3-245. GSxCOMMIT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
COMMIT_GS1 COMMIT_GS1 COMMIT_GS1 COMMIT_GS1 COMMIT_GS1 COMMIT_GS1 COMMIT_GS9 COMMIT_GS8
5 4 3 2 1 0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h
7 6 5 4 3 2 1 0
COMMIT_GS7 COMMIT_GS6 COMMIT_GS5 COMMIT_GS4 COMMIT_GS3 COMMIT_GS2 COMMIT_GS1 COMMIT_GS0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-259. GSxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 COMMIT_GS15 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS15 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
14 COMMIT_GS14 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS14 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
13 COMMIT_GS13 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS13 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
12 COMMIT_GS12 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS12 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
11 COMMIT_GS11 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS11 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn

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Table 3-259. GSxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
10 COMMIT_GS10 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS10 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
9 COMMIT_GS9 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS9 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
8 COMMIT_GS8 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS8 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
7 COMMIT_GS7 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS7 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
6 COMMIT_GS6 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS6 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
5 COMMIT_GS5 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS5 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
4 COMMIT_GS4 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS4 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
3 COMMIT_GS3 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS3 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
2 COMMIT_GS2 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS2 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn

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Table 3-259. GSxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
1 COMMIT_GS1 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS1 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
0 COMMIT_GS0 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS0 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn

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3.14.11.20 GSxMSEL Register (Offset = 44h) [reset = 0h]

GSxMSEL is shown in Figure 3-246 and described in Table 3-260.
Return to the Summary Table.
Global Shared RAM Master Sel Register

Figure 3-246. GSxMSEL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
MSEL_GS15 MSEL_GS14 MSEL_GS13 MSEL_GS12 MSEL_GS11 MSEL_GS10 MSEL_GS9 MSEL_GS8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
MSEL_GS7 MSEL_GS6 MSEL_GS5 MSEL_GS4 MSEL_GS3 MSEL_GS2 MSEL_GS1 MSEL_GS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-260. GSxMSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 MSEL_GS15 R/W 0h Master Select for GS15 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
14 MSEL_GS14 R/W 0h Master Select for GS14 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
13 MSEL_GS13 R/W 0h Master Select for GS13 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
12 MSEL_GS12 R/W 0h Master Select for GS12 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
11 MSEL_GS11 R/W 0h Master Select for GS11 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
10 MSEL_GS10 R/W 0h Master Select for GS10 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
9 MSEL_GS9 R/W 0h Master Select for GS9 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
8 MSEL_GS8 R/W 0h Master Select for GS8 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

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Table 3-260. GSxMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
7 MSEL_GS7 R/W 0h Master Select for GS7 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
6 MSEL_GS6 R/W 0h Master Select for GS6 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
5 MSEL_GS5 R/W 0h Master Select for GS5 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
4 MSEL_GS4 R/W 0h Master Select for GS4 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
3 MSEL_GS3 R/W 0h Master Select for GS3 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
2 MSEL_GS2 R/W 0h Master Select for GS2 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
1 MSEL_GS1 R/W 0h Master Select for GS1 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
0 MSEL_GS0 R/W 0h Master Select for GS0 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

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3.14.11.21 GSxACCPROT0 Register (Offset = 48h) [reset = 0h]

GSxACCPROT0 is shown in Figure 3-247 and described in Table 3-261.
Return to the Summary Table.
Global Shared RAM Access Protection Register 0

Figure 3-247. GSxACCPROT0 Register

31 30 29 28 27 26 25 24
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS3 GS3 GS3
R-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS2 GS2 GS2
R-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS1 GS1 GS1
R-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS0 GS0 GS0
R-0h R/W-0h R/W-0h R/W-0h

Table 3-261. GSxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 DMAWRPROT_GS3 R/W 0h DMA WR Protection For GS3 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_GS3 R/W 0h CPU WR Protection For GS3 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_GS3 R/W 0h Fetch Protection For GS3 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-19 RESERVED R 0h Reserved
18 DMAWRPROT_GS2 R/W 0h DMA WR Protection For GS2 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
17 CPUWRPROT_GS2 R/W 0h CPU WR Protection For GS2 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_GS2 R/W 0h Fetch Protection For GS2 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-11 RESERVED R 0h Reserved
10 DMAWRPROT_GS1 R/W 0h DMA WR Protection For GS1 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

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Table 3-261. GSxACCPROT0 Register Field Descriptions (continued)

Bit Field Type Reset Description
9 CPUWRPROT_GS1 R/W 0h CPU WR Protection For GS1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_GS1 R/W 0h Fetch Protection For GS1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_GS0 R/W 0h DMA WR Protection For GS0 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_GS0 R/W 0h CPU WR Protection For GS0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_GS0 R/W 0h Fetch Protection For GS0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.14.11.22 GSxACCPROT1 Register (Offset = 4Ah) [reset = 0h]

GSxACCPROT1 is shown in Figure 3-248 and described in Table 3-262.
Return to the Summary Table.
Global Shared RAM Access Protection Register 1

Figure 3-248. GSxACCPROT1 Register

31 30 29 28 27 26 25 24
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS7 GS7 GS7
R-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS6 GS6 GS6
R-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS5 GS5 GS5
R-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS4 GS4 GS4
R-0h R/W-0h R/W-0h R/W-0h

Table 3-262. GSxACCPROT1 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 DMAWRPROT_GS7 R/W 0h DMA WR Protection For GS7 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_GS7 R/W 0h CPU WR Protection For GS7 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_GS7 R/W 0h Fetch Protection For GS7 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-19 RESERVED R 0h Reserved
18 DMAWRPROT_GS6 R/W 0h DMA WR Protection For GS6 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
17 CPUWRPROT_GS6 R/W 0h CPU WR Protection For GS6 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_GS6 R/W 0h Fetch Protection For GS6 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-11 RESERVED R 0h Reserved
10 DMAWRPROT_GS5 R/W 0h DMA WR Protection For GS5 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

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Table 3-262. GSxACCPROT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
9 CPUWRPROT_GS5 R/W 0h CPU WR Protection For GS5 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_GS5 R/W 0h Fetch Protection For GS5 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_GS4 R/W 0h DMA WR Protection For GS4 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_GS4 R/W 0h CPU WR Protection For GS4 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_GS4 R/W 0h Fetch Protection For GS4 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.14.11.23 GSxACCPROT2 Register (Offset = 4Ch) [reset = 0h]

GSxACCPROT2 is shown in Figure 3-249 and described in Table 3-263.
Return to the Summary Table.
Global Shared RAM Access Protection Register 2

Figure 3-249. GSxACCPROT2 Register

31 30 29 28 27 26 25 24
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS11 GS11 GS11
R-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS10 GS10 GS10
R-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS9 GS9 GS9
R-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS8 GS8 GS8
R-0h R/W-0h R/W-0h R/W-0h

Table 3-263. GSxACCPROT2 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 DMAWRPROT_GS11 R/W 0h DMA WR Protection For GS11 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_GS11 R/W 0h CPU WR Protection For GS11 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_GS11 R/W 0h Fetch Protection For GS11 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-19 RESERVED R 0h Reserved
18 DMAWRPROT_GS10 R/W 0h DMA WR Protection For GS10 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
17 CPUWRPROT_GS10 R/W 0h CPU WR Protection For GS10 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_GS10 R/W 0h Fetch Protection For GS10 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-11 RESERVED R 0h Reserved
10 DMAWRPROT_GS9 R/W 0h DMA WR Protection For GS9 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

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Table 3-263. GSxACCPROT2 Register Field Descriptions (continued)

Bit Field Type Reset Description
9 CPUWRPROT_GS9 R/W 0h CPU WR Protection For GS9 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_GS9 R/W 0h Fetch Protection For GS9 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_GS8 R/W 0h DMA WR Protection For GS8 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_GS8 R/W 0h CPU WR Protection For GS8 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_GS8 R/W 0h Fetch Protection For GS8 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.14.11.24 GSxACCPROT3 Register (Offset = 4Eh) [reset = 0h]

GSxACCPROT3 is shown in Figure 3-250 and described in Table 3-264.
Return to the Summary Table.
Global Shared RAM Access Protection Register 3

Figure 3-250. GSxACCPROT3 Register

31 30 29 28 27 26 25 24
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS15 GS15 GS15
R-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS14 GS14 GS14
R-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS13 GS13 GS13
R-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS12 GS12 GS12
R-0h R/W-0h R/W-0h R/W-0h

Table 3-264. GSxACCPROT3 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 DMAWRPROT_GS15 R/W 0h DMA WR Protection For GS15 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_GS15 R/W 0h CPU WR Protection For GS15 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_GS15 R/W 0h Fetch Protection For GS15 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-19 RESERVED R 0h Reserved
18 DMAWRPROT_GS14 R/W 0h DMA WR Protection For GS14 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
17 CPUWRPROT_GS14 R/W 0h CPU WR Protection For GS14 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_GS14 R/W 0h Fetch Protection For GS14 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-11 RESERVED R 0h Reserved
10 DMAWRPROT_GS13 R/W 0h DMA WR Protection For GS13 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

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Table 3-264. GSxACCPROT3 Register Field Descriptions (continued)

Bit Field Type Reset Description
9 CPUWRPROT_GS13 R/W 0h CPU WR Protection For GS13 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_GS13 R/W 0h Fetch Protection For GS13 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_GS12 R/W 0h DMA WR Protection For GS12 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_GS12 R/W 0h CPU WR Protection For GS12 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_GS12 R/W 0h Fetch Protection For GS12 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.14.11.25 GSxTEST Register (Offset = 50h) [reset = 0h]

GSxTEST is shown in Figure 3-251 and described in Table 3-265.
Return to the Summary Table.
Global Shared RAM TEST Register

Figure 3-251. GSxTEST Register

31 30 29 28 27 26 25 24
TEST_GS15 TEST_GS14 TEST_GS13 TEST_GS12
R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
TEST_GS11 TEST_GS10 TEST_GS9 TEST_GS8
R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
TEST_GS7 TEST_GS6 TEST_GS5 TEST_GS4
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
TEST_GS3 TEST_GS2 TEST_GS1 TEST_GS0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-265. GSxTEST Register Field Descriptions

Bit Field Type Reset Description
31-30 TEST_GS15 R/W 0h Selects the defferent modes for GS15 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
29-28 TEST_GS14 R/W 0h Selects the defferent modes for GS14 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
27-26 TEST_GS13 R/W 0h Selects the defferent modes for GS13 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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Table 3-265. GSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 TEST_GS12 R/W 0h Selects the defferent modes for GS12 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
23-22 TEST_GS11 R/W 0h Selects the defferent modes for GS11 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
21-20 TEST_GS10 R/W 0h Selects the defferent modes for GS10 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
19-18 TEST_GS9 R/W 0h Selects the defferent modes for GS9 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
17-16 TEST_GS8 R/W 0h Selects the defferent modes for GS8 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
15-14 TEST_GS7 R/W 0h Selects the defferent modes for GS7 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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Table 3-265. GSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 TEST_GS6 R/W 0h Selects the defferent modes for GS6 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
11-10 TEST_GS5 R/W 0h Selects the defferent modes for GS5 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
9-8 TEST_GS4 R/W 0h Selects the defferent modes for GS4 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
7-6 TEST_GS3 R/W 0h Selects the defferent modes for GS3 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
5-4 TEST_GS2 R/W 0h Selects the defferent modes for GS2 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
3-2 TEST_GS1 R/W 0h Selects the defferent modes for GS1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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Table 3-265. GSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 TEST_GS0 R/W 0h Selects the defferent modes for GS0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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3.14.11.26 GSxINIT Register (Offset = 52h) [reset = 0h]

GSxINIT is shown in Figure 3-252 and described in Table 3-266.
Return to the Summary Table.
Global Shared RAM Init Register

Figure 3-252. GSxINIT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
INIT_GS15 INIT_GS14 INIT_GS13 INIT_GS12 INIT_GS11 INIT_GS10 INIT_GS9 INIT_GS8
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h
7 6 5 4 3 2 1 0
INIT_GS7 INIT_GS6 INIT_GS5 INIT_GS4 INIT_GS3 INIT_GS2 INIT_GS1 INIT_GS0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-266. GSxINIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 INIT_GS15 R-0/W1S 0h RAM Initialization control for GS15 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
14 INIT_GS14 R-0/W1S 0h RAM Initialization control for GS14 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
13 INIT_GS13 R-0/W1S 0h RAM Initialization control for GS13 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
12 INIT_GS12 R-0/W1S 0h RAM Initialization control for GS12 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
11 INIT_GS11 R-0/W1S 0h RAM Initialization control for GS11 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
10 INIT_GS10 R-0/W1S 0h RAM Initialization control for GS10 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
9 INIT_GS9 R-0/W1S 0h RAM Initialization control for GS9 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
8 INIT_GS8 R-0/W1S 0h RAM Initialization control for GS8 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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Table 3-266. GSxINIT Register Field Descriptions (continued)

Bit Field Type Reset Description
7 INIT_GS7 R-0/W1S 0h RAM Initialization control for GS7 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
6 INIT_GS6 R-0/W1S 0h RAM Initialization control for GS6 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
5 INIT_GS5 R-0/W1S 0h RAM Initialization control for GS5 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
4 INIT_GS4 R-0/W1S 0h RAM Initialization control for GS4 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
3 INIT_GS3 R-0/W1S 0h RAM Initialization control for GS3 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
2 INIT_GS2 R-0/W1S 0h RAM Initialization control for GS2 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_GS1 R-0/W1S 0h RAM Initialization control for GS1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 INIT_GS0 R-0/W1S 0h RAM Initialization control for GS0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.14.11.27 GSxINITDONE Register (Offset = 54h) [reset = 0h]

GSxINITDONE is shown in Figure 3-253 and described in Table 3-267.
Return to the Summary Table.
Global Shared RAM InitDone Status Register

Figure 3-253. GSxINITDONE Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS
15 14 13 12 11 10 9 8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS
7 6 5 4 3 2 1 0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-267. GSxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 INITDONE_GS15 R 0h RAM Initialization status for GS15 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
14 INITDONE_GS14 R 0h RAM Initialization status for GS14 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
13 INITDONE_GS13 R 0h RAM Initialization status for GS13 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
12 INITDONE_GS12 R 0h RAM Initialization status for GS12 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
11 INITDONE_GS11 R 0h RAM Initialization status for GS11 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
10 INITDONE_GS10 R 0h RAM Initialization status for GS10 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
9 INITDONE_GS9 R 0h RAM Initialization status for GS9 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
8 INITDONE_GS8 R 0h RAM Initialization status for GS8 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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Table 3-267. GSxINITDONE Register Field Descriptions (continued)

Bit Field Type Reset Description
7 INITDONE_GS7 R 0h RAM Initialization status for GS7 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
6 INITDONE_GS6 R 0h RAM Initialization status for GS6 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
5 INITDONE_GS5 R 0h RAM Initialization status for GS5 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
4 INITDONE_GS4 R 0h RAM Initialization status for GS4 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
3 INITDONE_GS3 R 0h RAM Initialization status for GS3 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
2 INITDONE_GS2 R 0h RAM Initialization status for GS2 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_GS1 R 0h RAM Initialization status for GS1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
0 INITDONE_GS0 R 0h RAM Initialization status for GS0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.14.11.28 GSxRAMTEST_LOCK Register (Offset = 56h) [reset = 0h]

GSxRAMTEST_LOCK is shown in Figure 3-254 and described in Table 3-268.
Return to the Summary Table.
Lock register to GSx RAM TEST registers

Figure 3-254. GSxRAMTEST_LOCK Register

31 30 29 28 27 26 25 24
KEY
R-0/W-0h
23 22 21 20 19 18 17 16
KEY
R-0/W-0h
15 14 13 12 11 10 9 8
GS15 GS14 GS13 GS12 GS11 GS10 GS9 GS8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
GS7 GS6 GS5 GS4 GS3 GS2 GS1 GS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-268. GSxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15 GS15 R/W 0h 0: Allows writes to GSxTEST.TEST_GS15 field.
1: Blocks writes to GSxTEST.TEST_GS15 field.
Reset type: SYSRSn
14 GS14 R/W 0h 0: Allows writes to GSxTEST.TEST_GS14 field.
1: Blocks writes to GSxTEST.TEST_GS14 field.
Reset type: SYSRSn
13 GS13 R/W 0h 0: Allows writes to GSxTEST.TEST_GS13 field.
1: Blocks writes to GSxTEST.TEST_GS13 field.
Reset type: SYSRSn
12 GS12 R/W 0h 0: Allows writes to GSxTEST.TEST_GS12 field.
1: Blocks writes to GSxTEST.TEST_GS12 field.
Reset type: SYSRSn
11 GS11 R/W 0h 0: Allows writes to GSxTEST.TEST_GS11 field.
1: Blocks writes to GSxTEST.TEST_GS11 field.
Reset type: SYSRSn
10 GS10 R/W 0h 0: Allows writes to GSxTEST.TEST_GS10 field.
1: Blocks writes to GSxTEST.TEST_GS10 field.
Reset type: SYSRSn
9 GS9 R/W 0h 0: Allows writes to GSxTEST.TEST_GS9 field.
1: Blocks writes to GSxTEST.TEST_GS9 field.
Reset type: SYSRSn
8 GS8 R/W 0h 0: Allows writes to GSxTEST.TEST_GS8 field.
1: Blocks writes to GSxTEST.TEST_GS8 field.
Reset type: SYSRSn
7 GS7 R/W 0h 0: Allows writes to GSxTEST.TEST_GS7 field.
1: Blocks writes to GSxTEST.TEST_GS7 field.
Reset type: SYSRSn
6 GS6 R/W 0h 0: Allows writes to GSxTEST.TEST_GS6 field.
1: Blocks writes to GSxTEST.TEST_GS6 field.
Reset type: SYSRSn

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Table 3-268. GSxRAMTEST_LOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
5 GS5 R/W 0h 0: Allows writes to GSxTEST.TEST_GS5 field.
1: Blocks writes to GSxTEST.TEST_GS5 field.
Reset type: SYSRSn
4 GS4 R/W 0h 0: Allows writes to GSxTEST.TEST_GS4 field.
1: Blocks writes to GSxTEST.TEST_GS4 field.
Reset type: SYSRSn
3 GS3 R/W 0h 0: Allows writes to GSxTEST.TEST_GS3 field.
1: Blocks writes to GSxTEST.TEST_GS3 field.
Reset type: SYSRSn
2 GS2 R/W 0h 0: Allows writes to GSxTEST.TEST_GS2 field.
1: Blocks writes to GSxTEST.TEST_GS2 field.
Reset type: SYSRSn
1 GS1 R/W 0h 0: Allows writes to GSxTEST.TEST_GS1 field.
1: Blocks writes to GSxTEST.TEST_GS1 field.
Reset type: SYSRSn
0 GS0 R/W 0h 0: Allows writes to GSxTEST.TEST_GS0 field.
1: Blocks writes to GSxTEST.TEST_GS0 field.
Reset type: SYSRSn

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3.14.11.29 MSGxLOCK Register (Offset = 60h) [reset = 0h]

MSGxLOCK is shown in Figure 3-255 and described in Table 3-269.
Return to the Summary Table.
Message RAM Config Lock Register

Figure 3-255. MSGxLOCK Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED LOCK_DMATO LOCK_CLA2T LOCK_CPUTO LOCK_CPUTO
CLA2 ODMA CM_MSGRAM CM_MSGRAM
1 0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
LOCK_CPUTO LOCK_DMATO LOCK_CLA1T LOCK_CLA1T LOCK_CPUTO LOCK_CPUTO
CPU_MSGRA CLA1 ODMA OCPU CLA1 CPU_MSGRA
M1 M0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-269. MSGxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
11 LOCK_DMATOCLA2 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for DMA2CLA MSG RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
10 LOCK_CLA2TODMA R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for CLA2DMA MSG RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
9 LOCK_CPUTOCM_MSG R/W 0h Locks the write to access protection, master select, initialization
RAM1 control and test register fields for CPU2CM MSG RAM1:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
8 LOCK_CPUTOCM_MSG R/W 0h Locks the write to access protection, master select, initialization
RAM0 control and test register fields for CPU2CM MSG RAM0:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
7 LOCK_CPUTOCPU_MSG R/W 0h Locks the write to access protection, master select, initialization
RAM1 control and test register fields for CPU2CPU MSG RAM1:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
6 LOCK_DMATOCLA1 R/W 0h Locks the write to access protection, master select, initialization
control and test for DMATOCLA1 RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn

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Table 3-269. MSGxLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
5 LOCK_CLA1TODMA R/W 0h Locks the write to access protection, master select, initialization
control and test for CLA1TODMA RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
2 LOCK_CLA1TOCPU R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for CLA1TOCPU RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
1 LOCK_CPUTOCLA1 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for CPUTOCLA1 RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
0 LOCK_CPUTOCPU_MSG R/W 0h Locks the write to access protection, master select, initialization
RAM0 control and test register fields for CPU2CPU MSG RAM0:
0: Write to ACCPROT, INIT fields are allowed.
1: Write to ACCPROT, INIT fields are blocked.
Reset type: SYSRSn

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3.14.11.30 MSGxCOMMIT Register (Offset = 62h) [reset = 0h]

MSGxCOMMIT is shown in Figure 3-256 and described in Table 3-270.
Return to the Summary Table.
Message RAM Config Lock Commit Register

Figure 3-256. MSGxCOMMIT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED COMMIT_DMA COMMIT_CLA COMMIT_CPU COMMIT_CPU
TOCLA_MSGR TODMA_MSG TOCM_MSGR TOCM_MSGR
AM1 RAM0 AM1 AM0
R-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h
7 6 5 4 3 2 1 0
COMMIT_CPU COMMIT_DMA COMMIT_CLA1 COMMIT_CLA1 COMMIT_CPU COMMIT_CPU
TOCPU_MSGR TOCLA1 TODMA TOCPU TOCLA1 TOCPU_MSGR
AM1 AM0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-270. MSGxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
11 COMMIT_DMATOCLA_M R/WSonce 0h Permanently Locks the write to access protection, master select,
SGRAM1 initialization control and test register fields for DMA2CLA MSG RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
10 COMMIT_CLATODMA_M R/WSonce 0h Permanently Locks the write to access protection, master select,
SGRAM0 initialization control and test register fields for CLA2DMA MSG RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
9 COMMIT_CPUTOCM_MS R/WSonce 0h Permanently Locks the write to access protection, master select,
GRAM1 initialization control and test register fields for CPU2CM MSG RAM1:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
8 COMMIT_CPUTOCM_MS R/WSonce 0h Permanently Locks the write to access protection, master select,
GRAM0 initialization control and test register fields for CPU2CM MSG RAM0:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
7 COMMIT_CPUTOCPU_M R/WSonce 0h Permanently Locks the write to access protection, master select,
SGRAM1 initialization control and test register fields for CPU2CPU MSG
RAM1:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
6 COMMIT_DMATOCLA1 R/WSonce 0h 0: Write to, INIT fields are allowed.
1: Write to, INIT fields are blocked.
Reset type: SYSRSn

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Table 3-270. MSGxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
5 COMMIT_CLA1TODMA R/WSonce 0h 0: Write to, INIT fields are allowed.
1: Write to, INIT fields are blocked.
Reset type: SYSRSn
2 COMMIT_CLA1TOCPU R/WSonce 0h Locks the write to access protection, master select, initialization
control and test register fields for CLA1TOCPU RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
1 COMMIT_CPUTOCLA1 R/WSonce 0h Locks the write to access protection, master select, initialization
control and test register fields for CPUTOCLA1 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
0 COMMIT_CPUTOCPU_M R/WSonce 0h Permanently Locks the write to access protection, master select,
SGRAM0 initialization control and test register fields for D0 RAM:
0: Write to ACCPROT, INIT fields are allowed based on value of lock
field in MSGxLOCK register.
1: Write to ACCPROT, INIT are permanently blocked.
Reset type: SYSRSn

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3.14.11.31 MSGxACCPROT0 Register (Offset = 68h) [reset = 0h]

MSGxACCPROT0 is shown in Figure 3-257 and described in Table 3-271.
Return to the Summary Table.
Message RAM Access Protection Register 0

Figure 3-257. MSGxACCPROT0 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED DMAWRPROT CPUWRPROT_
_CPUTOCPU_ CPUTOCPU_M
MSGRAM0 SGRAM0
R-0h R/W-0h R/W-0h

Table 3-271. MSGxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
23-19 RESERVED R 0h Reserved
15-11 RESERVED R 0h Reserved
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_CPUTOC R/W 0h DMA WR Protection For CPUTOCPU_MSGRAM0 RAM:
PU_MSGRAM0 0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_CPUTOC R/W 0h CPU WR Protection For CPUTOCPU_MSGRAM0 RAM:
PU_MSGRAM0 0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

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3.14.11.32 MSGxACCPROT1 Register (Offset = 6Ah) [reset = 0h]

MSGxACCPROT1 is shown in Figure 3-258 and described in Table 3-272.
Return to the Summary Table.
Message RAM Access Protection Register 1

Figure 3-258. MSGxACCPROT1 Register

31 30 29 28 27 26 25 24
RESERVED DMAWRPROT CPUWRPROT_
_CPUTOCPU_ CPUTOCPU_M
MSGRAM1 SGRAM1
R-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED
R-0h

Table 3-272. MSGxACCPROT1 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 DMAWRPROT_CPUTOC R/W 0h DMA WR Protection For CPUTOCPU_MSGRAM1 RAM:
PU_MSGRAM1 0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_CPUTOC R/W 0h CPU WR Protection For CPUTOCPU_MSGRAM1 RAM:
PU_MSGRAM1 0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
23-19 RESERVED R 0h Reserved
15-11 RESERVED R 0h Reserved
7-3 RESERVED R 0h Reserved

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3.14.11.33 MSGxACCPROT2 Register (Offset = 6Ch) [reset = 0h]

MSGxACCPROT2 is shown in Figure 3-259 and described in Table 3-273.
Return to the Summary Table.
Message RAM Access Protection Register 2

Figure 3-259. MSGxACCPROT2 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8
RESERVED DMAWRPROT CPUWRPROT_
_CPUTOCM_M CPUTOCM_MS
SGRAM1 GRAM1
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED DMAWRPROT CPUWRPROT_
_CPUTOCM_M CPUTOCM_MS
SGRAM0 GRAM0
R-0h R/W-0h R/W-0h

Table 3-273. MSGxACCPROT2 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
15-11 RESERVED R 0h Reserved
10 DMAWRPROT_CPUTOC R/W 0h DMA WR Protection For CPUTOCM_MSGRAM1 RAM:
M_MSGRAM1 0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
9 CPUWRPROT_CPUTOC R/W 0h CPU WR Protection For CPUTOCM_MSGRAM1 RAM:
M_MSGRAM1 0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_CPUTOC R/W 0h DMA WR Protection For CPUTOCM_MSGRAM0 RAM:
M_MSGRAM0 0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_CPUTOC R/W 0h CPU WR Protection For CPUTOCM_MSGRAM0 RAM:
M_MSGRAM0 0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

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3.14.11.34 MSGxTEST Register (Offset = 70h) [reset = 0h]

MSGxTEST is shown in Figure 3-260 and described in Table 3-274.
Return to the Summary Table.
Message RAM TEST Register

Figure 3-260. MSGxTEST Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
TEST_CPUTOCM_MSGRAM1 TEST_CPUTOCM_MSGRAM0
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
TEST_CPUTOCPU_MSGRAM1 TEST_DMATOCLA1 TEST_CLA1TODMA
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
TEST_CLA1TOCPU TEST_CPUTOCLA1 TEST_CPUTOCPU_MSGRAM0
R/W-0h R/W-0h R/W-0h

Table 3-274. MSGxTEST Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R 0h Reserved
19-18 TEST_CPUTOCM_MSGR R/W 0h Selects the defferent modes for CPUTOCM MSG RAM1:
AM1 00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
17-16 TEST_CPUTOCM_MSGR R/W 0h Selects the defferent modes for CPUTOCM MSG RAM0:
AM0 00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
15-14 TEST_CPUTOCPU_MSG R/W 0h Selects the defferent modes for CPUTOCPU MSG RAM0:
RAM1 00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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Table 3-274. MSGxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 TEST_DMATOCLA1 R/W 0h Selects the defferent modes for DMATOCLA1 MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
11-10 TEST_CLA1TODMA R/W 0h Selects the defferent modes for CLA1TODMA MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
5-4 TEST_CLA1TOCPU R/W 0h Selects the defferent modes for CLA1TOCPU MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
3-2 TEST_CPUTOCLA1 R/W 0h Selects the defferent modes for CPUTOCLA1 MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
1-0 TEST_CPUTOCPU_MSG R/W 0h Selects the defferent modes for CPUTOCPU MSG RAM0:
RAM0 00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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3.14.11.35 MSGxINIT Register (Offset = 72h) [reset = 0h]

MSGxINIT is shown in Figure 3-261 and described in Table 3-275.
Return to the Summary Table.
Message RAM Init Register

Figure 3-261. MSGxINIT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED INIT_CPUTOC INIT_CPUTOC
M_MSGRAM1 M_MSGRAM0
R-0h R-0/W1S-0h R-0/W1S-0h
7 6 5 4 3 2 1 0
INIT_CPUTOC INIT_DMATOC INIT_CLA1TOD INIT_CLA1TOC INIT_CPUTOC INIT_CPUTOC
PU_MSGRAM1 LA1 MA PU LA1 PU_MSGRAM0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-275. MSGxINIT Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
9 INIT_CPUTOCM_MSGRA R-0/W1S 0h RAM Initialization control for CPUTOCM MSG RAM1:
M1 0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
8 INIT_CPUTOCM_MSGRA R-0/W1S 0h RAM Initialization control for CPUTOCM MSG RAM0:
M0 0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
7 INIT_CPUTOCPU_MSGR R-0/W1S 0h RAM Initialization control for CPUTOCPU MSG RAM1:
AM1 0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
6 INIT_DMATOCLA1 R-0/W1S 0h RAM Initialization control for DMATOCLA1 MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
5 INIT_CLA1TODMA R-0/W1S 0h RAM Initialization control for CLA1TODMA MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
2 INIT_CLA1TOCPU R-0/W1S 0h RAM Initialization control for CLA1TOCPU MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_CPUTOCLA1 R-0/W1S 0h RAM Initialization control for CPUTOCLA1 MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 INIT_CPUTOCPU_MSGR R-0/W1S 0h RAM Initialization control for CPUTOCPU MSG RAM0:
AM0 0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.14.11.36 MSGxINITDONE Register (Offset = 74h) [reset = 0h]

MSGxINITDONE is shown in Figure 3-262 and described in Table 3-276.
Return to the Summary Table.
Message RAM InitDone Status Register

Figure 3-262. MSGxINITDONE Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED INITDONE_CP INITDONE_CP
UTOCM_MSG UTOCM_MSG
RAM1 RAM0
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
INITDONE_CP INITDONE_DM INITDONE_CL INITDONE_CL INITDONE_CP INITDONE_CP
UTOCPU_MSG ATOCLA1 A1TODMA A1TOCPU UTOCLA1 UTOCPU_MSG
RAM1 RAM0
R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-276. MSGxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
9 INITDONE_CPUTOCM_M R 0h RAM Initialization status for CPUTOCM MSG RAM1:
SGRAM1 0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
8 INITDONE_CPUTOCM_M R 0h RAM Initialization status for CPUTOCM MSG RAM0:
SGRAM0 0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
7 INITDONE_CPUTOCPU_ R 0h RAM Initialization status for CPUTOCPU MSG RAM1:
MSGRAM1 0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
6 INITDONE_DMATOCLA1 R 0h RAM Initialization status for DMATOCLA1 MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
5 INITDONE_CLA1TODMA R 0h RAM Initialization status for CLA1TODMA MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
2 INITDONE_CLA1TOCPU R 0h RAM Initialization status for CLA1TOCPU MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_CPUTOCLA1 R 0h RAM Initialization status for CPUTOCLA1 MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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Table 3-276. MSGxINITDONE Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INITDONE_CPUTOCPU_ R 0h RAM Initialization status for CPUTOCPU MSG RAM:
MSGRAM0 0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.14.11.37 MSGxRAMTEST_LOCK Register (Offset = 76h) [reset = 0h]

MSGxRAMTEST_LOCK is shown in Figure 3-263 and described in Table 3-277.
Return to the Summary Table.
Lock register to MSGx RAM TEST registers

Figure 3-263. MSGxRAMTEST_LOCK Register

31 30 29 28 27 26 25 24
KEY
R-0/W-0h
23 22 21 20 19 18 17 16
KEY
R-0/W-0h
15 14 13 12 11 10 9 8
RESERVED DMATOCLA2 CLA2TODMA CPUTOCM_MS CPUTOCM_MS
GRAM1 GRAM0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CPUTOCPU_M DMATOCLA1 CLA1TODMA CLA2TOCPU CPUTOCLA2 CLA1TOCPU CPUTOCLA1 CPUTOCPU_M
SGRAM1 SGRAM0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-277. MSGxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-12 RESERVED R 0h Reserved
11 DMATOCLA2 R/W 0h 0: Allows writes to MSGxTEST.TEST_DMATOCLA2 field.
1: Blocks writes to MSGxTEST.TEST_DMATOCLA2 field.
Reset type: SYSRSn
10 CLA2TODMA R/W 0h 0: Allows writes to MSGxTEST.TEST_CLA2TODMA field.
1: Blocks writes to MSGxTEST.TEST_CLA2TODMA field.
Reset type: SYSRSn
9 CPUTOCM_MSGRAM1 R/W 0h 0: Allows writes to MSGxTEST.TEST_CPUTOCM_MSGRAM1 field.
1: Blocks writes to MSGxTEST.TEST_CPUTOCM_MSGRAM1 field.
Reset type: SYSRSn
8 CPUTOCM_MSGRAM0 R/W 0h 0: Allows writes to MSGxTEST.TEST_CPUTOCM_MSGRAM0 field.
1: Blocks writes to MSGxTEST.TEST_CPUTOCM_MSGRAM0 field.
Reset type: SYSRSn
7 CPUTOCPU_MSGRAM1 R/W 0h 0: Allows writes to MSGxTEST.TEST_CPUTOCPU_MSGRAM1 field.
1: Blocks writes to MSGxTEST.TEST_CPUTOCPU_MSGRAM1
field.
Reset type: SYSRSn
6 DMATOCLA1 R/W 0h 0: Allows writes to MSGxTEST.TEST_DMATOCLA1 field.
1: Blocks writes to MSGxTEST.TEST_DMATOCLA1 field.
Reset type: SYSRSn
5 CLA1TODMA R/W 0h 0: Allows writes to MSGxTEST.TEST_CLA1TODMA field.
1: Blocks writes to MSGxTEST.TEST_CLA1TODMA field.
Reset type: SYSRSn
4 CLA2TOCPU R/W 0h 0: Allows writes to MSGxTEST.TEST_CLA2TOCPU field.
1: Blocks writes to MSGxTEST.TEST_CLA2TOCPU field.
Reset type: SYSRSn
3 CPUTOCLA2 R/W 0h 0: Allows writes to MSGxTEST.TEST_CPUTOCLA2 field.
1: Blocks writes to MSGxTEST.TEST_CPUTOCLA2 field.
Reset type: SYSRSn

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Table 3-277. MSGxRAMTEST_LOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
2 CLA1TOCPU R/W 0h 0: Allows writes to MSGxTEST.TEST_CLA1TOCPU field.
1: Blocks writes to MSGxTEST.TEST_CLA1TOCPU field.
Reset type: SYSRSn
1 CPUTOCLA1 R/W 0h 0: Allows writes to MSGxTEST.TEST_CPUTOCLA1 field.
1: Blocks writes to MSGxTEST.TEST_CPUTOCLA1 field.
Reset type: SYSRSn
0 CPUTOCPU_MSGRAM0 R/W 0h 0: Allows writes to MSGxTEST.TEST_CPUTOCPU_MSGRAM0 field.
1: Blocks writes to MSGxTEST.TEST_CPUTOCPU_MSGRAM0
field.
Reset type: SYSRSn

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3.14.11.38 ROM_LOCK Register (Offset = A0h) [reset = 0h]

ROM_LOCK is shown in Figure 3-264 and described in Table 3-278.
Return to the Summary Table.
ROM Config Lock Register

Figure 3-264. ROM_LOCK Register

31 30 29 28 27 26 25 24
KEY
R-0/W-0h
23 22 21 20 19 18 17 16
KEY
R-0/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED LOCK_CLADA LOCK_SECUR LOCK_BOOTR
TAROM EROM OM
R-0h R/W-0h R/W-0h R/W-0h

Table 3-278. ROM_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-3 RESERVED R 0h Reserved
2 LOCK_CLADATAROM R/W 0h Locks write access to test control fields (TEST and
FORCE_ERROR) of CLADATAROM
0: Write access allowed
1: Write access blocked
Reset type: SYSRSn
1 LOCK_SECUREROM R/W 0h Locks write access to test control fields (TEST and
FORCE_ERROR) of SECUREROM
0: Write access allowed
1: Write access blocked
Reset type: SYSRSn
0 LOCK_BOOTROM R/W 0h Locks write access to test control fields (TEST and
FORCE_ERROR) of BOOTROM
0: Write access allowed
1: Write access blocked
Reset type: SYSRSn

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3.14.11.39 ROM_TEST Register (Offset = A2h) [reset = 0h]

ROM_TEST is shown in Figure 3-265 and described in Table 3-279.
Return to the Summary Table.
ROM TEST Register

Figure 3-265. ROM_TEST Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED TEST_CLADATAROM TEST_SECUREROM TEST_BOOTROM
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-279. ROM_TEST Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R/W 0h Reserved
5-4 TEST_CLADATAROM R/W 0h Selects the different modes for CLADATAROM:
00: Functional Mode.
01: same as "00" but Parity check on data read is disabled (for
debug)
10: Parity Bits are visible on memory map (for debug)
11: Same as "00" but NMI is not generated on errors, used for
diagnostics. (for diagnostics)
Reset type: SYSRSn
3-2 TEST_SECUREROM R/W 0h Selects the different modes for SECUREROM:
00: Functional Mode.
01: same as "00" but Parity check on data read is disabled (for
debug)
10: Parity Bits are visible on memory map (for debug)
11: Same as "00" but NMI is not generated on errors, used for
diagnostics. (for diagnostics)
Reset type: SYSRSn
1-0 TEST_BOOTROM R/W 0h Selects the different modes for BOOTROM:
00: Functional Mode.
01: same as "00" but Parity check on data read is disabled (for
debug)
10: Parity Bits are visible on memory map (for debug)
11: Same as "00" but NMI is not generated on errors, used for
diagnostics. (for diagnostics)
Reset type: SYSRSn

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3.14.11.40 ROM_FORCE_ERROR Register (Offset = A4h) [reset = 0h]

ROM_FORCE_ERROR is shown in Figure 3-266 and described in Table 3-280.
Return to the Summary Table.
ROM Force Error register

Figure 3-266. ROM_FORCE_ERROR Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED FORCE_CLAD FORCE_SECU FORCE_BOOT
ATAROM_ERR REROM_ERR ROM_ERROR
OR OR
R-0h R/W-0h R/W-0h R/W-0h

Table 3-280. ROM_FORCE_ERROR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 FORCE_CLADATAROM_ R/W 0h Force parity error by feeding inverted Parity bit to Parity checking
ERROR logic.
Reset type: SYSRSn
1 FORCE_SECUREROM_E R/W 0h Force parity error by feeding inverted Parity bit to Parity checking
RROR logic.
Reset type: SYSRSn
0 FORCE_BOOTROM_ER R/W 0h Force parity error by feeding inverted Parity bit to Parity checking
ROR logic.
Reset type: SYSRSn

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3.14.11.41 PERI_MEM_TEST_LOCK Register (Offset = AAh) [reset = 0h]

PERI_MEM_TEST_LOCK is shown in Figure 3-267 and described in Table 3-281.
Return to the Summary Table.
Peripheral Memory Test Lock Register

Figure 3-267. PERI_MEM_TEST_LOCK Register

31 30 29 28 27 26 25 24
KEY
R-0/W-0h
23 22 21 20 19 18 17 16
KEY
R-0/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED LOCK_PERI_M
EM_TEST_CO
NTROL
R-0h R/W-0h

Table 3-281. PERI_MEM_TEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-1 RESERVED R 0h Reserved
0 LOCK_PERI_MEM_TEST R/W 0h Locks write access to register PERI_MEM_TEST_CONTROL
_CONTROL 0: Write access allowed
1: Write access blocked
Reset type: SYSRSn

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3.14.11.42 PERI_MEM_TEST_CONTROL Register (Offset = ACh) [reset = 0h]

PERI_MEM_TEST_CONTROL is shown in Figure 3-268 and described in Table 3-282.
Return to the Summary Table.
Peripheral Memory Test control Register

Figure 3-268. PERI_MEM_TEST_CONTROL Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED EtherCAT_ME EtherCAT_TES RESERVED RESERVED RESERVED RESERVED
M_FORCE_ER T_ENABLE
ROR
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-282. PERI_MEM_TEST_CONTROL Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R/W 0h Reserved
5 EtherCAT_MEM_FORCE R/W 0h Force error bit
_ERROR 0 : No effect
1 : Parity bit going to Parity checker module of EtherCAT is inverted
to introduce parity Error
Reset type: SYSRSn
4 EtherCAT_TEST_ENABL R/W 0h Selects EtherCAT test mode
E 0 : EtherCAT test mode disabled, Error on EtherCAT memory read
access will generate NMI
1 : EtherCAT test mode enabled, Error on EtherCAT memory read
access will NOT generate NMI, used for diagnostics
Reset type: SYSRSn
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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3.14.12 MEMORY_ERROR_REGS Registers

Table 3-283 lists the MEMORY_ERROR_REGS registers. All register offset addresses not listed in
Table 3-283 should be considered as reserved locations and the register contents should not be modified.

Table 3-283. MEMORY_ERROR_REGS Registers

Offset Acronym Register Name Write Protection Section
0h UCERRFLG Uncorrectable Error Flag Register Go
2h UCERRSET Uncorrectable Error Flag Set Register EALLOW Go
4h UCERRCLR Uncorrectable Error Flag Clear Register EALLOW Go
6h UCCPUREADDR Uncorrectable CPU Read Error Address Go
8h UCDMAREADDR Uncorrectable DMA Read Error Address Go
Ah UCCLA1READDR Uncorrectable CLA1 Read Error Address Go
Eh UCECATRAMADDR Uncorrectable etherCAT RAM Read Error Go
Address
20h CERRFLG Correctable Error Flag Register Go
22h CERRSET Correctable Error Flag Set Register EALLOW Go
24h CERRCLR Correctable Error Flag Clear Register EALLOW Go
26h CCPUREADDR Correctable CPU Read Error Address Go
2Ah CCLA1READDR Correctable CLA1 Read Error Address Go
2Eh CERRCNT Correctable Error Count Register Go
30h CERRTHRES Correctable Error Threshold Value Register EALLOW Go
32h CEINTFLG Correctable Error Interrupt Flag Status Register Go
34h CEINTCLR Correctable Error Interrupt Flag Clear Register EALLOW Go
36h CEINTSET Correctable Error Interrupt Flag Set Register EALLOW Go
38h CEINTEN Correctable Error Interrupt Enable Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-284 shows the codes that are
used for access types in this section.

Table 3-284. MEMORY_ERROR_REGS Access Type

Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

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Table 3-284. MEMORY_ERROR_REGS Access Type

Codes (continued)
Access Type Code Description
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.12.1 UCERRFLG Register (Offset = 0h) [reset = 0h]

UCERRFLG is shown in Figure 3-269 and described in Table 3-285.
Return to the Summary Table.
Uncorrectable Error Flag Register

Figure 3-269. UCERRFLG Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ECATRAMRDE CLA1RDERR DMARDERR CPURDERR
RR
R-0h R-0h R-0h R-0h R-0h

Table 3-285. UCERRFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-5 RESERVED R 0h Reserved
4 ECATRAMRDERR R 0h ECAT RAM Read Error Flag
0: No Error.
1: Uncorrectable error occurred on etherCAT RAM.
Reset type: SYSRSn
2 CLA1RDERR R 0h CLA1 Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during CLA1 read.
Reset type: SYSRSn
1 DMARDERR R 0h DMA Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during DMA read.
Reset type: SYSRSn
0 CPURDERR R 0h CPU Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during CPU read.
Reset type: SYSRSn

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3.14.12.2 UCERRSET Register (Offset = 2h) [reset = 0h]

UCERRSET is shown in Figure 3-270 and described in Table 3-286.
Return to the Summary Table.
Uncorrectable Error Flag Set Register

Figure 3-270. UCERRSET Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ECATRAMRDE CLA1RDERR DMARDERR CPURDERR
RR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-286. UCERRSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-5 RESERVED R 0h Reserved
4 ECATRAMRDERR R-0/W1S 0h ECAT RAM Read Error Flag
0: No Action.
1: ECATRAMRDERR Flag in UCERRFLG register will be set and
interrupt will be generated if enabled.
Reset type: SYSRSn
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

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3.14.12.3 UCERRCLR Register (Offset = 4h) [reset = 0h]

UCERRCLR is shown in Figure 3-271 and described in Table 3-287.
Return to the Summary Table.
Uncorrectable Error Flag Clear Register

Figure 3-271. UCERRCLR Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ECATRAMRDE CLA1RDERR DMARDERR CPURDERR
RR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-287. UCERRCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-5 RESERVED R 0h Reserved
4 ECATRAMRDERR R-0/W1S 0h ECAT RAM Read Error Flag
0: No action.
1: ECATRAMRDERR Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in UCERRFLG register will be cleared .
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn

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3.14.12.4 UCCPUREADDR Register (Offset = 6h) [reset = 0h]

UCCPUREADDR is shown in Figure 3-272 and described in Table 3-288.
Return to the Summary Table.
Uncorrectable CPU Read Error Address

Figure 3-272. UCCPUREADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCCPUREADDR
R-0h

Table 3-288. UCCPUREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCCPUREADDR R 0h This register captures the address location for which CPU read/fetch
access resulted in uncorrectable ECC/Parity error.
Reset type: SYSRSn

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3.14.12.5 UCDMAREADDR Register (Offset = 8h) [reset = 0h]

UCDMAREADDR is shown in Figure 3-273 and described in Table 3-289.
Return to the Summary Table.
Uncorrectable DMA Read Error Address

Figure 3-273. UCDMAREADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCDMAREADDR
R-0h

Table 3-289. UCDMAREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCDMAREADDR R 0h This register captures the address location for which DMA read
access resulted in uncorrectable Parity error.
Reset type: SYSRSn

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3.14.12.6 UCCLA1READDR Register (Offset = Ah) [reset = 0h]

UCCLA1READDR is shown in Figure 3-274 and described in Table 3-290.
Return to the Summary Table.
Uncorrectable CLA1 Read Error Address

Figure 3-274. UCCLA1READDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCCLA1READDR
R-0h

Table 3-290. UCCLA1READDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCCLA1READDR R 0h This register captures the address location for which CLA1
read/fetch access resulted in uncorrectable Parity error.
Reset type: SYSRSn

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3.14.12.7 UCECATRAMADDR Register (Offset = Eh) [reset = 0h]

UCECATRAMADDR is shown in Figure 3-275 and described in Table 3-291.
Return to the Summary Table.
Uncorrectable etherCAT RAM Read Error Address

Figure 3-275. UCECATRAMADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCECATRAMADDR
R-0h

Table 3-291. UCECATRAMADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCECATRAMADDR R 0h This register captures the address offset of the etherCAT RAM
location for which read access (access could be from etherCAT
master or from CPU/DMA) resulted in uncorrectable Parity error.
Reset type: SYSRSn

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3.14.12.8 CERRFLG Register (Offset = 20h) [reset = 0h]

CERRFLG is shown in Figure 3-276 and described in Table 3-292.
Return to the Summary Table.
Correctable Error Flag Register

Figure 3-276. CERRFLG Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0h R-0h R-0h

Table 3-292. CERRFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
2 CLA1RDERR R 0h CLA1 Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during CLA1 read.
Reset type: SYSRSn
1 DMARDERR R 0h DMA Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during DMA read.
Reset type: SYSRSn
0 CPURDERR R 0h CPU Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during CPU read.
Reset type: SYSRSn

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3.14.12.9 CERRSET Register (Offset = 22h) [reset = 0h]

CERRSET is shown in Figure 3-277 and described in Table 3-293.
Return to the Summary Table.
Correctable Error Flag Set Register

Figure 3-277. CERRSET Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-293. CERRSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

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3.14.12.10 CERRCLR Register (Offset = 24h) [reset = 0h]

CERRCLR is shown in Figure 3-278 and described in Table 3-294.
Return to the Summary Table.
Correctable Error Flag Clear Register

Figure 3-278. CERRCLR Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-294. CERRCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in CERRFLG register will be cleared.
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in CERRFLG register will be cleared .
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in CERRFLG register will be cleared.
Reset type: SYSRSn

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3.14.12.11 CCPUREADDR Register (Offset = 26h) [reset = 0h]

CCPUREADDR is shown in Figure 3-279 and described in Table 3-295.
Return to the Summary Table.
Correctable CPU Read Error Address

Figure 3-279. CCPUREADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCPUREADDR
R-0h

Table 3-295. CCPUREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 CCPUREADDR R 0h This register captures the address location for which CPU read/fetch
access resulted in correctable ECC error.
Reset type: SYSRSn

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3.14.12.12 CCLA1READDR Register (Offset = 2Ah) [reset = 0h]

CCLA1READDR is shown in Figure 3-280 and described in Table 3-296.
Return to the Summary Table.
Correctable CLA1 Read Error Address

Figure 3-280. CCLA1READDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCLA1READDR
R-0h

Table 3-296. CCLA1READDR Register Field Descriptions

Bit Field Type Reset Description
31-0 CCLA1READDR R 0h This register captures the address location for which CLA1
read/fetch access resulted in correctable ECC error.
Reset type: SYSRSn

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3.14.12.13 CERRCNT Register (Offset = 2Eh) [reset = 0h]

CERRCNT is shown in Figure 3-281 and described in Table 3-297.
Return to the Summary Table.
Correctable Error Count Register

Figure 3-281. CERRCNT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CERRCNT
R-0h R/W-0h

Table 3-297. CERRCNT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 CERRCNT R/W 0h This register holds the count of how many times correctable error
occurred.
Reset type: SYSRSn

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3.14.12.14 CERRTHRES Register (Offset = 30h) [reset = 0h]

CERRTHRES is shown in Figure 3-282 and described in Table 3-298.
Return to the Summary Table.
Correctable Error Threshold Value Register

Figure 3-282. CERRTHRES Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CERRTHRES
R-0h R/W-0h

Table 3-298. CERRTHRES Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 CERRTHRES R/W 0h When value in CERRCNT register is greater than value configured in
this register, corretable interrupt gets generated, if enabled.
Reset type: SYSRSn

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3.14.12.15 CEINTFLG Register (Offset = 32h) [reset = 0h]

CEINTFLG is shown in Figure 3-283 and described in Table 3-299.
Return to the Summary Table.
Correctable Error Interrupt Flag Status Register

Figure 3-283. CEINTFLG Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CEINTFLAG
R-0h R-0h

Table 3-299. CEINTFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTFLAG R 0h Total corrected error count exceeded threshold Flag
0: Total correctable errors < Threshold value configured in
CERRTHRES register.
1: Total correctable errors >= Threshold value configured in
CERRTHRES register.
Reset type: SYSRSn

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3.14.12.16 CEINTCLR Register (Offset = 34h) [reset = 0h]

CEINTCLR is shown in Figure 3-284 and described in Table 3-300.
Return to the Summary Table.
Correctable Error Interrupt Flag Clear Register

Figure 3-284. CEINTCLR Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CEINTCLR
R-0h R-0/W1S-0h

Table 3-300. CEINTCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTCLR R-0/W1S 0h 0: No action.
1: Total corrected error count exceeded flag in CEINTFLG register
will be cleared.
Reset type: SYSRSn

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3.14.12.17 CEINTSET Register (Offset = 36h) [reset = 0h]

CEINTSET is shown in Figure 3-285 and described in Table 3-301.
Return to the Summary Table.
Correctable Error Interrupt Flag Set Register

Figure 3-285. CEINTSET Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CEINTSET
R-0h R-0/W1S-0h

Table 3-301. CEINTSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTSET R-0/W1S 0h 0: No action.
1: Total corrected error count exceeded flag in CEINTFLG register
will be set and interrupt will be generated if enabled.
Reset type: SYSRSn

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3.14.12.18 CEINTEN Register (Offset = 38h) [reset = 0h]

CEINTEN is shown in Figure 3-286 and described in Table 3-302.
Return to the Summary Table.
Correctable Error Interrupt Enable Register

Figure 3-286. CEINTEN Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CEINTEN
R-0h R/W-0h

Table 3-302. CEINTEN Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTEN R/W 0h 0: Correctable Error Interrupt is disabled.
1: Correctable Error Interrupt is enabled.
Reset type: SYSRSn

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3.14.13 NMI_INTRUPT_REGS Registers

Table 3-303 lists the NMI_INTRUPT_REGS registers. All register offset addresses not listed in Table 3-
303 should be considered as reserved locations and the register contents should not be modified.

Table 3-303. NMI_INTRUPT_REGS Registers

Offset Acronym Register Name Write Protection Section
0h NMICFG NMI Configuration Register EALLOW Go
1h NMIFLG NMI Flag Register (SYSRsn Clear) Go
2h NMIFLGCLR NMI Flag Clear Register EALLOW Go
3h NMIFLGFRC NMI Flag Force Register EALLOW Go
4h NMIWDCNT NMI Watchdog Counter Register Go
5h NMIWDPRD NMI Watchdog Period Register EALLOW Go
6h NMISHDFLG NMI Shadow Flag Register Go
7h ERRORSTS Error pin status Go
8h ERRORSTSCLR ERRORSTS clear register EALLOW Go
9h ERRORSTSFRC ERRORSTS force register EALLOW Go
Ah ERRORCTL Error pin control register EALLOW Go
Bh ERRORLOCK Lock register to Error pin registers. EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-304 shows the codes that are
used for access types in this section.

Table 3-304. NMI_INTRUPT_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.13.1 NMICFG Register (Offset = 0h) [reset = 0h]

NMICFG is shown in Figure 3-287 and described in Table 3-305.
Return to the Summary Table.
NMI Configuration Register

Figure 3-287. NMICFG Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED NMIE
R-0-0h R/W1S-0h

Table 3-305. NMICFG Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 NMIE R/W1S 0h When set to 1 any condition will generate an NMI interrupt to the
C28 CPU and kick off the NMI watchdog counter. As part of boot
sequence this bit should be set after the device security related
initialization is complete.
0 NMI disabled
1 NMI enabled
Reset type: SYSRSn

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3.14.13.2 NMIFLG Register (Offset = 1h) [reset = 0h]

NMIFLG is shown in Figure 3-288 and described in Table 3-306.
Return to the Summary Table.
NMI Flag Register (SYSRsn Clear)

Figure 3-288. NMIFLG Register

15 14 13 12 11 10 9 8
CRC_FAIL ECATNMIn CMNMIWDRSn CPU2NMIWDR CPU2WDRSn CLBNMI
Sn
R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
ERADNMI PIEVECTERR CPU2HWBIST CPU1HWBIST FLUNCERR RAMUNCERR CLOCKFAIL NMIINT
ERR ERR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-306. NMIFLG Register Field Descriptions

Bit Field Type Reset Description
14 CRC_FAIL R 0h 0 CPUCRC and CLACRC check has not failed.
1 CPUCRC or CLACRC check has failed.
Reset type: SYSRSn
13 ECATNMIn R 0h 0 No reset request from EtherCAT IP.
1 NMI generated from EtherCAT IP.
No further NMI pulses are generated until this flag is cleared by the
user.
[1] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
12 CMNMIWDRSn R 0h CM NMIWDRSn Reset Indication Flag: This bit indicates if CM's
NMIWDRSn was fired or not.
0 No CM.NMIWDRsn was fired
1 CM.NMIWDRSn was fired to CM
[1] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
10 CPU2NMIWDRSn R 0h CPU2 NMIWDRSn Reset Indication Flag: This bit indicates if CPU2's
NMIWDRSn was fired or not.
0 No CPU2.NMIWDRsn was fired
1 CPU2.NMIWDRSn was fired to CPU2
Note:
[1] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
9 CPU2WDRSn R 0h CPU2 WDRSn Reset Indication Flag: This bit indicates if CPU2's
WDRSn was fired or not.
0 No CPU2.WDRsn was fired
1 CPU2.WDRSn was fired to CPU2
Note:
[1] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
8 CLBNMI R 0h Configurable Logic Block NMI Flag: This bit indicates if an NMI was
generated by the Configurable Logic Block. This bit can only be
cleared by the user writing to the corresponding clear bit in the
NMIFLGCLR register or by an SYSRSn reset:
0,No Configurable Logic Block NMI pending
1,Configurable Logic Block NMI generated
Reset type: SYSRSn
7 ERADNMI R 0h ERAD Module NMI Flag: This bit indicates if an NMI was generated
by the ERAD Module. This bit can only be cleared by the user writing
to the corresponding clear bit in the NMIFLGCLR register or by an
SYSRSn reset:
0,No ERAD NMI pending
1,ERAD NMI generated
Reset type: SYSRSn

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Table 3-306. NMIFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
6 PIEVECTERR R 0h PIE Vector Fetch Error Flag: This bit indicates if an error occurred on
an Vector Fecth by the CPU in the device.
In Dual core system CPU1.NMIWD gets an NMI on an Vector fetch
Error on CPU2. This bit can only be cleared by the user writing to
the corresponding clear bit in the NMIFLGCLR register or by an
SYSRSn reset:
0,No Vector Fetch Error condition (on the other CPU) pending
1,Vector Fetch error condition (on the other CPU) generated
Reset type: SYSRSn
5 CPU2HWBISTERR R 0h HW BIST Error NMI Flag: This bit indicates if the time out error or a
signature mismatch error condition during hardware BIST of C28
CPU2 occurred. This bit can only be cleared by the user writing to
the corresponding clear bit in the NMIFLGCLR register or by an
SYSRSn reset:
0,No C28 HWBIST error condition pending
1,C28 BIST error condition generated
Reset type: SYSRSn
4 CPU1HWBISTERR R 0h HW BIST Error NMI Flag: This bit indicates if the time out error or a
signature mismatch error condition during hardware BIST of C28
CPU1 occurred. This bit can only be cleared by the user writing to
the corresponding clear bit in the NMIFLGCLR register or by an
SYSRSn reset:
0,No C28 HWBIST error condition pending
1,C28 BIST error condition generated
Reset type: SYSRSn
3 FLUNCERR R 0h Flash Uncorrectable Error NMI Flag: This bit indicates if an
uncorrectable error occurred on a C28 Flash access and that
condition is latched. This bit can only be cleared by the user writing
to the corresponding clear bit in the NMIFLGCLR register or by an
SYSRSn reset:
0,No C28 Flash uncorrectable error condition pending
1,C28 Flash uncorrectable error condition generated
Reset type: SYSRSn
2 RAMUNCERR R 0h RAM Uncorrectable Error NMI Flag: This bit indicates if an
uncorrectable error occurred on a RAM access (by any master) and
that condition is latched. This bit can only be cleared by the user
writing to the corresponding clear bit in the NMIFLGCLR register or
by an SYSRSn reset:
0,No RAM uncorrectable error condition pending
1,RAM uncorrectable error condition generated
Note: This nmi is a combination of uncorrectable error in RAMs and
ROMs. ROM parity error would also set this flag.
Reset type: SYSRSn
1 CLOCKFAIL R 0h Clock Fail Interrupt Flag: These bits indicates if the CLOCKFAIL
condition is latched. These bits can only be cleared by the user
writing to the respective bit in the NMIFLGCLR register or by an
SYSRSn reset:
0,No CLOCKFAIL Condition Pending
1,CLOCKFAIL Condition Generated
Reset type: SYSRSn
0 NMIINT R 0h NMI Interrupt Flag: This bit indicates if an NMI interrupt was
generated. This bit can only be cleared by the user writing to the
respective bit in the NMIFLGCLR register or by an SYSRSn reset:
0 No NMI Interrupt Generated
1 NMI Interrupt Generated
No further NMI interrupts pulses are generated until this flag is
cleared by the user.
Reset type: SYSRSn

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3.14.13.3 NMIFLGCLR Register (Offset = 2h) [reset = 0h]

NMIFLGCLR is shown in Figure 3-289 and described in Table 3-307.
Return to the Summary Table.
NMI Flag Clear Register

Figure 3-289. NMIFLGCLR Register

15 14 13 12 11 10 9 8
CRC_FAIL ECATNMIn CMNMIWDRSn CPU2NMIWDR CPU2WDRSn CLBNMI
Sn
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h
7 6 5 4 3 2 1 0
ERADNMI PIEVECTERR CPU2HWBIST CPU1HWBIST FLUNCERR RAMUNCERR CLOCKFAIL NMIINT
ERR ERR
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-307. NMIFLGCLR Register Field Descriptions

Bit Field Type Reset Description
14 CRC_FAIL R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
13 ECATNMIn R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
[3] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
12 CMNMIWDRSn R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
[3] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
10 CPU2NMIWDRSn R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

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Table 3-307. NMIFLGCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
9 CPU2WDRSn R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
[3] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: SYSRSn
8 CLBNMI R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
7 ERADNMI R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
6 PIEVECTERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
5 CPU2HWBISTERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
4 CPU1HWBISTERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
3 FLUNCERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

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Table 3-307. NMIFLGCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
2 RAMUNCERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
1 CLOCKFAIL R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
0 NMIINT R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

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3.14.13.4 NMIFLGFRC Register (Offset = 3h) [reset = 0h]

NMIFLGFRC is shown in Figure 3-290 and described in Table 3-308.
Return to the Summary Table.
NMI Flag Force Register

Figure 3-290. NMIFLGFRC Register

15 14 13 12 11 10 9 8
CRC_FAIL ECATNMIn CMNMIWDRSn CPU2NMIWDR CPU2WDRSn CLBNMI
Sn
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h
7 6 5 4 3 2 1 0
ERADNMI PIEVECTERR CPU2HWBIST CPU1HWBIST FLUNCERR RAMUNCERR CLOCKFAIL RESERVED
ERR ERR
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0-0h

Table 3-308. NMIFLGFRC Register Field Descriptions

Bit Field Type Reset Description
14 CRC_FAIL R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
13 ECATNMIn R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
[1] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
12 CMNMIWDRSn R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
[1] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
10 CPU2NMIWDRSn R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Note:
[1] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: SYSRSn
9 CPU2WDRSn R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Note:
[1] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: SYSRSn
8 CLBNMI R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
7 ERADNMI R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn

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Table 3-308. NMIFLGFRC Register Field Descriptions (continued)

Bit Field Type Reset Description
6 PIEVECTERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
5 CPU2HWBISTERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
4 CPU1HWBISTERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
3 FLUNCERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
2 RAMUNCERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
1 CLOCKFAIL R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
0 RESERVED R-0 0h Reserved

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3.14.13.5 NMIWDCNT Register (Offset = 4h) [reset = 0h]

NMIWDCNT is shown in Figure 3-291 and described in Table 3-309.
Return to the Summary Table.
NMI Watchdog Counter Register

Figure 3-291. NMIWDCNT Register

15 14 13 12 11 10 9 8
NMIWDCNT
R-0h
7 6 5 4 3 2 1 0
NMIWDCNT
R-0h

Table 3-309. NMIWDCNT Register Field Descriptions

Bit Field Type Reset Description
15-0 NMIWDCNT R 0h NMI Watchdog Counter: This 16-bit incremental counter will start
incrementing whenever any one of the enabled FAIL flags are set. If
the counter reaches the period value, an NMIRSn signal is fired
which will then resets the system. The counter will reset to zero
when it reaches the period value and will then restart counting if any
of the enabled FAIL flags are set.
If no enabled FAIL flag is set, then the counter will reset to zero and
remain at zero until an enabled FAIL flag is set.
Normally, the software would respond to the NMI interrupt generated
and clear the offending FLAG(s) before the NMI watchdog triggers a
reset. In some situations, the software may decide to allow the
watchdog to reset the device anyway.
The counter is clocked at the SYSCLKOUT rate.
Reset type: SYSRSn

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3.14.13.6 NMIWDPRD Register (Offset = 5h) [reset = FFFFh]

NMIWDPRD is shown in Figure 3-292 and described in Table 3-310.
Return to the Summary Table.
NMI Watchdog Period Register

Figure 3-292. NMIWDPRD Register

15 14 13 12 11 10 9 8
NMIWDPRD
R/W-FFFFh
7 6 5 4 3 2 1 0
NMIWDPRD
R/W-FFFFh

Table 3-310. NMIWDPRD Register Field Descriptions

Bit Field Type Reset Description
15-0 NMIWDPRD R/W FFFFh NMI Watchdog Period: This 16-bit value contains the period value at
which a reset is generated when the watchdog counter matches. At
reset this value is set at the maximum. The software can decrease
the period value at initialization time.
Reset type: SYSRSn

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3.14.13.7 NMISHDFLG Register (Offset = 6h) [reset = 0h]

NMISHDFLG is shown in Figure 3-293 and described in Table 3-311.
Return to the Summary Table.
NMI Shadow Flag Register

Figure 3-293. NMISHDFLG Register

15 14 13 12 11 10 9 8
CRC_FAIL ECATNMIn CMNMIWDRSn CPU2NMIWDR CPU2WDRSn CLBNMI
Sn
R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
ERADNMI PIEVECTERR CPU2HWBIST CPU1HWBIST FLUNCERR RAMUNCERR CLOCKFAIL RESERVED
ERR ERR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0-0h

Table 3-311. NMISHDFLG Register Field Descriptions

Bit Field Type Reset Description
14 CRC_FAIL R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: SYSRSn
13 ECATNMIn R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
[2] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
12 CMNMIWDRSn R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
[2] This bit is reserved for CPU2.NMIFLG register
Reset type: PORESETn
10 CPU2NMIWDRSn R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn

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Table 3-311. NMISHDFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
9 CPU2WDRSn R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
[2] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: PORESETn
8 CLBNMI R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
7 ERADNMI R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
6 PIEVECTERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
5 CPU2HWBISTERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
4 CPU1HWBISTERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
3 FLUNCERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn

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Table 3-311. NMISHDFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
2 RAMUNCERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
1 CLOCKFAIL R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
0 RESERVED R-0 0h Reserved

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3.14.13.8 ERRORSTS Register (Offset = 7h) [reset = 2h]

ERRORSTS is shown in Figure 3-294 and described in Table 3-312.
Return to the Summary Table.
Error pin status

Figure 3-294. ERRORSTS Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED PINSTS ERROR
R-0-0h R-1h R-0h

Table 3-312. ERRORSTS Register Field Descriptions

Bit Field Type Reset Description
15-2 RESERVED R-0 0h Reserved
1 PINSTS R 1h 0, Error Pin is 0
1, Error Pin is 1
Note: ERRORSTS register can be read by CPU2 but cannot be
cleared by CPU2.
Reset type: PORESETn
0 ERROR R 0h 0,None of the error sources were triggered.
1, One or more of the error sources triggered, or
ERRORSTS.ERROR was set by a write of 1 to
ERRORSTSFRC.ERROR bit. Once set, the ERROR flag can be
cleared by writing 1 to ERRORSTSCLR.ERROR bit. Following are
the events/triggers which can set this bit:
1. If any of flags in NMISHDFLG register is set on CPU1/CPU2
2. Watchdog reset
3. Error on a Pie vector fetch
4. Efuse error
5. If any of flags in NMISHDFLG register is set on CM
On a read of this bit, the pin Error pin state will be returned.
Note: ERRORSTS register can be read by CPU2 but cannot be
cleared by CPU2.
Reset type: PORESETn

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3.14.13.9 ERRORSTSCLR Register (Offset = 8h) [reset = 0h]

ERRORSTSCLR is shown in Figure 3-295 and described in Table 3-313.
Return to the Summary Table.
ERRORSTS clear register

Figure 3-295. ERRORSTSCLR Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED ERROR
R-0-0h R-0/W1S-0h

Table 3-313. ERRORSTSCLR Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERROR R-0/W1S 0h 0,No effect
1, ERRORSTS.ERROR is cleared to 0
Note:This register is available only on CPU1
Reset type: PORESETn

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3.14.13.10 ERRORSTSFRC Register (Offset = 9h) [reset = 0h]

ERRORSTSFRC is shown in Figure 3-296 and described in Table 3-314.
Return to the Summary Table.
ERRORSTS force register

Figure 3-296. ERRORSTSFRC Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED ERROR
R-0-0h R-0/W1S-0h

Table 3-314. ERRORSTSFRC Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERROR R-0/W1S 0h 0,No effect
1, ERRORSTS.ERROR is set to 1
Note:This register is available only on CPU1
Reset type: PORESETn

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3.14.13.11 ERRORCTL Register (Offset = Ah) [reset = 0h]

ERRORCTL is shown in Figure 3-297 and described in Table 3-315.
Return to the Summary Table.
Error pin control register

Figure 3-297. ERRORCTL Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED ERRORPOLSE
L
R-0-0h R/W-0h

Table 3-315. ERRORCTL Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERRORPOLSEL R/W 0h 0, If ERRORSTS.ERROR is 1, Error pin will be driven with a value of
0, else 1.
1, If ERRORSTS.ERROR is 1, Error pin will be driven with a value of
1, else 0.
Note:This register is available only on CPU1
Reset type: PORESETn

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3.14.13.12 ERRORLOCK Register (Offset = Bh) [reset = 0h]

ERRORLOCK is shown in Figure 3-298 and described in Table 3-316.
Return to the Summary Table.
Lock register to Error pin registers.

Figure 3-298. ERRORLOCK Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED ERRORCTL
R-0-0h R/WSonce-0h

Table 3-316. ERRORLOCK Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERRORCTL R/WSonce 0h 0, Writes to ERRORCTL register allowed.
1, Writes to ERRORCTL register is blocked.
Writes of 0 to this bit has no effect. Write of 1 will set this bit, cleared
only on a SYSRSn.
Note:This register is available only on CPU1
Reset type: SYSRSn

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3.14.14 PIE_CTRL_REGS Registers

Table 3-317 lists the PIE_CTRL_REGS registers. All register offset addresses not listed in Table 3-317
should be considered as reserved locations and the register contents should not be modified.

Table 3-317. PIE_CTRL_REGS Registers

Offset Acronym Register Name Write Protection Section
0h PIECTRL ePIE Control Register Go
1h PIEACK Interrupt Acknowledge Register Go
2h PIEIER1 Interrupt Group 1 Enable Register Go
3h PIEIFR1 Interrupt Group 1 Flag Register Go
4h PIEIER2 Interrupt Group 2 Enable Register Go
5h PIEIFR2 Interrupt Group 2 Flag Register Go
6h PIEIER3 Interrupt Group 3 Enable Register Go
7h PIEIFR3 Interrupt Group 3 Flag Register Go
8h PIEIER4 Interrupt Group 4 Enable Register Go
9h PIEIFR4 Interrupt Group 4 Flag Register Go
Ah PIEIER5 Interrupt Group 5 Enable Register Go
Bh PIEIFR5 Interrupt Group 5 Flag Register Go
Ch PIEIER6 Interrupt Group 6 Enable Register Go
Dh PIEIFR6 Interrupt Group 6 Flag Register Go
Eh PIEIER7 Interrupt Group 7 Enable Register Go
Fh PIEIFR7 Interrupt Group 7 Flag Register Go
10h PIEIER8 Interrupt Group 8 Enable Register Go
11h PIEIFR8 Interrupt Group 8 Flag Register Go
12h PIEIER9 Interrupt Group 9 Enable Register Go
13h PIEIFR9 Interrupt Group 9 Flag Register Go
14h PIEIER10 Interrupt Group 10 Enable Register Go
15h PIEIFR10 Interrupt Group 10 Flag Register Go
16h PIEIER11 Interrupt Group 11 Enable Register Go
17h PIEIFR11 Interrupt Group 11 Flag Register Go
18h PIEIER12 Interrupt Group 12 Enable Register Go
19h PIEIFR12 Interrupt Group 12 Flag Register Go

Complex bit access types are encoded to fit into small table cells. Table 3-318 shows the codes that are
used for access types in this section.

Table 3-318. PIE_CTRL_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables

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Table 3-318. PIE_CTRL_REGS Access Type

Codes (continued)
Access Type Code Description
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.14.1 PIECTRL Register (Offset = 0h) [reset = 0h]

PIECTRL is shown in Figure 3-299 and described in Table 3-319.
Return to the Summary Table.
ePIE Control Register

Figure 3-299. PIECTRL Register

15 14 13 12 11 10 9 8
PIEVECT
R-0h
7 6 5 4 3 2 1 0
PIEVECT ENPIE
R-0h R/W-0h

Table 3-319. PIECTRL Register Field Descriptions

Bit Field Type Reset Description
15-1 PIEVECT R 0h These bits indicate the vector address of the vector fetched from the
ePIE vector table. The least significant bit of the address is ignored
and only bits 1 to 15 of the address are shown. The vector value can
be read by the user to determine which interrupt generated the
vector fetch.
Note: When a NMI is serviced, the PIEVECT bit-field does not reflect
the vector as it does for other interrupts.
Reset type: SYSRSn
0 ENPIE R/W 0h Enable vector fetching from ePIE block. This bit must be set to 1 for
peripheral interrupts to work. All ePIE registers (PIEACK, PIEIFR,
PIEIER) can be accessed even when the ePIE block is disabled.
Reset type: SYSRSn

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3.14.14.2 PIEACK Register (Offset = 1h) [reset = 0h]

PIEACK is shown in Figure 3-300 and described in Table 3-320.
Return to the Summary Table.
Acknowledge Register
When an interrupt propagates from the ePIE to a CPU interrupt line, the interrupt group's PIEACK bit is
set. This prevents other interrupts in that group from propagating to the CPU while the first interrupt is
handled. Writing a 1 to a PIEACK bit clears it and allows another interrupt from the corresponding group to
propagate. ISRs for PIE interrupts should clear the group's PIEACK bit before returning from the interrupt.
Writes of 0 are ignored.

Figure 3-300. PIEACK Register

15 14 13 12 11 10 9 8
RESERVED ACK12 ACK11 ACK10 ACK9
R-0-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h
7 6 5 4 3 2 1 0
ACK8 ACK7 ACK6 ACK5 ACK4 ACK3 ACK2 ACK1
R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h

Table 3-320. PIEACK Register Field Descriptions

Bit Field Type Reset Description
15-12 RESERVED R-0 0h Reserved
11 ACK12 R/W1S 0h Acknowledge PIE Interrupt Group 12
Reset type: SYSRSn
10 ACK11 R/W1S 0h Acknowledge PIE Interrupt Group 11
Reset type: SYSRSn
9 ACK10 R/W1S 0h Acknowledge PIE Interrupt Group 10
Reset type: SYSRSn
8 ACK9 R/W1S 0h Acknowledge PIE Interrupt Group 9
Reset type: SYSRSn
7 ACK8 R/W1S 0h Acknowledge PIE Interrupt Group 8
Reset type: SYSRSn
6 ACK7 R/W1S 0h Acknowledge PIE Interrupt Group 7
Reset type: SYSRSn
5 ACK6 R/W1S 0h Acknowledge PIE Interrupt Group 6
Reset type: SYSRSn
4 ACK5 R/W1S 0h Acknowledge PIE Interrupt Group 5
Reset type: SYSRSn
3 ACK4 R/W1S 0h Acknowledge PIE Interrupt Group 4
Reset type: SYSRSn
2 ACK3 R/W1S 0h Acknowledge PIE Interrupt Group 3
Reset type: SYSRSn
1 ACK2 R/W1S 0h Acknowledge PIE Interrupt Group 2
Reset type: SYSRSn
0 ACK1 R/W1S 0h Acknowledge PIE Interrupt Group 1
Reset type: SYSRSn

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3.14.14.3 PIEIER1 Register (Offset = 2h) [reset = 0h]

PIEIER1 is shown in Figure 3-301 and described in Table 3-321.
Return to the Summary Table.
Interrupt Group 1 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.

Figure 3-301. PIEIER1 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-321. PIEIER1 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 1.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 1.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 1.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 1.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 1.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 1.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 1.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 1.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 1.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 1.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 1.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 1.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 1.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 1.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 1.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 1.1
Reset type: SYSRSn

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3.14.14.4 PIEIFR1 Register (Offset = 3h) [reset = 0h]

PIEIFR1 is shown in Figure 3-302 and described in Table 3-322.
Return to the Summary Table.
Interrupt Group 1 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.

Figure 3-302. PIEIFR1 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-322. PIEIFR1 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 1.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 1.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 1.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 1.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 1.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 1.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 1.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 1.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 1.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 1.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 1.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 1.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 1.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 1.3
Reset type: SYSRSn

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Table 3-322. PIEIFR1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INTx2 R/W 0h Flag for Interrupt 1.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 1.1
Reset type: SYSRSn

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3.14.14.5 PIEIER2 Register (Offset = 4h) [reset = 0h]

PIEIER2 is shown in Figure 3-303 and described in Table 3-323.
Return to the Summary Table.
Interrupt Group 2 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.

Figure 3-303. PIEIER2 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-323. PIEIER2 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 2.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 2.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 2.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 2.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 2.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 2.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 2.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 2.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 2.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 2.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 2.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 2.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 2.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 2.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 2.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 2.1
Reset type: SYSRSn

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3.14.14.6 PIEIFR2 Register (Offset = 5h) [reset = 0h]

PIEIFR2 is shown in Figure 3-304 and described in Table 3-324.
Return to the Summary Table.
Interrupt Group 2 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.

Figure 3-304. PIEIFR2 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-324. PIEIFR2 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 2.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 2.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 2.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 2.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 2.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 2.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 2.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 2.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 2.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 2.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 2.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 2.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 2.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 2.3
Reset type: SYSRSn

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Table 3-324. PIEIFR2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INTx2 R/W 0h Flag for Interrupt 2.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 2.1
Reset type: SYSRSn

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3.14.14.7 PIEIER3 Register (Offset = 6h) [reset = 0h]

PIEIER3 is shown in Figure 3-305 and described in Table 3-325.
Return to the Summary Table.
Interrupt Group 3 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.

Figure 3-305. PIEIER3 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-325. PIEIER3 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 3.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 3.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 3.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 3.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 3.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 3.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 3.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 3.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 3.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 3.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 3.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 3.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 3.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 3.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 3.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 3.1
Reset type: SYSRSn

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3.14.14.8 PIEIFR3 Register (Offset = 7h) [reset = 0h]

PIEIFR3 is shown in Figure 3-306 and described in Table 3-326.
Return to the Summary Table.
Interrupt Group 3 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.

Figure 3-306. PIEIFR3 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-326. PIEIFR3 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 3.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 3.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 3.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 3.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 3.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 3.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 3.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 3.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 3.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 3.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 3.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 3.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 3.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 3.3
Reset type: SYSRSn

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Table 3-326. PIEIFR3 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INTx2 R/W 0h Flag for Interrupt 3.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 3.1
Reset type: SYSRSn

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3.14.14.9 PIEIER4 Register (Offset = 8h) [reset = 0h]

PIEIER4 is shown in Figure 3-307 and described in Table 3-327.
Return to the Summary Table.
Interrupt Group 4 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.

Figure 3-307. PIEIER4 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-327. PIEIER4 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 4.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 4.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 4.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 4.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 4.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 4.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 4.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 4.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 4.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 4.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 4.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 4.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 4.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 4.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 4.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 4.1
Reset type: SYSRSn

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3.14.14.10 PIEIFR4 Register (Offset = 9h) [reset = 0h]

PIEIFR4 is shown in Figure 3-308 and described in Table 3-328.
Return to the Summary Table.
Interrupt Group 4 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.

Figure 3-308. PIEIFR4 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-328. PIEIFR4 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 4.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 4.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 4.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 4.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 4.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 4.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 4.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 4.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 4.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 4.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 4.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 4.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 4.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 4.3
Reset type: SYSRSn

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Table 3-328. PIEIFR4 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INTx2 R/W 0h Flag for Interrupt 4.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 4.1
Reset type: SYSRSn

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3.14.14.11 PIEIER5 Register (Offset = Ah) [reset = 0h]

PIEIER5 is shown in Figure 3-309 and described in Table 3-329.
Return to the Summary Table.
Interrupt Group 5 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.

Figure 3-309. PIEIER5 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-329. PIEIER5 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 5.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 5.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 5.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 5.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 5.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 5.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 5.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 5.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 5.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 5.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 5.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 5.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 5.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 5.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 5.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 5.1
Reset type: SYSRSn

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3.14.14.12 PIEIFR5 Register (Offset = Bh) [reset = 0h]

PIEIFR5 is shown in Figure 3-310 and described in Table 3-330.
Return to the Summary Table.
Interrupt Group 5 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.

Figure 3-310. PIEIFR5 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-330. PIEIFR5 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 5.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 5.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 5.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 5.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 5.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 5.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 5.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 5.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 5.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 5.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 5.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 5.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 5.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 5.3
Reset type: SYSRSn

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Table 3-330. PIEIFR5 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INTx2 R/W 0h Flag for Interrupt 5.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 5.1
Reset type: SYSRSn

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3.14.14.13 PIEIER6 Register (Offset = Ch) [reset = 0h]

PIEIER6 is shown in Figure 3-311 and described in Table 3-331.
Return to the Summary Table.
Interrupt Group 6 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.

Figure 3-311. PIEIER6 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-331. PIEIER6 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 6.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 6.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 6.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 6.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 6.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 6.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 6.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 6.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 6.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 6.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 6.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 6.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 6.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 6.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 6.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 6.1
Reset type: SYSRSn

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3.14.14.14 PIEIFR6 Register (Offset = Dh) [reset = 0h]

PIEIFR6 is shown in Figure 3-312 and described in Table 3-332.
Return to the Summary Table.
Interrupt Group 6 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.

Figure 3-312. PIEIFR6 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-332. PIEIFR6 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 6.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 6.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 6.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 6.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 6.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 6.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 6.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 6.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 6.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 6.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 6.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 6.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 6.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 6.3
Reset type: SYSRSn

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Table 3-332. PIEIFR6 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INTx2 R/W 0h Flag for Interrupt 6.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 6.1
Reset type: SYSRSn

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3.14.14.15 PIEIER7 Register (Offset = Eh) [reset = 0h]

PIEIER7 is shown in Figure 3-313 and described in Table 3-333.
Return to the Summary Table.
Interrupt Group 7 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.

Figure 3-313. PIEIER7 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-333. PIEIER7 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 7.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 7.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 7.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 7.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 7.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 7.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 7.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 7.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 7.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 7.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 7.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 7.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 7.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 7.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 7.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 7.1
Reset type: SYSRSn

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3.14.14.16 PIEIFR7 Register (Offset = Fh) [reset = 0h]

PIEIFR7 is shown in Figure 3-314 and described in Table 3-334.
Return to the Summary Table.
Interrupt Group 7 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.

Figure 3-314. PIEIFR7 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-334. PIEIFR7 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 7.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 7.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 7.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 7.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 7.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 7.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 7.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 7.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 7.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 7.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 7.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 7.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 7.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 7.3
Reset type: SYSRSn

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Table 3-334. PIEIFR7 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INTx2 R/W 0h Flag for Interrupt 7.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 7.1
Reset type: SYSRSn

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3.14.14.17 PIEIER8 Register (Offset = 10h) [reset = 0h]

PIEIER8 is shown in Figure 3-315 and described in Table 3-335.
Return to the Summary Table.
Interrupt Group 8 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.

Figure 3-315. PIEIER8 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-335. PIEIER8 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 8.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 8.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 8.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 8.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 8.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 8.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 8.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 8.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 8.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 8.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 8.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 8.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 8.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 8.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 8.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 8.1
Reset type: SYSRSn

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3.14.14.18 PIEIFR8 Register (Offset = 11h) [reset = 0h]

PIEIFR8 is shown in Figure 3-316 and described in Table 3-336.
Return to the Summary Table.
Interrupt Group 8 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.

Figure 3-316. PIEIFR8 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-336. PIEIFR8 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 8.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 8.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 8.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 8.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 8.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 8.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 8.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 8.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 8.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 8.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 8.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 8.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 8.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 8.3
Reset type: SYSRSn

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Table 3-336. PIEIFR8 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INTx2 R/W 0h Flag for Interrupt 8.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 8.1
Reset type: SYSRSn

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3.14.14.19 PIEIER9 Register (Offset = 12h) [reset = 0h]

PIEIER9 is shown in Figure 3-317 and described in Table 3-337.
Return to the Summary Table.
Interrupt Group 9 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.

Figure 3-317. PIEIER9 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-337. PIEIER9 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 9.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 9.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 9.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 9.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 9.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 9.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 9.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 9.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 9.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 9.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 9.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 9.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 9.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 9.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 9.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 9.1
Reset type: SYSRSn

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3.14.14.20 PIEIFR9 Register (Offset = 13h) [reset = 0h]

PIEIFR9 is shown in Figure 3-318 and described in Table 3-338.
Return to the Summary Table.
Interrupt Group 9 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.

Figure 3-318. PIEIFR9 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-338. PIEIFR9 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 9.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 9.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 9.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 9.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 9.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 9.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 9.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 9.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 9.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 9.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 9.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 9.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 9.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 9.3
Reset type: SYSRSn

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Table 3-338. PIEIFR9 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INTx2 R/W 0h Flag for Interrupt 9.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 9.1
Reset type: SYSRSn

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3.14.14.21 PIEIER10 Register (Offset = 14h) [reset = 0h]

PIEIER10 is shown in Figure 3-319 and described in Table 3-339.
Return to the Summary Table.
Interrupt Group 10 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.

Figure 3-319. PIEIER10 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-339. PIEIER10 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 10.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 10.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 10.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 10.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 10.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 10.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 10.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 10.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 10.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 10.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 10.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 10.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 10.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 10.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 10.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 10.1
Reset type: SYSRSn

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3.14.14.22 PIEIFR10 Register (Offset = 15h) [reset = 0h]

PIEIFR10 is shown in Figure 3-320 and described in Table 3-340.
Return to the Summary Table.
Interrupt Group 10 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.

Figure 3-320. PIEIFR10 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-340. PIEIFR10 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 10.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 10.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 10.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 10.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 10.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 10.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 10.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 10.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 10.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 10.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 10.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 10.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 10.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 10.3
Reset type: SYSRSn

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Table 3-340. PIEIFR10 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INTx2 R/W 0h Flag for Interrupt 10.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 10.1
Reset type: SYSRSn

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3.14.14.23 PIEIER11 Register (Offset = 16h) [reset = 0h]

PIEIER11 is shown in Figure 3-321 and described in Table 3-341.
Return to the Summary Table.
Interrupt Group 11 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.

Figure 3-321. PIEIER11 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-341. PIEIER11 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 11.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 11.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 11.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 11.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 11.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 11.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 11.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 11.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 11.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 11.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 11.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 11.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 11.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 11.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 11.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 11.1
Reset type: SYSRSn

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3.14.14.24 PIEIFR11 Register (Offset = 17h) [reset = 0h]

PIEIFR11 is shown in Figure 3-322 and described in Table 3-342.
Return to the Summary Table.
Interrupt Group 11 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.

Figure 3-322. PIEIFR11 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-342. PIEIFR11 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 11.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 11.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 11.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 11.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 11.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 11.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 11.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 11.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 11.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 11.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 11.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 11.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 11.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 11.3
Reset type: SYSRSn

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Table 3-342. PIEIFR11 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INTx2 R/W 0h Flag for Interrupt 11.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 11.1
Reset type: SYSRSn

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3.14.14.25 PIEIER12 Register (Offset = 18h) [reset = 0h]

PIEIER12 is shown in Figure 3-323 and described in Table 3-343.
Return to the Summary Table.
Interrupt Group 12 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.

Figure 3-323. PIEIER12 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-343. PIEIER12 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 12.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 12.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 12.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 12.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 12.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 12.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 12.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 12.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 12.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 12.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 12.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 12.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 12.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 12.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 12.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 12.1
Reset type: SYSRSn

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3.14.14.26 PIEIFR12 Register (Offset = 19h) [reset = 0h]

PIEIFR12 is shown in Figure 3-324 and described in Table 3-344.
Return to the Summary Table.
Interrupt Group 12 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.

Figure 3-324. PIEIFR12 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-344. PIEIFR12 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 12.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 12.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 12.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 12.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 12.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 12.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 12.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 12.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 12.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 12.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 12.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 12.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 12.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 12.3
Reset type: SYSRSn

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Table 3-344. PIEIFR12 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INTx2 R/W 0h Flag for Interrupt 12.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 12.1
Reset type: SYSRSn

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3.14.15 ROM_PREFETCH_REGS Registers

Table 3-345 lists the ROM_PREFETCH_REGS registers. All register offset addresses not listed in
Table 3-345 should be considered as reserved locations and the register contents should not be modified.

Table 3-345. ROM_PREFETCH_REGS Registers

Offset Acronym Register Name Write Protection Section
0h ROMPREFETCH ROM Prefetch Configuration Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-346 shows the codes that are
used for access types in this section.

Table 3-346. ROM_PREFETCH_REGS Access Type

Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.15.1 ROMPREFETCH Register (Offset = 0h) [reset = 1h]

ROMPREFETCH is shown in Figure 3-325 and described in Table 3-347.
Return to the Summary Table.
ROM Prefetch Configuration Register

Figure 3-325. ROMPREFETCH Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED PFENABLE
R-0h R/W-1h

Table 3-347. ROMPREFETCH Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 PFENABLE R/W 1h 0: Prefetch is disabled for secure ROM and boot ROM.
1: Prefetch is enabled for secure ROM and boot ROM.
Reset type: SYSRSn

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3.14.16 ROM_WAIT_STATE_REGS Registers

Table 3-348 lists the ROM_WAIT_STATE_REGS registers. All register offset addresses not listed in
Table 3-348 should be considered as reserved locations and the register contents should not be modified.

Table 3-348. ROM_WAIT_STATE_REGS Registers

Offset Acronym Register Name Write Protection Section
0h ROMWAITSTATE ROM Wait State Configuration Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-349 shows the codes that are
used for access types in this section.

Table 3-349. ROM_WAIT_STATE_REGS Access Type

Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.16.1 ROMWAITSTATE Register (Offset = 0h) [reset = 0h]

ROMWAITSTATE is shown in Figure 3-326 and described in Table 3-350.
Return to the Summary Table.
ROM Wait State Configuration Register

Figure 3-326. ROMWAITSTATE Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED WSDISABLE
R-0h R/W-0h

Table 3-350. ROMWAITSTATE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 WSDISABLE R/W 0h 0: ROM Wait State is enabled. CPU accesses to secure ROM and
boot ROM are are 1-wait.
1: ROM Wait State is disabled. CPU accesses to secure ROM and
boot ROM are 0-wait.
Reset type: SYSRSn

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3.14.17 SYNC_SOC_REGS Registers

Table 26-108 lists the SYNC_SOC_REGS registers. All register offset addresses not listed in Table 26-
108 should be considered as reserved locations and the register contents should not be modified.

Table 3-351. SYNC_SOC_REGS Registers

Offset Acronym Register Name Write Protection Section
0h SYNCSELECT Sync Input and Output Select Register EALLOW Go
2h ADCSOCOUTSELECT External ADC (Off Chip) SOC Select Register EALLOW Go
4h SYNCSOCLOCK SYNCSEL and EXTADCSOC Select Lock EALLOW Go
register

Complex bit access types are encoded to fit into small table cells. Table 26-109 shows the codes that are
used for access types in this section.

Table 3-352. SYNC_SOC_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.17.1 SYNCSELECT Register (Offset = 0h) [reset = 0h]

SYNCSELECT is shown in Figure 26-176 and described in Table 26-110.
Return to the Summary Table.
Sync Input and Output Select Register

Figure 3-327. SYNCSELECT Register

31 30 29 28 27 26 25 24
SYNCOUT
R/W-0h
23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0

Table 3-353. SYNCSELECT Register Field Descriptions

Bit Field Type Reset Description
28-24 SYNCOUT R/W 0h Select Syncout Source:
00000: EPWM1SYNCOUT selected to drive the SYNCOUT pin.
00001: EPWM2SYNCOUT selected to drive the SYNCOUT pin.
00010: EPWM3SYNCOUT selected to drive the SYNCOUT pin.
00011: EPWM4SYNCOUT selected to drive the SYNCOUT pin.
00100: EPWM5SYNCOUT selected to drive the SYNCOUT pin.
00101: EPWM6SYNCOUT selected to drive the SYNCOUT pin.
00110: EPWM7SYNCOUT selected to drive the SYNCOUT pin.
00111: EPWM8SYNCOUT selected to drive the SYNCOUT pin.
01000: EPWM9SYNCOUT selected to drive the SYNCOUT pin.
01001: EPWM10SYNCOUT selected to drive the SYNCOUT pin.
01010: EPWM11SYNCOUT selected to drive the SYNCOUT pin.
01011: EPWM12SYNCOUT selected to drive the SYNCOUT pin.
01100: EPWM13SYNCOUT selected to drive the SYNCOUT pin.
01101: EPWM14SYNCOUT selected to drive the SYNCOUT pin.
01110: EPWM15SYNCOUT selected to drive the SYNCOUT pin.
01111: EPWM16SYNCOUT selected to drive the SYNCOUT pin.
10000: Reserved
10001: Reserved
10010: Reserved
10011: Reserved
10100: Reserved
10101: Reserved
10110: Reserved
10111: Reserved
11000: ECAP1SYNCOUT selected to drive the SYNCOUT pin.
11001: ECAP2SYNCOUT selected to drive the SYNCOUT pin.
11010: ECAP3SYNCOUT selected to drive the SYNCOUT pin.
11011: ECAP4SYNCOUT selected to drive the SYNCOUT pin.
11100: ECAP5SYNCOUT selected to drive the SYNCOUT pin.
11101: ECAP6SYNCOUT selected to drive the SYNCOUT pin.
11110: ECAP7SYNCOUT selected to drive the SYNCOUT pin.
11111: Reserved
Notes:
[1] Reserved position defaults to 00 selection
Reset type: CPU1.SYSRSn
15 RESERVED R-0 0h Reserved

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3.14.17.2 ADCSOCOUTSELECT Register (Offset = 2h) [reset = 0h]

ADCSOCOUTSELECT is shown in Figure 26-177 and described in Table 26-111.
Return to the Summary Table.
External ADC (Off Chip) SOC Select Register

Figure 3-328. ADCSOCOUTSELECT Register

31 30 29 28 27 26 25 24
PWM16SOCBE PWM15SOCBE PWM14SOCBE PWM13SOCBE PWM12SOCBE PWM11SOCBE PWM10SOCBE PWM9SOCBE
N N N N N N N N
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
PWM8SOCBE PWM7SOCBE PWM6SOCBE PWM5SOCBE PWM4SOCBE PWM3SOCBE PWM2SOCBE PWM1SOCBE
N N N N N N N N
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
PWM16SOCAE PWM15SOCAE PWM14SOCAE PWM13SOCAE PWM12SOCAE PWM11SOCAE PWM10SOCAE PWM9SOCAE
N N N N N N N N
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PWM8SOCAE PWM7SOCAE PWM6SOCAE PWM5SOCAE PWM4SOCAE PWM3SOCAE PWM2SOCAE PWM1SOCAE
N N N N N N N N
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-354. ADCSOCOUTSELECT Register Field Descriptions

Bit Field Type Reset Description
31 PWM16SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
30 PWM15SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
29 PWM14SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
28 PWM13SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
27 PWM12SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
26 PWM11SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
25 PWM10SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
24 PWM9SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn

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Table 3-354. ADCSOCOUTSELECT Register Field Descriptions (continued)

Bit Field Type Reset Description
23 PWM8SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
22 PWM7SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
21 PWM6SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
20 PWM5SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
19 PWM4SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
18 PWM3SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
17 PWM2SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
16 PWM1SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
15 PWM16SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
14 PWM15SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
13 PWM14SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
12 PWM13SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
11 PWM12SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
10 PWM11SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

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Table 3-354. ADCSOCOUTSELECT Register Field Descriptions (continued)

Bit Field Type Reset Description
9 PWM10SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
8 PWM9SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
7 PWM8SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
6 PWM7SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
5 PWM6SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
4 PWM5SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
3 PWM4SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
2 PWM3SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
1 PWM2SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
0 PWM1SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

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3.14.17.3 SYNCSOCLOCK Register (Offset = 4h) [reset = 0h]

SYNCSOCLOCK is shown in Figure 26-178 and described in Table 26-112.
Return to the Summary Table.
SYNCSEL and EXTADCSOC Select Lock register

Figure 3-329. SYNCSOCLOCK Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED ADCSOCOUTS SYNCSELECT
ELECT
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-355. SYNCSOCLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 ADCSOCOUTSELECT R/WSonce 0h ADCSOCOUTSELECT Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a
CPU1.SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
0 SYNCSELECT R/WSonce 0h SYNCSELECT Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a
CPU1.SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn

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3.14.18 SYS_STATUS_REGS Registers

Table 3-356 lists the SYS_STATUS_REGS registers. All register offset addresses not listed in Table 3-
356 should be considered as reserved locations and the register contents should not be modified.

Table 3-356. SYS_STATUS_REGS Registers

Offset Acronym Register Name Write Protection Section
0h CM_STATUS_INT_FLG Status of interrupts due to multiple sources of Go
Cortex-M4 reset.
2h CM_STATUS_INT_CLR CM_STATUS_INT_FLG clear register Go
4h CM_STATUS_INT_SET CM_STATUS_INT_FLG set register EALLOW Go
6h CM_STATUS_MASK CM_STATUS_MASK register EALLOW Go
10h SYS_ERR_INT_FLG Status of interrupts due to multiple different Go
errors in the system.
12h SYS_ERR_INT_CLR SYS_ERR_INT_FLG clear register Go
14h SYS_ERR_INT_SET SYS_ERR_INT_FLG set register EALLOW Go
16h SYS_ERR_MASK SYS_ERR_MASK register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-357 shows the codes that are
used for access types in this section.

Table 3-357. SYS_STATUS_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.18.1 CM_STATUS_INT_FLG Register (Offset = 0h) [reset = 0h]

CM_STATUS_INT_FLG is shown in Figure 3-330 and described in Table 3-358.
Return to the Summary Table.
Status of interrupts due to multiple sources of Cortex-M4 reset.
Note: This register is present only on CPU1.

Figure 3-330. CM_STATUS_INT_FLG Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CMVECTRESE CMSYSRESET CMNMIWDRST GINT
T REQ
R-0h R-0h R-0h R-0h R-0h

Table 3-358. CM_STATUS_INT_FLG Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3 CMVECTRESET R 0h 0:CMVECTRESET has not caused a reset of CM
1:CMVECTRESET had caused a reset of CM, an interrupt will be
fired if GINT flag is not set.
Reset type: SYSRSn
2 CMSYSRESETREQ R 0h 0:CMSYSRESETREQ has not caused a reset of CM
1:CMSYSRESETREQ had caused a reset of CM, an interrupt will be
fired if GINT flag is not set.
Reset type: SYSRSn
1 CMNMIWDRST R 0h 0:CMNMIWDRST has not caused a reset of CM
1:CMNMIWDRST had caused a reset of CM, an interrupt will be
fired if GINT flag is not set.
Reset type: SYSRSn
0 GINT R 0h Global Interrupt flag:
0: On any of the flags of CM_STATUS_INT_FLG register being set,
CM_STATUS_INT is pulsed and GINT flag would be set
1: No further interrupts would be fired until GINT flag is cleared
Reset type: SYSRSn

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3.14.18.2 CM_STATUS_INT_CLR Register (Offset = 2h) [reset = 0h]

CM_STATUS_INT_CLR is shown in Figure 3-331 and described in Table 3-359.
Return to the Summary Table.
CM_STATUS_INT_FLG clear register
Note: This register is present only on CPU1.

Figure 3-331. CM_STATUS_INT_CLR Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CMVECTRESE CMSYSRESET CMNMIWDRST GINT
T REQ
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-359. CM_STATUS_INT_CLR Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3 CMVECTRESET R-0/W1S 0h 0: No effect
1: CMVECTRESET flag of CM_STATUS_INT_FLG reister will be
cleared.
Reset type: SYSRSn
2 CMSYSRESETREQ R-0/W1S 0h 0: No effect
1: CMSYSRESETREQ flag of CM_STATUS_INT_FLG reister will be
cleared.
Reset type: SYSRSn
1 CMNMIWDRST R-0/W1S 0h 0: No effect
1: CMNMIWDRST flag of CM_STATUS_INT_FLG reister will be
cleared.
Reset type: SYSRSn
0 GINT R-0/W1S 0h 0: No effect
1: GINT flag of CM_STATUS_INT_FLG reister will be cleared.
Reset type: SYSRSn

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3.14.18.3 CM_STATUS_INT_SET Register (Offset = 4h) [reset = 0h]

CM_STATUS_INT_SET is shown in Figure 3-332 and described in Table 3-360.
Return to the Summary Table.
CM_STATUS_INT_FLG set register
Note: This register is present only on CPU1.

Figure 3-332. CM_STATUS_INT_SET Register

31 30 29 28 27 26 25 24
KEY
R-0/W-0h
23 22 21 20 19 18 17 16
KEY
R-0/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CMVECTRESE CMSYSRESET CMNMIWDRST RESERVED
T REQ
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0h

Table 3-360. CM_STATUS_INT_SET Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field would enable write to the other bit
fields of this register. Any other value written to KEY field would
block the write to the other fields of this register.
Note: Only a 32 bit write to this register will succeed in updating the
fields of this rigister, provided the correct value written to the KEY
field simultaneously
Reset type: SYSRSn
15-4 RESERVED R 0h Reserved
3 CMVECTRESET R-0/W1S 0h 0: No effect
1: CMVECTRESET flag of CM_STATUS_INT_FLG reister will be
set.
Reset type: SYSRSn
2 CMSYSRESETREQ R-0/W1S 0h 0: No effect
1: CMSYSRESETREQ flag of CM_STATUS_INT_FLG reister will be
set.
Reset type: SYSRSn
1 CMNMIWDRST R-0/W1S 0h 0: No effect
1: CMNMIWDRST flag of CM_STATUS_INT_FLG reister will be set.
Reset type: SYSRSn
0 RESERVED R 0h Reserved

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3.14.18.4 CM_STATUS_MASK Register (Offset = 6h) [reset = 0h]

CM_STATUS_MASK is shown in Figure 3-333 and described in Table 3-361.
Return to the Summary Table.
CM_STATUS_MASK register
Note: This register is present only on CPU1.

Figure 3-333. CM_STATUS_MASK Register

31 30 29 28 27 26 25 24
KEY
R-0/W-0h
23 22 21 20 19 18 17 16
KEY
R-0/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CMVECTRESE CMSYSRESET CMNMIWDRST RESERVED
T REQ
R-0h R/W-0h R/W-0h R/W-0h R-0h

Table 3-361. CM_STATUS_MASK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field would enable write to the other bit
fields of this register. Any other value written to KEY field would
block the write to the other fields of this register.
Note: Only a 32 bit write to this register will succeed in updating the
fields of this rigister, provided the correct value written to the KEY
field simultaneously
Reset type: SYSRSn
15-4 RESERVED R 0h Reserved
3 CMVECTRESET R/W 0h 0: CMVECTRESET flag of CM_STATUS_INT_FLG reister will be set
on a hardware event.
1: CMVECTRESET flag of CM_STATUS_INT_FLG reister will not be
set on a hardware event.
Reset type: SYSRSn
2 CMSYSRESETREQ R/W 0h 0: CMSYSRESETREQ flag of CM_STATUS_INT_FLG reister will be
set on a hardware event.
1: CMSYSRESETREQ flag of CM_STATUS_INT_FLG reister will not
be set on a hardware event.
Reset type: SYSRSn
1 CMNMIWDRST R/W 0h 0: CMNMIWDRST flag of CM_STATUS_INT_FLG reister will be set
on a hardware event.
1: CMNMIWDRST flag of CM_STATUS_INT_FLG reister will not be
set on a hardware event.
Reset type: SYSRSn
0 RESERVED R 0h Reserved

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3.14.18.5 SYS_ERR_INT_FLG Register (Offset = 10h) [reset = 0h]

SYS_ERR_INT_FLG is shown in Figure 3-334 and described in Table 3-362.
Return to the Summary Table.
Status of interrupts due to multiple different errors in the system.

Figure 3-334. SYS_ERR_INT_FLG Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED DCC2 DCC1
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
DCC0 AUX_PLL_SLIP SYS_PLL_SLIP RAM_ACC_VI FLASH_CORR RAM_CORREC EMIF_ERR GINT
_NOTSUPPOR _NOTSUPPOR OL ECTABLE_ER TABLE_ERR
TED TED R
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-362. SYS_ERR_INT_FLG Register Field Descriptions

Bit Field Type Reset Description
31-10 RESERVED R 0h Reserved
9 DCC2 R 0h 0: DCC2 has not fired an interrupt.
1: DCC2 has fired an interrupt
Reset type: SYSRSn
8 DCC1 R 0h 0: DCC1 has not fired an interrupt.
1: DCC1 has fired an interrupt
Reset type: SYSRSn
7 DCC0 R 0h 0: DCC0 has not fired an interrupt.
1: DCC0 has fired an interrupt
Reset type: SYSRSn
6 AUX_PLL_SLIP_NOTSUP R 0h RESERVED: This bit is reserved and the value read should be
PORTED ignored.
Reset type: SYSRSn
5 SYS_PLL_SLIP_NOTSUP R 0h RESERVED: This bit is reserved and the value read should be
PORTED ignored.
Reset type: SYSRSn
4 RAM_ACC_VIOL R 0h 0: None of the Masters have violated the set protection rules
1: At least one of the master accesses has violated one or more of
the access protection rules
Reset type: SYSRSn
3 FLASH_CORRECTABLE_ R 0h 0: Number of correctable errors detected has not exceeded the set
ERR threshold in FLASH.
1:Number of correctable errors detected has exceeded the set
threshold in FLASH.
Reset type: SYSRSn
2 RAM_CORRECTABLE_E R 0h 0: Number of correctable errors detected has not exceeded the set
RR threshold in any of the RAMs.
1:Number of correctable errors detected has exceeded the set
threshold in atleast one of the RAMs.
Reset type: SYSRSn
1 EMIF_ERR R 0h 0: EMIF error has not occurred.
1: EMIF error has occurred.
Reset type: SYSRSn

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Table 3-362. SYS_ERR_INT_FLG Register Field Descriptions (continued)

Bit Field Type Reset Description
0 GINT R 0h Global Interrupt flag:
0: On any of the flags of SYS_ERR_INT_FLG register being set,
SYS_ERR_INT is pulsed and GINT flag would be set
1: No further interrupts would be fired until GINT flag is cleared
Reset type: SYSRSn

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3.14.18.6 SYS_ERR_INT_CLR Register (Offset = 12h) [reset = 0h]

SYS_ERR_INT_CLR is shown in Figure 3-335 and described in Table 3-363.
Return to the Summary Table.
SYS_ERR_INT_FLG clear register

Figure 3-335. SYS_ERR_INT_CLR Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED DCC2 DCC1
R-0h R-0/W1S-0h R-0/W1S-0h
7 6 5 4 3 2 1 0
DCC0 AUX_PLL_SLIP SYS_PLL_SLIP RAM_ACC_VI FLASH_CORR RAM_CORREC EMIF_ERR GINT
_NOTSUPPOR _NOTSUPPOR OL ECTABLE_ER TABLE_ERR
TED TED R
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-363. SYS_ERR_INT_CLR Register Field Descriptions

Bit Field Type Reset Description
31-10 RESERVED R 0h Reserved
9 DCC2 R-0/W1S 0h 0: No effect
1: DCC2 flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn
8 DCC1 R-0/W1S 0h 0: No effect
1: DCC1 flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn
7 DCC0 R-0/W1S 0h 0: No effect
1: DCC0 flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn
6 AUX_PLL_SLIP_NOTSUP R-0/W1S 0h RESERVED: This bit is reserved and the value set should always be
PORTED "0"
Reset type: SYSRSn
5 SYS_PLL_SLIP_NOTSUP R-0/W1S 0h RESERVED: This bit is reserved and the value set should always be
PORTED "0"
Reset type: SYSRSn
4 RAM_ACC_VIOL R-0/W1S 0h 0: No effect
1: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will be
cleared.
Reset type: SYSRSn
3 FLASH_CORRECTABLE_ R-0/W1S 0h 0: No effect
ERR 1: FLASH_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG
reister will be cleared.
Reset type: SYSRSn
2 RAM_CORRECTABLE_E R-0/W1S 0h 0: No effect
RR 1: RAM_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister
will be cleared.
Reset type: SYSRSn
1 EMIF_ERR R-0/W1S 0h 0: No effect
1: EMIF_ERR flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn

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Table 3-363. SYS_ERR_INT_CLR Register Field Descriptions (continued)

Bit Field Type Reset Description
0 GINT R-0/W1S 0h 0: No effect
1: GINT flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn

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3.14.18.7 SYS_ERR_INT_SET Register (Offset = 14h) [reset = 0h]

SYS_ERR_INT_SET is shown in Figure 3-336 and described in Table 3-364.
Return to the Summary Table.
SYS_ERR_INT_FLG set register

Figure 3-336. SYS_ERR_INT_SET Register

31 30 29 28 27 26 25 24
KEY
R-0/W-0h
23 22 21 20 19 18 17 16
KEY
R-0/W-0h
15 14 13 12 11 10 9 8
RESERVED DCC2 DCC1
R-0h R-0/W1S-0h R-0/W1S-0h
7 6 5 4 3 2 1 0
DCC0 AUX_PLL_SLIP SYS_PLL_SLIP RAM_ACC_VI FLASH_CORR RAM_CORREC EMIF_ERR RESERVED
_NOTSUPPOR _NOTSUPPOR OL ECTABLE_ER TABLE_ERR
TED TED R
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0h

Table 3-364. SYS_ERR_INT_SET Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field would enable write to the other bit
fields of this register. Any other value written to KEY field would
block the write to the other fields of this register.
Note: Only a 32 bit write to this register will succeed in updating the
fields of this rigister, provided the correct value written to the KEY
field simultaneously
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 DCC2 R-0/W1S 0h 0: No effect
1: DCC2 flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
8 DCC1 R-0/W1S 0h 0: No effect
1: DCC1 flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
7 DCC0 R-0/W1S 0h 0: No effect
1: DCC0 flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
6 AUX_PLL_SLIP_NOTSUP R-0/W1S 0h RESERVED: This bit is reserved and the value set should always be
PORTED "0"
Reset type: SYSRSn
5 SYS_PLL_SLIP_NOTSUP R-0/W1S 0h RESERVED: This bit is reserved and the value set should always be
PORTED "0"
Reset type: SYSRSn
4 RAM_ACC_VIOL R-0/W1S 0h 0: No effect
1: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
3 FLASH_CORRECTABLE_ R-0/W1S 0h 0: No effect
ERR 1: FLASH_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG
reister will be set.
Reset type: SYSRSn

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Table 3-364. SYS_ERR_INT_SET Register Field Descriptions (continued)

Bit Field Type Reset Description
2 RAM_CORRECTABLE_E R-0/W1S 0h 0: No effect
RR 1: RAM_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister
will be set.
Reset type: SYSRSn
1 EMIF_ERR R-0/W1S 0h 0: No effect
1: EMIF_ERR flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
0 RESERVED R 0h Reserved

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3.14.18.8 SYS_ERR_MASK Register (Offset = 16h) [reset = 60h]

SYS_ERR_MASK is shown in Figure 3-337 and described in Table 3-365.
Return to the Summary Table.
SYS_ERR_MASK register

Figure 3-337. SYS_ERR_MASK Register

31 30 29 28 27 26 25 24
KEY
R/W-0h
23 22 21 20 19 18 17 16
KEY
R/W-0h
15 14 13 12 11 10 9 8
RESERVED DCC2 DCC1
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
DCC0 AUX_PLL_SLIP SYS_PLL_SLIP RAM_ACC_VI FLASH_CORR RAM_CORREC EMIF_ERR RESERVED
OL ECTABLE_ER TABLE_ERR
R
R/W-0h R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R-0h

Table 3-365. SYS_ERR_MASK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R/W 0h A value of 0xa5a5 to this field would enable write to the other bit
fields of this register. Any other value written to KEY field would
block the write to the other fields of this register.
Note: Only a 32 bit write to this register will succeed in updating the
fields of this rigister, provided the correct value written to the KEY
field simultaneously
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 DCC2 R/W 0h 0: DCC2 flag of SYS_ERR_INT_FLG reister will be set on a
hardware event.
1: DCC2 flag of SYS_ERR_INT_FLG reister will not be set on a
hardware event.
Reset type: SYSRSn
8 DCC1 R/W 0h 0: DCC1 flag of SYS_ERR_INT_FLG reister will be set on a
hardware event.
1: DCC1 flag of SYS_ERR_INT_FLG reister will not be set on a
hardware event.
Reset type: SYSRSn
7 DCC0 R/W 0h 0: DCC0 flag of SYS_ERR_INT_FLG reister will be set on a
hardware event.
1: DCC0 flag of SYS_ERR_INT_FLG reister will not be set on a
hardware event.
Reset type: SYSRSn
6 AUX_PLL_SLIP R/W 1h RESERVED: This bit is reserved and the value set should always be
"1"
Note: This bit must always be set to 1.
Reset type: SYSRSn
5 SYS_PLL_SLIP R/W 1h RESERVED: This bit is reserved and the value set should always be
"1"
Note: This bit must always be set to 1.
Reset type: SYSRSn

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Table 3-365. SYS_ERR_MASK Register Field Descriptions (continued)

Bit Field Type Reset Description
4 RAM_ACC_VIOL R/W 0h 0: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will be set
on a hardware event.
1: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will not be
set on a hardware event.
Reset type: SYSRSn
3 FLASH_CORRECTABLE_ R/W 0h 0: FLASH_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG
ERR reister will be set on a hardware event.
1: FLASH_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG
reister will not be set on a hardware event.
Reset type: SYSRSn
2 RAM_CORRECTABLE_E R/W 0h 0: RAM_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister
RR will be set on a hardware event.
1: RAM_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister
will not be set on a hardware event.
Reset type: SYSRSn
1 EMIF_ERR R/W 0h 0: EMIF_ERR flag of SYS_ERR_INT_FLG reister will be set on a
hardware event.
1: EMIF_ERR flag of SYS_ERR_INT_FLG reister will not be set on a
hardware event.
Reset type: SYSRSn
0 RESERVED R 0h Reserved

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3.14.19 TEST_ERROR_REGS Registers

Table 3-366 lists the TEST_ERROR_REGS registers. All register offset addresses not listed in Table 3-
366 should be considered as reserved locations and the register contents should not be modified.

Table 3-366. TEST_ERROR_REGS Registers

Offset Acronym Register Name Write Protection Section
0h CPU_RAM_TEST_ERROR_STS Ram Test: Error Status Register Go
2h CPU_RAM_TEST_ERROR_STS_C Ram Test: Error Status Clear Register Go
LR
4h CPU_RAM_TEST_ERROR_ADDR Ram Test: Error address register Go

Complex bit access types are encoded to fit into small table cells. Table 3-367 shows the codes that are
used for access types in this section.

Table 3-367. TEST_ERROR_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.19.1 CPU_RAM_TEST_ERROR_STS Register (Offset = 0h) [reset = 0h]

CPU_RAM_TEST_ERROR_STS is shown in Figure 3-338 and described in Table 3-368.
Return to the Summary Table.
Ram Test: Error Status Register

Figure 3-338. CPU_RAM_TEST_ERROR_STS Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED UNC_ERROR COR_ERROR
R-0h R-0h R-0h

Table 3-368. CPU_RAM_TEST_ERROR_STS Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 UNC_ERROR R 0h 0: Indicates that there were no "un-correctable errors" generated in
the RAM/ROM test mode.
1: Indicates that "un-correctable errors" wer generated in the
RAM/ROM test mode.
Reset type: SYSRSn
0 COR_ERROR R 0h 0: Indicates that there were no "correctable errors" generated in the
RAM/ROM test mode.
1: Indicates that "correctable errors" wer generated in the RAM/ROM
test mode.
Reset type: SYSRSn

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3.14.19.2 CPU_RAM_TEST_ERROR_STS_CLR Register (Offset = 2h) [reset = 0h]

CPU_RAM_TEST_ERROR_STS_CLR is shown in Figure 3-339 and described in Table 3-369.
Return to the Summary Table.
Ram Test: Error Status Clear Register

Figure 3-339. CPU_RAM_TEST_ERROR_STS_CLR Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED UNC_ERROR COR_ERROR
R-0h R-0/W1S-0h R-0/W1S-0h

Table 3-369. CPU_RAM_TEST_ERROR_STS_CLR Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 UNC_ERROR R-0/W1S 0h 0: No effect.
1: Clears the corresponding bit in CPU_RAM_TEST_ERROR_STS
register.
Reset type: SYSRSn
0 COR_ERROR R-0/W1S 0h 0: No effect.
1: Clears the corresponding bit in CPU_RAM_TEST_ERROR_STS
register.
Reset type: SYSRSn

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3.14.19.3 CPU_RAM_TEST_ERROR_ADDR Register (Offset = 4h) [reset = 0h]

CPU_RAM_TEST_ERROR_ADDR is shown in Figure 3-340 and described in Table 3-370.
Return to the Summary Table.
Ram Test: Error address register

Figure 3-340. CPU_RAM_TEST_ERROR_ADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
R-0h

Table 3-370. CPU_RAM_TEST_ERROR_ADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 ADDR R 0h Address of the location where error was detected in RAM/ROM test
modes.
Reset type: SYSRSn

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3.14.20 UID_REGS Registers

Table 3-371 lists the UID_REGS registers. All register offset addresses not listed in Table 3-371 should be
considered as reserved locations and the register contents should not be modified.

Table 3-371. UID_REGS Registers

Offset Acronym Register Name Write Protection Section
0h UID_PSRAND0 UID Psuedo-random 192 bit number Go
2h UID_PSRAND1 UID Psuedo-random 192 bit number Go
4h UID_PSRAND2 UID Psuedo-random 192 bit number Go
6h UID_PSRAND3 UID Psuedo-random 192 bit number Go
8h UID_PSRAND4 UID Psuedo-random 192 bit number Go
Ah UID_PSRAND5 UID Psuedo-random 192 bit number Go
Ch UID_UNIQUE UID Unique 32 bit number Go
Eh UID_CHECKSUM UID Checksum Go

Complex bit access types are encoded to fit into small table cells. Table 3-372 shows the codes that are
used for access types in this section.

Table 3-372. UID_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.20.1 UID_PSRAND0 Register (Offset = 0h) [reset = X]

UID_PSRAND0 is shown in Figure 3-341 and described in Table 3-373.
Return to the Summary Table.
UID Psuedo-random 192 bit number

Figure 3-341. UID_PSRAND0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-373. UID_PSRAND0 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.14.20.2 UID_PSRAND1 Register (Offset = 2h) [reset = X]

UID_PSRAND1 is shown in Figure 3-342 and described in Table 3-374.
Return to the Summary Table.
UID Psuedo-random 192 bit number

Figure 3-342. UID_PSRAND1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-374. UID_PSRAND1 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.14.20.3 UID_PSRAND2 Register (Offset = 4h) [reset = X]

UID_PSRAND2 is shown in Figure 3-343 and described in Table 3-375.
Return to the Summary Table.
UID Psuedo-random 192 bit number

Figure 3-343. UID_PSRAND2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-375. UID_PSRAND2 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.14.20.4 UID_PSRAND3 Register (Offset = 6h) [reset = X]

UID_PSRAND3 is shown in Figure 3-344 and described in Table 3-376.
Return to the Summary Table.
UID Psuedo-random 192 bit number

Figure 3-344. UID_PSRAND3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-376. UID_PSRAND3 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.14.20.5 UID_PSRAND4 Register (Offset = 8h) [reset = X]

UID_PSRAND4 is shown in Figure 3-345 and described in Table 3-377.
Return to the Summary Table.
UID Psuedo-random 192 bit number

Figure 3-345. UID_PSRAND4 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-377. UID_PSRAND4 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.14.20.6 UID_PSRAND5 Register (Offset = Ah) [reset = X]

UID_PSRAND5 is shown in Figure 3-346 and described in Table 3-378.
Return to the Summary Table.
UID Psuedo-random 192 bit number

Figure 3-346. UID_PSRAND5 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-378. UID_PSRAND5 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.14.20.7 UID_UNIQUE Register (Offset = Ch) [reset = X]

UID_UNIQUE is shown in Figure 3-347 and described in Table 3-379.
Return to the Summary Table.
UID Unique 32 bit number

Figure 3-347. UID_UNIQUE Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UniqueID
R-X

Table 3-379. UID_UNIQUE Register Field Descriptions

Bit Field Type Reset Description
31-0 UniqueID R X Unique portion of the UID. This identifier will be unique across all
devices with the same PARTIDH.
Reset type: N/A

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3.14.20.8 UID_CHECKSUM Register (Offset = Eh) [reset = X]

UID_CHECKSUM is shown in Figure 3-348 and described in Table 3-380.
Return to the Summary Table.
Fletcher checksum of UID_PSRAND and UID_UNIQUE registers

Figure 3-348. UID_CHECKSUM Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Checksum
R-X

Table 3-380. UID_CHECKSUM Register Field Descriptions

Bit Field Type Reset Description
31-0 Checksum R X Fletcher checksum of UID_PSRANDx and UID_UINIQUE
Reset type: N/A

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3.14.21 WD_REGS Registers

Table 3-381 lists the WD_REGS registers. All register offset addresses not listed in Table 3-381 should be
considered as reserved locations and the register contents should not be modified.

Table 3-381. WD_REGS Registers

Offset Acronym Register Name Write Protection Section
22h SCSR System Control & Status Register EALLOW Go
23h WDCNTR Watchdog Counter Register EALLOW Go
25h WDKEY Watchdog Reset Key Register EALLOW Go
29h WDCR Watchdog Control Register EALLOW Go
2Ah WDWCR Watchdog Windowed Control Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-382 shows the codes that are
used for access types in this section.

Table 3-382. WD_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.21.1 SCSR Register (Offset = 22h) [reset = 5h]

SCSR is shown in Figure 3-349 and described in Table 3-383.
Return to the Summary Table.
System Control & Status Register
It is recommended to only use 16 bit accesses to write to this register. Use a read-modify-write instruction
may inadvertently clear other bits.

Figure 3-349. SCSR Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED WDINTS WDENINT WDOVERRIDE
R-0-0h R-1h R/W-0h R/W1C-1h

Table 3-383. SCSR Register Field Descriptions

Bit Field Type Reset Description
15-3 RESERVED R-0 0h Reserved
2 WDINTS R 1h Watchdog Interrupt Status
This bit indicates the state of the active-low watchdog interrupt signal
(synchronized to SYSCLK). If the watchdog interrupt is used to wake
the system from a low-power mode, then that mode should only be
entered while this bit is high. Likewise, this bit must go high before
the watchdog can be safely disabled and re-enabled.
Reset type: SYSRSn
0h (R/W) = The watchdog interrupt signal is active.
1h (R/W) = The watchdog interrupt signal is inactive.
1 WDENINT R/W 0h Watchdog Interrupt Enable/Reset Disable
This bit determines whether the watchdog triggers an interrupt
(WAKE/WDOG) or a reset (WDRS) when the counter expires.
Reset type: SYSRSn
0h (R/W) = Counter expiration triggers a reset. This is the default
state on power-up and after any system reset.
1h (R/W) = Counter expiration triggers an interrupt.
0 WDOVERRIDE R/W1C 1h If this bit is set to 1, the user is allowed to change the state of the
Watchdog disable (WDDIS) bit in the Watchdog Control (WDCR)
register. If the WDOVERRIDE bit is cleared, by writing a 1 the
WDDIS bit cannot be modified by the user. Writing a 0 will have no
effect. If this bit is cleared, then it will remain in this state until a reset
occurs. The current state of this bit is readable by the user.
Reset type: SYSRSn

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3.14.21.2 WDCNTR Register (Offset = 23h) [reset = 0h]

WDCNTR is shown in Figure 3-350 and described in Table 3-384.
Return to the Summary Table.
Watchdog Counter Register

Figure 3-350. WDCNTR Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
WDCNTR
R-0h

Table 3-384. WDCNTR Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R-0 0h Reserved
7-0 WDCNTR R 0h Watchdog Counter
These bits contain the current value of the watchdog counter. This
counter increments with each WDCLK (INTOSC1) cycle. If the
counter overflows, either an interrupt or a reset is generated based
on the value of the WDINTEN bit in the SCSR register. If the correct
value is written to the WDKEY register, this counter is reset to zero.
Reset type: IORSn

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3.14.21.3 WDKEY Register (Offset = 25h) [reset = 0h]

WDKEY is shown in Figure 3-351 and described in Table 3-385.
Return to the Summary Table.
Watchdog Reset Key Register

Figure 3-351. WDKEY Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
WDKEY
R/W-0h

Table 3-385. WDKEY Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R-0 0h Reserved
7-0 WDKEY R/W 0h Watchdog Counter Reset
Writing 0x55 followed by 0xAA will cause the watchdog counter to
reset to zero, preventing an overflow. Writing other values has no
effect. Reads of this register return the value of the WDCR register.
Reset type: IORSn

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3.14.21.4 WDCR Register (Offset = 29h) [reset = 0h]

WDCR is shown in Figure 3-352 and described in Table 3-386.
Return to the Summary Table.
Watchdog Control Register

Figure 3-352. WDCR Register

15 14 13 12 11 10 9 8
RESERVED WDPRECLKDIV
R-0-0h R/W-0h
7 6 5 4 3 2 1 0
WDFLG WDDIS WDCHK WDPS
R/W1S-0h R/W-0h R-0/W-0h R/W-0h

Table 3-386. WDCR Register Field Descriptions

Bit Field Type Reset Description
15-12 RESERVED R-0 0h Reserved
11-8 WDPRECLKDIV R/W 0h Watchdog Clock Pre-divider
These bits determine the watchdog clock pre-divider, which is the
first of the two dividers between INTOSC1 and the watchdog counter
clock (WDCLK). The frequency of WDCLK is given by the formulas:
PREDIVCLK = INTOSC1 / Pre-divider
WDCLK = PREDIVCLK / Prescaler
Reset type: IORSn
0h (R/W) = PREDIVCLK = INTOSC1 / 512
1h (R/W) = PREDIVCLK = INTOSC1 / 1024
2h (R/W) = PREDIVCLK = INTOSC1 / 2048
3h (R/W) = PREDIVCLK = INTOSC1 / 4096
4h (R/W) = Reserved
5h (R/W) = Reserved
6h (R/W) = Reserved
7h (R/W) = Reserved
8h (R/W) = PREDIVCLK = INTOSC1 / 2
9h (R/W) = PREDIVCLK = INTOSC1 / 4
Ah (R/W) = PREDIVCLK = INTOSC1 / 8
Bh (R/W) = PREDIVCLK = INTOSC1 / 16
Ch (R/W) = PREDIVCLK = INTOSC1 / 32
Dh (R/W) = PREDIVCLK = INTOSC1 / 64
Eh (R/W) = PREDIVCLK = INTOSC1 / 128
Fh (R/W) = PREDIVCLK = INTOSC1 / 256
7 WDFLG R/W1S 0h Watchdog reset status flag bit. This bit, if set, indicates a watchdog
reset (WDRSTn) generated the reset condition. If 0, then it was en
external device or power-up reset condition. This bit remains latched
until the user writes a 1 to clear the condition. Writes of 0 will be
ignored.
Reset type: IORSn
6 WDDIS R/W 0h Watchdog Disable
Setting this bit disables the watchdog module. Clearing this bit
enables the watchdog module. This bit can be locked by the
WDOVERRIDE bit in the SCSR register. The watchdog is enabled
on reset.
Reset type: IORSn
5-3 WDCHK R-0/W 0h Watchdog Check Bits
During any write to this register, these bits must be written with the
value 101 (binary). Writing any other value will immediately trigger
the watchdog reset or interrupt.
Reset type: IORSn

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Table 3-386. WDCR Register Field Descriptions (continued)

Bit Field Type Reset Description
2-0 WDPS R/W 0h Watchdog Clock Prescaler
These bits determine the watchdog clock prescaler, which is the
second of the two dividers between INTOSC1 and the watchdog
counter clock (WDCLK). The frequency of WDCLK is given by the
formulas:
PREDIVCLK = INTOSC1 / Pre-divider
WDCLK = PREDIVCLK / Prescaler
The watchdog reset or interrupt pulse is 512 INTOSC1 cycles long,
so the counter period must be longer. To guarantee this, the product
of the prescaler and pre-divider must be greater than or equal to
four. The default prescaler value is 1.
Reset type: IORSn
0h (R/W) = WDCLK = PREDIVCLK / 1
1h (R/W) = WDCLK = PREDIVCLK / 1
2h (R/W) = WDCLK = PREDIVCLK / 2
3h (R/W) = WDCLK = PREDIVCLK / 4
4h (R/W) = WDCLK = PREDIVCLK / 8
5h (R/W) = WDCLK = PREDIVCLK / 16
6h (R/W) = WDCLK = PREDIVCLK / 32
7h (R/W) = WDCLK = PREDIVCLK / 64

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3.14.21.5 WDWCR Register (Offset = 2Ah) [reset = 0h]

WDWCR is shown in Figure 3-353 and described in Table 3-387.
Return to the Summary Table.
Watchdog Windowed Control Register

Figure 3-353. WDWCR Register

15 14 13 12 11 10 9 8
RESERVED FIRSTKEY
R-0-0h R-0h
7 6 5 4 3 2 1 0
MIN
R/W-0h

Table 3-387. WDWCR Register Field Descriptions

Bit Field Type Reset Description
15-9 RESERVED R-0 0h Reserved
8 FIRSTKEY R 0h This bit indicates if the 1st valid WDKEY (0x55 + 0xAA) got detected
after MIN was configured to a non-zero value
0: First Valid Key after non-zero MIN configuration has not happened
yet
1: First Valid key after non-zero MIN configuration got detected
Notes:
[1] If MIN = 0, this bit is never set
[2] If MIN is changed back to 0x0 from a non-zero value, this bit is
auto-cleared
[3] This bit is added for debug purposes only
Reset type: IORSn
7-0 MIN R/W 0h Watchdog Window Threshold
These bits specify the lower limit of the watchdog counter reset
window. If the counter is reset via the WDKEY register before the
counter value reaches the value in this register, the watchdog
immediately triggers a reset or interrupt.
Reset type: IORSn

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3.14.22 XINT_REGS Registers

Table 3-388 lists the XINT_REGS registers. All register offset addresses not listed in Table 3-388 should
be considered as reserved locations and the register contents should not be modified.

Table 3-388. XINT_REGS Registers

Offset Acronym Register Name Write Protection Section
0h XINT1CR XINT1 configuration register Go
1h XINT2CR XINT2 configuration register Go
2h XINT3CR XINT3 configuration register Go
3h XINT4CR XINT4 configuration register Go
4h XINT5CR XINT5 configuration register Go
8h XINT1CTR XINT1 counter register Go
9h XINT2CTR XINT2 counter register Go
Ah XINT3CTR XINT3 counter register Go

Complex bit access types are encoded to fit into small table cells. Table 3-389 shows the codes that are
used for access types in this section.

Table 3-389. XINT_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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3.14.22.1 XINT1CR Register (Offset = 0h) [reset = 0h]

XINT1CR is shown in Figure 3-354 and described in Table 3-390.
Return to the Summary Table.
XINT1 configuration register

Figure 3-354. XINT1CR Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-390. XINT1CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.14.22.2 XINT2CR Register (Offset = 1h) [reset = 0h]

XINT2CR is shown in Figure 3-355 and described in Table 3-391.
Return to the Summary Table.
XINT2 configuration register

Figure 3-355. XINT2CR Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-391. XINT2CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.14.22.3 XINT3CR Register (Offset = 2h) [reset = 0h]

XINT3CR is shown in Figure 3-356 and described in Table 3-392.
Return to the Summary Table.
XINT3 configuration register

Figure 3-356. XINT3CR Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-392. XINT3CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.14.22.4 XINT4CR Register (Offset = 3h) [reset = 0h]

XINT4CR is shown in Figure 3-357 and described in Table 3-393.
Return to the Summary Table.
XINT4 configuration register

Figure 3-357. XINT4CR Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-393. XINT4CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.14.22.5 XINT5CR Register (Offset = 4h) [reset = 0h]

XINT5CR is shown in Figure 3-358 and described in Table 3-394.
Return to the Summary Table.
XINT5 configuration register

Figure 3-358. XINT5CR Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-394. XINT5CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.14.22.6 XINT1CTR Register (Offset = 8h) [reset = 0h]

XINT1CTR is shown in Figure 3-359 and described in Table 3-395.
Return to the Summary Table.
XINT1 counter register

Figure 3-359. XINT1CTR Register

15 14 13 12 11 10 9 8
INTCTR
R-0h
7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-395. XINT1CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until the
next valid interrupt edge is detected. The counter must only be reset
by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.14.22.7 XINT2CTR Register (Offset = 9h) [reset = 0h]

XINT2CTR is shown in Figure 3-360 and described in Table 3-396.
Return to the Summary Table.
XINT2 counter register

Figure 3-360. XINT2CTR Register

15 14 13 12 11 10 9 8
INTCTR
R-0h
7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-396. XINT2CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until the
next valid interrupt edge is detected. The counter must only be reset
by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.14.22.8 XINT3CTR Register (Offset = Ah) [reset = 0h]

XINT3CTR is shown in Figure 3-361 and described in Table 3-397.
Return to the Summary Table.
XINT3 counter register

Figure 3-361. XINT3CTR Register

15 14 13 12 11 10 9 8
INTCTR
R-0h
7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-397. XINT3CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until the
next valid interrupt edge is detected. The counter must only be reset
by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.14.23 Register to Driverlib Function Mapping

Table 3-398. CPUTIMER Registers to Driverlib Functions

File Driverlib Function
TIM
cputimer.h CPUTimer_getTimerCount
PRD
cputimer.h CPUTimer_setPeriod
TCR
cputimer.c CPUTimer_setEmulationMode
cputimer.h CPUTimer_clearOverflowFlag
cputimer.h CPUTimer_disableInterrupt
cputimer.h CPUTimer_enableInterrupt
cputimer.h CPUTimer_reloadTimerCounter
cputimer.h CPUTimer_stopTimer
cputimer.h CPUTimer_resumeTimer
cputimer.h CPUTimer_startTimer
cputimer.h CPUTimer_getTimerOverflowStatus
TPR
cputimer.h CPUTimer_setPreScaler
TPRH
cputimer.h CPUTimer_setPreScaler

Table 3-399. WWD Registers to Driverlib Functions

File Driverlib Function
SCSR
sysctl.h SysCtl_setWatchdogMode
sysctl.h SysCtl_isWatchdogInterruptActive
WDCNTR
sysctl.h SysCtl_getWatchdogCounterValue
WDKEY
sysctl.h SysCtl_serviceWatchdog
WDCR
sysctl.h SysCtl_resetDevice
sysctl.h SysCtl_disableWatchdog
sysctl.h SysCtl_enableWatchdog
sysctl.h SysCtl_setWatchdogPredivider
sysctl.h SysCtl_setWatchdogPrescaler
WDWCR
sysctl.h SysCtl_setWatchdogWindowValue

Table 3-400. ASYSCTL Registers to Driverlib Functions

File Driverlib Function
TSNSCTL
asysctl.h ASysCtl_enableTemperatureSensor
asysctl.h ASysCtl_disableTemperatureSensor
LOCK
asysctl.h ASysCtl_lockTemperatureSensor

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Table 3-401. PIE Registers to Driverlib Functions

File Driverlib Function
CTRL
interrupt.c Interrupt_initModule
interrupt.h Interrupt_defaultHandler
interrupt.h Interrupt_enablePIE
interrupt.h Interrupt_disablePIE
ACK
interrupt.c Interrupt_disable
interrupt.h Interrupt_clearACKGroup
IER1
interrupt.c Interrupt_initModule
interrupt.c Interrupt_enable
interrupt.c Interrupt_disable
IFR1
interrupt.c Interrupt_initModule
IER2
interrupt.c Interrupt_initModule
IFR2
interrupt.c Interrupt_initModule
IER3
interrupt.c Interrupt_initModule
IFR3
interrupt.c Interrupt_initModule
IER4
interrupt.c Interrupt_initModule
IFR4
interrupt.c Interrupt_initModule
IER5
interrupt.c Interrupt_initModule
IFR5
interrupt.c Interrupt_initModule
IER6
interrupt.c Interrupt_initModule
IFR6
interrupt.c Interrupt_initModule
IER7
interrupt.c Interrupt_initModule
IFR7
interrupt.c Interrupt_initModule
IER8
interrupt.c Interrupt_initModule
IFR8
interrupt.c Interrupt_initModule
IER9
interrupt.c Interrupt_initModule
IFR9
interrupt.c Interrupt_initModule
IER10
interrupt.c Interrupt_initModule

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Table 3-401. PIE Registers to Driverlib Functions (continued)

File Driverlib Function
IFR10
interrupt.c Interrupt_initModule
IER11
interrupt.c Interrupt_initModule
IFR11
interrupt.c Interrupt_initModule
IER12
interrupt.c Interrupt_initModule
IFR12
interrupt.c Interrupt_initModule

Table 3-402. SYSCTL Registers to Driverlib Functions

File Driverlib Function
CLKSEM
sysctl.c SysCtl_setSemOwner
sysctl.h SysCtl_getSemOwner
CLKCFGLOCK1
sysctl.c SysCtl_lockClkConfig
CLKSRCCTL1
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setAuxClock
sysctl.c SysCtl_selectXTAL
sysctl.c SysCtl_selectXTALSingleEnded
sysctl.c SysCtl_selectOscSource
sysctl.h SysCtl_turnOnOsc
sysctl.h SysCtl_turnOffOsc
CLKSRCCTL2
can.h CAN_selectClockSource
sysctl.c SysCtl_getAuxClock
sysctl.c SysCtl_setAuxClock
CLKSRCCTL3
sysctl.h SysCtl_selectClockOutSource
SYSPLLCTL1
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
SYSPLLMULT
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
SYSPLLSTS
sysctl.c SysCtl_setClock
AUXPLLCTL1
sysctl.c SysCtl_getAuxClock
sysctl.c SysCtl_setAuxClock
AUXPLLMULT
sysctl.c SysCtl_getAuxClock
sysctl.c SysCtl_setAuxClock

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Table 3-402. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
AUXPLLSTS
sysctl.c SysCtl_setAuxClock
SYSCLKDIVSEL
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
sysctl.h SysCtl_setPLLSysClk
AUXCLKDIVSEL
sysctl.c SysCtl_getAuxClock
sysctl.c SysCtl_setAuxClock
sysctl.h SysCtl_setAuxPLLClk
sysctl.h SysCtl_setMCANClk
PERCLKDIVSEL
sysctl.h SysCtl_setEPWMClockDivider
sysctl.h SysCtl_setEMIF1ClockDivider
sysctl.h SysCtl_setEMIF2ClockDivider
XCLKOUTDIVSEL
sysctl.h SysCtl_setXClk
CLBCLKCTL
sysctl.h SysCtl_setCLBClk
LOSPCP
sysctl.c SysCtl_getLowSpeedClock
sysctl.h SysCtl_setLowSpeedClock
MCDCR
sysctl.h SysCtl_enableMCD
sysctl.h SysCtl_disableMCD
sysctl.h SysCtl_isMCDClockFailureDetected
sysctl.h SysCtl_resetMCD
sysctl.h SysCtl_connectMCDClockSource
sysctl.h SysCtl_disconnectMCDClockSource
X1CNT
sysctl.c SysCtl_pollX1Counter
sysctl.h SysCtl_getExternalOscCounterValue
sysctl.h SysCtl_clearExternalOscCounterValue
XTALCR
sysctl.c SysCtl_setAuxClock
sysctl.c SysCtl_selectXTAL
sysctl.c SysCtl_selectXTALSingleEnded
sysctl.h SysCtl_setExternalOscMode
sysctl.h SysCtl_turnOnOsc
ETHERCATCLKCTL
sysctl.h SysCtl_setECatClk
CMCLKCTL
sysctl.h SysCtl_setCMClk
sysctl.h SysCtl_setEnetClk
CPUSYSLOCK1
sysctl.c SysCtl_lockSysConfig

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Table 3-402. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
PIEVERRADDR
sysctl.h SysCtl_getPIEVErrAddr
ETHERCATCTL
sysctl.h SysCtl_enableEthercatI2Cloopback
sysctl.h SysCtl_disableEthercatI2Cloopback
PCLKCR0
sysctl.h SysCtl_enablePeripheral
sysctl.h SysCtl_disablePeripheral
PCLKCR1
- See PCLKCR0
PCLKCR2
- See PCLKCR0
PCLKCR3
- See PCLKCR0
PCLKCR4
- See PCLKCR0
PCLKCR6
- See PCLKCR0
PCLKCR7
- See PCLKCR0
PCLKCR8
- See PCLKCR0
PCLKCR9
- See PCLKCR0
PCLKCR10
- See PCLKCR0
PCLKCR11
- See PCLKCR0
PCLKCR13
- See PCLKCR0
PCLKCR14
- See PCLKCR0
PCLKCR16
- See PCLKCR0
SIMRESET
sysctl.h SysCtl_simulateReset
LPMCR
sysctl.h SysCtl_enterIdleMode
sysctl.h SysCtl_enterStandbyMode
sysctl.h SysCtl_setStandbyQualificationPeriod
sysctl.h SysCtl_enableWatchdogStandbyWakeup
sysctl.h SysCtl_disableWatchdogStandbyWakeup
GPIOLPMSEL0
sysctl.h SysCtl_enableLPMWakeupPin
sysctl.h SysCtl_disableLPMWakeupPin
GPIOLPMSEL1
sysctl.h SysCtl_enableLPMWakeupPin

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Table 3-402. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.h SysCtl_disableLPMWakeupPin
TMR2CLKCTL
cputimer.h CPUTimer_selectClockSource
sysctl.h SysCtl_setCputimer2Clk
RESCCLR
sysctl.h SysCtl_clearWatchdogResetStatus
RESC
sysctl.h SysCtl_getResetCause
sysctl.h SysCtl_clearResetCause
sysctl.h SysCtl_getWatchdogResetStatus
sysctl.h SysCtl_clearWatchdogResetStatus
CLA1TASKSRCSEL1
cla.c CLA_setTriggerSource
CLA1TASKSRCSEL2
cla.c CLA_setTriggerSource
DMACHSRCSEL1
dma.c DMA_configMode
DMACHSRCSEL2
dma.c DMA_configMode
DEVCFGLOCK1
sysctl.h SysCtl_lockCPUSelectRegs
PARTIDL
sysctl.c SysCtl_getDeviceParametric
PARTIDH
sysctl.c SysCtl_getDeviceParametric
REVID
sysctl.h SysCtl_getDeviceRevision
PERCNF1
sysctl.h SysCtl_readADCWrapper
FUSEERR
sysctl.h SysCtl_getEfuseError
SOFTPRES0
sysctl.h SysCtl_resetPeripheral
SOFTPRES1
- See SOFTPRES0
SOFTPRES2
- See SOFTPRES0
SOFTPRES3
- See SOFTPRES0
SOFTPRES4
- See SOFTPRES0
SOFTPRES6
- See SOFTPRES0
SOFTPRES7
- See SOFTPRES0
SOFTPRES8
- See SOFTPRES0

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Table 3-402. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
SOFTPRES9
- See SOFTPRES0
SOFTPRES10
- See SOFTPRES0
SOFTPRES11
- See SOFTPRES0
SOFTPRES13
- See SOFTPRES0
SOFTPRES14
- See SOFTPRES0
SOFTPRES16
- See SOFTPRES0
CPUSEL0
sysctl.h SysCtl_selectCPUForPeripheral
CPUSEL1
- See CPUSEL0
CPUSEL2
- See CPUSEL0
CPUSEL4
- See CPUSEL0
CPUSEL5
- See CPUSEL0
CPUSEL6
- See CPUSEL0
CPUSEL7
- See CPUSEL0
CPUSEL8
- See CPUSEL0
CPUSEL9
- See CPUSEL0
CPUSEL11
- See CPUSEL0
CPUSEL12
- See CPUSEL0
CPUSEL14
- See CPUSEL0
CPUSEL16
- See CPUSEL0
CPU2RESCTL
sysctl.c SysCtl_controlCPU2Reset
RSTSTAT
sysctl.h SysCtl_isCPU2Reset
sysctl.h SysCtl_getCPU2ResetStatus
sysctl.h SysCtl_clearCPU2ResetStatus
LPMSTAT
sysctl.h SysCtl_getCPU2LPMStatus

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Table 3-402. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
USBTYPE
sysctl.c SysCtl_configureType
sysctl.c SysCtl_isConfigTypeLocked
ECAPTYPE
sysctl.c SysCtl_configureType
sysctl.c SysCtl_isConfigTypeLocked
SDFMTYPE
sysctl.c SysCtl_configureType
sysctl.c SysCtl_isConfigTypeLocked
MEMMAPTYPE
sysctl.c SysCtl_configureType
sysctl.c SysCtl_isConfigTypeLocked
PERIPH_AC_LOCK
sysctl.h SysCtl_lockAccessControlRegs
CMRESCTL
sysctl.c SysCtl_controlCMReset
sysctl.h SysCtl_isCMReset
CMTOCPU1NMICTL
sysctl.h SysCtl_enableCMtoCPUNMI
sysctl.h SysCtl_disableCMtoCPUNMI
sysctl.h SysCtl_getCMtoCPUNMI
CMTOCPU1INTCTL
sysctl.h SysCtl_enableCMtoCPUInterrupt
sysctl.h SysCtl_disableCMtoCPUInterrupt
sysctl.h SysCtl_getCMtoCPUInterrupt
PALLOCATE0
sysctl.h SysCtl_allocateSharedPeripheral
CM_CONF_REGS_LOCK
sysctl.h SysCtl_lockCMConfig
CM_STATUS_INT_FLG
sysctl.h SysCtl_getCMInterruptStatus
CM_STATUS_INT_CLR
sysctl.h SysCtl_clearCMInterruptStatus
CM_STATUS_INT_SET
sysctl.h SysCtl_setCMInterruptStatus
CM_STATUS_MASK
sysctl.h SysCtl_getCMInterruptStatusMask
sysctl.h SysCtl_setCMInterruptStatusMask
SYS_ERR_INT_FLG
sysctl.h SysCtl_getInterruptStatus
SYS_ERR_INT_CLR
sysctl.h SysCtl_clearInterruptStatus
SYS_ERR_INT_SET
sysctl.h SysCtl_setInterruptStatus
SYS_ERR_MASK
sysctl.h SysCtl_getInterruptStatusMask
sysctl.h SysCtl_setInterruptStatusMask

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Table 3-402. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
SYNCSELECT
sysctl.h SysCtl_setSyncOutputConfig
ADCSOCOUTSELECT
sysctl.h SysCtl_enableExtADCSOCSource
sysctl.h SysCtl_disableExtADCSOCSource
SYNCSOCLOCK
sysctl.h SysCtl_lockExtADCSOCSelect
sysctl.h SysCtl_lockSyncSelect

Table 3-403. NMI Registers to Driverlib Functions

File Driverlib Function
CFG
sysctl.h SysCtl_enableNMIGlobalInterrupt
FLG
sysctl.h SysCtl_getNMIStatus
sysctl.h SysCtl_getNMIFlagStatus
sysctl.h SysCtl_isNMIFlagSet
sysctl.h SysCtl_clearNMIStatus
sysctl.h SysCtl_clearAllNMIFlags
sysctl.h SysCtl_forceNMIFlags
FLGCLR
sysctl.h SysCtl_clearNMIStatus
sysctl.h SysCtl_clearAllNMIFlags
FLGFRC
sysctl.h SysCtl_forceNMIFlags
WDCNT
sysctl.h SysCtl_getNMIWatchdogCounter
WDPRD
sysctl.h SysCtl_setNMIWatchdogPeriod
sysctl.h SysCtl_getNMIWatchdogPeriod
SHDFLG
sysctl.h SysCtl_getNMIShadowFlagStatus
sysctl.h SysCtl_isNMIShadowFlagSet
ERRORSTS
sysctl.h SysCtl_isErrorTriggered
sysctl.h SysCtl_getErrorPinStatus
sysctl.h SysCtl_forceError
sysctl.h SysCtl_clearError
ERRORSTSCLR
sysctl.h SysCtl_clearError
ERRORSTSFRC
sysctl.h SysCtl_forceError
ERRORCTL
sysctl.h SysCtl_selectErrPinPolarity
ERRORLOCK
sysctl.h SysCtl_lockErrControl

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Table 3-404. XINT Registers to Driverlib Functions

File Driverlib Function
1CR
gpio.c GPIO_setInterruptPin
gpio.h GPIO_setInterruptType
gpio.h GPIO_getInterruptType
gpio.h GPIO_enableInterrupt
gpio.h GPIO_disableInterrupt
2CR
- See 1CR
3CR
- See 1CR
4CR
- See 1CR
5CR
- See 1CR

Table 3-405. DCSM Registers to Driverlib Functions

File Driverlib Function
Z1_LINKPOINTER
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_readZone1CSMPwd
dcsm.h DCSM_getZone1LinkPointerError
Z1_OTPSECLOCK
dcsm.h DCSM_getZone1OTPSecureLockStatus
Z1_LINKPOINTERERR
dcsm.h DCSM_getZone1LinkPointerError
Z1_CSMKEY0
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CSMKEY1
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CSMKEY2
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CSMKEY3
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CR
dcsm.h DCSM_secureZone1
dcsm.h DCSM_getZone1CSMSecurityStatus
dcsm.h DCSM_getZone1ControlStatus
Z1_EXEONLYSECT1R
dcsm.c DCSM_getZone1FlashEXEStatus
Z1_EXEONLYSECT2R
dcsm.c DCSM_getZone1FlashEXEStatus
Z1_EXEONLYRAM1R
dcsm.c DCSM_getZone1RAMEXEStatus

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Table 3-405. DCSM Registers to Driverlib Functions (continued)

File Driverlib Function
Z2_LINKPOINTER
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_readZone2CSMPwd
dcsm.h DCSM_getZone2LinkPointerError
Z2_OTPSECLOCK
dcsm.h DCSM_getZone2OTPSecureLockStatus
Z2_LINKPOINTERERR
dcsm.h DCSM_getZone2LinkPointerError
Z2_CSMKEY0
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CSMKEY1
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CSMKEY2
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CSMKEY3
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CR
dcsm.h DCSM_secureZone2
dcsm.h DCSM_getZone2CSMSecurityStatus
dcsm.h DCSM_getZone2ControlStatus
Z2_EXEONLYSECT1R
dcsm.c DCSM_getZone2FlashEXEStatus
Z2_EXEONLYSECT2R
dcsm.c DCSM_getZone2FlashEXEStatus
Z2_EXEONLYRAM1R
dcsm.c DCSM_getZone2RAMEXEStatus
FLSEM
dcsm.c DCSM_claimZoneSemaphore
dcsm.c DCSM_releaseZoneSemaphore
SECTSTAT1
dcsm.h DCSM_getFlashSectorZone
RAMSTAT1
dcsm.h DCSM_getRAMZone
SECERRSTAT
dcsm.h DCSM_getFlashErrorStatus
SECERRCLR
dcsm.h DCSM_clearFlashErrorStatus
SECERRFRC
dcsm.h DCSM_forceFlashErrorStatus

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Table 3-406. MEMCFG Registers to Driverlib Functions

File Driverlib Function
DXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
DXCOMMIT
memcfg.c MemCfg_commitConfig
DXACCPROT0
memcfg.c MemCfg_setProtection
DXTEST
memcfg.c MemCfg_setTestMode
DXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
DXINITDONE
memcfg.c MemCfg_getInitStatus
DXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
LSXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
LSXCOMMIT
memcfg.c MemCfg_commitConfig
LSXMSEL
memcfg.c MemCfg_setLSRAMMasterSel
LSXCLAPGM
memcfg.h MemCfg_setCLAMemType
LSXACCPROT0
memcfg.c MemCfg_setProtection
LSXTEST
memcfg.c MemCfg_setTestMode
LSXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
LSXINITDONE
memcfg.c MemCfg_getInitStatus
LSXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
GSXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
GSXCOMMIT
memcfg.c MemCfg_commitConfig
GSXMSEL
memcfg.c MemCfg_setGSRAMMasterSel
GSXACCPROT0
memcfg.c MemCfg_setProtection

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Table 3-406. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
GSXACCPROT1
- See GSXACCPROT0
GSXACCPROT2
- See GSXACCPROT0
GSXACCPROT3
- See GSXACCPROT0
GSXTEST
memcfg.c MemCfg_setTestMode
GSXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
GSXINITDONE
memcfg.c MemCfg_getInitStatus
GSXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
MSGXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
MSGXCOMMIT
memcfg.c MemCfg_commitConfig
MSGXACCPROT0
memcfg.c MemCfg_setProtection
MSGXTEST
memcfg.c MemCfg_setTestMode
MSGXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
MSGXINITDONE
memcfg.c MemCfg_getInitStatus
MSGXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
ROM_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
ROM_TEST
memcfg.c MemCfg_setTestMode
ROM_FORCE_ERROR
memcfg.c MemCfg_forceMemError
PERI_MEM_TEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
PERI_MEM_TEST_CONTROL
memcfg.c MemCfg_forceMemError
memcfg.c MemCfg_enablePeriMemTestMode
memcfg.c MemCfg_disablePeriMemTestMode

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Table 3-406. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
EMIF1LOCK
emif.h EMIF_lockAccessConfig
emif.h EMIF_unlockAccessConfig
EMIF1COMMIT
emif.h EMIF_commitAccessConfig
EMIF1MSEL
emif.h EMIF_selectMaster
EMIF1ACCPROT0
emif.h EMIF_setAccessProtection
NMAVFLG
memcfg.h MemCfg_getViolationInterruptStatus
NMAVSET
memcfg.h MemCfg_forceViolationInterrupt
NMAVCLR
memcfg.h MemCfg_clearViolationInterruptStatus
NMAVINTEN
memcfg.h MemCfg_enableViolationInterrupt
memcfg.h MemCfg_disableViolationInterrupt
NMCPURDAVADDR
memcfg.c MemCfg_getViolationAddress
NMCPUWRAVADDR
memcfg.c MemCfg_getViolationAddress
MAVFLG
memcfg.h MemCfg_getViolationInterruptStatus
MAVSET
memcfg.h MemCfg_forceViolationInterrupt
MAVCLR
memcfg.h MemCfg_clearViolationInterruptStatus
MAVINTEN
memcfg.h MemCfg_enableViolationInterrupt
memcfg.h MemCfg_disableViolationInterrupt
MCPUFAVADDR
memcfg.c MemCfg_getViolationAddress
UCERRFLG
memcfg.h MemCfg_getUncorrErrorStatus
UCERRSET
memcfg.h MemCfg_forceUncorrErrorStatus
UCERRCLR
memcfg.h MemCfg_clearUncorrErrorStatus
UCCPUREADDR
memcfg.c MemCfg_getUncorrErrorAddress
UCDMAREADDR
memcfg.c MemCfg_getUncorrErrorAddress
CERRFLG
memcfg.h MemCfg_getCorrErrorStatus
CERRSET
memcfg.c MemCfg_getCorrErrorAddress

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Table 3-406. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
memcfg.h MemCfg_forceCorrErrorStatus
CERRCLR
memcfg.c MemCfg_getCorrErrorAddress
memcfg.h MemCfg_clearCorrErrorStatus
CCPUREADDR
memcfg.c MemCfg_getCorrErrorAddress
CERRCNT
memcfg.h MemCfg_getCorrErrorCount
CERRTHRES
memcfg.h MemCfg_setCorrErrorThreshold
CEINTFLG
memcfg.h MemCfg_getCorrErrorInterruptStatus
CEINTCLR
memcfg.h MemCfg_clearCorrErrorInterruptStatus
CEINTSET
memcfg.h MemCfg_forceCorrErrorInterrupt
CEINTEN
memcfg.h MemCfg_enableCorrErrorInterrupt
memcfg.h MemCfg_disableCorrErrorInterrupt
ROMWAITSTATE
memcfg.h MemCfg_enableROMWaitState
memcfg.h MemCfg_disableROMWaitState
ROMPREFETCH
memcfg.h MemCfg_enableROMPrefetch
memcfg.h MemCfg_disableROMPrefetch
CPU_RAM_TEST_ERROR_STS
memcfg.h MemCfg_getDiagErrorStatus
memcfg.h MemCfg_clearDiagErrorStatus
CPU_RAM_TEST_ERROR_STS_CLR
memcfg.h MemCfg_clearDiagErrorStatus
CPU_RAM_TEST_ERROR_ADDR
memcfg.h MemCfg_getDiagErrorAddress

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 Chapter 4
SPRUII0B – May 2019 – Revised May 2020

C28x Processor

This chapter contains a short description of the C28x Processor and extended instruction sets.
Further information can be found in the following document(s):
TMS320C28x CPU and Instruction Set Reference Guide
TMS320C28x Extended Instruction Sets Technical Reference Manual
Accelerators: Enhancing the Capabilities of the C2000 MCU Family Technical Brief
TMS320C28x FPU Primer

Topic ........................................................................................................................... Page

4.1 Introduction ..................................................................................................... 676

4.2 Features .......................................................................................................... 676
4.3 Floating-Point Unit ........................................................................................... 676
4.4 Trigonometric Math Unit ................................................................................... 676
4.5 VCRC Unit ....................................................................................................... 677

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4.1 Introduction
The C28x CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal
processing, reduced instruction set computing (RISC), microcontroller architectures, firmware, and tool
sets.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction
Set Reference Guide.

4.2 Features
The CPU features include a modified Harvard architecture and circular addressing. The RISC features are
single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and
unpacking, and bit manipulation. The modified Harvard architecture of the CPU enables instruction and
data fetches to be performed in parallel. The CPU can read instructions and data while it writes data
simultaneously to maintain the single-cycle instruction operation across the pipeline.

4.3 Floating-Point Unit

The C28x plus floating-point (C28x+FPU64) processor extends the capabilities of the C28x fixed-point
CPU by adding registers and instructions to support IEEE single-precision and double-percision floating
point operations.
Devices with the C28x+FPU64 include the standard C28x register set plus an additional set of floating-
point unit registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be
used in high-priority interrupts for fast context save and restore of the floating-point registers.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

4.4 Trigonometric Math Unit

The TMU extends the capabilities of a C28x+FPU64 by adding instructions and leveraging existing FPU64
instructions to speed up the execution of common trigonometric and arithmetic operations listed in
Table 4-1.

Table 4-1. TMU Supported Instructions

INSTRUCTIONS C EQUIVALENT OPERATION PIPELINE CYCLES
MPY2PIF32/64 RaH,RbH a = b * 2pi 2/3
DIV2PIF32/64 RaH,RbH a = b / 2pi 2/3
DIVF32/64 RaH,RbH,RcH a = b/c 5
SQRTF32/64 RaH,RbH a = sqrt(b) 5
SINPUF32/64 RaH,RbH a = sin(b*2pi) 4
COSPUF32/64 RaH,RbH a = cos(b*2pi) 4
ATANPUF32/64 RaH,RbH a = atan(b)/2pi 4
QUADF32/64 RaH,RbH,RcH,RdH Operation to assist in calculating ATANPU2 5

No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU
instructions use the existing FPU register set (R0H to R7H) to carry out their operations.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

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www.ti.com VCRC Unit

4.5 VCRC Unit

Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity
over large data blocks, communication packets, or code sections. The C28x+VCRC can perform 8-bit, 16-
bit, 24-bit, and 32-bit CRCs. For example, the VCU can compute the CRC for a block length of 10 bytes in
10 cycles. A CRC result register contains the current CRC, which is updated whenever a CRC instruction
is executed.
The following are the CRC polynomials used by the CRC calculation logic of VCRC:
• CRC8 polynomial = 0x07
• CRC16 polynomial1 = 0x8005
• CRC16 polynomial2 = 0x1021
• CRC24 polynomial = 0x5d6dcb
• CRC32 polynomial1 = 0x04c11db7
• CRC32 polynomial2 = 0x1edc6f41
This module can calculate CRCs for a byte of data in a single cycle. The CRC calculation for CRC8,
CRC16, CRC24 and CRC32 is done byte-wise (instead of computing on a complete 16-bit or 32-bit data
read by the C28x core) to match the byte-wise computation requirement mandated by various standards.
The VCRC Unit also allows the user to provide the size (1b-32b) and value of any polynomial to fit custom
CRC requirements. The CRC execution time increases to three cycles when using a custom polynomial.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

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 Chapter 5
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ROM Code and Peripheral Booting

This chapter describes the boot flow and functionality of the F2838x CPU1, CPU2, and Connectivity
Manager (CM) subsystems.

Topic ........................................................................................................................... Page

5.1 Introduction ..................................................................................................... 679

5.2 Device Boot Sequence ...................................................................................... 679
5.3 Device Boot Modes ........................................................................................... 681
5.4 Device Boot Configurations ............................................................................... 682
5.5 Device Boot Flow Diagrams ............................................................................... 687
5.6 Device Reset and Exception Handling ................................................................. 692
5.7 Boot ROM Description ...................................................................................... 694
5.8 Application Notes for Using the Bootloaders ....................................................... 732

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5.1 Introduction
The purpose of this chapter is to explain the boot read-only memory (ROM) code functionality for CPU1,
CPU2, and CM cores, including the boot procedure. It also discusses the functions and features of the
boot ROM code, and provides details about the ROM memory map contents. On every reset, the device
executes a boot sequence in the ROM depending on the reset type and boot configuration. This sequence
will initialize the device to run the application code. For CPU1, the boot ROM also contains peripheral
bootloaders which can be used to load an application into RAM. These bootloaders can be disabled for
safety or security purposes.
Refer to Table 5-1 for details on available boot features across CPU1, CPU2, and CM. Additionally,
Table 5-2 shows the sizes of the various ROMs on the device.

Table 5-1. Boot System Overview

Boot Feature CPU1 (Master) CPU2 CM
Initiate boot process Device Reset CPU1 Application CPU1 Application
Boot mode selection GPIOs IPC Register IPC Register
Supported boot modes:
• Flash boot
Yes Yes Yes
• Secure Flash boot
• RAM boot
Boot to User OTP No Yes Yes
Copy from IPC Message RAM and
No Yes Yes
boot to RAM
Peripheral boot loader support Yes No No

Table 5-2. ROM Memory

ROM CPU1 Size CPU2 Size CM Size
Unsecure boot ROM 192 KB 64 KB 64 KB
Secure ROM 64 KB 64 KB 32 KB
CLA data ROM 8 KB 8 KB N/A

5.2 Device Boot Sequence

The boot sequence describes the general boot ROM procedure each time a CPU core is reset. CPU1 is
the master and always boots first. Once CPU1 boots to the application, then the user's application code in
CPU1 can configure CPU2/CM boot IPC registers and release CPU2/CM from reset to boot. Table 5-3,
Table 5-4, and Table 5-5 detail the general overview of the boot-up procedures for each core.
During boot, each CPU's boot ROM code updates a boot status location in RAM that details the actions
taken during this process. Additionally, CPU2 writes the boot status to the CPU2TOCPU1IPCBOOTSTS
register and CM writes to CMTOCPU1IPCBOOTSTS to communicate the statuses to CPU1.
Refer to Section 5.7.11 for more details.

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Table 5-3. CPU1 Boot ROM Sequence

Step CPU1 Action
After reset, check for HWBIST reset. If it is a HWBIST reset, immediately branch and return to the user
1 application. If it is not a HWBIST reset, then continue boot and check the FUSE error register for any errors
and handle accordingly.
2 Clock configuration and flash power-up
3 Peripheral trimming and device configuration registers are loaded from OTP.
4 On power-on reset (POR), all CPU1 RAMs are initialized.
5 Non-maskable interrupt (NMI) handling is enabled and DCSM initialization is performed.
6 Device calibration is performed; trimming the specified peripherals with set OTP values.
7 Determine if polling the GPIO pins are needed for determining the boot mode and, if so, read the boot mode
GPIO pins to determine the boot mode to run.
Based on the boot mode and options, the appropriate boot sequence is executed. Refer to Section 5.5.1 for
8
a flow chart of the CPU1 boot sequences.

Table 5-4. CPU2 Boot ROM Sequence

Step CPU2 Action
1 CPU2 is released from reset by CPU1 application.
Once CPU1TOCPU2IPCFLG0 is set, read the CPU1TOCPU2IPCBOOTMODE register. If it is not set
2 correctly or has an invalid value, the IPC error command is sent to CPU1 and the CPU2 core will enter an
infinite loop and will not continue booting until the user corrects the register values and reset the CPU2.
3 Flash power-up
4 On POR, all CPU2 RAMs are initialized.
5 NMI handling is enabled.
Based on the boot mode set in CPU1TOCPU2IPCBOOTMODE register, CPU2 either enters "wait for
6 command" mode to wait for a future CPU1 boot mode command or CPU2 executes the requested boot
sequence. Refer to Section 5.5.2 for a flow chart of the CPU2 boot sequences.

Table 5-5. CM Boot ROM Sequence

Step CM Action
1 CM is released from reset by the CPU1 application.
Once CPU1TOCMIPCFLG0 is set, read the CPU1TOCMIPCBOOTMODE register.If it is not set correctly or
2 has an invalid value, the IPC error command is sent to CPU1 and the CM will enter an infinite loop and will
not continue booting until the user corrects the register values and reset the CM.
3 Flash power-up
4 On POR, all CM RAMs are initialized.
5 NMI handling is enabled.
Based on the boot mode set in CPU1TOCPU2IPCBOOTMODE register, CM either enters "wait for
6 command" mode to wait for a future CPU1 boot mode command or CM executes the requested boot
sequence. Refer to Section 5.5.3 for a flow chart of the CM boot sequences.

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5.3 Device Boot Modes

This section explains the default boot modes, as well as all the available boot modes supported on this
device. The CPU1 boot ROM uses the boot mode select, general purpose input/output (GPIO) pins to
determine the boot mode configuration. CPU2 boot ROM uses the CPU1TOCPU2IPCBOOTMODE
register to determine the boot mode configuration and CM boot ROM uses the
CPU1TOCMIPCBOOTMODE register to determine the boot mode configuration.
Table 5-6 shows the CPU1 boot mode options available for selection by the default boot mode select pins.
Users have the option to program the device to customize the boot modes selectable in the boot-up table
as well as the boot mode select pin GPIOs used.
All the available boot modes on the device are described in Table 5-8.

Table 5-6. Device Default Boot Modes for CPU1

GPIO72 GPIO84
Boot Mode
(Default boot mode select pin 1) (Default boot mode select pin 0)
Parallel IO 0 0
SCI / Wait Boot (1) 0 1
CAN 1 0
Flash / USB (2) 1 1
(1)
SCI boot mode can be used as a wait boot mode as long as SCI continues to wait for an 'A' or 'a' during the SCI autobaud lock
process.
(2)
On an unprogrammed device, selecting flash boot when the default flash entry address is unprogrammed will switch the boot
mode from flash boot to USB boot. See Table 5-7 for more details.

Table 5-7. CPU1 Flash-to-USB Boot Decision Table

Value at Flash Entry Point Address Reason for Value Realized Boot Mode
0x00000000 Flash is locked/secured Boot to Flash
0xFFFFFFFF Flash is not programmed USB Boot
Any other value Flash is programmed Boot to Flash

NOTE: The switch of flash boot mode to USB boot mode when flash is not programmed is only
available as part of the default boot mode table on an unprogrammed device. Once a
custom boot table is programmed in OTP or RAM, a selection of flash boot mode will not
switch to USB boot even when flash is unprogrammed.

Table 5-8. All Available Boot Modes

Boot Mode CPU Support Details
Parallel IO CPU1
SCI / Wait CPU1
CAN CPU1
Flash CPU1, CPU2, CM
Wait CPU1, CPU2, CM Refer to Section 5.7.7 for functional details of the boot modes.
RAM CPU1, CPU2, CM
Refer to Section 5.7.8 for boot table values and GPIOs for the
SPI CPU1
boot modes.
I2C CPU1
USB CPU1
Secure Flash CPU1, CPU2, CM
User OTP CPU2, CM
IPC Message Copy to RAM CPU2, CM

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NOTE: All the peripheral boot modes that are supported use the first instance of the peripheral
module (SCIA, SPIA, I2CA, CANA, and so forth). Whenever these boot modes are referred
to in this chapter, such as SCI boot, it is actually referring to the first module instance, which
means the SCI boot on the SCIA port. The same applies to the other peripheral boots.

5.4 Device Boot Configurations

This section details what boot configurations are available and how to configure them. This device
supports from 0 boot mode select pins up to 3 boot mode select pins as well as from 1 configured boot
mode up to 8 configured boot modes.
To change and configure the device from the default settings to custom settings for your application, use
the following process:
1. Determine all the various ways you want application to be able to boot. (For example: Primary boot
option of Flash boot for your main application, secondary boot option of CAN boot for firmware
updates, tertiary boot option of SCI boot for debugging, etc)
2. Based on the number of boot modes needed, determine how many boot mode select pins (BMSPs)
are required to select between your selected boot modes. (For example: 2 BMSPs are required to
select between 3 boot mode options)
3. Assign the required BMSPs to a physical GPIO pin. (For example, BMSP0 to GPIO50, BMSP1 to
GPIO51, and BMSP2 left as default which is disabled). Refer to Section 5.4.1 for all the details on
performing these configurations.
4. Assign the determined boot mode definitions to indexes in your custom boot table that correlate to the
decoded value of the BMSPs. For example, BOOTDEF0=Boot to Flash, BOOTDEF1=CAN Boot,
BOOTDEF2=SCI Boot; all other BOOTDEFx are left as default/nothing). Refer to Section 5.4.2 for all
the details on setting up and configuring the custom boot mode table.
Additionally, Section 5.4.3 provides some example use cases on how to configure the BMSPs and custom
boot tables.

5.4.1 Configuring Boot Mode Pins for CPU1

This section explains how the boot mode select pins can be customized by the user, by programming the
BOOTPINCONFIG location (refer to Table 5-9) in the user-configurable dual-zone security module
(DCSM) OTP. The location in the DCSM OTP is Z1-BOOTPINCONFIG or Z2-BOOTPINCONFIG. When
debugging, EMUBOOTPINCONFIG is the emulation equivalent of Z1-BOOTPINCONFIG/Z2-
BOOTPINCONFIG, and can be programmed to experiment with different boot modes without writing to
OTP. The device can be programmed to use 0, 1, 2, or 3 boot mode select pins as needed.

NOTE: When using Z2-BOOTPINCONFIG, the configurations programmed in this location will take
priority over the configurations in Z1-BOOTPINCONFIG. It is recommended to use Z1-
BOOTPINCONFIG first and then if OTP configurations need to be altered, switch to using
Z2-BOOTPINCONFIG.

Table 5-9. CPU1 BOOTPINCONFIG Bit Fields

Bit Name Description
Write 0x5A to these 8-bits to tell the boot ROM code that the bits in this
register are valid
31:24 Key
For EMUBOOTPINCONFIG only, write 0xA5 to emulate the standalone
boot flow and use the BMSPs/OTP BOOTDEF table
23:16 Boot Mode Select Pin 2 (BMSP2) Refer to BMSP0 description except for BMSP2
15:8 Boot Mode Select Pin 1 (BMSP1) Refer to BMSP0 description except for BMSP1

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Table 5-9. CPU1 BOOTPINCONFIG Bit Fields (continued)

Bit Name Description
Set to the GPIO pin to be used during boot (up to 255).
7:0 Boot Mode Select Pin 0 (BMSP0) 0x0 = GPIO0; 0x01 = GPIO1 and so on
Writing 0xFF disables BMSP0 and this pin is no longer used to select the
boot mode.

NOTE: The following GPIOs cannot be used as a BMSP. If selected for a particular BMSP, the boot
ROM automatically selects the factory default GPIO (the factory default for BMSP2 is 0xFF,
which disables the BMSP).
• GPIO 42 and GPIO 43
• GPIO 169 to 255

Table 5-10. CPU1 Standalone Boot Mode Select Pin Decoding

BOOTPIN_CONFIG
BMSP0 BMSP1 BMSP2 Realized Boot Mode
Key
Boot as defined by the factory default
!= 0x5A Don’t Care Don’t Care Don’t Care
BMSPs
Boot as defined in the boot table for
0xFF 0xFF 0xFF boot mode 0
(All BMSPs disabled)
Boot as defined by the value of BMSP0
Valid GPIO 0xFF 0xFF
(BMSP1 and BMSP2 disabled)
Boot as defined by the value of BMSP1
0xFF Valid GPIO 0xFF
(BMSP0 and BMSP2 disabled)
Boot as defined by the value of BMSP2
0xFF 0xFF Valid GPIO
(BMSP0 and BMSP1 disabled)
Boot as defined by the values of
Valid GPIO Valid GPIO 0xFF BMSP0 and BMSP1
(BMSP2 disabled)
Boot as defined by the values of
Valid GPIO 0xFF Valid GPIO BMSP0 and BMSP2
(BMSP1 disabled)
= 0x5A Boot as defined by the values of
0xFF Valid GPIO Valid GPIO BMSP1 and BMSP2
(BMSP0 disabled)
Boot as defined by the values of
Valid GPIO Valid GPIO Valid GPIO
BMSP0, BMSP1, and BMSP2
BMSP0 is reset to the factory default
BMSP0 GPIO
Invalid GPIO Valid GPIO Valid GPIO
Boot as defined by the values of
BMSP0, BMSP1, and BMSP2
BMSP1 is reset to the factory default
BMSP1 GPIO
Valid GPIO Invalid GPIO Valid GPIO
Boot as defined by the values of
BMSP0, BMSP1, and BMSP2
BMSP2 is reset to the factory default
state, which is disabled
Valid GPIO Valid GPIO Invalid GPIO
Boot as defined by the values of
BMSP0 and BMSP1

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NOTE: When decoding the boot mode, BMSP0 is the least-significant-bit and BMSP2 is the most-
significant-bit of the boot table index value. It is recommended when disabling BMSPs to
start with disabling BMSP2. For example, in an instance when only using BMSP2 (BMSP1
and BMSP0 are disabled), then only the boot table indexes of 0 and 4 will be selectable. In
the instance when using only BMSP0, then the selectable boot table indexes are 0 and 1.

5.4.2 Configuring Boot Mode Table Options for CPU1

This section explains how to configure the boot definition table, BOOTDEF, for CPU1. The 64-bit location
is located in user-configurable DCSM OTP in the Z1-BOOTDEF-LOW and Z1-BOOTDEF-HIGH locations.
When debugging, EMUBOOTDEF-LOW and EMUBOOTDEF-HIGH are the emulation equivalents of Z1-
BOOTDEF-LOW and Z1-BOOTDEF-HIGH, and can be programmed to experiment with different boot
mode options without writing to OTP. The range of customization to the boot definition table depends on
how many boot mode select pins (BMSP) are being used. For example, 0 BMSPs equals to 1 table entry,
1 BMSP equals to 2 table entries, 2 BMSPs equals to 4 table entries, and 3 BMSPs equals to 8 table
entries. Refer to Section 5.4.3 for examples on how to setup the BOOTPIN_CONFIG and BOOTDEF
values.

NOTE: The locations Z2-BOOTDEF-LOW and Z2-BOOTDEF-HIGH will be used instead of Z1-
BOOTDEF-LOW and Z1-BOOTDEF-HIGH locations when Z2-BOOTPINCONFIG is
configured. Refer to Section 5.4.1 for more details on BOOTPIN_CONFIG usage.

Table 5-11. CPU1 BOOTDEF Bit Fields

BOOTDEF
Byte Position Name Description
Name
Set the boot mode for index 0 of the boot
table.

Different boot modes and their options can

include, for example, a boot mode that
uses different GPIOs for a specific
BOOT_DEF0 7:0 BOOT_DEF0 Mode/Options bootloader or a different flash entry point
address. Any unsupported boot mode will
cause the device to either go to wait boot
or boot to flash.

Refer to Section 5.7.8 for valid BOOTDEF

values to set in the table.
BOOT_DEF1 15:8 BOOT_DEF1 Mode/Options
BOOT_DEF2 23:16 BOOT_DEF2 Mode/Options
BOOT_DEF3 31:24 BOOT_DEF3 Mode/Options
BOOT_DEF4 39:32 BOOT_DEF4 Mode/Options Refer to BOOT_DEF0 description
BOOT_DEF5 47:40 BOOT_DEF5 Mode/Options
BOOT_DEF6 55:48 BOOT_DEF6 Mode/Options
BOOT_DEF7 63:56 BOOT_DEF7 Mode/Options

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5.4.3 Boot Mode Example Use Cases

This section demonstrates some use cases for configuring the boot mode select pins and boot modes.

5.4.3.1 Zero Boot Mode Select Pins

This use case demonstrates a scenario for an application that does not use any boot mode select pins
and always has the device boot to flash.
1. Program the BOOTPIN_CONFIG location in OTP as follows:
• Set BOOTPIN_CONFIG.BMSP0 to 0xFF
• Set BOOTPIN_CONFIG.BMSP1 to 0xFF
• Set BOOTPIN_CONFIG.BMSP2 to 0xFF
• Set BOOTPIN_CONFIG.KEY to 0x5A for boot ROM to treat these register bits as valid and use the
custom boot table.
2. Program the BOOTDEF location options for the device. This essentially sets up a device-specific boot
mode table. Refer to Section 5.7.8 for valid BOOTDEF values to set in the table.
• Set BOOTDEF.BOOTDEF0 to 0x03 for booting to flash (entry address option 0). This sets flash
boot to boot table index 0.
• Refer to Section 5.7.3 for the available flash entry points.

Table 5-12. Zero Boot Pin Boot Table Result

Boot Mode Table Number Boot Mode
0 Flash Boot (0x03)

5.4.3.2 One Boot Mode Select Pin

This use case demonstrates a scenario for an application using one boot mode select pin to select
between booting to flash or using CAN boot.
1. Program the BOOTPIN_CONFIG location in OTP as follows:
• Set BOOTPIN_CONFIG.BMSP0 to a user specified GPIO, such as 0x0 for GPIO0
• Set BOOTPIN_CONFIG.BMSP1 to 0xFF
• Set BOOTPIN_CONFIG.BMSP2 to 0xFF
• Set BOOTPIN_CONFIG.KEY to 0x5A for boot ROM to treat these register bits as valid and use the
custom boot table.
2. Program the BOOTDEF location options for the device. This essentially sets up a device-specific boot
mode table. Refer to Section 5.7.8 for valid BOOTDEF values to set in the table.
• Set BOOTDEF.BOOTDEF0 to 0x02 for CAN booting. This sets CAN boot to boot table index 0.
• Set BOOTDEF.BOOTDEF1 to 0x03 for booting to flash (entry address option 0). This sets flash
boot to boot table index 1.

Table 5-13. One Boot Pin Boot Table Result

Boot Mode Table Number Boot Mode
0 CAN Boot (0x02)
1 Flash Boot (0x03)

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5.4.3.3 Three Boot Mode Select Pins

This use case demonstrates a scenario for an application using three boot mode select pins to select
between various boot modes in the custom boot table.
1. Program the BOOTPIN_CONFIG location in OTP as follows:
• Set BOOTPIN_CONFIG.BMSP0 to a user specified GPIO, such as 0x0 for GPIO0
• Set BOOTPIN_CONFIG.BMSP1 to a user specified GPIO, such as 0x1 for GPIO1
• Set BOOTPIN_CONFIG.BMSP2 to a user specified GPIO, such as 0x2 for GPIO2
• Set BOOTPIN_CONFIG.KEY to 0x5A for boot ROM to treat these register bits as valid and use the
custom boot table.
2. Program the BOOTDEF location options for the device. This essentially sets up a device-specific boot
mode table. Refer to Section 5.7.8 for valid BOOTDEF values to set in the table.
• Set BOOTDEF.BOOTDEF0 to 0x02 for CAN booting. This sets CAN boot to boot table index 0.
• Set BOOTDEF.BOOTDEF1 to 0x03 for booting to flash (entry address option 0). This sets flash
boot to boot table index 1.
• Set BOOTDEF.BOOTDEF2 to 0x24 for booting to wait boot (alternate option). This sets wait boot
to boot table index 2.
• Set BOOTDEF.BOOTDEF3 to 0x66 for SPI booting (alternate GPIO option 3). This sets SPI boot
to boot table index 3.
• Set BOOTDEF.BOOTDEF4 to 0x43 for booting to flash (entry address option 2). This sets flash
boot to boot table index 4.
• Set BOOTDEF.BOOTDEF5 to 0x09 for USB booting. This sets USB boot to boot table index 5.

Table 5-14. Three Boot Pins Boot Table Result

Boot Mode Table Number Boot Mode
0 CAN Boot (0x02)
1 Flash Boot (0x03)
2 Wait Boot - Alt (0x24)
3 SPI - Alt3 (0x66)
4 Flash Boot - Alt2 (0x43)
5 USB Boot (0x09)

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5.5 Device Boot Flow Diagrams

This section details the boot flow diagrams for CPU1, CPU2, and CM.

5.5.1 CPU1 Boot Flow

Upon reset, CPU1 follows the boot flow shown in Figure 5-1. Depending on whether a JTAG debugger is
connected to the device, CPU1 will either continue booting following the emulation boot flow or standalone
boot flow. Figure 5-2 shows the emulation boot flow when JTAG debugger is connected. Figure 5-3 shows
the standalone boot flow when no JTAG debugger is connected to the device.

Figure 5-1. CPU1 Device Boot Flow

Reset

CPU1 Boot Start

HWBIST
Branch to Application Reset Cause

All Other
Resets

Disable Watchdog

Configure Clock Divider

Any other resets POR or XRS
Reset Cause Power up Flash
Device Configuration

XRS
Clear boot ROM Stack to zero Reset Cause

POR

RAM Initialization
Enable NMI
(all CPU1 RAMS)

DCSM Initialization

POR Configure If set, Enable

Check Z2/Z1
Reset Cause SYSPLL and switch
GPREG2
to PLL

All other Not

Resets Configured
PLL Failed
To Lock PLL Locked
PLL Run Memory Power On Self-Test

Disable SYSPLL and RAM Initialization

Enable pull ups on unbonded IOs
switch to INTOSC (all CPU1 RAMs)

Device
Calibration

Clear POR/XRS reset

causes

No Yes
Is Debugger
Standalone Boot Emulation Boot
Connected?

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Figure 5-2. CPU1 Emulation Boot Flow

Emulation Boot Mode Start

Read EMU boot locations:

EMUBOOTPINCONFIG
EMUBOOTDEF

Unsupported
(=0xA5) Check Key
Emulate Wait
EMU_BOOTPIN_
Standalone Boot Boot
CONFIG_KEY

(=0x5A)

Get EMU Configurable user boot

mode options

Use BOOTPINCONFIG to determine

boot mode select GPIOs and read
those pins

Supported Unsupported
Boot Mode Decode Boot Mode
BOOTDEF options for Wait Boot
boot mode

Is Yes Run Failed

Secure Flash secure flash Halt Debugger
Boot? calculation

No

Start the peripheral loader process or

set memory address to branch Passed

Enable
Watchdog

Branch to Application
Code

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Figure 5-3. CPU1 Standalone Boot Flow

Standalone Boot Mode Start

Read OTP loaded registers:

Z2-BOOTPINCONFIG

Any Other
Check Z2 Value Read OTP loaded registers:
OTP_BOOTPIN_
Z1-BOOTPINCONFIG
CONFIG_KEY

Any Other
Check Z1 Value Read factory default two boot mode
OTP_BOOTPIN_
select GPIO pins
(=0x5A) CONFIG_KEY

(=0x5A) Decode boot mode from pins

Use Z2 registers: Use Z1 registers:

Z2-BOOTPINCONFIG Z1-BOOTPINCONFIG
Z2-BOOTDEF Z1-BOOTDEF

Yes
Is flash boot?

Use BOOTPINCONFIG to determine

boot mode select GPIOs and read
those pins Is flash entry No
Yes
address
programmed?

No
Unsupported Boot
Mode Decode
BOOTDEF table
for boot mode Set boot mode to USB boot

Start the peripheral loader process or

Flash Boot set address to branch
Supported Boot
Mode

Enable
Watchdog

No Is Yes Run Failed Enable Watchdog

Secure Flash secure flash
and reset Branch to Application
Boot? calculation
Code

Start the peripheral loader process or Passed

set address to branch

Enable
Watchdog

Branch to Application
Code

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5.5.2 CPU2 Boot Flow

Upon reset, CPU2 follows the boot flow shown in Figure 5-4. CPU2 only boots once configured and
released from reset by CPU1. Refer to Section 5.7.2 for more details.

Figure 5-4. CPU2 Boot Flow

XRS

POR CPU1 SYSRSn

Security (SCC)

CPU2
HWBIST Held in Reset
Reset
Software Release Request
Application Releases from CPU1
CPU2 from Reset
Debugger
CPU2 Boot Start
Reset

All other
Brand to HWBIST resets
Reset Cause
Application

Disable Watchdog

Wait for CPU1 to set IPCFLG0

Send IPC command No Is register Read

to CPU1 and wait. configured CPU1TOCPU2IPCBOOTMODE
(CPU1 must reset CPU2) correctly? Register

Yes

POR or
XRS
Reset Cause Flash Power Up

All other resets

XRS
Clear boot ROM Stack to zero Reset Cause

POR

RAM Initialization
Clear POR reset cause Enable NMI
(CPU2 RAMs)

CPU1 set IPCFLG0

Wait mode Wait in loop

Read boot mode
for IPC Flag

Other boot
Failed
mode Send IPC notification to CPU1

Is Yes Run Passed

Secure Flash secure flash
Boot? calculation

No

Is Yes No
Copy length
IPC RAM Copy
Is valid?
Boot?

No Yes

Run specified boot mode

Enable Watchdog Branch to Application

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5.5.3 Connectivity Manager (CM) Boot Flow

Upon reset, CM follows the boot flow shown in Figure 5-5. CM only boots once configured and released
from reset by CPU1. Refer to Section 5.7.2 for more details.

Figure 5-5. CM Boot Flow

SCC Reset

POR CPU1 SYSRSn

VECTRESET
Reset

CM
CM NMI Watchdog Held in Reset
Reset (XRS)
Software Release Request
Application Releases from CPU1
CM from Reset
CM Software Reset
CM Boot Start
(SYSRESETREQ)

Disable Watchdog

Wait for CPU1 to set IPCFLG0

Read
CPU1TOCMIPCBOOTMODE
Register

Send IPC command No Is register

to CPU1 and wait. configured
(CPU1 must reset CM) correctly?

Yes

All other
resets
Reset Cause Flash Power Up

VECTRESET
All other
resets
Clear boot ROM Stack to zero Reset Cause

POR

RAM Initialization
Clear POR reset cause Enable NMI
(all CM RAMS)

CPU1 set IPCFLG0

Wait mode Wait in loop

Read boot mode
for IPC Flag

Other boot
Failed
mode Send IPC notification to CPU1

Is Yes Run Passed

Secure Flash secure flash
Boot? calculation

No

Is Yes No
Copy length
IPC RAM Copy
Is valid?
Boot?

No Yes

Run specified boot mode

Enable Watchdog Branch to Application

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5.6 Device Reset and Exception Handling

5.6.1 Reset Causes and Handling

Table 5-15 explains the actions each boot ROM performs upon reset for a specific reset cause.

Table 5-15. Boot ROM Reset Causes and Actions

Reset Source CPU1 Boot ROM Action CPU2 Boot ROM Action CM Boot ROM Action
1. Configure Clock Divider
2. Flash Power Up 1. Flash Power Up 1. Flash Power Up
3. Device configuration and 2. RAM Initialization 2. RAM Initialization
Power on Reset (POR)
trimming
4. RAM Initialization 3. Continue default boot flow 3. Continue default boot flow
5. Continue default boot flow
External Reset (XRS) 1. Configure Clock Divider
For CPU1, XRS triggers
2. Flash Power Up 1. Flash Power Up 1. Flash Power Up
include:
• Watchdog Reset 3. Device configuration and 2. Clear RAM for boot stack 2. Clear RAM for boot stack
trimming
• NMI Watchdog Reset
• EtherCAT Reset 4. Clear RAM for boot stack 3. Continue default boot flow 3. Continue default boot flow
• SIMRESET XRS 5. Continue default boot flow
1. Read HWBIST return 1. Read HWBIST return
address address
Hardware Built-In Self Test 2. If set, branch to address 2. If set, branch to address Not Applicable
(HWBIST)
3. If not set, continue boot 3. If not set, continue boot
following "Debugger Reset" following "Debugger Reset"
boot flow actions boot flow actions
Secure Copy Code (SCC) 1. Clear RAM for boot stack 1. Clear RAM for boot stack 1. Flash Power Up
Reset (CPU1, CPU2)
2. Continue default boot flow 2. Continue default boot flow 2. Clear RAM for boot stack
Watchdog Reset (CPU2)
NMI Watchdog Reset (CPU2) 3. Continue default boot flow
Execute Override Logic (EOL)
Reset (CM)
1. Clear RAM for boot stack
SIMRESET_CPU1 Not Applicable Not Applicable
2. Continue default boot flow
Debugger Reset (CPU1, 1. Clear RAM for boot stack 1. Clear RAM for boot stack 1. Clear RAM for boot stack
CPU2)
2. Continue default boot flow 2. Continue default boot flow 2. Continue default boot flow
VECTRESET (CM)

5.6.2 Exceptions and Interrupts Handling

Table 5-16 explains the actions each boot ROM performs if any exceptions that can occur happen during
boot. The exception handling philosophy for CPU1, in most cases, is to log the error and continue booting
to reach the application. The exception handling philosophy for CPU2 and CM is to log the error, notify
CPU1, and let CPU1 handle the action.
For any CPU2 NMI event sources, CPU2 NMI handler will clear the NMI flag to stop the NMI watchdog
counter and prevent CPU2 from resetting. The error pin will go low or high (depending on the polarity
configuration on the error pin and the reset type) temporarily before the NMI flag is cleared. Therefore, a
shorter pulse width of the error pin signal means CPU2 (or CM) is the source of the error. Following this,
CPU2 sends an error IPC message to CPU1 in order for CPU1 to handle the error and reset CPU2.
For any CM NMI event sources, the CM NMI handler will clear the NMI flag to stop the NMI watchdog
counter and prevent CM from resetting. The error pin will go low or high (depending on the polarity
configuration on the error pin and the reset type) temporarily before the NMI flag is cleared. Therefore, a
shorter pulse width of the error pin signal means CM (or CPU2) is the source of the error. Following this,
the CM sends an error IPC message to CPU1 in order for CPU1 to handle the error and reset CM.

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Table 5-16. Boot ROM Exceptions and Actions

Exception Event Source CPU1 Boot ROM Action CPU2 Boot ROM Action CM Boot ROM Action Event Logged
Single-bit error in Ignore and continue to boot No action No action No
FUSEERR
Multi-bit error in FUSEERR Reset the device No action No action No
Clock Fail Clear the NMI flag and Clear NMI flag, update boot Clear NMI flag, update boot Yes
continue to boot status to CPU1, send error status to CPU1, send error
IPC to CPU1, and wait in IPC to CPU1, and wait in
loop loop
RAM Uncorrectable Error Perform RAM initialization Clear NMI flag, update boot Clear NMI flag, update boot Yes (1)
ROM Parity Error and reset the device status to CPU1, send error status to CPU1, send error
IPC to CPU1, and wait in IPC to CPU1, and wait in
loop loop
Flash Uncorrectable Error Reset the device Clear NMI flag, update boot Clear NMI flag, update boot Yes
status to CPU1, send error status to CPU1, send error
IPC to CPU1, and wait in IPC to CPU1, and wait in
loop loop
HWBIST Error Clear the NMI flag and Clear NMI flag, update boot No action Yes
continue to boot status to CPU1, send error
IPC to CPU1, and wait in
loop
PIE Vector Mismatch (2) Fetch error handler Fetch error handler No action Yes
address, if address is address, if address is
configured, call handler, configured, call handler,
else reset the device else clear NMI flag, update
boot status to CPU1, send
error IPC to CPU1, and
wait in loop
Embedded Real-time Clear the NMI flag and Clear NMI flag, update boot No action Yes
Analysis and Diagnostic continue to boot status to CPU1, send error
(ERAD) NMI IPC to CPU1, and wait in
loop
MCAN Uncorrectable Error Clear the NMI flag and No action Clear NMI flag, update boot Yes
continue to boot status to CPU1, send error
IPC to CPU1, and wait in
loop
EtherCAT NMI Clear the NMI flag and No action Clear NMI flag, update boot Yes
continue to boot status to CPU1, send error
IPC to CPU1, and wait in
loop
ITRAP Exception Record memory address of Send IPC to CPU1 with No action Yes
where the illegal instruction memory address of the
was executed and let illegal instruction and wait
device reset in loop
Invalid IPCBOOTMODE No action Send IPC to CPU1 and wait Send IPC to CPU1 and wait Yes
Value upon Reset in loop in loop
Secure Flash Boot Failure Enable watchdog and let Send IPC to CPU1 and Send IPC to CPU1 and Yes
device reset return to wait boot mode return to wait boot mode
Hard Fault Exception No action No action Update boot status to Yes
CPU1, send error IPC to
CPU1, and wait in loop
Any Unsupported Interrupt Ignore and continue to boot Ignore and continue to boot Update boot status to Yes (CM Only)
CPU1, send error IPC to
CPU1 with the interrupt
exception number, and wait
in loop
(1)
For CPU1, a RAM uncorrectable error or ROM parity error will clear the boot status information stored in RAM because a RAM
initialization is performed to attempt to correct the error. Since the boot status information is erased, this exception can be identified in
that a NMIWD reset occurred and all the RAMs are erased.
(2)
A PIE vector mismatch in one core (such as CPU1 or CPU2) will trigger the PIE vector mismatch interrupt in other cores.

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5.7 Boot ROM Description

This section explains the details regarding the device boot ROMs.

5.7.1 CPU1 Boot ROM Configuration Registers

CPU1 boot ROM code involves several memory addresses and registers used during execution. There
are two sets of configurations; one for emulation and one for standalone boot flow. The emulation
locations located in RAM emulate the OTP configurations and can be written to as many times as needed.
The user configurable DCSM OTP locations used in the standalone boot flow program the device OTP
and hence can only be written once. For bit field configuration details for BOOTPIN-CONFIG and
BOOTDEF, see Section 5.4.1 and Section 5.4.2.
Additionally, the CPU1 boot ROM supports boot configurations from DCSM zone 1 and zone 2 registers.
Zone 2 configurations will supercede zone 1 configurations, so it is recommended to use zone 1
configurations and use zone 2 as a secondary option.

NOTE: All boot configurations for CPU2 and CM are set through CPU1TOCPU2IPCBOOTMODE
and CPU1TOCMIPCBOOTMODE registers. See more details in Section 5.7.2.

Table 5-17. CPU1 Boot ROM Registers

Boot Flow Register Name Boot ROM Name Register Address User OTP Address
- EMUBOOTPINCONFIG 0x0000 0D00 -
Emulation - EMUBOOTDEF-LOW 0x0000 0D04 -
- EMUBOOTDEF-HIGH 0x0000 0D06 -
Z1-GPREG1 Z1-BOOTPINCONFIG 0x0005 F008 0x0007 8008
Standalone Z1-GPREG2 Z1-BOOT-GPREG2 0x0005 F00A 0x0007 800A
(Using Z1) Z1-GPREG3 Z1-BOOTDEF-LOW 0x0005 F00C 0x0007 800C
Z1-GPREG4 Z1-BOOTDEF-HIGH 0x0005 F00E 0x0007 800E
Z2-GPREG1 Z2-BOOTPINCONFIG 0x0005 F088 0x0007 8208
Standalone Z2-GPREG2 Z2-BOOT-GPREG2 0x0005 F08A 0x0007 820A
(Using Z2) Z2-GPREG3 Z2-BOOTDEF-LOW 0x0005 F08C 0x0007 820C
Z2-GPREG4 Z2-BOOTDEF-HIGH 0x0005 F08E 0x0007 820E

5.7.1.1 GPREG2 Usage and MPOST Configuration

Table 5-18 explains how the bit field values from the user configurable DCSM OTP location, Z1-BOOT-
GPREG2 or Z2-BOOT-GPREG2, are decoded by CPU1 boot ROM.

Table 5-18. CPU1 DCSM Z1/Z2 GPREG2 Bit Fields

Bit Name Description Boot ROM Action
Write 0x5A to these 8-bits to
tell the boot ROM code that If user set to 0x5A, boot ROM will use the values in this register. If set
31:24 Key
the bits in this register are to any other value, boot ROM will ignore values in this register.
valid
23:8 Reserved Reserved No Action
0x0 = MPOST will be run with PLL enabled for high speed (110MHz).
When configured to a valid
0xC = MPOST will be run with PLL enabled for medium speed (80MHz).
Run value, MPOST (Memory
7:4 0x3 = MPOST will be run with PLL enabled for low speed (60MHz).
MPOST (1) Power on Self-Test) will be
0x9 = MPOST will be run using INTOSC2 with PLL disabled (10MHz).
run on all device memories
Any other value = MPOST will not be run.
3:0 Reserved Reserved No Action
(1)
If MPOST is configured to run with PLL enabled and the PLL fails to lock, then the MPOST run will be skipped altogether. This
doesn't apply if MPOST is configured to use INTOSC2 with PLL disabled.

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5.7.2 Booting CPU2 and CM

This section details the boot up flow for CPU2 and CM. This includes the process, how to configure
IPCBOOTMODE, and the error IPC commands that CPU2/CM report to CPU1.

5.7.2.1 Boot Up Procedure

The boot configurations for CPU2 and CM are set by the CPU1 application. The CPU1 application
configures the clocks for CPU2/CM, sets the boot mode and other parameters in the IPCBOOTMODE
register, and releases CPU2/CM from reset to boot.
CPU2 and CM have two states where CPU1 can configure their boot mode. The first state occurs before
CPU2/CM boot and when they are still in reset. The second state occurs after CPU2/CM have been
released from reset to wait boot mode where the cores wait for an IPC flag to be set by CPU1 to indicate
that a boot mode has been set in the IPCBOOTMODE register. The procedures that CPU1 must follow
are detailed in Table 5-19 and Table 5-20.

NOTE: Regardless of reset source, CPU2 and CM each require their respective IPCFLG0 to be set
by CPU1 on every reset in order to confirm the contents of IPCBOOTMODE are valid and
continue their boot process.

Table 5-19. CPU2 Boot Procedure

CPU2 State CPU1 Application Actions
1. Configures CPU2 clocks
2. Configures the CPU1TOCPU2IPCBOOTMODE register
Held in Reset (Refer to Section 5.7.2.2 for configuration details)
3. Sets CPU1TOCPU2IPCFLG0 (1)
4. Releases CPU2 from being held in reset
1. Configures the CPU1TOCPU2IPCBOOTMODE register
In Wait Boot Mode waiting for the IPC Flag (Refer to Section 5.7.2.2 for configuration details)
2. Sets CPU1TOCPU2IPCFLG0 (1)
(1)
CPU2 will ACK and clear this IPC flag during boot up.

Table 5-20. CM Boot Procedure

CM State CPU1 Application Actions
1. Configures CM clocks
2. Configures the CPU1TOCMIPCBOOTMODE register
Held in Reset (Refer to Section 5.7.2.2 for configuration details)
3. Sets CPU1TOCMIPCFLG0 (1)
4. Releases CM from being held in reset
1. Configures the CPU1TOCMIPCBOOTMODE register
In Wait Boot Mode waiting for IPC Flag (Refer to Section 5.7.2.2 for configuration details)
2. Sets CPU1TOCMIPCFLG0 (1)
(1)
CM will ACK and clear this IPC flag during boot up.

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5.7.2.2 IPCBOOTMODE Details

This section details the CPU1TOCPU2IPCBOOTMODE and CPU1TOCMIPCBOOTMODE register bit-field
configurations and requirements for booting CPU2/CM.

NOTE: If any of the bit-fields of CPU1TOCPU2IPCBOOTMODE or CPU1TOCMIPCBOOTMODE

registers are set with invalid values, an error IPC command is sent to CPU1. CPU2/CM then
enter a wait loop where CPU2/CM wait for CPU1 to re-configure the IPCBOOTMODE
register correctly and issue a reset to the respective core.

Table 5-21. CPU1TOCPU2IPCBOOTMODE Register Details

Bit Name Valid Values Description
Key must be set for this register
31:24 Key 0x5A
to be considered valid.
23:20 Reserved - Reserved
Sets the data length (in words)
for the "Copy from IPC Message
0x0 = 0 words (Boot mode not used) RAM and Boot to M1RAM" boot
0x1 = 100 words mode. This is the number words
IPC Message RAM 0x2 = 200 words to be copied from
19:16
Copy Length ... CPU1TOCPU2MSGRAM1 to
0x9 = 900 words CPU2 M1RAM.
0xA = 1000 words (1)
If not using this boot mode, set
value to 0x0.
0xA = 10MHz (2)
Sets the clock frequency (in
0xB = 11MHz
15:8 CPU2 Device Frequency MHz) that CPU2 is configured
...
at.
0xC8 = 200MHz (2)
0x0 = None/Wait Boot
0x03 = Flash Boot Option 0 (Sector 0)
0x23 = Flash Boot Option 1 (Sector 4)
0x43 = Flash Boot Option 2 (Sector 8)
0x63 = Flash Boot Option 3 (Sector 13)
0x0A = Secure Flash Boot Option 0 (Sector 0)
7:0 CPU2 Boot Mode Sets the boot mode for CPU2
0x2A = Secure Flash Boot Option 1 (Sector 4)
0x4A = Secure Flash Boot Option 2 (Sector 8)
0x6A = Secure Flash Boot Option 3 (Sector 13)
0x0C = IPC Message RAM copy and boot to M1RAM
0x05 = Boot to M0RAM
0x0B = Boot to User OTP
(1)
Values greater than 0xA are invalid.
(2)
Values less than 0xA (10MHz) or greater than 0xC8 (200MHz) are invalid.

Table 5-22. CPU1TOCMIPCBOOTMODE Register Details

Bit Name Valid Values Description
Key must be set for this register
31:24 Key 0x5A
to be considered valid.
23:20 Reserved - Reserved
Sets the data length (in words)
for the "Copy from IPC Message
0x0 = 0 words / 0 bytes (Boot mode not used) RAM and Boot to S0RAM" boot
0x1 = 100 words / 200 bytes mode. This is the number words
IPC Message RAM 0x2 = 200 words / 400 bytes to be copied from
19:16
Copy Length ... CPU1TOCMMSGRAM1 to CM
0x9 = 900 words / 1800 bytes S0RAM.
0xA = 1000 words / 2000 bytes (1)
If not using this boot mode, set
value to 0x0.

(1)
Values greater than 0xA are invalid.

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Table 5-22. CPU1TOCMIPCBOOTMODE Register Details (continued)

Bit Name Valid Values Description
0xA = 10MHz (2)
0xB = 11MHz Sets the clock frequency (in
15:8 CM Device Frequency
... MHz) that CM is configured at.
0x7D = 125MHz (2)
0x0 = None/Wait Boot
0x03 = Flash Boot Option 0 (Sector 0)
0x23 = Flash Boot Option 1 (Sector 4)
0x43 = Flash Boot Option 2 (Sector 8)
0x63 = Flash Boot Option 3 (Sector 13)
0x0A = Secure Flash Boot Option 0 (Sector 0)
7:0 CM Boot Mode Sets the boot mode for CM
0x2A = Secure Flash Boot Option 1 (Sector 4)
0x4A = Secure Flash Boot Option 2 (Sector 8)
0x6A = Secure Flash Boot Option 3 (Sector 13)
0x0C = IPC Message RAM copy and boot to S0RAM
0x05 = Boot to S0RAM
0x0B = Boot to User OTP
(2)
Values less than 0xA (10MHz) or greater than 0x7D (125MHz) are invalid.

5.7.2.3 Error IPC Command Table

This section details the IPC commands that CPU2 or CM can send to CPU1 to notify CPU1 regarding an
error that occurred.

NOTE: After CPU2 or CM sends the error IPC command to CPU1, CPU2/CM will set
CPU2TOCPU1IPCFLG0/CMTOCPU1IPCFLG0.

Table 5-23. CPU2 to CPU1 Error IPC Commands

Description IPCSENDCOM Value IPCSENDADDR Value
No Command 0x0000 0000 Not Used
IPCBOOTMODE Value(s)
0xFFFF FFFF Not Used
Incorrect
If RAM is accessible, the address for the source of the ITRAP
CPU2 in ITRAP 0xFFFF FFFE
will be provided
CPU2 got NMI 0xFFFF FFFA Not Used
CPU2 Secure Flash CMAC
0xFFFF FFF9 Not Used
Calculation Failed

Table 5-24. CM to CPU1 Error IPC Commands

Description IPCSENDCOM Value IPCSENDADDR Value
No Command 0x0000 0000 Not Used
IPCBOOTMODE Value(s)
0xFFFF FFFF Not Used
Incorrect
CM got Hard Fault Exception 0xFFFF FFFE Not Used
CM got Unsupported Interrupt 0xFFFF FFFB Active Exception Number
CM got NMI 0xFFFF FFFA Not Used
CM Secure Flash CMAC
0xFFFF FFF9 Not Used
Calculation Failed

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5.7.3 Entry Points

This section gives details about the entry point addresses for various boot modes. These entry points
direct the boot ROM what address to branch to at the end of booting as per the selected boot mode.

Table 5-25. Entry Point Addresses for CPU1

Entry Point Details Address
Flash / Secure Flash (Option 0) Flash Sector 0 0x0008 0000
Flash / Secure Flash (Option 1) Flash Sector 4 0x0008 8000
Flash / Secure Flash (Option 2) Flash Sector 8 0x000A 8000
Flash / Secure Flash (Option 3) Flash Sector 13 0x000B E000
RAM M0RAM 0x0000 0000

Table 5-26. Entry Point Addresses for CPU2

Entry Point Details Address
Flash / Secure Flash (Option 0) Flash Sector 0 0x0008 0000
Flash / Secure Flash (Option 1) Flash Sector 4 0x0008 8000
Flash / Secure Flash (Option 2) Flash Sector 8 0x000A 8000
Flash / Secure Flash (Option 3) Flash Sector 13 0x000B E000
RAM M0RAM 0x0000 0000
CPU1 IPC Message RAM Copy to CPU2 RAM M1RAM 0x0000 0400
User OTP CPU2 User OTP 0x0007 8000

Table 5-27. Entry Point Addresses for CM

Entry Point Details Address
Flash / Secure Flash (Option 0) Flash Sector 0 0x0020 0000
Flash / Secure Flash (Option 1) Flash Sector 4 0x0021 0000
Flash / Secure Flash (Option 2) Flash Sector 8 0x0025 0000
Flash / Secure Flash (Option 3) Flash Sector 13 0x0027 C000
RAM S0RAM 0x2000 0800
CPU1 IPC Message RAM Copy to CM RAM S0RAM 0x2000 0800
User OTP CM User OTP 0x003C 0000

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5.7.4 Wait Points

During boot ROM execution, there are situations where the CPU may enter a wait loop in the code. This
state can occur for a variety of reasons. Table 5-28, Table 5-29, and Table 5-30 detail the address ranges
that the CPU PC register for each core will fall between if boot has entered one of these instances.

Table 5-28. Wait Point Addresses for CPU1

Silicon Rev0 Address Range Silicon RevA Address Range Description
0x3FB100 – 0x3FB106 0x3FB112 – 0x3FB117 In Wait Boot Mode
0x3FBEE2 – 0x3FBF09 0x3FBEEB – 0x3FBF12 In SCI Boot waiting on autobaud lock
0x3FE839 – 0x3FE92D 0x3FE839 – 0x3FE92D In NMI Handler
0x3FE7F1 – 0x3FE823 0x3FE7F1 – 0x3FE823 In PIE Vector Mismatch Handler
0x3FE944 – 0x3FE970 0x3FE944 – 0x3FE970 In ITRAP ISR
0x3FB12A – 0x3FB12E 0x3FB13C – 0x3FB142 Failed secure flash CMAC verification loop

Table 5-29. Wait Point Addresses for CPU2

Silicon Rev0,A Address Range Description
0x3FB41D – 0x3FB42B In Wait Boot Mode waiting for boot command
0x3FB459 – 0x3FB503 In NMI Handler
0x3FB504 – 0x3FB559 In ITRAP ISR
0x3FB173 – 0x3FB1B7 In loop due to invalid CPU1TOCPU2IPCBOOTMODE value(s) and/or
CPU1TOCPU2IPCFLG0 is not set

Table 5-30. Wait Point Addresses for CM

Silicon Rev0,A Address Range Description
0x180C – 0x1818 In Wait Boot Mode waiting for boot command
0x4018 – 0x41C2 In NMI Handler
0x41C4 – 0x41E8 In Hard Fault Handler
0x41EA – 0x421A In Default Interrupt Handler
0x1618 – 0x16C4 In loop due to invalid CPU1TOCMIPCBOOTMODE value(s) and/or CPU1TOCMIPCFLG0 is
not set

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5.7.5 Memory Maps

This section details the ROM memory maps.

5.7.5.1 Boot ROM Memory Maps

Table 5-31. CPU1 Boot ROM Memory Map

Memory Origin Address Length (Words)
ROM Signature 0x003E 8000 0x0002
AES Tables 0x003E 8002 0x1400
IQmath Tables 0x003E 9402 0x166D
FPU32 Fast Tables 0x003F 6946 0x081A
FPU64 Fast Tables 0x003F 7160 0x0D30
FPU32 Twiddle Tables 0x003F 7E90 0x0DF8
FPU64 Twiddle Tables 0x003F 8DD0 0x1BF0
Boot 0x003F A9C0 0x3E00
Interrupt Handlers 0x003F E7C0 0x01B1
CPU Fast Data (1) 0x003F EA22 0x0100
Boot Checksum 0x003F FE40 0x0042
Full ROM Checksum 0x003F FEC0 0x0042
CRC Table 0x003F FF32 0x0008
Version 0x003F FF7A 0x0002
Vector Table 0x003F FFBE 0x0042
(1)
Check the data manual to determine if these are available for your device part number. If not available, treat these sections as
reserved.

Table 5-32. CPU2 Boot ROM Memory Map

Memory Origin Address Length (Words)
ROM Signature 0x003E 8000 0x0002
AES Tables 0x003E 8002 0x1400
IQmath Tables 0x003E 9402 0x166D
FPU32 Fast Tables 0x003F 6946 0x081A
FPU64 Fast Tables 0x003F 7160 0x0D30
FPU32 Twiddle Tables 0x003F 7E90 0x0DF8
FPU64 Twiddle Tables 0x003F 8DD0 0x1BF0
Boot 0x003F A9C0 0x3E00
Interrupt Handlers 0x003F E7C0 0x0173
CPU Fast Data (1) 0x003F EA22 0x0100
Boot Checksum 0x003F FE40 0x0042
Full ROM Checksum 0x003F FEC0 0x0042
CRC Table 0x003F FF32 0x0008
Version 0x003F FF7A 0x0002
Vector Table 0x003F FFBE 0x0042
(1)
Check the data manual to determine if these are available for your device part number. If not available, treat these sections as
reserved.

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Table 5-33. CM Boot ROM Memory Map

Memory Origin Address Length (Bytes)
Vector Table 0x0000 0000 0x0140
Version 0x0000 0140 0x0004
Boot Checksum 0x0000 0144 0x0084
Full ROM Checksum 0x0000 01C8 0x0084
Boot 0x0000 024C 0x3DCC
Interrupt Handlers 0x0000 4018 0x0204
CRC Table 0x0000 FBFC 0x0400
ROM Signature 0x0000 FFFC 0x0004

5.7.5.2 CLA Data ROM Memory Maps

Table 5-34. CPU1 CLA Data ROM Memory Map

Memory Origin Address Length (Words)
FFT Tables (Load) 0x0100 1070 0x0800
Data (Load) 0x0100 1870 0x078A
Version (Load) 0x0100 1FFA 0x0006
FFT Tables (Run) 0x0000 F070 0x0800
Data (Run) 0x0000 F870 0x078A
Version (Run) 0x0000 FFFA 0x0006

Table 5-35. CPU2 CLA Data ROM Memory Map

Memory Origin Address Length (Words)
FFT Tables (Load) 0x0100 1070 0x0800
Data (Load) 0x0100 1870 0x078A
Version (Load) 0x0100 1FFA 0x0006
FFT Tables (Run) 0x0000 F070 0x0800
Data (Run) 0x0000 F870 0x078A
Version (Run) 0x0000 FFFA 0x0006

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5.7.5.3 Reserved RAM Memory Maps

This section details memory usage in RAM that is reserved for boot ROM to use. These memory sections
should be reserved in the user application.

Table 5-36. CPU1 Reserved RAM Memory Map

Memory Description Origin Address End Address Length (Words)
Boot Status, Boot
RAM Mode, MPOST Status, 0x0000 0002 0x0000 01B0 0x01AF
Boot Stack

Table 5-37. CPU2 Reserved RAM Memory Map

Memory Description Origin Address End Address Length (Words)
Boot Status, Boot
RAM 0x0000 0002 0x0000 01A8 0x01A7
Mode, Boot Stack

Table 5-38. CM Reserved RAM Memory Map

Memory Description Origin Address End Address Length (Bytes)
Boot Status, Boot
RAM 0x2000 0000 0x2000 07FF 0x0800
Mode, Boot Stack

5.7.6 ROM Tables

Table 5-39 details the boot ROM and CLA ROM symbol libraries that can be integrated into an application
to use the available ROM functions and tables.

Table 5-39. ROM Symbol Tables

ROM Symbols Library Name Location
ROM Bootloaders and Functions F2838xCPU1_BootROM_Symbols
F2838xCPU1_BootROM_Symbols
FPU32 and FPU64 Tables
F2838xCPU2_BootROM_Symbols
F2838xCPU1_BootROM_Symbols
AES Tables
F2838xCPU2_BootROM_Symbols
F2838xCPU1_CLADATAROM_Symbols Under /libraries/boot_rom in
CLA Data ROM C2000Ware
F2838xCPU2_CLADATAROM_Symbols
F2838xCPU1_IQMathROM_Symbols
IQmath
F2838xCPU2_IQMathROM_Symbols
F2838xCPU1_SecureZoneCode_Symbols
Secure Zone Functions F2838xCPU2_SecureZoneCode_Symbols
F2838xCM_SecureZoneCode_Symbols

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5.7.7 Boot Modes and Loaders

The available boot modes and bootloaders supported on this device are detailed in this section.

5.7.7.1 Boot Modes

Table 5-40 details the available boot modes that do not involve a peripheral boot loader.

Table 5-40. Boot Mode Availability

Boot Mode CPU Support
Wait Boot CPU1, CPU2, CM
Flash Boot CPU1, CPU2, CM
Secure Flash Boot CPU1, CPU2, CM
RAM Boot CPU1, CPU2, CM
User OTP Boot CPU2, CM
IPC Message Copy to RAM Boot CPU2, CM

5.7.7.1.1 Wait Boot

The wait boot mode puts the CPU in a loop and does not branch to the user application code. The device
can either enter wait boot mode through configuration or because an error occurred during boot up. TI
recommends using wait boot when using a debugger to avoid any JTAG complications. CPU2 and CM
can exit wait boot mode and run a different boot mode when CPU1 sets the respective CPU IPCFLG0.
More information regarding this can found at Section 5.7.2.

Table 5-41. Reasons for Entering Wait Boot

CPU Actions Resulting in Wait Boot
• Wait boot is selected by user configuration
CPU1 • Decoded boot mode is unrecognized/invalid when a debugger is connected to the device
• The emulation BOOTPIN_CONFIG key isn't set to 0xA5 or 0x5A
• Wait boot is selected by user configuration
• Decoded boot mode is unrecognized/invalid when a debugger is connected to the device
CPU2 • Secure flash boot CMAC calculation returns failure
• IPC Message copy to RAM length specified is invalid (out of range) when trying to use this
boot mode
• Wait boot is selected by user configuration
• Decoded boot mode is unrecognized/invalid when a debugger is connected to the device
CM • Secure flash boot CMAC calculation returns failure
• IPC Message copy to RAM length specified is invalid (out of range) when trying to use this
boot mode

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5.7.7.1.2 Flash Boot

Flash boot mode branches to the configured memory address in flash. Refer to Section 5.7.3 for all the
available flash address options.
For CPU1, on an unprogrammed device, flash boot can be switched to USB boot. See more details in
Section 5.3.

5.7.7.1.3 Secure Flash Boot

Secure flash boot mode is similar to flash boot mode in that the boot flow branches to the configured
memory address in flash except only after the flash memory contents have been authenticated. The flash
authentication uses a Cipher-based Message Authentication Protocol (CMAC) to authenticate 16KB of
flash starting from the configured flash entry point address. The CMAC calculation requires a user-defined
128-bit key programmed in the CPU1 User OTP Zone 1 Header OTP CMACKEY bit field. Additionally, the
user must calculate the golden CMAC tag based on the 16KB flash memory range and store it along with
the user code at a hardcoded address in flash. During secure flash boot, the calculated CMAC tag is
compared to the user golden CMAC tag in flash to determine the pass/fail status of the CMAC
authentication. When authentication passes, boot flow continues and branches to flash to begin executing
the application. When authentication fails, the boot flow actions performed vary by core. Refer to Table 5-
43 for details on failure actions for each core.
For the available secure flash boot entry address options, refer to Section 5.7.3.
For generating the secure flash golden CMAC tag for CPU1 or CPU2, refer to the TMS320C28x Assembly
Language Tools User’s Guide within section “Using Secure Flash Boot on TMS320F2838x Devices” for
instructions.
For generating the secure flash golden CMAC tag for CM, refer to the ARM Assembly Language Tools
v19.6.0.STS, within section “Using Secure Flash Boot on TMS320F2838x Devices” for instructions.

NOTE:
• User must ensure that the flash sector that encompasses the configured flash
entry point and the first 16KB of flash is assigned to Zone 1 for any cores setup
to use secure flash boot.
• Recommended to use device JTAGLOCK when using secure flash boot.
• If only using secure flash boot for CPU2/CM, then the CPU1 application must
first dummy load the Z1 OTP CMACKEY before releasing CPU2/CM from reset.
When dummy loading, CPU1 application must first disable flash data caching,
then perform the dummy load, and then the application can re-enable flash data
caching.

Table 5-42. Secure Flash Tag and Key Details

Name Address Details
Located in flash, offset from the entry point address, by 2 words
(CPU1/CPU2) or 4 bytes (CM).
When CMAC calculations are performed, the golden tag
location in memory will be considered all 0xFs. Refer to
Example 5-1 for an example regarding linker configuration on
CPU1.
CMAC Golden Lower memory contains the tag's MSW and higher memory
CPU1/CPU2:Flash Entry Point Address + 0x2
Tag contains the LSW
CM: Flash Entry Point Address + 0x4
(128-bit)
Example (on CPU1):
Tag = 0x00112233 44556677 8899AABB CCDDEEFF
Address 0x0 = 0x00112233
Address 0x2 = 0x44556677
Address 0x4 = 0x8899AABB
Address 0x6 = 0xCCDDEEFF

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Table 5-42. Secure Flash Tag and Key Details (continued)

Name Address Details
Located in CPU1 Zone 1 User Header OTP
(CMACKEY0, CMACKEY1, CMACKEY2, CMACKEY3)
CMACKEY0 contains the key's MSW and CMACKEY3 contains
the LSW
CMAC 128-Bit
0x0007 8018 Example:
Key
Key = 0x00112233 44556677 8899AABB CCDDEEFF
CMACKEY0 = 0x00112233
CMACKEY1 = 0x44556677
CMACKEY2 = 0x8899AABB
CMACKEY3 = 0xCCDDEEFF

Table 5-43. Secure Flash Authentication Failure Actions

CPU Action on Failed Authentication
CPU1 Reset the device (If using debugger, device halts)
CPU2 Send IPC message to CPU1, update CPU2 boot status to indicate failure, and return to wait boot
CM Send IPC message to CPU1, update CM boot status to indicate failure, and return to wait boot

Table 5-44. Secure Flash on all CPUs Recommended Flow

Step Action
1 Secure flash boot CPU1
CPU1 application configures CPU2 and CM to boot using Secure Flash Boot and releases CPU2/CM from
2
reset
3 CPU2 and CM perform secure flash boot
4 CPU2 and CM applications signal to CPU1 via IPC that booting is complete
For CPU1/CPU2/CM, any flash beyond the first 16KB from the entry point that is planned for use should be
5 authenticated by the user using a different CMAC golden tag embedded at an address somewhere within the
already authenticated 16KB of flash

Example 5-1. Secure Flash CPU1 Linker File Example

MEMORY
{
/* Code Start branch to _c_int00 */
BEGIN : origin = 0x80000, length = 0x0002

/* User calculated golden CMAC tag for Flash Sector 0 */

GOLDEN_CMAC_TAG : origin = 0x80002, length = 0x0008

/* Flash Sector 0 containing application code */

FLASH_SECTOR_0 : origin = 0x8000A, length = 0x1FF6
.
.
.
}

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5.7.7.1.4 RAM Boot

RAM boot mode branches to the configured memory address in RAM. Refer to Section 5.7.3 for all the
available RAM address options.

5.7.7.1.5 User OTP Boot

User OTP boot mode branches to the configured memory address in User OTP. Refer to Section 5.7.3 for
all the available user OTP address options.

5.7.7.1.6 IPC Message Copy to RAM Boot

IPC message copy to RAM involves copying application code from CPU1 IPC message RAM 1 to
CPU2/CM destination RAM for execution. The maximum copy length size is 1000 words (2000 bytes) and
the minimum is 100 words (200 bytes). Refer to Table 5-45 for details regarding configuration and
execution flow of this boot mode.

Table 5-45. IPC Message Copy Steps

Step Action
CPU1 application links CPU2/CM code to copy in either CPU1TOCPU2MSGRAM1 or
1
CPU1TOCMMSGRAM1.
CPU1 application configures CPU2/CM IPCBOOTMODE with the copy length and IPC message copy as the
2
boot mode. See Section 5.7.2.2 for more IPCBOOTMODE details.
Once CPU2/CM is released from reset to boot, CPU2/CM begins copying from
3 CPU1TOCPU2MSGRAM1/CPU1TOCMMSGRAM1 to their destination RAM. Refer to Table 5-46 for
destination RAM details.
Once the copying is complete, CPU2/CM boot branches to the entry address of the destination RAM and
4
begins executing the application.

Table 5-46. IPC Message Copy Destination Address

Destination Address Range (1)
CPU RAM
(For max copy length of 1000 words)
CPU2 M1RAM 0x0000 0400 to 0x0000 07E6
CM S0RAM 0x2000 0800 to 0x2000 0FCC
(1)
This memory should be allocated and reserved in the CPU2/CM application linker command file when using this boot mode.

5.7.7.2 Bootloaders
This section details the available boot modes that use a peripheral boot loader. For more specific details
on the supported data stream structure used by the following bootloaders, refer to Section 5.8.1.

NOTE: These are only available on CPU1.

5.7.7.2.1 SCI Boot Mode

The SCI boot mode asynchronously transfers code from SCI-A to internal memory. This boot mode only
supports an incoming 8-bit data stream and follows the data flow as outlined in Example 5-2.

Figure 5-6. Overview of SCI Bootloader Operation

SCIRXDA
Control Host
Subsystem (Data and program
boot ROM SCITXDA source)

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The device communicates with the external host by communication through the SCI-A peripheral. The
autobaud feature of the SCI port is used to lock baud rates with the host. For this reason the SCI loader is
very flexible and you can use a number of different baud rates to communicate with the device.
After each data transfer, the bootloader will echo back the 8-bit character received to the host. This allows
the host to check that each character was received by the bootloader.
At higher baud rates, the slew rate of the incoming data bits can be affected by transceiver and connector
performance. While normal serial communications may work well, this slew rate may limit reliable auto-
baud detection at higher baud rates (typically beyond 100kbaud) and cause the auto-baud lock feature to
fail. To avoid this, the following is recommended:
1. Achieve a baud-lock between the host and SCI bootloader using a lower baud rate.
2. Load the incoming application or custom loader at this lower baud rate.
3. The host may then handshake with the loaded application to set the SCI baud rate register to the
desired high baud rate.

Figure 5-7. Overview of SCI Boot Function

SCI_Boot

Enable the SCI-A clock Echo autobaud character

set the LSPCLK to /4

Enable the SCIA TX and RX pin Read KeyValue

functionality and pullups on
TX and RX

Valid No
Setup SCI-A for KeyValue Jump to Flash
1 stop, 8-bit character, (0x08AA)
no parity, use internal ?
SC clock, no loopback,
disable Rx/Tx interrupts
Yes

Read and discard 8

Disable SCI FIFOs reserved words

Prime SCI-A baud register Read EntryPoint address

Enable autobaud detection Read data in the standard

boot stream format

No Autobaud
lock
?

Return
Yes EntryPoint

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5.7.7.2.2 SPI Boot Mode

The SPI loader expects an SPI-compatible 16-bit or 24-bit addressable serial EEPROM or serial flash
device to be present on the SPI-A pins as indicated in Figure 5-8. The SPI bootloader supports an 8-bit
data stream. It does not support a 16-bit data stream.

Figure 5-8. SPI Loader

Serial SPI
EEPROM
SPIA_SIMO
DIN
Control SPIA_SOMI
DOUT
subsystem SPIA_CLK CLK
SPIA_STE CS

The SPI boot ROM loader initializes the SPI module to interface to a serial SPI EEPROM or flash. Devices
of this type include, but are not limited to, the Xicor X25320 (4Kx8) and Xicor X25256 (32Kx8) SPI serial
SPI EEPROMs and the Atmel AT25F1024A serial flash.
The SPI boot ROM loader initializes the SPI with the following settings: FIFO enabled, 8-bit character,
internal SPICLK master mode and talk mode, clock phase = 1, polarity = 0, using the slowest baud rate.
If the download is to be performed from an SPI port on another device, then that device must be set up to
operate in the slave mode and mimic a serial SPI EEPROM. Immediately after entering the SPI_Boot
function, the pin functions for the SPI pins are set to primary and the SPI is initialized. The initialization is
done at the slowest speed possible. Once the SPI is initialized and the key value read, you could specify a
change in baud rate or low speed peripheral clock.

Table 5-47. SPI 8-Bit Data Stream

Byte Contents
1 LSB: AA (KeyValue for memory width = 8-bits)
2 MSB: 08h (KeyValue for memory width = 8-bits)
3 LSB: LOSPCP
4 MSB: SPIBRR
5 LSB: reserved for future use
6 MSB: reserved for future use
... ...
... Reserved
...
17 LSB: reserved for future use
18 MSB: reserved for future use
19 LSB: Upper half (MSW) of Entry point PC[23:16]
20 MSB: Upper half (MSW) of Entry point PC[31:24] (Note: Always 0x00)
21 LSB: Lower half (LSW) of Entry point PC[7:0]
22 MSB: Lower half (LSW) of Entry point PC[15:8]
... ....
... Data for this section.
...
... Blocks of data in the format size/destination address/data as shown in the generic
data stream description
... ...
... Data for this section.
...
n LSB: 00h
n+1 MSB: 00h - indicates the end of the source

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The data transfer is done in "burst" mode from the serial SPI EEPROM. The transfer is carried out entirely
in byte mode (SPI at 8 bits/character). A step-by-step description of the sequence follows:
Step 1. The SPI-A port is initialized
Step 2. The GPIO pin, as defined by SPI option configured from Table 5-61, is used as a chip-select
for the serial SPI EEPROM or flash
Step 3. The SPI-A outputs a read command for the serial SPI EEPROM or flash
Step 4. The SPI-A sends the serial SPI EEPROM an address 0x0000; that is, the host requires that
the EEPROM or flash must have the downloadable packet starting at address 0x0000 in the
EEPROM or flash. The loader is compatible with both 16-bit addresses and 24-bit addresses.
Step 5. The next word fetched must match the key value for an 8-bit data stream (0x08AA). The least
significant byte of this word is the byte read first and the most significant byte is the next byte
fetched. This is true of all word transfers on the SPI. If the key value does not match, then the
load is aborted and the bootloader jumps to flash.
Step 6. The next two bytes fetched can be used to change the value of the low speed peripheral
clock register (LOSPCP) and the SPI baud rate register (SPIBRR). The first byte read is the
LOSPCP value and the second byte read is the SPIBRR value. The next seven words are
reserved for future enhancements. The SPI bootloader reads these seven words and
discards them.
Step 7. The next two words makeup the 32-bit entry point address where execution will continue after
the boot load process is complete. This is typically the entry point for the program being
downloaded through the SPI port.
Step 8. Multiple blocks of code and data are then copied into memory from the external serial SPI
EEPROM through the SPI port. The blocks of code are organized in the standard data stream
structure presented earlier. This is done until a block size of 0x0000 is encountered. At that
point in time the entry point address is returned to the calling routine that then exits the
bootloader and resumes execution at the address specified.

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Figure 5-9. Data Transfer From EEPROM Flow

SPI_Boot

Enable the SPI-A clock

Set the LSPCLK to 4 Valid No
KeyValue Jump to Flash
(0x08AA)
?
Enable SPISIMOA,
SPISOMI and SPICLKA
pin functionality and enable Yes
pullups on those pins
Read LOSPCP value Change LOSPCP

Set up SPI-A for

8-bit character,
Use internal SPI clock,
master mode
Use slowest baud rate (0x7F)
Relinquish SPI-A from reset

Read SPIBRR value Change SPIBRR

Set chip enable high

Enable EEPROM
Send read command and Read and discard 7
start at EEPROM address reserved words
0x0000

Read EntryPoint Return

Read KeyValue address Call CopyData EntryPoint

5.7.7.2.3 I2C Boot Mode

The I2C bootloader expects an 8-bit wide I2C-compatible EEPROM device to be present at address 0x50
on the I2C-A bus as indicated in Figure 5-10. The EEPROM must adhere to conventional I2C EEPROM
protocol, as described in this section, with a 16-bit base address architecture.

Figure 5-10. EEPROM Device at Address 0x50

SDA SCL

I2CA_SDA
Control
subsystem
I2CA_SCL
I2C
SDA EEPROM

SCL Slave Address

0x50

If the download is to be performed from a device other than an EEPROM, then that device must be set up
to operate in the slave mode and mimic the I2C EEPROM. Immediately after entering the I2C boot
function, the GPIO pins are configured for I2C-A operation and the I2C is initialized. The following
requirements must be met when booting from the I2C module:
• The input frequency to the device must be in the appropriate range.
• The EEPROM must be at slave address 0x50.
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Figure 5-11. Overview of I2C Boot Function

NACK Yes
I2C_Boot
received Jump to Flash
?
Enable I2CA_SDA and
I2CA_SCL pins No
Enable pullups on
I2CA_SDA and I2CA_SCL Read KeyValue

Enable I2C-A clock

Valid No
KeyValue Jump to Flash
(0x08AA)
Set slave address 0x50
?
I2C prescaler I2CPSC = or 0
Yes
100-kHz bit rate Put 12c-A in Reset
Read I2CPSC value Set I2CPSC value
Enable TX/RX FIFOs to Read I2CCLKH value Set I2CCLKH value
receive 2 bytes. Read 12CCLKL value Set I2CCLKL value
Bring I2C-A out of Reset

Place I2C in master

transmitter mode
Set EEPROM address
pointer to 0x0000 Read and discard 5
reserved words

Read EntryPoint
address

Read data in standard

boot stream format

Return
EntryPoint

The bit-period prescalers (I2CCLKH and I2CCLKL) are configured by the bootloader to run the I2C at a 50
percent duty cycle at 100-kHz bit rate (standard I2C mode) when the system clock is 10 MHz. These
registers can be modified after receiving the first few bytes from the EEPROM. This allows the
communication to be increased up to a 400-kHz bit rate (fast I2C mode) during the remaining data reads.
Arbitration, bus busy, and slave signals are not checked. Therefore, no other master is allowed to control
the bus during this initialization phase. If the application requires another master during I2C boot mode,
that master must be configured to hold off sending any I2C messages until the application software
signals that it is past the bootloader portion of initialization.
The non-acknowledgment bit is checked only during the first message sent to initialize the EEPROM base
address. This is to make sure that an EEPROM is present at address 0x50 before continuing. If an
EEPROM is not present, the non-acknowledgment bit is not checked during the address phase of the data
read messages (I2C_Get Word). If a non acknowledgment is received during the data read messages, the
I2C bus will hang. Table 26-1 shows the 8-bit data stream used by the I2C.

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Table 5-48. I2C 8-Bit Data Stream

Byte Contents
1 LSB: AA (KeyValue for memory width = 8 bits)
2 MSB: 08h (KeyValue for memory width = 8 bits)
3 LSB: I2CPSC[7:0]
4 reserved
5 LSB: I2CCLKH[7:0]
6 MSB: I2CCLKH[15:8]
7 LSB: I2CCLKL[7:0]
8 MSB: I2CCLKL[15:8]
... ...
... Data for this section.
...
17 LSB: Reserved for future use
18 MSB: Reserved for future use
19 LSB: Upper half of entry point PC
20 MSB: Upper half of entry point PC[22:16] (Note: Always 0x00)
21 LSB: Lower half of entry point PC[15:8]
22 MSB: Lower half of entry point PC[7:0]
... ...
... Data for this section.
...
Blocks of data in the format size/destination address/data as shown in the generic data stream
description.
... ...
... Data for this section.
...
n LSB: 00h
n+1 MSB: 00h - indicates the end of the source

The I2C EEPROM protocol required by the I2C bootloader is shown in Figure 5-12 and Figure 5-13. The
first communication, which sets the EEPROM address pointer to 0x0000 and reads the KeyValue
(0x08AA) from it, is shown in Figure 5-12. All subsequent reads are shown in Figure 5-13 and are read
two bytes at a time.

Figure 5-12. Random Read

RESTART

NO ACK
START

WRITE

READ

STOP
MSB

MSB

ACK
ACK

ACK

ACK
ACK
LSB

LSB

SDA LINE
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 1 01 0 0 0 0 1 0

Device Address Address Device DATA BYTE 1 DATA BYTE 2

Address Pointer, MSB Pointer, LSB Address

Figure 5-13. Sequential Read

NO ACK
START

READ

STOP
ACK

ACK

SDA LINE
1 01 0 0 0 0 1 0

Device DATA BYTE n DATA BYTE n+1

Address

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5.7.7.2.4 Parallel Boot Mode

The parallel general purpose I/O (GPIO) boot mode asynchronously transfers code from GPIO88,
GPIO62:GPIO58, GPIO90:GPIO89 to internal memory. Each value is eight bits long and follows the same
data flow as outlined in Figure 5-14.

Figure 5-14. Overview of Parallel GPIO Bootloader Operation

28x control − GPIO91
Host control − GPIO92 Host
boot ROM (data and program
8 source)

Data GP I/O port GPIO[88, 62:58, 90:89]

The control subsystem communicates with the external host device by polling/driving the GPIO92 and
GPIO91 lines. The handshake protocol shown in Figure 5-15 must be used to successfully transfer each
word via GPIO [88,62:58,90:89]. This protocol is very robust and allows for a slower or faster host to
communicate with the master subsystem.
Two consecutive 8-bit words are read to form a single 16-bit word. The least significant byte (LSB) is read
first followed by the most significant byte (MSB). In this case, data is read from GPIO[88,62:58,90:89].
The 8-bit data stream is shown in Table 5-49.

Table 5-49. Parallel GPIO Boot 8-Bit Data Stream

Bytes GPIO[88,62:58, GPIO[88,62:58, Description
90:89] 90:89]
(Byte 1 of 2) (Byte 2 of 2)
1 2 AA 08 0x08AA (KeyValue for memory width = 16 bits)
3 4 00 00 8 reserved words (words 2 - 9)
... ... ... ... ...
17 18 00 00 Last reserved word
19 20 BB 00 Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0x00BBCCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of first block Addr[31:16]
27 28 DD CC Destination address of first block Addr[15:0] (Addr = 0xAABBCCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ...
... Data for this section.
...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the 2nd block to load = 0xMMNN words
. BB AA Destination address of second block Addr[31:16]
. DD CC Destination address of second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
. …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

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The device first signals the host that it is ready to begin data transfer by pulling the GPIO91 pin low. The
host load then initiates the data transfer by pulling the GPIO92 pin low. The complete protocol is shown in
Figure 5-15.

Figure 5-15. Parallel GPIO Bootloader Handshake Protocol

1 2 3 4 5 6

Host control
GPIO92

Device control
GPIO91

1. The device indicates it is ready to start receiving data by pulling the GPIO91 pin low.
2. The bootloader waits until the host puts data on GPIO [88,62:58,90:89]. The host signals to the device
that data is ready by pulling the GPIO92 pin low.
3. The device reads the data and signals the host that the read is complete by pulling GPIO91 high.
4. The bootloader waits until the host acknowledges the device by pulling GPIO92 high.
5. The device again indicates it is ready for more data by pulling the GPIO91 pin low.
This process is repeated for each data value to be sent.
Figure 5-16 shows an overview of the Parallel GPIO bootloader flow.

Figure 5-16. Parallel GPIO Mode Overview

Parallel_Boot

Initialize GP I/O MUX Read and discard 8

and Dir registers reserved words
GPIO[88,62:58,90:89] = input
GPIO92 = input
GPIO91 = output
Enable pullups on Read EntryPoint
address
GPIO[88,62:58,90:89]

Call
CopyData

Valid
No KeyValue
Return Flash EntryPoint (0x08AA)
?
Return
Yes EntryPoint

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Figure 5-17 shows the transfer flow from the host side. The operating speed of the CPU and host are not
critical in this mode as the host will wait for the device and the device will in turn wait for the host. In this
manner the protocol will work with both a host running faster and a host running slower than the device.

Figure 5-17. Parallel GPIO Mode - Host Transfer Flow

Start transfer

No Device ready
(GPIO91=0)
?

Yes No Device ack

(GPIO91=1)
Load GPIO[88,62:58,90:89] with data ?

Yes
Signal that data
is ready Acknowledge device
(GPIO92=0) (GPIO92=1)

More Yes
data
?

No

End transfer

Figure 5-18 shows the flow used to read a single word of data from the parallel port.
• 8-bit data stream
The 8-bit routine, shown in Figure 5-18, discards the upper eight bits of the first read from the port and
treats the lower eight bits masked with GPIO89 in bit position 7 and GPIO90 in bit position six as the
least significant byte (LSB) of the word to be fetched. The routine will then perform a second read to
fetch the most significant byte (MSB). The routine will then perform a second read to fetch the most
significant byte (MSB). It then combines the MSB and LSB into a single 16-bit value to be passed back
to the calling routine.

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Figure 5-18. 8-Bit Parallel GetWord Function

Parallel_GetWordData A
8 bit

Signal host that device is ready Signal host that device

is ready to read MSB
(GPIO91 = 0) (GPIO91 = 0)

Data Data
ready No ready No
(GPIO92 = 0) (GPIO92 = 0)
? ?

Yes Yes

Read word of data

from GPIO[88,62:58,90:89] Read GPIO for LSB and
MSB of 16-bit data

Device ack read complete

(GPIO91 = 1)

Device ack read complete

(GPIO91 = 1)

Host
ack No
(GPIO92 = 1)
? Host
ack No
Yes (GPIO92 = 1)
?

Yes

WordData = MSB:LSB

A
Return WordData

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5.7.7.2.5 CAN Boot Mode

The CAN bootloader asynchronously transfers code from CAN-A to internal memory. The host can be any
CAN node. The communication is first done with 11-bit standard identifiers (with a MSGID of 0x1) using
two bytes per data frame. The host can download a kernel to reconfigure the CAN if higher data
throughput is desired.

Figure 5-19. Overview of CAN-A Bootloader Operation

28x

CAN bus
CAN
host

28x

The bit timing registers are programmed in such a way that a 100 kbps bit rate is achieved with a 20 MHz
external oscillator, a shown in Table 5-50.

Table 5-50. Bit-Rate Value for Internal Oscillators

OSCCLK SYSCLK Bit Rate
20 MHz 10 MHz 100 kbps

The SYSCLKOUT values shown are the reset values with the default PLL setting. The BRP and bit-time
values are hard-coded to 10 and 20, respectively.

NOTE: The CPU1 CAN boot loader uses XTAL as the bit clock source and INTOSC2 as the system
clock source.

Mailbox 1 is programmed with a standard MSGID of 0x1 for boot-loader communication. The CAN host
should transmit only two bytes at a time, LSB first and MSB next. For example, to transmit the word
0x08AA to the device, transmit AA first, followed by 08. The program flow of the CAN bootloader is
identical to the SCI bootloader. The data sequence for the CAN bootloader is shown in Table 5-51.

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Table 5-51. CAN 8-Bit Data Stream

Bytes Byte 1 of 2 Byte 2 of 2 Description
1 2 AA 08 0x08AA (KeyValue for memory width = 16 bits)
3 4 00 00 reserved
5 6 00 00 reserved
7 8 00 00 reserved
9 10 00 00 reserved
11 12 00 00 reserved
13 14 00 00 reserved
15 16 00 00 reserved
17 18 00 00 reserved
19 20 BB AA Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0xAABBCCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of first block Addr[31:16]
27 28 DD CC Destination address of the first block Addr[15:0] (Addr = 0xAABBCCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ....
... Data for this section.
...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the second block to load = 0xMMNN words
. BB AA Destination address of the second block Addr[31:16]
. DD CC Destination address of the second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
. …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

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5.7.7.2.6 USB Boot Mode

In USB boot mode, the device will enumerate with vendor ID 0x1cbe and product ID 0x00ff. The device
descriptor and interface descriptor both show the class as 0xFF (vendor-specific), the subclass as 0x00,
and the protocol as 0x00. After enumeration, the device will wait for data. Data should be sent via bulk
OUT transfers to endpoint 1. The data is interpreted as a series of 8-bit bytes in the standard data stream
format described in Section 5.8.1, shown here in Table 5-52. No reserved bytes are used. Once the data
transfer is complete (block size of 0x0000 sent), the device will disconnect from the USB bus, allowing
other software to make use of the module if desired. Figure 5-20 illustrates the flow for USB boot mode.

Figure 5-20. USB Boot Flow

USB_Boot

Host sends boot

loader data in the
Wait for standard stream
connection format via bulk OUT
transfers to
endpoint 1

Enumerate to host
PC with ID 1cbe:00ff Valid key
Jump to flash
(0x08AA)?

Host PC installs
drivers
MCU loads data into
RAM

MCU waits
for data MCU disconnects
from the USB bus

Return EntryPoint

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Table 5-52. USB 8-Bit Data Stream

Bytes First Byte Second Byte Description
(LSB) (MSB)
1 2 AA 08 0x08AA (KeyValue for memory width = 16bits)
3 4 00 00 reserved
5 6 00 00 reserved
7 8 00 00 reserved
9 10 00 00 reserved
11 12 00 00 reserved
13 14 00 00 reserved
15 16 00 00 reserved
17 18 00 00 reserved
19 20 BB AA Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0xAABBCCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of the first block Addr[31:16]
27 28 DD CC Destination address of the first block Addr[15:0] (Addr = 0xAABBCCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ....
... Data for this section.
...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the 2nd block to load = 0xMMNN words
. BB AA Destination address of the second block Addr[31:16]
. DD CC Destination address of the second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
. …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

Implementing PC-side USB software is not trivial. It is recommended to use the TI-provided tools and
drivers to load data in USB boot mode. Hex and binary files for loader tools can be generated from COFF
(.out) files using the hex2000 tool. To produce a plain binary file in the boot loader format, use the
following command line:
hex2000 -boot -b Program_to_Load.out -o Binary_Loader_Data.dat
For more information on hex2000, see the TMS320C28x Assembly Language Tools User's Guide.

NOTE: INTOSC2 must be enabled before invoking the USB boot loader. If INTOSC2 is not enabled,
the boot loader will hang. A debugger reset or SCC reset will not enable INTOSC2 if it has
been disabled by the application.

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5.7.8 GPIO Assignments for CPU1

This section details the GPIOs and boot option values used for each CPU1 boot mode set in the
BOOT_DEF memory location located at Z1-BOOTDEF-LOW/ Z2-BOOTDEF-LOW and Z1-BOOTDEF-
HIGH/ Z2-BOOTDEF-HIGH. Refer to Section 5.4.2 on how to configure BOOT_DEF. When selecting a
boot mode option, make sure to verify that the necessary pins are available in the pin mux options for the
specific device package being used.

NOTE: These configurations only apply to CPU1. Refer to Section 5.7.2 for details on configuring
CPU2 and CM boot modes.

Table 5-53. SCI Boot Options

Option BOOTDEF Value SCITXDA GPIO SCIRXDA GPIO
0 (default) 0x01 GPIO29 GPIO28
1 0x21 GPIO84 GPIO85
2 0x41 GPIO36 GPIO35
3 0x61 GPIO42 GPIO43
4 0x81 GPIO65 GPIO64
5 0xA1 GPIO135 GPIO136
6 0xC1 GPIO8 GPIO9

Table 5-54. CAN Boot Options

Option BOOTDEF Value CANTXA GPIO CANRXA GPIO
0 (default) 0x02 GPIO37 GPIO36
1 0x22 GPIO71 GPIO70
2 0x42 GPIO63 GPIO62
3 0x62 GPIO19 GPIO18
4 0x82 GPIO4 GPIO5
5 0xA2 GPIO31 GPIO30

Table 5-55. I2C Boot Options

Option BOOTDEF Value SDAA GPIO SCLA GPIO
0 0x07 GPIO91 GPIO92
1 0x27 GPIO32 GPIO33
2 0x47 GPIO42 GPIO43
3 0x67 GPIO0 GPIO1
4 0x87 GPIO104 GPIO105

Table 5-56. USB Boot Options

Option BOOTDEF Value USBDM GPIO USBDP GPIO
0 (default) 0x09 GPIO42 GPIO43

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Table 5-57. RAM Boot Options

Option BOOTDEF Value RAM Entry Point
(Address)
0 0x05 0x0000 0000

Table 5-58. Flash Boot Options

Option BOOTDEF Value Flash Entry Point Flash Sector
(Address)
0 (default) 0x03 0x0008 0000 CPU1 Bank0 Sector 0
1 0x23 0x0008 8000 CPU1 Bank 0 Sector 4
2 0x43 0x000A 8000 CPU1 Bank 0 Sector 8
3 0x63 0x000B E000 CPU1 Bank 0 Sector 13

Table 5-59. Secure Flash Boot Options

Option BOOTDEF Value Flash Entry Point Flash Sector
(Address)
0 0x0A 0x0008 0000 CPU1 Bank0 Sector 0
1 0x2A 0x0008 8000 CPU1 Bank 0 Sector 4
2 0x4A 0x000A 8000 CPU1 Bank 0 Sector 8
3 0x6A 0x000B E000 CPU1 Bank 0 Sector 13

Table 5-60. Wait Boot Options

Option BOOTDEF Value Watchdog
0 0x04 Enabled
1 0x24 Disabled

Table 5-61. SPI Boot Options

Option BOOTDEF Value SPISIMOA SPISOMIA SPICLKA SPISTEA
0 0x06 GPIO58 GPIO59 GPIO60 GPIO61
1 0x26 GPIO16 GPIO17 GPIO18 GPIO19
2 0x46 GPIO32 GPIO33 GPIO34 GPIO35
3 0x66 GPIO16 GPIO17 GPIO56 GPIO57
4 0x86 GPIO54 GPIO55 GPIO56 GPIO57

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Table 5-62. Parallel Boot Options

Option BOOTDEF Value D0-D7 GPIO DSP Control GPIO Host Control GPIO
0 (default) 0x0 D0 - GPIO89 GPIO91 GPIO92
D1 - GPIO90
D2 - GPIO58
D3 - GPIO59
D4 - GPIO60
D5 - GPIO61
D6 - GPIO62
D7 - GPIO88

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5.7.9 Secure ROM Function APIs

Within secure ROM of each core, functions are available to be called by the application to perform
EXEONLY flash/RAM tasks in a secure manner.

NOTE: The application should disable interrupts before calling one of the EXEONLY function APIs.
If a vector fetch request is given by the CPU (C28 or CM, depending on the subsystem)
while its program counter (PC) is within the EXEONLY function API code of the Secure
ROM, a reset will fire (RSN if from C28; SYSRESETn if from CM). The consequence of this
is if an NMI or ITRAP or Bus Fault occurs while the PC is executing one of the EXEONLY
API functions, the NMI/ITRAP/Fault cannot be serviced because a reset will be fired to that
subsystem.

The secure copy code zone 1 and zone 2 functions allow EXEONLY Flash to be copied to EXEONLY
RAM in a secure manner. The source must be from EXEONLY Flash and the destination to EXEONLY
RAM. There is no support to copy EXEONLY ROM or EXEONLY RAM to RAM. Both Flash and RAM
must be set to EXEONLY and configured for the same zone. Additionally, the copy size must not cross
over the flash sector boundary. Any violations of these requirements will result in a failure status returned.
Upon successful copy of the data, the number of 16-bit words copied is returned.

Table 5-63. Secure Copy Code Function

CPU Function Prototype Function Parameters Function Return Value

Uint16 SecureCopyCodeZ1(Uint32 size : The number of 16-bit words to 0xXXXX : Returns the number of
size, Uint16 *dst, Uint16 *src) copy 16-bit words copied

dst : The destination memory 0x0000 : Indicates one of the

CPU1, CPU2, address in EXEONLY RAM following: Copy length is zero; Copy
CM size crosses over flash sector
src : The source memory address in boundary; Flash and RAM don't
Uint16 SecureCopyCodeZ2(Uint32 EXEONLY Flash belong to the same zone; Flash
size, Uint16 *dst, Uint16 *src) and/or RAM aren't set to EXEONLY;
Error occurred during data copy

The secure CRC calculation zone 1 and zone 2 functions allow a safety CRC check of EXEONLY
memory in a secure manner. The CRC length provided must be a value from 1 to 8 where 1 represents a
CRC size of 32 16-bit words and 8 represents a CRC size of 4096 16-bit words. The source address
specifies the starting address for the CRC and the destination address is the location that the resulting
CRC value will be stored. The source and destination memories must be configured for the same zone.
Additionally, the CRC length must not cross over the flash sector or RAM block boundary. On the CM,
there is an additional requirement that CRCLOCK isn't enabled. Any violations of these requirements will
result in a failure status returned. Upon successful CRC, the number of 16-bit words CRC'd is returned.

Table 5-64. Secure CRC Calculation Function

CPU Function Prototype Function Parameters Function Return Value

len_id : A number from 1 to 8 which

Uint16 SecureCRCCalcZ1(Uint16 corresponds to length options of 32, 0xXXXX : Returns the number of
len_id, Uint16 *dst, Uint16 *src) 64, 128, 256, 512, 1024, 2048, or 16-bit words CRC'd
4096 16-bit words

dst : The destination memory 0x0000 : Indicates one of the

CPU1, CPU2, address for resulting CRC following: Invalid length option;
CM Source address isn't modulo of
src : The source memory address to length value; Destination address
begin CRC calculation isn't within secure RAM; CRC size
Uint16 SecureCRCCalcZ2(Uint16 crosses over flash sector or RAM
size, Uint16 *dst, Uint16 *src) block boundary; The source and
destination memory don't belong to
the same zone; On CM, CRCLOCK
is enabled

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The calculate CMAC (Cipher-based Message Authentication Code) function calculates a CMAC tag
for a specified memory range using the user set CMAC key in OTP and returns pass/failure depending if
the calculated tag matches the golden tag. The memory address range provided must align to a 128-bit
boundary (split evenly into 128-bit blocks). If this requirement is not met, the function will return a status
indicating a boundary violation. When using the CM CMAC function, there is an additional requirement
that the CM must be running in privileged mode.
For generating the secure flash golden CMAC tag for CPU1 or CPU2, refer to the TMS320C28x Assembly
Language Tools User’s Guide within section Using Secure Flash Boot on TMS320F2838x Devices for
instructions.
For generating the secure flash golden CMAC tag for CM, refer to the ARM Assembly Language Tools
v19.6.0.STS, within section Using Secure Flash Boot on TMS320F2838x Devices for instructions.
The 128-bit golden CMAC tag:
• Must be stored inside of the memory address range that the calculation is performed on.
• Another golden CMAC tag (from a different memory address range that is being authenticated) can't
be nested inside a different CMAC authentication memory address range. (For example, a CMAC on
addresses 0x1000 to 0x2000 can't contain the golden CMAC tag for memory address ranges 0x4000
to 0x5000)
• The starting address of the golden CMAC tag must align to a 32-bit boundary, such as 0x80002 on
CPU1/CPU2 or 0x200004 on the CM.
• The CMAC calculation will treat the memory addresses containing the golden tag as all ones.

NOTE: If calling this function, without running the secure flash boot mode, then a dummy load must
be performed for the Z1 OTP CMACKEY before calling the function. Additionally, the flash
data caching should be disabled before performing the dummy load and then the flash data
caching can be re-enabled after the dummy load.

Table 5-65. Secure Flash CMAC Calculation Function

CPU Function Prototype Function Parameters Function Return Value
startAddress : The starting memory 0xFFFFFFFF : The calculated
address for the calculation CMAC tag doesn't match the golden
(Example: 0x80000) tag (failure)
uint32_t
endAddress : The ending memory 0xA5A5A5A5 : The memory address
CPU1BROM_calculateCMAC(uint32_t
CPU1 address for the calculation range isn't aligned to a 128-bit
startAddress, uint32_t endAddress,
(Example: 0x82000) boundary or length is zero
uint32_t tagAddress)
tagAddress : The starting memory
0x00000000 : The calculated CMAC
address of where the golden CMAC
tag matches the golden tag (pass)
tag is stored. (Example: 0x80002)
startAddress : The starting memory 0xFFFFFFFF : The calculated
address for the calculation CMAC tag doesn't match the golden
(Example: 0x80000) tag (failure)
uint32_t
endAddress : The ending memory 0xA5A5A5A5 : The memory address
CPU2BROM_calculateCMAC(uint32_t
CPU2 address for the calculation range isn't aligned to a 128-bit
startAddress, uint32_t endAddress,
(Example: 0x82000) boundary or length is zero
uint32_t tagAddress)
tagAddress : The starting memory
0x00000000 : The calculated CMAC
address of where the golden CMAC
tag matches the golden tag (pass)
tag is stored. (Example: 0x80002)

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Table 5-65. Secure Flash CMAC Calculation Function (continued)

CPU Function Prototype Function Parameters Function Return Value
0xFFFFFFFF : The calculated
CMAC tag doesn't match the golden
tag (failure)
startAddress : The starting memory
address for the calculation
(Example: 0x200000)
0xA5A5A5A5 : The memory address
range isn't aligned to a 128-bit
boundary or length is zero
endAddress : The ending memory
uint32_t
address for the calculation
CMBROM_calculateCMAC(uint32_t
CM (Example: 0x200000)
startAddress, uint32_t endAddress,
uint32_t tagAddress) 0x5A5A5A5A : The CM isn't running
in privileged mode
tagAddress : The starting memory
address of where the golden CMAC
tag is stored. (Example: 0x200004)
0xE1E1E1E1: The CM AES engine
timed out. AES engine may not be
working as expected

0x00000000 : The calculated CMAC

tag matches the golden tag (pass)

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5.7.10 Clock Initializations

During boot-up, the boot ROM initializes the device clocking, depending upon the reset source, to assist in
faster boot time response. Clock configurations are performed by the boot ROM code only for POR and
XRS reset types. For all other resets, the boot ROM starts executing with the clocks that were already set
up before reset.

NOTE: Only CPU1 performs clock configurations during boot up. CPU1 application configures
clocks for CPU2 and CM before releasing them from reset. Refer to Section 5.7.2 for more
details.
If the PLL is used during the CPU1 boot process, it will be bypassed by the boot ROM code
before branching to the user application.

Table 5-66. CPU1 Boot Clock Sources

Source Frequency Description
INTOSC2 10 MHz Default clock source
Set as clock source if missing clock is detected at power up or
INTOSC1 10 MHz
right after device reset
Enabled only as part of MPOST boot flow. PLL is bypassed and
SYSPLL 110MHz, 80MHz, or 60MHz disabled after memory test has completed. See more details
regarding enabling MPOST in Section 5.7.1.1.
SYSPLL = 180MHz Enabled only as part of USB Bootloader. Both PLLs are
SYSPLL and AUXPLL
AUXPLL = 60MHz bypassed and disabled after the bootloader actions complete.

Table 5-67. CPU1 Clock State After Boot

Reset Source Clock State
1. Using INTOSC2
POR/XRS
2. System clock divider set to /1
All other Resets Maintain clocks setup before device reset.

5.7.11 Boot Status information

Boot ROM keeps a record of the various actions and events that occur during boot ROM execution. The
reason for this is because NMI and other exceptions are enabled by default in the device and must be
handled accordingly. Boot ROM stores the boot status information in a RAM location so that the user
application can read this boot status and take the necessary actions per application’s needs to handle
these events.

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5.7.11.1 CPU1 Booting Status

CPU1 boot ROM health and booting status is written to a 32-bit address in M0RAM. This status is cleared
on a POR or XRS reset. The previous status is retained on any other reset. For example, a user should
clear the status before performing a debugger device reset in order to view the latest boot ROM actions
reflected in the status.

Table 5-68. CPU1 Boot Status Address

Description Address
CPU1 Boot ROM Status 0x0000 0002

Table 5-69. CPU1 Boot Status Bit Fields

Bit Description
31 CPU1 Boot ROM has finished running
30 Missing clock NMI occurred
29 RAM Uncorrectable Error NMI or ROM Parity Error occurred
28 Flash Uncorrectable Error NMI occurred
27 HWBIST NMI occurred
26 PIE Vector NMI occurred
25 RL NMI occurred
24 PIE Mismatch occurred
23 ITRAP occurred
22 ERAD NMI occurred
21 EtherCAT NMI occurred
20 MCAN NMI occurred
19 SYSPLL or AUXPLL failed to enable
18 MPOST (Memory Power On Self-Test) Complete
17 RAM Initialization Complete
16 DCSM Initialization Complete
15 HWBIST Reset Handled
14 POR Reset Handled
13 XRS Reset Handled
12 All Resets Handled
11:8 Not Used
0x0 = Invalid / No Status set yet
0x1 = CPU1 Boot ROM has started running
0x2 = Running Flash Boot
0x3 = Running Secure Flash Boot
0x4 = Running Parallel Boot
0x5 = Running RAM Boot
7:0
0x6 = Running SCI Boot
0x7 = Running SPI Boot
0x8 = Running I2C Boot
0x9 = Running CAN Boot
0xA = Running USB Boot
0xB = Running Wait Boot

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5.7.11.2 CPU2 Booting Status

CPU2 boot ROM health and booting status is written to a 32-bit address in M0RAM. This status is cleared
on every CPU2 reset. Additionally, a copy of the status is written to CPU2TOCPU1IPCBOOTSTS for
CPU1 to have access to CPU2's boot status.

Table 5-70. CPU2 Boot ROM Status Address

Description Address
CPU2 Boot ROM Status 0x0000 0002

Table 5-71. CPU2 Boot Status Bit Fields

Bit Description
31 CPU2 Boot ROM has finished running
30 Missing clock NMI occurred
29 RAM Uncorrectable Error NMI or ROM Parity Error occurred
28 Flash Uncorrectable Error NMI occurred
27 HWBIST NMI occurred
26 PIE Vector NMI occurred
25 RL NMI occurred
24 PIE Mismatch occurred
23 ITRAP occurred
22 ERAD NMI occurred
21 Secure Flash Boot CMAC returned failure
20 Not Used
Invalid length specified in CPU1TOCPU2IPCBOOTMODE for IPC message RAM
19
copy length
18 Invalid (or missing configuration) in CPU1TOCPU2IPCBOOTMODE
17 RAM Initialization Complete
16 Not Used
15 HWBIST Reset Handled
14 POR Reset Handled
13 XRS Reset Handled
12 All Resets Handled
11:8 Not Used
0x0 = Invalid / No Status set yet
0x1 = CPU2 Boot ROM has started running
0x2 = Running Flash Boot
0x3 = Running Secure Flash Boot
7:0 0x4 = Running IPC Message Copy to RAM Boot
0x5 = Running RAM Boot
0x6 = Running User OTP Boot
0x7 = Running Wait Boot
0x8 = Waiting for CPU1 to set CPU1TOCPU2IPCFLG0 to allow CPU2 to start booting

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5.7.11.3 CM Booting Status

CM boot ROM health and booting status is written to a 32-bit address in S0RAM. This status is cleared on
every CM reset. Additionally, a copy of the status is written to CMTOCPU1IPCBOOTSTS for CPU1 to
have access to the CM's boot status.

Table 5-72. CM Boot ROM Status Address

Description Address
CM Boot ROM Status 0x2000 0000

Table 5-73. CM Boot Status Bit Fields

Bit Description
31 CM Boot ROM has finished running
30 Missing clock NMI occurred
29 RAM Uncorrectable Error NMI or ROM Parity Error occurred
28 Flash Uncorrectable Error NMI occurred
27 MCAN NMI occurred
26 Windowed Watchdog NMI occurred
25 An EtherCAT NMI occurred
24 Not Used
23 Hard Fault occurred
22 Unassigned interrupt occurred
21 Secure Flash Boot CMAC returned failure
20 Not Used
Invalid length specified in CPU1TOCMIPCBOOTMODE for IPC message RAM copy
19
length
18 Invalid (or missing configuration) in CPU1TOCMIPCBOOTMODE
17 RAM Initialization Complete
16:15 Not Used
14 POR Reset Handled
13 Not Used
12 All Resets Handled
11:8 Not Used
0x0 = Invalid / No Status set yet
0x1 = CM Boot ROM has started running
0x2 = Running Flash Boot
0x3 = Running Secure Flash Boot
7:0 0x4 = Running IPC Message Copy to RAM Boot
0x5 = Running RAM Boot
0x6 = Running User OTP Boot
0x7 = Running Wait Boot
0x8 = Waiting for CPU1 to set CPU1TOCMIPCFLG0 to allow CM to start booting

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5.7.11.4 Boot Mode and MPOST Status

Once the boot mode is decoded during the boot flow for each core, the boot mode value is written to
RAM. Additionally, on CPU1, when running the MPOST (Memory Power On Self-Test), the test result is
written to RAM.

Table 5-74. Boot Mode and MPOST Status Addresses

Description Address
CPU1 Boot Mode 0x0000 0004
CPU2 Boot Mode 0x0000 0004
CM Boot Mode 0x2000 0004
MPOST Result
0x0000 0006
(CPU1 Only)

5.7.12 ROM Version

The ROM revision and release date information is stored at the ROM locations specified in this section.
Reading a revision number value of “0x100” represents version “1.0”, “0x101” represents version “1.1”,
and so on. Reading a revision date value of “0x0916” represents “09/16” or “September 2016”.

Table 5-75. Boot ROM Version Information for CPU1

Start Address End Address Contents Silicon Revision 0 Silicon Revision A
Values Values
0x003F FF7A 0x003F FF7A Revision Number 0x0100 0x0200
0x003F FF7B 0x003F FF7B Revision Date 0x0418 0x0819

Table 5-76. Boot ROM Version Information for CPU2

Start Address End Address Contents Silicon Revision 0 Silicon Revision A
Values Values
0x003F FF7A 0x003F FF7A Revision Number 0x0100 0x0100
0x003F FF7B 0x003F FF7B Revision Date 0x0418 0x0418

Table 5-77. Boot ROM Version Information for CM

Start Address End Address Contents Silicon Revision 0 Silicon Revision A
Values Values
0x0000 0140 0x0000 0141 Revision Number 0x0100 0x0200
0x0000 0142 0x0000 0143 Revision Date 0x0418 0x0819

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5.8 Application Notes for Using the Bootloaders

5.8.1 Boot Data Stream Structure

This section details the data transfer protocols or stream structures that allow boot data transfer between
boot ROM and host device. This data transfer protocol is compatible to the respective bootloaders on
C2000 devices.

5.8.1.1 Bootloader Data Stream Structure

The following table and associated examples show the structure of the data stream incoming to the
bootloader. The basic structure is the same for all the bootloaders and is based on the C54x source data
stream generated by the C54x hex utility. The C28x hex utility (hex2000.exe) has been updated to support
this structure. The hex2000.exe utility is included with the C2000 code generation tools. All values in the
data stream structure are in hex. Refer to The C2000 Hex Utility for more details on using the C28x hex
utility to convert a project to this format.
The first 16-bit word in the data stream is known as the key value. The key value is used to tell the
bootloader the width of the incoming stream: 8 or 16 bits. Note that not all bootloaders will accept both 8
and 16-bit streams. Please refer to the detailed information on each loader for the valid data stream width.
For an 8-bit data stream, the key value is 0x08AA and for a 16-bit stream it is 0x10AA. If a bootloader
receives an invalid key value, then the load is aborted.
The next eight words are used to initialize register values or otherwise enhance the bootloader by passing
values to it. If a bootloader does not use these values then they are reserved for future use and the
bootloader simply reads the value and then discards it. Currently only the SPI and I2C and parallel
bootloaders use these words to initialize registers.
The tenth and eleventh words comprise the 22-bit entry point address. This address is used to initialize
the PC after the boot load is complete. This address is most likely the entry point of the program
downloaded by the bootloader.
The twelfth word in the data stream is the size of the first data block to be transferred. The size of the
block is defined as 8-bit data stream format. For example, to transfer a block of 20 8-bit data values from
an 8-bit data stream, the block size would be 0x000A to indicate 10 16-bit words.
The next two words tell the loader the destination address of the block of data. Following the size and
address will be the 16-bit words that makeup that block of data.
This pattern of block size/destination address repeats for each block of data to be transferred. Once all the
blocks have been transferred, a block size of 0x0000 signals to the loader that the transfer is complete. At
this point the loader will return the entry point address to the calling routine which in turn will cleanup and
exit. Execution will then continue at the entry point address as determined by the input data stream
contents.

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Table 5-78. LSB/MSB Loading Sequence in 8-Bit Data Stream

Byte Contents
LSB (First Byte of 2) MSB (Second Byte of 2)
1 2 LSB: AA (KeyValue for memory width = 8 bits) MSB: 08h (KeyValue for memory width = 8 bits)
3 4 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
5 6 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
7 8 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
... ... ... ...
... ... ... ...
17 18 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
19 20 LSB: Upper half of Entry point PC[23:16] MSB: Upper half of entry point PC[31:24] (Always 0x00)
21 22 LSB: Lower half of Entry point PC[7:0] MSB: Lower half of Entry point PC[15:8]
23 24 LSB: Block size in words of the first block to load. If the block MSB: block size
size is 0, this indicates the end of the source program.
Otherwise another block follows. For example, a block size of
0x000A would indicate 10 words or 20 bytes in the block.
25 26 LSB: MSW destination address, first block Addr[23:16] MSB: MSW destination address, first block Addr[31:24]
27 28 LSB: LSW destination address, first block Addr[7:0] MSB: LSW destination address, first block Addr[15:8]
29 30 LSB: First word of the first block being loaded MSB: First word of the first block being loaded
... ... ... ...
... ... ... ...
. . LSB: Last word of the first block to load MSB: Last word of the first block to load
. . LSB: Block size of the second block MSB: Block size of the second block
. . LSB: MSW destination address, second block Addr[23:16] MSB: MSW destination address, second block Addr[31:24]
. . LSB: LSW destination address, second block Addr[7:0] MSB: LSW destination address, second block Addr[15:8]
. . LSB: First word of the second block being loaded MSB: First word of the second block being loaded
... ... ... ...
... ... ... ...
. . LSB: Last word of the second block MSB: Last word of the second block
. . LSB: Block size of the last block MSB: Block size of the last block
. . LSB: MSW of destination address of last block Addr[23:16] MSB: MSW destination address, last block Addr[31:24]
. . LSB: LSW destination address, last block Addr[7:0] MSB: LSW destination address, last block Addr[15:8]
. . LSB: First word of the last block being loaded MSB: First word of the last block being loaded
... ... ... ...
... ... ... ...
. . LSB: Last word of the last block MSB: Last word of the last block
n n+1 LSB: 00h MSB: 00h - indicates the end of the source

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Example 5-2. Data Stream Structure 8-bit

AA 08 ; 0x08AA 8-bit key value

00 00 00 00 ; 8 reserved words
00 00 00 00
00 00 00 00
00 00 00 00
3F 00 00 80 ; 0x003F8000 EntryAddr, starting point after boot load completes
05 00 ; 0x0005 - First block consists of 5 16-bit words
3F 00 10 90 ; 0x003F9010 - First block will be loaded starting at 0x3F9010
01 00 ; Data loaded = 0x0001 0x0002 0x0003 0x0004 0x0005
02 00
03 00
04 00
05 00
02 00 ; 0x0002 - 2nd block consists of 2 16-bit words
3F 00 00 80 ; 0x003F8000 - 2nd block will be loaded starting at 0x3F8000
00 77 ; Data loaded = 0x7700 0x7625
25 76
00 00 ; 0x0000 - Size of 0 indicates end of data stream

After load has completed the following memory values will have been initialized as follows:

Location Value
0x3F9010 0x0001
0x3F9011 0x0002
0x3F9012 0x0003
0x3F9013 0x0004
0x3F9014 0x0005
0x3F8000 0x7700
0x3F8001 0x7625
PC Begins execution at 0x3F8000

5.8.2 The C2000 Hex Utility

To use the features of the bootloader, you must generate a data stream and boot table as described in
Section 5.8.1.1. The hex conversion utility tool, included with the 28x code generation tools, can generate
the required data stream including the required boot table. This section describes the hex2000 utility. An
example of a file conversion performed by hex2000 is described in Example 5-3.
The hex utility supports creation of the boot table required for the SCI, SPI, I2C, CAN, and parallel I/O
loaders. That is, the hex utility adds the required information to the file such as the key value, reserved
bits, entry point, address, block start address, block length and terminating value. The contents of the boot
table vary slightly depending on the boot mode and the options selected when running the hex conversion
utility. The actual file format required by the host (ASCII, binary, hex, and so on) will differ from one
specific application to another and some additional conversion may be required.
To build the boot table, follow these steps:
1. Assemble or compile the code.
This creates the object files that will then be used by the linker to create a single output file.
2. Link the file.
The linker combines all of the object files into a single output file in common object file format (ELF).
The specified linker command file is used by the linker to allocate the code sections to different
memory blocks. Each block of the boot table data corresponds to an initialized section in the ELF file.
Uninitialized sections are not converted by the hex conversion utility. The following options may be
useful:

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The linker -m option can be used to generate a map file. This map file will show all of the sections that
were created, their location in memory and their length. It can be useful to check this file to make sure
that the initialized sections are where you expect them to be.
The linker -w option configures the linker to show if the linker assigned a section to a memory region
automatically. For example, if you have a section in your code called .TI.ramfunc.
3. Run the hex conversion utility.
Choose the appropriate options for the desired boot mode and run the hex conversion utility to convert
the ELF file produced by the linker to a boot table.
See the TMS320C28x Assembly Language Tools User's Guide and the TMS320C28x Optimizing C/C++
Compiler User's Guide for more information on the compiling and linking process.
Table 5-79 summarizes the hex conversion utility options available for the bootloader. See the
TMS320C28x Assembly Language Tools User's Guide for a detailed description of the hex2000
operations used to generate a boot table. Updates will be made to support the I2C boot. See the Codegen
release notes for the latest information.

Table 5-79. Boot Loader Options

Option Description
-boot Convert all sections into bootable form (use instead of a SECTIONS directive)
-sci8 Specify the source of the bootloader table as the SCI-A port, 8-bit mode
-spi8 Specify the source of the bootloader table as the SPI-A port, 8-bit mode
-gpio8 Specify the source of the bootloader table as the GPIO port, 8-bit mode
-bootorg value Specify the source address of the bootloader table
-lospcp value Specify the initial value for the LOSPCP register. This value is used only for the spi8 boot table format
and ignored for all other formats. If the value is greater than 0x7F, the value is truncated to 0x7F.
-spibrr value Specify the initial value for the SPIBRR register. This value is used only for the spi8 boot table format and
ignored for all other formats. If the value is greater than 0x7F, the value is truncated to 0x7F.
-e value Specify the entry point at which to begin execution after boot loading. The value can be an address or a
global symbol. This value is optional. The entry point can be defined at compile time using the linker -e
option to assign the entry point to a global symbol. The entry point for a C program is normally _c_int00
unless defined otherwise by the -e linker option.
-i2c8 Specify the source of the bootloader table as the I2C-A port, 8-bit
-i2cpsc value Specify the value for the I2CPSC register. This value will be loaded and take effect after all I2C options
are loaded, prior to reading data from the EEPROM. This value will be truncated to the least significant
eight bits and should be set to maintain an I2C module clock of 7-12 MHz.
-i2cclkh value Specify the value for the I2CCLKH register. This value will be loaded and take effect after all I2C options
are loaded, prior to reading data from the EEPROM.
-i2cclkl value Specify the value for the I2CCLKL register. This value will be loaded and take effect after all I2C options
are loaded, prior to reading data from the EEPROM.

Example 5-3. HEX2000.exe Command Syntax

C: HEX2000 GPIO34TOG.OUT -boot -gpio8 -a

Where:
- boot Convert all sections into bootable form.
- gpio8 Use the GPIO in 8-bit mode data format. The eCAN uses the same data format as the GPIO in 8-
bit mode.
- a Select ASCII-Hex as the output format.

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 Chapter 6
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Dual Code Security Module (DCSM)

This chapter explains the dual code security module.

Topic ........................................................................................................................... Page

6.1 Introduction ..................................................................................................... 737

6.2 Functional Description ...................................................................................... 737
6.3 Flash and OTP Erase/Program ........................................................................... 744
6.4 Secure Copy Code ............................................................................................ 744
6.5 SecureCRC ...................................................................................................... 745
6.6 CSM Impact on Other On-Chip Resources ........................................................... 745
6.7 Incorporating Code Security in User Applications ................................................ 747
6.8 DCSM Registers ............................................................................................... 752

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6.1 Introduction
The dual code security module (DCSM) is a security feature incorporated in this device. It prevents access
and visibility to on-chip secure memories (and other secure resources) by unauthorized persons. It also
prevents duplication and reverse-engineering of proprietary code. The term “secure” means that access to
on-chip secure memories and resources is blocked. The term “unsecure” means that access is allowed;
that is, the contents of the memory could be read by any means (for example, through a debugging tool
such as Code Composer Studio™ IDE.
There are two security zones, Zone1 (Z1) and Zone2 (Z2). Unlike earlier C2000 devices where each CPU
subsystem had two security zones, on this device, both security zones are shared by each CPU
subsystem. This means secure resources from each CPU subsystem are allocated to Zone1 or Zone2. All
the security configurations are controlled by the CPU1 subsystem only (programmed in CPU1 USER
OTP). Other CPU subsystems have only read access to these configurations via their own memory map
registers.

6.2 Functional Description

The security module restricts the CPU access to on-chip secure memory and resources without
interrupting or stalling CPU execution. When a read occurs to a secure memory location, the read returns
a zero value and CPU execution continues with the next instruction. This, in effect, blocks read and write
access to secure memories through the JTAG port or external peripherals.
The code security mechanism offers protection for two zones, Zone1 (Z1) and Zone2 (Z2). The security
mechanism for both the zones is identical. Each zone has its own dedicated secure resource and
allocated secure resource. The following are different secure resources available on this device:
• OTP: Each zone has its own dedicated secure OTP (USER OTP) on CPU1 subsystem. This contains
the security configurations for the individual zone. If a zone is secure, its USER OTP content (including
CSM passwords) can be read (execution not allowed) only if the zone is unlocked using the password
match flow (PMF).
• RAM: All Dx and LSx RAMs on C28x and C0/C1 RAMs on the Connectivity Manager(CM) can be
secure RAM on this device. On this device IPC MSG RAMs between different subsystems can also be
configured to be secure RAM. This enables secure message exchange between CPU subsystems.
These RAMs can be allocated to either zone by configuring the respective GRABRAM locations in the
CPU1 USER OTP.
• Flash Sectors: Flash sectors of each CPU subsystems can be made secure on this device. Each
Flash sector can be allocated to either zone by configuring the respective GRABSECT locations in the
CPU1 USER OTP.
• Secure ROM: This device also has secure ROM on each CPU subsystem which is EXEONLY-
protected. These ROM contains specific function for the user, provided by TI.
Table 6-1 shows the status of a RAM block/Flash sector based on the configuration in the
GRABRAM/GRABSECT register.
The security of each zone is ensured by its own 128-bit (four 32-bit words) password (CSM password).
The password for each zone is stored in CPU1 USER OTP. A zone can be unsecured by executing the
password match flow (PMF), described in Section 6.7.4.
There are three types of accesses: data/program reads, JTAG access, and instruction fetches (calls,
jumps, code executions, ISRs). Instruction fetches are never blocked. JTAG accesses are always blocked
when a memory is secure. Data reads to a secure memory are always blocked unless the program is
executing from a memory which belongs to the same zone. Data reads to unsecure memory are always
allowed. Table 6-2 shows the levels of security.

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Table 6-1. RAM/Flash Status

Zone 1 Zone 2
GRAMRAMx/GRABSECTx Bits GRAMRAMx/GRABSECT Bits Ownership and Accessibility
01 10 RAM block/Flash Sector belongs to Zone1
01 11 (1) RAM block/Flash Sector belongs to Zone1
10 01 RAM block/Flash Sector belongs to Zone2
11 (2) 01 RAM block/Flash Sector belongs to Zone2
10 10 RAM block/Flash Sector is unsecure
11 (2) 11 (1) RAM block/Flash Sector is unsecure
11 11 RAM block/Flash Sector inaccessible if either of the zone
is secure (CSM passwords are programmed). User should
never leave these values default (11) if CSM passwords
are programmed for even one zone.
(1)
Zone2 must be unsecure. Assumption in this case is that user is not using Zone2 so none of the fields, including passwords, in Zone2
USER OTP are programmed by user hence Zone2 will always be unsecure.
(2)
Zone1 must be unsecure. Assumption in this case is that user is not using Zone1 so none of the fields, including passwords, in Zone1
USER OTP are programmed by user hence Zone1 will always be unsecure.

NOTE: You should never program any other values in these fields. Failing any these conditions for a
RAM block/Flash sector will make that RAM block/Flash sector inaccessible.

Table 6-2. Security Levels

PMF Executed With Operating Mode of the
Correct Password? Zone Program Fetch Location Security Description
No Secure Outside secure memory Only instruction fetches by the CPU are
allowed to secure memory. In other words,
code can still be executed, but not read.
No Secure Inside secure memory CPU has full access (except for
EXEONLY memories where read is not
allowed). JTAG port cannot read the
secured memory contents.
Yes Unsecure Anywhere Full access for CPU and JTAG port to
secure memory of that zone.

6.2.1 CSM Passwords

Unlike earlier C2000 devices, on this device ALL_1 value
(0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF) for CSM password for a zone does not unsecure
the zone. Instead, if for any zone the CSM password values get loaded as ALL_1 from USER OTP, the
device will be in BLOCKED state. Due to this reason TI will program a few bits in the second 32-bit
password value (ZxOTP_CSMPSWD1) in every zone select block of each zone with value ‘0’. The default
value for this password location is chosen in a manner that the respective ECC value remains ALL_1. Due
to this, the CSMPSWD1 value programmed by TI for every zone select block is different. Please see
Table 6-3 for ZxOTP_CSMPSWD1 value, programmed by TI on every device. Since ECC is not
programmed, the user will be able to change this value by flipping the bits which are ‘1’ to ‘0’ but leaving
the ones which are already programmed by TI as ‘0’. BOOTROM code will write the default password
value into the KEYx register to unlock the device as part of device initialization sequence.
If the password locations of a zone have all 128 bits as zeros (ALL_0), that zone becomes permanently
secure (LOCKED state), regardless of the contents of the CSMKEYx registers which means the zone
cannot be unlocked using PMF, the password match flow described in Section 6.7.4. Therefore, the user
should never use ALL_0 as password. A password of ALL_0 will prevent debug of secure code or
reprogramming the Flash sectors. CSMKEYx registers are user-accessible registers that are used to
unsecure the zones.

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Table 6-3. Default Value of ZxOTP (Programmed by TI)

Zone Select Block Zone1 USER OTP Zone2 USER OTP
Address Value Address Value
JLM_ENABLE 0x00078006 0xffff000f NA NA
(JTAGLOCK)
PSWDLOCK 0x00078010 0xfb7fffff 0x00078210 0x1f7fffff
CRCLOCK 0x00078012 0x7fffffff 0x00078212 0x3fffffff
JTAGPSWDH0 0x00078014 0x4bffffff NA NA
JTAGPSWDH1 0x00078016 0x3fffffff NA NA
Zone_Select_Block0 0x00078022 (CSMPSWD1) 0x4d7fffff 0x00078222 (CSMPSWD1) 0x1f7fffff
Zone_Select_Block0 0x0007803e (JTAGPSWDL1) 0x2bffffff NA NA
Zone_Select_Block1 0x00078042 (CSMPSWD1) 0x5f7fffff 0x00078242 (CSMPSWD1) 0xe57fffff
Zone_Select_Block1 0x0007805e (JTAGPSWDL1) 0x27ffffff NA NA
Zone_Select_Block2 0x00078062 (CSMPSWD1) 0x1dffffff 0x00078262 (CSMPSWD1) 0x4fffffff
Zone_Select_Block2 0x0007807e (JTAGPSWDL1) 0x7b7fffff NA NA
Zone_Select_Block3 0x00078082 (CSMPSWD1) 0xaf7fffff 0x00078282 (CSMPSWD1) 0xe37fffff
Zone_Select_Block3 0x0007809e (JTAGPSWDL1) 0xc9ffffff NA NA
Zone_Select_Block4 0x000780a2 (CSMPSWD1) 0x1bffffff 0x000782a2 (CSMPSWD1) 0x57ffffff
Zone_Select_Block4 0x000780be (JTAGPSWDL1) 0x7d7fffff NA NA
Zone_Select_Block5 0x000780c2 (CSMPSWD1) 0x17ffffff 0x000782c2 (CSMPSWD1) 0x5bffffff
Zone_Select_Block5 0x000780de (JTAGPSWDL1) 0x6f7fffff NA NA
Zone_Select_Block6 0x000780e2 (CSMPSWD1) 0xbd7fffff 0x000782e2 (CSMPSWD1) 0xf17fffff
Zone_Select_Block6 0x000780fe (JTAGPSWDL1) 0x33ffffff NA NA
Zone_Select_Block7 0x00078102 (CSMPSWD1) 0x9f7fffff 0x00078302 (CSMPSWD1) 0x3b7fffff
Zone_Select_Block7 0x0007811e (JTAGPSWDL1) 0x0fffffff NA NA
Zone_Select_Block8 0x00078122 (CSMPSWD1) 0x2bffffff 0x00078322 (CSMPSWD1) 0x8fffffff
Zone_Select_Block8 0x0007813e (JTAGPSWDL1) 0xbb7fffff NA NA
Zone_Select_Block9 0x00078142 (CSMPSWD1) 0x27ffffff 0x00078342 (CSMPSWD1) 0x6bffffff
Zone_Select_Block9 0x0007815e (JTAGPSWDL1) 0x5f7fffff NA NA
Zone_Select_Block10 0x00078162 (CSMPSWD1) 0x7b7fffff 0x00078362 (CSMPSWD1) 0x377fffff
Zone_Select_Block10 0x0007817e (JTAGPSWDL1) 0x1dffffff NA NA
Zone_Select_Block11 0x00078182 (CSMPSWD1) 0xc9ffffff 0x00078382 (CSMPSWD1) 0x9bffffff
Zone_Select_Block11 0x0007819e (JTAGPSWDL1) 0xaf7fffff NA NA
Zone_Select_Block12 0x000781a2 (CSMPSWD1) 0x7d7fffff 0x000783a2 (CSMPSWD1) 0x2f7fffff
Zone_Select_Block12 0x000781be (JTAGPSWDL1) 0x1bffffff NA NA
Zone_Select_Block13 0x000781c2 (CSMPSWD1) 0x6f7fffff 0x000783c2 (CSMPSWD1) 0xcb7fffff
Zone_Select_Block13 0x000781de (JTAGPSWDL1) 0x17ffffff NA NA
Zone_Select_Block14 0x000781e2 (CSMPSWD1) 0x33ffffff 0x000783e2 (CSMPSWD1) 0x97ffffff
Zone_Select_Block14 0x000781fe (JTAGPSWDL1) 0xbd7fffff

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6.2.2 Emulation Code Security Logic (ECSL)

In addition to the CSM, the emulation code security logic (ECSL) has been implemented using a 64-bit
password (part of existing CSM password) for each zone to prevent unauthorized users from stepping
through secure code. A halt in secure code while the emulator is connected will trip the ECSL and break
the emulation connection. To allow emulation of secure code, while maintaining the CSM protection
against secure memory reads, the user must write the correct 64-bit password into the CSMKEY (0/1)
registers, which matches the password value stored in the USER OTP of that zone. This will disable the
ECSL for the specific zone.
When initially debugging a device with the password locations in OTP programmed (secured), the
emulator takes some time to take control of the CPU. During this time, the CPU will start running and may
execute an instruction that performs an access to a protected ECSL area and if the CPU is halted when
the program counter (PC) is pointing to a secure location, the ECSL will trip and cause the emulator
connection to be broken.
The solution to this problem is:
• Use the Wait Boot Mode boot option. In this mode, the CPU will be in a loop and hence will not jump to
the user application code. Using this BOOTMODE, the user can connect to CCS and debug the code.

6.2.3 CPU Secure Logic

The CPU Secure Logic (CPUSL) on this device prevents a hacker from reading the CPU registers in a
watch window while code is running in a secure zone. All accesses to CPU registers when the PC points
to a secure location are blocked by this logic. The only exception to this is read access to the PC. It is
highly recommended not to write into the CPU register in this case, because proper code execution may
get affected. If the CSM is unlocked using the CSM password match flow, the CPUSL logic also gets
disabled.

6.2.4 Execute-Only Protection

To achieve a higher level of security on secure Flash sectors and RAM blocks that store critical user code
(instruction opcodes), the Execute-Only protection feature is provided. When the Execute-Only protection
is turned on for any secure Flash sector or RAM block, data reads to that Flash sector or RAM block are
disallowed from any code (even from secure code). Execute-only protection for a Flash sector and RAM
block can be turned on by configuring the bit field associated for that particular sector/RAM block in the
zone's (which has ownership of that sector/RAM block) EXEONLYSECT and EXEONLYRAM register,
respectively.

6.2.5 Password Lock

The password locations in USER OTP for each zone can be locked by programming the zone’s
PSWDLOCK field with any value other than “1111” (0xF) at the PSWDLOCK location in OTP. Until the
passwords of a zone are locked, password locations will not be secure and can be read from the
debugger as well as code running from non-secure memory. This feature can be used by the user to avoid
accidental locking of the zone while programming the Flash sectors during the software development
phase. On a fresh device the value for password lock fields for all zones at the PSWDLOCK location in
OTP will be “1111” which means the password for all zones will be unlocked.

NOTE: Password unlock only makes password locations non-secure. All other secure memories
remains secure as per security settings. Since password locations are non-secure, anyone
can read the password and make the zone un-secure by running through PMF, user must
program PSWDLOCK locations to lock the password before sending the device in field.

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6.2.6 JTAGLOCK
Sometimes you want to disable the JTAG access on a device to avoid any debug access to it. This can be
done by using the JTAGLOCK feature on this device. You need to follow a two step process to enable the
JTAGLOCK feature (both steps can be performed at the same time).
1. Program the JTAG passwords. This device has a 128-bit JTAG password that needs to be
programmed in Z1 USER OTP of CPU1. JTAG passwords are split into two parts, JTAGPSWDH and
JTAGPSWDL. JTAGPSWDH is part of Z1 USER OTP header and JTAGPSWDL is part of Z1 Zone
Select Block (ZSB). What this means is program JTAGPSWDH once and change the JTAGPSWDL
multiple times, if needed. Code Composer Studio has an integrated tool that you need to use to unlock
the JTAGLOCK on device.
2. After programming the JTAG passwords, you need to enable the JTAGLOCK module (JLM) by
programming bit [3:0] of Z1OTP_JLM_ENABLE with any value other than 0xF. It is recommended to
program all four bits with a value 0x0.

6.2.7 Link Pointer and Zone Select

For each of the two security zones, a dedicated OTP block exists on CPU1 that holds the configuration
related to zone’s security. The following are user programmable configurations:

• ZxOTP_LINKPOINTER1 • ZxOTP_CSMPSWD1
• ZxOTP_LINKPOINTER2 • ZxOTP_CSMPSWD2
• ZxOTP_LINKPOINTER3 • ZxOTP_CSMPSWD3
• Z1OTP_JLM_ENABLE • ZxOTP_GRABSECT1
• ZxOTP_GPREG1 • ZxOTP_GRABSECT2
• ZxOTP_GPREG2 • ZxOTP_GRABSECT3
• ZxOTP_GPREG3 • ZxOTP_GRABRAM1
• ZxOTP_GPREG4 • ZxOTP_GRABRAM2
• ZxOTP_PSWDLOCK • ZxOTP_GRABRAM3
• ZxOTP_CRCLOCK • ZxOTP_EXEONLYSECT1
• Z1OTP_JTAGPSWDH • ZxOTP_EXEONLYSECT2
• Z1OTP_CMACKEY • ZxOTP_EXEONLYRAM1
• ZxOTP_CSMPSWD0 • Z1OTP_JTAGPSWDL

Since OTP cannot be erased, the following configurations are placed in zone select blocks of each zone’s
OTP Flash of both the banks:

• ZxOTP_CSMPSWD0 • ZxOTP_GRABRAM1
• ZxOTP_CSMPSWD1 • ZxOTP_GRABRAM2
• ZxOTP_CSMPSWD2 • ZxOTP_GRABRAM3
• ZxOTP_CSMPSWD3 • ZxOTP_EXEONLYSECT1
• ZxOTP_GRABSECT1 • ZxOTP_EXEONLYSECT2
• ZxOTP_GRABSECT2 • ZxOTP_EXEONLYRAM1
• ZxOTP_GRABSECT3 • Z1OTP_JTAGPSWDL

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The location of the valid zone select block in OTP is decided based on the value of three 14-bit link
pointers (Zx-LINKPOINTERx) programmed in the OTP of each zone. All OTP locations except link
pointers and Z1OTP_JLM_ENABLE locations are protected with ECC. Since the link pointer locations are
not protected with ECC, three link pointers are provided that need to be programmed with the same value.
The final value of the link pointer is resolved in hardware, when a dummy read is done to all the link
pointers, by comparing all the three values (bit-wise voting logic). Since in OTP, a ‘1’ can be flipped by the
user to ‘0’ but ‘0’ can not be flipped to ‘1’ (no erase operation for OTP), the most significant bit position in
the resolved link pointer which is ‘0’, defines the valid base address for the zone select block. While
generating the final link pointer value, if the bit pattern is not one of those listed in Figure 6-1, the final link
pointer value becomes All_1 (0xFFFF_FFFF), which selects the Zone-Select-Block1 (also known as the
default zone select block).

Figure 6-1. Storage of Zone-Select Bits in OTP

Selected Zone1 ZSB Zone2 ZSB
Zx-LINKPOINTER
ZSB Address Address

32xxxxxxxxxxxxxxxxxx11111111111111 ZSB1 0x78020 0x78220

32xxxxxxxxxxxxxxxxxx11111111111110 ZSB2 0x78040 0x78240

32xxxxxxxxxxxxxxxxxx11111111111100 ZSB3 0x78060 0x78260

32xxxxxxxxxxxxxxxxxx11111111111000 ZSB4 0x78080 0x78280

32xxxxxxxxxxxxxxxxxx11111111110000 ZSB5 0x780a0 0x782a0

32xxxxxxxxxxxxxxxxxx11111111100000 ZSB6 0x780c0 0x782c0

32xxxxxxxxxxxxxxxxxx11111111000000 ZSB7 0x780e0 0x782e0

32xxxxxxxxxxxxxxxxxx11111110000000 ZSB8 0x78100 0x78300

32xxxxxxxxxxxxxxxxxx11111100000000 ZSB9 0x78120 0x78320

32xxxxxxxxxxxxxxxxxx11111000000000 ZSB10 0x78140 0x78340

32xxxxxxxxxxxxxxxxxx11110000000000 ZSB11 0x78160 0x78360

32xxxxxxxxxxxxxxxxxx11100000000000 ZSB12 0x78180 0x78380

32xxxxxxxxxxxxxxxxxx11000000000000 ZSB13 0x781a0 0x783a0

32xxxxxxxxxxxxxxxxxx10000000000000 ZSB14 0x781c0 0x783c0

32xxxxxxxxxxxxxxxxxx00000000000000 ZSB15 0x781e0 0x783e0

NOTE: Address locations for other security settings that are not part of Zone Select blocks can be
programmed only once; therefore, the user should program them towards end of the
development cycle.

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Figure 6-2. Location of Zone-Select Block Based on Link-Pointer

Zone2 OTP Flash
Zone1 OTP Flash
0x78200 Z2OTP_LINKPOINTER1
0x78000 Z1OTP_LINKPOINTER1
0x78202 Z2OTP_LINKPOINTER2
0x78002 Z1OTP_LINKPOINTER2
0x78204 Z2OTP_LINKPOINTER3
0x78004 Z1OTP_LINKPOINTER3
0x78206 Reserved
0x78006 Z1OTP_JLM_ENABLE
0x78208 Z2OTP_GPREG1
0x78008 Z1OTP_GPREG1 Zone Select Block (ZSB)
0x7820A Z2OTP_GPREG2
0x7800A Z1OTP_GPREG2
Address Offset 0x7820C Z2OTP_GPREG3
32-bit Content
0x7800C Z1OTP_GPREG3 (from ZSB Base)
0x7820E Z2OTP_GPREG4
0x7800E Z1OTP_GPREG4 0x0 ZxOTP_CSMPSWD0
0x78210 Z2OTP_PSWDLOCK
0x78010 Z1OTP_PSWDLOCK 0x2 ZxOTP_CSMPSWD1
0x78212 Z2OTP_CRCLOCK
0x78012 Z1OTP_CRCLOCK 0x4 ZxOTP_CSMPSWD2
0x78214 Reserved
0x78014 Z1OTP_JTAGPSWDH0 0x6 ZxOTP_CSMPSWD3
0x78216 Reserved
0x78016 Z1OTP_JTAGPSWDH1 0x8 ZxOTP_GRABSECT1
0x78218 Reserved
0x78018 Z1OTP_CMACKEY0 0xa ZxOTP_GRABSECT2
0x7821A Reserved
0x7801A Z1OTP_CMACKEY1 0xc ZxOTP_GRABSECT3
0x7821C Reserved
0x7801C Z1OTP_CMACKEY2 0xe ZxOTP_GRABRAM1
0x7821E Reserved
0x7801E Z1OTP_CMACKEY3 0x10 ZxOTP_GRABRAM2
Zone Select Block 1
Zone Select Block 1 0x78220
0x78020 0x12 ZxOTP_GRABRAM3 (32x16 Bits)
(32x16 Bits)
Zone Select Block 2
Zone Select Block 2 0x14 ZxOTP_EXEONLYSECT1 0x78240
0x78040 (32x16 Bits)
(32x16 Bits)
0x16 ZxOTP_EXEONLYSECT2

0x18 ZxOTP_EXEONLYRAM1
Zone Select Block 15
Zone Select Block 15 0x783E0
0x781E0 (32x16 Bits)
(32x16 Bits) 0x1a Reserved

0x1c ZxOTP_JTAGPSWDL0

0x1e ZxOTP_JTAGPSWDL1

NOTE: USER OTP is ECC protected. The user must program the ECC value while programming the
security setting in USER OTP. Failing to program the correct ECC value will cause the
device to be blocked permanently and the user will have to replace the device.

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6.2.8 C Code Example to Get Zone Select Block Addr for Zone1
unsigned long LinkPointer;
unsigned long *Zone1SelBlockPtr;
int Bitpos = 13;
int ZeroFound = 0;
// Read Z1-Linkpointer register of DCSM module.
LinkPointer = *(unsigned long *)0x5F000;
// Bits 31 to 15 as most-sigificant 0 are reserved LinkPointer options
LinkPointer = LinkPointer << 18;
while ((ZeroFound == 0) && (bitpos > -1))
{
if ((LinkPointer & 0x80000000) == 0)
{
ZeroFound = 1;
Zone1SelBlockPtr = (unsigned long *)(0x78000 + ((bitpos + 2)*32));
}
else
{
bitpos--;
LinkPointer = LinkPointer << 1;
}
}
if (ZeroFound == 0)
{
//Default in case there is no zero found.
Zone1SelBlockPtr = (unsigned long *)0x78020;
}

6.3 Flash and OTP Erase/Program

On this device, OTP as well as normal Flash, are secure resources. Each zone has its own dedicated
CPU1 OTP, whereas normal Flash sectors can be allocated to any zone based on the value programmed
in the GRABSECTx location in OTP. Each zone has its own 128bit CSM passwords. Read and write
accesses are not allowed to resources assigned to Z1 by code running from memory allocated to Z2 and
vice versa. Before programming any secure Flash sector the user must either unlock the zone to which
that particular sector belongs using PMF or execute the Flash programming code from secure memory
which belongs to the same zone. The same is the case for erasing any secure Flash sector. To program
the security settings in CPU1 OTP Flash, the user must unlock the CSM of the respective zone. Unless
the zone is unlocked, security settings in OTP Flash can not be updated. The OTP content cannot be
erased.
A semaphore mechanism is provided to avoid the program/erase conflict between Z1 and Z2. A zone
needs to grab this semaphore to successfully complete the erase/program operation on the secure Flash
sectors allocated to that zone. A semaphore can be grabbed by a zone by writing the appropriate value in
the SEM field of the FLSEM register. For further details of this field, see the register description.

6.4 Secure Copy Code

In some applications, the user may want to copy the code from secure Flash to secure RAM for better
performance. The user cannot do this for EXEONLY flash sectors because EXEONLY secure memories
cannot be read from anywhere. TI provides specific “Secure Copy Code” library functions for each zone to
enable the user to copy content from EXEONLY secure flash sectors to EXEONLY RAM blocks. These
functions do the copy-code operation in a highly secure environment and allow a copy to be performed
only when the following conditions are met:
• The secure RAM block and the secure flash sector belong to the same zone.
• Both the secure RAM block and the secure flash sector have EXEONLY protection enabled.
For further usage of these library functions, see the device-specific Boot ROM documentation.

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6.5 SecureCRC
Since reads from EXEONLY memories are not allowed, the user cannot calculate the CRC on content in
EXEONLY memories using the CRC engine available on this device (e.g. VCUCRC, GCRC) or software.
In some safety-critical applications, the user may have to calculate the CRC even on these memories. To
enable this without compromising on security, TI provides specific “SecureCRC” library functions for each
zone. These functions do the CRC calculation in highly secure environment and allow a CRC calculation
to be performed only when the following conditions are met:
• The source address should be modulo the number of words (based on length_id) for which the CRC
needs to be calculated.
• The destination address should belong to the same zone as the source address.
For further usage of these library functions, see the device-specific Boot ROM documentation.

NOTE: The user must disable all the interrupts before calling the secure functions in ROM. If there is
a vector fetch during secure function execution, the CPU gets reset immediately.

Disclaimer: The Code Security Module (CSM) included on this device was designed to password protect
the data stored in the associated memory and is warranted by Texas Instruments (TI), in accordance with
its standard terms and conditions, to conform to TI's published specifications for the warranty period
applicable for this device. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM
CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET
FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR
FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY
CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER
CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR
NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES
INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR
INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

6.6 CSM Impact on Other On-Chip Resources

On this device, some of the memories are not secure. To avoid any potential hacking when the device is
in the default state (post reset), accesses (all types) to all memories (secure as well as non-secure, except
BOOT-ROM and OTP ) are disabled until proper security initialization is done. This means that after reset
none of the memory resources except BOOT_ROM and OTP is accessible to the user.
The following steps are required by CPU1 after reset (any type of reset) to initialize the security on device.

Security Initialization
• Dummy Read to address location of SECDC (0x703F0, TI-reserved register) in TI OTP
• Dummy Read to address location of Z1OTP_LINKPOINTER1 in Z1 OTP
• Dummy Read to address location of Z1OTP_LINKPOINTER2 in Z1 OTP
• Dummy Read to address location of Z1OTP_LINKPOINTER3 in Z1 OTP
• Dummy Read to address location of Z2OTP_LINKPOINTER1 in Z2 OTP
• Dummy Read to address location of Z2OTP_LINKPOINTER2 in Z2 OTP
• Dummy Read to address location of Z2OTP_LINKPOINTER3 in Z2 OTP
• Dummy Read to address location Z1OTP_JLM_ENABLE in Z1 OTP
• Dummy Read to address location of Z1OTP_GPREG1, Z1OTP_GPREG2, Z1OTP_GPREG3,
Z1OTP_GPREG4 in Z1 OTP
• Dummy Read to address location of Z1OTP_PSWDLOCK in Z1 OTP
• Dummy Read to address location of Z1OTP_CRCLOCK in Z1 OTP
• Dummy Read to address location of Z1OTP_JTAGPSWDH0, Z1OTP_JTAGPSWDH1 in Z1 OTP

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• Dummy Read to address location of Z2OTP_GPREG1, Z2OTP_GPREG2, Z2OTP_GPREG3,

Z2OTP_GPREG4 in Z2 OTP
• Dummy Read to address location of Z2OTP_PSWDLOCK in Z2 OTP
• Dummy Read to address location of Z2OTP_CRCLOCK in Z2 OTP
• Read to memory map register of Z1_LINKPOINTER in DCSM module to calculate the address of zone
select block for Z1
• Dummy read to address location of Z1OTP_GRABSECT1, Z1OTP_GRABSECT2,
Z1OTP_GRABSECT3 in Z1 OTP
• Dummy read to address location of Z1OTP_GRABRAM1, Z1OTP_GRABRAM2, Z1OTP_GRABRAM3
in Z1 OTP
• Dummy read to address location of Z1OTP_EXEONLYSECT1, Z1OTP_EXEONLYSECT2 in Z1 OTP
• Dummy read to address location of Z1OTP_EXEONLYRAM1 in Z1 OTP
• Dummy Read to address location of Z1OTP_JTAGPSWDL0, Z1OTP_JTAGPSWDL1 in Z1 OTP
• Read to memory map register of Z2_LINKPOINTER in DCSM module to calculate the address of zone
select block for Z2
• Dummy read to address location of Z2OTP_GRABSECT1, Z2OTP_GRABSECT2,
Z2OTP_GRABSECT3 in Z2 OTP
• Dummy read to address location of Z2OTP_GRABRAM1, Z2OTP_GRABRAM2, Z2OTP_GRABRAM3
in Z2 OTP
• Dummy read to address location of Z2OTP_EXEONLYSECT1, Z2OTP_EXEONLYSECT2 in Z2 OTP
• Dummy read to address location of Z2OTP_EXEONLYRAM1 in Z2 OTP

NOTE: Security Initialization is done by CPU1 BOOTROM code on all the resets (as part of device
initialization) which assert CPU1 SYSRSn. This will not be part of user application code
The order of initialization matters hence if a memory watch window with the USER OTP
address is opened in the debugger (CCS) the security initialization could occur in an
incorrect order, locking the device down. To avoid this, user should not keep a memory
window with USER OTP address opened in the debugger(CCS) when performing a reset.

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6.7 Incorporating Code Security in User Applications

Code security is typically not required in the development phase of a project. However, security is needed
once a robust code is developed for a zone. Before such a code is programmed in the Flash memory, a
CSM password should be chosen to secure the zone. Once a CSM password is in place for a zone, the
zone is secured (programming a password at the appropriate locations and either performing a device
reset or setting the FORCESEC bit (Zx_CR.31) is the action that secures the device). From that time on,
access to debug the contents of secure memory by any means (via JTAG, code running off external/on-
chip memory, and so forth) requires a valid password. A password is not needed to run the code out of
secure memory (such as in a typical end-user usage); however, access to secure memory contents for
debug purposes, requires a password.

6.7.1 Environments That Require Security Unlocking

The following are the typical situations under which unsecuring the zone can be required:
• Code development using debuggers (such as Code Composer Studio). This is the most common
environment during the design phase of a product.
• Flash programming using TI's Flash utilities such as Code Composer Studio On-Chip Flash
Programmer plug-in or the Uniflash tool. Flash programming is common during code development and
testing. Once the user supplies the necessary password, the flash utilities disable the security logic
before attempting to program the Flash. In custom programming solutions that use the Flash API
supplied by TI, unlocking the CSM can be avoided by executing the Flash programming algorithms
from secure memory.
• Custom environment defined by the application
In addition to the above, access to secure memory contents can be required in situations such as:
– Using the on-chip bootloader to load code or data into secure SARAM or to erase and program the
Flash.
– Executing code from on-chip unsecure memory and requiring access to secure memory for the
lookup table. This is not a suggested operating condition as supplying the password from external
code could compromise code security.
The unsecuring sequence is identical in all the above situations. This sequence is referred to as the
password match flow (PMF) for simplicity. Figure 6-3 explains the sequence of operation that is required
every time the user attempts to unsecure a particular zone. A code example is listed for clarity.

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6.7.2 CSM Password Match Flow

Password match flow (PMF) is essentially a sequence of four dummy reads from password locations
(PWL) followed by four writes (32-bit writes) to CSMKEY(0/1/2/3) registers. Figure 6-3 shows how PMF
helps to initialize the security logic registers and disable security logic.

Figure 6-3. CSM Password Match Flow (PMF)

START

Zone secure after reset or

runtime

Read Linkpointer and

calculate the address of
ZoneSelectBlock

Dummy Read of CSM PWL of

the Secure Zone which
needed to be unsecure

Write the CSM Password of YES

that Zone into
CSMKEY(0/1/2/3) registers.

NO
Correct
Password ?

YES

Zone Unsecure

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6.7.3 C Code Example to Unsecure C28x Zone1

volatile long int *CSM = (volatile long int *)5F090; //CSM register file volatile
long int *CSMPWL = (volatile long int *)0x78020; //CSM Password location (assuming default Zone
select block)
volatile int tmp;
int I;
// Read the 128-bits of the CSM password locations (PWL)
//
for (I=0;I<4; I++) tmp = *CSMPWL++;
// Write the 128-bit password to the CSMKEY registers
// If this password matches that stored in the
// CSLPWL then the CSM will become unsecure. If it does not
// match, then the zone will remain secure.
// An example password of: // 0x11112222333344445555666677778888 is used.
*CSM++ = 0x22221111; // Register Z1_CSMKEY0 at 0x5F090
*CSM++ = 0x44443333; // Register Z1_CSMKEY1 at 0x5F092
*CSM++ = 0x66665555; // Register Z1_CSMKEY2 at 0x5F094
*CSM++ = 0x88887777; // Register Z1_CSMKEY3 at 0x5F096

6.7.4 C Code Example to Resecure C28x Zone1

volatile int *Z1_CR = 0x5F019; //CSMSCR register

//Set FORCESEC bit
*Z1_CR = 0x8000;

NOTE: User must use the FORCESEC feature to resecure the zone from same subsystem which
has unlocked the zone. E.g. if CM subsystem has unlocked the Zone1 by entering the CSM
password in CSMKEYx then only CM subsystem should resecure the Zone1 using
FORCESEC feature.

6.7.5 Environments That Require ECSL Unlocking

The following are the typical situations under which unsecuring can be required:
• The user develops some main IP, and then outsources peripheral functions to a subcontractor who
must be able to run the user code during debug and may halt while main IP code is running. If ECSL is
not unlocked, then Code Composer Studio connections will get disconnected, which can be
inconvenient for the user. Note that unlocking ECSL does not enable access to secure code but only
avoids disconnection of CCS (JTAG).

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6.7.6 ECSL Password Match Flow

A password match flow (PMF) is essentially a sequence of eight dummy reads from password locations
(PWL) followed by two writes to KEY registers. Figure 6-4 shows how the PMF helps to initialize the
security logic registers and disable security logic.

Figure 6-4. ECSL Password Match Flow (PMF)

START

Zone’s ECSL LOCK after

reset or runtime

Read Linkpointer and

calculate the address of
ZoneSelectBlock

Dummy Read of CSM PWL of

the Secure Zone for which
ECSL need to be unlock

Write the ECSL Password of YES

that Zone into CSMKEY(0/1)
registers.

NO
Correct
Password ?

YES

Zone ECSL unlock

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6.7.7 ECSL Disable Considerations for any Zone

A zone with ECSL enabled should have a predetermined ECSL password stored in the ECSL password
locations in Flash (same as lower 64 bits of CSM passwords). The following are steps to disable the ECSL
for any particular zone:
• Perform a dummy read of CSM password locations of that Zone.
• Write the password into the CSMKEY0/1 registers, corresponding to that Zone.
• If the password is correct, the ECSL gets disabled; otherwise, it stays enabled.

6.7.7.1 C Code Example to Disable ECSL for C28x-Zone1

volatile long int *ECSL = (volatile int *)0x5F090; //ECSL register file
volatile long int *ECSLPWL = (volatile int *)0x78028; //ECSL Password location (assuming default
Zone sel block)
volatile int tmp;
int I;
// Read the 64-bits of the password locations (PWL).
for (I=0;I<2; I++) tmp = *ECSLPWL++;
// Write the 64-bit password to the CSMKEYx registers
// If this password matches that stored in the
// CSMPWL then ECSL will get disable. If it does not
// match, then the zone will remain secure.
// An example password of: // 0x1111222233334444 is used.
*ECSL++ = 0x22221111; // Register Z1_CSMKEY0 at 0x5F090
*ECSL++ = 0x44443333; // Register Z1_CSMKEY1 at 0x5F092

NOTE: If the CM subsystem is out of reset when ECSL is unlocked by any of the subsystem, one
must reset the CM before trying to lock the ECSL again. Unless CM is reset, ECSL can not
be locked again by entering the incorrect KEY or using the FORCESEC.

6.7.8 Device Unique ID

CPU1 TI OTP contains a 256-bit value that is made up of both random and sequential parts. This value
can be used as a seed for code encryption. The starting address of the value is 0x7020C. The first 192
bits are random, the next 32 bits are sequential, and the last 32 bits are a checksum value.

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6.8 DCSM Registers

This section describes the various DCSM Registers.

NOTE: Except SECERRSTAT, SECERRCLR and SECERRFRC registers, all other registers (non-
OTP space) are mapped on all three subsystem. For CM subsystem, x8 offset need to be
used.

6.8.1 DCSM Base Addresses

Table 6-4. DCSM Base Address Table (C28)

Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU2 DMA CLA
Instance Structure Protected

DcsmZ1Regs DCSM_REGS DCSM_Z1_BASE 0x0005_F000 YES YES - - YES

DcsmZ2Regs DCSM_REGS DCSM_Z2_BASE 0x0005_F080 YES YES - - YES
DCSM_COMMON_RE DCSMCOMMON_BAS
DcsmCommonRegs 0x0005_F0C0 YES YES - - YES
GS E
DCSM_Z1_OTP_REG
DcsmZ1OtpRegs DCSM_Z1OTP_BASE 0x0007_8000 YES - - - -
S
DCSM_Z2_OTP_REG
DcsmZ2OtpRegs DCSM_Z2OTP_BASE 0x0007_8200 YES - - - -
S

Table 6-5. CM DCSM Base Address Table (CM)

DriverLib Name Base Address uDMA Access Ethernet DMA Access
DCSM_Z1_BASE 0x4008_5000 - -
DCSM_Z2_BASE 0x4008_5100 - -
DCSMCOMMON_BASE 0x4008_5180 - -

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6.8.2 DCSM_COMMON_REGS Registers

Table 6-6 lists the DCSM_COMMON_REGS registers. All register offset addresses not listed in Table 6-6
should be considered as reserved locations and the register contents should not be modified.

Table 6-6. DCSM_COMMON_REGS Registers

Offset Offset Acronym Register Name Write Section
(x8) (x16) Protection
0h 0h FLSEM Flash Wrapper Semaphore Register EALLOW Go
10h 8h SECTSTAT1 Flash Sectors Status Register 1 Go
14h Ah SECTSTAT2 Flash Sectors Status Register 2 Go
18h Ch SECTSTAT3 Flash Sectors Status Register 3 Go
20h 10h RAMSTAT1 RAM Status Register 1 Go
24h 12h RAMSTAT2 RAM Status Register 2 Go
28h 14h RAMSTAT3 RAM Status Register 3 Go
30h 18h SECERRSTAT Security Error Status Register Go
34h 1Ah SECERRCLR Security Error Clear Register Go
38h 1Ch SECERRFRC Security Error Force Register Go

Complex bit access types are encoded to fit into small table cells. Table 6-7 shows the codes that are
used for access types in this section.

Table 6-7. DCSM_COMMON_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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6.8.2.1 FLSEM Register (Offset (x8) = 0h, Offset (x16) = 0h) [reset = 0h]
FLSEM is shown in Figure 6-5 and described in Table 6-8.
Return to the Summary Table.
Flash Wrapper Semaphore Register

Figure 6-5. FLSEM Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY RESERVED SEM
R-0/W-0h R-0h R/W-0h

Table 6-8. FLSEM Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 KEY R-0/W 0h Writing a value 0xA5 into this field will allow the writing of the SEM
bits, else writes are ignored. Reads will return 0.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved
1-0 SEM R/W 0h 00 : Flash Wrapper registers can be written by code running from
non-secure zone.
01 : Flash Wrapper registers can be written by code running from
Zone1 security zone.
10 : Flash Wrapper registers can be written by code running from
Zone2 security zone
11 : Flash Wrapper registers can be written by code running from
non-secure zone.
Allowed State Transitions in this field.
00 TO 11 : Not allowed.
11 TO 00 : Not allowed.
00/11 TO 01 : Code running from Zone1 only can perform this
transition.
01 TO 00/11 : Code running from Zone1 only can perform this
transition.
00/11 TO 10 : Code running from Zone2 only can perform this
transition.
10 TO 00/11 : Code running from Zone2 can perform this transition
10 TO 01 : Not allowed.
01 TO 10 : Not allowed.
Reset type: SYSRSn

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6.8.2.2 SECTSTAT1 Register (Offset (x8) = 10h, Offset (x16) = 8h) [reset = 0h]
SECTSTAT1 is shown in Figure 6-6 and described in Table 6-9.
Return to the Summary Table.
Flash Sectors Status Register 1

Figure 6-6. SECTSTAT1 Register

31 30 29 28 27 26 25 24
RESERVED STATUS_SECT13 STATUS_SECT12
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
STATUS_SECT11 STATUS_SECT10 STATUS_SECT9 STATUS_SECT8
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
STATUS_SECT7 STATUS_SECT6 STATUS_SECT5 STATUS_SECT4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
STATUS_SECT3 STATUS_SECT2 STATUS_SECT1 STATUS_SECT0
R-0h R-0h R-0h R-0h

Table 6-9. SECTSTAT1 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 STATUS_SECT13 R 0h Reflects the status of flash CPU1 BANK Sector 13.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
25-24 STATUS_SECT12 R 0h Reflects the status of flash CPU1 BANK Sector 12.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
23-22 STATUS_SECT11 R 0h Reflects the status of flash CPU1 BANK Sector 11.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
21-20 STATUS_SECT10 R 0h Reflects the status of flash CPU1 BANK Sector 10.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
19-18 STATUS_SECT9 R 0h Reflects the status of flash CPU1 BANK Sector 9.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-9. SECTSTAT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
17-16 STATUS_SECT8 R 0h Reflects the status of flash CPU1 BANK sector 8.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_SECT7 R 0h Reflects the status of flash CPU1 BANK Sector 7.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_SECT6 R 0h Reflects the status of flash CPU1 BANK Sector 6.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_SECT5 R 0h Reflects the status of flash CPU1 BANK Sector 5.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_SECT4 R 0h Reflects the status of flash CPU1 BANK Sector 4.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_SECT3 R 0h Reflects the status of flash CPU1 BANK Sector 3.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_SECT2 R 0h Reflects the status of flash CPU1 BANK Sector 2.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_SECT1 R 0h Reflects the status of flash CPU1 BANK sector 1.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_SECT0 R 0h Reflects the status of flash CPU1 BANK Sector 0.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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6.8.2.3 SECTSTAT2 Register (Offset (x8) = 14h, Offset (x16) = Ah) [reset = 0h]
SECTSTAT2 is shown in Figure 6-7 and described in Table 6-10.
Return to the Summary Table.
Flash Sectors Status Register 2

Figure 6-7. SECTSTAT2 Register

31 30 29 28 27 26 25 24
RESERVED STATUS_SECT13 STATUS_SECT12
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
STATUS_SECT11 STATUS_SECT10 STATUS_SECT9 STATUS_SECT8
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
STATUS_SECT7 STATUS_SECT6 STATUS_SECT5 STATUS_SECT4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
STATUS_SECT3 STATUS_SECT2 STATUS_SECT1 STATUS_SECT0
R-0h R-0h R-0h R-0h

Table 6-10. SECTSTAT2 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 STATUS_SECT13 R 0h Reflects the status of flash CM BANK Sector 13.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
25-24 STATUS_SECT12 R 0h Reflects the status of flash CM BANK Sector 12.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
23-22 STATUS_SECT11 R 0h Reflects the status of flash CM BANK Sector 11.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
21-20 STATUS_SECT10 R 0h Reflects the status of flash CM BANK Sector 10.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
19-18 STATUS_SECT9 R 0h Reflects the status of flash CM BANK Sector 9.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-10. SECTSTAT2 Register Field Descriptions (continued)

Bit Field Type Reset Description
17-16 STATUS_SECT8 R 0h Reflects the status of flash CM BANK sector 8.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_SECT7 R 0h Reflects the status of flash CM BANK Sector 7.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_SECT6 R 0h Reflects the status of flash CM BANK Sector 6.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_SECT5 R 0h Reflects the status of flash CM BANK Sector 5.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_SECT4 R 0h Reflects the status of flash CM BANK Sector 4.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_SECT3 R 0h Reflects the status of flash CM BANK Sector 3.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_SECT2 R 0h Reflects the status of flash CM BANK Sector 2.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_SECT1 R 0h Reflects the status of flash CM BANK sector 1.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_SECT0 R 0h Reflects the status of flash CM BANK Sector 0.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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6.8.2.4 SECTSTAT3 Register (Offset (x8) = 18h, Offset (x16) = Ch) [reset = 0h]
SECTSTAT3 is shown in Figure 6-8 and described in Table 6-11.
Return to the Summary Table.
Flash Sectors Status Register 3

Figure 6-8. SECTSTAT3 Register

31 30 29 28 27 26 25 24
RESERVED STATUS_SECT13 STATUS_SECT12
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
STATUS_SECT11 STATUS_SECT10 STATUS_SECT9 STATUS_SECT8
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
STATUS_SECT7 STATUS_SECT6 STATUS_SECT5 STATUS_SECT4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
STATUS_SECT3 STATUS_SECT2 STATUS_SECT1 STATUS_SECT0
R-0h R-0h R-0h R-0h

Table 6-11. SECTSTAT3 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 STATUS_SECT13 R 0h Reflects the status of flash CPU2 BANK Sector 13.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
25-24 STATUS_SECT12 R 0h Reflects the status of flash CPU2 BANK Sector 12.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
23-22 STATUS_SECT11 R 0h Reflects the status of flash CPU2 BANK Sector 11.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
21-20 STATUS_SECT10 R 0h Reflects the status of flash CPU2 BANK Sector 10.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
19-18 STATUS_SECT9 R 0h Reflects the status of flash CPU2 BANK Sector 9.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-11. SECTSTAT3 Register Field Descriptions (continued)

Bit Field Type Reset Description
17-16 STATUS_SECT8 R 0h Reflects the status of flash CPU2 BANK sector 8.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_SECT7 R 0h Reflects the status of flash CPU2 BANK Sector 7.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_SECT6 R 0h Reflects the status of flash CPU2 BANK Sector 6.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_SECT5 R 0h Reflects the status of flash CPU2 BANK Sector 5.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_SECT4 R 0h Reflects the status of flash CPU2 BANK Sector 4.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_SECT3 R 0h Reflects the status of flash CPU2 BANK Sector 3.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_SECT2 R 0h Reflects the status of flash CPU2 BANK Sector 2.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_SECT1 R 0h Reflects the status of flash CPU2 BANK sector 1.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_SECT0 R 0h Reflects the status of flash CPU2 BANK Sector 0.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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6.8.2.5 RAMSTAT1 Register (Offset (x8) = 20h, Offset (x16) = 10h) [reset = 0h]
RAMSTAT1 is shown in Figure 6-9 and described in Table 6-12.
Return to the Summary Table.
RAM Status Register 1

Figure 6-9. RAMSTAT1 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED STATUS_RAM9 STATUS_RAM8
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
STATUS_RAM7 STATUS_RAM6 STATUS_RAM5 STATUS_RAM4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
STATUS_RAM3 STATUS_RAM2 STATUS_RAM1 STATUS_RAM0
R-0h R-0h R-0h R-0h

Table 6-12. RAMSTAT1 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 STATUS_RAM9 R 0h Reflects the status of CPU1.D1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_RAM8 R 0h Reflects the status of CPU1.D0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_RAM7 R 0h Reflects the status of CPU1.LS7 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_RAM6 R 0h Reflects the status of CPU1.LS6 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_RAM5 R 0h Reflects the status of CPU1.LS5 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-12. RAMSTAT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
9-8 STATUS_RAM4 R 0h Reflects the status of CPU1.LS4 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_RAM3 R 0h Reflects the status of CPU1.LS3 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_RAM2 R 0h Reflects the status of CPU1.LS2 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_RAM1 R 0h Reflects the status of CPU1.LS1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_RAM0 R 0h Reflects the status of CPU1.LS0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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6.8.2.6 RAMSTAT2 Register (Offset (x8) = 24h, Offset (x16) = 12h) [reset = 0h]
RAMSTAT2 is shown in Figure 6-10 and described in Table 6-13.
Return to the Summary Table.
RAM Status Register 2

Figure 6-10. RAMSTAT2 Register

31 30 29 28 27 26 25 24
STATUS_RAM15 STATUS_RAM14 STATUS_RAM13 STATUS_RAM12
R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
STATUS_RAM11 STATUS_RAM10 STATUS_RAM9 STATUS_RAM8
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
STATUS_RAM7 STATUS_RAM6 STATUS_RAM5 STATUS_RAM4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED STATUS_RAM1 STATUS_RAM0
R-0h R-0h R-0h

Table 6-13. RAMSTAT2 Register Field Descriptions

Bit Field Type Reset Description
31-30 STATUS_RAM15 R 0h Reflects the status of CM to CPU2 MSG RAM 1.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
29-28 STATUS_RAM14 R 0h Reflects the status of MSG RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
27-26 STATUS_RAM13 R 0h Reflects the status of MSG RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
25-24 STATUS_RAM12 R 0h Reflects the status of MSG RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
23-22 STATUS_RAM11 R 0h Reflects the status of MSG RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-13. RAMSTAT2 Register Field Descriptions (continued)

Bit Field Type Reset Description
21-20 STATUS_RAM10 R 0h Reflects the status of CM to CPU2 MSG RAM 0.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
19-18 STATUS_RAM9 R 0h Reflects the status of CPU2 to CM MSG RAM 1.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_RAM8 R 0h Reflects the status of CPU2 to CM MSG RAM 0.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_RAM7 R 0h Reflects the status of CM to CPU1 MSG RAM 1.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_RAM6 R 0h Reflects the status of CM to CPU1 MSG RAM 0.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_RAM5 R 0h Reflects the status of CPU1 to CM MSG RAM 1.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_RAM4 R 0h Reflects the status of CPU1 to CM MSG RAM 0.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-4 RESERVED R 0h Reserved
3-2 STATUS_RAM1 R 0h Reflects the status of C1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-13. RAMSTAT2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 STATUS_RAM0 R 0h Reflects the status of C0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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6.8.2.7 RAMSTAT3 Register (Offset (x8) = 28h, Offset (x16) = 14h) [reset = 0h]
RAMSTAT3 is shown in Figure 6-11 and described in Table 6-14.
Return to the Summary Table.
RAM Status Register 3

Figure 6-11. RAMSTAT3 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED STATUS_RAM9 STATUS_RAM8
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
STATUS_RAM7 STATUS_RAM6 STATUS_RAM5 STATUS_RAM4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
STATUS_RAM3 STATUS_RAM2 STATUS_RAM1 STATUS_RAM0
R-0h R-0h R-0h R-0h

Table 6-14. RAMSTAT3 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 STATUS_RAM9 R 0h Reflects the status of CPU2.D1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_RAM8 R 0h Reflects the status of CPU2.D0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_RAM7 R 0h Reflects the status of CPU2.LS7 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_RAM6 R 0h Reflects the status of CPU2.LS6 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_RAM5 R 0h Reflects the status of CPU2.LS5 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-14. RAMSTAT3 Register Field Descriptions (continued)

Bit Field Type Reset Description
9-8 STATUS_RAM4 R 0h Reflects the status of CPU2.LS4 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_RAM3 R 0h Reflects the status of CPU2.LS3 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_RAM2 R 0h Reflects the status of CPU2.LS2 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_RAM1 R 0h Reflects the status of CPU2.LS1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_RAM0 R 0h Reflects the status of CPU2.LS0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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6.8.2.8 SECERRSTAT Register (Offset (x8) = 30h, Offset (x16) = 18h) [reset = 0h]
SECERRSTAT is shown in Figure 6-12 and described in Table 6-15.
Return to the Summary Table.
Security Error Status Register

Figure 6-12. SECERRSTAT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR
R-0-0h R-0h

Table 6-15. SECERRSTAT Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 ERR R 0h This bit indicates if any error has occurred in the load of any security
configuration from USER-OTP.
0: No error has occurred in the load of security information from
USER-OTP
1: Error has occurred in the load of security information from USER-
OTP
Reset type: PORESETn

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6.8.2.9 SECERRCLR Register (Offset (x8) = 34h, Offset (x16) = 1Ah) [reset = 0h]
SECERRCLR is shown in Figure 6-13 and described in Table 6-16.
Return to the Summary Table.
Security Error Clear Register

Figure 6-13. SECERRCLR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR
R-0-0h R-
0/W1S
-0h

Table 6-16. SECERRCLR Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 ERR R-0/W1S 0h A write of '1' clears the SECERRSTST.ERR bit. Write of '0' is
ignored. This bit always reads back '0'.
Reset type: N/A

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6.8.2.10 SECERRFRC Register (Offset (x8) = 38h, Offset (x16) = 1Ch) [reset = 0h]
SECERRFRC is shown in Figure 6-14 and described in Table 6-17.
Return to the Summary Table.
Security Error Force Register

Figure 6-14. SECERRFRC Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
R-0/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR
R-0-0h R-
0/W1S
-0h

Table 6-17. SECERRFRC Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h In order to write to the ERR bits, 0x5a5a must be written to these
key bits at the same time. Otherwise, writes are ignored. The key is
cleared immediately after writing, so it must be written again for
every write to ERR. Reads will return 0.
Reset type: N/A
15-1 RESERVED R-0 0h Reserved
0 ERR R-0/W1S 0h A write of '1', along with the proper KEY, sets the
SECERRSTST.ERR bit. Write of '0' is ignored. This bit always reads
back '0'.
Reset type: N/A

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6.8.3 DCSM_Z1_OTP Registers

Table 6-18 lists the DCSM_Z1_OTP registers. All register offset addresses not listed in Table 6-18 should
be considered as reserved locations and the register contents should not be modified.

Table 6-18. DCSM_Z1_OTP Registers

Offset Acronym Register Name Write Protection Section
0h Z1OTP_LINKPOINTER1 Zone 1 Link Pointer1 Go
2h Z1OTP_LINKPOINTER2 Zone 1 Link Pointer2 Go
4h Z1OTP_LINKPOINTER3 Zone 1 Link Pointer3 Go
6h Z1OTP_JLM_ENABLE Zone 1 JTAGLOCK Enable Register Go
8h Z1OTP_GPREG1 Zone 1 General Purpose Register 1 Go
Ah Z1OTP_GPREG2 Zone 1 General Purpose Register 2 Go
Ch Z1OTP_GPREG3 Zone 1 General Purpose Register 3 Go
Eh Z1OTP_GPREG4 Zone 1 General Purpose Register 4 Go
10h Z1OTP_PSWDLOCK Secure Password Lock Go
12h Z1OTP_CRCLOCK Secure CRC Lock Go
14h Z1OTP_JTAGPSWDH0 JTAG Lock Permanent Password 0 Go
16h Z1OTP_JTAGPSWDH1 JTAG Lock Permanent Password 1 Go
18h Z1OTP_CMACKEY0 Secure Boot CMAC Key 0 Go
1Ah Z1OTP_CMACKEY1 Secure Boot CMAC Key 1 Go
1Ch Z1OTP_CMACKEY2 Secure Boot CMAC Key 2 Go
1Eh Z1OTP_CMACKEY3 Secure Boot CMAC Key 3 Go

Complex bit access types are encoded to fit into small table cells. Table 6-19 shows the codes that are
used for access types in this section.

Table 6-19. DCSM_Z1_OTP Access Type Codes

Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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6.8.3.1 Z1OTP_LINKPOINTER1 Register (Offset = 0h) [reset = FFFFFFFFh]

Z1OTP_LINKPOINTER1 is shown in Figure 6-15 and described in Table 6-20.
Return to the Summary Table.
Zone 1 Link Pointer1

Figure 6-15. Z1OTP_LINKPOINTER1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER1
R-FFFFFFFFh

Table 6-20. Z1OTP_LINKPOINTER1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_LINKPOINTER1 R FFFFFFFFh Zone1 Link Pointer 1 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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6.8.3.2 Z1OTP_LINKPOINTER2 Register (Offset = 2h) [reset = FFFFFFFFh]

Z1OTP_LINKPOINTER2 is shown in Figure 6-16 and described in Table 6-21.
Return to the Summary Table.
Zone 1 Link Pointer2

Figure 6-16. Z1OTP_LINKPOINTER2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER2
R-FFFFFFFFh

Table 6-21. Z1OTP_LINKPOINTER2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_LINKPOINTER2 R FFFFFFFFh Zone1 Link Pointer 2 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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6.8.3.3 Z1OTP_LINKPOINTER3 Register (Offset = 4h) [reset = FFFFFFFFh]

Z1OTP_LINKPOINTER3 is shown in Figure 6-17 and described in Table 6-22.
Return to the Summary Table.
Zone 1 Link Pointer3

Figure 6-17. Z1OTP_LINKPOINTER3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER3
R-FFFFFFFFh

Table 6-22. Z1OTP_LINKPOINTER3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_LINKPOINTER3 R FFFFFFFFh Zone1 Link Pointer 3 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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6.8.3.4 Z1OTP_JLM_ENABLE Register (Offset = 6h) [reset = FFFFFFFFh]

Z1OTP_JLM_ENABLE is shown in Figure 6-18 and described in Table 6-23.
Return to the Summary Table.
Zone 1 JTAGLOCK Enable Register

Figure 6-18. Z1OTP_JLM_ENABLE Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_JLM_ENABLE
R-FFFFFFFFh

Table 6-23. Z1OTP_JLM_ENABLE Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_JLM_ENABLE R FFFFFFFFh Zone1 JLM_ENABLE register location in USER OTP.
Note: When this value is loaded into Z1_JLM_ENABLE, if the value
is 32-bit all-1s, the JTAGLOCK will be enabled. Before shipping
parts to customers, TI will program the default value to
0xFFFF_000F, which will disable the JTAGLOCK feature. Users
should program 0xFFFF_0000 to enable the JTAGLOCK feature.
Reset type: N/A

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6.8.3.5 Z1OTP_GPREG1 Register (Offset = 8h) [reset = FFFFFFFFh]

Z1OTP_GPREG1 is shown in Figure 6-19 and described in Table 6-24.
Return to the Summary Table.
Zone 1 General Purpose Register 1

Figure 6-19. Z1OTP_GPREG1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG1
R-FFFFFFFFh

Table 6-24. Z1OTP_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG1 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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6.8.3.6 Z1OTP_GPREG2 Register (Offset = Ah) [reset = FFFFFFFFh]

Z1OTP_GPREG2 is shown in Figure 6-20 and described in Table 6-25.
Return to the Summary Table.
Zone 1 General Purpose Register 2

Figure 6-20. Z1OTP_GPREG2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG2
R-FFFFFFFFh

Table 6-25. Z1OTP_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG2 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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6.8.3.7 Z1OTP_GPREG3 Register (Offset = Ch) [reset = FFFFFFFFh]

Z1OTP_GPREG3 is shown in Figure 6-21 and described in Table 6-26.
Return to the Summary Table.
Zone 1 General Purpose Register 3

Figure 6-21. Z1OTP_GPREG3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG3
R-FFFFFFFFh

Table 6-26. Z1OTP_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG3 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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6.8.3.8 Z1OTP_GPREG4 Register (Offset = Eh) [reset = FFFFFFFFh]

Z1OTP_GPREG4 is shown in Figure 6-22 and described in Table 6-27.
Return to the Summary Table.
Zone 1 General Purpose Register 4

Figure 6-22. Z1OTP_GPREG4 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG4
R-FFFFFFFFh

Table 6-27. Z1OTP_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG4 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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6.8.3.9 Z1OTP_PSWDLOCK Register (Offset = 10h) [reset = FFFFFFFFh]

Z1OTP_PSWDLOCK is shown in Figure 6-23 and described in Table 6-28.
Return to the Summary Table.
Secure Password Lock

Figure 6-23. Z1OTP_PSWDLOCK Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_PSWDLOCK
R-FFFFFFFFh

Table 6-28. Z1OTP_PSWDLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_PSWDLOCK R FFFFFFFFh Zone1 password lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-bit all-
1s, CSMPSWD will remain locked. Before shipping parts to
customers, TI would change the value of this location in such a way
that the ECC field remains all-1s and also LSB 4-bits remain
4'b1111.
Reset type: N/A

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6.8.3.10 Z1OTP_CRCLOCK Register (Offset = 12h) [reset = FFFFFFFFh]

Z1OTP_CRCLOCK is shown in Figure 6-24 and described in Table 6-29.
Return to the Summary Table.
Secure CRC Lock

Figure 6-24. Z1OTP_CRCLOCK Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_CRCLOCK
R-FFFFFFFFh

Table 6-29. Z1OTP_CRCLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_CRCLOCK R FFFFFFFFh Zone1 CRC lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-bit all-
1s, VCU will not have ability to calculate CRC on secured memory
content.. Before shipping parts to customers, TI would change the
value of this location in such a way that the ECC field remains all-1s
and also LSB 4-bits remain 4'b1111.
Reset type: N/A

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6.8.3.11 Z1OTP_JTAGPSWDH0 Register (Offset = 14h) [reset = FFFFFFFFh]

Z1OTP_JTAGPSWDH0 is shown in Figure 6-25 and described in Table 6-30.
Return to the Summary Table.
JTAG Lock Permanent Password 0

Figure 6-25. Z1OTP_JTAGPSWDH0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JTAGPSWDH0
R-FFFFFFFFh

Table 6-30. Z1OTP_JTAGPSWDH0 Register Field Descriptions

Bit Field Type Reset Description
31-0 JTAGPSWDH0 R FFFFFFFFh JTAG Lock Password High 0 (bits 95:64) location in USER Z1 OTP.
This value is dummy loaded into the non-memory-mapped
JTAGPSWD register, bits 95:64.
TI must program a default value into this location, leaving the ECC
bits all 1's.
Reset type: N/A

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6.8.3.12 Z1OTP_JTAGPSWDH1 Register (Offset = 16h) [reset = FFFFFFFFh]

Z1OTP_JTAGPSWDH1 is shown in Figure 6-26 and described in Table 6-31.
Return to the Summary Table.
JTAG Lock Permanent Password 1

Figure 6-26. Z1OTP_JTAGPSWDH1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JTAGPSWDH1
R-FFFFFFFFh

Table 6-31. Z1OTP_JTAGPSWDH1 Register Field Descriptions

Bit Field Type Reset Description
31-0 JTAGPSWDH1 R FFFFFFFFh JTAG Lock Password High 1 (bits 127:96) location in USER Z1
OTP.
This value is dummy loaded into the non-memory-mapped
JTAGPSWD register, bits 127:96.
Reset type: N/A

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6.8.3.13 Z1OTP_CMACKEY0 Register (Offset = 18h) [reset = FFFFFFFFh]

Z1OTP_CMACKEY0 is shown in Figure 6-27 and described in Table 6-32.
Return to the Summary Table.
Secure Boot CMAC Key 0

Figure 6-27. Z1OTP_CMACKEY0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY0
R-FFFFFFFFh

Table 6-32. Z1OTP_CMACKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY0 R FFFFFFFFh Secure Boot CMAC Key 0 (bits 31:0) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY0 register.
Reset type: N/A

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6.8.3.14 Z1OTP_CMACKEY1 Register (Offset = 1Ah) [reset = FFFFFFFFh]

Z1OTP_CMACKEY1 is shown in Figure 6-28 and described in Table 6-33.
Return to the Summary Table.
Secure Boot CMAC Key 1

Figure 6-28. Z1OTP_CMACKEY1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY1
R-FFFFFFFFh

Table 6-33. Z1OTP_CMACKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY1 R FFFFFFFFh Secure Boot CMAC Key 1 (bits 63:32) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY1 register.
Reset type: N/A

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6.8.3.15 Z1OTP_CMACKEY2 Register (Offset = 1Ch) [reset = FFFFFFFFh]

Z1OTP_CMACKEY2 is shown in Figure 6-29 and described in Table 6-34.
Return to the Summary Table.
Secure Boot CMAC Key 2

Figure 6-29. Z1OTP_CMACKEY2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY2
R-FFFFFFFFh

Table 6-34. Z1OTP_CMACKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY2 R FFFFFFFFh Secure Boot CMAC Key 2 (bits 95:64) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY2 register.
Reset type: N/A

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6.8.3.16 Z1OTP_CMACKEY3 Register (Offset = 1Eh) [reset = FFFFFFFFh]

Z1OTP_CMACKEY3 is shown in Figure 6-30 and described in Table 6-35.
Return to the Summary Table.
Secure Boot CMAC Key 3

Figure 6-30. Z1OTP_CMACKEY3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY3
R-FFFFFFFFh

Table 6-35. Z1OTP_CMACKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY3 R FFFFFFFFh Secure Boot CMAC Key 3 (bits 127:96) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY3 register.
Reset type: N/A

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6.8.4 DCSM_Z1_REGS Registers

Table 6-36 lists the DCSM_Z1_REGS registers. All register offset addresses not listed in Table 6-36
should be considered as reserved locations and the register contents should not be modified.

Table 6-36. DCSM_Z1_REGS Registers

Offset Offset Acronym Register Name Write Section
(x8) (x16) Protection
0h 0h Z1_LINKPOINTER Zone 1 Link Pointer Go
4h 2h Z1_OTPSECLOCK Zone 1 OTP Secure Lock Go
8h 4h Z1_JLM_ENABLE Zone 1 JTAGLOCK Enable Register Go
Ch 6h Z1_LINKPOINTERERR Link Pointer Error Go
10h 8h Z1_GPREG1 Zone 1 General Purpose Register-1 Go
14h Ah Z1_GPREG2 Zone 1 General Purpose Register-2 Go
18h Ch Z1_GPREG3 Zone 1 General Purpose Register-3 Go
1Ch Eh Z1_GPREG4 Zone 1 General Purpose Register-4 Go
20h 10h Z1_CSMKEY0 Zone 1 CSM Key 0 Go
24h 12h Z1_CSMKEY1 Zone 1 CSM Key 1 Go
28h 14h Z1_CSMKEY2 Zone 1 CSM Key 2 Go
2Ch 16h Z1_CSMKEY3 Zone 1 CSM Key 3 Go
30h 18h Z1_CR Zone 1 CSM Control Register Go
34h 1Ah Z1_GRABSECT1R Zone 1 Grab Flash Status Register 1 Go
38h 1Ch Z1_GRABSECT2R Zone 1 Grab Flash Status Register 2 Go
3Ch 1Eh Z1_GRABSECT3R Zone 1 Grab Flash Status Register 3 Go
40h 20h Z1_GRABRAM1R Zone 1 Grab RAM Status Register 1 Go
44h 22h Z1_GRABRAM2R Zone 1 Grab RAM Status Register 2 Go
48h 24h Z1_GRABRAM3R Zone 1 Grab RAM Status Register 3 Go
4Ch 26h Z1_EXEONLYSECT1R Zone 1 Execute Only Flash Status Register Go
1
50h 28h Z1_EXEONLYSECT2R Zone 1 Execute Only Flash Status Register Go
2
54h 2Ah Z1_EXEONLYRAM1R Zone 1 Execute Only RAM Status Register 1 Go
5Ch 2Eh Z1_JTAGKEY0 JTAG Unlock Key Register 0 Go
60h 30h Z1_JTAGKEY1 JTAG Unlock Key Register 1 Go
64h 32h Z1_JTAGKEY2 JTAG Unlock Key Register 2 Go
68h 34h Z1_JTAGKEY3 JTAG Unlock Key Register 3 Go
6Ch 36h Z1_CMACKEY0 Secure Boot CMAC Key Status Register 0 Go
70h 38h Z1_CMACKEY1 Secure Boot CMAC Key Status Register 1 Go
74h 3Ah Z1_CMACKEY2 Secure Boot CMAC Key Status Register 2 Go
78h 3Ch Z1_CMACKEY3 Secure Boot CMAC Key Status Register 3 Go

Complex bit access types are encoded to fit into small table cells. Table 6-37 shows the codes that are
used for access types in this section.

Table 6-37. DCSM_Z1_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write

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Table 6-37. DCSM_Z1_REGS Access Type

Codes (continued)
Access Type Code Description
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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6.8.4.1 Z1_LINKPOINTER Register (Offset (x8) = 0h, Offset (x16) = 0h) [reset = FFFFC000h]
Z1_LINKPOINTER is shown in Figure 6-31 and described in Table 6-38.
Return to the Summary Table.
Zone 1 Link Pointer

Figure 6-31. Z1_LINKPOINTER Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LINKPOINTER
R-0003FFFFh R-0h

Table 6-38. Z1_LINKPOINTER Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0003FFFFh Reserved
13-0 LINKPOINTER R 0h This is resolved Link-Pointer value which is generated by looking at
the three physical Link-Pointer values loaded from OTP
Reset type: SYSRSn

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6.8.4.2 Z1_OTPSECLOCK Register (Offset (x8) = 4h, Offset (x16) = 2h) [reset = 1h]
Z1_OTPSECLOCK is shown in Figure 6-32 and described in Table 6-39.
Return to the Summary Table.
Zone 1 OTP Secure Lock

Figure 6-32. Z1_OTPSECLOCK Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED CRCLOCK
R-0h R-0h
7 6 5 4 3 2 1 0
PSWDLOCK RESERVED JTAGLOCK
R-0h R-0h R-1h

Table 6-39. Z1_OTPSECLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 RESERVED R 0h Reserved
11-8 CRCLOCK R 0h Value in this field gets loaded from Z1_CRCLOCK[3:0] when a read
is issued to address location of Z1_CRCLOCK in OTP.
1111 : VCU has ability to calculate CRC on secure memories.
Other Value : VCU doesn't have ability to calculate CRC on secure
memories.
Reset type: XRSn
7-4 PSWDLOCK R 0h Value in this field gets loaded from Z1_PSWDLOCK[3:0] when a
read is issued to address location of Z1_PSWDLOCK in OTP.
1111 : CSM password locations in OTP are not protected and can
be read from debugger as well as code running from anywhere.
Other Value : CSM password locations in OTP are protected and
can't be read without unlocking CSM of that zone.
Reset type: XRSn
3-1 RESERVED R 0h Reserved
0 JTAGLOCK R 1h Reflects the state of the JTAGLOCK feature.
0 : JTAG is not locked
1 : JTAG is locked
Reset type: PORESETn

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6.8.4.3 Z1_JLM_ENABLE Register (Offset (x8) = 8h, Offset (x16) = 4h) [reset = Fh]
Z1_JLM_ENABLE is shown in Figure 6-33 and described in Table 6-40.
Return to the Summary Table.
Zone 1 JTAGLOCK Enable Register

Figure 6-33. Z1_JLM_ENABLE Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED Z1_JLM_ENABLE
R-0-0h R-Fh

Table 6-40. Z1_JLM_ENABLE Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3-0 Z1_JLM_ENABLE R Fh Zone1 JLM_ENABLE register. The value in this field gets loaded
from Z1OTP_JLM_ENABLE[3:0] when a read is issued to address
location of Z1OTP_JLM_ENABLE in OTP. If
Z1OTP_JLM_ENABLE[31:0] is equal to all ones during the load, the
JTAGLOCK is not bypassed (is enabled). If the value of
Z1OTP_JLM_ENABLE[31:0] is not all ones during the load, the
JTAGLOCK is governed as follows by the Z1_JLM_ENABLE bits:
1111 : JTAG/Emulation access is allowed (JTAGLOCK is not
enabled)
Other values: JTAGLOCK is governed by the
JTAGKEY==JTAGPSWD match condition
Reset type: PORESETn

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6.8.4.4 Z1_LINKPOINTERERR Register (Offset (x8) = Ch, Offset (x16) = 6h) [reset = 0h]
Z1_LINKPOINTERERR is shown in Figure 6-34 and described in Table 6-41.
Return to the Summary Table.
Link Pointer Error

Figure 6-34. Z1_LINKPOINTERERR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED Z1_LINKPOINTERERR
R-0-0h R-0h

Table 6-41. Z1_LINKPOINTERERR Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R-0 0h Reserved
13-0 Z1_LINKPOINTERERR R 0h These bits indicate errors during formation of the resolved Link-
Pointer value after the three physical Link-Pointer values loaded of
OTP in flash.
0 : No Error.
Other : Error on bit positions which is set to 1.
Reset type: SYSRSn

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6.8.4.5 Z1_GPREG1 Register (Offset (x8) = 10h, Offset (x16) = 8h) [reset = 0h]
Z1_GPREG1 is shown in Figure 6-35 and described in Table 6-42.
Return to the Summary Table.
Zone 1 General Purpose Register-1

Figure 6-35. Z1_GPREG1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG1
R-0h

Table 6-42. Z1_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG1 R 0h This field gets loaded with the contents of Z1OTP_GPREG1
locations in Zone-1-USER-OTP when a dummy read is issued to that
address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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6.8.4.6 Z1_GPREG2 Register (Offset (x8) = 14h, Offset (x16) = Ah) [reset = 0h]
Z1_GPREG2 is shown in Figure 6-36 and described in Table 6-43.
Return to the Summary Table.
Zone 1 General Purpose Register-2

Figure 6-36. Z1_GPREG2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG2
R-0h

Table 6-43. Z1_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG2 R 0h This field gets loaded with the contents of Z1OTP_GPREG2
locations in Zone-1-USER-OTP when a dummy read is issued to that
address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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6.8.4.7 Z1_GPREG3 Register (Offset (x8) = 18h, Offset (x16) = Ch) [reset = 0h]
Z1_GPREG3 is shown in Figure 6-37 and described in Table 6-44.
Return to the Summary Table.
Zone 1 General Purpose Register-3

Figure 6-37. Z1_GPREG3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG3
R-0h

Table 6-44. Z1_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG3 R 0h This field gets loaded with the contents of Z1OTP_GPREG3
locations in Zone-1-USER-OTP when a dummy read is issued to that
address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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6.8.4.8 Z1_GPREG4 Register (Offset (x8) = 1Ch, Offset (x16) = Eh) [reset = 0h]
Z1_GPREG4 is shown in Figure 6-38 and described in Table 6-45.
Return to the Summary Table.
Zone 1 General Purpose Register-4

Figure 6-38. Z1_GPREG4 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG4
R-0h

Table 6-45. Z1_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG4 R 0h This field gets loaded with the contents of Z1OTP_GPREG4
locations in Zone-1-USER-OTP when a dummy read is issued to that
address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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6.8.4.9 Z1_CSMKEY0 Register (Offset (x8) = 20h, Offset (x16) = 10h) [reset = 0h]
Z1_CSMKEY0 is shown in Figure 6-39 and described in Table 6-46.
Return to the Summary Table.
Zone 1 CSM Key 0

Figure 6-39. Z1_CSMKEY0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY0
R/W-0h

Table 6-46. Z1_CSMKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY0 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD0, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.8.4.10 Z1_CSMKEY1 Register (Offset (x8) = 24h, Offset (x16) = 12h) [reset = 0h]
Z1_CSMKEY1 is shown in Figure 6-40 and described in Table 6-47.
Return to the Summary Table.
Zone 1 CSM Key 1

Figure 6-40. Z1_CSMKEY1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY1
R/W-0h

Table 6-47. Z1_CSMKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY1 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD1, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.8.4.11 Z1_CSMKEY2 Register (Offset (x8) = 28h, Offset (x16) = 14h) [reset = 0h]
Z1_CSMKEY2 is shown in Figure 6-41 and described in Table 6-48.
Return to the Summary Table.
Zone 1 CSM Key 2

Figure 6-41. Z1_CSMKEY2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY2
R/W-0h

Table 6-48. Z1_CSMKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY2 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD2, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.8.4.12 Z1_CSMKEY3 Register (Offset (x8) = 2Ch, Offset (x16) = 16h) [reset = 0h]
Z1_CSMKEY3 is shown in Figure 6-42 and described in Table 6-49.
Return to the Summary Table.
Zone 1 CSM Key 3

Figure 6-42. Z1_CSMKEY3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY3
R/W-0h

Table 6-49. Z1_CSMKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY3 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD3, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.8.4.13 Z1_CR Register (Offset (x8) = 30h, Offset (x16) = 18h) [reset = 00080000h]
Z1_CR is shown in Figure 6-43 and described in Table 6-50.
Return to the Summary Table.
Zone 1 CSM Control Register

Figure 6-43. Z1_CR Register

31 30 29 28 27 26 25 24
FORCESEC RESERVED
R-0/W-0h R-0h
23 22 21 20 19 18 17 16
ARMED UNSECURE ALLONE ALLZERO RESERVED
R-0h R-0h R-0h R-1h R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED
R-0-0h

Table 6-50. Z1_CR Register Field Descriptions

Bit Field Type Reset Description
31 FORCESEC R-0/W 0h A write '1' to this fields resets the state of zone. If zone is unlocked,
it'll lock(secure) the zone and also resets all the bits in this register.
Reset type: SYSRSn
30-24 RESERVED R 0h Reserved
22 ARMED R 0h 0 : Dummy read to CSM Password locations in OTP hasn't been
performed.
1 : Dummy read to CSM Password locations in OTP has been
performed.
Reset type: SYSRSn
21 UNSECURE R 0h Indiacates the state of Zone.
0 : Zone is in lock(secure) state.
1 : Zone is in unlock(unsecure) state.
Reset type: SYSRSn
20 ALLONE R 0h Indicates the state of CSM passwords.
0 : Zone CSM Passwords are not all ones.
1 : Zone CSM Passwords are all ones.
Reset type: SYSRSn
19 ALLZERO R 1h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all zeros.
1 : CSM Passwords are all zero and device is permanently locked.
Reset type: SYSRSn
18-16 RESERVED R 0h Reserved
15-4 RESERVED R-0 0h Reserved

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6.8.4.14 Z1_GRABSECT1R Register (Offset (x8) = 34h, Offset (x16) = 1Ah) [reset = 0h]
Z1_GRABSECT1R is shown in Figure 6-44 and described in Table 6-51.
Return to the Summary Table.
Zone 1 Grab Flash Status Register 1

Figure 6-44. Z1_GRABSECT1R Register

31 30 29 28 27 26 25 24
RESERVED GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 6-51. Z1_GRABSECT1R Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z1_GRABSECT1[27:26] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 13 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 13 to Zone1.
10 : No request for CPU1 Flash Sector 13
11 : No request for CPU1 Flash Sector 13 when this zone is
UNLOCKED. Else CPU1 Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z1_GRABSECT1[25:24] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 12 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 12 to Zone1.
10 : No request for CPU1 Flash Sector 12
11 : No request for CPU1 Flash Sector 12 when this zone is
UNLOCKED. Else CPU1 Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z1_GRABSECT1[23:22] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 11 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 11 to Zone1.
10 : No request for CPU1 Flash Sector 11
11 : No request for CPU1 Flash Sector 11 when this zone is
UNLOCKED. Else CPU1 Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z1_GRABSECT1[21:20] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 10 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 10 to Zone1.
10 : No request for CPU1 Flash Sector 10
11 : No request for CPU1 Flash Sector 10 when this zone is
UNLOCKED. Else CPU1 Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-51. Z1_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z1_GRABSECT1[19:18] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 9 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 9 to Zone1.
10 : No request for CPU1 Flash Sector 9
11 : No request for CPU1 Flash Sector 9 when this zone is
UNLOCKED. Else CPU1 Flash Sector 9 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z1_GRABSECT1[17:16] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 8 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 8 to Zone1.
10 : No request for CPU1 Flash Sector 8
11 : No request for CPU1 Flash Sector 8 when this zone is
UNLOCKED. Else CPU1 Flash Sector 8 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z1_GRABSECT1[15:14] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 7 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 7 to Zone1.
10 : No request for CPU1 Flash Sector 7
11 : No request for CPU1 Flash Sector 7 when this zone is
UNLOCKED. Else CPU1 Flash Sector 7 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z1_GRABSECT1[13:12] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 6 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 6 to Zone1.
10 : No request for CPU1 Flash Sector 6
11 : No request for CPU1 Flash Sector 6 when this zone is
UNLOCKED. Else CPU1 Flash Sector 6 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z1_GRABSECT1[11:10] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 5 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 5 to Zone1.
10 : No request for CPU1 Flash Sector 5
11 : No request for CPU1 Flash Sector 5 when this zone is
UNLOCKED. Else CPU1 Flash Sector 5 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z1_GRABSECT1[9:8] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 4 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 4 to Zone1.
10 : No request for CPU1 Flash Sector 4
11 : No request for CPU1 Flash Sector 4 when this zone is
UNLOCKED. Else CPU1 Flash Sector 4 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z1_GRABSECT1[7:6] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 3 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 3 to Zone1.
10 : No request for CPU1 Flash Sector 3
11 : No request for CPU1 Flash Sector 3 when this zone is
UNLOCKED. Else CPU1 Flash Sector 3 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-51. Z1_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z1_GRABSECT1[5:4] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 2 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 2 to Zone1.
10 : No request for CPU1 Flash Sector 2
11 : No request for CPU1 Flash Sector 2 when this zone is
UNLOCKED. Else CPU1 Flash Sector 2 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z1_GRABSECT1[3:2] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 1 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 1 to Zone1.
10 : No request for CPU1 Flash Sector 1
11 : No request for CPU1 Flash Sector 1 when this zone is
UNLOCKED. Else CPU1 Flash Sector 1 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z1_GRABSECT1[1:0] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 0 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 0 to Zone1.
10 : No request for CPU1 Flash Sector 0
11 : No request for CPU1 Flash Sector 0 when this zone is
UNLOCKED. Else CPU1 Flash Sector 0 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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6.8.4.15 Z1_GRABSECT2R Register (Offset (x8) = 38h, Offset (x16) = 1Ch) [reset = 0h]
Z1_GRABSECT2R is shown in Figure 6-45 and described in Table 6-52.
Return to the Summary Table.
Zone 1 Grab Flash Status Register 2

Figure 6-45. Z1_GRABSECT2R Register

31 30 29 28 27 26 25 24
RESERVED GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 6-52. Z1_GRABSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z1_GRABSECT2[27:26] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 13 is inaccessible.
01 : Request to allocate CM Flash Sector 13 to Zone1.
10 : No request for CM Flash Sector 13
11 : No request for CM Flash Sector 13 when this zone is
UNLOCKED. Else CM Flash Sector 13 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z1_GRABSECT2[25:24] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 12 is inaccessible.
01 : Request to allocate CM Flash Sector 12 to Zone1.
10 : No request for CM Flash Sector 12
11 : No request for CM Flash Sector 12 when this zone is
UNLOCKED. Else CM Flash Sector 12 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z1_GRABSECT2[23:22] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 11 is inaccessible.
01 : Request to allocate CM Flash Sector 11 to Zone1.
10 : No request for CM Flash Sector 11
11 : No request for CM Flash Sector 11 when this zone is
UNLOCKED. Else CM Flash Sector 11 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z1_GRABSECT2[21:20] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 10 is inaccessible.
01 : Request to allocate CM Flash Sector 10 to Zone1.
10 : No request for CM Flash Sector 10
11 : No request for CM Flash Sector 10 when this zone is
UNLOCKED. Else CM Flash Sector 10 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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Table 6-52. Z1_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z1_GRABSECT2[19:18] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 9 is inaccessible.
01 : Request to allocate CM Flash Sector 9 to Zone1.
10 : No request for CM Flash Sector 9
11 : No request for CM Flash Sector 9 when this zone is
UNLOCKED. Else CM Flash Sector 9 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z1_GRABSECT2[17:16] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 8 is inaccessible.
01 : Request to allocate CM Flash Sector 8 to Zone1.
10 : No request for CM Flash Sector 8
11 : No request for CM Flash Sector 8 when this zone is
UNLOCKED. Else CM Flash Sector 8 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z1_GRABSECT2[15:14] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 7 is inaccessible.
01 : Request to allocate CM Flash Sector 7 to Zone1.
10 : No request for CM Flash Sector 7
11 : No request for CM Flash Sector 7 when this zone is
UNLOCKED. Else CM Flash Sector 7 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z1_GRABSECT2[13:12] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 6 is inaccessible.
01 : Request to allocate CM Flash Sector 6 to Zone1.
10 : No request for CM Flash Sector 6
11 : No request for CM Flash Sector 6 when this zone is
UNLOCKED. Else CM Flash Sector 6 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z1_GRABSECT2[11:10] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 5 is inaccessible.
01 : Request to allocate CM Flash Sector 5 to Zone1.
10 : No request for CM Flash Sector 5
11 : No request for CM Flash Sector 5 when this zone is
UNLOCKED. Else CM Flash Sector 5 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z1_GRABSECT2[9:8] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 4 is inaccessible.
01 : Request to allocate CM Flash Sector 4 to Zone1.
10 : No request for CM Flash Sector 4
11 : No request for CM Flash Sector 4 when this zone is
UNLOCKED. Else CM Flash Sector 4 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z1_GRABSECT2[7:6] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 3 is inaccessible.
01 : Request to allocate CM Flash Sector 3 to Zone1.
10 : No request for CM Flash Sector 3
11 : No request for CM Flash Sector 3 when this zone is
UNLOCKED. Else CM Flash Sector 3 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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Table 6-52. Z1_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z1_GRABSECT2[5:4] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 2 is inaccessible.
01 : Request to allocate CM Flash Sector 2 to Zone1.
10 : No request for CM Flash Sector 2
11 : No request for CM Flash Sector 2 when this zone is
UNLOCKED. Else CM Flash Sector 2 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z1_GRABSECT2[3:2] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 1 is inaccessible.
01 : Request to allocate CM Flash Sector 1 to Zone1.
10 : No request for CM Flash Sector 1
11 : No request for CM Flash Sector 1 when this zone is
UNLOCKED. Else CM Flash Sector 1 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z1_GRABSECT2[1:0] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 0 is inaccessible.
01 : Request to allocate CM Flash Sector 0 to Zone1.
10 : No request for CM Flash Sector 0
11 : No request for CM Flash Sector 0 when this zone is
UNLOCKED. Else CM Flash Sector 0 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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6.8.4.16 Z1_GRABSECT3R Register (Offset (x8) = 3Ch, Offset (x16) = 1Eh) [reset = 0h]
Z1_GRABSECT3R is shown in Figure 6-46 and described in Table 6-53.
Return to the Summary Table.
Zone 1 Grab Flash Status Register 3

Figure 6-46. Z1_GRABSECT3R Register

31 30 29 28 27 26 25 24
RESERVED GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 6-53. Z1_GRABSECT3R Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z1_GRABSECT3[27:26] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 13 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 13 to Zone1.
10 : No request for CPU2 Flash Sector 13
11 : No request for CPU2 Flash Sector 13 when this zone is
UNLOCKED. Else CPU2 Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z1_GRABSECT3[25:24] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 12 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 12 to Zone1.
10 : No request for CPU2 Flash Sector 12
11 : No request for CPU2 Flash Sector 12 when this zone is
UNLOCKED. Else CPU2 Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z1_GRABSECT3[23:22] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 11 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 11 to Zone1.
10 : No request for CPU2 Flash Sector 11
11 : No request for CPU2 Flash Sector 11 when this zone is
UNLOCKED. Else CPU2 Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z1_GRABSECT3[21:20] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 10 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 10 to Zone1.
10 : No request for CPU2 Flash Sector 10
11 : No request for CPU2 Flash Sector 10 when this zone is
UNLOCKED. Else CPU2 Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-53. Z1_GRABSECT3R Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z1_GRABSECT3[19:18] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 9 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 9 to Zone1.
10 : No request for CPU2 Flash Sector 9
11 : No request for CPU2 Flash Sector 9 when this zone is
UNLOCKED. Else CPU2 Flash Sector 9 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z1_GRABSECT3[17:16] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 8 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 8 to Zone1.
10 : No request for CPU2 Flash Sector 8
11 : No request for CPU2 Flash Sector 8 when this zone is
UNLOCKED. Else CPU2 Flash Sector 8 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z1_GRABSECT3[15:14] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 7 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 7 to Zone1.
10 : No request for CPU2 Flash Sector 7
11 : No request for CPU2 Flash Sector 7 when this zone is
UNLOCKED. Else CPU2 Flash Sector 7 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z1_GRABSECT3[13:12] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 6 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 6 to Zone1.
10 : No request for CPU2 Flash Sector 6
11 : No request for CPU2 Flash Sector 6 when this zone is
UNLOCKED. Else CPU2 Flash Sector 6 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z1_GRABSECT3[11:10] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 5 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 5 to Zone1.
10 : No request for CPU2 Flash Sector 5
11 : No request for CPU2 Flash Sector 5 when this zone is
UNLOCKED. Else CPU2 Flash Sector 5 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z1_GRABSECT3[9:8] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 4 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 4 to Zone1.
10 : No request for CPU2 Flash Sector 4
11 : No request for CPU2 Flash Sector 4 when this zone is
UNLOCKED. Else CPU2 Flash Sector 4 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z1_GRABSECT3[7:6] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 3 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 3 to Zone1.
10 : No request for CPU2 Flash Sector 3
11 : No request for CPU2 Flash Sector 3 when this zone is
UNLOCKED. Else CPU2 Flash Sector 3 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-53. Z1_GRABSECT3R Register Field Descriptions (continued)

Bit Field Type Reset Description
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z1_GRABSECT3[5:4] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 2 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 2 to Zone1.
10 : No request for CPU2 Flash Sector 2
11 : No request for CPU2 Flash Sector 2 when this zone is
UNLOCKED. Else CPU2 Flash Sector 2 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z1_GRABSECT3[3:2] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 1 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 1 to Zone1.
10 : No request for CPU2 Flash Sector 1
11 : No request for CPU2 Flash Sector 1 when this zone is
UNLOCKED. Else CPU2 Flash Sector 1 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z1_GRABSECT3[1:0] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 0 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 0 to Zone1.
10 : No request for CPU2 Flash Sector 0
11 : No request for CPU2 Flash Sector 0 when this zone is
UNLOCKED. Else CPU2 Flash Sector 0 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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6.8.4.17 Z1_GRABRAM1R Register (Offset (x8) = 40h, Offset (x16) = 20h) [reset = 0h]
Z1_GRABRAM1R is shown in Figure 6-47 and described in Table 6-54.
Return to the Summary Table.
Zone 1 Grab RAM Status Register 1

Figure 6-47. Z1_GRABRAM1R Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED GRAB_RAM9 GRAB_RAM8
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
GRAB_RAM3 GRAB_RAM2 GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h R-0h

Table 6-54. Z1_GRABRAM1R Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 GRAB_RAM9 R 0h Value in this field gets loaded from Z1_GRABRAM1[19:18] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 D1 RAM is inaccessible.
01 : Request to allocate CPU1 D1 RAM to Zone1.
10 : No request for CPU1 D1 RAM
11 : No request for CPU1 D1 RAM when this zone is UNLOCKED.
Else CPU1 D1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_RAM8 R 0h Value in this field gets loaded from Z1_GRABRAM1[17:16] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 D0 RAM is inaccessible.
01 : Request to allocate CPU1 D0 RAM to Zone1.
10 : No request for CPU1 D0 RAM
11 : No request for CPU1 D0 RAM when this zone is UNLOCKED.
Else CPU1 D0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z1_GRABRAM1[15:14] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS7 RAM is inaccessible.
01 : Request to allocate CPU1 LS7 RAM to Zone1.
10 : No request for CPU1 LS7 RAM
11 : No request for CPU1 LS7 RAM when this zone is UNLOCKED.
Else CPU1 LS7 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z1_GRABRAM1[13:12] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS6 RAM is inaccessible.
01 : Request to allocate CPU1 LS6 RAM to Zone1.
10 : No request for CPU1 LS6 RAM
11 : No request for CPU1 LS6 RAM when this zone is UNLOCKED.
Else CPU1 LS6 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-54. Z1_GRABRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z1_GRABRAM1[11:10] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS5 RAM is inaccessible.
01 : Request to allocate CPU1 LS5 RAM to Zone1.
10 : No request for CPU1 LS5 RAM
11 : No request for CPU1 LS5 RAM when this zone is UNLOCKED.
Else CPU1 LS5 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z1_GRABRAM1[9:8] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS4 RAM is inaccessible.
01 : Request to allocate CPU1 LS4 RAM to Zone1.
10 : No request for CPU1 LS4 RAM
11 : No request for CPU1 LS4 RAM when this zone is UNLOCKED.
Else CPU1 LS4 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-6 GRAB_RAM3 R 0h Value in this field gets loaded from Z1_GRABRAM1[7:6] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS3 RAM is inaccessible.
01 : Request to allocate CPU1 LS3 RAM to Zone1.
10 : No request for CPU1 LS3 RAM
11 : No request for CPU1 LS3 RAM when this zone is UNLOCKED.
Else CPU1 LS3 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_RAM2 R 0h Value in this field gets loaded from Z1_GRABRAM1[5:4] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS2 RAM is inaccessible.
01 : Request to allocate CPU1 LS2 RAM to Zone1.
10 : No request for CPU1 LS2 RAM
11 : No request for CPU1 LS2 RAM when this zone is UNLOCKED.
Else CPU1 LS2 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z1_GRABRAM1[3:2] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS1 RAM is inaccessible.
01 : Request to allocate CPU1 LS1 RAM to Zone1.
10 : No request for CPU1 LS1 RAM
11 : No request for CPU1 LS1 RAM when this zone is UNLOCKED.
Else CPU1 LS1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z1_GRABRAM1[1:0] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS0 RAM is inaccessible.
01 : Request to allocate CPU1 LS0 RAM to Zone1.
10 : No request for CPU1 LS0 RAM
11 : No request for CPU1 LS0 RAM when this zone is UNLOCKED.
Else CPU1 LS0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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6.8.4.18 Z1_GRABRAM2R Register (Offset (x8) = 44h, Offset (x16) = 22h) [reset = 0h]
Z1_GRABRAM2R is shown in Figure 6-48 and described in Table 6-55.
Return to the Summary Table.
Zone 1 Grab RAM Status Register 2

Figure 6-48. Z1_GRABRAM2R Register

31 30 29 28 27 26 25 24
GRAB_RAM15 GRAB_RAM14 GRAB_RAM13 GRAB_RAM12
R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
GRAB_RAM11 GRAB_RAM10 GRAB_RAM9 GRAB_RAM8
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h

Table 6-55. Z1_GRABRAM2R Register Field Descriptions

Bit Field Type Reset Description
31-30 GRAB_RAM15 R 0h Value in this field gets loaded from Z1_GRABRAM2[31:30] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the higher addressed half of
CPU2TOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
29-28 GRAB_RAM14 R 0h Value in this field gets loaded from Z1_GRABRAM2[29:28] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the lower addressed half of
CPU2TOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
27-26 GRAB_RAM13 R 0h Value in this field gets loaded from Z1_GRABRAM2[27:26] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the higher addressed half of
CPU1TOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-55. Z1_GRABRAM2R Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 GRAB_RAM12 R 0h Value in this field gets loaded from Z1_GRABRAM2[25:24] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the lower addressed half of
CPU1TOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
23-22 GRAB_RAM11 R 0h Value in this field gets loaded from Z1_GRABRAM2[23:22] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the higher addressed half of
CMTOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
21-20 GRAB_RAM10 R 0h Value in this field gets loaded from Z1_GRABRAM2[21:20] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the lower addressed half of
CMTOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
19-18 GRAB_RAM9 R 0h Value in this field gets loaded from Z1_GRABRAM2[19:18] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the higher addressed half of
CPU2TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_RAM8 R 0h Value in this field gets loaded from Z1_GRABRAM2[17:16] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the lower addressed half of
CPU2TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z1_GRABRAM2[15:14] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the higher addressed half of
CMTOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-55. Z1_GRABRAM2R Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z1_GRABRAM2[13:12] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the lower addressed half of
CMTOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z1_GRABRAM2[11:10] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the higher addressed half of
CPU1TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z1_GRABRAM2[9:8] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the lower addressed half of
CPU1TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-4 RESERVED R 0h Reserved
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z1_GRABRAM2[3:2] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
00 : Invalid. CM C1 RAM is inaccessible.
01 : Request to allocate CM C1 RAM to Zone1.
10 : No request for CM C1 RAM
11 : No request for CM C1 RAM when this zone is UNLOCKED. Else
CM C1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z1_GRABRAM2[1:0] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
00 : Invalid. CM C0 RAM is inaccessible.
01 : Request to allocate CM C0 RAM to Zone1.
10 : No request for CM C0 RAM
11 : No request for CM C0 RAM when this zone is UNLOCKED. Else
CM C0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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6.8.4.19 Z1_GRABRAM3R Register (Offset (x8) = 48h, Offset (x16) = 24h) [reset = 0h]
Z1_GRABRAM3R is shown in Figure 6-49 and described in Table 6-56.
Return to the Summary Table.
Zone 1 Grab RAM Status Register 3

Figure 6-49. Z1_GRABRAM3R Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED GRAB_RAM9 GRAB_RAM8
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
GRAB_RAM3 GRAB_RAM2 GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h R-0h

Table 6-56. Z1_GRABRAM3R Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 GRAB_RAM9 R 0h Value in this field gets loaded from Z1_GRABRAM3[19:18] when a
read is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 D1 RAM is inaccessible.
01 : Request to allocate CPU2 D1 RAM to Zone1.
10 : No request for CPU2 D1 RAM
11 : No request for CPU2 D1 RAM when this zone is UNLOCKED.
Else CPU2 D1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_RAM8 R 0h Value in this field gets loaded from Z1_GRABRAM3[17:16] when a
read is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 D0 RAM is inaccessible.
01 : Request to allocate CPU2 D0 RAM to Zone1.
10 : No request for CPU2 D0 RAM
11 : No request for CPU2 D0 RAM when this zone is UNLOCKED.
Else CPU2 D0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z1_GRABRAM3[15:14] when a
read is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS7 RAM is inaccessible.
01 : Request to allocate CPU2 LS7 RAM to Zone1.
10 : No request for CPU2 LS7 RAM
11 : No request for CPU2 LS7 RAM when this zone is UNLOCKED.
Else CPU2 LS7 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z1_GRABRAM3[13:12] when a
read is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS6 RAM is inaccessible.
01 : Request to allocate CPU2 LS6 RAM to Zone1.
10 : No request for CPU2 LS6 RAM
11 : No request for CPU2 LS6 RAM when this zone is UNLOCKED.
Else CPU2 LS6 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-56. Z1_GRABRAM3R Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z1_GRABRAM3[11:10] when a
read is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS5 RAM is inaccessible.
01 : Request to allocate CPU2 LS5 RAM to Zone1.
10 : No request for CPU2 LS5 RAM
11 : No request for CPU2 LS5 RAM when this zone is UNLOCKED.
Else CPU2 LS5 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z1_GRABRAM3[9:8] when a
read is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS4 RAM is inaccessible.
01 : Request to allocate CPU2 LS4 RAM to Zone1.
10 : No request for CPU2 LS4 RAM
11 : No request for CPU2 LS4 RAM when this zone is UNLOCKED.
Else CPU2 LS4 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-6 GRAB_RAM3 R 0h Value in this field gets loaded from Z1_GRABRAM3[7:6] when a
read is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS3 RAM is inaccessible.
01 : Request to allocate CPU2 LS3 RAM to Zone1.
10 : No request for CPU2 LS3 RAM
11 : No request for CPU2 LS3 RAM when this zone is UNLOCKED.
Else CPU2 LS3 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_RAM2 R 0h Value in this field gets loaded from Z1_GRABRAM3[5:4] when a
read is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS2 RAM is inaccessible.
01 : Request to allocate CPU2 LS2 RAM to Zone1.
10 : No request for CPU2 LS2 RAM
11 : No request for CPU2 LS2 RAM when this zone is UNLOCKED.
Else CPU2 LS2 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z1_GRABRAM3[3:2] when a
read is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS1 RAM is inaccessible.
01 : Request to allocate CPU2 LS1 RAM to Zone1.
10 : No request for CPU2 LS1 RAM
11 : No request for CPU2 LS1 RAM when this zone is UNLOCKED.
Else CPU2 LS1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z1_GRABRAM3[1:0] when a
read is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS0 RAM is inaccessible.
01 : Request to allocate CPU2 LS0 RAM to Zone1.
10 : No request for CPU2 LS0 RAM
11 : No request for CPU2 LS0 RAM when this zone is UNLOCKED.
Else CPU2 LS0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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6.8.4.20 Z1_EXEONLYSECT1R Register (Offset (x8) = 4Ch, Offset (x16) = 26h) [reset = 0h]
Z1_EXEONLYSECT1R is shown in Figure 6-50 and described in Table 6-57.
Return to the Summary Table.
Zone 1 Execute Only Flash Status Register 1

Figure 6-50. Z1_EXEONLYSECT1R Register

31 30 29 28 27 26 25 24
RESERVED EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM
_SECT13 _SECT12 _SECT11 _SECT10 _SECT9 _SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM
_SECT7 _SECT6 _SECT5 _SECT4 _SECT3 _SECT2 _SECT1 _SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U1_SECT13 U1_SECT12 U1_SECT11 U1_SECT10 U1_SECT9 U1_SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U1_SECT7 U1_SECT6 U1_SECT5 U1_SECT4 U1_SECT3 U1_SECT2 U1_SECT1 U1_SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-57. Z1_EXEONLYSECT1R Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R 0h Reserved
29 EXEONLY_CM_SECT13 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[29] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 13 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 13 (only
if it's allocated to Zone1)
Reset type: SYSRSn
28 EXEONLY_CM_SECT12 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[28] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 12 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 12 (only
if it's allocated to Zone1)
Reset type: SYSRSn
27 EXEONLY_CM_SECT11 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[27] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 11 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 11 (only
if it's allocated to Zone1)
Reset type: SYSRSn
26 EXEONLY_CM_SECT10 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[26] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 10 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 10 (only
if it's allocated to Zone1)
Reset type: SYSRSn

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Table 6-57. Z1_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
25 EXEONLY_CM_SECT9 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[25] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 9 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 9 (only if
it's allocated to Zone1)
Reset type: SYSRSn
24 EXEONLY_CM_SECT8 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[24] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 8 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 8 (only if
it's allocated to Zone1)
Reset type: SYSRSn
23 EXEONLY_CM_SECT7 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[23] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 7 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 7 (only if
it's allocated to Zone1)
Reset type: SYSRSn
22 EXEONLY_CM_SECT6 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[22] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 6 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 6 (only if
it's allocated to Zone1)
Reset type: SYSRSn
21 EXEONLY_CM_SECT5 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[21] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 5 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 5 (only if
it's allocated to Zone1)
Reset type: SYSRSn
20 EXEONLY_CM_SECT4 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[20] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 4 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 4 (only if
it's allocated to Zone1)
Reset type: SYSRSn
19 EXEONLY_CM_SECT3 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[19] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 3 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 3 (only if
it's allocated to Zone1)
Reset type: SYSRSn
18 EXEONLY_CM_SECT2 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[18] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 2 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 2 (only if
it's allocated to Zone1)
Reset type: SYSRSn
17 EXEONLY_CM_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[17] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 1 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 1 (only if
it's allocated to Zone1)
Reset type: SYSRSn

820 Dual Code Security Module (DCSM) SPRUII0B – May 2019 – Revised May 2020
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Table 6-57. Z1_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
16 EXEONLY_CM_SECT0 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[16] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 0 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 0 (only if
it's allocated to Zone1)
Reset type: SYSRSn
15-14 RESERVED R 0h Reserved
13 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[13] when a
3 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 13
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 13
(only if it's allocated to Zone1)
Reset type: SYSRSn
12 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[12] when a
2 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 12
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 12
(only if it's allocated to Zone1)
Reset type: SYSRSn
11 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[11] when a
1 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 11
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 11
(only if it's allocated to Zone1)
Reset type: SYSRSn
10 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[10] when a
0 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 10
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 10
(only if it's allocated to Zone1)
Reset type: SYSRSn
9 EXEONLY_CPU1_SECT9 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[9] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 9 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 9
(only if it's allocated to Zone1)
Reset type: SYSRSn
8 EXEONLY_CPU1_SECT8 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[8] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 8 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 8
(only if it's allocated to Zone1)
Reset type: SYSRSn
7 EXEONLY_CPU1_SECT7 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[7] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 7 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 7
(only if it's allocated to Zone1)
Reset type: SYSRSn

SPRUII0B – May 2019 – Revised May 2020 Dual Code Security Module (DCSM) 821
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Table 6-57. Z1_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
6 EXEONLY_CPU1_SECT6 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[6] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 6 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 6
(only if it's allocated to Zone1)
Reset type: SYSRSn
5 EXEONLY_CPU1_SECT5 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[5] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 5 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 5
(only if it's allocated to Zone1)
Reset type: SYSRSn
4 EXEONLY_CPU1_SECT4 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[4] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 4 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 4
(only if it's allocated to Zone1)
Reset type: SYSRSn
3 EXEONLY_CPU1_SECT3 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[3] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 3 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 3
(only if it's allocated to Zone1)
Reset type: SYSRSn
2 EXEONLY_CPU1_SECT2 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[2] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 2 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 2
(only if it's allocated to Zone1)
Reset type: SYSRSn
1 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[1] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 1 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 1
(only if it's allocated to Zone1)
Reset type: SYSRSn
0 EXEONLY_CPU1_SECT0 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[0] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 0 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 0
(only if it's allocated to Zone1)
Reset type: SYSRSn

822 Dual Code Security Module (DCSM) SPRUII0B – May 2019 – Revised May 2020
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6.8.4.21 Z1_EXEONLYSECT2R Register (Offset (x8) = 50h, Offset (x16) = 28h) [reset = 0h]
Z1_EXEONLYSECT2R is shown in Figure 6-51 and described in Table 6-58.
Return to the Summary Table.
Zone 1 Execute Only Flash Status Register 2

Figure 6-51. Z1_EXEONLYSECT2R Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U2_SECT13 U2_SECT12 U2_SECT11 U2_SECT10 U2_SECT9 U2_SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U2_SECT7 U2_SECT6 U2_SECT5 U2_SECT4 U2_SECT3 U2_SECT2 U2_SECT1 U2_SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-58. Z1_EXEONLYSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0h Reserved
13 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[13] when a
3 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 13
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 13
(only if it's allocated to Zone1)
Reset type: SYSRSn
12 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[12] when a
2 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 12
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 12
(only if it's allocated to Zone1)
Reset type: SYSRSn
11 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[11] when a
1 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 11
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 11
(only if it's allocated to Zone1)
Reset type: SYSRSn
10 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[10] when a
0 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 10
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 10
(only if it's allocated to Zone1)
Reset type: SYSRSn

SPRUII0B – May 2019 – Revised May 2020 Dual Code Security Module (DCSM) 823
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Table 6-58. Z1_EXEONLYSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
9 EXEONLY_CPU2_SECT9 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[9] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 9 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 9
(only if it's allocated to Zone1)
Reset type: SYSRSn
8 EXEONLY_CPU2_SECT8 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[8] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 8 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 8
(only if it's allocated to Zone1)
Reset type: SYSRSn
7 EXEONLY_CPU2_SECT7 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[7] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 7 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 7
(only if it's allocated to Zone1)
Reset type: SYSRSn
6 EXEONLY_CPU2_SECT6 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[6] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 6 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 6
(only if it's allocated to Zone1)
Reset type: SYSRSn
5 EXEONLY_CPU2_SECT5 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[5] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 5 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 5
(only if it's allocated to Zone1)
Reset type: SYSRSn
4 EXEONLY_CPU2_SECT4 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[4] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 4 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 4
(only if it's allocated to Zone1)
Reset type: SYSRSn
3 EXEONLY_CPU2_SECT3 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[3] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 3 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 3
(only if it's allocated to Zone1)
Reset type: SYSRSn
2 EXEONLY_CPU2_SECT2 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[2] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 2 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 2
(only if it's allocated to Zone1)
Reset type: SYSRSn
1 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[1] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 1 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 1
(only if it's allocated to Zone1)
Reset type: SYSRSn

824 Dual Code Security Module (DCSM) SPRUII0B – May 2019 – Revised May 2020
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Table 6-58. Z1_EXEONLYSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
0 EXEONLY_CPU2_SECT0 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[0] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 0 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 0
(only if it's allocated to Zone1)
Reset type: SYSRSn

SPRUII0B – May 2019 – Revised May 2020 Dual Code Security Module (DCSM) 825
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6.8.4.22 Z1_EXEONLYRAM1R Register (Offset (x8) = 54h, Offset (x16) = 2Ah) [reset = 0h]
Z1_EXEONLYRAM1R is shown in Figure 6-52 and described in Table 6-59.
Return to the Summary Table.
Zone 1 Execute Only RAM Status Register 1

Figure 6-52. Z1_EXEONLYRAM1R Register

31 30 29 28 27 26 25 24
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M31 M30 M29 M28 M27 M26 M25 M24
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
EXEONLY_RA EXEONLY_RA RESERVED EXEONLY_RA EXEONLY_RA
M23 M22 M17 M16
R-0h R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED EXEONLY_RA EXEONLY_RA
M9 M8
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M7 M6 M5 M4 M3 M2 M1 M0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-59. Z1_EXEONLYRAM1R Register Field Descriptions

Bit Field Type Reset Description
31 EXEONLY_RAM31 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[31] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS0 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS0 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
30 EXEONLY_RAM30 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[30] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS1 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS1 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
29 EXEONLY_RAM29 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[29] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS2 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS2 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
28 EXEONLY_RAM28 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[28] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS3 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS3 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn

826 Dual Code Security Module (DCSM) SPRUII0B – May 2019 – Revised May 2020
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Table 6-59. Z1_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
27 EXEONLY_RAM27 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[27] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS4 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS4 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
26 EXEONLY_RAM26 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[26] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS5 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS5 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
25 EXEONLY_RAM25 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[25] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS6 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS6 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
24 EXEONLY_RAM24 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[24] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS7 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS7 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
23 EXEONLY_RAM23 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[23] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 D0 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 D0 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
22 EXEONLY_RAM22 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[22] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 D1 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 D1 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
21-18 RESERVED R 0h Reserved
17 EXEONLY_RAM17 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[17] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CM C1 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CM C1 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
16 EXEONLY_RAM16 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[16] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CM C0 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CM C0 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved

SPRUII0B – May 2019 – Revised May 2020 Dual Code Security Module (DCSM) 827
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Table 6-59. Z1_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
9 EXEONLY_RAM9 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[9] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU1 D1 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 D1 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
8 EXEONLY_RAM8 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[8] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU1 D0 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 D0 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
7 EXEONLY_RAM7 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[7] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS7 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS7 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
6 EXEONLY_RAM6 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[6] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS6 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS6 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
5 EXEONLY_RAM5 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[5] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS5 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS5 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
4 EXEONLY_RAM4 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[4] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS4 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS4 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
3 EXEONLY_RAM3 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[3] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS3 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS3 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
2 EXEONLY_RAM2 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[2] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS2 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS2 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
1 EXEONLY_RAM1 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[1] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS1 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS1 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn

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Table 6-59. Z1_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
0 EXEONLY_RAM0 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[0] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS0 RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS0 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn

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6.8.4.23 Z1_JTAGKEY0 Register (Offset (x8) = 5Ch, Offset (x16) = 2Eh) [reset = 0h]
Z1_JTAGKEY0 is shown in Figure 6-53 and described in Table 6-60.
Return to the Summary Table.
JTAG Unlock Key Register 0

Figure 6-53. Z1_JTAGKEY0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY0
R-0h

Table 6-60. Z1_JTAGKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY0 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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6.8.4.24 Z1_JTAGKEY1 Register (Offset (x8) = 60h, Offset (x16) = 30h) [reset = 0h]
Z1_JTAGKEY1 is shown in Figure 6-54 and described in Table 6-61.
Return to the Summary Table.
JTAG Unlock Key Register 1

Figure 6-54. Z1_JTAGKEY1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY1
R-0h

Table 6-61. Z1_JTAGKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY1 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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6.8.4.25 Z1_JTAGKEY2 Register (Offset (x8) = 64h, Offset (x16) = 32h) [reset = 0h]
Z1_JTAGKEY2 is shown in Figure 6-55 and described in Table 6-62.
Return to the Summary Table.
JTAG Unlock Key Register 2

Figure 6-55. Z1_JTAGKEY2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY2
R-0h

Table 6-62. Z1_JTAGKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY2 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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6.8.4.26 Z1_JTAGKEY3 Register (Offset (x8) = 68h, Offset (x16) = 34h) [reset = 0h]
Z1_JTAGKEY3 is shown in Figure 6-56 and described in Table 6-63.
Return to the Summary Table.
JTAG Unlock Key Register 3

Figure 6-56. Z1_JTAGKEY3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY3
R-0h

Table 6-63. Z1_JTAGKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY3 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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6.8.4.27 Z1_CMACKEY0 Register (Offset (x8) = 6Ch, Offset (x16) = 36h) [reset = 0h]
Z1_CMACKEY0 is shown in Figure 6-57 and described in Table 6-64.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 0

Figure 6-57. Z1_CMACKEY0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY0
R-0h

Table 6-64. Z1_CMACKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY0 R 0h Value in this field gets loaded from CMACKEY0 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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6.8.4.28 Z1_CMACKEY1 Register (Offset (x8) = 70h, Offset (x16) = 38h) [reset = 0h]
Z1_CMACKEY1 is shown in Figure 6-58 and described in Table 6-65.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 1

Figure 6-58. Z1_CMACKEY1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY1
R-0h

Table 6-65. Z1_CMACKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY1 R 0h Value in this field gets loaded from CMACKEY1 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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6.8.4.29 Z1_CMACKEY2 Register (Offset (x8) = 74h, Offset (x16) = 3Ah) [reset = 0h]
Z1_CMACKEY2 is shown in Figure 6-59 and described in Table 6-66.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 2

Figure 6-59. Z1_CMACKEY2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY2
R-0h

Table 6-66. Z1_CMACKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY2 R 0h Value in this field gets loaded from CMACKEY2 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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6.8.4.30 Z1_CMACKEY3 Register (Offset (x8) = 78h, Offset (x16) = 3Ch) [reset = 0h]
Z1_CMACKEY3 is shown in Figure 6-60 and described in Table 6-67.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 3

Figure 6-60. Z1_CMACKEY3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY3
R-0h

Table 6-67. Z1_CMACKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY3 R 0h Value in this field gets loaded from CMACKEY3 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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6.8.5 DCSM_Z2_OTP Registers

Table 6-68 lists the DCSM_Z2_OTP registers. All register offset addresses not listed in Table 6-68 should
be considered as reserved locations and the register contents should not be modified.

Table 6-68. DCSM_Z2_OTP Registers

Offset Acronym Register Name Write Protection Section
0h Z2OTP_LINKPOINTER1 Zone 2 Link Pointer1 Go
2h Z2OTP_LINKPOINTER2 Zone 2 Link Pointer2 Go
4h Z2OTP_LINKPOINTER3 Zone 2 Link Pointer3 Go
8h Z2OTP_GPREG1 Zone 2 General Purpose Register 1 Go
Ah Z2OTP_GPREG2 Zone 2 General Purpose Register 2 Go
Ch Z2OTP_GPREG3 Zone 2 General Purpose Register 3 Go
Eh Z2OTP_GPREG4 Zone 2 General Purpose Register 4 Go
10h Z2OTP_PSWDLOCK Secure Password Lock Go
12h Z2OTP_CRCLOCK Secure CRC Lock Go

Complex bit access types are encoded to fit into small table cells. Table 6-69 shows the codes that are
used for access types in this section.

Table 6-69. DCSM_Z2_OTP Access Type Codes

Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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6.8.5.1 Z2OTP_LINKPOINTER1 Register (Offset = 0h) [reset = FFFFFFFFh]

Z2OTP_LINKPOINTER1 is shown in Figure 6-61 and described in Table 6-70.
Return to the Summary Table.
Zone 2 Link Pointer1

Figure 6-61. Z2OTP_LINKPOINTER1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER1
R-FFFFFFFFh

Table 6-70. Z2OTP_LINKPOINTER1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_LINKPOINTER1 R FFFFFFFFh Zone2 Link Pointer 1 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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6.8.5.2 Z2OTP_LINKPOINTER2 Register (Offset = 2h) [reset = FFFFFFFFh]

Z2OTP_LINKPOINTER2 is shown in Figure 6-62 and described in Table 6-71.
Return to the Summary Table.
Zone 2 Link Pointer2

Figure 6-62. Z2OTP_LINKPOINTER2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER2
R-FFFFFFFFh

Table 6-71. Z2OTP_LINKPOINTER2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_LINKPOINTER2 R FFFFFFFFh Zone2 Link Pointer 2 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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6.8.5.3 Z2OTP_LINKPOINTER3 Register (Offset = 4h) [reset = FFFFFFFFh]

Z2OTP_LINKPOINTER3 is shown in Figure 6-63 and described in Table 6-72.
Return to the Summary Table.
Zone 2 Link Pointer3

Figure 6-63. Z2OTP_LINKPOINTER3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER3
R-FFFFFFFFh

Table 6-72. Z2OTP_LINKPOINTER3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_LINKPOINTER3 R FFFFFFFFh Zone2 Link Pointer 3 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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6.8.5.4 Z2OTP_GPREG1 Register (Offset = 8h) [reset = FFFFFFFFh]

Z2OTP_GPREG1 is shown in Figure 6-64 and described in Table 6-73.
Return to the Summary Table.
Zone 2 General Purpose Register 1

Figure 6-64. Z2OTP_GPREG1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG1
R-FFFFFFFFh

Table 6-73. Z2OTP_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG1 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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6.8.5.5 Z2OTP_GPREG2 Register (Offset = Ah) [reset = FFFFFFFFh]

Z2OTP_GPREG2 is shown in Figure 6-65 and described in Table 6-74.
Return to the Summary Table.
Zone 2 General Purpose Register 2

Figure 6-65. Z2OTP_GPREG2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG2
R-FFFFFFFFh

Table 6-74. Z2OTP_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG2 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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6.8.5.6 Z2OTP_GPREG3 Register (Offset = Ch) [reset = FFFFFFFFh]

Z2OTP_GPREG3 is shown in Figure 6-66 and described in Table 6-75.
Return to the Summary Table.
Zone 2 General Purpose Register 3

Figure 6-66. Z2OTP_GPREG3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG3
R-FFFFFFFFh

Table 6-75. Z2OTP_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG3 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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6.8.5.7 Z2OTP_GPREG4 Register (Offset = Eh) [reset = FFFFFFFFh]

Z2OTP_GPREG4 is shown in Figure 6-67 and described in Table 6-76.
Return to the Summary Table.
Zone 2 General Purpose Register 4

Figure 6-67. Z2OTP_GPREG4 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG4
R-FFFFFFFFh

Table 6-76. Z2OTP_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG4 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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6.8.5.8 Z2OTP_PSWDLOCK Register (Offset = 10h) [reset = FFFFFFFFh]

Z2OTP_PSWDLOCK is shown in Figure 6-68 and described in Table 6-77.
Return to the Summary Table.
Secure Password Lock

Figure 6-68. Z2OTP_PSWDLOCK Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_PSWDLOCK
R-FFFFFFFFh

Table 6-77. Z2OTP_PSWDLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_PSWDLOCK R FFFFFFFFh Zone2 password lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-bit all-
1s, CSMPSWD will remain locked. Before shipping parts to
customers, TI would change the value of this location in such a way
that the ECC field remains all-1s and also LSB 4-bits remain
4'b1111.
Reset type: N/A

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6.8.5.9 Z2OTP_CRCLOCK Register (Offset = 12h) [reset = FFFFFFFFh]

Z2OTP_CRCLOCK is shown in Figure 6-69 and described in Table 6-78.
Return to the Summary Table.
Secure CRC Lock

Figure 6-69. Z2OTP_CRCLOCK Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_CRCLOCK
R-FFFFFFFFh

Table 6-78. Z2OTP_CRCLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_CRCLOCK R FFFFFFFFh Zone2 CRC lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-bit all-
1s, VCU will not have ability to calculate CRC on secured memory
content.. Before shipping parts to customers, TI would change the
value of this location in such a way that the ECC field remains all-1s
and also LSB 4-bits remain 4'b1111.
Reset type: N/A

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6.8.6 DCSM_Z2_REGS Registers

Table 6-79 lists the DCSM_Z2_REGS registers. All register offset addresses not listed in Table 6-79
should be considered as reserved locations and the register contents should not be modified.

Table 6-79. DCSM_Z2_REGS Registers

Offset Offset Acronym Register Name Write Section
(x8) (x16) Protection
0h 0h Z2_LINKPOINTER Zone 2 Link Pointer Go
4h 2h Z2_OTPSECLOCK Zone 2 OTP Secure Lock Go
Ch 6h Z2_LINKPOINTERERR Link Pointer Error Go
10h 8h Z2_GPREG1 Zone 2 General Purpose Register-1 Go
14h Ah Z2_GPREG2 Zone 2 General Purpose Register-2 Go
18h Ch Z2_GPREG3 Zone 2 General Purpose Register-3 Go
1Ch Eh Z2_GPREG4 Zone 2 General Purpose Register-4 Go
20h 10h Z2_CSMKEY0 Zone 2 CSM Key 0 Go
24h 12h Z2_CSMKEY1 Zone 2 CSM Key 1 Go
28h 14h Z2_CSMKEY2 Zone 2 CSM Key 2 Go
2Ch 16h Z2_CSMKEY3 Zone 2 CSM Key 3 Go
30h 18h Z2_CR Zone 2 CSM Control Register Go
34h 1Ah Z2_GRABSECT1R Zone 2 Grab Flash Status Register 1 Go
38h 1Ch Z2_GRABSECT2R Zone 2 Grab Flash Status Register 2 Go
3Ch 1Eh Z2_GRABSECT3R Zone 2 Grab Flash Status Register 3 Go
40h 20h Z2_GRABRAM1R Zone 2 Grab RAM Status Register 1 Go
44h 22h Z2_GRABRAM2R Zone 2 Grab RAM Status Register 2 Go
48h 24h Z2_GRABRAM3R Zone 2 Grab RAM Status Register 3 Go
4Ch 26h Z2_EXEONLYSECT1R Zone 2 Execute Only Flash Status Register Go
1
50h 28h Z2_EXEONLYSECT2R Zone 2 Execute Only Flash Status Register Go
2
54h 2Ah Z2_EXEONLYRAM1R Zone 2 Execute Only RAM Status Register 1 Go

Complex bit access types are encoded to fit into small table cells. Table 6-80 shows the codes that are
used for access types in this section.

Table 6-80. DCSM_Z2_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables

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Table 6-80. DCSM_Z2_REGS Access Type

Codes (continued)
Access Type Code Description
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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6.8.6.1 Z2_LINKPOINTER Register (Offset (x8) = 0h, Offset (x16) = 0h) [reset = FFFFC000h]
Z2_LINKPOINTER is shown in Figure 6-70 and described in Table 6-81.
Return to the Summary Table.
Zone 2 Link Pointer

Figure 6-70. Z2_LINKPOINTER Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LINKPOINTER
R-0003FFFFh R-0h

Table 6-81. Z2_LINKPOINTER Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0003FFFFh Reserved
13-0 LINKPOINTER R 0h This is resolved Link-Pointer value which is generated by looking at
the three physical Link-Pointer values loaded from OTP
Reset type: SYSRSn

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6.8.6.2 Z2_OTPSECLOCK Register (Offset (x8) = 4h, Offset (x16) = 2h) [reset = 1h]
Z2_OTPSECLOCK is shown in Figure 6-71 and described in Table 6-82.
Return to the Summary Table.
Zone 2 OTP Secure Lock

Figure 6-71. Z2_OTPSECLOCK Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED CRCLOCK
R-0h R-0h
7 6 5 4 3 2 1 0
PSWDLOCK RESERVED JTAGLOCK
R-0h R-0h R-1h

Table 6-82. Z2_OTPSECLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 RESERVED R 0h Reserved
11-8 CRCLOCK R 0h Value in this field gets loaded from Z2_CRCLOCK[3:0] when a read
is issued to address location of Z2_CRCLOCK in OTP.
1111 : VCU has ability to calculate CRC on secure memories.
Other Value : VCU doesn't have ability to calculate CRC on secure
memories.
Reset type: XRSn
7-4 PSWDLOCK R 0h Value in this field gets loaded from Z2_PSWDLOCK[3:0] when a
read is issued to address location of Z1_PSWDLOCK in OTP.
1111 : CSM password locations in OTP are not protected and can
be read from debugger as well as code running from anywhere.
Other Value : CSM password locations in OTP are protected and
can't be read without unlocking CSM of that zone.
Reset type: XRSn
3-1 RESERVED R 0h Reserved
0 JTAGLOCK R 1h Reflects the state of the JTAGLOCK feature.
0 : JTAG is not locked
1 : JTAG is locked
This bit is a copy of the Z1_OTPSECLOCK.JTAGLOCK bit.
Reset type: PORESETn

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6.8.6.3 Z2_LINKPOINTERERR Register (Offset (x8) = Ch, Offset (x16) = 6h) [reset = 0h]
Z2_LINKPOINTERERR is shown in Figure 6-72 and described in Table 6-83.
Return to the Summary Table.
Link Pointer Error

Figure 6-72. Z2_LINKPOINTERERR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED Z2_LINKPOINTERERR
R-0-0h R-0h

Table 6-83. Z2_LINKPOINTERERR Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R-0 0h Reserved
13-0 Z2_LINKPOINTERERR R 0h These bits indicate errors during formation of the resolved Link-
Pointer value after the three physical Link-Pointer values loaded of
OTP in flash.
0 : No Error.
Other : Error on bit positions which is set to 1.
Reset type: SYSRSn

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6.8.6.4 Z2_GPREG1 Register (Offset (x8) = 10h, Offset (x16) = 8h) [reset = 0h]
Z2_GPREG1 is shown in Figure 6-73 and described in Table 6-84.
Return to the Summary Table.
Zone 2 General Purpose Register-1

Figure 6-73. Z2_GPREG1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG1
R-0h

Table 6-84. Z2_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG1 R 0h This field gets loaded with the contents of Z2OTP_GPREG1
locations in Zone-2-USER-OTP when a dummy read is issued to that
address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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6.8.6.5 Z2_GPREG2 Register (Offset (x8) = 14h, Offset (x16) = Ah) [reset = 0h]
Z2_GPREG2 is shown in Figure 6-74 and described in Table 6-85.
Return to the Summary Table.
Zone 2 General Purpose Register-2

Figure 6-74. Z2_GPREG2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG2
R-0h

Table 6-85. Z2_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG2 R 0h This field gets loaded with the contents of Z2OTP_GPREG2
locations in Zone-2-USER-OTP when a dummy read is issued to that
address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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6.8.6.6 Z2_GPREG3 Register (Offset (x8) = 18h, Offset (x16) = Ch) [reset = 0h]
Z2_GPREG3 is shown in Figure 6-75 and described in Table 6-86.
Return to the Summary Table.
Zone 2 General Purpose Register-3

Figure 6-75. Z2_GPREG3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG3
R-0h

Table 6-86. Z2_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG3 R 0h This field gets loaded with the contents of Z2OTP_GPREG3
locations in Zone-2-USER-OTP when a dummy read is issued to that
address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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6.8.6.7 Z2_GPREG4 Register (Offset (x8) = 1Ch, Offset (x16) = Eh) [reset = 0h]
Z2_GPREG4 is shown in Figure 6-76 and described in Table 6-87.
Return to the Summary Table.
Zone 2 General Purpose Register-4

Figure 6-76. Z2_GPREG4 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG4
R-0h

Table 6-87. Z2_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG4 R 0h This field gets loaded with the contents of Z2OTP_GPREG4
locations in Zone-2-USER-OTP when a dummy read is issued to that
address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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6.8.6.8 Z2_CSMKEY0 Register (Offset (x8) = 20h, Offset (x16) = 10h) [reset = 0h]
Z2_CSMKEY0 is shown in Figure 6-77 and described in Table 6-88.
Return to the Summary Table.
Zone 2 CSM Key 0

Figure 6-77. Z2_CSMKEY0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY0
R/W-0h

Table 6-88. Z2_CSMKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY0 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD0, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.8.6.9 Z2_CSMKEY1 Register (Offset (x8) = 24h, Offset (x16) = 12h) [reset = 0h]
Z2_CSMKEY1 is shown in Figure 6-78 and described in Table 6-89.
Return to the Summary Table.
Zone 2 CSM Key 1

Figure 6-78. Z2_CSMKEY1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY1
R/W-0h

Table 6-89. Z2_CSMKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY1 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD1, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.8.6.10 Z2_CSMKEY2 Register (Offset (x8) = 28h, Offset (x16) = 14h) [reset = 0h]
Z2_CSMKEY2 is shown in Figure 6-79 and described in Table 6-90.
Return to the Summary Table.
Zone 2 CSM Key 2

Figure 6-79. Z2_CSMKEY2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY2
R/W-0h

Table 6-90. Z2_CSMKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY2 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD2, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.8.6.11 Z2_CSMKEY3 Register (Offset (x8) = 2Ch, Offset (x16) = 16h) [reset = 0h]
Z2_CSMKEY3 is shown in Figure 6-80 and described in Table 6-91.
Return to the Summary Table.
Zone 2 CSM Key 3

Figure 6-80. Z2_CSMKEY3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY3
R/W-0h

Table 6-91. Z2_CSMKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY3 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD3, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.8.6.12 Z2_CR Register (Offset (x8) = 30h, Offset (x16) = 18h) [reset = 00080000h]
Z2_CR is shown in Figure 6-81 and described in Table 6-92.
Return to the Summary Table.
Zone 2 CSM Control Register

Figure 6-81. Z2_CR Register

31 30 29 28 27 26 25 24
FORCESEC RESERVED
R-0/W-0h R-0h
23 22 21 20 19 18 17 16
ARMED UNSECURE ALLONE ALLZERO RESERVED
R-0h R-0h R-0h R-1h R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED
R-0-0h

Table 6-92. Z2_CR Register Field Descriptions

Bit Field Type Reset Description
31 FORCESEC R-0/W 0h A write '1' to this fields resets the state of zone. If zone is unlocked,
it'll lock(secure) the zone and also resets all the bits in this register.
Reset type: SYSRSn
30-24 RESERVED R 0h Reserved
22 ARMED R 0h 0 : Dummy read to CSM Password locations in OTP hasn't been
performed.
1 : Dummy read to CSM Password locations in OTP has been
performed.
Reset type: SYSRSn
21 UNSECURE R 0h Indiacates the state of Zone.
0 : Zone is in lock(secure) state.
1 : Zone is in unlock(unsecure) state.
Reset type: SYSRSn
20 ALLONE R 0h Indicates the state of CSM passwords.
0 : Zone CSM Passwords are not all ones.
1 : Zone CSM Passwords are all ones.
Reset type: SYSRSn
19 ALLZERO R 1h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all zeros.
1 : CSM Passwords are all zero and device is permanently locked.
Reset type: SYSRSn
18-16 RESERVED R 0h Reserved
15-4 RESERVED R-0 0h Reserved

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6.8.6.13 Z2_GRABSECT1R Register (Offset (x8) = 34h, Offset (x16) = 1Ah) [reset = 0h]
Z2_GRABSECT1R is shown in Figure 6-82 and described in Table 6-93.
Return to the Summary Table.
Zone 2 Grab Flash Status Register 1

Figure 6-82. Z2_GRABSECT1R Register

31 30 29 28 27 26 25 24
RESERVED GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 6-93. Z2_GRABSECT1R Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z2_GRABSECT1[27:26] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 13 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 13 to Zone2.
10 : No request for CPU1 Flash Sector 13
11 : No request for CPU1 Flash Sector 13 when this zone is
UNLOCKED. Else CPU1 Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z2_GRABSECT1[25:24] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 12 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 12 to Zone2.
10 : No request for CPU1 Flash Sector 12
11 : No request for CPU1 Flash Sector 12 when this zone is
UNLOCKED. Else CPU1 Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z2_GRABSECT1[23:22] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 11 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 11 to Zone2.
10 : No request for CPU1 Flash Sector 11
11 : No request for CPU1 Flash Sector 11 when this zone is
UNLOCKED. Else CPU1 Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z2_GRABSECT1[21:20] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 10 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 10 to Zone2.
10 : No request for CPU1 Flash Sector 10
11 : No request for CPU1 Flash Sector 10 when this zone is
UNLOCKED. Else CPU1 Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-93. Z2_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z2_GRABSECT1[19:18] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 9 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 9 to Zone2.
10 : No request for CPU1 Flash Sector 9
11 : No request for CPU1 Flash Sector 9 when this zone is
UNLOCKED. Else CPU1 Flash Sector 9 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z2_GRABSECT1[17:16] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 8 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 8 to Zone2.
10 : No request for CPU1 Flash Sector 8
11 : No request for CPU1 Flash Sector 8 when this zone is
UNLOCKED. Else CPU1 Flash Sector 8 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z2_GRABSECT1[15:14] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 7 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 7 to Zone2.
10 : No request for CPU1 Flash Sector 7
11 : No request for CPU1 Flash Sector 7 when this zone is
UNLOCKED. Else CPU1 Flash Sector 7 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z2_GRABSECT1[13:12] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 6 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 6 to Zone2.
10 : No request for CPU1 Flash Sector 6
11 : No request for CPU1 Flash Sector 6 when this zone is
UNLOCKED. Else CPU1 Flash Sector 6 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z2_GRABSECT1[11:10] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 5 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 5 to Zone2.
10 : No request for CPU1 Flash Sector 5
11 : No request for CPU1 Flash Sector 5 when this zone is
UNLOCKED. Else CPU1 Flash Sector 5 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z2_GRABSECT1[9:8] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 4 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 4 to Zone2.
10 : No request for CPU1 Flash Sector 4
11 : No request for CPU1 Flash Sector 4 when this zone is
UNLOCKED. Else CPU1 Flash Sector 4 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z2_GRABSECT1[7:6] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 3 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 3 to Zone2.
10 : No request for CPU1 Flash Sector 3
11 : No request for CPU1 Flash Sector 3 when this zone is
UNLOCKED. Else CPU1 Flash Sector 3 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-93. Z2_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z2_GRABSECT1[5:4] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 2 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 2 to Zone2.
10 : No request for CPU1 Flash Sector 2
11 : No request for CPU1 Flash Sector 2 when this zone is
UNLOCKED. Else CPU1 Flash Sector 2 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z2_GRABSECT1[3:2] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 1 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 1 to Zone2.
10 : No request for CPU1 Flash Sector 1
11 : No request for CPU1 Flash Sector 1 when this zone is
UNLOCKED. Else CPU1 Flash Sector 1 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z2_GRABSECT1[1:0] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 0 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 0 to Zone2.
10 : No request for CPU1 Flash Sector 0
11 : No request for CPU1 Flash Sector 0 when this zone is
UNLOCKED. Else CPU1 Flash Sector 0 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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6.8.6.14 Z2_GRABSECT2R Register (Offset (x8) = 38h, Offset (x16) = 1Ch) [reset = 0h]
Z2_GRABSECT2R is shown in Figure 6-83 and described in Table 6-94.
Return to the Summary Table.
Zone 2 Grab Flash Status Register 2

Figure 6-83. Z2_GRABSECT2R Register

31 30 29 28 27 26 25 24
RESERVED GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 6-94. Z2_GRABSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z2_GRABSECT2[27:26] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 13 is inaccessible.
01 : Request to allocate CM Flash Sector 13 to Zone2.
10 : No request for CM Flash Sector 13
11 : No request for CM Flash Sector 13 when this zone is
UNLOCKED. Else CM Flash Sector 13 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z2_GRABSECT2[25:24] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 12 is inaccessible.
01 : Request to allocate CM Flash Sector 12 to Zone2.
10 : No request for CM Flash Sector 12
11 : No request for CM Flash Sector 12 when this zone is
UNLOCKED. Else CM Flash Sector 12 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z2_GRABSECT2[23:22] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 11 is inaccessible.
01 : Request to allocate CM Flash Sector 11 to Zone2.
10 : No request for CM Flash Sector 11
11 : No request for CM Flash Sector 11 when this zone is
UNLOCKED. Else CM Flash Sector 11 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z2_GRABSECT2[21:20] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 10 is inaccessible.
01 : Request to allocate CM Flash Sector 10 to Zone2.
10 : No request for CM Flash Sector 10
11 : No request for CM Flash Sector 10 when this zone is
UNLOCKED. Else CM Flash Sector 10 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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Table 6-94. Z2_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z2_GRABSECT2[19:18] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 9 is inaccessible.
01 : Request to allocate CM Flash Sector 9 to Zone2.
10 : No request for CM Flash Sector 9
11 : No request for CM Flash Sector 9 when this zone is
UNLOCKED. Else CM Flash Sector 9 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z2_GRABSECT2[17:16] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 8 is inaccessible.
01 : Request to allocate CM Flash Sector 8 to Zone2.
10 : No request for CM Flash Sector 8
11 : No request for CM Flash Sector 8 when this zone is
UNLOCKED. Else CM Flash Sector 8 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z2_GRABSECT2[15:14] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 7 is inaccessible.
01 : Request to allocate CM Flash Sector 7 to Zone2.
10 : No request for CM Flash Sector 7
11 : No request for CM Flash Sector 7 when this zone is
UNLOCKED. Else CM Flash Sector 7 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z2_GRABSECT2[13:12] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 6 is inaccessible.
01 : Request to allocate CM Flash Sector 6 to Zone2.
10 : No request for CM Flash Sector 6
11 : No request for CM Flash Sector 6 when this zone is
UNLOCKED. Else CM Flash Sector 6 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z2_GRABSECT2[11:10] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 5 is inaccessible.
01 : Request to allocate CM Flash Sector 5 to Zone2.
10 : No request for CM Flash Sector 5
11 : No request for CM Flash Sector 5 when this zone is
UNLOCKED. Else CM Flash Sector 5 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z2_GRABSECT2[9:8] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 4 is inaccessible.
01 : Request to allocate CM Flash Sector 4 to Zone2.
10 : No request for CM Flash Sector 4
11 : No request for CM Flash Sector 4 when this zone is
UNLOCKED. Else CM Flash Sector 4 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z2_GRABSECT2[7:6] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 3 is inaccessible.
01 : Request to allocate CM Flash Sector 3 to Zone2.
10 : No request for CM Flash Sector 3
11 : No request for CM Flash Sector 3 when this zone is
UNLOCKED. Else CM Flash Sector 3 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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Table 6-94. Z2_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z2_GRABSECT2[5:4] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 2 is inaccessible.
01 : Request to allocate CM Flash Sector 2 to Zone2.
10 : No request for CM Flash Sector 2
11 : No request for CM Flash Sector 2 when this zone is
UNLOCKED. Else CM Flash Sector 2 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z2_GRABSECT2[3:2] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 1 is inaccessible.
01 : Request to allocate CM Flash Sector 1 to Zone2.
10 : No request for CM Flash Sector 1
11 : No request for CM Flash Sector 1 when this zone is
UNLOCKED. Else CM Flash Sector 1 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z2_GRABSECT2[1:0] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 0 is inaccessible.
01 : Request to allocate CM Flash Sector 0 to Zone2.
10 : No request for CM Flash Sector 0
11 : No request for CM Flash Sector 0 when this zone is
UNLOCKED. Else CM Flash Sector 0 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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6.8.6.15 Z2_GRABSECT3R Register (Offset (x8) = 3Ch, Offset (x16) = 1Eh) [reset = 0h]
Z2_GRABSECT3R is shown in Figure 6-84 and described in Table 6-95.
Return to the Summary Table.
Zone 2 Grab Flash Status Register 3

Figure 6-84. Z2_GRABSECT3R Register

31 30 29 28 27 26 25 24
RESERVED GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 6-95. Z2_GRABSECT3R Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z2_GRABSECT3[27:26] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 13 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 13 to Zone2.
10 : No request for CPU2 Flash Sector 13
11 : No request for CPU2 Flash Sector 13 when this zone is
UNLOCKED. Else CPU2 Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z2_GRABSECT3[25:24] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 12 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 12 to Zone2.
10 : No request for CPU2 Flash Sector 12
11 : No request for CPU2 Flash Sector 12 when this zone is
UNLOCKED. Else CPU2 Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z2_GRABSECT3[23:22] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 11 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 11 to Zone2.
10 : No request for CPU2 Flash Sector 11
11 : No request for CPU2 Flash Sector 11 when this zone is
UNLOCKED. Else CPU2 Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z2_GRABSECT3[21:20] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 10 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 10 to Zone2.
10 : No request for CPU2 Flash Sector 10
11 : No request for CPU2 Flash Sector 10 when this zone is
UNLOCKED. Else CPU2 Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-95. Z2_GRABSECT3R Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z2_GRABSECT3[19:18] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 9 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 9 to Zone2.
10 : No request for CPU2 Flash Sector 9
11 : No request for CPU2 Flash Sector 9 when this zone is
UNLOCKED. Else CPU2 Flash Sector 9 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z2_GRABSECT3[17:16] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 8 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 8 to Zone2.
10 : No request for CPU2 Flash Sector 8
11 : No request for CPU2 Flash Sector 8 when this zone is
UNLOCKED. Else CPU2 Flash Sector 8 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z2_GRABSECT3[15:14] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 7 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 7 to Zone2.
10 : No request for CPU2 Flash Sector 7
11 : No request for CPU2 Flash Sector 7 when this zone is
UNLOCKED. Else CPU2 Flash Sector 7 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z2_GRABSECT3[13:12] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 6 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 6 to Zone2.
10 : No request for CPU2 Flash Sector 6
11 : No request for CPU2 Flash Sector 6 when this zone is
UNLOCKED. Else CPU2 Flash Sector 6 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z2_GRABSECT3[11:10] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 5 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 5 to Zone2.
10 : No request for CPU2 Flash Sector 5
11 : No request for CPU2 Flash Sector 5 when this zone is
UNLOCKED. Else CPU2 Flash Sector 5 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z2_GRABSECT3[9:8] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 4 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 4 to Zone2.
10 : No request for CPU2 Flash Sector 4
11 : No request for CPU2 Flash Sector 4 when this zone is
UNLOCKED. Else CPU2 Flash Sector 4 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z2_GRABSECT3[7:6] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 3 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 3 to Zone2.
10 : No request for CPU2 Flash Sector 3
11 : No request for CPU2 Flash Sector 3 when this zone is
UNLOCKED. Else CPU2 Flash Sector 3 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-95. Z2_GRABSECT3R Register Field Descriptions (continued)

Bit Field Type Reset Description
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z2_GRABSECT3[5:4] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 2 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 2 to Zone2.
10 : No request for CPU2 Flash Sector 2
11 : No request for CPU2 Flash Sector 2 when this zone is
UNLOCKED. Else CPU2 Flash Sector 2 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z2_GRABSECT3[3:2] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 1 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 1 to Zone2.
10 : No request for CPU2 Flash Sector 1
11 : No request for CPU2 Flash Sector 1 when this zone is
UNLOCKED. Else CPU2 Flash Sector 1 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z2_GRABSECT3[1:0] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 0 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 0 to Zone2.
10 : No request for CPU2 Flash Sector 0
11 : No request for CPU2 Flash Sector 0 when this zone is
UNLOCKED. Else CPU2 Flash Sector 0 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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6.8.6.16 Z2_GRABRAM1R Register (Offset (x8) = 40h, Offset (x16) = 20h) [reset = 0h]
Z2_GRABRAM1R is shown in Figure 6-85 and described in Table 6-96.
Return to the Summary Table.
Zone 2 Grab RAM Status Register 1

Figure 6-85. Z2_GRABRAM1R Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED GRAB_RAM9 GRAB_RAM8
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
GRAB_RAM3 GRAB_RAM2 GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h R-0h

Table 6-96. Z2_GRABRAM1R Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 GRAB_RAM9 R 0h Value in this field gets loaded from Z2_GRABRAM1[19:18] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 D1 RAM is inaccessible.
01 : Request to allocate CPU1 D1 RAM to Zone2.
10 : No request for CPU1 D1 RAM
11 : No request for CPU1 D1 RAM when this zone is UNLOCKED.
Else CPU1 D1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_RAM8 R 0h Value in this field gets loaded from Z2_GRABRAM1[17:16] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 D0 RAM is inaccessible.
01 : Request to allocate CPU1 D0 RAM to Zone2.
10 : No request for CPU1 D0 RAM
11 : No request for CPU1 D0 RAM when this zone is UNLOCKED.
Else CPU1 D0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z2_GRABRAM1[15:14] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS7 RAM is inaccessible.
01 : Request to allocate CPU1 LS7 RAM to Zone2.
10 : No request for CPU1 LS7 RAM
11 : No request for CPU1 LS7 RAM when this zone is UNLOCKED.
Else CPU1 LS7 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z2_GRABRAM1[13:12] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS6 RAM is inaccessible.
01 : Request to allocate CPU1 LS6 RAM to Zone2.
10 : No request for CPU1 LS6 RAM
11 : No request for CPU1 LS6 RAM when this zone is UNLOCKED.
Else CPU1 LS6 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-96. Z2_GRABRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z2_GRABRAM1[11:10] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS5 RAM is inaccessible.
01 : Request to allocate CPU1 LS5 RAM to Zone2.
10 : No request for CPU1 LS5 RAM
11 : No request for CPU1 LS5 RAM when this zone is UNLOCKED.
Else CPU1 LS5 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z2_GRABRAM1[9:8] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS4 RAM is inaccessible.
01 : Request to allocate CPU1 LS4 RAM to Zone2.
10 : No request for CPU1 LS4 RAM
11 : No request for CPU1 LS4 RAM when this zone is UNLOCKED.
Else CPU1 LS4 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-6 GRAB_RAM3 R 0h Value in this field gets loaded from Z2_GRABRAM1[7:6] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS3 RAM is inaccessible.
01 : Request to allocate CPU1 LS3 RAM to Zone2.
10 : No request for CPU1 LS3 RAM
11 : No request for CPU1 LS3 RAM when this zone is UNLOCKED.
Else CPU1 LS3 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_RAM2 R 0h Value in this field gets loaded from Z2_GRABRAM1[5:4] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS2 RAM is inaccessible.
01 : Request to allocate CPU1 LS2 RAM to Zone2.
10 : No request for CPU1 LS2 RAM
11 : No request for CPU1 LS2 RAM when this zone is UNLOCKED.
Else CPU1 LS2 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z2_GRABRAM1[3:2] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS1 RAM is inaccessible.
01 : Request to allocate CPU1 LS1 RAM to Zone2.
10 : No request for CPU1 LS1 RAM
11 : No request for CPU1 LS1 RAM when this zone is UNLOCKED.
Else CPU1 LS1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z2_GRABRAM1[1:0] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS0 RAM is inaccessible.
01 : Request to allocate CPU1 LS0 RAM to Zone2.
10 : No request for CPU1 LS0 RAM
11 : No request for CPU1 LS0 RAM when this zone is UNLOCKED.
Else CPU1 LS0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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6.8.6.17 Z2_GRABRAM2R Register (Offset (x8) = 44h, Offset (x16) = 22h) [reset = 0h]
Z2_GRABRAM2R is shown in Figure 6-86 and described in Table 6-97.
Return to the Summary Table.
Zone 2 Grab RAM Status Register 2

Figure 6-86. Z2_GRABRAM2R Register

31 30 29 28 27 26 25 24
GRAB_RAM15 GRAB_RAM14 GRAB_RAM13 GRAB_RAM12
R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
GRAB_RAM11 GRAB_RAM10 GRAB_RAM9 GRAB_RAM8
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h

Table 6-97. Z2_GRABRAM2R Register Field Descriptions

Bit Field Type Reset Description
31-30 GRAB_RAM15 R 0h Value in this field gets loaded from Z2_GRABRAM2[31:30] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the higher addressed half of
CPU2TOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
29-28 GRAB_RAM14 R 0h Value in this field gets loaded from Z2_GRABRAM2[29:28] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the lower addressed half of
CPU2TOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
27-26 GRAB_RAM13 R 0h Value in this field gets loaded from Z2_GRABRAM2[27:26] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the higher addressed half of
CPU1TOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-97. Z2_GRABRAM2R Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 GRAB_RAM12 R 0h Value in this field gets loaded from Z2_GRABRAM2[25:24] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the lower addressed half of
CPU1TOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
23-22 GRAB_RAM11 R 0h Value in this field gets loaded from Z2_GRABRAM2[23:22] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the higher addressed half of
CMTOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
21-20 GRAB_RAM10 R 0h Value in this field gets loaded from Z2_GRABRAM2[21:20] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the lower addressed half of
CMTOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
19-18 GRAB_RAM9 R 0h Value in this field gets loaded from Z2_GRABRAM2[19:18] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the higher addressed half of
CPU2TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_RAM8 R 0h Value in this field gets loaded from Z2_GRABRAM2[17:16] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the lower addressed half of
CPU2TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z2_GRABRAM2[15:14] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the higher addressed half of
CMTOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-97. Z2_GRABRAM2R Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z2_GRABRAM2[13:12] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the lower addressed half of
CMTOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z2_GRABRAM2[11:10] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the higher addressed half of
CPU1TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z2_GRABRAM2[9:8] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the lower addressed half of
CPU1TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-4 RESERVED R 0h Reserved
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z2_GRABRAM2[3:2] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
00 : Invalid. CM C1 RAM is inaccessible.
01 : Request to allocate CM C1 RAM to Zone2.
10 : No request for CM C1 RAM
11 : No request for CM C1 RAM when this zone is UNLOCKED. Else
CM C1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z2_GRABRAM2[1:0] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
00 : Invalid. CM C0 RAM is inaccessible.
01 : Request to allocate CM C0 RAM to Zone2.
10 : No request for CM C0 RAM
11 : No request for CM C0 RAM when this zone is UNLOCKED. Else
CM C0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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6.8.6.18 Z2_GRABRAM3R Register (Offset (x8) = 48h, Offset (x16) = 24h) [reset = 0h]
Z2_GRABRAM3R is shown in Figure 6-87 and described in Table 6-98.
Return to the Summary Table.
Zone 2 Grab RAM Status Register 3

Figure 6-87. Z2_GRABRAM3R Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED GRAB_RAM9 GRAB_RAM8
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
GRAB_RAM3 GRAB_RAM2 GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h R-0h

Table 6-98. Z2_GRABRAM3R Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 GRAB_RAM9 R 0h Value in this field gets loaded from Z2_GRABRAM3[19:18] when a
read is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 D1 RAM is inaccessible.
01 : Request to allocate CPU2 D1 RAM to Zone2.
10 : No request for CPU2 D1 RAM
11 : No request for CPU2 D1 RAM when this zone is UNLOCKED.
Else CPU2 D1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_RAM8 R 0h Value in this field gets loaded from Z2_GRABRAM3[17:16] when a
read is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 D0 RAM is inaccessible.
01 : Request to allocate CPU2 D0 RAM to Zone2.
10 : No request for CPU2 D0 RAM
11 : No request for CPU2 D0 RAM when this zone is UNLOCKED.
Else CPU2 D0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z2_GRABRAM3[15:14] when a
read is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS7 RAM is inaccessible.
01 : Request to allocate CPU2 LS7 RAM to Zone2.
10 : No request for CPU2 LS7 RAM
11 : No request for CPU2 LS7 RAM when this zone is UNLOCKED.
Else CPU2 LS7 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z2_GRABRAM3[13:12] when a
read is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS6 RAM is inaccessible.
01 : Request to allocate CPU2 LS6 RAM to Zone2.
10 : No request for CPU2 LS6 RAM
11 : No request for CPU2 LS6 RAM when this zone is UNLOCKED.
Else CPU2 LS6 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-98. Z2_GRABRAM3R Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z2_GRABRAM3[11:10] when a
read is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS5 RAM is inaccessible.
01 : Request to allocate CPU2 LS5 RAM to Zone2.
10 : No request for CPU2 LS5 RAM
11 : No request for CPU2 LS5 RAM when this zone is UNLOCKED.
Else CPU2 LS5 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z2_GRABRAM3[9:8] when a
read is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS4 RAM is inaccessible.
01 : Request to allocate CPU2 LS4 RAM to Zone2.
10 : No request for CPU2 LS4 RAM
11 : No request for CPU2 LS4 RAM when this zone is UNLOCKED.
Else CPU2 LS4 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-6 GRAB_RAM3 R 0h Value in this field gets loaded from Z2_GRABRAM3[7:6] when a
read is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS3 RAM is inaccessible.
01 : Request to allocate CPU2 LS3 RAM to Zone2.
10 : No request for CPU2 LS3 RAM
11 : No request for CPU2 LS3 RAM when this zone is UNLOCKED.
Else CPU2 LS3 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_RAM2 R 0h Value in this field gets loaded from Z2_GRABRAM3[5:4] when a
read is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS2 RAM is inaccessible.
01 : Request to allocate CPU2 LS2 RAM to Zone2.
10 : No request for CPU2 LS2 RAM
11 : No request for CPU2 LS2 RAM when this zone is UNLOCKED.
Else CPU2 LS2 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z2_GRABRAM3[3:2] when a
read is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS1 RAM is inaccessible.
01 : Request to allocate CPU2 LS1 RAM to Zone2.
10 : No request for CPU2 LS1 RAM
11 : No request for CPU2 LS1 RAM when this zone is UNLOCKED.
Else CPU2 LS1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z2_GRABRAM3[1:0] when a
read is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS0 RAM is inaccessible.
01 : Request to allocate CPU2 LS0 RAM to Zone2.
10 : No request for CPU2 LS0 RAM
11 : No request for CPU2 LS0 RAM when this zone is UNLOCKED.
Else CPU2 LS0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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6.8.6.19 Z2_EXEONLYSECT1R Register (Offset (x8) = 4Ch, Offset (x16) = 26h) [reset = 0h]
Z2_EXEONLYSECT1R is shown in Figure 6-88 and described in Table 6-99.
Return to the Summary Table.
Zone 2 Execute Only Flash Status Register 1

Figure 6-88. Z2_EXEONLYSECT1R Register

31 30 29 28 27 26 25 24
RESERVED EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM
_SECT13 _SECT12 _SECT11 _SECT10 _SECT9 _SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM
_SECT7 _SECT6 _SECT5 _SECT4 _SECT3 _SECT2 _SECT1 _SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U1_SECT13 U1_SECT12 U1_SECT11 U1_SECT10 U1_SECT9 U1_SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U1_SECT7 U1_SECT6 U1_SECT5 U1_SECT4 U1_SECT3 U1_SECT2 U1_SECT1 U1_SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-99. Z2_EXEONLYSECT1R Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R 0h Reserved
29 EXEONLY_CM_SECT13 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[29] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 13 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 13 (only
if it's allocated to Zone2)
Reset type: SYSRSn
28 EXEONLY_CM_SECT12 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[28] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 12 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 12 (only
if it's allocated to Zone2)
Reset type: SYSRSn
27 EXEONLY_CM_SECT11 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[27] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 11 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 11 (only
if it's allocated to Zone2)
Reset type: SYSRSn
26 EXEONLY_CM_SECT10 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[26] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 10 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 10 (only
if it's allocated to Zone2)
Reset type: SYSRSn

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Table 6-99. Z2_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
25 EXEONLY_CM_SECT9 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[25] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 9 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 9 (only if
it's allocated to Zone2)
Reset type: SYSRSn
24 EXEONLY_CM_SECT8 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[24] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 8 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 8 (only if
it's allocated to Zone2)
Reset type: SYSRSn
23 EXEONLY_CM_SECT7 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[23] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 7 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 7 (only if
it's allocated to Zone2)
Reset type: SYSRSn
22 EXEONLY_CM_SECT6 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[22] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 6 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 6 (only if
it's allocated to Zone2)
Reset type: SYSRSn
21 EXEONLY_CM_SECT5 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[21] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 5 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 5 (only if
it's allocated to Zone2)
Reset type: SYSRSn
20 EXEONLY_CM_SECT4 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[20] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 4 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 4 (only if
it's allocated to Zone2)
Reset type: SYSRSn
19 EXEONLY_CM_SECT3 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[19] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 3 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 3 (only if
it's allocated to Zone2)
Reset type: SYSRSn
18 EXEONLY_CM_SECT2 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[18] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 2 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 2 (only if
it's allocated to Zone2)
Reset type: SYSRSn
17 EXEONLY_CM_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[17] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 1 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 1 (only if
it's allocated to Zone2)
Reset type: SYSRSn

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Table 6-99. Z2_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
16 EXEONLY_CM_SECT0 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[16] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 0 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 0 (only if
it's allocated to Zone2)
Reset type: SYSRSn
15-14 RESERVED R 0h Reserved
13 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[13] when a
3 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 13
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 13
(only if it's allocated to Zone2)
Reset type: SYSRSn
12 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[12] when a
2 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 12
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 12
(only if it's allocated to Zone2)
Reset type: SYSRSn
11 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[11] when a
1 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 11
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 11
(only if it's allocated to Zone2)
Reset type: SYSRSn
10 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[10] when a
0 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 10
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 10
(only if it's allocated to Zone2)
Reset type: SYSRSn
9 EXEONLY_CPU1_SECT9 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[9] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 9 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 9
(only if it's allocated to Zone2)
Reset type: SYSRSn
8 EXEONLY_CPU1_SECT8 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[8] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 8 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 8
(only if it's allocated to Zone2)
Reset type: SYSRSn
7 EXEONLY_CPU1_SECT7 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[7] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 7 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 7
(only if it's allocated to Zone2)
Reset type: SYSRSn

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Table 6-99. Z2_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
6 EXEONLY_CPU1_SECT6 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[6] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 6 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 6
(only if it's allocated to Zone2)
Reset type: SYSRSn
5 EXEONLY_CPU1_SECT5 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[5] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 5 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 5
(only if it's allocated to Zone2)
Reset type: SYSRSn
4 EXEONLY_CPU1_SECT4 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[4] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 4 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 4
(only if it's allocated to Zone2)
Reset type: SYSRSn
3 EXEONLY_CPU1_SECT3 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[3] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 3 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 3
(only if it's allocated to Zone2)
Reset type: SYSRSn
2 EXEONLY_CPU1_SECT2 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[2] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 2 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 2
(only if it's allocated to Zone2)
Reset type: SYSRSn
1 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[1] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 1 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 1
(only if it's allocated to Zone2)
Reset type: SYSRSn
0 EXEONLY_CPU1_SECT0 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[0] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 0 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 0
(only if it's allocated to Zone2)
Reset type: SYSRSn

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6.8.6.20 Z2_EXEONLYSECT2R Register (Offset (x8) = 50h, Offset (x16) = 28h) [reset = 0h]
Z2_EXEONLYSECT2R is shown in Figure 6-89 and described in Table 6-100.
Return to the Summary Table.
Zone 2 Execute Only Flash Status Register 2

Figure 6-89. Z2_EXEONLYSECT2R Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U2_SECT13 U2_SECT12 U2_SECT11 U2_SECT10 U2_SECT9 U2_SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U2_SECT7 U2_SECT6 U2_SECT5 U2_SECT4 U2_SECT3 U2_SECT2 U2_SECT1 U2_SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-100. Z2_EXEONLYSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0h Reserved
13 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[13] when a
3 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 13
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 13
(only if it's allocated to Zone2)
Reset type: SYSRSn
12 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[12] when a
2 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 12
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 12
(only if it's allocated to Zone2)
Reset type: SYSRSn
11 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[11] when a
1 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 11
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 11
(only if it's allocated to Zone2)
Reset type: SYSRSn
10 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[10] when a
0 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 10
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 10
(only if it's allocated to Zone2)
Reset type: SYSRSn

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Table 6-100. Z2_EXEONLYSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
9 EXEONLY_CPU2_SECT9 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[9] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 9 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 9
(only if it's allocated to Zone2)
Reset type: SYSRSn
8 EXEONLY_CPU2_SECT8 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[8] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 8 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 8
(only if it's allocated to Zone2)
Reset type: SYSRSn
7 EXEONLY_CPU2_SECT7 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[7] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 7 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 7
(only if it's allocated to Zone2)
Reset type: SYSRSn
6 EXEONLY_CPU2_SECT6 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[6] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 6 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 6
(only if it's allocated to Zone2)
Reset type: SYSRSn
5 EXEONLY_CPU2_SECT5 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[5] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 5 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 5
(only if it's allocated to Zone2)
Reset type: SYSRSn
4 EXEONLY_CPU2_SECT4 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[4] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 4 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 4
(only if it's allocated to Zone2)
Reset type: SYSRSn
3 EXEONLY_CPU2_SECT3 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[3] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 3 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 3
(only if it's allocated to Zone2)
Reset type: SYSRSn
2 EXEONLY_CPU2_SECT2 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[2] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 2 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 2
(only if it's allocated to Zone2)
Reset type: SYSRSn
1 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[1] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 1 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 1
(only if it's allocated to Zone2)
Reset type: SYSRSn

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Table 6-100. Z2_EXEONLYSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
0 EXEONLY_CPU2_SECT0 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[0] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 0 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 0
(only if it's allocated to Zone2)
Reset type: SYSRSn

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6.8.6.21 Z2_EXEONLYRAM1R Register (Offset (x8) = 54h, Offset (x16) = 2Ah) [reset = 0h]
Z2_EXEONLYRAM1R is shown in Figure 6-90 and described in Table 6-101.
Return to the Summary Table.
Zone 2 Execute Only RAM Status Register 1

Figure 6-90. Z2_EXEONLYRAM1R Register

31 30 29 28 27 26 25 24
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M31 M30 M29 M28 M27 M26 M25 M24
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
EXEONLY_RA EXEONLY_RA RESERVED EXEONLY_RA EXEONLY_RA
M23 M22 M17 M16
R-0h R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED EXEONLY_RA EXEONLY_RA
M9 M8
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M7 M6 M5 M4 M3 M2 M1 M0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-101. Z2_EXEONLYRAM1R Register Field Descriptions

Bit Field Type Reset Description
31 EXEONLY_RAM31 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[31] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS0 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS0 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
30 EXEONLY_RAM30 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[30] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS1 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS1 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
29 EXEONLY_RAM29 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[29] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS2 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS2 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
28 EXEONLY_RAM28 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[28] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS3 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS3 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn

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Table 6-101. Z2_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
27 EXEONLY_RAM27 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[27] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS4 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS4 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
26 EXEONLY_RAM26 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[26] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS5 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS5 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
25 EXEONLY_RAM25 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[25] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS6 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS6 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
24 EXEONLY_RAM24 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[24] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS7 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS7 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
23 EXEONLY_RAM23 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[23] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 D0 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 D0 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
22 EXEONLY_RAM22 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[22] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 D1 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 D1 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
21-18 RESERVED R 0h Reserved
17 EXEONLY_RAM17 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[17] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CM C1 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CM C1 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
16 EXEONLY_RAM16 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[16] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CM C0 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CM C0 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved

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Table 6-101. Z2_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
9 EXEONLY_RAM9 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[9] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU1 D1 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 D1 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
8 EXEONLY_RAM8 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[8] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU1 D0 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 D0 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
7 EXEONLY_RAM7 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[7] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS7 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS7 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
6 EXEONLY_RAM6 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[6] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS6 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS6 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
5 EXEONLY_RAM5 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[5] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS5 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS5 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
4 EXEONLY_RAM4 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[4] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS4 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS4 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
3 EXEONLY_RAM3 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[3] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS3 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS3 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
2 EXEONLY_RAM2 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[2] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS2 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS2 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
1 EXEONLY_RAM1 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[1] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS1 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS1 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn

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Table 6-101. Z2_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
0 EXEONLY_RAM0 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[0] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS0 RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS0 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn

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 Chapter 7
SPRUII0B – May 2019 – Revised May 2020

Background CRC-32 (BGCRC)

The Background CRC (BGCRC) module that helps to identify memory faults and corruption, is discussed
in this chapter.

Topic ........................................................................................................................... Page

7.1 Introduction ..................................................................................................... 890

7.2 Features .......................................................................................................... 890
7.3 Functional Description ...................................................................................... 891
7.4 Application of the BGCRC ................................................................................. 894
7.5 BGCRC Registers ............................................................................................. 898

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7.1 Introduction
The Background CRC (BGCRC) module computes a CRC-32 on a configurable block of memory. It
accomplishes this by fetching the specified block of memory during idle cycles (when the CPU, CLA, or
DMA is not accessing the memory block). The calculated CRC-32 value is compared against a golden
CRC-32 value to indicate a pass or fail. In essence, the BGCRC helps identify memory faults and
corruption. There are two BGCRC modules (CPU_CRC and CLA_CRC) per CPU subsystem. The two
BGCRC modules differ only in the memories they test.

7.2 Features
The BGCRC module has the following features:
• One cycle CRC-32 computation on 32 bits of data
• No CPU bandwidth impact for zero wait state memory
• Minimal CPU bandwidth impact for non-zero wait state memory
• Dual operation modes (CRC-32 mode and scrub mode)
• Watchdog timer to time CRC-32 completion
• Ability to pause and resume CRC-32 computation

7.2.1 Memory Wait States and Memory Map

Figure 7-1 shows the memory map of the BGCRC module. M0, M1, D[x]RAM, MSGRAM, LS[x]RAM and
GS[x]RAM are all zero wait-state memories. BGCRC will access these memories with minimal impact on
normal program operation. For instance, if a BGCRC access is being made to a zero wait-state memory in
the current cycle, the earliest the operating program can make access to the same memory location will
be in the next cycle. Similarly for the non-zero wait state memories SECROM, DATAROM and
BOOTROM, the worst case delay for functional access after a BGCRC access will be the wait state
amount.
Figure 7-1 shows the memory map of the BGCRC module.

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Figure 7-1. BGCRC Memory Map

7.3 Functional Description

The CRC-32 calculation of the BGCRC module can be kicked off by configuring the register
BGCRC_EN.START to 1010. Once started, the module will perform the background memory checks
without CPU or CLA intervention. However, on completion of the CRC-32 calculation or in the event of a
failure, the CPU or CLA will be notified through an interrupt and task, respectively. Figure 7-2 shows the
BGCRC block diagram.
As highlighted in the overview, there are two BGCRC modules per CPU subsystem. CPU_CRC that is
configurable by the CPU can only generate an interrupt. CLA_CRC however, can be configured by both
the CPU and CLA and can generate an interrupt to the CPU or task for the CLA.

Figure 7-2. BGCRC Block Diagram

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7.3.1 Data Read Unit

Once the CRC-32 calculation is started, the BGCRC module will continuously read data from memory as a
background process. These reads happen during the idle times (when the CPU, CLA or DMA is not
accessing the memory block) and so will not impact functional access. The data read unit will only read
data if there is no pending functional access. The data read unit begins operation by reading a block of
data BGCRC_CTRL2.BLOCK_SIZE from address BGCRC_START_ADDR. Note that
BGCRC_START_ADDR must be 0x80 word aligned. For a non-0x80 word aligned
BGCRC_START_ADDR, the LSB bits will be zeroed out to get a 0x80 word aligned
BGCRC_START_ADDR. For instance, if the programmed BGCRC_START_ADDR = 0x1AF3, the internal
0x80 word aligned start address will be 0x1A80.
When the data read unit reads a block of data, ECC and parity will be checked. Any ECC or parity errors
that occur during the read will be indicated by setting the respective NMI and generating an interrupt if
configured as so. The BGCRC module however, will not write back the corrected memory contents on the
occurrence of a correctable ECC error. Writing back the corrected values should be handled by software.

7.3.2 CRC-32 Compute Unit

After the data read unit reads a block of data, it feeds this data to the CRC-32 compute unit. This unit
computes the CRC-32 using the standard polynomial 0x04C11DB7 (x32 + x26 + x23 + x22 + x16 + x12 +
x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1). The CRC-32 unit retrieves 32-bit of data at a time from the
block of data to compute the polynomial. This computation takes 1 cycle. For instance the CRC-32
calculation for 1KB block of data will be 256 cycles, 1 cycle for each of the 256 32-bit chunks. The initial
value for the CRC-32 computation can be configured using BGCRC_SEED.
After the CRC-32 calculation is complete for a data block, the final result is loaded into BGCRC_RESULT.
Note that BGCRC_RESULT will only contain the final calculation for the whole data block; intermediate
32-bit calculations will not update BGCRC_RESULT. The value in BGCRC_RESULT will be compared
against the value in BGCRC_GOLDEN by hardware and the NMI/Interrupt flags will be set accordingly by
the CRC notification unit.
Once CRC-32 calculation is commenced, it can be halted by setting BGCRC_CTRL2.TEST_HALT to
1010. Clearing this bit resumes CRC-32 calculation from the halt point.

7.3.3 CRC Notification Unit

After the CRC-32 compute unit completes the CRC-32 calculation for a block of data or fails to complete
the calculation within BGCRC_WD_MIN and BGCRC_WD_MAX, if configured, it will send out a
NMI/Interrupt on the occurrence of a pass or fail. In addition, during a data read by the data read unit, if an
ECC or parity error occurs, the CRC notification unit can send out a NMI/Interrupt. In the case of an ECC
or parity error, the BGCRC will stop operation and BGCRC_CURR_ADDR will contain the memory
address which caused the ECC or parity error. The contents of BGCRC_CURR_ADDR in addition to the
NMI/Interrupt flags can be used to debug a BGCRC failure.

7.3.3.1 CPU Interrupt, CLA Task and NMI

The BGCRC module has configurable Interrupt and NMI lines. NMIs are enabled by default but can be
disabled by writing 0xA to BGCRC_CTRL1.NMIDIS register. Conversely, all Interrupts are disabled by
default but can be enabled by writing 0x7E to BGCRC_INTEN register. When an error occurs in the
BGCRC, it can be configured to generate an NMI or Interrupt. Since NMIs are enabled by default, all
BGCRC errors will cause an NMI. Figure 7-3 and Figure 7-4 show the NMI and Interrupt lines,
respectively.

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Figure 7-3. BGCRC NMI

Figure 7-4. BGCRC Interrupt

7.3.4 Operating Modes

BGCRC module supports two modes of operation: CRC mode and scrub mode. The mode of operation
can be configured by clearing or setting the register BGCRC_CTRL2.SCRUB_MODE.

7.3.4.1 CRC Mode

In CRC mode, the BGCRC module operates as explained in Section 7.3.2. CRC-32 calculation is
performed on a block of data and the result compared against a golden value. ECC and parity errors are
checked in this mode. Result mismatch, ECC or parity error can trigger an NMI/Interrupt.

7.3.4.2 Scrub Mode

In scrub mode, the CRC-32 result is not compared against the golden value and BGCRC_RESULT
register is not updated. ECC and parity errors are also checked in this mode. However unlike CRC mode,
NMI/Interrupt will only be from ECC or parity error. In scrub mode, Parity and ECC bits of the memory
block need to be initialized by the CPU and/or CLA.

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7.3.5 BGCRC Watchdog

The BGCRC module has an embedded windowed watchdog which is used as a diagnostic to check
memory test completion within the expected time window. This can protect against hardware defects
which can cause the memory check not to complete in the allotted time which may not be caught by the
system watchdog as the error may be due to the CLA or DMA having continuous access. Windowing also
helps detect additional failure modes in the watchdog operation, for example, stuck watchdog.
The BGCRC watchdog is enabled by default and starts when the BGCRC module begins reading from
memory. The watchdog can be disabled using the register BGCRC_WD_CFG.WDDIS. The BGCRC
watchdog counter is a 32-bit counter with its value reflected in BGCRC_WD_CNT register. The lower and
upper window settings are configured using BGCRC_WD_MIN and BGCRC_WD_MAX respectively.
BGCRC_WD_MIN and BGCRC_WD_MAX need to be configured before the test is started and shouldn’t
be changed while the BGCRC is operating. If configured, an NMI or Interrupt will be triggered if the
memory test fails to complete within the configured time window. The counter stops on completion of the
CRC-32 check done, CRC-32 check failure and ECC/Parity errors. The counter is reset when the next
memory check begins.
The BGCRC watchdog can be halted by configuring the BGCRC_WD_CFG.WDDIS register. After the
watchdog resumes from being halted, the counter starts counting from the previous count unless a new
memory check operation is initiated. The counter is not halted when CRC-32 computation halts but by
default will halt during a debug halt. The behavior of the watchdog during emulation can be changed by
configuring the appropriate BGCRC registers. In addition, due to the changing nature of memory contents
during emulation, it’s not recommended to run BGCRC during emulation. CRC-32 computation will
continue during a watchdog failure and software needs to address this condition.

7.3.6 Hardware and Software Faults Protection

The configuration registers are protected using a lock and commit configuration. Each of the configuration
registers can be individually locked and committed. The register once locked, can no longer be updated
until the lock is removed. However if the register lock is committed, no further writes is permitted until the
device is reset. It is recommended to lock the registers after configuration to protect against corruption due
to software faults. In addition, registers critical to the module functionality and fault detection are
implemented using multi-bit fields to protect against hardware faults.

7.4 Application of the BGCRC

This section contains use case scenarios of how the BGCRC module can be configured to test a block of
memory. However, the use case scenarios presented are for reference only and do not cover all the
possible application scenarios. These use case scenarios could be used as a starting point to configure
the BGCRC module for specific applications.

7.4.1 Software Configuration

The configuration registers for the BGCRC can be split into three groups (see Table 7-1):
• CFG1 – Registers that determine the operating mode and configured at the beginning.
• CFG2 – Registers that need to be updated during kickoff of a new test.
• CFG3 – Registers used for test and error management.

Table 7-1. BGCRC Register Groups

CFG1 - One Time Configuration CFG2 - Periodic Configuration CFG3 - Registers Used for Test and Error
Registers Registers Management
BGCRC_CTRL1 BGCRC_EN BGCRC_NMICLR
BGCRC_WD_CFG BGCRC_CTRL2 BGCRC_INTCLR
BGCRC_INTEN BGCRC_START_ADDR BGCRC_NMIFRC
BGCRC_SEED BGCRC_GOLDEN BGCRC_INTFRC
BGCRC_WD_MIN
BGCRC_WD_MAX

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CFG1 registers are expected to be locked and committed after initial configuration. It is recommended to
lock the CFG2 and CFG3 registers after configuration. Figure 7-5 shows the BGCRC execution sequence.

Figure 7-5. BGCRC Execution Sequence Flow

7.4.2 Decision on Error Response Severity

The error sources for BGCRC are:
• Test completion before BGCRC_WD_MIN.
• Test completed after BGCRC_WD_MAX.
• Mismatch between the calculated CRC and golden CRC.
• Uncorrectable error during data read (single bit error for parity memory or double bit error for ECC
memory).
• Correctable error during memory read (single bit error for ECC memory).
Error severity can be chosen as either NMI or Interrupt. By default, error severity is set to NMI. It is not
possible to configure error response for each individual error source. The response can be chosen as
either Interrupt or NMI for all error sources. When error severity is chosen as NMI, ERROR_STS pin will
be asserted during an error. CPU and CLA should be assigned the same error severity.

7.4.3 Decision of Master for CLA_CRC

CPU_CRC can only be kicked off by the CPU. However, CLA_CRC can be kicked off by the CPU or CLA.
If BGCRC error severity is chosen as NMI, it is possible to handle the background test using the CLA and
error response with the CPU. Once the master for BGCRC is chosen, it is possible to prevent accesses
from other masters by using the system level access protection configuration.

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7.4.4 Execution of Time Critical Code from Wait-Stated Memories

BGCRC access to functionally wait-stated memories will also be wait-stated by the same number. Since it
is impossible to predict the next functional access, any ongoing BGCRC access will have to complete
before functional access is granted. To mitigate delay in functional access, the BGCRC can be halted
when time-critical code which accesses the wait-stated memories is in progress. When BGCRC execution
is halted, the BGCRC watchdog will not be halted. This is consistent with the safety requirement to
complete the background test in a predictable window irrespective of the user code. In such scenarios, it is
recommended to adjust the upper BGCRC watchdog window limit to account for the halt duration during
functional access. However, if required, the BGCRC watchdog can be disabled.

7.4.5 BGCRC Execution

Two notes about BGCRC execution are as follows:
• BGCRC task can run as a background task once kicked off by the master.
• BGCRC task does not impact functional execution for zero-wait stated memories. For memories with
higher wait-states, the BGCRC engine can be halted to make functional execution predictable.
Figure 7-6 shows a few examples of BGCRC execution sequences.

Figure 7-6. BGCRC Execution Sequence Example

7.4.6 Debug/Error Response for BGCRC Errors

The BGCRC error severity can be decoded by reading the BGCRC_INTFLG or BGCRC_NMIFLG. The
errors can be:
• WD_OVERFLOW/WD_UNDERFLOW: The test didn’t complete in the programmed window. System
timing needs to be checked to understand reason for non-completion of the test.
BGCRC_CURR_ADDR and BGCRC_WD_CNT indicate how far the test progressed.
• UNCORRECTABLE_ERR: BGCRC_CURR_ADDR will contain the address of the memory location
causing the error. This error is due to single bit failure for Parity SRAM or double bit failure for ECC
SRAM. The memory location can be reloaded (if possible, for cases where code is copied from flash)
to see if the problem resolves. If the problem persists, it could be a permanent defect.

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• CORRECTABLE_ERR: This error is due to single bit failure for ECC SRAM. If the problem location is
accessed again (execution from the location for execute only memory or reading the location in other
cases), the expectation is that the single bit error will be corrected. If the single bit error is not
corrected, this could be an indication of a permanent defect.
• CRC_FAIL: This indicates a failure in the computation of the CRC-32 value. This error doesn’t occur in
scrub mode. For SRAMs with protection, in the absence of code bugs, this error is less likely since the
error will most often manifest as a correctable/uncorrectable error. Code bugs can cause failure if the
code inadvertently writes to a wrong address thus causing a CRC-32 error.

7.4.7 BGCRC Golden CRC-32 Value Computation

The C28x is a little-endian 16-bit word addressable CPU. Therefore, the 32-bit value of 0x12345678
stored at address 0x100 is stored as follows in the C28x memory:

Table 7-2. Data Address Location Example 1

Address 0x100 0x101
Data 0x5678 0x1234

The BGCRC order of byte calculations of the above example is 0x78, 0x56, 0x34, 0x12 and yields
0x6A330D2D. The 32-bit polynomial 0x04C11DB7 is used with an initialization vector of 0x00000000. The
code snippet in Figure 7-7 shows the effective bit processing. Processing for all 32-bits within a word
occurs in a single cycle within the BGCRC hardware.

Figure 7-7. BGCRC Golden Value

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A second example with two 32-bit words, 0x12345678 and 0x9ABCDEF0 at address 0x100 and 0x102
successively, would calculate the bytes in the order 0x78, 0x56, 0x34, 0x12, 0xDE, 0xBC, and 0x9A and
yield 0x7E0B4164.

Table 7-3. Data Address Location Example 2

Address 0x100 0x101 0x102 0x103
Data 0x5678 0x1234 0xDEF0 0x9ABC

All data input to the BGCRC must align to a 32-bit boundary, both in the starting address and the size. It is
possible to include 16-bit data within the span of data; however, when the data is read by the BGCRC, it
will always assume 32-bits and conform to the above calculation order. For example, if two 16-bit words
(0xA0B1 and 0xC2D3) were placed in between the two 32-bit words above, the calculations would be
performed in byte order 0x78, 0x56, 0x34, 0x12, 0xB1, 0xA0, 0xD3, 0xC2, 0xF0, 0xDE, 0xBC and 0x9A
and yield 0x2AEFD987.

Table 7-4. Data Address Location Example 3

Address 0x100 0x101 0x102 0x103 0x104 0x105
Data 0x5678 0x1234 0xA0B1 0xC2D3 0xDEF0 0x9ABC

7.5 BGCRC Registers

This section describes the Background CRC registers.

7.5.1 BGCRC Base Addresses

Table 7-5. BGCRC Base Address Table (C28)

Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU2 DMA CLA
Instance Structure Protected

BgcrcCla1Regs BGCRCCLA_REGS BGCRC_CLA1_BASE 0x0000_6380 YES YES - YES YES

BgcrcCpu1Regs BGCRCCPU_REGS BGCRC_CPU_BASE 0x0000_6340 YES YES - - YES

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7.5.2 BGCRC_REGS Registers

Table 7-6 lists the BGCRC_REGS registers. All register offset addresses not listed in Table 7-6 should be
considered as reserved locations and the register contents should not be modified.

Table 7-6. BGCRC_REGS Registers

Offset Acronym Register Name Write Protection Section
0h BGCRC_EN BGCRC Enable EALLOW Go
2h BGCRC_CTRL1 BGCRC Control register 1 EALLOW Go
4h BGCRC_CTRL2 BGCRC Control register 2 EALLOW Go
6h BGCRC_START_ADDR Start address for the BGCRC check EALLOW Go
8h BGCRC_SEED Seed for CRC calculation EALLOW Go
Eh BGCRC_GOLDEN Golden CRC to be compared against EALLOW Go
10h BGCRC_RESULT CRC calculated Go
12h BGCRC_CURR_ADDR Current address regsiter Go
1Ch BGCRC_WD_CFG BGCRC windowed watchdog configuration EALLOW Go
1Eh BGCRC_WD_MIN BGCRC windowed watchdog min value EALLOW Go
20h BGCRC_WD_MAX BGCRC windowed watchdog max value EALLOW Go
22h BGCRC_WD_CNT BGCRC windowed watchdog count Go
2Ah BGCRC_NMIFLG BGCRC NMI flag register Go
2Ch BGCRC_NMICLR BGCRC NMI flag clear register EALLOW Go
2Eh BGCRC_NMIFRC BGCRC NMI flag force register EALLOW Go
34h BGCRC_INTEN Interrupt enable EALLOW Go
36h BGCRC_INTFLG Interrupt flag Go
38h BGCRC_INTCLR Interrupt flag clear EALLOW Go
3Ah BGCRC_INTFRC Interrupt flag force EALLOW Go
3Ch BGCRC_LOCK BGCRC register map lockconfiguration EALLOW Go
3Eh BGCRC_COMMIT BGCRC register map commit configuration EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 7-7 shows the codes that are
used for access types in this section.

Table 7-7. BGCRC_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables

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Table 7-7. BGCRC_REGS Access Type

Codes (continued)
Access Type Code Description
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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7.5.2.1 BGCRC_EN Register (Offset = 0h) [reset = 0h]

BGCRC_EN is shown in Figure 7-8 and described in Table 7-8.
Return to the Summary Table.
BGCRC Enable

Figure 7-8. BGCRC_EN Register

31 30 29 28 27 26 25 24
RUN_STS RESERVED
R-0h R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED START
R-0-0h R-0/W-0h

Table 7-8. BGCRC_EN Register Field Descriptions

Bit Field Type Reset Description
31 RUN_STS R 0h Status bit:
0 : CRC module is IDLE
1 : CRC module is Active
This bit will remain set during BGCRC_CTRL2.TEST_HALT = 1
Reset type: CPUx.SYSRSn
30-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3-0 START R-0/W 0h Start Bit:
"1010": Kick-off CRC calculations
"any other value": ignored
Notes:
Setting this anytime during the CRC caluclation will reset and re-start
the CRC calculation. BGCRC_WD_CNT regsters will be reset
CRCEN.START = "1010". BGCRC_INTFLG, BGCRC_NMIFLG will
not be impacted by this configuration.
Reset type: CPUx.SYSRSn

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7.5.2.2 BGCRC_CTRL1 Register (Offset = 2h) [reset = 0h]

BGCRC_CTRL1 is shown in Figure 7-9 and described in Table 7-9.
Return to the Summary Table.
BGCRC Control register 1

Figure 7-9. BGCRC_CTRL1 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED NMIDIS
R-0-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED FREE_SOFT RESERVED
R-0-0h R/W-0h R-0-0h

Table 7-9. BGCRC_CTRL1 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19-16 NMIDIS R/W 0h 1010 : NMI is disabled
Any other value : NMI is enabled.
Reset type: CPUx.SYSRSn
15-5 RESERVED R-0 0h Reserved
4 FREE_SOFT R/W 0h Emulation control bit : This bit controls behaviour of CRC calculation
during emulation
0 : Soft, CRC module and CRC Watchdog stops immediately on
DEBUG SUSPEND (of CRC-master ).
1 : Free, CRC calcuation and CRC watchdog is not affected by
DEBUG HALT (of CRC-master )
Reset type: CPUx.SYSRSn
3-0 RESERVED R-0 0h Reserved

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7.5.2.3 BGCRC_CTRL2 Register (Offset = 4h) [reset = 0h]

BGCRC_CTRL2 is shown in Figure 7-10 and described in Table 7-10.
Return to the Summary Table.
BGCRC Control register 2

Figure 7-10. BGCRC_CTRL2 Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED SCRUB_MODE
R-0-0h R/W-0h
15 14 13 12 11 10 9 8
TEST_HALT RESERVED BLOCK_SIZE
R/W-0h R-0-0h R/W-0h
7 6 5 4 3 2 1 0
BLOCK_SIZE
R/W-0h

Table 7-10. BGCRC_CTRL2 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19-16 SCRUB_MODE R/W 0h Scrub mode configuration
1010 : Scrub mode, CRC of data is not compared with the golden
CRC. Error check is done using the ECC/Parity logic.
Any other value: CRC value is compared with golden CRC at the
end in addition to the data correctness check by ECC/Parity logic.
Notes:
1010 configuration is used for scrub mode (for data memories)
where the memory value is read and ECC/Parity logic is used for the
error detection. BGCRC_RESULT.CRC_VALUE is not updated in
this configuration.
Reset type: CPUx.SYSRSn
15-12 TEST_HALT R/W 0h Halt Bit :
1010 : Module operation is stopped
Any other value : CRC calaculation will continue/resume from where
it was halted
Notes:
BGCRC_EN.START = 1010 configuration with TEST_HALT = 1010
will halt the CRC calculation. The new check will resume when
TEST_HALT is configured to a value other than 1010
Reset type: CPUx.SYSRSn
11-10 RESERVED R-0 0h Reserved
9-0 BLOCK_SIZE R/W 0h Configures the block size for the check
0x0 : 256 Byte (default)
0x1 : 512 Byte
0x2 : 768 Byte
0x3 : 1KB
...
0x3FF : 256KB
(0xn : (n+1)*256Byte)
Reset type: CPUx.SYSRSn

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7.5.2.4 BGCRC_START_ADDR Register (Offset = 6h) [reset = 0h]

BGCRC_START_ADDR is shown in Figure 7-11 and described in Table 7-11.
Return to the Summary Table.
Start address for the BGCRC check

Figure 7-11. BGCRC_START_ADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
START_ADDRESS
R/W-0h

Table 7-11. BGCRC_START_ADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 START_ADDRESS R/W 0h START_ADDRESS indicates the start point of the test.
(For CPU_CRC, this will be the CPU address. For CLA_CRC, this
will be the CLA address where the memory is mapped)
Reset type: CPUx.SYSRSn

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7.5.2.5 BGCRC_SEED Register (Offset = 8h) [reset = 0h]

BGCRC_SEED is shown in Figure 7-12 and described in Table 7-12.
Return to the Summary Table.
Seed for CRC calculation

Figure 7-12. BGCRC_SEED Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEED
R/W-0h

Table 7-12. BGCRC_SEED Register Field Descriptions

Bit Field Type Reset Description
31-0 SEED R/W 0h Initial value of CRC, this value is coiped to the CRC register on
triggering CRC calculation by writing to START bit.
Reset type: CPUx.SYSRSn

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7.5.2.6 BGCRC_GOLDEN Register (Offset = Eh) [reset = 0h]

BGCRC_GOLDEN is shown in Figure 7-13 and described in Table 7-13.
Return to the Summary Table.
Golden CRC to be compared against

Figure 7-13. BGCRC_GOLDEN Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_VALUE
R/W-0h

Table 7-13. BGCRC_GOLDEN Register Field Descriptions

Bit Field Type Reset Description
31-0 CRC_VALUE R/W 0h Golden CRC register:
If CRC check is enabled, the calcuated CRC value is compared with
golden CRC and status is updated.
Reset type: CPUx.SYSRSn

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7.5.2.7 BGCRC_RESULT Register (Offset = 10h) [reset = 0h]

BGCRC_RESULT is shown in Figure 7-14 and described in Table 7-14.
Return to the Summary Table.
CRC calculated

Figure 7-14. BGCRC_RESULT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_VALUE
R-0h

Table 7-14. BGCRC_RESULT Register Field Descriptions

Bit Field Type Reset Description
31-0 CRC_VALUE R 0h CRC result register
This reister value will be updated only on the completion of CRC
check on a block of data as programmed by
BGCRC_CTRL2.BLOCK_SIZE.
Reset type: CPUx.SYSRSn

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7.5.2.8 BGCRC_CURR_ADDR Register (Offset = 12h) [reset = 0h]

BGCRC_CURR_ADDR is shown in Figure 7-15 and described in Table 7-15.
Return to the Summary Table.
Current address regsiter

Figure 7-15. BGCRC_CURR_ADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRENT_ADDR
R-0h

Table 7-15. BGCRC_CURR_ADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 CURRENT_ADDR R 0h Current address from where the data is fetched.
During a failure, the CURRENT_ADDR field indicates the value from
where the last fetch happened.
Reset type: CPUx.SYSRSn

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7.5.2.9 BGCRC_WD_CFG Register (Offset = 1Ch) [reset = 0h]

BGCRC_WD_CFG is shown in Figure 7-16 and described in Table 7-16.
Return to the Summary Table.
BGCRC windowed watchdog configuration

Figure 7-16. BGCRC_WD_CFG Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED WDDIS
R-0-0h R/W-0h

Table 7-16. BGCRC_WD_CFG Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3-0 WDDIS R/W 0h 1010: CRC Watchdog counter is disabled.
Any other value: CRC watchdog is enabled
Watchdog is an upcounter and starts counting when
BGCRC_EN.START is asserted. Watchdog continues to count
during TEST_HALT state also(BGCRC_CTRL2.TEST_HALT =
"1010"). CRC watchdog can be disabled during TEST_HALT by
explicit configuration. (BGCRC_WD_CFG.WDDIS = 1010). Once the
watchdog is disabled and re-enabled, watchdog count resumes from
the previous disabled point.
Reset type: CPUx.SYSRSn

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7.5.2.10 BGCRC_WD_MIN Register (Offset = 1Eh) [reset = 0h]

BGCRC_WD_MIN is shown in Figure 7-17 and described in Table 7-17.
Return to the Summary Table.
BGCRC windowed watchdog min value

Figure 7-17. BGCRC_WD_MIN Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MINVAL
R/W-0h

Table 7-17. BGCRC_WD_MIN Register Field Descriptions

Bit Field Type Reset Description
31-0 MINVAL R/W 0h If the CRC computation completes before
BGCRC_WD_MIN.MINVAL FAIL_STATUS.WD_UNDERFLOW flag
gets set.
Reset type: CPUx.SYSRSn

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7.5.2.11 BGCRC_WD_MAX Register (Offset = 20h) [reset = FFFFFFFFh]

BGCRC_WD_MAX is shown in Figure 7-18 and described in Table 7-18.
Return to the Summary Table.
BGCRC windowed watchdog max value

Figure 7-18. BGCRC_WD_MAX Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAXVAL
R/W-FFFFFFFFh

Table 7-18. BGCRC_WD_MAX Register Field Descriptions

Bit Field Type Reset Description
31-0 MAXVAL R/W FFFFFFFFh If the CRC computation doesn't complete before
BGCRC_WD_MIN.MAXVAL FAIL_STATUS.WD_OVERFLOW flag
gets set.
Reset type: CPUx.SYSRSn

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7.5.2.12 BGCRC_WD_CNT Register (Offset = 22h) [reset = 0h]

BGCRC_WD_CNT is shown in Figure 7-19 and described in Table 7-19.
Return to the Summary Table.
BGCRC windowed watchdog count

Figure 7-19. BGCRC_WD_CNT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WD_CNT
R-0h

Table 7-19. BGCRC_WD_CNT Register Field Descriptions

Bit Field Type Reset Description
31-0 WD_CNT R 0h CRC windowed watchdog counter value
Counter value freezes at the end of CRC computation and will be
reloaded only by BGCRC_EN.START = "1010" configuration.
BGCRC_WD_CNT register freezes when a failure occurs.
Reset type: CPUx.SYSRSn

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7.5.2.13 BGCRC_NMIFLG Register (Offset = 2Ah) [reset = 0h]

BGCRC_NMIFLG is shown in Figure 7-20 and described in Table 7-20.
Return to the Summary Table.
BGCRC NMI flag register

Figure 7-20. BGCRC_NMIFLG Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL RESERVED RESERVED
W OW E_ERR BLE_ERR
R-0-0h R-0h R-0h R-0h R-0h R-0h R-0-0h R-0-0h

Table 7-20. BGCRC_NMIFLG Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R 0h Windowed watchdog Overflow.
1 : Test did not complete before BGCRC_WD_MAX.MAXVAL
0 : No such errors
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R 0h Windowed watchdog underflow.
1 : Test completed before BGCRC_WD_MIN.MINVAL
0 : No such errors
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R 0h Correctable error indication:
0 : No ECC correctable error during memory read
1 : Correctable ECC error during memory read
Note: ECC computation is done during every memory read.
(Correctable errors are not ignored since the module doesn't write-
back corrected value. The error remains in the memory and required
corrective action need to be taken by CPU/CLA as part of ISR)
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R 0h Uncorrectable error indication:
0 : No ECC-uncorrectable/Parity error during memory read
1 : ECC-uncorrectable/Parity error during memory read
Note: ECC/Parity check is done during every memory read.
Reset type: CPUx.SYSRSn
2 CRC_FAIL R 0h CRC FAIL interrupt
0 : No failure in CRC check.
1 : CRC check failure
Note: Comparion is enabled only after CRC calc is completed
Reset type: CPUx.SYSRSn
1 RESERVED R-0 0h Reserved
0 RESERVED R-0 0h Reserved

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7.5.2.14 BGCRC_NMICLR Register (Offset = 2Ch) [reset = 0h]

BGCRC_NMICLR is shown in Figure 7-21 and described in Table 7-21.
Return to the Summary Table.
BGCRC NMI flag clear register

Figure 7-21. BGCRC_NMICLR Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL RESERVED RESERVED
W OW E_ERR BLE_ERR
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0-0h R-0-0h

Table 7-21. BGCRC_NMICLR Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R-0/W1S 0h Clear WD_OVERFLOW NMI flag
0 No effect
1 Clears NMI flag
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R-0/W1S 0h Clear WD_UNDERFLOW NMI flag
0 No effect
1 Clears NMI flag
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R-0/W1S 0h Clear CORRECTABLE_ERR NMI flag
0 No effect
1 Clears NMI flag
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R-0/W1S 0h Clear UNCORRECTABLE_ERROR NMI flag
0 No effect
1 Clears NMI flag
Reset type: CPUx.SYSRSn
2 CRC_FAIL R-0/W1S 0h Clear CRC_FAIL NMI flag
0 No effect
1 Clears NMI flag
Reset type: CPUx.SYSRSn
1 RESERVED R-0 0h Reserved
0 RESERVED R-0 0h Reserved

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7.5.2.15 BGCRC_NMIFRC Register (Offset = 2Eh) [reset = 0h]

BGCRC_NMIFRC is shown in Figure 7-22 and described in Table 7-22.
Return to the Summary Table.
BGCRC NMI flag force register

Figure 7-22. BGCRC_NMIFRC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL RESERVED RESERVED
W OW E_ERR BLE_ERR
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0-0h R-0-0h

Table 7-22. BGCRC_NMIFRC Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R-0/W1S 0h Force WD_OVERFLOW NMI flag
0 No effect
1 force NMI flag
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R-0/W1S 0h Force WD_UNDERFLOW NMI flag
0 No effect
1 force NMI flag
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R-0/W1S 0h Force CORRECTABLE_ERR NMI flag
0 No effect
1 force NMI flag
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R-0/W1S 0h Force UNCORRECTABLE_ERR NMI flag
0 No effect
1 force NMI flag
Reset type: CPUx.SYSRSn
2 CRC_FAIL R-0/W1S 0h Force CRC_FAIL NMI flag
0 No effect
1 force NMI flag
Reset type: CPUx.SYSRSn
1 RESERVED R-0 0h Reserved
0 RESERVED R-0 0h Reserved

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7.5.2.16 BGCRC_INTEN Register (Offset = 34h) [reset = 0h]

BGCRC_INTEN is shown in Figure 7-23 and described in Table 7-23.
Return to the Summary Table.
Interrupt enable

Figure 7-23. BGCRC_INTEN Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL TEST_DONE RESERVED
W OW E_ERR BLE_ERR
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0-0h

Table 7-23. BGCRC_INTEN Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R 0h Reserved
6 WD_OVERFLOW R/W 0h 0 WD_OVERFLOW Interrupt disabled
1 WD_OVERFLOW Interrupt enabled
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R/W 0h 0 WD_UNDERFLOW Interrupt disabled
1 WD_UNDERFLOW Interrupt enabled
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R/W 0h 0 CORRECTABLE_ERR Interrupt disabled
1 CORRECTABLE_ERR Interrupt enabled
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R/W 0h 0 UNCORRECTABLE_ERR Interrupt disabled
1 UNCORRECTABLE_ERR Interrupt enabled
Reset type: CPUx.SYSRSn
2 CRC_FAIL R/W 0h 0 CRC_FAIL Interrupt disabled
1 CRC_FAIL Interrupt enabled
Reset type: CPUx.SYSRSn
1 TEST_DONE R/W 0h 0 TEST_DONE Interrupt disabled
1 TEST_DONE Interrupt enabled
Reset type: CPUx.SYSRSn
0 RESERVED R-0 0h Reserved

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7.5.2.17 BGCRC_INTFLG Register (Offset = 36h) [reset = 0h]

BGCRC_INTFLG is shown in Figure 7-24 and described in Table 7-24.
Return to the Summary Table.
Interrupt flag

Figure 7-24. BGCRC_INTFLG Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL TEST_DONE INT
W OW E_ERR BLE_ERR
R-0-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-24. BGCRC_INTFLG Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R 0h Windowed watchdog Overflow.
1 : Test did not completed before BGCRC_WD_MAX.MAXVAL
0 : No such errors
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R 0h Windowed watchdog underflow.
1 : Test completed before BGCRC_WD_MIN.MINVAL
0 : No such errors
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R 0h Correctable error indication:
0 : No ECC correctable error during memory read
1 : Correctable ECC error during memory read
Note: ECC computation is done during every memory read.
(Correctable errors are not ignored since the module doesn't write-
back corrected value. The error remains in the memory and required
corrective action need to be taken by CPU/CLA as part of ISR)
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R 0h uncorrectable error indication:
0 : No ECC-uncorrectable/Parity error during memory read
1 : ECC-uncorrectable/Parity error during memory read
Note: ECC/Parity check is done during every memory read.
Reset type: CPUx.SYSRSn
2 CRC_FAIL R 0h CRC fail interrupt
0 : No failure of CRC check
1 : CRC check failure
Note: Comparion is enabled only after CRC calc is completed
Reset type: CPUx.SYSRSn
1 TEST_DONE R 0h Done Interrupt Status flag
0 CRC calculation is in progress or CRC module is idle.
1 CRC calculation is done.
Note: TEST_DONE flag will get set on CRC calculation completion
even in case of CRC mismatch
Reset type: CPUx.SYSRSn

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Table 7-24. BGCRC_INTFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INT R 0h Global Interrupt Status flag
0 No interrupt generated
1 Interrupt was generated
Reset type: CPUx.SYSRSn

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7.5.2.18 BGCRC_INTCLR Register (Offset = 38h) [reset = 0h]

BGCRC_INTCLR is shown in Figure 7-25 and described in Table 7-25.
Return to the Summary Table.
Interrupt flag clear

Figure 7-25. BGCRC_INTCLR Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL TEST_DONE INT
W OW E_ERR BLE_ERR
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-25. BGCRC_INTCLR Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
2 CRC_FAIL R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
1 TEST_DONE R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
0 INT R-0/W1S 0h Global Interrupt Clear
0 No effect
1 Clears the interrupt flag and enables further interrupts to be
generated if an event flags is set to 1.
Reset type: CPUx.SYSRSn

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7.5.2.19 BGCRC_INTFRC Register (Offset = 3Ah) [reset = 0h]

BGCRC_INTFRC is shown in Figure 7-26 and described in Table 7-26.
Return to the Summary Table.
Interrupt flag force

Figure 7-26. BGCRC_INTFRC Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
RESERVED
R-0-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL TEST_DONE RESERVED
W OW E_ERR BLE_ERR
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0-0h

Table 7-26. BGCRC_INTFRC Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
2 CRC_FAIL R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
1 TEST_DONE R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
0 RESERVED R-0 0h Reserved

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7.5.2.20 BGCRC_LOCK Register (Offset = 3Ch) [reset = 0h]

BGCRC_LOCK is shown in Figure 7-27 and described in Table 7-27.
Return to the Summary Table.
BGCRC register map lockconfiguration

Figure 7-27. BGCRC_LOCK Register

31 30 29 28 27 26 25 24
RESERVED RESERVED BGCRC_INTFR RESERVED RESERVED BGCRC_INTE RESERVED RESERVED
C N
R-0-0h R-0-0h R/W-0h R-0-0h R-0-0h R/W-0h R-0-0h R-0-0h
23 22 21 20 19 18 17 16
BGCRC_NMIF RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BGCRC_WD_
RC MAX
R/W-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R/W-0h
15 14 13 12 11 10 9 8
BGCRC_WD_ BGCRC_WD_C RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
MIN FG
R/W-0h R/W-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h
7 6 5 4 3 2 1 0
BGCRC_GOLD RESERVED RESERVED BGCRC_SEED BGCRC_STAR BGCRC_CTRL BGCRC_CTRL BGCRC_EN
EN T_ADDR 2 1
R/W-0h R-0-0h R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-27. BGCRC_LOCK Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0 0h Reserved
30 RESERVED R-0 0h Reserved
29 BGCRC_INTFRC R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
28 RESERVED R-0 0h Reserved
27 RESERVED R-0 0h Reserved
26 BGCRC_INTEN R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
25 RESERVED R-0 0h Reserved
24 RESERVED R-0 0h Reserved
23 BGCRC_NMIFRC R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
22 RESERVED R-0 0h Reserved
21 RESERVED R-0 0h Reserved
20 RESERVED R-0 0h Reserved
19 RESERVED R-0 0h Reserved
18 RESERVED R-0 0h Reserved
17 RESERVED R-0 0h Reserved
16 BGCRC_WD_MAX R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
15 BGCRC_WD_MIN R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn

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Table 7-27. BGCRC_LOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
14 BGCRC_WD_CFG R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
13 RESERVED R-0 0h Reserved
12 RESERVED R-0 0h Reserved
11 RESERVED R-0 0h Reserved
10 RESERVED R-0 0h Reserved
9 RESERVED R-0 0h Reserved
8 RESERVED R-0 0h Reserved
7 BGCRC_GOLDEN R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
6 RESERVED R-0 0h Reserved
5 RESERVED R-0 0h Reserved
4 BGCRC_SEED R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
3 BGCRC_START_ADDR R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
2 BGCRC_CTRL2 R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
1 BGCRC_CTRL1 R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
0 BGCRC_EN R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn

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7.5.2.21 BGCRC_COMMIT Register (Offset = 3Eh) [reset = 0h]

BGCRC_COMMIT is shown in Figure 7-28 and described in Table 7-28.
Return to the Summary Table.
BGCRC register map commit configuration

Figure 7-28. BGCRC_COMMIT Register

31 30 29 28 27 26 25 24
RESERVED RESERVED BGCRC_INTFR RESERVED RESERVED BGCRC_INTE RESERVED RESERVED
C N
R-0-0h R-0-0h R/WSonce-0h R-0-0h R-0-0h R/WSonce-0h R-0-0h R-0-0h
23 22 21 20 19 18 17 16
BGCRC_NMIF RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BGCRC_WD_
RC MAX
R/WSonce-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R/WSonce-0h
15 14 13 12 11 10 9 8
BGCRC_WD_ BGCRC_WD_C RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
MIN FG
R/WSonce-0h R/WSonce-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h
7 6 5 4 3 2 1 0
BGCRC_GOLD RESERVED RESERVED BGCRC_SEED BGCRC_STAR BGCRC_CTRL BGCRC_CTRL BGCRC_EN
EN T_ADDR 2 1
R/WSonce-0h R-0-0h R-0-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 7-28. BGCRC_COMMIT Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0 0h Reserved
30 RESERVED R-0 0h Reserved
29 BGCRC_INTFRC R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
28 RESERVED R-0 0h Reserved
27 RESERVED R-0 0h Reserved
26 BGCRC_INTEN R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
25 RESERVED R-0 0h Reserved
24 RESERVED R-0 0h Reserved
23 BGCRC_NMIFRC R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
22 RESERVED R-0 0h Reserved
21 RESERVED R-0 0h Reserved
20 RESERVED R-0 0h Reserved
19 RESERVED R-0 0h Reserved
18 RESERVED R-0 0h Reserved
17 RESERVED R-0 0h Reserved

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Table 7-28. BGCRC_COMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
16 BGCRC_WD_MAX R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
15 BGCRC_WD_MIN R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
14 BGCRC_WD_CFG R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
13 RESERVED R-0 0h Reserved
12 RESERVED R-0 0h Reserved
11 RESERVED R-0 0h Reserved
10 RESERVED R-0 0h Reserved
9 RESERVED R-0 0h Reserved
8 RESERVED R-0 0h Reserved
7 BGCRC_GOLDEN R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
6 RESERVED R-0 0h Reserved
5 RESERVED R-0 0h Reserved
4 BGCRC_SEED R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
3 BGCRC_START_ADDR R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
2 BGCRC_CTRL2 R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
1 BGCRC_CTRL1 R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
0 BGCRC_EN R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn

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 Chapter 8
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Control Law Accelerator (CLA)

The Control Law Accelerator (CLA) Type-2 is an independent, fully-programmable, 32-bit floating-point
math processor that brings concurrent control-loop execution to the C28x family. The low interrupt latency
of the CLA allows it to read ADC samples "just-in-time." This significantly reduces the ADC sample to
output delay to enable faster system response and higher MHz control loops. By using the CLA to service
time-critical control loops, the main CPU is free to perform other system tasks such as communications
and diagnostics. This chapter provides an overview of the architectural structure and components of the
control law accelerator.

Topic ........................................................................................................................... Page

8.1 Introduction ..................................................................................................... 926

8.2 Features .......................................................................................................... 926
8.3 CLA Interface ................................................................................................... 928
8.4 CLA, DMA, and CPU Arbitration ......................................................................... 935
8.5 CLA Configuration and Debug ........................................................................... 936
8.6 Pipeline ........................................................................................................... 940
8.7 Instruction Set.................................................................................................. 946
8.8 CLA Registers ................................................................................................ 1063

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8.1 Introduction
The Control Law Accelerator extends the capabilities of the C28x CPU by adding parallel processing.
Time-critical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the
CLA enables faster system response and higher frequency control loops. Utilizing the CLA for time-critical
tasks frees up the main CPU to perform other system and communication functions concurrently.

8.2 Features
The following is a list of major features of the CLA:
• C compilers are available for CLA software development.
• Clocked at the same rate as the main CPU (SYSCLKOUT).
• An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
• Program Address Bus (PAB) and Program Data Bus (PDB)
• Data Read Address Bus (DRAB), Data Read Data Bus (DRDB), Data Write Address Bus
(DWAB), and Data Write Data Bus (DWDB)
– Independent eight stage pipeline.
– program counter (MPC)
– Four 32-bit result registers (MR0-MR3)
– Two 16-bit auxiliary registers (MAR0, MAR1)
– Status register (MSTF)
• Instruction set includes:
– IEEE single-precision (32-bit) floating point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions.
– Conditional branch and call
– Data load/store operations
• The CLA program code can consist of up to eight tasks or interrupt service routines, or 7 tasks and a
main background task.
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the configurable CLA program memory space.
– One task is serviced at a time until its completion. There is no nesting of tasks.
– Upon task completion a task-specific interrupt is flagged within the PIE.
– When a task finishes the next highest-priority pending task is automatically started.
– The Type-2 CLA can have a main task that runs continuously in the background, while other high
priority events trigger a foreground task.
• Task trigger mechanisms:
– C28x CPU via the IACK instruction
– Task1 to Task8: up to 256 possible trigger sources from peripherals connected to the shared bus
on which the CLA assumes secondary ownership.
– Task8 can be set to be the background task, while Tasks 1 through 7 take peripheral triggers.
• Memory and Shared Peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– Two dedicated message RAMs for communication between the CLA and the DMA.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.

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Figure 8-1. CLA (Type 2) Block Diagram

CLA Control
Register Set

MIFR(16)
MPERINT1 MIOVF(16) CLA_INT1
From Shared to to
Peripherals MPERINT8 MICLR(16) CLA_INT8
MICLROVF(16) C28x
PIE INT11
MIFRC(16) CPU
MIER(16) INT12
MIRUN(16)
LVF
MCTLBGRND(16)
LUF
MSTSBGRND(16)
CLA1SOFTINTEN(16)
CLA1INTFRC(16)
SYSCLK
CLA Clock Enable MVECT1(16)
CPU Read/Write Data Bus
SYSRS MVECT2(16)
MVECT3(16)
MVECT4(16) CLA Program
MVECT5(16) CLA Program Bus Memory (LSx)
MVECT6(16)
MVECT7(16)
MVECT8(16) LSxMSEL[MSEL_LSx]
MVECTBGRND(16) LSxCLAPGM[CLAPGM_LSx]
MVECTBGRNDACTIVE(16)
MPSACTL(16)

CPU Data Bus

MPSA1(32) CLA Data
MPSA2(32) Memory (LSx)

MCTL(16)
CLA Data Bus

CLA Message
CLA Execution
RAMs
Register Set

MPC(16)
MSTF(32)
MR0(32)
MR1(32) Shared
MR2(32) MEALLOW Peripherals
MR3(32)
MAR0(16)
MAR1(16)
CPU Read Data Bus

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8.3 CLA Interface

This section describes how the C28x main CPU can interface to the CLA and vice versa.

8.3.1 CLA Memory

The CLA can access three types of memory: program, data and message RAMs. The behavior and
arbitration for each type of memory is described in detail below. The CLA RAMs are protected by the
DCSM module. Refer to the DCSM section of this manual for more details on the security scheme.
• CLA Program Memory
The CLA program can be loaded any of the local shared memories (LSxRAM). At reset, all memory
blocks are mapped to the CPU. While mapped to the CPU space, the CPU can copy the CLA program
code into the memory. During debug, the memory can also be loaded directly by Code Composer
Studio™ IDE.
Once the memory is initialized with CLA code, the CPU maps it to the CLA program space by:
1. Assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit.
2. Specifying the memory block as a code block for the CLA by writing a 1 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit.
When a memory block is configured as CLA program memory, debug accesses are allowed only on
cycles where the CLA is not fetching a new instruction. A detailed explanation of the memory
configurations and access arbitration (CPU, CLA, and DEBUG) process can be found in Section 3.12.
All CLA program fetches are performed as 32-bit read operations and all opcodes must be aligned to
an even address. Since all CLA opcodes are 32-bits, this alignment occurs naturally.
• CLA Data Memory
Any of the device’s LSxRAMs can serve as data memory blocks to the CLA. At reset, all blocks are
mapped to the CPU memory space, whereby the CPU can initialize the memory with data tables,
coefficients, and so on, for the CLA to use.
Once the memory is initialized with CLA data, the CPU maps it to the CLA data space by:
1. Assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit.
2. Specifying the memory block as a data block for the CLA by writing a 0 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit. The value of this bit at reset is 0.
When a memory block is configured as CLA data memory, CLA read and write accesses are arbitrated
along with CPU accesses. The user has the option of turning on CPU fetch or write protection to the
memory by writing to the appropriate bits of the MemCfgRegs.LSxACCPROTx registers. A detailed
explanation of the memory configurations and access arbitration (CPU, CLA, and DEBUG) process
can be found in Section 3.12.
• CLA Shared Message RAMs
There are two memory blocks for data sharing and communication between the CLA and the CPU.
The message RAMs are always mapped to both CPU and CLA memory spaces, and only data access
is allowed; no program fetches can be performed.
– CLA to CPU Message RAM
The CLA can use this block to pass data to the CPU. This block is both readable and writable by
the CLA. This block is also readable by the CPU but writes by the CPU are ignored.
– CPU to CLA Message RAM
The CPU can use this block to pass data and messages to the CLA. This message RAM is both
readable and writable by the CPU. The CLA can perform reads but writes by the CLA are ignored.

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8.3.2 CLA Memory Bus

The CLA has dedicated bus architecture similar to that of the C28x CPU where there are separate
program read, data read, and data write buses. Thus, there can be simultaneous instruction fetch, data
read, and data write in a single cycle. Like the C28x CPU, the CLA expects memory logic to align any 32-
bit read or write to an even address. If the address-generation logic generates an odd address, the CLA
will begin reading or writing at the previous even address. This alignment does not affect the address
values generated by the address-generation logic.
• CLA Program Bus
The CLA program bus has an access range of 32K 32-bit instructions. Since all CLA instructions are
32 bits, this bus always fetches 32 bits at a time and the opcodes must be even-word aligned. The
amount of program space available for the CLA is limited to the number of available LSxRAM blocks.
This number is device-dependent and will be described in the device-specific data manual.
• CLA Data Read Bus
The CLA data read bus has a 64K x 16 address range. The bus can perform 16 or 32-bit reads and
will automatically stall if there are memory access conflicts. The data read bus has access to both the
message RAMs, CLA data memory, and the shared peripherals.
• CLA Data Write Bus
The CLA data write bus has a 64K x 16 address range. This bus can perform 16 or 32-bit writes. The
bus will automatically stall if there are memory access conflicts. The data write bus has access to the
CLA to CPU message RAM, CLA data memory, and the shared peripherals.

8.3.3 Shared Peripherals and EALLOW Protection

For a given CPU subsystem, the CPU, CLA, and DMA can share access to some peripherals. There is a
3-way arbitration among the different master's that is described in Section 8.4. Each peripheral has an
access control register with two bit fields, CPUnAC, CLAnAC, and DMAnAC (n being the instance) that
determine what kind of access is given to that particular master.
Note: The CLA read access time to the bus is 2-wait states while write access is 0-wait.
Refer to the device data manual for the list of peripherals connected to the bus.
Several peripheral control registers are protected from spurious 28x CPU writes by the EALLOW
protection mechanism. These same registers are also protected from spurious CLA writes. The EALLOW
bit in the CPU status register 1 (ST1) indicates the state of protection for the CPU. Likewise the
MEALLOW bit in the CLA status register (MSTF) indicates the state of write protection for the CLA. The
MEALLOW CLA instruction enables write access by the CLA to EALLOW protected registers. Likewise the
MEDIS CLA instruction will disable write access. This way the CLA can enable/disable write access
independent of the CPU.
The ADC offers the option to generate an early interrupt pulse at the start of a sample conversion. If this
option is used to start an ADC-triggered CLA task, the user may use the intervening cycles, until the
completion of the conversion, to perform preliminary calculations or loads and stores before finally reading
the ADC value. The CLA pipeline activity for this scenario is shown in Section 8.6.

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8.3.4 CLA Tasks and Interrupt Vectors

The CLA program code is divided up into tasks or interrupt service routines. Tasks do not have a fixed
starting location or length. The CLA program memory can be divided up as desired. The CLA uses the
contents of the interrupt vectors (MVECT1 to MVECT8) to determine where a task begins; tasks are
terminated by the MSTOP instruction.
The CLA supports eight tasks. Task 1 has the highest priority and task 8 has the lowest priority. The Type-
2 CLA offers the option of setting the lowest priority task, for example, Task 8, as a background task that,
once triggered, runs continuously until the user either terminates it or resets the CLA or the device. The
remaining tasks, 1 through 7, maintain their priority levels and interrupt the background task when
triggered.
The background task is enabled by setting the BGEN bit in the MCTLBGRND register; this causes the
hardware to disable task 8 in the MIER register. The background task derives its interrupt vector from the
MVECTBGRND register instead of MVECT8.
A task can be requested by a peripheral interrupt or by software:
• Peripheral interrupt trigger
Each task can be triggered by software-selectable interrupt sources. The trigger for each task is
defined by writing an appropriate value to the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit
field. Each option specifies an interrupt source from a specific peripheral on the shared bus. The
peripheral interrupt triggers are listed in Table 8-1.

Table 8-1. Configuration Options

Select Value (8-bit) CLA Trigger Source
0 Software Trigger
1 ADCA1_INT
2 ADCA2_INT
3 ADCA3_INT
4 ADCA4_INT
5 ADCA_EVT_INT
6 ADCB1_INT
7 ADCB2_INT
8 ADCB3_INT
9 ADCB4_INT
10 ADCB_EVT_INT
11 ADCC1_INT
12 ADCC2_INT
13 ADCC3_INT
14 ADCC4_INT
15 ADCC_EVT_INT
16 ADCD1_INT
17 ADCD2_INT
18 ADCD3_INT
19 ADCD4_INT
20 ADCD_EVT_INT
21-28 Reserved
29 XINT1
30 XINT2
31 XINT3
32 XINT4
33 XINT5
34-35 Reserved
36 EPWM1INT

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Table 8-1. Configuration Options (continued)

Select Value (8-bit) CLA Trigger Source
37 EPWM2INT
38 EPWM3INT
39 EPWM4INT
40 EPWM5INT
41 EPWM6INT
42 EPWM7INT
43 EPWM8INT
44 EPWM9INT
45 EPWM10INT
46 EPWM11NT
47 EPWM12INT
48 EPWM13INT
49 EPWM14INT
50 EPWM15INT
51 EPWM16INT
52 MCANA_EVT0
53 MCANA_EVT1
54 MCANA_EVT2
55-67 Reserved
68 TINT0
69 TINT1
70 TINT2
71 MXINTA
72 MRINTA
73 MXINTB
74 MRINTB
75 ECAP1INT
76 ECAP2INT
77 ECAP3INT
78 ECAP4INT
79 ECAP5INT
80 ECAP6INT
81 ECAP7INT
82 Reserved
83 EQEP1INT
84 EQEP2INT
85 EQEP3INT
86 Reserved
87 Reserved
88 Reserved
89 Reserved
90 Reserved
91 Reserved
92 ECAP6INT2
93 ECAP7INT2
94 Reserved
95 SD1INT

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Table 8-1. Configuration Options (continued)

Select Value (8-bit) CLA Trigger Source
96 SD2INT
97 Reserved
98 Reserved
99 Reserved
100 Reserved
101 Reserved
102 Reserved
103 ECAT_SYNC0
104 ECAT_SYNC1
105 PMBUSAINT
106 Reserved
107 Reserved
108 Reserved
109 SPITXINTA
110 SPIRXINTA
111 SPITXINTB
112 SPIRXINTB
113 SPITXINTC
114 SPIRXINTC
115 SPITXINTD
116 SPIRXINTD
117 CLB5INT
118 CLB6INT
119 CLB7INT
120 CLB8INT
121 CLA1CRC_INT
122 Reserved
123 FSITXA_INT1
124 FSITXA_INT2
125 FSIRXA_INT1
126 FSIRXA_INT2
127 CLB1INT
128 CLB2INT
129 CLB3INT
130 CLB4INT
131-142 Reserved
143 SD1_INT1
144 SD1_INT2
145 SD1_INT3
146 SD1_INT4
147 SD2_INT1
148 SD2_INT2
149 SD2_INT3
150 SD2_INT4
151-154 Reserved
155 FSITXB_INT1
156 FSITXB_INT2

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Table 8-1. Configuration Options (continued)

Select Value (8-bit) CLA Trigger Source
157 FSIRXB_INT1
158 FSIRXB_INT2
159 FSIRXC_INT1
160 FSIRXC_INT2
161 FSIRXD_INT1
162 FSIRXD_INT2
163 FSIRXE_INT1
164 FSIRXE_INT2
165 FSIRXF_INT1
166 FSIRXF_INT2
167 FSIRXG_INT1
168 FSIRXG_INT2
169 FSIRXH_INT1
170 FSIRXH_INT2
171-255 Reserved

For example, Task 1 (MVECT1) can be set to trigger on EPWMINT1 by writing 36 to

DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK1. To disable the triggering of a task by a
peripheral, the user must set the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit field to 0. It
should be noted that a CLA task only triggers on a level transition (an edge) of the configured interrupt
source.
• Software Trigger
CPU software can trigger tasks by writing to the MIFRC register or by the IACK instruction. Using the
IACK instruction is more efficient because it does not require you to issue an EALLOW to set MIFR
bits. Set the MCTL[IACKE] bit to enable the IACK feature. Each bit in the operand of the IACK
instruction corresponds to a task. For example IACK #0x0001 will set bit 0 in the MIFR register to start
task 1. Likewise IACK #0x0003 will set bits 0 and 1 in the MIFR register to start task 1 and task 2.
• Background Task
The Type-2 CLA allows the user to use Task 8 as a background task that runs continuously until the
user disables it or resets the device (or the CLA using a soft reset). The background task vector is
given by the MVECTBGRND register and its operation controlled by the MCTLBGRND register; it is
enabled by setting the BGEN bit to 1. The user can then kick off the task through software by writing a
1 to the BGSTART bit (TRIGEN must be 0), or through a peripheral by setting the TRIGEN bit to 1 and
then setting the trigger source in the bit-field, DmaClaSrcSelRegs.CLA1TASKSRCSEL2.bit.TASK8. By
default the background task is interruptible; the highest priority pending task will be executed first.
When a task completes, and there aren’t any pending tasks, the execution returns to the background
task. The CLA keeps track of the branching point by saving the return address to the
MVECTBGRNDACTIVE register, and then popping this address to the MPC when execution returns.
The user may choose to make sections of the background task un-interruptible; it is possible to do this
with the MSETC BGINTM assembly instruction.
Subsequently, enabling interrupts with the MCLRC BGINTM instruction.
The background interrupt mask bit, BGINTM, can be queried in the MSTSBGRND register. This
register also provides the current status of the background task; if it is currently executing, the RUN bit
is set to 1, if another trigger for the background task is received while it has already started the
overflow (BGOVF) bit is set.
The CLA has its own fetch mechanism and can run and execute a task independently of the CPU. Only
one task is serviced at a time; there is no nesting of tasks unless the background task in enabled, then
one level of nesting is possible. The task currently running is indicated in the MIRUN register; if the
background task is enabled, and running, it is reflected in the MSTSBGRND register (the RUN bit).

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Interrupts that have been received but not yet serviced are indicated in the flag register (MIFR). If an
interrupt request from a peripheral is received and that same task is already flagged, then the overflow
flag bit is set. Overflow flags will remain set until they are cleared by the CPU. If the CLA is idle (no task is
currently running) or is executing the background task, then the highest priority interrupt request that is
both flagged (MIFR) and enabled (MIER) will start.

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The flow is as follows:

1. The associated RUN register bit is set (MIRUN) and the flag bit (MIFR) is cleared.
2. The CLA begins execution at the location indicated by the associated interrupt vector (MVECTx).
MVECT contains the absolute 16-bit address of the task in the lower 64K memory space. If a task is
interrupting the background task then the current program address is stored in the
MVECTBGRNDACTIVE register before execution jumps to the task; this saved address is restored to
the MPC when the task completes and execution returns to the background task.
3. The CLA executes instructions until the MSTOP instruction is found. This indicates the end of the task.
4. The MIRUN bit is cleared.
5. The task-specific interrupt to the PIE is issued. This informs the main CPU that the task has
completed.
6. The CLA returns to idle (or to the background task, if enabled). Once a task completes the next
highest-priority pending task is automatically serviced and this sequence repeats.

8.3.5 CLA Software Interrupt to CPU

The CLA can issue a software interrupt to the C28x CPU at any point in the code through the use of the
CLA1SOFTINTEN and CLA1INTFRC registers. Please see Section 8.8 for a description of these registers.
If a software interrupt is selected for a CLA task, then an end-of-task interrupt will not be issued to the
C28x when that task completes.

8.4 CLA, DMA, and CPU Arbitration

Typically, CLA activity is independent of the CPU activity. Under the circumstance where the CLA, DMA,
or CPU attempt to concurrently access memory or a peripheral register within the same interface, an
arbitration procedure will occur. This section describes this arbitration.
The arbitration follows a fixed arbitration scheme with highest priority first:
1. DMA WRITE
2. DMA READ
3. CLA WRITE
4. CLA READ
5. CPU WRITE
6. CPU READ
They are covered in detail in the Section 3.12.

8.4.1 CLA Message RAM

Message RAMs consist of four blocks:
• CLA to CPU Message RAM
• CPU to CLA Message RAM
• DMA to CLA Message RAM
• CLA to DMA Message RAM
These blocks are useful for passing data between the CLA and CPU or CLA and DMA. No opcode
fetches, from either the CLA or CPU, are allowed from the message RAMs. A write protection violation will
not be generated if the CLA attempts to write to the CPU to CLA or DMA to CLA message RAM but the
write will be ignored. The arbitration scheme for the message RAMs are the same as those for the shared
memories described in Section 3.12.

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The message RAMs have the following characteristics:

• CLA to CPU Message RAM:
The following accesses are allowed:
– CPU reads
– CLA data reads and writes
– CPU debug reads and writes

The following accesses are ignored:

– CPU writes
• CPU to CLA Message RAM:
The following accesses are allowed:
– CPU reads and writes
– CLA reads
– CPU debug reads and writes

The following accesses are ignored:

– CLA writes

8.5 CLA Configuration and Debug

This section discusses the steps necessary to configure and debug the CLA.

8.5.1 Building a CLA Application

The control law accelerator can be programmed in either CLA assembly code, using the instructions
described in Section 8.7, or a reduced subset of the C language. CLA assembly code resides in the same
project with C28x code. The only restriction is the CLA code must be in its own assembly section. This
can be easily done using the .sect assembly directive. This does not prevent CLA and C28x code from
being linked into the same memory region in the linker command file.
System and CLA initialization are performed by the main CPU. This would typically be done in C or C++
but can also include C28x assembly code. The main CPU will also copy the CLA code to the program
memory and, if needed, initialize the CLA data RAM(s). Once system initialization is complete and the
application begins, the CLA will service its interrupts using the CLA assembly code (or tasks). The main
CPU can perform other tasks concurrently with CLA program execution.
The CLA Type 2 requires Codegen V16.9.1.LTS or later with the compiler switch: --cla_support=cla2.

8.5.2 Typical CLA Initialization Sequence

A typical CLA initialization sequence is performed by the main CPU as described in this section.
1. Copy CLA code into the CLA program RAM
The source for the CLA code can initially reside in the flash or a data stream from a communications
peripheral or anywhere the main CPU can access it. The debugger can also be used to load code
directly to the CLA program RAM during development.
2. Initialize CLA data RAM, if necessary
Populate the CLA data RAM with any required data coefficients or constants.
3. Configure the CLA registers
Configure the CLA registers, but keep interrupts disabled until later (leave MIER = 0):
• Enable the CLA peripheral clock using the assigned PCLKCRn register
The peripheral clock control (PCLKCRn) registers are defined in the System Control chapter.

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• Populate the CLA task interrupt vectors

– MVECT1 to MVECT8
Each vector needs to be initialized with the start address of the task to be executed when the
CLA receives the associated interrupt. This address is the full 16-bit starting address of the task
in the lower 64K section of memory.
– MVECT1 to MVECT7, and MVECTBGRND
When using the background task, its vector (MVECTBGRND) must be loaded with the start
address of the task in lower 64K of memory. Note that Task 8 is ignored when the background
task is enabled
• Select the task interrupt sources
For each task select the interrupt source in the CLA1TASKSRCSELx register. If a task is software
triggered, select no interrupt. Since the background task takes the place of Task 8, it will use the
same peripheral trigger source as task 8.
• Enable IACK to start a task from software, if desired
To enable the IACK instruction to start a task set the MCTL[IACKE] bit. Using the IACK instruction
avoids having to set and clear the EALLOW bit. If the background task is enabled, the IACK bit for
task 8 is ignored; the user must, instead, write to the BGSTART bit of the MCTLBGRND register to
start the background task (TRIGEN should be 0 to avoid a peripheral trigger from causing an
overflow, for example, MSTSBGRND.BGOVF is set to 1).
• Map CLA data RAM to CLA space, if necessary
Map the data RAM to the CLA space by first, assigning ownership of the memory block to the CLA
by writing a 1 to the memory block’s MemCfgRegs.LSxMSEL[MSEL_LSx] bit, and then specifying
the memory block as a CLA data block by writing a 0 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit. When an LSx memory is configured as a CLA data
memory, the CLA read/write accesses are arbitrated along with CPU accesses. The user has the
option of turning on CPU fetch or write protection to the memory by writing to the appropriate bits of
the MemCfgRegs.LSxACCPROTx registers.
• Map CLA program RAM to CLA space
Map the CLA program RAM to CLA space by first assigning ownership of the memory block to the
CLA by writing a 1 to the memory block’s MemCfgRegs.LSxMSEL[MSEL_LSx] bit, and then
specifying the memory block as CLA code memory by writing a 1 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit. When an LSx memory is configured as CLA
program memory, only debug accesses are allowed on cycles in which the CLA is not fetching a
new instruction.
4. Initialize the PIE vector table and registers
When a CLA task completes, the associated interrupt in the PIE will be flagged. The CLA overflow and
underflow flags also have associated interrupts within the PIE.
5. Enable CLA tasks/interrupts
Set appropriate bits in the interrupt enable register (MIER) to allow the CLA to service interrupts. It
should be noted that a CLA task only triggers on a level transition (a falling edge) of the configured
interrupt source. If a peripheral is enabled and an interrupt fires before the CLA is configured, then the
CLA will not see the interrupt edge and will not respond. To avoid this, configure the CLA before the
peripherals or clear any pending peripheral interrupts before setting bits in the MIER register.
6. Initialize other peripherals
Initialize any peripherals (such as ePWM, ADC, and others) that will generate interrupt triggers for
enabled CLA tasks.
The CLA is now ready to service interrupts and the message RAMs can be used to pass data between
the CPU and the CLA. Mapping of the CLA program and data RAMs typically occurs only during the
initialization process. If the RAM mapping needs to be changed after initialization, the CLA interrupts
must be disabled and all tasks must be completed (by checking the MIRUN register) prior to modifying
the RAM ownership.

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8.5.3 Debugging CLA Code

Debugging the CLA code is a simple process that occurs independently of the main CPU. The type 2 CLA
adds a true software breakpoint feature.

8.5.3.1 Software Breakpoint Support (MDEBUGSTOP1)

The MDEBUGSTOP1 instruction is meant to be used as a software breakpoint; the instruction on which
the execution must halt is replaced with this instruction.
The MDEBUGSTOP1 and MDEBUGSTOP instructions differ in how the CLA pipeline is treated. When
halted, the MDEBUGSTOP1 instruction will flush all the instructions that have already been fetched; on a
single-step or run-free command, the CLA will re-fetch the same instruction which it replaced. Table 8-2
illustrates the pipeline behavior.

Table 8-2. Pipeline Behavior of the MDEBUGSTOP1 Instruction

Cycles F1 F2 D1 D2 R1 R2 E W Comments
1 i1
2 i2 i1
3 i3 i2 i1
4 i4 i3 i2 i1
5 MDEBUG i4 i3 i2 i1
STOP1
6 i6 MDEBUG i4 i3 i2 i1
STOP1
7 i7 i6 MDEBUG i4 i3 i2 i1
STOP1
9 i8 Flushed Flushed Flushed i4 i3 i2 i1 CLA
(MNOP) (MNOP) (MNOP) halted
10 i5(MDEBUG Flushed Flushed Flushed Flushed i4 i3 i2 CLA
STOP1) (MNOP) (MNOP) (MNOP) (MNOP) step/run
11 i6 i5(MDEBUG Flushed Flushed Flushed Flushed i4 i3 CLA
STOP1) (MNOP) (MNOP) (MNOP) (MNOP) step/run
12 i7 i6 i5(MDEBUG Flushed Flushed Flushed Flushed i4 CLA
STOP1) (MNOP) (MNOP) (MNOP) (MNOP) step/run
13 i8 i7 i6 i5(MDEBUG Flushed Flushed Flushed Flushed CLA
STOP1) (MNOP) (MNOP) (MNOP) (MNOP) step/run

A software breakpoint is placed at instruction i5. The instruction, i5, is then replaced with
MDEBUGSTOP1. It takes 3 cycles for the MDEBUGSTOP1 to reach the D2 phase at which point the
instructions i6, i7, and i8 that were previously fetched are now flushed from the pipeline. The instruction,
i5, is then re-fetched and execution continues as before.

8.5.3.2 Legacy Breakpoint Support (MDEBUGSTOP)

1. Insert a breakpoint in CLA code
Insert a CLA breakpoint (MDEBUGSTOP instruction) into the code where you want the CLA to halt,
then rebuild and reload the code. Because the CLA does not flush its pipeline when you single-step,
the MDEBUGSTOP instruction must be inserted as part of the code. The debugger cannot insert it as
needed.
If CLA breakpoints are not enabled, then the MDEBUGSTOP will be ignored and is treated as a
MNOP. The MDEBUGSTOP instruction can be placed anywhere in the CLA code as long as it is not
within three instructions of a MBCNDD, MCCNDD, or MRCNDD instruction. When programming in C,
the user can use the __mdebugstop() intrinsic instead; the compiler will ensure that the placement of
the MDEBUSTOP instruction in the generated assembly does not violate any of the pipeline
restrictions.

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2. Enable CLA breakpoints

Enable the CLA breakpoints in the debugger. In Code Composer Studio, this is done by connecting to
the CLA core (or tap) from the debug perspective. Breakpoints are disabled when the core is
disconnected.
3. Start the task
There are three ways to start the task:
1. The peripheral can assert an interrupt,
2. The main CPU can execute an IACK instruction, or
3. The user can manually write to the MIFRC register in the debugger window
When the task starts, the CLA will execute instructions until the MDEBUGSTOP is in the D2 phase of
the pipeline. At this point, the CLA will halt and the pipeline will be frozen. The MPC register will reflect
the address of the MDEBUGSTOP instruction.
4. Single-step the CLA code
Once halted, the user can single-step the CLA code. The behavior of a CLA single-step is different
than the main C28x. When issuing a CLA single-step, the pipeline is clocked only one cycle and then
again frozen. On the 28x CPU, the pipeline is flushed for each single-step.
You can also run to the next MDEBUGSTOP or to the end of the task. If another task is pending, it will
automatically start when you run to the end of the task.

NOTE: A CLA fetch has higher priority than CPU debug reads. For this reason, it is possible for the
CLA to permanently block CPU debug accesses if the CLA is executing in a loop. This might
occur when initially developing CLA code due to a bug that causes an infinite loop. To avoid
locking up the main CPU, the program memory will return all 0x0000 for CPU debug reads
when the CLA is running. When the CLA is halted or idle then normal CPU debug read and
write access to CLA program memory can be performed.
If the CLA gets caught in an infinite loop, you can use a soft or hard reset to exit the
condition. A debugger reset will also exit the condition.

There are special cases that can occur when single-stepping a task such that the program counter,
MPC, reaches the MSTOP instruction at the end of the task.
• MPC halts at or after the MSTOP with a task already pending
If you are single-stepping or halted in "task A" and "task B" comes in before the MPC reaches the
MSTOP, then "task B" will start if you continue to step through the MSTOP instruction. Basically if
"task B" is pending before the MPC reaches MSTOP in "task A" then there is no issue in "task B"
starting and no special action is required.
• MPC halts at or after the MSTOP with no task pending
In this case you have single-stepped or halted in "task A" and the MPC has reached the MSTOP
with no tasks pending. If "task B" comes in at this point, it will be flagged in the MIFR register but it
may or may not start if you continue to single-step through the MSTOP instruction of "task A."
It depends on exactly when the new task comes in. To reliably start "task B" perform a soft reset
and reconfigure the MIER bits. Once this is done, you can start single-stepping "task B."
This case can be handled slightly differently if there is control over when "task B" comes in (for
example using the IACK instruction to start the task). In this case you have single-stepped or halted
in "task A" and the MPC has reached the MSTOP with no tasks pending. Before forcing "task B,"
run free to force the CLA out of the debug state. Once this is done you can force "task B" and
continue debugging.
5. Disable CLA breakpoints, if desired
In Code Composer Studio you can disable the CLA breakpoints by disconnecting the CLA core in the
debug perspective. Make sure to first issue a run or reset; otherwise, the CLA will be halted and no
other tasks will start.

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8.5.4 CLA Illegal Opcode Behavior

If the CLA fetches an opcode that does not correspond to a legal instruction, it will behave as follows:
• The CLA will halt with the illegal opcode in the D2 phase of the pipeline as if it were a breakpoint. This
will occur whether CLA breakpoints are enabled or not.
• The CLA will issue the task-specific interrupt to the PIE.
• The MIRUN bit for the task will remain set.
Further single-stepping is ignored once execution halts due to an illegal op-code. To exit this situation,
issue either a soft or hard reset of the CLA as described in Section 8.5.5.

8.5.5 Resetting the CLA

There may be times when you need to reset the CLA. For example, during code debug the CLA may enter
an infinite loop due to a code bug. The CLA has two types of resets: hard and soft. Both of these resets
can be performed by the debugger or by the main CPU.
• Hard Reset
Writing a 1 to the MCTL[HARDRESET] bit will perform a hard reset of the CLA. The behavior of a hard
reset is the same as a system reset (via XRS or the debugger). In this case all CLA configuration and
execution registers will be set to their default state and CLA execution will halt.
• Soft Reset
Writing a 1 to the MCTL[SOFTRESET] bit performs a soft reset of the CLA. If a task is executing it will
halt and the associated MIRUN bit will be cleared. All bits within the interrupt enable (MIER) register
will also be cleared so that no new tasks start. In addition, the background task's start bit
(MCTLBGRN.BGSTART) and Trigger Enable bit (MCTLBGRND.TRIGEN) are reset. The
MVECTBGRNACTIVE is set to the value of MVECTBGRND, and the status register (MSTSBGRND) is
also reset.

8.6 Pipeline
This section describes the CLA pipeline stages and presents cases where pipeline alignment must be
considered.

8.6.1 Pipeline Overview

The CLA pipeline is very similar to the C28x pipeline with eight stages:
1. Fetch 1 (F1)
During the F1 stage the program read address is placed on the CLA program address bus.
2. Fetch 2 (F2)
During the F2 stage the instruction is read using the CLA program data bus.
3. Decode 1 (D1)
During D1 the instruction is decoded.
4. Decode 2 (D2)
Generate the data read address. Changes to MAR0 and MAR1 due to post-increment using indirect
addressing takes place in the D2 phase. Conditional branch decisions are also made at this stage
based on the MSTF register flags.
5. Read 1 (R1)
Place the data read address on the CLA data-read address bus. If a memory conflict exists, the R1
stage will be stalled.
6. Read 2 (R2)
Read the data value using the CLA data read data bus.
7. Execute (EXE)
Execute the operation. Changes to MAR0 and MAR1 due to loading an immediate value or value from
memory take place in this stage.

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8. Write (W)
Place the write address and write data on the CLA write data bus. If a memory conflict exists, the W
stage will be stalled.

8.6.2 CLA Pipeline Alignment

The majority of the CLA instructions do not require any special pipeline considerations. This section lists
the few operations that do require special consideration.
• Write Followed by Read
In both the C28x and the CLA pipeline the read operation occurs before the write. This means that if a
read operation immediately follows a write, then the read will complete first as shown in Table 8-3. In
most cases this does not cause a problem since the contents of one memory location does not depend
on the state of another. For accesses to peripherals where a write to one location can affect the value
in another location the code must wait for the write to complete before issuing the read as shown in
Table 8-4.
This behavior is different for the 28x CPU. For the 28x CPU any write followed by read to the same
location is protected by what is called write-followed-by-read protection. This protection automatically
stalls the pipeline so that the write will complete before the read. In addition some peripheral frames
are protected such that a 28x CPU write to one location within the frame will always complete before a
read to the frame. The CLA does not have this protection mechanism. Instead the code must wait to
perform the read.

Table 8-3. Write Followed by Read - Read Occurs First

Instruction F1 F2 D1 D2 R1 R2 E W
I1 MMOV16 @Reg1, MR3 I1
I2 MMOV16 MR2, @Reg2 I2 I1
I2 I1
I2 I1
I2 I1
I2 I1
I2 I1
I2 I1

Table 8-4. Write Followed by Read - Write Occurs First

Instruction F1 F2 D1 D2 R1 R2 E W
I1 MMOV16 @Reg1, MR3 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
I5 MMOV16 MR2, @Reg2 I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3
I5 I4
I5

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• Delayed Conditional instructions: MBCNDD, MCCNDD, and MRCNDD

Referring to Example 8-1, the following applies to delayed conditional instructions:
– I1
I1 is the last instruction that can effect the CNDF flags for the branch, call or return instruction. The
CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is made whether to
branch or not when MBCNDD, MCCNDD, or MRCNDD is in the D2 phase.
– I2, I3, and I4
The three instructions preceding MBCNDD can change MSTF flags but will have no effect on
whether the MBCNDD instruction branches or not. This is because the flag modification will occur
after the D2 phase of the branch, call or return instruction. These three instructions must not be a
MSTOP, MDEBUGSTOP, MBCNDD, MCCNDD, or MRCNDD.
– I5, I6, and I7
The three instructions following a branch, call or return are always executed irrespective of whether
the condition is true or not. These instructions must not be MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD or MRCNDD.
For a more detailed description refer to the functional description for MBCNDD, MCCNDD, and
MRCNDD.

Example 8-1. Code Fragment For MBCNDD, MCCNDD, or MRCNDD

<Instruction 1> ; I1 Last instruction that can affect flags for

; the branch, call or return operation

<Instruction 2> ; I2 Cannot be stop, branch, call or return

<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return

<branch/call/ret> ; MBCNDD, MCCNDD or MRCNDD

; I5-I7: Three instructions after are always

; executed whether the branch/call or return is
; taken or not

<Instruction 5> ; I5 Cannot be stop, branch, call or return

<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return

<Instruction 8> ; I8
<Instruction 9> ; I9
....

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• Stop or Halting a Task: MSTOP and MDEBUGSTOP

The MSTOP and MDEBUGSTOP instructions cannot be placed three instructions before or after a
conditional branch, call or return instruction (MBCNDD, MCCNDD, or MRCNDD). Refer to Example 8-
1. To single-step through a branch/call or return, insert the MDEBUGSTOP at least four instructions
back and step from there.
• Loading MAR0 or MAR1
A load of auxiliary register MAR0 or MAR1 will occur in the EXE phase of the pipeline. Any post
increment of MAR0 or MAR1 using indirect addressing will occur in the D2 phase of the pipeline.
Referring to Example 8-2, the following applies when loading the auxiliary registers:
– I1 and I2
The two instructions following the load instruction will use the value in MAR0 or MAR1 before the
update occurs.
– I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-increment
addressing occur in the D2 phase. Thus I3 cannot use the auxiliary register or there will be a
conflict. In the case of a conflict, the update due to address-mode post increment will win and the
auxiliary register will not be updated with #_X.
– I4
Starting with the 4th instruction MAR0 or MAR1 will have the new value.

Example 8-2. Code Fragment for Loading MAR0 or MAR1

; Assume MAR0 is 50 and #_X is 20

MMOVI16 MAR0, #_X ; Load MAR0 with address of X (20)

<Instruction 1> ; I1 Will use the old value of MAR0 (50)
<Instruction 2> ; I2 Will use the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Will use the new value of MAR0 (20)
<Instruction 5> ; I5 Will use the new value of MAR0 (20
....

• Background Task Interrupted Close to a Branch

When the background task is running, if another task request happens (and MSTSBGRND.BGINTM is
not set), then the following sequence of operations happen.
– A check is made to determine if the following instructions are not in the pipeline (D2 – R2).
• MBCNDD
• MCCNDD
• MRCNDD
If any of the above instructions are present in the pipeline, the back ground task continues to execute
until such time when the condition is satisfied. Once it is satisfied, the following actions are performed:
– The MPC value of the D1 phase instruction is saved to the MVECTBGRNDACTIVE register.
– The run status bit of the background task (MSTSBGRND.RUNSTS) is cleared.
– An MSTOP instruction is forced into the D2 phase of the pipeline; it will cause the background task
to terminate.
When the background task terminates, the CLA picks the next highest pending task and begins
execution. It is important to note that while the background task is pending it has the lowest priority and
will, therefore, yield to any other pending task. Once all pending non-background tasks have completed
execution the CLA will restore the program counter (MPC), that is, load the address from the
MVECTBGRNDACTIVE register to the MPC, set the background status to RUN (MSTSBGRND.RUN =
1), and continue execution from that point.

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• MSTOP in the Background Task

If an MSTOP instruction occurs in the D1 phase while the background task is running, the following
sequence of operations happens:
– The RUN bit (MSTSBGRND.RUN) is cleared.
– The address stored in MVECTBGRND is copied over to MVECTBGRNDACTIVE.
– An interrupt, signaling the background task has completed execution, is generated. This interrupt
signal is ANDed with the interrupt from Task 8 and fed to the PIE. It should be noted that if an
illegal instruction occurs inside the background task, the interrupt for task 8 is fired.
– When the background task terminates, the CLA resumes arbitration among the pending tasks.

8.6.2.1 ADC Early Interrupt to CLA Response

The ADC can be configured to generate an early interrupt pulse before the ADC conversion completes. If
this option is used to start a CLA task, the CLA will be able to read the result as soon as the conversion
result is available in the ADC result register. This combination of just-in-time sampling along with the low
interrupt response of the CLA enable faster system response and higher frequency control loops.
Timings for ADC conversions are shown in the timing diagrams of the ADC chapter. If the ADCCLK is a
divided down version of the SYSCLK, the user will have to account for the conversion time in SYSCLK
cycles.
For example, if using the 12-bit ADC with ADCCLK at SYSCLK / 4, it would take 10.5 ADCCLK x 4
SYSCLK = 42 SYSCLK cycles to complete a conversion. If using the ADC in 16-bit mode at the same
ADCCLK, it would take 29.5 ADCCLK x 4 SYSCLK = 118 SYSCLK cycles, and so on.
From a CLA perspective, the pipeline activity is shown in Table 8-5 for an N-cycle (SYSCLK) ADC
conversion. The N-2 instruction will arrive in the R2 phase just in time to read the result register. While the
prior instructions will enter the R2 phase of the pipeline too soon to read the conversion, they can be
efficiently used for pre-processing calculations needed by the task.

Table 8-5. ADC to CLA Early Interrupt Response

ADC Activity CLA Activity F1 F2 D1 D2 R1 R2 E W
Sample
Sample
...
Sample
Conversion(Cycle 1) Interrupt Received
Conversion(Cycle 2) Task Startup
Conversion(Cycle 3) Task Startup
Conversion(Cycle 4) I(Cycle 4) I(Cycle 4)

Conversion(Cycle 5) I(Cycle 5) I(Cycle 5) I(Cycle 4)

Conversion(...) ... ... ... ... ... ... ...

Conversion(Cycle N-6) I(Cycle N-6) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8) I(Cycle N-9) I(Cycle N-10) I(Cycle N-11)
Conversion(Cycle N-5) I(Cycle N-5) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8) I(Cycle N-9) I(Cycle N-10)
Conversion(Cycle N-4) I(Cycle N-4) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8) I(Cycle N-9)
Conversion(Cycle N-3) I(Cycle N-3) I(Cycle N-3) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8)
Read
Conversion(Cycle N-2) Read RESULT I(Cycle N-3) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7)
RESULT
Read
Conversion(Cycle N-1) I(Cycle N-3) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6)
RESULT
Read
Conversion(Cycle N-0) I(Cycle N-3) I(Cycle N-4) I(Cycle N-5)
RESULT
Read
Conversion Complete I(Cycle N-3) I(Cycle N-4)
RESULT
Read
RESULT Latched I(Cycle N-3)
RESULT
Read
RESULT Available
RESULT

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8.6.3 Parallel Instructions

Parallel instructions are single opcodes that perform two operations in parallel. The following types of
parallel instructions are available: math operation in parallel with a move operation, or two math
operations in parallel. Both operations complete in a single cycle and there are no special pipeline
alignment requirements.

Example 8-3. Math Operation with Parallel Load

; MADDF32 || MMOV32 instruction: 32-bit floating-point add with parallel move

; MADDF32 is a 1 cycle operation
; MMOV32 is a 1 cycle operation
MADDF32 MR0, MR1, #2 ; MR0 = MR1 + 2,
|| MMOV32 MR1, @Val ; MR1 gets the contents of Val
; <-- MMOV32 completes here (MR1 is valid)
; <-- DDF32 completes here (MR0 is valid)
MMPYF32 MR0, MR0, MR1 ; Any instruction, can use MR1 and/or MR0

Example 8-4. Multiply with Parallel Add

; MMPYF32 || MADDF32 instruction: 32-bit floating-point multiply with parallel add

; MMPYF32 is a 1 cycle operation
; MADDF32 is a 1 cycle operation
MMPYF32 MR0, MR1, MR3 ; MR0 = MR1 * MR3
|| MADDF32 MR1, MR2, MR0 ; MR1 = MR2 + MR0 (Uses value of MR0 before MMPYF32)
; <-- MMPYF32 and MADDF32 complete here (MR0 and MR1 are valid)
MMPYF32 MR1, MR1, MR0 ; Any instruction, can use MR1 and/or MR0

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8.7 Instruction Set

This section describes the assembly language instructions of the control law accelerator. Also described
are parallel operations, conditional operations, resource constraints, and addressing modes. The
instructions listed here are independent from C28x and C28x+FPU instruction sets.

8.7.1 Instruction Descriptions

This section gives detailed information on the instruction set. Each instruction may present the following
information:
• Operands
• Opcode
• Description
• Exceptions
• Pipeline
• Examples
• See also
The example INSTRUCTION is shown to familiarize you with the way each instruction is described. The
example describes the kind of information you will find in each part of the individual instruction description
and where to obtain more information. CLA instructions follow the same format as the C28x; the source
operand(s) are always on the right and the destination operand(s) are on the left.
The explanations for the syntax of the operands used in the instruction descriptions for the C28x CLA are
given in Table 8-6.

Table 8-6. Operand Nomenclature

Symbol Description
#16FHi 16-bit immediate (hex or float) value that represents the upper 16-bits of an IEEE 32-bit floating-point value.
Lower 16-bits of the mantissa are assumed to be zero.
#16FHiHex 16-bit immediate hex value that represents the upper 16-bits of an IEEE 32-bit floating-point value.
Lower 16-bits of the mantissa are assumed to be zero.
#16FLoHex A 16-bit immediate hex value that represents the lower 16-bits of an IEEE 32-bit floating-point value
#32Fhex 32-bit immediate value that represents an IEEE 32-bit floating-point value
#32F Immediate float value represented in floating-point representation
#0.0 Immediate zero
#SHIFT Immediate value of 1 to 32 used for arithmetic and logical shifts.
addr Opcode field indicating the addressing mode
CNDF Condition to test the flags in the MSTF register
FLAG Selected flags from MSTF register (OR) 8 bit mask indicating which floating-point status flags to change
MAR0 auxiliary register 0
MAR1 auxiliary register 1
MARx Either MAR0 or MAR1
mem16 16-bit memory location accessed using direct, indirect, or offset addressing modes
mem32 32-bit memory location accessed using direct, indirect, or offset addressing modes
MRa MR0 to MR3 registers
MRb MR0 to MR3 registers
MRc MR0 to MR3 registers
MRd MR0 to MR3 registers
MRe MR0 to MR3 registers
MRf MR0 to MR3 registers
MSTF CLA Floating-point Status Register
shift Opcode field indicating the number of bits to shift.
VALUE Flag value of 0 or 1 for selected flag (OR) 8 bit mask indicating the flag value; 0 or 1

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Each instruction has a table that gives a list of the operands and a short description. Instructions always
have their destination operand(s) first followed by the source operand(s).

Table 8-7. INSTRUCTION dest, source1, source2 Short Description

Description
dest1 Description for the 1st operand for the instruction
source1 Description for the 2nd operand for the instruction
source2 Description for the 3rd operand for the instruction
Opcode This section shows the opcode for the instruction
Description Detailed description of the instruction execution is described. Any constraints on the operands imposed by
the processor or the assembler are discussed.
Restrictions Any constraints on the operands or use of the instruction imposed by the processor are discussed.
Pipeline This section describes the instruction in terms of pipeline cycles as described in Section 8.6
Example Examples of instruction execution. If applicable, register and memory values are given before and after
instruction execution. Some examples are code fragments while other examples are full tasks that assume
the CLA is correctly configured and the main CPU has passed it data.
Operands Each instruction has a table that gives a list of the operands and a short description. Instructions always
have their destination operand(s) first followed by the source operand(s).

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8.7.2 Addressing Modes and Encoding

The CLA uses the same address to access data and registers as the main CPU. For example if the main
CPU accesses an ePWM register at address 0x00 6800, then the CLA will access it using address
0x6800. Since all CLA accessible memory and registers are within the low 64k x 16 of memory, only the
low 16-bits of the address are used by the CLA.
To address the CLA data memory, message RAMs and shared peripherals, the CLA supports two
addressing modes:
• Direct addressing mode: Uses the address of the variable or register directly.
• Indirect addressing with 16-bit post increment. This mode uses either XAR0 or XAR1.
The CLA does not use a data page pointer or a stack pointer. The two addressing modes are encoded as
shown Table 8-8.

Table 8-8. Addressing Modes

Addressing Mode 'addr' Opcode Description
Field
Encode (1)
@dir 0000 Direct Addressing Mode
Example 1: MMOV32 MR1, @_VarA
Example 2: MMOV32 MR1, @_EPwm1Regs.CMPA.all
In this case the 'mmmm mmmm mmmm mmmm' opcode field will be populated with the
16-bit address of the variable. This is the low 16-bits of the address that you would use to
access the variable using the main CPU.
For example @_VarA will populate the address of the variable VarA. and
@_EPwm1Regs.CMPA.all will populate the address of the CMPA register.
*MAR0[#imm16]++ 0001 MAR0 Indirect Addressing with 16-bit Immediate Post Increment
*MAR1[#imm16]++ 0010 MAR1 Indirect Addressing with 16-bit Immediate Post Increment
addr = MAR0 (or MAR1) Access memory using the address stored in MAR0 (or MAR1).
MAR0 (or MAR1) += Then post increment MAR0 (or MAR1) by #imm16.
#imm16
Example 1: MMOV32 MR0, *MAR0[2]++
Example 2: MMOV32 MR1, *MAR1[-2]++
For a post increment of 0 the assembler will accept both *MAR0 and *MAR0[0]++.
The 'mmmm mmmm mmmm mmmm' opcode field will be populated with the signed 16-bit
pointer offset. For example if #imm16 is 2, then the opcode field will be 0x0002. Likewise if
#imm16 is -2, then the opcode field will be 0xFFFE.
If addition of the 16-bit immediate causes overflow, then the value will wrap around on a
16-bit boundary.
*MAR0+[#imm16] 0101 MAR0 Offset Addressing with 16-bit Immediate Offset
*MAR1+[#imm16] 0110 MAR1 Offset Addressing with 16-bit Immediate Offset
addr = MAR0 Add the offset #imm16
(or MAR1) + #imm16to address stored in MAR0(MAR1) to access the desired memory
the base location
Example 1: MMOV32 MR0, *MAR0+[2]
Example 1: MMOV32 MR1, *MAR1+[-2]
The ‘mmmm mmmm mmmm mmmm’ opcode field will be populated with the signed 16-bit
pointer offset. For example if #imm16 is 2, then the opcode field will be 0x0002. Likewise if
#imm16 is -2, then the opcode field will be 0xFFFE.
If the addition of the 16-bit immediate causes overflow, the value will wrap around on a 16-
bit boundary.
(1)
Values not shown are reserved.

Encoding for the shift fields in the MASR32, MLSR32 and MLSL32 instructions is shown in Table 8-9.

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Table 8-9. Shift Field Encoding

Shift Value 'shift' Opcode
Field Encode
1 0000
2 0001
3 0010
.... ....
32 1111

Table 8-11 shows the condition field encoding for conditional instructions such as MNEGF, MSWAPF,
MBCNDD, MCCNDD, and MRCNDD.
For instructions that use MRx (where x could be 'a' through 'f') as operands, the trailing alphabet appears
in the opcode as a two-bit field. For example,
MMPYF32 MRa, MRb, MRc ||
MADDF32 MRd, MRe, MRf

whose opcode is,

LSW: 0000 ffee ddcc bbaa
MSW: 0111 1010 0000 0000

The two-bit field specifies one of four working registers according to Table 8-10.

Table 8-10. Operand Encoding

Two-Bit Field Working Register
b’00 MR0
b’01 MR1
b’10 MR2
b’11 MR3

Table 8-11. Condition Field Encoding

(1)
Encode CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal to zero NF == 0
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to zero ZF == 1 OR NF == 1
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
(2)
1111 UNCF Unconditional with flag modification None
(1)
Values not shown are reserved.
(2)
This is the default operation if no CNDF field is specified. This condition will allow the ZF and NF flags to be modified when a
conditional operation is executed. All other conditions will not modify these flags.

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8.7.3 Instructions
The instructions are listed alphabetically, preceded by a summary.
Table 8-12. General Instructions
Title ...................................................................................................................................... Page

MABSF32 MRa, MRb — 32-Bit Floating-Point Absolute Value ................................................................... 952

MADD32 MRa, MRb, MRc — 32-Bit Integer Add ................................................................................... 953
MADDF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Addition ................................................................ 954
MADDF32 MRa, MRb, #16FHi — 32-Bit Floating-Point Addition ................................................................. 955
MADDF32 MRa, MRb, MRc — 32-Bit Floating-Point Addition .................................................................... 957
MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa — 32-Bit Floating-Point Addition with Parallel Move ............... 958
MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Addition with Parallel Move ............... 959
MAND32 MRa, MRb, MRc — Bitwise AND .......................................................................................... 961
MASR32 MRa, #SHIFT — Arithmetic Shift Right ................................................................................... 962
MBCNDD 16BitDest {, CNDF} — Branch Conditional Delayed .................................................................. 963
MCCNDD 16BitDest {, CNDF} — Call Conditional Delayed ...................................................................... 968
MCLRC BGINTM — Clear Background Task Interrupt Mask ..................................................................... 972
MCMP32 MRa, MRb — 32-Bit Integer Compare for Equal, Less Than or Greater Than...................................... 973
MCMPF32 MRa, MRb — 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than ............................ 974
MCMPF32 MRa, #16FHi — 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than ......................... 975
MDEBUGSTOP — Debug Stop Task ................................................................................................ 977
MDEBUGSTOP1 — Software Breakpoint ........................................................................................... 978
MEALLOW — Enable CLA Write Access to EALLOW Protected Registers ................................................... 979
MEDIS — Disable CLA Write Access to EALLOW Protected Registers ....................................................... 980
MEINVF32 MRa, MRb — 32-Bit Floating-Point Reciprocal Approximation ...................................................... 981
MEISQRTF32 MRa, MRb — 32-Bit Floating-Point Square-Root Reciprocal Approximation .................................. 982
MF32TOI16 MRa, MRb — Convert 32-Bit Floating-Point Value to 16-Bit Integer .............................................. 983
MF32TOI16R MRa, MRb — Convert 32-Bit Floating-Point Value to 16-Bit Integer and Round .............................. 984
MF32TOI32 MRa, MRb — Convert 32-Bit Floating-Point Value to 32-Bit Integer .............................................. 985
MF32TOUI16 MRa, MRb — Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer ............................... 986
MF32TOUI16R MRa, MRb — Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer and Round ................ 987
MF32TOUI32 MRa, MRb — Convert 32-Bit Floating-Point Value to 32-Bit Unsigned Integer ............................... 988
MFRACF32 MRa, MRb — Fractional Portion of a 32-Bit Floating-Point Value ................................................. 989
MI16TOF32 MRa, MRb — Convert 16-Bit Integer to 32-Bit Floating-Point Value ............................................. 990
MI16TOF32 MRa, mem16 — Convert 16-Bit Integer to 32-Bit Floating-Point Value .......................................... 991
MI32TOF32 MRa, mem32 — Convert 32-Bit Integer to 32-Bit Floating-Point Value .......................................... 992
MI32TOF32 MRa, MRb — Convert 32-Bit Integer to 32-Bit Floating-Point Value ............................................. 993
MLSL32 MRa, #SHIFT — Logical Shift Left ......................................................................................... 994
MLSR32 MRa, #SHIFT — Logical Shift Right ....................................................................................... 995
MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Multiply and Accumulate
with Parallel Move ............................................................................................................ 996
MMAXF32 MRa, MRb — 32-Bit Floating-Point Maximum ......................................................................... 999
MMAXF32 MRa, #16FHi — 32-Bit Floating-Point Maximum ..................................................................... 1001
MMINF32 MRa, MRb — 32-Bit Floating-Point Minimum ......................................................................... 1002
MMINF32 MRa, #16FHi — 32-Bit Floating-Point Minimum ...................................................................... 1004
MMOV16 MARx, MRa, #16I — Load the Auxiliary Register with MRa + 16-bit Immediate Value .......................... 1005
MMOV16 MARx, mem16 — Load MAR1 with 16-bit Value...................................................................... 1008
MMOV16 mem16, MARx — Move 16-Bit Auxiliary Register Contents to Memory ........................................... 1010
MMOV16 mem16, MRa — Move 16-Bit Floating-Point Register Contents to Memory ....................................... 1011
MMOV32 mem32, MRa — Move 32-Bit Floating-Point Register Contents to Memory ...................................... 1013
MMOV32 mem32, MSTF — Move 32-Bit MSTF Register to Memory .......................................................... 1014

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Table 8-12. General Instructions (continued)

MMOV32 MRa, mem32 {, CNDF} — Conditional 32-Bit Move .................................................................. 1015
MMOV32 MRa, MRb {, CNDF} — Conditional 32-Bit Move ..................................................................... 1017
MMOV32 MSTF, mem32 — Move 32-Bit Value from Memory to the MSTF Register ....................................... 1019
MMOVD32 MRa, mem32 — Move 32-Bit Value from Memory with Data Copy............................................... 1020
MMOVF32 MRa, #32F — Load the 32-Bits of a 32-Bit Floating-Point Register ............................................... 1021
MMOVI16 MARx, #16I — Load the Auxiliary Register with the 16-Bit Immediate Value .................................... 1022
MMOVI32 MRa, #32FHex — Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate ................... 1023
MMOVIZ MRa, #16FHi — Load the Upper 16-Bits of a 32-Bit Floating-Point Register ..................................... 1024
MMOVZ16 MRa, mem16 — Load MRx With 16-bit Value ....................................................................... 1025
MMOVXI MRa, #16FLoHex — Move Immediate to the Low 16-Bits of a Floating-Point Register .......................... 1026
MMPYF32 MRa, MRb, MRc — 32-Bit Floating-Point Multiply ................................................................... 1027
MMPYF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Multiply ............................................................... 1028
MMPYF32 MRa, MRb, #16FHi — 32-Bit Floating-Point Multiply ............................................................... 1030
MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf — 32-Bit Floating-Point Multiply with Parallel Add ........... 1032
MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Multiply with Parallel Move .............. 1034
MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa — 32-Bit Floating-Point Multiply with Parallel Move .............. 1036
MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf — 32-Bit Floating-Point Multiply with Parallel Subtract ..... 1037
MNEGF32 MRa, MRb{, CNDF} — Conditional Negation ........................................................................ 1038
MNOP — No Operation ............................................................................................................. 1040
MOR32 MRa, MRb, MRc — Bitwise OR............................................................................................ 1041
MRCNDD {CNDF} — Return Conditional Delayed ................................................................................ 1042
MSETC BGINTM — Set Background Task Interrupt Mask ...................................................................... 1046
MSETFLG FLAG, VALUE — Set or Clear Selected Floating-Point Status Flags ............................................ 1047
MSTOP — Stop Task ................................................................................................................. 1048
MSUB32 MRa, MRb, MRc — 32-Bit Integer Subtraction......................................................................... 1050
MSUBF32 MRa, MRb, MRc — 32-Bit Floating-Point Subtraction .............................................................. 1051
MSUBF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Subtraction............................................................ 1052
MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Subtraction with Parallel Move ......... 1053
MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa — 32-Bit Floating-Point Subtraction with Parallel Move ......... 1054
MSWAPF MRa, MRb {, CNDF} — Conditional Swap ............................................................................ 1055
MTESTTF CNDF — Test MSTF Register Flag Condition ........................................................................ 1057
MUI16TOF32 MRa, mem16 — Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value ........................... 1059
MUI16TOF32 MRa, MRb — Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value .............................. 1060
MUI32TOF32 MRa, mem32 — Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value ........................... 1061
MUI32TOF32 MRa, MRb — Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value .............................. 1062
MXOR32 MRa, MRb, MRc — Bitwise Exclusive Or............................................................................... 1063

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MABSF32 MRa, MRb 32-Bit Floating-Point Absolute Value

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1110 0010 0000

Description The absolute value of MRb is loaded into MRa. Only the sign bit of the operand is
modified by the MABSF32 instruction.
if (MRb < 0) {MRa = -MRb};
else {MRa = MRb};

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

NF = 0;
ZF = 0;
if ( MRa(30:23) == 0) ZF = 1;

Pipeline This is a single-cycle instruction.

Example MMOVIZ MR0, #-2.0 ; MR0 = -2.0 (0xC0000000)
MABSF32 MR0, MR0 ; MR0 = 2.0 (0x40000000), ZF = NF = 0

MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)

MABSF32 MR0, MR0 ; MR0 = 5.0 (0x40A00000), ZF = NF = 0

MMOVIZ MR0, #0.0 ; MR0 = 0.0

MABSF32 MR0, MR0 ; MR0 = 0.0 ZF = 1, NF = 0

See also MNEGF32 MRa, MRb {, CNDF}

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MADD32 MRa, MRb, MRc 32-Bit Integer Add

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point destination register (MR0 to MR3)
MRc CLA floating-point destination register (MR0 to MR3)

Opcode LSW: 0000 0000 000cc bbaa

MSW: 0111 1110 1100 0000

Description 32-bit integer addition of MRb and MRc.

MRa(31:0) = MRb(31:0) + MRc(31:0);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; };

Pipeline This is a single-cycle instruction.

Example ; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
; Calculate Y2 = A + B + C
;
_Cla1Task1:
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MADD32 MR3, MR0, MR1 ; A + B
MADD32 MR3, MR2, MR3 ; A + B + C = -4 (0xFFFFFFFC)
MMOV32 @_y2, MR3 ; Store y2
MSTOP ; end of task

See also MAND32 MRa, MRb, MRc

MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MADDF32 MRa, #16FHi, MRb 32-Bit Floating-Point Addition

Operands
MRa CLA floating-point destination register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-
point value. The low 16-bits of the mantissa are assumed to be all 0.
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: IIII IIII IIII IIII

MSW: 0111 0111 1100 bbaa

Description Add MRb to the floating-point value represented by the immediate operand. Store the
result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler will accept either a hex or float as the immediate value.
That is, the value -1.5 can be represented as #-1.5 or #0xBFC0.
MRa = MRb + #16FHi:0;

This instruction can also be written as MADDF32 MRa, MRb, #16FHi.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.

Pipeline This is a single-cycle instruction.

Example ; Add to MR1 the value 2.0 in 32-bit floating-point format
; Store the result in MR0
MADDF32 MR0, #2.0, MR1 ; MR0 = 2.0 + MR1

; Add to MR3 the value -2.5 in 32-bit floating-point format

; Store the result in MR2
MADDF32 MR2, #-2.5, MR3 ; MR2 = -2.5 + MR3

; Add to MR3 the value 0x3FC00000 (1.5)

; Store the result in MR3
MADDF32 MR3, #0x3FC0, MR3 ; MR3 = 1.5 + MR3

See also MADDF32 MRa, MRb, #16FHi

MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MADDF32 MRa, MRb, #16FHi 32-Bit Floating-Point Addition

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-
point value. The low 16-bits of the mantissa are assumed to be all 0.

Opcode LSW: IIII IIII IIII IIII

MSW: 0111 0111 1100 bbaa

Description Add MRb to the floating-point value represented by the immediate operand. Store the
result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler will accept either a hex or float as the immediate value.
That is, the value -1.5 can be represented as #-1.5 or #0xBFC0.
MRa = MRb + #16FHi:0;

This instruction can also be written as MADDF32 MRa, #16FHi, MRb.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.

Pipeline This is a single-cycle instruction.

Example 1 ; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store it in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrement the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

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Example 2 ; Show the basic operation of MADDF32

;
; Add to MR1 the value 2.0 in 32-bit floating-point format
; Store the result in MR0
MADDF32 MR0, MR1, #2.0 ; MR0 = MR1 + 2.0

; Add to MR3 the value -2.5 in 32-bit floating-point format

; Store the result in MR2
MADDF32 MR2, MR3, #-2.5 ; MR2 = MR3 + (-2.5)

; Add to MR0 the value 0x3FC00000 (1.5)

; Store the result in MR0
MADDF32 MR0, MR0, #0x3FC0 ; MR0 = MR0 + 1.5

See also MADDF32 MRa, #16FHi, MRb

MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MADDF32 MRa, MRb, MRc 32-Bit Floating-Point Addition

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode LSW: 000 0000 00cc bbaa

MSW: 0111 1100 0010 0000

Description Add the contents of MRc to the contents of MRb and load the result into MRa.
MRa = MRb + MRc;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.

Pipeline This is a single-cycle instruction.

Example ; Given M1, X1 and B1 are 32-bit floating point numbers
; Calculate Y1 = M1*X1+B1
;
_Cla1Task1:
MMOV32 MR0,@M1 ; Load MR0 with M1
MMOV32 MR1,@X1 ; Load MR1 with X1
MMPYF32 MR1,MR1,MR0 ; Multiply M1*X1
|| MMOV32 MR0,@B1 ; and in parallel load MR0 with B1
MADDF32 MR1,MR1,MR0 ; Add M*X1 to B1 and store in MR1
MMOV32 @Y1,MR1 ; Store the result
MSTOP ; end of task

See also MADDF32 MRa, #16FHi, MRb

MADDF32 MRa, MRb, #16FHi
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa 32-Bit Floating-Point Addition with Parallel Move

Operands
MRd CLA floating-point destination register for the MADDF32 (MR0 to MR3)
MRe CLA floating-point source register for the MADDF32 (MR0 to MR3)
MRf CLA floating-point source register for the MADDF32 (MR0 to MR3)
mem32 32-bit memory location accessed using one of the available addressing modes. This
will be the destination of the MMOV32.
MRa CLA floating-point source register for the MMOV32 (MR0 to MR3)

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0101 ffee ddaa addr

Description Perform an MADDF32 and a MMOV32 in parallel. Add MRf to the contents of MRe and
store the result in MRd. In parallel move the contents of MRa to the 32-bit location
mem32.
MRd = MRe + MRf;
[mem32] = MRa;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.

Pipeline Both MADDF32 and MMOV32 complete in a single cycle.

Example ; Given A, B and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A * B) + C
;
_Cla1Task2:
MMOV32 MR0, @_A ; Load MR0 with A
MMOV32 MR1, @_B ; Load MR1 with B
MMPYF32 MR1, MR1, MR0 ; Multiply A*B
|| MMOV32 MR0, @_C ; and in parallel load MR0 with C
MADDF32 MR1, MR1, MR0 ; Add (A*B) to C
|| MMOV32 @_Y2, MR1 ; and in parallel store A*B
MMOV32 @_Y3, MR1 ; Store the A*B + C
MSTOP ; end of task

See also MADDF32 MRa, #16FHi, MRb

MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32

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MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 32-Bit Floating-Point Addition with Parallel Move

Operands
MRd CLA floating-point destination register for the MADDF32 (MR0 to MR3).
MRd cannot be the same register as MRa.
MRe CLA floating-point source register for the MADDF32 (MR0 to MR3)
MRf CLA floating-point source register for the MADDF32 (MR0 to MR3)
MRa CLA floating-point destination register for the MMOV32 (MR0 to MR3).
MRa cannot be the same register as MRd.
mem32 32-bit memory location accessed using one of the available addressing modes. This is
the source for the MMOV32.

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0001 ffee ddaa addr

Description Perform an MADDF32 and a MMOV32 operation in parallel. Add MRf to the contents of
MRe and store the result in MRd. In parallel move the contents of the 32-bit location
mem32 to MRa.
MRd = MRe + MRf;
MRa = [mem32];

Restrictions The destination register for the MADDF32 and the MMOV32 must be unique. That is,
MRa and MRd cannot be the same register.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
The MMOV32 Instruction will set the NF and ZF flags as follows:
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; };

Pipeline The MADDF32 and the MMOV32 both complete in a single cycle.
Example 1 ; Given A, B and C are 32-bit floating-point numbers
; Calculate Y1 = A + 4B
; Y2 = A + C
;
_Cla1Task1:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR1, MR1, #4.0 ; Multiply 4 * B
|| MMOV32 MR2, @C and in parallel load C
MADDF32 MR3, MR0, MR1 ; Add A + 4B
MADDF32 MR3, MR0, MR2 ; Add A + C
|| MMOV32 @Y1, MR3 ; and in parallel store A+4B
MMOV32 @Y2, MR3 ; store A + C MSTOP
; end of task

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Example 2 ; Given A, B and C are 32-bit floating-point numbers

; Calculate Y3 = (A + B)
; Y4 = (A + B) * C
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MADDF32 MR1, MR1, MR0 ; Add A+B
|| MMOV32 MR0, @C ; and in parallel load MR0 with C
MMPYF32 MR1, MR1, MR0 ; Multiply (A+B) by C
|| MMOV32 @Y3, MR1 ; and in parallel store A+B
MMOV32 @Y4, MR1 ; Store the (A+B) * C
MSTOP ; end of task

See also MADDF32 MRa, #16FHi, MRb

MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MAND32 MRa, MRb, MRc Bitwise AND

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 00cc bbaa

MSW: 0111 1100 0110 0000

Description Bitwise AND of MRb with MRc.

MRa(31:0) = MRb(31:0) AND MRc(31:0);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example MMOVIZ MR0, #0x5555 ; MR0 = 0x5555AAAA
MMOVXI MR0, #0xAAAA

MMOVIZ MR1, #0x5432 ; MR1 = 0x5432FEDC

MMOVXI MR1, #0xFEDC

; 0101 AND 0101 = 0101 (5)

; 0101 AND 0100 = 0100 (4)
; 0101 AND 0011 = 0001 (1)
; 0101 AND 0010 = 0000 (0)
; 1010 AND 1111 = 1010 (A)
; 1010 AND 1110 = 1010 (A)
; 1010 AND 1101 = 1000 (8)
; 1010 AND 1100 = 1000 (8)

MAND32 MR2, MR1, MR0 ; MR3 = 0x5410AA88

See also MADD32 MRa, MRb, MRc

MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MASR32 MRa, #SHIFT Arithmetic Shift Right

Operands
MRa CLA floating-point source/destination register (MR0 to MR3)
#SHIFT Number of bits to shift (1 to 32)

Opcode LSW: 0000 0000 0shi ftaa

MSW: 0111 1011 0100 0000

Description Arithmetic shift right of MRa by the number of bits indicated. The number of bits can be 1
to 32.
MARa(31:0) = Arithmetic Shift(MARa(31:0) by #SHIFT bits);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example ; Given m2 = (int32)32
; x2 = (int32)64
; b2 = (int32)-128
;
; Calculate
; m2 = m2/2
; x2 = x2/4
; b2 = b2/8
;
_Cla1Task2:
MMOV32 MR0, @_m2 ; MR0 = 32 (0x00000020)
MMOV32 MR1, @_x2 ; MR1 = 64 (0x00000040)
MMOV32 MR2, @_b2 ; MR2 = -128 (0xFFFFFF80)
MASR32 MR0, #1 ; MR0 = 16 (0x00000010)
MASR32 MR1, #2 ; MR1 = 16 (0x00000010)
MASR32 MR2, #3 ; MR2 = -16 (0xFFFFFFF0)
MMOV32 @_m2, MR0 ; store results
MMOV32 @_x2, MR1
MMOV32 @_b2, MR2
MSTOP ; end of task

See also MADD32 MRa, MRb, MRc

MAND32 MRa, MRb, MRc
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MBCNDD 16BitDest {, CNDF} Branch Conditional Delayed

Operands
16BitDest 16-bit destination if condition is true
CNDF Optional condition tested

Opcode LSW: dest dest dest dest

MSW: 0111 1001 1000 cndf

Description If the specified condition is true, then branch by adding the signed 16BitDest value to the
MPC value. Otherwise, continue without branching. If the address overflows, it wraps
around. Therefore a value of "0xFFFE" will put the MPC back to the MBCNDD
instruction.
Please refer to the pipeline section for important information regarding this instruction.
if (CNDF == TRUE) MPC += 16BitDest;

CNDF is one of the following conditions:

(1)
Encode CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal to zero NF == 0
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to zero ZF == 1 OR NF == 1
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
(2)
1111 UNCF Unconditional with flag None
modification
(1)
Values not shown are reserved.
(2)
This is the default operation if no CNDF field is specified. This condition will allow the ZF and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

Restrictions The MBCNDD instruction is not allowed three instructions before or after a MBCNDD,
MCCNDD or MRCNDD instruction. Refer to the pipeline section for more information.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline The MBCNDD instruction by itself is a single-cycle instruction. As shown in Table 8-13
for each branch 6 instruction slots are executed; three before the branch instruction (I2-
I4) and three after the branch instruction (I5-I7). The total number of cycles for a branch
taken or not taken depends on the usage of these slots. That is, the number of cycles
depends on how many slots are filled with a MNOP as well as which slots are filled. The
effective number of cycles for a branch can, therefore, range from 1 to 7 cycles. The
number of cycles for a branch taken may not be the same as for a branch not taken.

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Referring to Table 8-13 and Table 8-14, the instructions before and after MBCNDD have
the following properties:
• I1
– I1 is the last instruction that can effect the CNDF flags for the MBCNDD
instruction. The CNDF flags are tested in the D2 phase of the pipeline. That is, a
decision is made whether to branch or not when MBCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for I1.
• I2, I3 and I4
– The three instructions proceeding MBCNDD can change MSTF flags but will have
no effect on whether the MBCNDD instruction branches or not. This is because
the flag modification will occur after the D2 phase of the MBCNDD instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP,
MBCNDD, MCCNDD or MRCNDD.
• I5, I6 and I7
– The three instructions following MBCNDD are always executed irrespective of
whether the branch is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP,
MBCNDD, MCCNDD or MRCNDD.
<Instruction 1> ; I1 Last instruction that can affect flags for
; the MBCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
MBCNDD _Skip, NEQ ; Branch to Skip if not eqal to zero
; Three instructions after MBCNDD are always
; executed whether the branch is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8
<Instruction 9> ; I9
....
_Skip:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
....
....
MSTOP
....

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Table 8-13. Pipeline Activity For MBCNDD, Branch Not Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MBCNDD MBCNDD I4 I3 I2 I1
I5 I5 MBCNDD I4 I3 I2 I1
I6 I6 I5 MBCNDD I4 I3 I2 I1
I7 I7 I6 I5 MBCNDD I4 I3 I2
I8 I8 I7 I6 I5 - I4 I3
I9 I9 I8 I7 I6 I5 - I4
I10 I10 I9 I8 I7 I6 I5 -
I10 I9 I8 I7 I6 I5
I10 I9 I8 I7 I6
I10 I9 I8 I7
I10 I9 I8
I10 I9
I10
Table 8-14. Pipeline Activity For MBCNDD, Branch Taken
Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MBCNDD MBCNDD I4 I3 I2 I1
I5 I5 MBCNDD I4 I3 I2 I1
I6 I6 I5 MBCNDD I4 I3 I2 I1
I7 I7 I6 I5 MBCNDD I4 I3 I2
d1 d1 I7 I6 I5 - I4 I3
d2 d2 d1 I7 I6 I5 - I4
d3 d3 d2 d1 I7 I6 I5 -
d3 d2 d1 I7 I6 I5
d3 d2 d1 I7 I6
d3 d2 d1 I7
d3 d2 d1
d3 d2
d3

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Example 1 ; if (State == 0.1)

; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task1:
MMOV32 MR0, @State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MNOP
MNOP
MNOP
MBCNDD Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MNOP ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MMOV32 MR1, @RampState ; Execute if (A) branch not taken
MMOVXI MR2, #RAMPMASK ; Execute if (A) branch not taken
MOR32 MR1, MR2 ; Execute if (A) branch not taken
MMOV32 @RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken
Skip1:
MCMPF32 MR0,#0.01 ; Affects flags for 2nd MBCNDD (B)
MNOP
MNOP
MNOP
MBCNDD Skip2,NEQ ; (B) If State != 0.01, go to Skip2
MNOP ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MMOV32 MR1, @CoastState ; Execute if (B) branch not taken
MMOVXI MR2, #COASTMASK ; Execute if (B) branch not taken
MOR32 MR1, MR2 ; Execute if (B) branch not taken
MMOV32 @CoastState, MR1 ; Execute if (B) branch not taken
MSTOP
Skip2:
MMOV32 MR3, @SteadyState ; Executed if (B) branch taken
MMOVXI MR2, #STEADYMASK ; Executed if (B) branch taken
MOR32 MR3, MR2 ; Executed if (B) branch taken
MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

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Example 2 ; This example is the same as Example 1, except

; the code is optimized to take advantage of delay slots
;
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task2:
MMOV32 MR0, @State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MCMPF32 MR0, #0.01 ; Check used by 2nd MBCNDD (B)
MTESTTF EQ ; Store EQ flag in TF for 2nd MBCNDD (B)
MNOP
MBCNDD Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MMOV32 MR1, @RampState ; Always executed
MMOVXI MR2, #RAMPMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken

Skip1:
MMOV32 MR3, @SteadyState
MMOVXI MR2, #STEADYMASK
MOR32 MR3, MR2
MBCNDD Skip2, NTF ; (B) if State != .01, go to Skip2
MMOV32 MR1, @CoastState ; Always executed
MMOVXI MR2, #COASTMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @CoastState, MR1 ; Execute if (B) branch not taken
MSTOP ; end of task if (B) branch not taken

Skip2:
MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

See also MCCNDD 16BitDest, CNDF

MRCNDD CNDF

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MCCNDD 16BitDest {, CNDF} Call Conditional Delayed

Operands
16BitDest 16-bit destination if condition is true
CNDF Optional condition to be tested

Opcode LSW: dest dest dest dest

MSW: 0111 1001 1001 cndf

Description If the specified condition is true, then store the return address in the RPC field of MSTF
and make the call by adding the signed 16BitDest value to the MPC value. Otherwise,
continue code execution without making the call. If the address overflows, it wraps
around. Therefore a value of "0xFFFE" will put the MPC back to the MCCNDD
instruction.
Please refer to the pipeline section for important information regarding this instruction.
if (CNDF == TRUE)
{
RPC = return address;
MPC += 16BitDest;
};

CNDF is one of the following conditions:

(3)
Encode CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal to zero NF == 0
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to zero ZF == 1 OR NF == 1
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
(4)
1111 UNCF Unconditional with flag None
modification
(3)
Values not shown are reserved.
(4)
This is the default operation if no CNDF field is specified. This condition will allow the ZF and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

Restrictions The MCCNDD instruction is not allowed three instructions before or after a MBCNDD,
MCCNDD, or MRCNDD instruction. Refer to the Pipeline section for more details.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

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Pipeline The MCCNDD instruction by itself is a single-cycle instruction. As shown in Table 8-15,
for each call 6 instruction slots are executed; three before the call instruction (I2-I4) and
three after the call instruction (I5-I7). The total number of cycles for a call taken or not
taken depends on the usage of these slots. That is, the number of cycles depends on
how many slots are filled with a MNOP as well as which slots are filled. The effective
number of cycles for a call can, therefore, range from 1 to 7 cycles. The number of
cycles for a call taken may not be the same as for a call not taken.
Referring to the following code fragment and the pipeline diagrams in Table 8-15 and
Table 8-16, the instructions before and after MCCNDD have the following properties:
• I1
– I1 is the last instruction that can effect the CNDF flags for the MCCNDD
instruction. The CNDF flags are tested in the D2 phase of the pipeline. That is, a
decision is made whether to branch or not when MCCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for I1.
• I2, I3 and I4
– The three instructions proceeding MCCNDD can change MSTF flags but will have
no effect on whether the MCCNDD instruction makes the call or not. This is
because the flag modification will occur after the D2 phase of the MCCNDD
instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP,
MBCNDD, MCCNDD or MRCNDD.
• I5, I6 and I7
– The three instructions following MBCNDD are always executed irrespective of
whether the branch is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP,
MBCNDD, MCCNDD or MRCNDD.

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<Instruction 1> ; I1 Last instruction that can affect flags for

; the MCCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return

MCCNDD _func, NEQ ; Call to func if not eqal to zero

; Three instructions after MCCNDD are always

; executed whether the call is taken or not

<Instruction 5> ; I5 Cannot be stop, branch, call or return

<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8 The address of this instruction is saved
; in the RPC field of the MSTF register.
; Upon return this value is loaded into MPC
; and fetching continues from this point.
<Instruction 9> ; I9
....
_func:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
<Destination 4> ; d4 Last instruction that can affect flags for
; the MRCNDD operation

<Destination 5> ; d5 Cannot be stop, branch, call or return

<Destination 6> ; d6 Cannot be stop, branch, call or return
<Destination 7> ; d7 Cannot be stop, branch, call or return

MRCNDD UNC ; Return to <Instruction 8>, unconditional

; Three instructions after MRCNDD are always

; executed whether the return is taken or not

<Destination 8> ; d8 Cannot be stop, branch, call or return

<Destination 9> ; d9 Cannot be stop, branch, call or return
<Destination 10> ; d10 Cannot be stop, branch, call or return
<Destination 11> ; d11
....
MSTOP

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Table 8-15. Pipeline Activity For MCCNDD, Call Not Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MCCNDD MCCNDD I4 I3 I2 I1
I5 I5 MCCNDD I4 I3 I2 I1
I6 I6 I5 MCCNDD I4 I3 I2 I1
I7 I7 I6 I5 MCCNDD I4 I3 I2
I8 I8 I7 I6 I5 - I4 I3
I9 I9 I8 I7 I6 I5 - I4
I10 I10 I9 I8 I7 I6 I5 -
etc .... I10 I9 I8 I7 I6 I5
.... I10 I9 I8 I7 I6
.... I10 I9 I8 I7
.... I10 I9 I8
I10 I9
I10

Table 8-16. Pipeline Activity For MCCNDD, Call Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MCCNDD MCCNDD I4 I3 I2 I1
I5 I5 MCCNDD I4 I3 I2 I1
I6 I6 I5 MCCNDD I4 I3 I2 I1
(1)
I7 I7 I6 I5 MCCNDD I4 I3 I2
d1 d1 I7 I6 I5 - I4 I3
d2 d2 d1 I7 I6 I5 - I4
d3 d3 d2 d1 I7 I6 I5 -
etc .... d3 d2 d1 I7 I6 I5
.... d3 d2 d1 I7 I6
.... d3 d2 d1 I7
.... d3 d2 d1
d3 d2
d3
(1)
The RPC value in the MSTF register will point to the instruction following I7 (instruction I8).

Example ;

See also MBCNDD #16BitDest, CNDF

MMOV32 mem32, MSTF
MMOV32 MSTF, mem32
MRCNDD CNDF

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MCLRC BGINTM Clear Background Task Interrupt Mask

Operands
None This instruction does not have any operands

Opcode LSW: 0000 0000 0000 0000

MSW: 0111 1111 0111 0000

Description This instruction will clear the background task interrupt mask (BGINTM) bit in the
MSTSBGRND register, allowing any code thereafter to be interrupted by a higher priority
task. This instruction clears the BGINTM bit at the end of its D2 phase.
Note: This instruction does not require the MEALLOW bit to be asserted before or
deasserted after clearing BGINTM.

Flags This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example MCLRC BGINTM ; Allow the background task to be
; interrupted by clearing the
; MSTSBGRND.BGINTM bit

See also MSETC BGINTM

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MCMP32 MRa, MRb 32-Bit Integer Compare for Equal, Less Than or Greater Than

Operands
MRa CLA floating-point source register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1111 0010 0000

Description Set ZF and NF flags on the result of MRa - MRb where MRa and MRb are 32-bit
integers. For a floating point compare refer to MCMPF32.

NOTE: A known hardware issue exists in the MCMP32 instruction. Signed

integer comparisons using MCMP32 by itself will set the status bits in a
way that is not useful for comparison when the difference between the
two operands is too large, such as when the inputs have opposite sign
and are near the extreme 32-bit signed values. This affects both signed
and unsigned integer comparisons.
The compiler (version 18.1.5.LTS or higher) has implemented a
workaround for this issue. The compiler checks the upper bits of the
operands by performing a floating point comparison before proceeding to
do the integer comparison or subtraction.
The compiler flag --cla_signed_compare_workaround enables this
workaround.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

If(MRa == MRb) {ZF=1; NF=0;}

If(MRa > MRb) {ZF=0; NF=0;}
If(MRa < MRb) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example ; Behavior of ZF and NF flags for different comparisons
;
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MCMP32 MR2, MR2 ; NF = 0, ZF = 1
MCMP32 MR0, MR1 ; NF = 1, ZF = 0
MCMP32 MR1, MR0 ; NF = 0, ZF = 0

See also MADD32 MRa, MRb, MRc

MSUB32 MRa, MRb, MRc

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MCMPF32 MRa, MRb 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than

Operands
MRa CLA floating-point source register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1101 0000 0000

Description Set ZF and NF flags on the result of MRa - MRb. The MCMPF32 instruction is performed
as a logical compare operation. This is possible because of the IEEE format offsetting
the exponent. Basically the bigger the binary number, the bigger the floating-point value.
Special cases for inputs:
• Negative zero will be treated as positive zero.
• A denormalized value will be treated as positive zero.
• Not-a-Number (NaN) will be treated as infinity.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

If(MRa == MRb) {ZF=1; NF=0;}

If(MRa > MRb) {ZF=0; NF=0;}
If(MRa < MRb) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example ; Behavior of ZF and NF flags for different comparisons

MMOVIZ MR1, #-2.0 ; MR1 = -2.0 (0xC0000000)

MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MCMPF32 MR1, MR0 ; ZF = 0, NF = 1
MCMPF32 MR0, MR1 ; ZF = 0, NF = 0
MCMPF32 MR0, MR0 ; ZF = 1, NF = 0

See also MCMPF32 MRa, #16FHi

MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, #16FHi
MMINF32 MRa, MRb

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MCMPF32 MRa, #16FHi 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than

Operands
MRa CLA floating-point source register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-
point value. The low 16-bits of the mantissa are assumed to be all 0.

Opcode LSW: IIII IIII IIII IIII

MSW: 0111 1000 1100 00aa

Description Compare the value in MRa with the floating-point value represented by the immediate
operand. Set the ZF and NF flags on (MRa - #16FHi:0).
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler will accept either a hex or float as the immediate
value. That is, -1.5 can be represented as #-1.5 or #0xBFC0.
The MCMPF32 instruction is performed as a logical compare operation. This is possible
because of the IEEE floating-point format offsets the exponent. Basically the bigger the
binary number, the bigger the floating-point value.
Special cases for inputs:
• Negative zero will be treated as positive zero.
• Denormalized value will be treated as positive zero.
• Not-a-Number (NaN) will be treated as infinity.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

If(MRa == #16FHi:0) {ZF=1, NF=0;}

If(MRa > #16FHi:0) {ZF=0, NF=0;}
If(MRa < #16FHi:0) {ZF=0, NF=1;}

Pipeline This is a single-cycle instruction

Example 1 ; Behavior of ZF and NF flags for different comparisons

MMOVIZ MR1, #-2.0 ; MR1 = -2.0 (0xC0000000)

MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MCMPF32 MR1, #-2.2 ; ZF = 0, NF = 0
MCMPF32 MR0, #6.5 ; ZF = 0, NF = 1
MCMPF32 MR0, #5.0 ; ZF = 1, NF = 0

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Example 2 ; X is an array of 32-bit floating-point values

; and has len elements. Find the maximum value in
; the array and store it in Result
;
; Note: MCMPF32 and MSWAPF can be replaced with MMAXF32
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0

LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MCMPF32 MR2, MR1 ; Compare MR2 with MR1
MSWAPF MR1, MR2, GT ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

See also MCMPF32 MRa, MRb

MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, #16FHi
MMINF32 MRa, MRb

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MDEBUGSTOP Debug Stop Task

Operands
none This instruction does not have any operands

Opcode LSW: 0000 0000 0000 0000

MSW: 0111 1111 0110 0000

Description When CLA breakpoints are enabled, the MDEBUGSTOP instruction is used to halt a
task so that it can be debugged. That is, MDEBUGSTOP is the CLA breakpoint. If CLA
breakpoints are not enabled, the MDEBUGSTOP instruction behaves like a MNOP.
Unlike the MSTOP, the MIRUN flag is not cleared and an interrupt is not issued. A
single-step or run operation will continue execution of the task.

Restrictions The MDEBUGSTOP instruction cannot be placed 3 instructions before or after a

MBCNDD, MCCNDD or MRCNDD instruction.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example ;

See also MSTOP, MDEBUGSTOP1

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MDEBUGSTOP1 Software Breakpoint

Operands
none This instruction does not have any operands

Opcode LSW: 0000 0000 0000 0000

MSW: 0111 1111 0011 0000

Description The instruction at which a software breakpoint is placed will be replaced by the
MDEBUGSTOP1 instruction. It will halt execution once it reaches the D2 phase in the
pipeline; at that point the subsequent instructions that were fetched, after the halt, will be
flushed from the pipeline. The replace instruction will be re-fetched after this and
execution can continue normally (either in run or step mode).
See Section 8.5.3 for a detailed explanation of its operation.

Restrictions The MDEBUGSTOP1 instruction cannot be placed 3 instructions before or after a

MBCNDD, MCCNDD or MRCNDD instruction.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example ;

See also MSTOP, MDEBUGSTOP

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MEALLOW Enable CLA Write Access to EALLOW Protected Registers

Operands
none This instruction does not have any operands

Opcode LSW: 0000 0000 0000 0000

MSW: 0111 1111 1001 0000

Description This instruction sets the MEALLOW bit in the CLA status register MSTF. When this bit is
set, the CLA is allowed write access to EALLOW protected registers. To again protect
against CLA writes to protected registers, use the MEDIS instruction.
MEALLOW and MEDIS only control CLA write access; reads are allowed even if
MEALLOW has not been executed. MEALLOW and MEDIS are also independent from
the main CPU's EALLOW/EDIS. This instruction does not modify the EALLOW bit in the
main CPU's status register. The MEALLOW bit in MSTF only controls access for the
CLA while the EALLOW bit in the ST1 register only controls access for the main CPU.
As with EALLOW, the MEALLOW bit is overridden via the JTAG port, allowing full control
of register accesses during debug from Code Composer Studio.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example ; C header file including definition of
; the EPwm1Regs structure
;
; The ePWM TZSEL register is EALLOW protected
;
.cdecls C,LIST,"CLAShared.h"
...
_Cla1Task1:
...
MEALLOW ; Allow CLA write access
MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL
MEDIS ; Disallow CLA write access
...
...
MSTOP

See also MEDIS

SPRUII0B – May 2019 – Revised May 2020 Control Law Accelerator (CLA) 979
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MEDIS Disable CLA Write Access to EALLOW Protected Registers

Operands
none This instruction does not have any operands

Opcode LSW: 0000 0000 0000 0000

MSW: 0111 1111 1011 0000

Description This instruction clears the MEALLOW bit in the CLA status register MSTF. When this bit
is clear, the CLA is not allowed write access to EALLOW-protected registers. To enable
CLA writes to protected registers, use the MEALLOW instruction.
MEALLOW and MEDIS only control CLA write access; reads are allowed even if
MEALLOW has not been executed. MEALLOW and MEDIS are also independent from
the main CPU's EALLOW/EDIS. This instruction does not modify the EALLOW bit in the
main CPU's status register. The MEALLOW bit in MSTF only controls access for the
CLA while the EALLOW bit in the ST1 register only controls access for the main CPU.
As with EALLOW, the MEALLOW bit is overridden via the JTAG port, allowing full control
of register accesses during debug from Code Composer Studio.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example ; C header file including definition of
; the EPwm1Regs structure
;
; The ePWM TZSEL register is EALLOW protected
;
.cdecls C,LIST,"CLAShared.h"
...
_Cla1Task1:
...
MEALLOW ; Allow CLA write access
MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL
MEDIS ; Disallow CLA write access
...
...
MSTOP

See also MEALLOW

980 Control Law Accelerator (CLA) SPRUII0B – May 2019 – Revised May 2020
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MEINVF32 MRa, MRb 32-Bit Floating-Point Reciprocal Approximation

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1111 0000 0000

Description This operation generates an estimate of 1/X in 32-bit floating-point format accurate to
approximately 8 bits. This value can be used in a Newton-Raphson algorithm to get a
more accurate answer. That is:
Ye = Estimate(1/X);
Ye = Ye*(2.0 - Ye*X);
Ye = Ye*(2.0 - Ye*X);

After two iterations of the Newton-Raphson algorithm, you will get an exact answer
accurate to the 32-bit floating-point format. On each iteration the mantissa bit accuracy
approximately doubles. The MEINVF32 operation will not generate a negative zero,
DeNorm or NaN value.
MRa = Estimate of 1/MRb;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MEINVF32 generates an underflow condition.
• LVF = 1 if MEINVF32 generates an overflow condition.

Pipeline This is a single-cycle instruction.

Example ; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den ; MR1 = Den
MEINVF32 MR2, MR1 ; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num ; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den ; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ ; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0 ; Store result
MSTOP ; end of task

See also MEISQRTF32 MRa, MRb

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MEISQRTF32 MRa, MRb 32-Bit Floating-Point Square-Root Reciprocal Approximation

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1110 0100 0000

Description This operation generates an estimate of 1/sqrt(X) in 32-bit floating-point format accurate
to approximately 8 bits. This value can be used in a Newton-Raphson algorithm to get a
more accurate answer. That is:
Ye = Estimate(1/sqrt(X));
Ye = Ye*(1.5 - Ye*Ye*X/2.0);
Ye = Ye*(1.5 - Ye*Ye*X/2.0);

After 2 iterations of the Newton-Raphson algorithm, you will get an exact answer
accurate to the 32-bit floating-point format. On each iteration the mantissa bit accuracy
approximately doubles. The MEISQRTF32 operation will not generate a negative zero,
DeNorm or NaN value.
MRa = Estimate of 1/sqrt (MRb);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MEISQRTF32 generates an underflow condition.
• LVF = 1 if MEISQRTF32 generates an overflow condition.

Pipeline This is a single-cycle instruction.

Example ; Y = sqrt(X)
; Ye = Estimate(1/sqrt(X));
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Y = X*Ye
;
_Cla1Task3:
MMOV32 MR0, @_x ; MR0 = X
MEISQRTF32 MR1, MR0 ; MR1 = Ye = Estimate(1/sqrt(X))
MMOV32 MR1, @_x, EQ ; if(X == 0.0) Ye = 0.0
MMPYF32 MR3, MR0, #0.5 ; MR3 = X*0.5
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR0, MR1, MR0 ; MR0 = Y = Ye*X
MMOV32 @_y, MR0 ; Store Y = sqrt(X)
MSTOP ; end of task

See also MEINVF32 MRa, MRb

982 Control Law Accelerator (CLA) SPRUII0B – May 2019 – Revised May 2020
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MF32TOI16 MRa, MRb Convert 32-Bit Floating-Point Value to 16-Bit Integer

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1101 1110 0000

Description Convert a 32-bit floating point value in MRb to a 16-bit integer and truncate. The result
will be stored in MRa.
MRa(15:0) = F32TOI16(MRb);
MRa(31:16) = sign extension of MRa(15);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MF32TOI16 MR1, MR0 ; MR1(15:0) = MF32TOI16(MR0) = 0x0005
; MR1(31:16) = Sign extension of MR1(15) = 0x0000
MMOVIZ MR2, #-5.0 ; MR2 = -5.0 (0xC0A00000)
MF32TOI16 MR3, MR2 ; MR3(15:0) = MF32TOI16(MR2) = -5 (0xFFFB)
; MR3(31:16) = Sign extension of MR3(15) = 0xFFFF

See also MF32TOI16R MRa, MRb

MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOI16R MRa, MRb Convert 32-Bit Floating-Point Value to 16-Bit Integer and Round

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1110 0110 0000

Description Convert the 32-bit floating point value in MRb to a 16-bit integer and round to the nearest
even value. The result is stored in MRa.
MRa(15:0) = F32TOI16round(MRb);
MRa(31:16) = sign extension of MRa(15);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example MMOVIZ MR0, #0x3FD9 ; MR0(31:16) = 0x3FD9
MMOVXI MR0, #0x999A ; MR0(15:0) = 0x999A
; MR0 = 1.7 (0x3FD9999A)
MF32TOI16R MR1, MR0 ; MR1(15:0) = MF32TOI16round (MR0) = 2 (0x0002)
; MR1(31:16) = Sign extension of MR1(15) = 0x0000
MMOVF32 MR2, #-1.7 ; MR2 = -1.7 (0xBFD9999A)
MF32TOI16R MR3, MR2 ; MR3(15:0) = MF32TOI16round (MR2) = -2 (0xFFFE)
; MR3(31:16) = Sign extension of MR2(15) = 0xFFFF

See also MF32TOI16 MRa, MRb

MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOI32 MRa, MRb Convert 32-Bit Floating-Point Value to 32-Bit Integer

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1101 0110 0000

Description Convert the 32-bit floating-point value in MRb to a 32-bit integer value and truncate.
Store the result in MRa.
MRa = F32TOI32(MRb);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example 1 MMOVF32 MR2, #11204005.0 ; MR2 = 11204005.0 (0x4B2AF5A5)
MF32TOI32 MR3, MR2 ; MR3 = MF32TOI32(MR2) = 11204005 (0x00AAF5A5)
MMOVF32 MR0, #-11204005.0 ; MR0 = -11204005.0 (0xCB2AF5A5)
MF32TOI32 MR1, MR0 ; MR1 = MF32TOI32(MR0) = -11204005 (0xFF550A5B)

Example 2 ; Given X, M and B are IQ24 numbers:

; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
; Convert M, X and B from IQ24 to float
;
_Cla1Task2:
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)

; Convert Y from float32 to IQ24

MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also MF32TOUI32 MRa, MRb

MI32TOF32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MF32TOUI16 MRa, MRb Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1110 1010 0000

Description Convert the 32-bit floating point value in MRb to an unsigned 16-bit integer value and
truncate to zero. The result will be stored in MRa. To instead round the integer to the
nearest even value use the MF32TOUI16R instruction.
MRa(15:0) = F32TOUI16(MRb);
MRa(31:16) = 0x0000;

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example MMOVIZ MR0, #9.0 ; MR0 = 9.0 (0x41100000)
MF32TOUI16 MR1, MR0 ; MR1(15:0) = MF32TOUI16(MR0) = 9 (0x0009)
; MR1(31:16) = 0x0000
MMOVIZ MR2, #-9.0 ; MR2 = -9.0 (0xC1100000)
MF32TOUI16 MR3, MR2 ; MR3(15:0) = MF32TOUI16(MR2) = 0 (0x0000)
; MR3(31:16) = 0x0000

See also MF32TOI16 MRa, MRb

MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOUI16R MRa, MRb Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer and Round

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1110 1100 0000

Description Convert the 32-bit floating-point value in MRb to an unsigned 16-bit integer and round to
the closest even value. The result will be stored in MRa. To instead truncate the
converted value, use the MF32TOUI16 instruction.
MRa(15:0) = MF32TOUI16round(MRb);
MRa(31:16) = 0x0000;

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example MMOVIZ MR0, #0x412C ; MR0 = 0x412C
MMOVXI MR0, #0xCCCD ; MR0 = 0xCCCD ; MR0 = 10.8 (0x412CCCCD)
MF32TOUI16R MR1, MR0 ; MR1(15:0) = MF32TOUI16round(MR0) = 11 (0x000B)
; MR1(31:16) = 0x0000
MMOVF32 MR2, #-10.8 ; MR2 = -10.8 (0x0xC12CCCCD)
MF32TOUI16R MR3, MR2 ; MR3(15:0) = MF32TOUI16round(MR2) = 0 (0x0000)
; MR3(31:16) = 0x0000

See also MF32TOI16 MRa, MRb

MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOUI32 MRa, MRb Convert 32-Bit Floating-Point Value to 32-Bit Unsigned Integer

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1101 1010 0000

Description Convert the 32-bit floating-point value in MRb to an unsigned 32-bit integer and store the
result in MRa.
MRa = F32TOUI32(MRb);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example MMOVIZ MR0, #12.5 ; MR0 = 12.5 (0x41480000)
MF32TOUI32 MR0, MR0 ; MR0 = MF32TOUI32 (MR0) = 12 (0x0000000C)
MMOVIZ MR1, #-6.5 ; MR1 = -6.5 (0xC0D00000)
MF32TOUI32 MR2, MR1 ; MR2 = MF32TOUI32 (MR1) = 0.0 (0x00000000)

See also MF32TOI32 MRa, MRb

MI32TOF32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MFRACF32 MRa, MRb Fractional Portion of a 32-Bit Floating-Point Value

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1110 0000 0000

Description Returns in MRa the fractional portion of the 32-bit floating-point value in MRb

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example MMOVIZ MR2, #19.625 ; MR2 = 19.625 (0x419D0000)
MFRACF32 MR3, MR2 ; MR3 = MFRACF32(MR2) = 0.625 (0x3F200000)0)

See also

SPRUII0B – May 2019 – Revised May 2020 Control Law Accelerator (CLA) 989
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MI16TOF32 MRa, MRb Convert 16-Bit Integer to 32-Bit Floating-Point Value

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1110 1000 0000

Description Convert the 16-bit signed integer in MRb to a 32-bit floating point value and store the
result in MRa.
MRa = MI16TOF32(MRb);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example MMOVIZ MR0, #0x0000 ; MR0(31:16) = 0.0 (0x0000)
MMOVXI MR0, #0x0004 ; MR0(15:0) = 4.0 (0x0004)
MI16TOF32 MR1, MR0 ; MR1 = MI16TOF32 (MR0) = 4.0 (0x40800000)

MMOVIZ MR2, #0x0000 ; MR2(31:16) = 0.0 (0x0000)

MMOVXI MR2, #0xFFFC ; MR2(15:0) = -4.0 (0xFFFC)
MI16TOF32 MR3, MR2 ; MR3 = MI16TOF32 (MR2) = -4.0 (0xC0800000)
MSTOP

See also MF32TOI16 MRa, MRb

MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MI16TOF32 MRa, mem16 Convert 16-Bit Integer to 32-Bit Floating-Point Value

Operands
MRa CLA floating-point destination register (MR0 to MR3)
mem16 16-bit source memory location to be converted

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0111 0101 00aa addr

Description Convert the 16-bit signed integer indicated by the mem16 pointer to a 32-bit floating-
point value and store the result in MRa.
MRa = MI16TOF32[mem16];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction:

Example ; Assume A = 4 (0x0004)
; B = -4 (0xFFFC)

MI16TOF32 MR0, @_A ; MR0 = MI16TOF32(A) = 4.0 (0x40800000)

MI16TOF32 MR1, @_B ; MR1 = MI16TOF32(B) = -4.0 (0xC0800000

See also MF32TOI16 MRa, MRb

MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MI32TOF32 MRa, mem32 Convert 32-Bit Integer to 32-Bit Floating-Point Value

Operands
MRa CLA floating-point destination register (MR0 to MR3)
mem32 32-bit memory source for the MMOV32 operation.

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0111 0100 01aa addr

Description Convert the 32-bit signed integer indicated by mem32 to a 32-bit floating point value and
store the result in MRa.
MRa = MI32TOF32[mem32];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example ; Given X, M and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
; Convert M, X and B from IQ24 to float
;

_Cla1Task3:
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)

; Convert Y from float32 to IQ24

MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also MF32TOI32 MRa, MRb

MF32TOUI32 MRa, MRb
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MI32TOF32 MRa, MRb Convert 32-Bit Integer to 32-Bit Floating-Point Value

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1101 1000 0000

Description Convert the signed 32-bit integer in MRb to a 32-bit floating-point value and store the
result in MRa.
MRa = MI32TOF32(MRb);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example ; Example1:
;
MMOVIZ MR2, #0x1111 ; MR2(31:16) = 4369 (0x1111)
MMOVXI MR2, #0x1111 ; MR2(15:0) = 4369 (0x1111)
; MR2 = +286331153 (0x11111111)
MI32TOF32 MR3, MR2 ; MR3 = MI32TOF32 (MR2) = 286331153.0 (0x4D888888)

See also MF32TOI32 MRa, MRb

MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MLSL32 MRa, #SHIFT Logical Shift Left

Operands
MRa CLA floating-point source/destination register (MR0 to MR3)
#SHIFT Number of bits to shift (1 to 32)

Opcode LSW: 0000 0000 0shi ftaa

MSW: 0111 1011 1100 0000

Description Logical shift left of MRa by the number of bits indicated. The number of bits can be 1 to
32.
MARa(31:0) = Logical Shift Left(MARa(31:0) by #SHIFT bits);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example ; Given m2 = (int32)32
; x2 = (int32)64
; b2 = (int32)-128
;
; Calculate:
; m2 = m2*2
; x2 = x2*4
; b2 = b2*8
;
_Cla1Task3:
MMOV32 MR0, @_m2 ; MR0 = 32 (0x00000020)
MMOV32 MR1, @_x2 ; MR1 = 64 (0x00000040)
MMOV32 MR2, @_b2 ; MR2 = -128 (0xFFFFFF80)
MLSL32 MR0, #1 ; MR0 = 64 (0x00000040)
MLSL32 MR1, #2 ; MR1 = 256 (0x00000100)
MLSL32 MR2, #3 ; MR2 = -1024 (0xFFFFFC00)
MMOV32 @_m2, MR0 ; Store results
MMOV32 @_x2, MR1
MMOV32 @_b2, MR2
MSTOP ; end of task

See also MADD32 MRa, MRb, MRc

MASR32 MRa, #SHIFT
MAND32 MRa, MRb, MRc
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MLSR32 MRa, #SHIFT Logical Shift Right

Operands
MRa CLA floating-point source/destination register (MR0 to MR3)
#SHIFT Number of bits to shift (1 to 32)

Opcode LSW: 0000 0000 0shi ftaa

MSW: 0111 1011 1000 0000

Description Logical shift right of MRa by the number of bits indicated. The number of bits can be 1 to
32. Unlike the arithmetic shift (MASR32), the logical shift does not preserve the number's
sign bit. Every bit in the operand is moved the specified number of bit positions, and the
vacant bit-positions are filled in with zeros
MARa(31:0) = Logical Shift Right(MARa(31:0) by #SHIFT bits);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1;}

Pipeline This is a single-cycle instruction.

Example ; Illustrate the difference between MASR32 and MLSR32

MMOVIZ MR0, #0xAAAA ; MR0 = 0xAAAA5555

MMOVXI MR0, #0x5555

MMOV32 MR1, MR0 ; MR1 = 0xAAAA5555

MMOV32 MR2, MR0 ; MR2 = 0xAAAA5555

MASR32 MR1, #1 ; MR1 = 0xD5552AAA

MLSR32 MR2, #1 ; MR2 = 0x55552AAA

MASR32 MR1, #1 ; MR1 = 0xEAAA9555

MLSR32 MR2, #1 ; MR2 = 0x2AAA9555

MASR32 MR1, #6 ; MR1 = 0xFFAAAA55

MLSR32 MR2, #6 ; MR2 = 0x00AAAA55

See also MADD32 MRa, MRb, MRc

MASR32 MRa, #SHIFT
MAND32 MRa, MRb, MRc
MLSL32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 32-Bit Floating-Point Multiply and
Accumulate with Parallel Move

Operands
MR3 floating-point destination/source register MR3 for the add operation
MR2 CLA floating-point source register MR2 for the add operation
MRd CLA floating-point destination register (MR0 to MR3) for the multiply operation
MRd cannot be the same register as MRa
MRe CLA floating-point source register (MR0 to MR3) for the multiply operation
MRf CLA floating-point source register (MR0 to MR3) for the multiply operation
MRa CLA floating-point destination register for the MMOV32 operation (MR0 to MR3).
MRa cannot be MR3 or the same register as MRd.
mem32 32-bit source for the MMOV32 operation

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0011 ffee ddaa addr

Description Multiply and accumulate the contents of floating-point registers and move from register
to memory. The destination register for the MMOV32 cannot be the same as the
destination registers for the MMACF32.
MR3 = MR3 + MR2;
MRd = MRe * MRf;
MRa = [mem32];

Restrictions The destination registers for the MMACF32 and the MMOV32 must be unique. That is,
MRa cannot be MR3 and MRa cannot be the same register as MRd.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMACF32 (add or multiply) generates an underflow condition.
• LVF = 1 if MMACF32 (add or multiply) generates an overflow condition.
MMOV32 sets the NF and ZF flags as follows:
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

Pipeline MMACF32 and MMOV32 complete in a single cycle.

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Example 1 ; Perform 5 multiply and accumulate operations:

;
; X and Y are 32-bit floating point arrays
;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3
;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X ; MAR0 points to X array
MMOVI16 MAR1, #_Y ; MAR1 points to Y array
MNOP ; Delay for MAR0, MAR1 load
MNOP ; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++ ; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y0, MAR1 += 2

MMPYF32 MR2, MR0, MR1 ; MR2 = A = X0 * Y0

|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X1, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y1, MAR1 += 2

MMPYF32 MR3, MR0, MR1 ; MR3 = B = X1 * Y1

|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X2, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y2, MAR2 += 2

MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2

|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y3 M

MACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 * Y3

|| MMOV32 MR0, *MAR0 ; In parallel MR0 = X4
MMOV32 MR1, *MAR1 ; MR1 = Y4

MMPYF32 MR2, MR0, MR1 ; MR2 = E = X4 * Y4

|| MADDF32 MR3, MR3, MR2 ; in parallel MR3 = (A + B + C) + D

MADDF32 MR3, MR3, MR2 ; MR3 = (A + B + C + D) + E

MMOV32 @_Result, MR3 ; Store the result
MSTOP ; end of task

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Example 2 ; sum = X0*B0 + X1*B1 + X2*B2 + Y1*A1 + Y2*B2

;
; X2 = X1
; X1 = X0
; Y2 = Y1 ; Y1 = sum
;
_ClaTask2:
MMOV32 MR0, @_B2 ; MR0 = B2
MMOV32 MR1, @_X2 ; MR1 = X2
MMPYF32 MR2, MR1, MR0 ; MR2 = X2*B2
|| MMOV32 MR0, @_B1 ; MR0 = B1
MMOVD32 MR1, @_X1 ; MR1 = X1, X2 = X1
MMPYF32 MR3, MR1, MR0 ; MR3 = X1*B1
|| MMOV32 MR0, @_B0 ; MR0 = B0
MMOVD32 MR1, @_X0 ; MR1 = X0, X1 = X0

; MR3 = X1*B1 + X2*B2, MR2 = X0*B0

; MR0 = A2
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A2 M

MOV32 MR1, @_Y2 ; MR1 = Y2

; MR3 = X0*B0 + X1*B1 + X2*B2, MR2 = Y2*A2

; MR0 = A1
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A1

MMOVD32 MR1,@_Y1 ; MR1 = Y1, Y2 = Y1

MADDF32 MR3, MR3, MR2 ; MR3 = Y2*A2 + X0*B0 + X1*B1 + X2*B2
|| MMPYF32 MR2, MR1, MR0 ; MR2 = Y1*A1
MADDF32 MR3, MR3, MR2 ; MR3 = Y1*A1 + Y2*A2 + X0*B0 + X1*B1 + X2*B2
MMOV32 @_Y1, MR3 ; Y1 = MR3
MSTOP ; end of task

See also MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MMAXF32 MRa, MRb 32-Bit Floating-Point Maximum

Operands
MRa CLA floating-point source/destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1101 0010 0000

Description if(MRa < MRb) MRa = MRb;

Special cases for the output from the MMAXF32 operation:

• NaN output will be converted to infinity
• A denormalized output will be converted to positive zero.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored
in the destination register.
if(MRa == MRb) {ZF=1; NF=0;}
if(MRa > MRb) {ZF=0; NF=0;}
if(MRa < MRb) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example 1 MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #-2.0 ; MR1 = -2.0 (0xC0000000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMAXF32 MR2, MR1 ; MR2 = -1.5, ZF = NF = 0
MMAXF32 MR1, MR2 ; MR1 = -1.5, ZF = 0, NF = 1
MMAXF32 MR2, MR0 ; MR2 = 5.0, ZF = 0, NF = 1
MAXF32 MR0, MR2 ; MR2 = 5.0, ZF = 1, NF = 0

Example 2 ; X is an array of 32-bit floating-point values

; Find the maximum value in an array X
; and store it in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

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See also MCMPF32 MRa, MRb

MCMPF32 MRa, #16FHi
MMAXF32 MRa, #16FHi
MMINF32 MRa, MRb
MMINF32 MRa, #16FHi

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MMAXF32 MRa, #16FHi 32-Bit Floating-Point Maximum

Operands
MRa CLA floating-point source/destination register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-
point value. The low 16-bits of the mantissa are assumed to be all 0.

Opcode LSW: IIII IIII IIII IIII

MSW: 0111 1001 0000 00aa

Description Compare MRa with the floating-point value represented by the immediate operand. If the
immediate value is larger, then load it into MRa.
if(MRa < #16FHi:0) MRa = #16FHi:0;

#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler will accept either a hex or float as the immediate
value. That is, -1.5 can be represented as #-1.5 or #0xBFC0.
Special cases for the output from the MMAXF32 operation:
• NaN output will be converted to infinity
• A denormalized output will be converted to positive zero.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored
in the destination register.
if(MRa == #16FHi:0) {ZF=1; NF=0;}
if(MRa > #16FHi:0) {ZF=0; NF=0;}
if(MRa < #16FHi:0) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMAXF32 MR0, #5.5 ; MR0 = 5.5, ZF = 0, NF = 1
MMAXF32 MR1, #2.5 ; MR1 = 4.0, ZF = 0, NF = 0
MMAXF32 MR2, #-1.0 ; MR2 = -1.0, ZF = 0, NF = 1
MMAXF32 MR2, #-1.0 ; MR2 = -1.5, ZF = 1, NF = 0

See also MMAXF32 MRa, MRb

MMINF32 MRa, MRb
MMINF32 MRa, #16FHi

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MMINF32 MRa, MRb 32-Bit Floating-Point Minimum

Operands
MRa CLA floating-point source/destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1101 0100 0000

Description if(MRa > MRb) MRa = MRb;

Special cases for the output from the MMINF32 operation:

• NaN output will be converted to infinity
• A denormalized output will be converted to positive zero.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored
in the destination register.
if(MRa == MRb) {ZF=1; NF=0;}
if(MRa > MRb) {ZF=0; NF=0;}
if(MRa < MRb) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example 1 MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMINF32 MR0, MR1 ; MR0 = 4.0, ZF = 0, NF = 0
MMINF32 MR1, MR2 ; MR1 = -1.5, ZF = 0, NF = 0
MMINF32 MR2, MR1 ; MR2 = -1.5, ZF = 1, NF = 0
MMINF32 MR1, MR0 ; MR2 = -1.5, ZF = 0, NF = 1

Example 2 ;
; X is an array of 32-bit floating-point values
; Find the minimum value in an array X
; and store it in Result
;

_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMINF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

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See also MMAXF32 MRa, MRb

MMAXF32 MRa, #16FHi
MMINF32 MRa, #16FHi

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MMINF32 MRa, #16FHi 32-Bit Floating-Point Minimum

Operands
MRa floating-point source/destination register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-
point value. The low 16-bits of the mantissa are assumed to be all 0.

Opcode LSW: IIII IIII IIII IIII

MSW: 0111 1001 0100 00aa

Description Compare MRa with the floating-point value represented by the immediate operand. If the
immediate value is smaller, then load it into MRa.
if(MRa > #16FHi:0) MRa = #16FHi:0;

#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler will accept either a hex or float as the immediate
value. That is, -1.5 can be represented as #-1.5 or #0xBFC0.
Special cases for the output from the MMINF32 operation:
• NaN output will be converted to infinity
• A denormalized output will be converted to positive zero.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored
in the destination register.
if(MRa == #16FHi:0) {ZF=1; NF=0;}
if(MRa > #16FHi:0) {ZF=0; NF=0;}
if(MRa < #16FHi:0) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMINF32 MR0, #5.5 ; MR0 = 5.0, ZF = 0, NF = 1
MMINF32 MR1, #2.5 ; MR1 = 2.5, ZF = 0, NF = 0
MMINF32 MR2, #-1.0 ; MR2 = -1.5, ZF = 0, NF = 1
MMINF32 MR2, #-1.5 ; MR2 = -1.5, ZF = 1, NF = 0

See also MMAXF32 MRa, #16FHi

MMAXF32 MRa, MRb
MMINF32 MRa, MRb

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MMOV16 MARx, MRa, #16I Load the Auxiliary Register with MRa + 16-bit Immediate Value

Operands
MARx Auxiliary register MAR0 or MAR1
MRa CLA Floating-point register (MR0 to MR3)
#16I 16-bit immediate value

Opcode LSW: IIII IIII IIII IIII (opcode of MMOV16 MAR0, MRa, #16I)
MSW: 0111 1111 1101 00AA

LSW: IIII IIII IIII IIII (opcode of MMOV16 MAR1, MRa, #16I)
MSW: 0111 1111 1111 00AA

Description Load the auxiliary register, MAR0 or MAR1, with MRa(15:0) + 16-bit immediate value.
Refer to the pipeline section for important information regarding this instruction.
MARx = MRa(15:0) + #16I;

Flags This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction. The load of MAR0 or MAR1 will occur in the EXE
phase of the pipeline. Any post increment of MAR0 or MAR1 using indirect addressing
will occur in the D2 phase of the pipeline. Therefore the following applies when loading
the auxiliary registers:
• I1 and I2
The two instructions following MMOV16 will use MAR0/MAR1 before the update
occurs. Thus these two instructions will use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-
increment addressing occur in the D2 phase. Thus I3 cannot use the auxiliary
register or there will be a conflict. In the case of a conflict, the update due to address-
mode post increment will win and the auxiliary register will not be updated with #_X.
• I4
Starting with the 4th instruction MAR0 or MAR1 will be the new value loaded with
MMOVI16.
; Assume MAR0 is 50, MR0 is 10, and #_X is 20

MMOV16 MAR0, MR0, #_X ; Load MAR0 with address of X (20) + MR0 (10)
<Instruction 1> ; I1 Will use the old value of MAR0 (50)
<Instruction 2> ; I2 Will use the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Will use the new value of MAR0 (30)
<Instruction 5> ; I5
Table 8-17. Pipeline Activity For MMOV16 MARx, MRa , #16I
Instruction F1 F2 D1 D2 R1 R2 E W
MMOV16 MAR0, MR0, #_X MMOV16
I1 I1 MMOV16
I2 I2 I1 MMOV16
I3 I3 I2 I1 MMOV16
I4 I4 I3 I2 I1 MMOV16
I5 I5 I4 I3 I2 I1 MMOV16
MMOV1
I6 I6 I5 I4 I3 I2 I1
6

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Example 1 ; Calculate an offset into a sin/cos table

;
_Cla1Task1:
MMOV32 MR0,@_rad ; MR0 = rad
MMOV32 MR1,@_TABLE_SIZEDivTwoPi ; MR1 = TABLE_SIZE/(2*Pi)
MMPYF32 MR1,MR0,MR1 ; MR1 = rad* TABLE_SIZE/(2*Pi)
|| MMOV32 MR2,@_TABLE_MASK ; MR2 = TABLE_MASK
MF32TOI32 MR3,MR1 ; MR3 = K=int(rad*TABLE_SIZE/(2*Pi))
MAND32 MR3,MR3,MR2 ; MR3 = K & TABLE_MASK
MLSL32 MR3,#1 ; MR3 = K * 2

MMOV16 MAR0,MR3,#_Cos0 ; MAR0 K*2+addr of table.Cos0

MFRACF32 MR1,MR1 ; I1
MMOV32 MR0,@_TwoPiDivTABLE_SIZE ; I2
MMPYF32 MR1,MR1,MR0 ; I3
|| MMOV32 MR0,@_Coef3

MMOV32 MR2,*MAR0[#-64]++ ; MR2 = *MAR0, MAR0 += (-64)

...
...
MSTOP ; end of task

Example 2 ; This task logs the last NUM_DATA_POINTS

; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task will go back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC will trigger this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
; T_sys = 1/200MHz = 5ns
; T_adc = 4*T_sys = 20ns
; The ADC will take 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register may be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg 0, N
.loop
MNOP ;I1 - I28 Wait till I36 to read result
.eval N + 1, N
.break N = 28
.endloop
MMOVZ16 MR0, @_ConversionCount ;I29 Current Conversion
MMOV16 MAR1, MR0, #_VoltageCLA ;I30 Next array location
MUI16TOF32 MR0, MR0 ;I31 Convert count to float32
MADDF32 MR0, MR0, #1.0 ;I32 Add 1 to conversion count
MCMPF32 MR0, #NUM_DATA_POINTS.0 ;I33 Compare count to max
MF32TOUI16 MR0, MR0 ;I34 Convert count to Uint16
MNOP ;I35 Wait till I36 to read result
MMOVZ16 MR2, @_AdcaResultRegs.ADCRESULT1 ;I36 Read ADCRESULT1
MMOV16 *MAR1, MR2 ; Store ADCRESULT1
MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS
MMOVIZ MR1, #0.0 ; Always executed: MR1=0
MNOP
MNOP
MMOV16 @_ConversionCount, MR0 ; If branch not taken
MSTOP ; store current count

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www.ti.com Instruction Set
_RestartCount
MMOV16 @_ConversionCount, MR1 ; If branch taken, restart count
MSTOP ; end of task

; This task initializes the ConversionCount

; to zero
;
_Cla1Task8:
MMOVIZ MR0, #0.0
MMOV16 @_ConversionCount, MR0
MSTOP
_ClaT8End:

See also

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Instruction Set www.ti.com

MMOV16 MARx, mem16 Load MAR1 with 16-bit Value

Operands
MARx CLA auxiliary register MAR0 or MAR1
mem16 16-bit destination memory accessed using one of the available addressing modes

Opcode LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 MAR0, mem16)
MSW: 0111 0110 0000 addr

LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 MAR1, mem16)
MSW: 0111 0110 0100 addr

Description Load MAR0 or MAR1 with the 16-bit value pointed to by mem16. Refer to the pipeline
section for important information regarding this instruction.
MAR1 = [mem16];

Flags No flags MSTF flags are affected.

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction. The load of MAR0 or MAR1 will occur in the EXE
phase of the pipeline. Any post increment of MAR0 or MAR1 using indirect addressing
will occur in the D2 phase of the pipeline. Therefore the following applies when loading
the auxiliary registers:
• I1 and I2
The two instructions following MMOV16 will use MAR0/MAR1 before the update
occurs. Thus these two instructions will use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-
increment addressing occur in the D2 phase. Thus I3 cannot use the auxiliary
register or there will be a conflict. In the case of a conflict, the update due to address-
mode post increment will win send the auxiliary register will not be updated with #_X.
• I4
Starting with the 4th instruction MAR0 or MAR1 will be the new value loaded with
MMOV16.
; Assume MAR0 is 50 and @_X is 20

MMOV16 MAR0, @_X ; Load MAR0 with the contents of X (20)

<Instruction 1> ; I1 Will use the old value of MAR0 (50)
<Instruction 2> ; I2 Will use the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Will use the new value of MAR0 (20)
<Instruction 5> ; I5
....
Table 8-18. Pipeline Activity For MMOV16 MAR0/MAR1, mem16
Instruction F1 F2 D1 D2 R1 R2 E W
MMOV16 MAR0, @_X MMOV16
I1 I1 MMOV16
I2 I2 I1 MMOV16
I3 I3 I2 I1 MMOV16
I4 I4 I3 I2 I1 MMOV16
I5 I5 I4 I3 I2 I1 MMOV16
MMOV1
I6 I6 I5 I4 I3 I2 I1
6

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www.ti.com Instruction Set

Example ; This task logs the last NUM_DATA_POINTS

; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task will go back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC will trigger this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
; T_sys = 1/200MHz = 5ns
; T_adc = 4*T_sys = 20ns
; The ADC will take 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register may be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg 0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval N + 1, N
.break N = 28
.endloop
MMOVZ16 MR0, @_ConversionCount ;I29 Current Conversion
MMOV16 MAR1, MR0, #_VoltageCLA ;I30 Next array location
MUI16TOF32 MR0, MR0 ;I31 Convert count to float32
MADDF32 MR0, MR0, #1.0 ;I32 Add 1 to conversion count
MCMPF32 MR0, #NUM_DATA_POINTS.0 ;I33 Compare count to max
MF32TOUI16 MR0, MR0 ;I34 Convert count to Uint16
MNOP ;I35 Wait till I36 to read result
MMOVZ16 MR2, @_AdcaResultRegs.ADCRESULT1 ;I36 Read ADCRESULT1
MMOV16 *MAR1, MR2 ; Store ADCRESULT1
MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS
MMOVIZ MR1, #0.0 ; Always executed: MR1=0
MNOP
MNOP
MMOV16 @_ConversionCount, MR0 ; If branch not taken
MSTOP ; store current count

_RestartCount
MMOV16 @_ConversionCount, MR1 ; If branch taken, restart count
MSTOP ; end of task

; This task initializes the ConversionCount

; to zero
;
_Cla1Task8:
MMOVIZ MR0, #0.0
MMOV16 @_ConversionCount, MR0
MSTOP
_ClaT8End:

See also

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MMOV16 mem16, MARx Move 16-Bit Auxiliary Register Contents to Memory

Operands
mem16 16-bit destination memory accessed using one of the available addressing modes
MARx CLA auxiliary register MAR0 or MAR1

Opcode LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 mem16, MAR0)
MSW: 0111 0110 1000 addr

LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 mem16, MAR1)
MSW: 0111 0110 1100 addr

Description Store the contents of MAR0 or MAR1 in the 16-bit memory location pointed to by
mem16.
[mem16] = MAR0;

Flags No flags MSTF flags are affected.

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
See also

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www.ti.com Instruction Set

MMOV16 mem16, MRa Move 16-Bit Floating-Point Register Contents to Memory

Operands
mem16 16-bit destination memory accessed using one of the available addressing modes
MRa CLA floating-point source register (MR0 to MR3)

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0111 0101 11aa addr

Description Move 16-bit value from the lower 16-bits of the floating-point register (MRa(15:0)) to the
location pointed to by mem16.
[mem16] = MRa(15:0);

Flags No flags MSTF flags are affected.

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example ; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task will go back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC will trigger this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
; T_sys = 1/200MHz = 5ns
; T_adc = 4*T_sys = 20ns
; The ADC will take 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register may be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg 0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval N + 1, N
.break N = 28
.endloop
MMOVZ16 MR0, @_ConversionCount ;I29 Current Conversion
MMOV16 MAR1, MR0, #_VoltageCLA ;I30 Next array location
MUI16TOF32 MR0, MR0 ;I31 Convert count to float32
MADDF32 MR0, MR0, #1.0 ;I32 Add 1 to conversion count
MCMPF32 MR0, #NUM_DATA_POINTS.0 ;I33 Compare count to max
MF32TOUI16 MR0, MR0 ;I34 Convert count to Uint16
MNOP ;I35 Wait till I36 to read result
MMOVZ16 MR2, @_AdcaResultRegs.ADCRESULT1 ;I36 Read ADCRESULT1
MMOV16 *MAR1, MR2 ; Store ADCRESULT1
MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS
MMOVIZ MR1, #0.0 ; Always executed: MR1=0
MNOP
MNOP
MMOV16 @_ConversionCount, MR0 ; If branch not taken
MSTOP ; store current count

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_RestartCount
MMOV16 @_ConversionCount, MR1 ; If branch taken, restart count
MSTOP ; end of task

; This task initializes the ConversionCount

; to zero
;
_Cla1Task8:
MMOVIZ MR0, #0.0
MMOV16 @_ConversionCount, MR0
MSTOP
_ClaT8End:

See also MMOVIZ MRa, #16FHi

MMOVXI MRa, #16FLoHex

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www.ti.com Instruction Set

MMOV32 mem32, MRa Move 32-Bit Floating-Point Register Contents to Memory

Operands
MRa floating-point register (MR0 to MR3)
mem32 32-bit destination memory accessed using one of the available addressing modes

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0111 0100 11aa addr

Description Move from MRa to 32-bit memory location indicated by mem32.

[mem32] = MRa;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

No flags affected.

Pipeline This is a single-cycle instruction.

Example ; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating point arrays;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X ; MAR0 points to X array
MMOVI16 MAR1, #_Y ; MAR1 points to Y array
MNOP ; Delay for MAR0, MAR1 load
MNOP ; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++ ; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y0, MAR1 += 2
MMPYF32 MR2, MR0, MR1 ; MR2 = A = X0 * Y0
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X1, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y1, MAR1 += 2
MMPYF32 MR3, MR0, MR1 ; MR3 = B = X1 * Y1
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X2, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y2, MAR2 += 2

MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2

|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y3

MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 * Y3

|| MMOV32 MR0, *MAR0 ; In parallel MR0 = X4
MMOV32 MR1, *MAR1 ; MR1 = Y4
MMPYF32 MR2, MR0, MR1 ; MR2 = E = X4 * Y4
|| MADDF32 MR3, MR3, MR2 ; in parallel MR3 = (A + B + C) + D
MADDF32 MR3, MR3, MR2 ; MR3 = (A + B + C + D) + E
MMOV32 @_Result, MR3 ; Store the result MSTOP ; end of task

See also MMOV32 mem32, MSTF

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MMOV32 mem32, MSTF Move 32-Bit MSTF Register to Memory

Operands
MSTF floating-point status register
mem32 32-bit destination memory

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0111 0111 0100 addr

Description Copy the CLA's floating-point status register, MSTF, to memory.

[mem32] = MSTF;

Flags This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

One of the uses of this instruction is to save off the return PC (RPC) prior to calling a
function. The decision to jump to a function is made when the MCCNDD is in the
decode2 (D2) phase of the pipeline; the RPC is also updated in this phase. The actual
jump occurs three cycles later when MCCNDD enters its execution (E) phase. The user
must, therefore, save the old RPC before MCCNDD updates it in the D2 phase, that is, it
must save MSTF three instructions prior to the function call.

Example The following example illustrates the pipeline flow for the context save (of the flags and
RPC) prior to a function call. The first column in the comments shows the pipeline stages
for the MMOV32 instruction while the second column pertains to the MCCNDD
instruction.
MMOV32 @_temp, MSTF ; D2| |
MNOP ; R1|F1| MCCNDD is fetched
MNOP ; R2|F2|
MNOP ; E |D1|
MCCNDD _bar, UNC ; W |D2| old RPC written to memory,
; | | RPC updated with MPC+1
MNOP ; |R1|
MNOP ; |R2|
MNOP ; |E | execution branches to _bar

See also MMOV32 mem32, MRa

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MMOV32 MRa, mem32 {, CNDF} Conditional 32-Bit Move

Operands
MRa CLA floating-point destination register (MR0 to MR3)
mem32 32-bit memory location accessed using one of the available addressing modes
CNDF optional condition.

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0111 00cn dfaa addr

Description If the condition is true, then move the 32-bit value referenced by mem32 to the floating-
point register indicated by MRa.
if (CNDF == TRUE) MRa = [mem32];

CNDF is one of the following conditions:

(1)
Encode CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal to zero NF == 0
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to zero ZF == 1 OR NF == 1
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
(2)
1111 UNCF Unconditional with flag None
modification
(1)
Values not shown are reserved.
(2)
This is the default operation if no CNDF field is specified. This condition will allow the ZF and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

if(CNDF == UNCF)
{
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }
}
else No flags modified;

Pipeline This is a single-cycle instruction.

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Example ; Given A, B, X, M1 and M2 are 32-bit floating-point

; numbers
;
; if(A == B) calculate Y = X*M1
; if(A! = B) calculate Y = X*M2
;
_Cla1Task5:
MMOV32 MR0, @_A
MMOV32 MR1, @_B
MCMPF32 MR0, MR1
MMOV32 MR2, @_M1, EQ ; if A == B, MR2 = M1
; Y = M1*X
MMOV32 MR2, @_M2, NEQ ; if A! = B, MR2 = M2
; Y = M2*X
MMOV32 MR3, @_X
MMPYF32 MR3, MR2, MR3 ; Calculate Y
MMOV32 @_Y, MR3 ; Store Y
MSTOP ; end of task

See also MMOV32 MRa, MRb {, CNDF}

MMOVD32 MRa, mem32

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www.ti.com Instruction Set

MMOV32 MRa, MRb {, CNDF} Conditional 32-Bit Move

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)
CNDF optional condition.

Opcode LSW: 0000 0000 cndf bbaa

MSW: 0111 1010 1100 0000

Description If the condition is true, then move the 32-bit value in MRb to the floating-point register
indicated by MRa.
if (CNDF == TRUE) MRa = MRb;

CNDF is one of the following conditions:

(3)
Encode CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal to zero NF == 0
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to zero ZF == 1 OR NF == 1
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
(4)
1111 UNCF Unconditional with flag None
modification
(3)
Values not shown are reserved.
(4)
This is the default operation if no CNDF field is specified. This condition will allow the ZF, and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

if(CNDF == UNCF)
{
NF = MRa(31); ZF = 0;
if(MRa(30:23) == 0) {ZF = 1; NF = 0;}
}
else No flags modified;

Pipeline This is a single-cycle instruction.

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Example ; Given: X = 8.0

; Y = 7.0
; A = 2.0
; B = 5.0
; _ClaTask1
MMOV32 MR3, @_X ; MR3 = X = 8.0
MMOV32 MR0, @_Y ; MR0 = Y = 7.0
MMAXF32 MR3, MR0 ; ZF = 0, NF = 0, MR3 = 8.0
MMOV32 MR1, @_A, GT ; true, MR1 = A = 2.0
MMOV32 MR1, @_B, LT ; false, does not load MR1
MMOV32 MR2, MR1, GT ; true, MR2 = MR1 = 2.0
MMOV32 MR2, MR0, LT ; false, does not load MR2
MSTOP

See also MMOV32 MRa, mem32 {,CNDF}

1018 Control Law Accelerator (CLA) SPRUII0B – May 2019 – Revised May 2020
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www.ti.com Instruction Set

MMOV32 MSTF, mem32 Move 32-Bit Value from Memory to the MSTF Register

Operands
MSTF CLA status register
mem32 32-bit source memory location

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0111 0111 0000 addr

Description Move from memory to the CLA's status register MSTF. This instruction is most useful
when nesting function calls (via MCCNDD).
MSTF = [mem32];

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified Yes Yes Yes Yes Yes

Loading the status register will overwrite all flags and the RPC field. The MEALLOW field
is not affected.

Pipeline This is a single-cycle instruction.

Example

See also MMOV32 mem32, MSTF

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MMOVD32 MRa, mem32 Move 32-Bit Value from Memory with Data Copy

Operands
MRa CLA floating-point register (MR0 to MR3)
mem32 32-bit memory location accessed using one of the available addressing modes

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0111 0100 00aa addr

Description Move the 32-bit value referenced by mem32 to the floating-point register indicated by
MRa.
MRa = [mem32];
[mem32+2] = [mem32];

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0){ ZF = 1; NF = 0; }

Pipeline This is a single-cycle instruction.

Example ; sum = X0*B0 + X1*B1 + X2*B2 + Y1*A1 + Y2*B2
;
; X2 = X1
; X1 = X0
; Y2 = Y1
; Y1 = sum
;
_Cla1Task2:
MMOV32 MR0, @_B2 ; MR0 = B2
MMOV32 MR1, @_X2 ; MR1 = X2
MMPYF32 MR2, MR1, MR0 ; MR2 = X2*B2
|| MMOV32 MR0, @_B1 ; MR0 = B1
MMOVD32 MR1, @_X1 ; MR1 = X1, X2 = X1
MMPYF32 MR3, MR1, MR0 ; MR3 = X1*B1
|| MMOV32 MR0, @_B0 ; MR0 = B0
MMOVD32 MR1, @_X0 ; MR1 = X0, X1 = X0

; MR3 = X1*B1 + X2*B2, MR2 = X0*B0

; MR0 = A2
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A2

MMOV32 MR1, @_Y2 ; MR1 = Y2

; MR3 = X0*B0 + X1*B1 + X2*B2, MR2 = Y2*A2

; MR0 = A1
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A1

MMOVD32 MR1,@_Y1 ; MR1 = Y1, Y2 = Y1

MADDF32 MR3, MR3, MR2 ; MR3 = Y2*A2 + X0*B0 + X1*B1 + X2*B2
|| MMPYF32 MR2, MR1, MR0 ; MR2 = Y1*A1
MADDF32 MR3, MR3, MR2 ; MR3 = Y1*A1 + Y2*A2 + X0*B0 + X1*B1 + X2*B2
MMOV32 @_Y1, MR3 ; Y1 = MR3
MSTOP ; end of task

See also MMOV32 MRa, mem32 {,CNDF}

1020 Control Law Accelerator (CLA) SPRUII0B – May 2019 – Revised May 2020
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www.ti.com Instruction Set

MMOVF32 MRa, #32F Load the 32-Bits of a 32-Bit Floating-Point Register

Operands This instruction is an alias for MMOVIZ and MMOVXI instructions. The second operand
is translated by the assembler such that the instruction becomes:
MMOVIZ MRa, #16FHiHex MMOVXI MRa, #16FLoHex
MRa CLA floating-point destination register (MR0 to MR3)
#32F immediate float value represented in floating-point representation

Opcode LSW: IIII IIII IIII IIII (opcode of MMOVIZ MRa, #16FHiHex)
MSW: 0111 1000 0100 00aa
LSW: IIII IIII IIII IIII (opcode of MMOVXI MRa, #16FLoHex)
MSW: 0111 1000 1000 00aa

Description Note: This instruction accepts the immediate operand only in floating-point
representation. To specify the immediate value as a hex value (IEEE 32-bit floating-
point format) use the MOVI32 MRa, #32FHex instruction.
Load the 32-bits of MRa with the immediate float value represented by #32F.
#32F is a float value represented in floating-point representation. The assembler will only
accept a float value represented in floating-point representation. That is, 3.0 can only be
represented as #3.0. #0x40400000 will result in an error.
MRa = #32F;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline Depending on #32FH, this instruction takes one or two cycles. If all of the lower 16-bits
of the IEEE 32-bit floating-point format of #32F are zeros, then the assembler will
convert MMOVF32 into only MMOVIZ instruction. If the lower 16-bits of the IEEE 32-bit
floating-point format of #32F are not zeros, then the assembler will convert MMOVF32
into MMOVIZ and MMOVXI instructions.
Example MMOVF32 MR1, #3.0 ; MR1 = 3.0 (0x40400000)
; Assembler converts this instruction as
; MMOVIZ MR1, #0x4040

MMOVF32 MR2, #0.0 ; MR2 = 0.0 (0x00000000)

; Assembler converts this instruction as
; MMOVIZ MR2, #0x0

MMOVF32 MR3, #12.265 ; MR3 = 12.625 (0x41443D71)

; Assembler converts this instruction as
; MMOVIZ MR3, #0x4144
; MMOVXI MR3, #0x3D71

See also MMOVIZ MRa, #16FHi

MMOVXI MRa, #16FLoHex
MMOVI32 MRa, #32FHex

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MMOVI16 MARx, #16I Load the Auxiliary Register with the 16-Bit Immediate Value

Operands
MARx Auxiliary register MAR0 or MAR1
#16I 16-bit immediate value

Opcode LSW: IIII IIII IIII IIII (opcode of MMOVI16 MAR0, #16I)
MSW: 0111 1111 1100 0000

LSW: IIII IIII IIII IIII (opcode of MMOVI16 MAR1, #16I)

MSW: 0111 1111 1110 0000

Description Load the auxiliary register, MAR0 or MAR1, with a 16-bit immediate value. Refer to the
pipeline section for important information regarding this instruction.
MARx = #16I;

Flags This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction. The immediate load of MAR0 or MAR1 will occur in the
EXE phase of the pipeline. Any post increment of MAR0 or MAR1 using indirect
addressing will occur in the D2 phase of the pipeline. Therefore the following applies
when loading the auxiliary registers:
• I1 and I2
The two instructions following MMOVI16 will use MAR0/MAR1 before the update
occurs. Thus these two instructions will use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-
increment addressing occur in the D2 phase. Thus I3 cannot use the auxiliary
register or there will be a conflict. In the case of a conflict, the update due to address-
mode post increment will win snd the auxiliary register will not be updated with #_X.
• I4
Starting with the 4th instruction MAR0 or MAR1 will be the new value loaded with
MMOVI16.
; Assume MAR0 is 50 and #_X is 20

MMOVI16 MAR0, #_X ; Load MAR0 with address of X (20)

<Instruction 1> ; I1 Will use the old value of MAR0 (50)
<Instruction 2> ; I2 Will use the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Will use the new value of MAR0 (20)
<Instruction 5> ; I5
....
Table 8-19. Pipeline Activity For MMOVI16 MAR0/MAR1, #16I
Instruction F1 F2 D1 D2 R1 R2 E W
MMOVI16 MAR0, #_X MMOVI16
I1 I1 MMOVI16
I2 I2 I1 MMOVI16
I3 I3 I2 I1 MMOVI16
I4 I4 I3 I2 I1 MMOVI16
I5 I5 I4 I3 I2 I1 MMOVI16
MMOVI
I6 I6 I5 I4 I3 I2 I1
16

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MMOVI32 MRa, #32FHex Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate

Operands
MRa floating-point register (MR0 to MR3)
#32FHex A 32-bit immediate value that represents an IEEE 32-bit floating-point value.

This instruction is an alias for MMOVIZ and MMOVXI instructions. The second operand
is translated by the assembler such that the instruction becomes:
MMOVIZ MRa, #16FHiHex
MMOVXI MRa, #16FLoHex

Opcode LSW: IIII IIII IIII IIII (opcode of MMOVIZ MRa, #16FHiHex)
MSW: 0111 1000 0100 00aa

LSW: IIII IIII IIII IIII (opcode of MMOVXI MRa, #16FLoHex)

MSW: 0111 1000 1000 00aa

Description Note: This instruction only accepts a hex value as the immediate operand. To specify the
immediate value with a floating-point representation use the MMOVF32 MRa, #32F
instruction.
Load the 32-bits of MRa with the immediate 32-bit hex value represented by #32Fhex.
#32Fhex is a 32-bit immediate hex value that represents the IEEE 32-bit floating-point
value of a floating-point number. The assembler will only accept a hex immediate value.
That is, 3.0 can only be represented as #0x40400000. #3.0 will result in an error.
MRa = #32FHex;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline Depending on #32FHex, this instruction takes one or two cycles. If all of the lower 16-
bits of #32FHex are zeros, then assembler will convert MOVI32 to the MMOVIZ
instruction. If the lower 16-bits of #32FHex are not zeros, then assembler will convert
MOVI32 to a MMOVIZ and a MMOVXI instruction.
Example MOVI32 MR1, #0x40400000 ; MR1 = 0x40400000
; Assembler converts this instruction as
; MMOVIZ MR1, #0x4040

MOVI32 MR2, #0x00000000 ; MR2 = 0x00000000

; Assembler converts this instruction as
; MMOVIZ MR2, #0x0

MOVI32 MR3, #0x40004001 ; MR3 = 0x40004001

; Assembler converts this instruction as
; MMOVIZ MR3, #0x4000
; MMOVXI MR3, #0x4001

MOVI32 MR0, #0x00004040 ; MR0 = 0x00004040

; Assembler converts this instruction as
; MMOVIZ MR0, #0x0000
; MMOVXI MR0, #0x4040

See also MMOVIZ MRa, #16FHi

MMOVXI MRa, #16FLoHex
MMOVF32 MRa, #32F

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MMOVIZ MRa, #16FHi Load the Upper 16-Bits of a 32-Bit Floating-Point Register

Operands
MRa floating-point register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-
point value. The low 16-bits of the mantissa are assumed to be all 0.

Opcode LSW: IIII IIII IIII IIII

MSW: 0111 1000 0100 00aa

Description Load the upper 16-bits of MRa with the immediate value #16FHi and clear the low 16-
bits of MRa.
#16FHiHex is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-
bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0. The
assembler will only accept a decimal or hex immediate value. That is, -1.5 can be
represented as #-1.5 or #0xBFC0.
By itself, MMOVIZ is useful for loading a floating-point register with a constant in which
the lowest 16-bits of the mantissa are 0. Some examples are 2.0 (0x40000000), 4.0
(0x40800000), 0.5 (0x3F000000), and -1.5 (0xBFC00000). If a constant requires all 32-
bits of a floating-point register to be iniitalized, then use MMOVIZ along with the
MMOVXI instruction.
MRa(31:16) = #16FHi;
MRa(15:0) = 0;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example ; Load MR0 and MR1 with -1.5 (0xBFC00000)
MMOVIZ MR0, #0xBFC0 ; MR0 = 0xBFC00000 (1.5)
MMOVIZ MR1, #-1.5 ; MR1 = -1.5 (0xBFC00000)

; Load MR2 with pi = 3.141593 (0x40490FDB)

MMOVIZ MR2, #0x4049 ; MR2 = 0x40490000
MMOVXI MR2, #0x0FDB ; MR2 = 0x40490FDB

See also MMOVF32 MRa, #32F

MMOVI32 MRa, #32FHex
MMOVXI MRa, #16FLoHex

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MMOVZ16 MRa, mem16 Load MRx With 16-bit Value

Operands
MRa CLA floating-point destination register (MR0 to MR3)
mem16 16-bit source memory location

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0111 0101 10aa addr

Description Move the 16-bit value referenced by mem16 to the floating-point register indicated by
MRa.
MRa(31:16) = 0;
MRa(15:0) = [mem16];

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.
NF = 0;
if (MRa(31:0)== 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

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MMOVXI MRa, #16FLoHex Move Immediate to the Low 16-Bits of a Floating-Point Register

Operands
MRa CLA floating-point register (MR0 to MR3)
#16FLoHex A 16-bit immediate hex value that represents the lower 16-bits of an IEEE 32-bit
floating-point value. The upper 16-bits will not be modified.

Opcode LSW: IIII IIII IIII IIII

MSW: 0111 1000 1000 00aa

Description Load the low 16-bits of MRa with the immediate value #16FLoHex. #16FLoHex
represents the lower 16-bits of an IEEE 32-bit floating-point value. The upper 16-bits of
MRa will not be modified. MMOVXI can be combined with the MMOVIZ instruction to
initialize all 32-bits of a MRa register.
MRa(15:0) = #16FLoHex;
MRa(31:16) = Unchanged;

Flags
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example ; Load MR0 with pi = 3.141593 (0x40490FDB)
MMOVIZ MR0,#0x4049 ; MR0 = 0x40490000
MMOVXI MR0,#0x0FDB ; MR0 = 0x40490FDB

See also MMOVIZ MRa, #16FHi

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MMPYF32 MRa, MRb, MRc 32-Bit Floating-Point Multiply

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 00cc bbaa

MSW: 0111 1100 0000 0000

Description Multiply the contents of two floating-point registers.

MRa = MRb * MRc;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline This is a single-cycle instruction.

Example ; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den ; MR1 = Den
MEINVF32 MR2, MR1 ; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num ; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den ; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ ; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0 ; Store result
MSTOP ; end of task

See also MMPYF32 MRa, #16FHi, MRb

MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf
MMPYF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MMPYF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf
MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRa, #16FHi, MRb 32-Bit Floating-Point Multiply

Operands
MRa CLA floating-point destination register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-
point value. The low 16-bits of the mantissa are assumed to be all 0.
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: IIII IIII IIII IIII

MSW: 0111 0111 1000 bbaa

Description Multiply MRb with the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler will accept either a hex or float as the immediate value.
That is, the value -1.5 can be represented as #-1.5 or #0xBFC0.
MRa = MRb * #16FHi:0;

This instruction can also be written as MMPYF32 MRa, MRb, #16FHi.

Flags This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline This is a single-cycle instruction.

Example 1 ; Same as example 2 but #16FHi is represented in float
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, #3.0, MR3 ; MR0 = 3.0 * MR3 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

Example 2 ; Same as example 1 but #16FHi is represented in Hex

MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, #0x4040, MR3 ; MR0 = 0x4040 * MR3 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

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Example 3 ; Given X, M and B are IQ24 numbers:

; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
;
_Cla1Task2:
;
; Convert M, X and B from IQ24 to float
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also MMPYF32 MRa, MRb, #16FHi

MMPYF32 MRa, MRb, MRc
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MMPYF32 MRa, MRb, #16FHi 32-Bit Floating-Point Multiply

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-
point value. The low 16-bits of the mantissa are assumed to be all 0.

Opcode LSW: IIII IIII IIII IIII

MSW: 0111 0111 1000 bbaa

Description Multiply MRb with the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler will accept either a hex or float as the immediate value.
That is, the value -1.5 can be represented as #-1.5 or #0xBFC0.
MRa = MRb * #16FHi:0;

This instruction can also be writen as MMPYF32 MRa, #16FHi, MRb.

Flags This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline This is a single-cycle instruction.

Example 1 ;Same as example 2 but #16FHi is represented in float
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, MR3, #3.0 ; MR0 = MR3 * 3.0 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

Example 2 ;Same as above example but #16FHi is represented in Hex

MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, MR3, #0x4040 ; MR0 = MR3 * 0x4040 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

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Example 3 ; Given X, M and B are IQ24 numbers:

; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
_Cla1Task2:
;
; Convert M, X and B from IQ24 to float
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, #0x3380, MR0 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, #0x3380, MR1 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, #0x3380, MR2 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)

; Convert Y from float32 to IQ24

MMPYF32 MR2, #0x4B80, MR2 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also MMPYF32 MRa, #16FHi, MRb

MMPYF32 MRa, MRb, MRc

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MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf 32-Bit Floating-Point Multiply with Parallel
Add

Operands
MRa CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRa cannot be the same register as MRd
MRb CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRc CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRd CLA floating-point destination register for MADDF32 (MR0 to MR3)
MRd cannot be the same register as MRa
MRe CLA floating-point source register for MADDF32 (MR0 to MR3)
MRf CLA floating-point source register for MADDF32 (MR0 to MR3)

Opcode LSW: 0000 ffee ddcc bbaa

MSW: 0111 1010 0000 0000

Description Multiply the contents of two floating-point registers with parallel addition of two registers.
MRa = MRb * MRc;
MRd = MRe + MRf;

Restrictions The destination register for the MMPYF32 and the MADDF32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 or MADDF32 generates an underflow condition.
• LVF = 1 if MMPYF32 or MADDF32 generates an overflow condition.

Pipeline Both MMPYF32 and MADDF32 complete in a single cycle.

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Example ; Perform 5 multiply and accumulate operations:

;
; X and Y are 32-bit floating point arrays
;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3
;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X ; MAR0 points to X array
MMOVI16 MAR1, #_Y ; MAR1 points to Y array
MNOP ; Delay for MAR0, MAR1 load
MNOP ; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++ ; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y0, MAR1 += 2

MMPYF32 MR2, MR0, MR1 ; MR2 = A = X0 * Y0

|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X1, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y1, MAR1 += 2

MMPYF32 MR3, MR0, MR1 ; MR3 = B = X1 * Y1

|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X2, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y2, MAR2 += 2

MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2

|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y3

MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 * Y3

|| MMOV32 MR0, *MAR0 ; In parallel MR0 = X4
MMOV32 MR1, *MAR1 ; MR1 = Y4

MMPYF32 MR2, MR0, MR1 ; MR2 = E = X4 * Y4

|| MADDF32 MR3, MR3, MR2 ; in parallel MR3 = (A + B + C) + D

MADDF32 MR3, MR3, MR2 ; MR3 = (A + B + C + D) + E

MMOV32 @_Result, MR3 ; Store the result
MSTOP ; end of task

See also MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 32-Bit Floating-Point Multiply with Parallel Move

Operands
MRd CLA floating-point destination register for the MMPYF32 (MR0 to MR3)
MRd cannot be the same register as MRa
MRe CLA floating-point source register for the MMPYF32 (MR0 to MR3)
MRf CLA floating-point source register for the MMPYF32 (MR0 to MR3)
MRa CLA floating-point destination register for the MMOV32 (MR0 to MR3)
MRa cannot be the same register as MRd
mem32 32-bit memory location accessed using one of the available addressing modes. This
will be the source of the MMOV32.

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0000 ffee ddaa addr

Description Multiply the contents of two floating-point registers and load another.
MRd = MRe * MRf;
MRa = [mem32];

Restrictions The destination register for the MMPYF32 and the MMOV32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.
The MMOV32 Instruction will set the NF and ZF flags as follows:
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

Pipeline Both MMPYF32 and MMOV32 complete in a single cycle.

Example 1 ; Given M1, X1 and B1 are 32-bit floating point
; Calculate Y1 = M1*X1+B1
;
_Cla1Task1:
MMOV32 MR0, @M1 ; Load MR0 with M1
MMOV32 MR1, @X1 ; Load MR1 with X1
MMPYF32 MR1, MR1, MR0 ; Multiply M1*X1
|| MMOV32 MR0, @B1 ; and in parallel load MR0 with B1
MADDF32 MR1, MR1, MR0 ; Add M*X1 to B1 and store in MR1
MMOV32 @Y1, MR1 ; Store the result
MSTOP ; end of task

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Example 2 ; Given A, B and C are 32-bit floating-point numbers

; Calculate Y2 = (A * B)
; Y3 = (A * B) * C
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR1, MR1, MR0 ; Multiply A*B
|| MMOV32 MR0, @C ; and in parallel load MR0 with C
MMPYF32 MR1, MR1, MR0 ; Multiply (A*B) by C
|| MMOV32 @Y2, MR1 ; and in parallel store A*B
MMOV32 @Y3, MR1 ; Store the result
MSTOP ; end of task

See also MMPYF32 MRd, MRe, MRf || MMOV32 mem32, MRa

MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa 32-Bit Floating-Point Multiply with Parallel Move

Operands
MRd CLA floating-point destination register for the MMPYF32 (MR0 to MR3)
MRe CLA floating-point source register for the MMPYF32 (MR0 to MR3)
MRf CLA floating-point source register for the MMPYF32 (MR0 to MR3)
mem32 32-bit memory location accessed using one of the available addressing modes. This
will be the destination of the MMOV32.
MRa CLA floating-point source register for the MMOV32 (MR0 to MR3)

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0100 ffee ddaa addr

Description Multiply the contents of two floating-point registers and move from memory to register.
MRd = MRe * MRf;
[mem32] = MRa;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline MMPYF32 and MMOV32 both complete in a single cycle.

Example ; Given A, B and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A * B) * C
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR1, MR1, MR0 ; Multiply A*B
|| MMOV32 MR0, @C ; and in parallel load MR0 with C
MMPYF32 MR1, MR1, MR0 ; Multiply (A*B) by C
|| MMOV32 @Y2, MR1 ; and in parallel store A*B
MMOV32 @Y3, MR1 ; Store the result
MSTOP ; end of task

See also MMPYF32 MRd, MRe, MRf || MMOV32 MRa, mem32

MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf 32-Bit Floating-Point Multiply with Parallel
Subtract

Operands
MRa CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRa cannot be the same register as MRd
MRb CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRc CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRd CLA floating-point destination register for MSUBF32 (MR0 to MR3)
MRd cannot be the same register as MRa
MRe CLA floating-point source register for MSUBF32 (MR0 to MR3)
MRf CLA floating-point source register for MSUBF32 (MR0 to MR3)

Opcode LSW: 0000 ffee ddcc bbaa

MSW: 0111 1010 0100 0000

Description Multiply the contents of two floating-point registers with parallel subtraction of two
registers.
MRa = MRb * MRc;
MRd = MRe - MRf;

Restrictions The destination register for the MMPYF32 and the MSUBF32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 or MSUBF32 generates an underflow condition.
• LVF = 1 if MMPYF32 or MSUBF32 generates an overflow condition.

Pipeline MMPYF32 and MSUBF32 both complete in a single cycle.

Example ; Given A, B and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A - B)
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR2, MR0, MR1 ; Multiply (A*B)
|| MSUBF32 MR3, MR0, MR1 ; and in parallel Sub (A-B)
MMOV32 @Y2, MR2 ; Store A*B
MMOV32 @Y3, MR3 ; Store A-B
MSTOP ; end of task

See also MSUBF32 MRa, MRb, MRc

MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa

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MNEGF32 MRa, MRb{, CNDF} Conditional Negation

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)
CNDF condition tested

Opcode LSW: 0000 0000 cndf bbaa

MSW: 0111 1010 1000 0000

Description if (CNDF == true) {MRa = - MRb; }

else {MRa = MRb; }

CNDF is one of the following conditions:

(5)
Encode CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal to zero NF == 0
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to zero ZF == 1 OR NF == 1
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
(6)
1111 UNCF Unconditional with flag None
modification
(5)
Values not shown are reserved.
(6)
This is the default operation if no CNDF field is specified. This condition will allow the ZF, and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

Pipeline This is a single-cycle instruction.

Example 1
; Show the basic operation of MNEGF32
;
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMPYF32 MR3, MR1, MR2 ; MR3 = -6.0
MMPYF32 MR0, MR0, MR1 ; MR0 = 20.0
MMOVIZ MR1, #0.0
MCMPF32 MR3, MR1 ; NF = 1
MNEGF32 MR3, MR3, LT ; if NF = 1, MR3 = 6.0
MCMPF32 MR0, MR1 ; NF = 0
MNEGF32 MR0, MR0, GEQ ; if NF = 0, MR0 = -20.0

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Example 2 ; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den

; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den ; MR1 = Den
MEINVF32 MR2, MR1 ; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num ; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den ; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ ; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0 ; Store result
MSTOP ; end of task

See also MABSF32 MRa, MRb

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MNOP No Operation

Operands
none This instruction does not have any operands

Opcode LSW: 0000 0000 0000 0000

MSW: 0111 1111 1010 0000

Description Do nothing. This instruction is used to fill required pipeline delay slots when other
instructions are not available to fill the slots.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example ; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store it in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP ; Too late to affect MBCNDD
MNOP ; Too late to affect MBCNDD
MNOP ; Too late to affect MBCNDD
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Pad to seperate MBCNDD and MSTOP
MNOP ; Pad to seperate MBCNDD and MSTOP
MSTOP ; End of task

See also

1040 Control Law Accelerator (CLA) SPRUII0B – May 2019 – Revised May 2020
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MOR32 MRa, MRb, MRc Bitwise OR

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 00cc bbaa

MSW: 0111 1100 1000 0000

Description Bitwise OR of MRb with MRc.

MARa(31:0) = MARb(31:0) OR MRc(31:0);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x5555 ; MR0 = 0x5555AAAA
MMOVXI MR0, #0xAAAA

MMOVIZ MR1, #0x5432 ; MR1 = 0x5432FEDC

MMOVXI MR1, #0xFEDC

; 0101 OR 0101 = 0101 (5)

; 0101 OR 0100 = 0101 (5)
; 0101 OR 0011 = 0111 (7)
; 0101 OR 0010 = 0111 (7)
; 1010 OR 1111 = 1111 (F)
; 1010 OR 1110 = 1110 (E)
; 1010 OR 1101 = 1111 (F)
; 1010 OR 1100 = 1110 (E)
MOR32 MR2, MR1, MR0 ; MR3 = 0x5555FEFE

See also MAND32 MRa, MRb, MRc

MXOR32 MRa, MRb, MRc

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MRCNDD {CNDF} Return Conditional Delayed

Operands
CNDF optional condition.

Opcode LSW: 0000 0000 0000 0000

MSW: 0111 1001 1010 cndf

Description If the specified condition is true, then the RPC field of MSTF is loaded into MPC and
fetching continues from that location. Otherwise program fetches will continue without
the return.
Please refer to the pipeline section for important information regarding this instruction.
if (CNDF == TRUE) MPC = RPC;

CNDF is one of the following conditions:

(7)
Encode CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal to zero NF == 0
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to zero ZF == 1 OR NF == 1
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
(8)
1111 UNCF Unconditional with flag None
modification
(7)
Values not shown are reserved.
(8)
This is the default operation if no CNDF field is specified. This condition will allow the ZF and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

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Pipeline The MRCNDD instruction by itself is a single-cycle instruction. As shown in Table 8-20,
for each return 6 instruction slots are executed; three before the return instruction (d5-
d7) and three after the return instruction (d8-d10). The total number of cycles for a return
taken or not taken depends on the usage of these slots. That is, the number of cycles
depends on how many slots are filled with a MNOP as well as which slots are filled. The
effective number of cycles for a return can, therefore, range from 1 to 7 cycles. The
number of cycles for a return taken may not be the same as for a return not taken.
Referring to the following code fragment and the pipeline diagrams in Table 8-20 and
Table 8-21, the instructions before and after MRCNDD have the following properties:

;
;
<Instruction 1> ; I1 Last instruction that can affect flags for
; the MCCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return

MCCNDD _func, NEQ ; Call to func if not eqal to zero

; Three instructions after MCCNDD are always
; executed whether the call is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8 The address of this instruction is saved
; in the RPC field of the MSTF register.
; Upon return this value is loaded into MPC
; and fetching continues from this point.
<Instruction 9> ; I9
<Instruction 10> ; I10
....
....
_func:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
<Destination 4> ; d4 Last instruction that can affect flags for
; the MRCNDD operation
<Destination 5> ; d5 Cannot be stop, branch, call or return
<Destination 6> ; d6 Cannot be stop, branch, call or return
<Destination 7> ; d7 Cannot be stop, branch, call or return

MRCNDD NEQ ; Return to <Instruction 8> if not equal to zero

; Three instructions after MRCNDD are always
; executed whether the return is taken or not
<Destination 8> ; d8 Cannot be stop, branch, call or return
<Destination 9> ; d9 Cannot be stop, branch, call or return
<Destination 10> ; d10 Cannot be stop, branch, call or return
<Destination 11> ; d11
<Destination 12> ; d12
....
....
MSTOP
....
• d4
– d4 is the last instruction that can effect the CNDF flags for the MRCNDD
instruction. The CNDF flags are tested in the D2 phase of the pipeline. That is, a
decision is made whether to return or not when MRCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for d4.
• d5, d6 and d7
– The three instructions proceeding MRCNDD can change MSTF flags but will have
no effect on whether the MRCNDD instruction makes the return or not. This is
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because the flag modification will occur after the D2 phase of the MRCNDD
instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP,
MBCNDD, MCCNDD or MRCNDD.
• d8, d9 and d10
– The three instructions following MRCNDD are always executed irrespective of
whether the return is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP,
MBCNDD, MCCNDD or MRCNDD.

Table 8-20. Pipeline Activity For MRCNDD, Return Not Taken

Instruction F1 F2 D1 D2 R1 R2 E W
d4 d4 d3 d2 d1 I7 I6 I5
d5 d5 d4 d3 d2 d1 I7 I6
d6 d6 d5 d4 d3 d2 d1 i7
d7 d7 d6 d5 d4 d3 d2 d1
MRCNDD MRCNDD d7 d6 d5 d4 d3 d2
d8 d8 MRCNDD d7 d6 d5 d4 d3
d9 d9 d8 MRCNDD d7 d6 d5 d4
d10 d10 d9 d8 MRCNDD d7 d6 d5
d11 d11 d10 d9 d8 - d7 d6
d12 d12 d11 d10 d9 d8 - d7
etc.... .... d12 d11 d10 d9 d8 -
.... .... .... d12 d11 d10 d9 d8
.... .... .... .... d12 d11 d10 d9
d12 d11 d10
d12 d11
d12

Table 8-21. Pipeline Activity For MRCNDD, Return Taken

Instruction F1 F2 D1 D2 R1 R2 E W
d4 d4 d3 d2 d1 I7 I6 I5
d5 d5 d4 d3 d2 d1 I7 I6
d6 d6 d5 d4 d3 d2 d1 i7
d7 d7 d6 d5 d4 d3 d2 d1
MRCNDD MRCNDD d7 d6 d5 d4 d3 d2
d8 d8 MRCNDD d7 d6 d5 d4 d3
d9 d9 d8 MRCNDD d7 d6 d5 d4
d10 d10 d9 d8 MRCNDD d7 d6 d5
I8 I8 d10 d9 d8 - d7 d6
I9 I9 I8 d10 d9 d8 - d7
I10 I10 I9 I8 d10 d9 d8 -
etc.... .... I10 I9 I8 d10 d9 d8
.... .... I10 I9 I8 d10 d9
.... .... I10 I9 I8 d10
I10 I9 I8
I10 I9
I10

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Example ;

See also MBCNDD #16BitDest, CNDF

MCCNDD 16BitDest, CNDF
MMOV32 mem32, MSTF
MMOV32 MSTF, mem32

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MSETC BGINTM Set Background Task Interrupt Mask

Operands
none This instruction does not have any operands

Opcode LSW: 0000 0000 0000 0000

MSW: 0111 1111 0101 0000

Description This instruction will set the background task interrupt mask (BGINTM) bit in the
MSTSBGRND register, making any code thereafter un-interruptible. No other higher
priority task will be able to interrupt the background task until the BGINTM is cleared.
This instruction sets the BGINTM bit at the end of its D2 phase.
Note: This instruction does not require the MEALLOW bit to be asserted before, or de-
asserted after, setting BGINTM.

Flags This instruction does not modify the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example MSETC BGINTM ; Set the MSTSBGRND.BGINTM bit
; to prevent any other tasks from
; interrupting the background task

See also MCLRC BGINTM

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MSETFLG FLAG, VALUE Set or Clear Selected Floating-Point Status Flags

Operands
FLAG 8 bit mask indicating which floating-point status flags to change.
VALUE 8 bit mask indicating the flag value; 0 or 1.

Opcode LSW: FFFF FFFF VVVV VVVV

MSW: 0111 1001 1100 0000

Description The MSETFLG instruction is used to set or clear selected floating-point status flags in
the MSTF register. The FLAG field is an 11-bit value that indicates which flags will be
changed. That is, if a FLAG bit is set to 1 it indicates that flag will be changed; all other
flags will not be modified. The bit mapping of the FLAG field is shown below:
RNDF3 reserve reserve TF reserve reserved ZF NF LUF LVF
2 d d d

9 8 7 6 5 4 3 2 1 0

The VALUE field indicates the value the flag should be set to; 0 or 1.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified Yes Yes Yes Yes Yes

Any flag can be modified by this instruction. The MEALLOW and RPC fields cannot be
modified with this instruction.

Pipeline This is a single-cycle instruction.

Example To make it easier and legible, the assembler accepts a FLAG=VALUE syntax for the
MSTFLG operation as shown below:
MSETFLG RNDF32=0, TF=0, NF=1; FLAG = 11000100; VALUE = 00XXX1XX;

See also MMOV32 mem32, MSTF

MMOV32 MSTF, mem32

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MSTOP Stop Task

Operands
none This instruction does not have any operands

Opcode LSW: 0000 0000 0000 0000

MSW: 0111 1111 1000 0000

Description The MSTOP instruction must be placed to indicate the end of each task. In addition,
placing MSTOP in unused memory locations within the CLA program RAM can be useful
for debugging and preventing run away CLA code. When MSTOP enters the D2 phase
of the pipeline, the MIRUN flag for the task is cleared and the associated interrupt is
flagged in the PIE vector table.
There are three special cases that can occur when single-stepping a task such that the
MPC reaches the MSTOP instruction.
1. If you are single-stepping or halted in "task A" and "task B" comes in before the MPC
reaches the MSTOP, then "task B" will start if you continue to step through the
MSTOP instruction. Basically if "task B" is pending before the MPC reaches MSTOP
in "task A" then there is no issue in "task B" starting and no special action is required.
2. In this case you have single-stepped or halted in "task A" and the MPC has reached
the MSTOP with no tasks pending. If "task B" comes in at this point, it will be flagged
in the MIFR register but it may or may not start if you continue to single-step through
the MSTOP instruction of "task A". It depends on exactly when the new task comes
in. To reliably start "task B" perform a soft reset and reconfigure the MIER bits. Once
this is done, you can start single-stepping "task B".
3. Case 2 can be handled slightly differently if there is control over when "task B" comes
in (for example using the IACK instruction to start the task). In this case you have
single-stepped or halted in "task A" and the MPC has reached the MSTOP with no
tasks pending. Before forcing "task B", run free to force the CLA out of the debug
state. Once this is done you can force "task B" and continue debugging.

Restrictions The MSTOP instruction cannot be placed 3 instructions before or after a MBCNDD,
MCCNDD or MRCNDD instruction.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction. Table 8-22 shows the pipeline behavior of the MSTOP
instruction. The MSTOP instruction cannot be placed with 3 instructions of a MBCNDD,
MCCNDD or MRCNDD instruction.

1048Control Law Accelerator (CLA) SPRUII0B – May 2019 – Revised May 2020
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Table 8-22. Pipeline Activity For MSTOP

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
MSTOP MSTOP I3 I2 I1
I4 I4 MSTOP I3 I2 I1
I5 I5 I4 MSTOP I3 I2 I1
I6 I6 I5 I4 MSTOP I3 I2 I1
New Task Arbitrated and Piroitized - - - - - I3 I2
New Task Arbitrated and Piroitized - - - - - - I3
I1 I1 - - - - - -
I2 I2 I1 - - - - -
I3 I3 I2 I1 - - - -
I4 I4 I3 I2 I1 - - -
I5 I5 I4 I3 I2 I1 - -
I6 I6 I5 I4 I3 I2 I1 -
I7 I7 I6 I5 I4 I3 I2 I1
etc ....

Example ; Given A = (int32)1

; B = (int32)2
; C = (int32)-7
;
; Calculate Y2 = A - B - C
_Cla1Task3:
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MSUB32 MR3, MR0, MR1 ; A + B
MSUB32 MR3, MR3, MR2 ; A + B + C = 6 (0x0000006)
MMOV32 @_y2, MR3 ; Store y2
MSTOP ; End of task

See also MDEBUGSTOP , MDEBUGSTOP1

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MSUB32 MRa, MRb, MRc 32-Bit Integer Subtraction

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point destination register (MR0 to MR3)
MRc CLA floating-point destination register (MR0 to MR3)

Opcode LSW: 0000 0000 00cc bbaa

MSW: 0111 1100 1110 0000

Description 32-bit integer addition of MRb and MRc.

MARa(31:0) = MARb(31:0) - MRc(31:0);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example ; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
;
Calculate Y2 = A - B - C
;
_Cla1Task3:
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MSUB32 MR3, MR0, MR1 ; A + B
MSUB32 MR3, MR3, MR2 ; A + B + C = 6 (0x0000006)
MMOV32 @_y2, MR3 ; Store y2
MSTOP ; End of task

See also MADD32 MRa, MRb, MRc

MAND32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc

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MSUBF32 MRa, MRb, MRc 32-Bit Floating-Point Subtraction

Operands
MRa CLA floating-point destination register (MR0 to R1)
MRb CLA floating-point source register (MR0 to R1)
MRc CLA floating-point source register (MR0 to R1)

Opcode LSW: 0000 0000 00cc bbaa

MSW: 0111 1100 0100 0000

Description Subtract the contents of two floating-point registers

MRa = MRb - MRc;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.

Pipeline This is a single-cycle instruction.

Example
; Given A, B and C are 32-bit floating-point numbers
; Calculate Y2 = A + B - C
;
_Cla1Task5:
MMOV32 MR0, @_A ; Load MR0 with A
MMOV32 MR1, @_B ; Load MR1 with B
MADDF32 MR0, MR1, MR0 ; Add A + B
|| MMOV32 MR1, @_C ; and in parallel load C
MSUBF32 MR0, MR0, MR1 ; Subtract C from (A + B)
MMOV32 @Y, MR0 ; (A+B) - C
MSTOP ; end of task

See also MSUBF32 MRa, #16FHi, MRb

MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSUBF32 MRa, #16FHi, MRb 32-Bit Floating-Point Subtraction

Operands
MRa CLA floating-point destination register (MR0 to R1)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-
point value. The low 16-bits of the mantissa are assumed to be all 0.
MRb CLA floating-point source register (MR0 to R1)

Opcode LSW: IIII IIII IIII IIII

MSW: 0111 1000 0000 baaa

Description Subtract MRb from the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler will accept either a hex or float as the immediate value.
That is, the value -1.5 can be represented as #-1.5 or #0xBFC0.
MRa = #16FHi:0 - MRb;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.

Pipeline This is a single-cycle instruction.

Example ; Y = sqrt(X)
; Ye = Estimate(1/sqrt(X));
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Y = X*Ye
;
_Cla1Task3:
MMOV32 MR0, @_x ; MR0 = X
MEISQRTF32 MR1, MR0 ; MR1 = Ye = Estimate(1/sqrt(X))
MMOV32 MR1, @_x, EQ ; if(X == 0.0) Ye = 0.0
MMPYF32 MR3, MR0, #0.5 ; MR3 = X*0.5
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR0, MR1, MR0 ; MR0 = Y = Ye*X
MMOV32 @_y, MR0 ; Store Y = sqrt(X)
MSTOP ; end of task

See also MSUBF32 MRa, MRb, MRc

MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 32-Bit Floating-Point Subtraction with Parallel
Move

Operands
MRd CLA floating-point destination register (MR0 to MR3) for the MSUBF32 operation
MRd cannot be the same register as MRa
MRe CLA floating-point source register (MR0 to MR3) for the MSUBF32 operation
MRf CLA floating-point source register (MR0 to MR3) for the MSUBF32 operation
MRa CLA floating-point destination register (MR0 to MR3) for the MMOV32 operation
MRa cannot be the same register as MRd
mem32 32-bit memory location accessed using one of the available addressing modes. Source
for the MMOV32 operation.

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0010 ffee ddaa addr

Description Subtract the contents of two floating-point registers and move from memory to a floating-
point register.
MRd = MRe - MRf;
MRa = [mem32];

Restrictions The destination register for the MSUBF32 and the MMOV32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.
The MMOV32 Instruction will set the NF and ZF flags as follows:

Pipeline Both MSUBF32 and MMOV32 complete in a single cycle.

Example NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

See also MSUBF32 MRa, MRb, MRc

MSUBF32 MRa, #16FHi, MRb
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa 32-Bit Floating-Point Subtraction with Parallel
Move

Operands
MRd CLA floating-point destination register (MR0 to MR3) for the MSUBF32 operation
MRe CLA floating-point source register (MR0 to MR3) for the MSUBF32 operation
MRf CLA floating-point source register (MR0 to MR3) for the MSUBF32 operation
mem32 32-bit destination memory location for the MMOV32 operation
MRa CLA floating-point source register (MR0 to MR3) for the MMOV32 operation

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0110 ffee ddaa addr

Description Subtract the contents of two floating-point registers and move from a floating-point
register to memory.
MRd = MRe - MRf;
[mem32] = MRa;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.

Pipeline Both MSUBF32 and MMOV32 complete in a single cycle.

Example
See also MSUBF32 MRa, MRb, MRc
MSUBF32 MRa, #16FHi, MRb
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

1054 Control Law Accelerator (CLA) SPRUII0B – May 2019 – Revised May 2020
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MSWAPF MRa, MRb {, CNDF} Conditional Swap

Operands
MRa CLA floating-point register (MR0 to MR3)
MRb CLA floating-point register (MR0 to MR3)
CNDF Optional condition tested based on the MSTF flags

Opcode LSW: 0000 0000 CNDF bbaa

MSW: 0111 1011 0000 0000

Description Conditional swap of MRa and MRb.

if (CNDF == true) swap MRa and MRb;

CNDF is one of the following conditions:

(1)
Encode CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal to zero NF == 0
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to zero ZF == 1 OR NF == 1
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
(2)
1111 UNCF Unconditional with flag None
modification
(1)
Values not shown are reserved.
(2)
This is the default operation if no CNDF field is specified. This condition will allow the ZF and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

No flags affected

Pipeline This is a single-cycle instruction.

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Example ; X is an array of 32-bit floating-point values

; and has len elements. Find the maximum value in
; the array and store it in Result
;
; Note: MCMPF32 and MSWAPF can be replaced by MMAXF32
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MCMPF32 MR2, MR1 ; Compare MR2 with MR1
MSWAPF MR1, MR2, GT ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

See also

1056 Control Law Accelerator (CLA) SPRUII0B – May 2019 – Revised May 2020
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MTESTTF CNDF Test MSTF Register Flag Condition

Operands
CNDF condition to test based on MSTF flags

Opcode LSW: 0000 0000 0000 cndf

MSW: 0111 1111 0100 0000

Description Test the CLA floating-point condition and if true, set the MSTF[TF] flag. If the condition is
false, clear the MSTF[TF] flag. This is useful for temporarily storing a condition for later
use.
if (CNDF == true) TF = 1;
else TF = 0;

CNDF is one of the following conditions:

(3)
Encode CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal to zero NF == 0
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to zero ZF == 1 OR NF == 1
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
(4)
1111 UNCF Unconditional with flag None
modification
(3)
Values not shown are reserved.
(4)
This is the default operation if no CNDF field is specified. This condition will allow the ZF and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified Yes No No No No

TF = 0;
if (CNDF == true) TF = 1;

Note: If (CNDF == UNC or UNCF), the TF flag will be set to 1.

Pipeline This is a single-cycle instruction.

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Example ; if (State == 0.1)

; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task2:
MMOV32 MR0, @_State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MCMPF32 MR0, #0.01 ; Check used by 2nd MBCNDD (B)
MTESTTF EQ ; Store EQ flag in TF for 2nd MBCNDD (B)
MNOP
MBCNDD _Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MMOV32 MR1, @_RampState ; Always executed
MMOVXI MR2, #RAMPMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @_RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken

_Skip1:
MMOV32 MR3, @_SteadyState
MMOVXI MR2, #STEADYMASK
MOR32 MR3, MR2
MBCNDD _Skip2, NTF ; (B) if State != .01, go to Skip2
MMOV32 MR1, @_CoastState ; Always executed
MMOVXI MR2, #COASTMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @_CoastState, MR1 ; Execute if (B) branch not taken
MSTOP ; end of task if (B) branch not taken

_Skip2:
MMOV32 @_SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

See also

1058 Control Law Accelerator (CLA) SPRUII0B – May 2019 – Revised May 2020
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MUI16TOF32 MRa, mem16 Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value

Operands
MRa CLA floating-point destination register (MR0 to MR3)
mem16 16-bit source memory location

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0111 0101 01aa addr

Description When converting F32 to I16/UI16 data format, the MF32TOI16/UI16 operation truncates
to zero while the MF32TOI16R/UI16R operation will round to nearest (even) value.
MRa = UI16TOF32[mem16];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
See also MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MUI16TOF32 MRa, MRb Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1110 1110 0000

Description Convert an unsigned 16-bit integer to a 32-bit floating-point value. When converting
float32 to I16/UI16 data format, the MF32TOI16/UI16 operation truncates to zero while
the MF32TOI16R/UI16R operation will round to nearest (even) value.
MRa = UI16TOF32[MRb];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example MMOVXI MR1, #0x800F ; MR1(15:0) = 32783 (0x800F)
MUI16TOF32 MR0, MR1 ; MR0 = UI16TOF32 (MR1(15:0))
; = 32783.0 (0x47000F00)

See also MF32TOI16 MRa, MRb

MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16

1060 Control Law Accelerator (CLA) SPRUII0B – May 2019 – Revised May 2020
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MUI32TOF32 MRa, mem32 Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value

Operands
MRa CLA floating-point destination register (MR0 to MR3)
mem32 32-bit memory location accessed using one of the available addressing modes

Opcode LSW: mmmm mmmm mmmm mmmm

MSW: 0111 0100 10aa addr

Description MRa = UI32TOF32[mem32];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example ; Given x2, m2 and b2 are Uint32 numbers:
;
; x2 = Uint32(2) = 0x00000002
; m2 = Uint32(1) = 0x00000001
; b2 = Uint32(3) = 0x00000003
;
; Calculate y2 = x2 * m2 + b2
;
_Cla1Task1:
MUI32TOF32 MR0, @_m2 ; MR0 = 1.0 (0x3F800000)
MUI32TOF32 MR1, @_x2 ; MR1 = 2.0 (0x40000000)
MUI32TOF32 MR2, @_b2 ; MR2 = 3.0 (0x40400000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR3, MR2, MR3 ; Y=MX+B = 5.0 (0x40A00000)
MF32TOUI32 MR3, MR3 ; Y = Uint32(5.0) = 0x00000005
MMOV32 @_y2, MR3 ; store result
MSTOP ; end of task

See also MF32TOI32 MRa, MRb

MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, MRb

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MUI32TOF32 MRa, MRb Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 0000 bbaa

MSW: 0111 1101 1100 0000

Description MRa = UI32TOF32 [MRb];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example MMOVIZ MR3, #0x8000 ; MR3(31:16) = 0x8000
MMOVXI MR3, #0x1111 ; MR3(15:0) = 0x1111
; MR3 = 2147488017
MUI32TOF32 MR3, MR3 ; MR3 = MUI32TOF32 (MR3) = 2147488017.0 (0x4F000011)

See also MF32TOI32 MRa, MRb

MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MXOR32 MRa, MRb, MRc Bitwise Exclusive Or

Operands
MRa CLA floating-point destination register (MR0 to MR3)
MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode LSW: 0000 0000 00cc bbaa

MSW: 0111 1100 1010 0000

Description Bitwise XOR of MRb with MRc.

MARa(31:0) = MARb(31:0) XOR MRc(31:0);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example MMOVIZ MR0, #0x5555 ; MR0 = 0x5555AAAA
MMOVXI MR0, #0xAAAA

MMOVIZ MR1, #0x5432 ; MR1 = 0x5432FEDC

MMOVXI MR1, #0xFEDC

; 0101 XOR 0101 = 0000 (0)

; 0101 XOR 0100 = 0001 (1)
; 0101 XOR 0011 = 0110 (6)
; 0101 XOR 0010 = 0111 (7)
; 1010 XOR 1111 = 0101 (5)
; 1010 XOR 1110 = 0100 (4)
; 1010 XOR 1101 = 0111 (7)
; 1010 XOR 1100 = 0110 (6)

MXOR32 MR2, MR1, MR0 ; MR3 = 0x01675476

See also MAND32 MRa, MRb, MRc

MOR32 MRa, MRb, MRc

8.8 CLA Registers

This section describes the Control Law Accelerator registers.

8.8.1 CLA Base Addresses

Table 8-23. CLA Base Address Table (C28 and CLA)

Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU2 DMA CLA
Instance Structure Protected

Cla1Regs CLA_REGS CLA1_BASE 0x0000_1400 YES YES - - -

Cla1SoftIntRegs CLA_SOFTINT_REGS CLASOFTINT_BASE 0x0000_0CE0 - - - YES -
Cla1OnlyRegs CLA_ONLY_REGS CLAONLY_BASE 0x0000_0C00 - - - YES -

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8.8.2 CLA_ONLY_REGS Registers

Table 8-24 lists the CLA_ONLY_REGS registers. All register offset addresses not listed in Table 8-24
should be considered as reserved locations and the register contents should not be modified.

Table 8-24. CLA_ONLY_REGS Registers

Offset Acronym Register Name Write Protection Section
80h _MVECTBGRNDACTIVE Active register for MVECTBGRND. EALLOW Go
C0h _MPSACTL CLA PSA Control Register EALLOW Go
C2h _MPSA1 CLA PSA1 Register EALLOW Go
C4h _MPSA2 CLA PSA2 Register EALLOW Go
E0h SOFTINTEN CLA Software Interrupt Enable Register Go
E2h SOFTINTFRC CLA Software Interrupt Force Register Go

Complex bit access types are encoded to fit into small table cells. Table 8-25 shows the codes that are
used for access types in this section.

Table 8-25. CLA_ONLY_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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8.8.2.1 _MVECTBGRNDACTIVE Register (Offset = 80h) [reset = 0h]

_MVECTBGRNDACTIVE is shown in Figure 8-2 and described in Table 8-26.
Return to the Summary Table.
Gives the current interrupted MPC value of the background task, if the background task was running and
interrupted, or reflects the MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.

Figure 8-2. _MVECTBGRNDACTIVE Register

15 14 13 12 11 10 9 8
i16
R-0h
7 6 5 4 3 2 1 0
i16
R-0h

Table 8-26. _MVECTBGRNDACTIVE Register Field Descriptions

Bit Field Type Reset Description
15-0 i16 R 0h Gives the current interrupted MPC value of the background task, if
the background task was running and interrupted, or reflects the
MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.
Reset type: SYSRSn

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8.8.2.2 _MPSACTL Register (Offset = C0h) [reset = 0h]

_MPSACTL is shown in Figure 8-3 and described in Table 8-27.
Return to the Summary Table.
PSA Control Register

Figure 8-3. _MPSACTL Register

15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
MPSA2CFG MPSA2CLEAR MPSA1CLEAR MDWDBCYC MDWDBSTAR MPABCYC MPABSTART
T
R/W-0h R-0/W1S-0h R-0/W1S-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-27. _MPSACTL Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7-6 MPSA2CFG R/W 0h CLA PSA2 Polynomial Configuration Bits: These bits configure the
type of polynomial used for PSA2. The polynomials chosen are
commonly used in the industry:
Mode Polynomial Type
0,0 PSA
0,1 CRC32
1,0 CRC16
1,1 CRC16-CCITT
Note: [1] Polynomial configuration should be performed when PSA2
is stopped.
Reset type: SYSRSn
5 MPSA2CLEAR R-0/W1S 0h CLA PSA2 Clear Bit:
Writing of "1" will clear contents of PSA2 register.
Writes of "0" are ignored.
Always reads back a "0"
Note: Clearing operation should be performed when PSA2 is
stopped.
Reset type: SYSRSn
4 MPSA1CLEAR R-0/W1S 0h CLA PSA1 Clear Bit:
Writing of "1" will clear contents of PSA1 register.
Writes of "0" are ignored.
Always reads back a "0"
Note: Clearing operation should be performed when PSA1 is
stopped.
Reset type: SYSRSn
3 MDWDBCYC R/W 0h CLA Data Write Data Bus PSA2 Cycle or Event Based Bit:
0 PSA2 calculated on every cycle
1 PSA2 calculated on every bus event
Reset type: SYSRSn
2 MDWDBSTART R/W 0h CLA Data Write Data Bus PSA2 Start/Stop Bit:
0 PSA2 stopped
1 PSA2 start
Reset type: SYSRSn
1 MPABCYC R/W 0h CLA Program Address Bus PSA1 Cycle/Event Based Bit:
0 PSA1 calculated on every cycle
1 PSA1 calculated on every bus event
Reset type: SYSRSn
0 MPABSTART R/W 0h CLA Program Address Bus PSA1 Start/Stop Bit:
0 PSA1 stopped
1 PSA1 start
Reset type: SYSRSn

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8.8.2.3 _MPSA1 Register (Offset = C2h) [reset = 0h]

_MPSA1 is shown in Figure 8-4 and described in Table 8-28.
Return to the Summary Table.
PSA1 Register

Figure 8-4. _MPSA1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R/W-0h

Table 8-28. _MPSA1 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R/W 0h PSA1 Value: Reading this register gives the current PSA1 value.
The value can be read at any time.
Writes to this register are allowed to initialize the PSA1 to a known
value. Writes to this register should only be made when PSA1 is
stopped.
Register value is cleared to zero by reset or by writing to the
MPSA1CLEAR bit in the MPSACTL register.
Reset type: SYSRSn

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8.8.2.4 _MPSA2 Register (Offset = C4h) [reset = 0h]

_MPSA2 is shown in Figure 8-5 and described in Table 8-29.
Return to the Summary Table.
PSA2 Register

Figure 8-5. _MPSA2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R/W-0h

Table 8-29. _MPSA2 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R/W 0h PSA2 Value: Reading this register gives the current PSA2 value.
The value can be read at any time.
Writes to this register are allowed to initialize the PSA2 to a known
value. Writes to this register should only be made when PSA2 is
stopped.
Register value is cleared to zero by reset or by writing to the
MPSA2CLEAR bit in the MPSACTL register.
Reset type: SYSRSn

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8.8.2.5 SOFTINTEN Register (Offset = E0h) [reset = 0h]

SOFTINTEN is shown in Figure 8-6 and described in Table 8-30.
Return to the Summary Table.
Enables the ability to generate CLA task interrupt from within the task, by writing to SOFTINTFRC register.
SOFTINTFRC register can only be written from CLA.

Figure 8-6. SOFTINTEN Register

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-30. SOFTINTEN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
6 TASK7 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
5 TASK6 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
4 TASK5 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
3 TASK4 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
2 TASK3 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
1 TASK2 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
0 TASK1 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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8.8.2.6 SOFTINTFRC Register (Offset = E2h) [reset = 0h]

SOFTINTFRC is shown in Figure 8-7 and described in Table 8-31.
Return to the Summary Table.
Writing a value of 1 in a bit will generate the corresponding task interrupt.

Figure 8-7. SOFTINTFRC Register

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 8-31. SOFTINTFRC Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
6 TASK7 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
5 TASK6 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
4 TASK5 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
3 TASK4 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
2 TASK3 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
1 TASK2 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
0 TASK1 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn

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8.8.3 CLA_REGS Registers

Table 8-32 lists the CLA_REGS registers. All register offset addresses not listed in Table 8-32 should be
considered as reserved locations and the register contents should not be modified.

Table 8-32. CLA_REGS Registers

Offset Acronym Register Name Write Protection Section
0h MVECT1 Task Interrupt Vector EALLOW Go
1h MVECT2 Task Interrupt Vector EALLOW Go
2h MVECT3 Task Interrupt Vector EALLOW Go
3h MVECT4 Task Interrupt Vector EALLOW Go
4h MVECT5 Task Interrupt Vector EALLOW Go
5h MVECT6 Task Interrupt Vector EALLOW Go
6h MVECT7 Task Interrupt Vector EALLOW Go
7h MVECT8 Task Interrupt Vector EALLOW Go
10h MCTL Control Register EALLOW Go
1Bh _MVECTBGRNDACTIVE Active register for MVECTBGRND. EALLOW Go
1Ch SOFTINTEN CLA Software Interrupt Enable Register Go
1Dh _MSTSBGRND Status register for the back ground task. EALLOW Go
1Eh _MCTLBGRND Control register for the back ground task. EALLOW Go
1Fh _MVECTBGRND Vector for the back ground task. EALLOW Go
20h MIFR Interrupt Flag Register EALLOW Go
21h MIOVF Interrupt Overflow Flag Register EALLOW Go
22h MIFRC Interrupt Force Register EALLOW Go
23h MICLR Interrupt Flag Clear Register EALLOW Go
24h MICLROVF Interrupt Overflow Flag Clear Register EALLOW Go
25h MIER Interrupt Enable Register EALLOW Go
26h MIRUN Interrupt Run Status Register EALLOW Go
28h _MPC CLA Program Counter Go
2Ah _MAR0 CLA Auxiliary Register 0 Go
2Bh _MAR1 CLA Auxiliary Register 1 Go
2Eh _MSTF CLA Floating-Point Status Register Go
30h _MR0 CLA Floating-Point Result Register 0 Go
34h _MR1 CLA Floating-Point Result Register 1 Go
38h _MR2 CLA Floating-Point Result Register 2 Go
3Ch _MR3 CLA Floating-Point Result Register 3 Go
42h _MPSACTL CLA PSA Control Register EALLOW Go
44h _MPSA1 CLA PSA1 Register EALLOW Go
46h _MPSA2 CLA PSA2 Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 8-33 shows the codes that are
used for access types in this section.

Table 8-33. CLA_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write

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Table 8-33. CLA_REGS Access Type

Codes (continued)
Access Type Code Description
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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8.8.3.1 MVECT1 Register (Offset = 0h) [reset = 0h]

MVECT1 is shown in Figure 8-8 and described in Table 8-34.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .

Figure 8-8. MVECT1 Register

15 14 13 12 11 10 9 8
MVECT
R/W-0h
7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-34. MVECT1 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.3.2 MVECT2 Register (Offset = 1h) [reset = 0h]

MVECT2 is shown in Figure 8-9 and described in Table 8-35.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .

Figure 8-9. MVECT2 Register

15 14 13 12 11 10 9 8
MVECT
R/W-0h
7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-35. MVECT2 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.3.3 MVECT3 Register (Offset = 2h) [reset = 0h]

MVECT3 is shown in Figure 8-10 and described in Table 8-36.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .

Figure 8-10. MVECT3 Register

15 14 13 12 11 10 9 8
MVECT
R/W-0h
7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-36. MVECT3 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.3.4 MVECT4 Register (Offset = 3h) [reset = 0h]

MVECT4 is shown in Figure 8-11 and described in Table 8-37.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .

Figure 8-11. MVECT4 Register

15 14 13 12 11 10 9 8
MVECT
R/W-0h
7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-37. MVECT4 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.3.5 MVECT5 Register (Offset = 4h) [reset = 0h]

MVECT5 is shown in Figure 8-12 and described in Table 8-38.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .

Figure 8-12. MVECT5 Register

15 14 13 12 11 10 9 8
MVECT
R/W-0h
7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-38. MVECT5 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.3.6 MVECT6 Register (Offset = 5h) [reset = 0h]

MVECT6 is shown in Figure 8-13 and described in Table 8-39.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .

Figure 8-13. MVECT6 Register

15 14 13 12 11 10 9 8
MVECT
R/W-0h
7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-39. MVECT6 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.3.7 MVECT7 Register (Offset = 6h) [reset = 0h]

MVECT7 is shown in Figure 8-14 and described in Table 8-40.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .

Figure 8-14. MVECT7 Register

15 14 13 12 11 10 9 8
MVECT
R/W-0h
7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-40. MVECT7 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.3.8 MVECT8 Register (Offset = 7h) [reset = 0h]

MVECT8 is shown in Figure 8-15 and described in Table 8-41.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .

Figure 8-15. MVECT8 Register

15 14 13 12 11 10 9 8
MVECT
R/W-0h
7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-41. MVECT8 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.3.9 MCTL Register (Offset = 10h) [reset = 0h]

MCTL is shown in Figure 8-16 and described in Table 8-42.
Return to the Summary Table.
Control Register

Figure 8-16. MCTL Register

15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED IACKE SOFTRESET HARDRESET
R-0h R/W-0h R-0/W1S-0h R-0/W1S-0h

Table 8-42. MCTL Register Field Descriptions

Bit Field Type Reset Description
15-3 RESERVED R 0h Reserved
2 IACKE R/W 0h IACK Operation Enable Bit: Writing a "1" to this bit will enable the
IACK operation for setting the MIFR bits in the same manner as the
MIFRC register (write of "1" will set respective MIFR bit). At reset,
this feature is disabled.
This feature enables the C28 CPU to efficiently trigger a task.
Note: IACK operation should ignore EALLOW status of C28 core
when accessing the MIFRC register.
Reset type: SYSRSn
0h (R/W) = The CLA ignores the IACK instruction. (default)
1h (R/W) = Enable the main CPU to use the IACK #16bit instruction
to set MIFR bits in the same manner as writing to the MIFRC
register. Each bit in the operand, #16bit, corresponds to a bit in the
MIFRC register. Using IACK has the advantage of not having to first
set the EALLOW bit. This allows the main CPU to efficiently trigger a
CLA task through software.
Examples IACK #0x0001 Write a 1 to MIFRC bit 0 to force task 1
IACK #0x0003 Write a 1 to MIFRC bit 0 and 1 to force task 1 and
task 2
1 SOFTRESET R-0/W1S 0h Soft Reset Bit: Writing a "1" to this bit will stop a current task, clear
the RUN flag and also clear all bits in the MIER register. Writes of
"0" are ignored and reads always return a "0".
Note: After issuing SOFTRESET command, user should wait at least
1 clock cycle before attempting to write to MIER register.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 are ignored.
1h (R/W) = Writing a 1 will cause a soft reset of the CLA. This will
stop the current task, clear the MIRUN flag and clear all bits in the
MIER register. After a soft reset you must wait at least 1
SYSCLKOUT cycle before reconfiguring the MIER bits. If these two
operations are done back-to-back then the MIER bits will not get set.
0 HARDRESET R-0/W1S 0h Hard Reset Bit: Writing a "1" to this bit will cause a HARD reset on
the CLA. The behavior of a HARD reset is the same as a system
reset SYSRSn on the CLA. Writes of "0" are ignored and reads
always return a "0".
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 are ignored.
1h (R/W) = Writing a 1 will cause a hard reset of the CLA. This will
set all CLA registers to their default state.

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8.8.3.10 _MVECTBGRNDACTIVE Register (Offset = 1Bh) [reset = 0h]

_MVECTBGRNDACTIVE is shown in Figure 8-17 and described in Table 8-43.
Return to the Summary Table.
Gives the current interrupted MPC value of the background task, if the background task was running and
interrupted, or reflects the MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.

Figure 8-17. _MVECTBGRNDACTIVE Register

15 14 13 12 11 10 9 8
i16
R-0h
7 6 5 4 3 2 1 0
i16
R-0h

Table 8-43. _MVECTBGRNDACTIVE Register Field Descriptions

Bit Field Type Reset Description
15-0 i16 R 0h Gives the current interrupted MPC value of the background task, if
the background task was running and interrupted, or reflects the
MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.
Reset type: SYSRSn

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8.8.3.11 SOFTINTEN Register (Offset = 1Ch) [reset = 0h]

SOFTINTEN is shown in Figure 8-18 and described in Table 8-44.
Return to the Summary Table.
Enables the ability to generate CLA task interrupt from within the task, by writing to SOFTINTFRC register.
SOFTINTFRC register can only be written from CLA. Only reads are allowed from CPU. Writes are not
allowed from CPU.

Figure 8-18. SOFTINTEN Register

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-44. SOFTINTEN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
6 TASK7 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
5 TASK6 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
4 TASK5 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
3 TASK4 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
2 TASK3 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
1 TASK2 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
0 TASK1 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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8.8.3.12 _MSTSBGRND Register (Offset = 1Dh) [reset = 0h]

_MSTSBGRND is shown in Figure 8-19 and described in Table 8-45.
Return to the Summary Table.
Status bits for the backgrondtask.

Figure 8-19. _MSTSBGRND Register

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED BGOVF _BGINTM RUN
R/W-0h R/W1C-0h R-0h R-0h

Table 8-45. _MSTSBGRND Register Field Descriptions

Bit Field Type Reset Description
15-3 RESERVED R/W 0h Reserved
2 BGOVF R/W1C 0h Value of 1 indicates a hardware trigger (which is enabled) occurred
while the MCTLBGRND.BGSTART bit is set.
Writing a value of 1 to this bit clears the BGOVF bit.
Write of 0 has no effect,
Value of 0 indicates the background task trigger did not result in a
overflow.
Reset type: SYSRSn
1 _BGINTM R 0h Value of 1 indicates that backgroiund task will not be interrupted.
This bit is set when MSETC _BGINTM bit is executed.
Value of 0 indicates that background task can be interrupted.
Reset type: SYSRSn
0 RUN R 0h Value of 1 indicates that background task is running.
Value of 0 indicates that background task is not running.
Reset type: SYSRSn

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8.8.3.13 _MCTLBGRND Register (Offset = 1Eh) [reset = 0h]

_MCTLBGRND is shown in Figure 8-20 and described in Table 8-46.
Return to the Summary Table.
Holds the configuration bits to start the background task, enable hardware trigger.

Figure 8-20. _MCTLBGRND Register

15 14 13 12 11 10 9 8
BGEN RESERVED
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED TRIGEN BGSTART
R/W-0h R/W-0h R/W1S-0h

Table 8-46. _MCTLBGRND Register Field Descriptions

Bit Field Type Reset Description
15 BGEN R/W 0h 0 Background task is disabled, BGSTART will not be set either in a
hardware trigger or by writing 1 to BGSTART bit.
1 Background task is enabled and MIER[INT8] will be cleared,
preventing task 8 from triggering.
Reset type: SYSRSn
14-2 RESERVED R/W 0h Reserved
1 TRIGEN R/W 0h Hardware trigger enable for the background task.
1 Hardware trigger is enabled.
0 Hardware trigger is disabled.
Note: Trigger source for the background task will be the same as
that for task 8
Reset type: SYSRSn
0 BGSTART R/W1S 0h Value of 1 will start the background task, provided there are no other
pending tasks.
- Value of 0 has no effect if the background task has not started.
- This bit is also set by hardware, if MCTLBGRND.TRIGEN = 1 and
a hardware trigger occurs.
- This bit is cleared by hardware when a MSTOP instruction occurs
in the background task
- If the background task is running and this bit is cleared, it will not
have any effect on the task execution.
Reset type: SYSRSn

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8.8.3.14 _MVECTBGRND Register (Offset = 1Fh) [reset = 0h]

_MVECTBGRND is shown in Figure 8-21 and described in Table 8-47.
Return to the Summary Table.
These bits specify the start address for the background task . The value in this register is forced into the
MPC register when the background task starts.

Figure 8-21. _MVECTBGRND Register

15 14 13 12 11 10 9 8
i16
R/W-0h
7 6 5 4 3 2 1 0
i16
R/W-0h

Table 8-47. _MVECTBGRND Register Field Descriptions

Bit Field Type Reset Description
15-0 i16 R/W 0h MPC Start Address: These bits specify the start address for the
background task . The value in this register is forced into the MPC
register, when the background task starts.
Reset type: SYSRSn

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8.8.3.15 MIFR Register (Offset = 20h) [reset = 0h]

MIFR is shown in Figure 8-22 and described in Table 8-48.
Return to the Summary Table.
Each bit in the interrupt flag register corresponds to a CLA task. The corresponding bit is automatically set
when the task request is received from the peripheral interrupt. The bit can also be set by the main CPU
writing to the MIFRC register or using the IACK instruction to start the task. To use the IACK instruction to
begin a task first enable this feature in the MCTL register. If the bit is already set when a new peripheral
interrupt is received, then the corresponding overflow bit will be set in the MIOVF register.
The corresponding MIFR bit is automatically cleared when the task begins execution. This will occur if the
interrupt is enabled in the MIER register and no other higher priority task is pending. The bits can also be
cleared manually by writing to the MICLR register. Writes to the MIFR register are ignored.

Figure 8-22. MIFR Register

15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 8-48. MIFR Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 8 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 8 interrupt has been received and is pending execution

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Table 8-48. MIFR Register Field Descriptions (continued)

Bit Field Type Reset Description
6 INT7 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 7 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 7 interrupt has been received and is pending execution
5 INT6 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 6 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 6 interrupt has been received and is pending execution
4 INT5 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 5 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 5 interrupt has been received and is pending execution

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Table 8-48. MIFR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 4 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 4 interrupt has been received and is pending execution
2 INT3 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 3 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 3 interrupt has been received and is pending execution
1 INT2 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 2 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 2 interrupt has been received and is pending execution

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Table 8-48. MIFR Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INT1 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 1 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 1 interrupt has been received and is pending execution

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8.8.3.16 MIOVF Register (Offset = 21h) [reset = 0h]

MIOVF is shown in Figure 8-23 and described in Table 8-49.
Return to the Summary Table.
Each bit in the overflow flag register corresponds to a CLA task. The bit is set when an interrupt overflow
event has occurred for the specific task. An overflow event occurs when the MIFR register bit is already
set when a new interrupt is received from a peripheral source. The MIOVF bits are only affected by
peripheral interrupt events. They do not respond to a task request by the main CPU IACK instruction or by
directly setting MIFR bits. The overflow flag will remain latched and can only be cleared by writing to the
overflow flag clear (MICLROVF) register. Writes to the MIOVF register are ignored.

Figure 8-23. MIOVF Register

15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 8-49. MIOVF Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as
a new peripheral interrupt occurs, the overflow flag will not be
affected and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 8 interrupt overflow has not occurred (default)
1h (R/W) = A task 8 interrupt overflow has occurred
6 INT7 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as
a new peripheral interrupt occurs, the overflow flag will not be
affected and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 7 interrupt overflow has not occurred (default)
1h (R/W) = A task 7 interrupt overflow has occurred

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Table 8-49. MIOVF Register Field Descriptions (continued)

Bit Field Type Reset Description
5 INT6 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as
a new peripheral interrupt occurs, the overflow flag will not be
affected and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 6 interrupt overflow has not occurred (default)
1h (R/W) = A task 6 interrupt overflow has occurred
4 INT5 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as
a new peripheral interrupt occurs, the overflow flag will not be
affected and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 5 interrupt overflow has not occurred (default)
1h (R/W) = A task 5 interrupt overflow has occurred
3 INT4 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as
a new peripheral interrupt occurs, the overflow flag will not be
affected and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 4 interrupt overflow has not occurred (default)
1h (R/W) = A task 4 interrupt overflow has occurred
2 INT3 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as
a new peripheral interrupt occurs, the overflow flag will not be
affected and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 3 interrupt overflow has not occurred (default)
1h (R/W) = A task 3 interrupt overflow has occurred

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Table 8-49. MIOVF Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INT2 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as
a new peripheral interrupt occurs, the overflow flag will not be
affected and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 2 interrupt overflow has not occurred (default)
1h (R/W) = A task 2 interrupt overflow has occurred
0 INT1 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as
a new peripheral interrupt occurs, the overflow flag will not be
affected and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 1 interrupt overflow has not occurred (default)
1h (R/W) = A task 1 interrupt overflow has occurred

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8.8.3.17 MIFRC Register (Offset = 22h) [reset = 0h]

MIFRC is shown in Figure 8-24 and described in Table 8-50.
Return to the Summary Table.
The interrupt force register can be used by the main CPU to start tasks through software. Writing a 1 to a
MIFRC bit will set the corresponding bit in the MIFR register. Writes of 0 are ignored and reads always
return 0. The IACK #16bit operation can also be used to start tasks and has the same effect as the
MIFRC register. To enable IACK to set MIFR bits you must first set the MCTL[IACKE] bit. Using IACK has
the advantage of not having to first set the EALLOW bit. This allows the main CPU to efficiently trigger
CLA tasks through software.

Figure 8-24. MIFRC Register

15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 8-50. MIFRC Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 8 interrupt
6 INT7 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 7 interrupt
5 INT6 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 6 interrupt
4 INT5 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 5 interrupt

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Table 8-50. MIFRC Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 4 interrupt
2 INT3 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 3 interrupt
1 INT2 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 2 interrupt
0 INT1 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 1 interrupt

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8.8.3.18 MICLR Register (Offset = 23h) [reset = 0h]

MICLR is shown in Figure 8-25 and described in Table 8-51.
Return to the Summary Table.
Normally bits in the MIFR register are automatically cleared when a task begins. The interrupt flag clear
register can be used to instead manually clear bits in the interrupt flag (MIFR) register. Writing a 1 to a
MICLR bit will clear the corresponding bit in the MIFR register. Writes of 0 are ignored and reads always
return 0.

Figure 8-25. MICLR Register

15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 8-51. MICLR Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 8 interrupt flag
6 INT7 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 7 interrupt flag
5 INT6 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 6 interrupt flag
4 INT5 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 5 interrupt flag

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Table 8-51. MICLR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 4 interrupt flag
2 INT3 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 3 interrupt flag
1 INT2 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 2 interrupt flag
0 INT1 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 1 interrupt flag

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8.8.3.19 MICLROVF Register (Offset = 24h) [reset = 0h]

MICLROVF is shown in Figure 8-26 and described in Table 8-52.
Return to the Summary Table.
Overflow flag bits in the MIOVF register are latched until manually cleared using the MICLROVF register.
Writing a 1 to a MICLROVF bit will clear the corresponding bit in the MIOVF register. Writes of 0 are
ignored and reads always return 0.

Figure 8-26. MICLROVF Register

15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 8-52. MICLROVF Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF
bit. Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 8 interrupt overflow flag
6 INT7 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF
bit. Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 7 interrupt overflow flag
5 INT6 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF
bit. Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 6 interrupt overflow flag
4 INT5 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF
bit. Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 5 interrupt overflow flag
3 INT4 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF
bit. Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 4 interrupt overflow flag

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Table 8-52. MICLROVF Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INT3 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF
bit. Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 3 interrupt overflow flag
1 INT2 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF
bit. Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 2 interrupt overflow flag
0 INT1 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF
bit. Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 1 interrupt overflow flag

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8.8.3.20 MIER Register (Offset = 25h) [reset = 0h]

MIER is shown in Figure 8-27 and described in Table 8-53.
Return to the Summary Table.
Setting the bits in the interrupt enable register (MIER) allow an incoming interrupt or main CPU software to
start the corresponding CLA task. Writing a 0 will block the task, but the interrupt request will still be
latched in the flag register (MIFLG). Setting the MIER register bit to 0 while the corresponding task is
executing will have no effect on the task. The task will continue to run until it hits the MSTOP instruction.
When a soft reset is issued, the MIER bits are cleared. There should always be at least a 1 SYSCLKOUT
delay between issuing the soft reset and reconfiguring the MIER bits.

Figure 8-27. MIER Register

15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-53. MIER Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is set
to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 8 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 8 interrupt is enabled
6 INT7 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is set
to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 7 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 7 interrupt is enabled

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Table 8-53. MIER Register Field Descriptions (continued)

Bit Field Type Reset Description
5 INT6 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is set
to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 6 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 6 interrupt is enabled
4 INT5 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is set
to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 5 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 5 interrupt is enabled
3 INT4 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is set
to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 4 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 4 interrupt is enabled
2 INT3 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is set
to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 3 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 3 interrupt is enabled

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Table 8-53. MIER Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INT2 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is set
to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 2 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 2 interrupt is enabled
0 INT1 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is set
to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 1 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 1 interrupt is enabled

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8.8.3.21 MIRUN Register (Offset = 26h) [reset = 0h]

MIRUN is shown in Figure 8-28 and described in Table 8-54.
Return to the Summary Table.
The interrupt run status register (MIRUN) indicates which task is currently executing. Only one MIRUN bit
will ever be set to a 1 at any given time. The bit is automatically cleared when the task competes and the
respective interrupt is fed to the peripheral interrupt expansion (PIE) block of the device. This lets the main
CPU know when a task has completed. The main CPU can stop a currently running task by writing to the
MCTL[SOFTRESET] bit. This will clear the MIRUN flag and stop the task. In this case no interrupt will be
generated to the PIE.

Figure 8-28. MIRUN Register

15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 8-54. MIRUN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R 0h These bits indicate which task is currently active. Only one bit can be
set to "1" at any one time. The bit is automatically cleared to "0"
when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 8 is not executing (default)
1h (R/W) = Task 8 is executing
6 INT7 R 0h These bits indicate which task is currently active. Only one bit can be
set to "1" at any one time. The bit is automatically cleared to "0"
when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 7 is not executing (default)
1h (R/W) = Task 7 is executing
5 INT6 R 0h These bits indicate which task is currently active. Only one bit can be
set to "1" at any one time. The bit is automatically cleared to "0"
when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 6 is not executing (default)
1h (R/W) = Task 6 is executing

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Table 8-54. MIRUN Register Field Descriptions (continued)

Bit Field Type Reset Description
4 INT5 R 0h These bits indicate which task is currently active. Only one bit can be
set to "1" at any one time. The bit is automatically cleared to "0"
when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 5 is not executing (default)
1h (R/W) = Task 5 is executing
3 INT4 R 0h These bits indicate which task is currently active. Only one bit can be
set to "1" at any one time. The bit is automatically cleared to "0"
when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 4 is not executing (default)
1h (R/W) = Task 4 is executing
2 INT3 R 0h These bits indicate which task is currently active. Only one bit can be
set to "1" at any one time. The bit is automatically cleared to "0"
when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 3 is not executing (default)
1h (R/W) = Task 3 is executing
1 INT2 R 0h These bits indicate which task is currently active. Only one bit can be
set to "1" at any one time. The bit is automatically cleared to "0"
when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 2 is not executing (default)
1h (R/W) = Task 2 is executing
0 INT1 R 0h These bits indicate which task is currently active. Only one bit can be
set to "1" at any one time. The bit is automatically cleared to "0"
when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 1 is not executing (default)
1h (R/W) = Task 1 is executing

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8.8.3.22 _MPC Register (Offset = 28h) [reset = 0h]

_MPC is shown in Figure 8-29 and described in Table 8-55.
Return to the Summary Table.
CLA Program Counter

Figure 8-29. _MPC Register

15 14 13 12 11 10 9 8
_MPC
R-0h
7 6 5 4 3 2 1 0
_MPC
R-0h

Table 8-55. _MPC Register Field Descriptions

Bit Field Type Reset Description
15-0 _MPC R 0h Program Counter: The PC value is initialized by the appropriate
MVECTx register when an interrupt (task) is serviced.
The MPC register address 16-bits and not 32-bits. Hence the
address range of the CLA with a 16-bit MPC is 64Kx16 words or 32K
CLA instructions.
Notes: [1] To be consistent with C28 core implementation, the PC
value points to the instruction in D2 stage of pipeline.
[2] After a STOP operation, and with no other task pending, the PC
will remain pointing to the STOP operation.
Reset type: SYSRSn

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8.8.3.23 _MAR0 Register (Offset = 2Ah) [reset = 0h]

_MAR0 is shown in Figure 8-30 and described in Table 8-56.
Return to the Summary Table.
CLA Auxiliary Register 0

Figure 8-30. _MAR0 Register

15 14 13 12 11 10 9 8
_MAR0
R-0h
7 6 5 4 3 2 1 0
_MAR0
R-0h

Table 8-56. _MAR0 Register Field Descriptions

Bit Field Type Reset Description
15-0 _MAR0 R 0h CLA Auxillary Register 0
Reset type: SYSRSn

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8.8.3.24 _MAR1 Register (Offset = 2Bh) [reset = 0h]

_MAR1 is shown in Figure 8-31 and described in Table 8-57.
Return to the Summary Table.
CLA Auxiliary Register 1

Figure 8-31. _MAR1 Register

15 14 13 12 11 10 9 8
_MAR1
R-0h
7 6 5 4 3 2 1 0
_MAR1
R-0h

Table 8-57. _MAR1 Register Field Descriptions

Bit Field Type Reset Description
15-0 _MAR1 R 0h CLA Auxillary Register 1
Reset type: SYSRSn

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8.8.3.25 _MSTF Register (Offset = 2Eh) [reset = 0h]

_MSTF is shown in Figure 8-32 and described in Table 8-58.
Return to the Summary Table.
The CLA status register (MSTF) reflects the results of different operations. These are the basic rules for
the flags:
- Zero and negative flags are cleared or set based on:
- floating-point moves to registers
- the result of compare, minimum, maximum, negative and absolute value operations
- the integer result of operations such as MMOV16, MAND32, MOR32, MXOR32, MCMP32,
MASR32, MLSR32
- Overflow and underflow flags are set by floating-point math instructions such as multiply, add, subtract
and 1/x. These flags may also be connected to the peripheral interrupt expansion (PIE) block on your
device. This can be useful for debugging underflow and overflow conditions within an application.

Figure 8-32. _MSTF Register

31 30 29 28 27 26 25 24
RESERVED _RPC
R-0h R-0h
23 22 21 20 19 18 17 16
_RPC
R-0h
15 14 13 12 11 10 9 8
_RPC MEALLOW RESERVED RNDF32 RESERVED
R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED TF RESERVED ZF NF LUF LVF
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 8-58. _MSTF Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-12 _RPC R 0h Return program counter
The _RPC is used to save and restore the MPC address by the
MCCNDD and MRCNDD operations
Reset type: SYSRSn
11 MEALLOW R 0h MEALLOW Status
This bit enables and disables CLA write access to EALLOW
protected registers This is independent of the state of the EALLOW
bit in the main CPU status register This status bit can be saved and
restored by the MMOV32 STF, mem32 instruction
Reset type: SYSRSn
0h (R/W) = The CLA cannot write to EALLOW protected registers.
This bit is cleared by the CLA instruction, MEDIS.
1h (R/W) = The CLA is allowed to write to EALLOW protected
registers. This bit is set by the CLA instruction, MEALLOW.
10 RESERVED R 0h Reserved
9 RNDF32 R 0h Round 32-bit Floating-Point Mode
Use the MSETFLG and MMOV32 MSTF, mem32 instructions to
change the rounding mode
Reset type: SYSRSn
0h (R/W) = If this bit is zero, the MMPYF32, MADDF32 and
MSUBF32 instructions will round to zero (truncate).
1h (R/W) = If this bit is one, the MMPYF32, MADDF32 and
MSUBF32 instructions will round to the nearest even value.
8-7 RESERVED R 0h Reserved

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Table 8-58. _MSTF Register Field Descriptions (continued)

Bit Field Type Reset Description
6 TF R 0h Test Flag
The MTESTTF instruction can modify this flag based on the
condition tested The MSETFLG and MMOV32 MSTF, mem32
instructions can also be used to modify this flag
Reset type: SYSRSn
0h (R/W) = The condition tested with the MTESTTF instruction is
false.
1h (R/W) = The condition tested with the MTESTTF instruction is
true.
5-4 RESERVED R 0h Reserved
3 ZF R 0h Zero Flag
- Instructions that modify this flag based on the floating-point value
stored in the destination register:
MMOV32, MMOVD32, MABSF32, MNEGF32
- Instructions that modify this flag based on the floating-point result
of the operation:
MCMPF32, MMAXF32, and MMINF32
- Instructions that modify this flag based on the integer result of the
operation:
MMOV16, MAND32, MOR32, MXOR32, MCMP32, MASR32,
MLSR32 and
MLSL32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = The value is not zero
1h (R/W) = The value is zero
2 NF R 0h Negative Flag
- Instructions that modify this flag based on the floating-point value
stored in the destination register:
MMOV32, MMOVD32, MABSF32, MNEGF32
- Instructions that modify this flag based on the floating-point result
of the operation:
MCMPF32, MMAXF32, and MMINF32
- Instructions that modify this flag based on the integer result of the
operation:
MMOV16, MAND32, MOR32, MXOR32, MCMP32, MASR32,
MLSR32 and
MLSL32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = The value is not negative
1h (R/W) = The value is negative
1 LUF R 0h Latched Underflow Flag
The following instructions will set this flag to 1 if an underflow occurs:
MMPYF32, MADDF32,
MSUBF32, MMACF32, MEINVF32, MEISQRTF32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = An underflow condition has not been latched
1h (R/W) = An underflow condition has been latched
0 LVF R 0h Latched Overflow Flag
The following instructions will set this flag to 1 if an overflow occurs:
MMPYF32, MADDF32, MSUBF32, MMACF32, MEINVF32,
MEISQRTF32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = An overflow condition has not been latched
1h (R/W) = An overflow condition has been latched

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8.8.3.26 _MR0 Register (Offset = 30h) [reset = 0h]

_MR0 is shown in Figure 8-33 and described in Table 8-59.
Return to the Summary Table.
CLA Floating-Point Result Register 0

Figure 8-33. _MR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 8-59. _MR0 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 0
Reset type: SYSRSn

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8.8.3.27 _MR1 Register (Offset = 34h) [reset = 0h]

_MR1 is shown in Figure 8-34 and described in Table 8-60.
Return to the Summary Table.
CLA Floating-Point Result Register 1

Figure 8-34. _MR1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 8-60. _MR1 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 1
Reset type: SYSRSn

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8.8.3.28 _MR2 Register (Offset = 38h) [reset = 0h]

_MR2 is shown in Figure 8-35 and described in Table 8-61.
Return to the Summary Table.
CLA Floating-Point Result Register 2

Figure 8-35. _MR2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 8-61. _MR2 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 2
Reset type: SYSRSn

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8.8.3.29 _MR3 Register (Offset = 3Ch) [reset = 0h]

_MR3 is shown in Figure 8-36 and described in Table 8-62.
Return to the Summary Table.
CLA Floating-Point Result Register 3

Figure 8-36. _MR3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 8-62. _MR3 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 3
Reset type: SYSRSn

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8.8.3.30 _MPSACTL Register (Offset = 42h) [reset = 0h]

_MPSACTL is shown in Figure 8-37 and described in Table 8-63.
Return to the Summary Table.
PSA Control Register

Figure 8-37. _MPSACTL Register

15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
MPSA2CFG MPSA2CLEAR MPSA1CLEAR MDWDBCYC MDWDBSTAR MPABCYC MPABSTART
T
R/W-0h R-0/W1S-0h R-0/W1S-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-63. _MPSACTL Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7-6 MPSA2CFG R/W 0h CLA PSA2 Polynomial Configuration Bits: These bits configure the
type of polynomial used for PSA2. The polynomials chosen are
commonly used in the industry:
Mode Polynomial Type
0,0 PSA
0,1 CRC32
1,0 CRC16
1,1 CRC16-CCITT
Note: [1] Polynomial configuration should be performed when PSA2
is stopped.
Reset type: SYSRSn
5 MPSA2CLEAR R-0/W1S 0h CLA PSA2 Clear Bit:
Writing of "1" will clear contents of PSA2 register.
Writes of "0" are ignored.
Always reads back a "0"
Note: Clearing operation should be performed when PSA2 is
stopped.
Reset type: SYSRSn
4 MPSA1CLEAR R-0/W1S 0h CLA PSA1 Clear Bit:
Writing of "1" will clear contents of PSA1 register.
Writes of "0" are ignored.
Always reads back a "0"
Note: Clearing operation should be performed when PSA1 is
stopped.
Reset type: SYSRSn
3 MDWDBCYC R/W 0h CLA Data Write Data Bus PSA2 Cycle or Event Based Bit:
0 PSA2 calculated on every cycle
1 PSA2 calculated on every bus event
Reset type: SYSRSn
2 MDWDBSTART R/W 0h CLA Data Write Data Bus PSA2 Start/Stop Bit:
0 PSA2 stopped
1 PSA2 start
Reset type: SYSRSn
1 MPABCYC R/W 0h CLA Program Address Bus PSA1 Cycle/Event Based Bit:
0 PSA1 calculated on every cycle
1 PSA1 calculated on every bus event
Reset type: SYSRSn
0 MPABSTART R/W 0h CLA Program Address Bus PSA1 Start/Stop Bit:
0 PSA1 stopped
1 PSA1 start
Reset type: SYSRSn

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8.8.3.31 _MPSA1 Register (Offset = 44h) [reset = 0h]

_MPSA1 is shown in Figure 8-38 and described in Table 8-64.
Return to the Summary Table.
PSA1 Register

Figure 8-38. _MPSA1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R/W-0h

Table 8-64. _MPSA1 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R/W 0h PSA1 Value: Reading this register gives the current PSA1 value.
The value can be read at any time.
Writes to this register are allowed to initialize the PSA1 to a known
value. Writes to this register should only be made when PSA1 is
stopped.
Register value is cleared to zero by reset or by writing to the
MPSA1CLEAR bit in the MPSACTL register.
Reset type: SYSRSn

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8.8.3.32 _MPSA2 Register (Offset = 46h) [reset = 0h]

_MPSA2 is shown in Figure 8-39 and described in Table 8-65.
Return to the Summary Table.
PSA2 Register

Figure 8-39. _MPSA2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R/W-0h

Table 8-65. _MPSA2 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R/W 0h PSA2 Value: Reading this register gives the current PSA2 value.
The value can be read at any time.
Writes to this register are allowed to initialize the PSA2 to a known
value. Writes to this register should only be made when PSA2 is
stopped.
Register value is cleared to zero by reset or by writing to the
MPSA2CLEAR bit in the MPSACTL register.
Reset type: SYSRSn

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8.8.4 CLA_SOFTINT_REGS Registers

Table 8-66 lists the CLA_SOFTINT_REGS registers. All register offset addresses not listed in Table 8-66
should be considered as reserved locations and the register contents should not be modified.

Table 8-66. CLA_SOFTINT_REGS Registers

Offset Acronym Register Name Write Protection Section
0h SOFTINTEN CLA Software Interrupt Enable Register Go
2h SOFTINTFRC CLA Software Interrupt Force Register Go

Complex bit access types are encoded to fit into small table cells. Table 8-67 shows the codes that are
used for access types in this section.

Table 8-67. CLA_SOFTINT_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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8.8.4.1 SOFTINTEN Register (Offset = 0h) [reset = 0h]

SOFTINTEN is shown in Figure 8-40 and described in Table 8-68.
Return to the Summary Table.
Enables the ability to generate CLA task interrupt from within the task, by writing to SOFTINTFRC register.
SOFTINTFRC register can only be written from CLA.

Figure 8-40. SOFTINTEN Register

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-68. SOFTINTEN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
6 TASK7 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
5 TASK6 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
4 TASK5 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
3 TASK4 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
2 TASK3 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
1 TASK2 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
0 TASK1 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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8.8.4.2 SOFTINTFRC Register (Offset = 2h) [reset = 0h]

SOFTINTFRC is shown in Figure 8-41 and described in Table 8-69.
Return to the Summary Table.
Writing a value of 1 in a bit will generate the corresponding task interrupt.This register is only accessible
by the CLA (not the CPU).

Figure 8-41. SOFTINTFRC Register

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 8-69. SOFTINTFRC Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
6 TASK7 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
5 TASK6 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
4 TASK5 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
3 TASK4 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
2 TASK3 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
1 TASK2 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
0 TASK1 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn

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 Chapter 9
SPRUII0B – May 2019 – Revised May 2020

Configurable Logic Block (CLB)

This chapter describes the features and operation of the C2000 configurable logic block (CLB) that is a
collection of configurable blocks that may be inter-connected using software to implement custom digital
logic functions.

Topic ........................................................................................................................... Page

9.1 Introduction ................................................................................................... 1121

9.2 Features ........................................................................................................ 1121
9.3 CLB Input/Output Connection .......................................................................... 1123
9.4 CLB Tile ......................................................................................................... 1140
9.5 CPU Interface ................................................................................................. 1158
9.6 CLB Registers ................................................................................................ 1160

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9.1 Introduction
The C2000 configurable logic block (CLB) is a collection of configurable blocks that can be inter-
connected using software to implement custom digital logic functions. The CLB is able to enhance existing
peripherals through a set of crossbar interconnections, which provide a high level of connectivity to
existing control peripherals such as enhanced pulse width modulators (ePWM), enhanced capture
modules (eCAP), and enhanced quadrature encoder pulse modules (eQEP). The crossbars also allow the
CLB to be connected to external GPIO pins. In this way, the CLB can be configured to interact with device
peripherals to perform small logical functions such as simple PWM generators, or to implement custom
serial data exchange protocols.
The CLB peripheral is configured through the CLB tool. For more information on the CLB tool, available
examples, application reports, and user's guide, refer to the following location in your C2000WARE
package (C2000Ware_2_00_00_03 and higher):
C2000WARE_INSTALL_LOCATION\utilities\clb_tool\clb_syscfg\doc

9.2 Features
The CLB subsystem contains a number of identical tiles. There are four such tiles in the CLB subsystem;
other devices may contain more or fewer tiles. Tiles are numbered 1 to ‘N’, where ‘N’ is the total tile count
on the device. Each tile contains combinational and sequential logic blocks, as well as other dedicated
hardware to be described later in this document. Figure 9-1 shows the structure of the CLB subsystem in
the device.
The tile contains the core logic, providing the logic reconfiguration capability. Each CLB tile is associated
with a separate CPU interface, which contains the registers needed to control and configure the logic in
the tile. The CPU interface also contains data transfer buffers that can be used as part of the configurable
logic to exchange data with the rest of the device. Figure 9-2 shows the connections between the tile, the
CPU interface, and the device.

Figure 9-1. Block Diagram of the CLB Subsystem in the Device

CLB1 Int
CPU I/F CLB Output X-BAR
CLB XBAR G L S TILE 1 XTRIP
Input XBAR1
X-BAR
XBAR
L O y CLB X-BAR
O C s
B A t
A L e
L m
B B
U U B
S S u
s ePWM,eQEP, & eCAP Peripherals
ePWM, eQEP, & eCAP Peripherals

L
O
C
A CLBn Int
L CPU I/F TILE n
B
U
S

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Figure 9-2. Block Diagram of a CLB Tile and CPU Interface

Inputs from other Tiles

RECONFIG_CLK

PIE Interrupt Cell

Inputs
Input Selection
& Filtering 8
CPU Interface Signals CLB
CLB Tile
Outputs
Control & Configuration
SYSCLK Registers

Data Exchange
Memory

CPU Interface Block

9.2.1 CLB Clock

In this device, the CLB clock is called CLBx clock that can be enabled or disabled by
SYSCTL_PERIPH_CLK_CLBx through the SysCtl_enablePeripheral function. The maximum frequency
is 150 MHz and it can be enabled and configured by modifying the CLBx clock.

9.2.1.1 CLB Clock Prescalar

Starting with CLB Type 2, a clock prescalar module is available. The prescalar module can generate a
prescaled version of the CLB clock signal that can be used as an input to the CLB TILEs.

NOTE: The prescaler logic does not change the actual clocking speed of the CLB. The prescalar
generates a strobe (which can toggle at the defined prescaled rate) which is made available
as another input signal to the CLB logic and it is only used when required.

The prescalar module is shown in Figure 9-3.

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Figure 9-3. CLB Clock Prescalar

PRESCALAR Module

CLB_PRESCALE_CTRL.S
CLB_PRESCALE_CTRL.PRESC
TRB
ALAR
Equal? PRESCALED Clock
(Available at the CLB
16-bit Counter Register
CLB Clock Local Mux Options)

CLB_PRESCALE_CTRL.T
AP

Counter Register Bits Selected Bit

9.3 CLB Input/Output Connection

9.3.1 Overview
There are four instances of the CLB module in the device. Each CLB instance has a common set of input
signals referred to as global input signals. Additionally, each CLB instance has a specific set of input
signals that are unique to each instance, and are referred to as local input signals. Each of the eight inputs
of a CLB can be chosen from any of the global input signals or the local input signals.

9.3.2 CLB Input Selection

Each CLB module has eight inputs that feed into the reconfigurable logic cell. Each of these inputs can be
selectively driven by a predefined set of signals. A two-level mux structure allows each input of each CLB
instance to select a signal.
A set of signals is common to all the CLB instances. These are referred to as global inputs in Figure 9-4.
A separate set of signals is unique to each instance of the CLB. These are referred to as local inputs in
Figure 9-4.
Registers CLB_LCL_MUX_SEL_1 and CLB_LCL_MUX_SEL_2 control the local mux selection for each of
the eight inputs. The mux control registers CLB_GLBL_MUX_SEL_1 and CLB_GLBL_MUX_SEL_2
control the global mux selection for each of the eight inputs.
The local mux select value of 0 causes the selected global mux input signal to be connected to the
corresponding CLB Input. For example, setting CLB_LCL_MUX_SEL_IN_0 = 0 and
CLB_GLBL_MUX_SEL_IN_0 = 8 causes the global mux input number 8 to be connected to CLB Input 0.
The input filter feature can be used to enable edge detection on the CLB inputs. The input filter feature
can also synchronize the input with the CLB clock.
The global and local input mux settings are shown in Table 9-1 and Table 9-2.

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Figure 9-4. CLB Input Mux and Filter

Synchronizer
GPREG [n]
Cell input [n]
(BOUNDARY IN[n])
Synchronizer
Local Inputs Filter
CLB_INPUT_FILTER.SYNC[n]
CLB_IN_MUX_SEL_0[n]

CLB_INPUT_FILTER.FIN[n]
CLB_INPUT_FILTER.SYNC[n]
CLB_LCL_MUX_SEL_1/2

Global Inputs

CLB_GLBL_MUX_SEL_1/2

Table 9-1. Global Signals and Mux Selection

Global Input Mux Bit
SYNC/ASYNC Signal Name Instance Name
Position
CLB1 to CLB4
0 ASYNC ePWMxA EPWM1
1 ASYNC PWMA[OE] EPWM1
2 ASYNC ePWMxB EPWM1
3 ASYNC PWMB[OE] EPWM1
4 SYNC CTR=ZERO EPWM1
5 SYNC CTR=PRD EPWM1
6 SYNC CTR_Dir EPWM1
7 SYNC TBCLK EPWM1
8 SYNC CTR=CMPA EPWM1
9 SYNC CTR=CMPB EPWM1
10 SYNC CTR=CMPC EPWM1
11 SYNC CTR=CMPD EPWM1
12 SYNC PWMA[AQ] EPWM1
13 SYNC PWMB[AQ] EPWM1
14 SYNC PWMA[DB] EPWM1
15 SYNC PWMB[DB] EPWM1
16 ASYNC ePWMxA EPWM2
17 ASYNC PWMA[OE] EPWM2
18 ASYNC ePWMxB EPWM2
19 ASYNC PWMB[OE] EPWM2
20 SYNC CTR=ZERO EPWM2
21 SYNC CTR=PRD EPWM2
22 SYNC CTR_Dir EPWM2
23 SYNC TBCLK EPWM2
24 SYNC CTR=CMPA EPWM2
25 SYNC CTR=CMPB EPWM2
26 SYNC CTR=CMPC EPWM2
27 SYNC CTR=CMPD EPWM2
28 SYNC PWMA[AQ] EPWM2
29 SYNC PWMB[AQ] EPWM2
30 SYNC PWMA[DB] EPWM2
31 SYNC PWMB[DB] EPWM2
32 ASYNC ePWMxA EPWM3
33 ASYNC PWMA[OE] EPWM3
34 ASYNC ePWMxB EPWM3

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Table 9-1. Global Signals and Mux Selection (continued)

Global Input Mux Bit
SYNC/ASYNC Signal Name Instance Name
Position
35 ASYNC PWMB[OE] EPWM3
36 SYNC CTR=ZERO EPWM3
37 SYNC CTR=PRD EPWM3
38 SYNC CTR_Dir EPWM3
39 SYNC TBCLK EPWM3
40 SYNC CTR=CMPA EPWM3
41 SYNC CTR=CMPB EPWM3
42 SYNC CTR=CMPC EPWM3
43 SYNC CTR=CMPD EPWM3
44 SYNC PWMA[AQ] EPWM3
45 SYNC PWMB[AQ] EPWM3
46 SYNC PWMA[DB] EPWM3
47 SYNC PWMB[DB] EPWM3
48 ASYNC ePWMxA EPWM4
49 ASYNC PWMA[OE] EPWM4
50 ASYNC ePWMxB EPWM4
51 ASYNC PWMB[OE] EPWM4
52 SYNC CTR=ZERO EPWM4
53 SYNC CTR=PRD EPWM4
54 SYNC CTR_Dir EPWM4
55 SYNC TBCLK EPWM4
56 SYNC CTR=CMPA EPWM4
57 SYNC CTR=CMPB EPWM4
58 SYNC CTR=CMPC EPWM4
59 SYNC CTR=CMPD EPWM4
60 SYNC PWMA[AQ] EPWM4
61 SYNC PWMB[AQ] EPWM4
62 SYNC PWMA[DB] EPWM4
63 SYNC PWMB[DB] EPWM4
64 ASYNC AUXSIG0 CLB X BAR
65 ASYNC AUXSIG1 CLB X BAR
66 ASYNC AUXSIG2 CLB X BAR
67 ASYNC AUXSIG2 CLB X BAR
68 ASYNC AUXSIG4 CLB X BAR
69 ASYNC AUXSIG5 CLB X BAR
70 ASYNC AUXSIG6 CLB X BAR
71 ASYNC AUXSIG7 CLB X BAR
72 SYNC CLB1_OUT16 CLB1
73 SYNC CLB1_OUT17 CLB1
74 SYNC CLB1_OUT18 CLB1
75 SYNC CLB1_OUT19 CLB1
76 SYNC CLB1_OUT20 CLB1
77 SYNC CLB1_OUT21 CLB1
78 SYNC CLB1_OUT22 CLB1
79 SYNC CLB1_OUT23 CLB1
80 SYNC CLB2_OUT16 CLB2
81 SYNC CLB2_OUT17 CLB2
82 SYNC CLB2_OUT18 CLB2
83 SYNC CLB2_OUT19 CLB2
84 SYNC CLB2_OUT20 CLB2
85 SYNC CLB2_OUT21 CLB2

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Table 9-1. Global Signals and Mux Selection (continued)

Global Input Mux Bit
SYNC/ASYNC Signal Name Instance Name
Position
86 SYNC CLB2_OUT22 CLB2
87 SYNC CLB2_OUT23 CLB2
88 SYNC CLB3_OUT16 CLB3
89 SYNC CLB3_OUT17 CLB3
90 SYNC CLB3_OUT18 CLB3
91 SYNC CLB3_OUT19 CLB3
92 SYNC CLB3_OUT20 CLB3
93 SYNC CLB3_OUT21 CLB3
94 SYNC CLB3_OUT22 CLB3
95 SYNC CLB3_OUT23 CLB3
96 SYNC CLB4_OUT16 CLB4
97 SYNC CLB4_OUT17 CLB4
98 SYNC CLB4_OUT18 CLB4
99 SYNC CLB4_OUT19 CLB4
100 SYNC CLB4_OUT20 CLB4
101 SYNC CLB4_OUT21 CLB4
102 SYNC CLB4_OUT22 CLB4
103 SYNC CLB4_OUT23 CLB4
104 SYNC ERAD event 0 CPU1.ERAD
105 SYNC ERAD event 1 CPU1.ERAD
106 SYNC ERAD event 2 CPU1.ERAD
107 SYNC ERAD event 3 CPU1.ERAD
108 SYNC ERAD event 4 CPU1.ERAD
109 SYNC ERAD event 5 CPU1.ERAD
110 SYNC ERAD event 6 CPU1.ERAD
111 SYNC ERAD event 7 CPU1.ERAD
112 SYNC DATA_PKT_RCVD FSIRXA
113 SYNC ERROR_PKT_RCVD FSIRXA
114 SYNC PING_PKT_RCVD FSIRXA
115 SYNC frame_done FSIRXA
116 SYNC PKT_TAG[0] FSIRXA
117 SYNC PKT_TAG[1] FSIRXA
118 SYNC PKT_TAG[2] FSIRXA
119 SYNC PKT_TAG[3] FSIRXA
120 ASYNC SPICLK(OUT) SPIA
121 ASYNC SPISOMI(IN) SPIA
122 ASYNC SPISTE(OUT) SPIA
123 ASYNC SPICLK(OUT) SPIB
124 ASYNC SPISOMI(IN) SPIB
125 ASYNC SPISTE(OUT) SPIB
126 SYNC CPU2.HALT CPU2
CLB5 to CLB8
0 ASYNC ePWMxA EPWM5
1 ASYNC PWMA[OE] EPWM5
2 ASYNC ePWMxB EPWM5
3 ASYNC PWMB[OE] EPWM5
4 SYNC CTR=ZERO EPWM5
5 SYNC CTR=PRD EPWM5
6 SYNC CTR_Dir EPWM5
7 SYNC TBCLK EPWM5
8 SYNC CTR=CMPA EPWM5

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Table 9-1. Global Signals and Mux Selection (continued)

Global Input Mux Bit
SYNC/ASYNC Signal Name Instance Name
Position
9 SYNC CTR=CMPB EPWM5
10 SYNC CTR=CMPC EPWM5
11 SYNC CTR=CMPD EPWM5
12 SYNC PWMA[AQ] EPWM5
13 SYNC PWMB[AQ] EPWM5
14 SYNC PWMA[DB] EPWM5
15 SYNC PWMB[DB] EPWM5
16 ASYNC ePWMxA EPWM6
17 ASYNC PWMA[OE] EPWM6
18 ASYNC ePWMxB EPWM6
19 ASYNC PWMB[OE] EPWM6
20 SYNC CTR=ZERO EPWM6
21 SYNC CTR=PRD EPWM6
22 SYNC CTR_Dir EPWM6
23 SYNC TBCLK EPWM6
24 SYNC CTR=CMPA EPWM6
25 SYNC CTR=CMPB EPWM6
26 SYNC CTR=CMPC EPWM6
27 SYNC CTR=CMPD EPWM6
28 SYNC PWMA[AQ] EPWM6
29 SYNC PWMB[AQ] EPWM6
30 SYNC PWMA[DB] EPWM6
31 SYNC PWMB[DB] EPWM6
32 ASYNC ePWMxA EPWM7
33 ASYNC PWMA[OE] EPWM7
34 ASYNC ePWMxB EPWM7
35 ASYNC PWMB[OE] EPWM7
36 SYNC CTR=ZERO EPWM7
37 SYNC CTR=PRD EPWM7
38 SYNC CTR_Dir EPWM7
39 SYNC TBCLK EPWM7
40 SYNC CTR=CMPA EPWM7
41 SYNC CTR=CMPB EPWM7
42 SYNC CTR=CMPC EPWM7
43 SYNC CTR=CMPD EPWM7
44 SYNC PWMA[AQ] EPWM7
45 SYNC PWMB[AQ] EPWM7
46 SYNC PWMA[DB] EPWM7
47 SYNC PWMB[DB] EPWM7
48 ASYNC ePWMxA EPWM8
49 ASYNC PWMA[OE] EPWM8
50 ASYNC ePWMxB EPWM8
51 ASYNC PWMB[OE] EPWM8
52 SYNC CTR=ZERO EPWM8
53 SYNC CTR=PRD EPWM8
54 SYNC CTR_Dir EPWM8
55 SYNC TBCLK EPWM8
56 SYNC CTR=CMPA EPWM8
57 SYNC CTR=CMPB EPWM8
58 SYNC CTR=CMPC EPWM8
59 SYNC CTR=CMPD EPWM8

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Table 9-1. Global Signals and Mux Selection (continued)

Global Input Mux Bit
SYNC/ASYNC Signal Name Instance Name
Position
60 SYNC PWMA[AQ] EPWM8
61 SYNC PWMB[AQ] EPWM8
62 SYNC PWMA[DB] EPWM8
63 SYNC PWMB[DB] EPWM8
64 ASYNC AUXSIG0 CLB X BAR
65 ASYNC AUXSIG1 CLB X BAR
66 ASYNC AUXSIG2 CLB X BAR
67 ASYNC AUXSIG2 CLB X BAR
68 ASYNC AUXSIG4 CLB X BAR
69 ASYNC AUXSIG5 CLB X BAR
70 ASYNC AUXSIG6 CLB X BAR
71 ASYNC AUXSIG7 CLB X BAR
72 SYNC CLB5_OUT16 CLB5
73 SYNC CLB5_OUT17 CLB5
74 SYNC CLB5_OUT18 CLB5
75 SYNC CLB5_OUT19 CLB5
76 SYNC CLB5_OUT20 CLB5
77 SYNC CLB5_OUT21 CLB5
78 SYNC CLB5_OUT22 CLB5
79 SYNC CLB5_OUT23 CLB5
80 SYNC CLB6_OUT16 CLB6
81 SYNC CLB6_OUT17 CLB6
82 SYNC CLB6_OUT18 CLB6
83 SYNC CLB6_OUT19 CLB6
84 SYNC CLB6_OUT20 CLB6
85 SYNC CLB6_OUT21 CLB6
86 SYNC CLB6_OUT22 CLB6
87 SYNC CLB6_OUT23 CLB6
88 SYNC CLB3_OUT16 CLB3
89 SYNC CLB3_OUT17 CLB3
90 SYNC CLB3_OUT18 CLB3
91 SYNC CLB3_OUT19 CLB3
92 SYNC CLB3_OUT20 CLB3
93 SYNC CLB3_OUT21 CLB3
94 SYNC CLB3_OUT22 CLB3
95 SYNC CLB3_OUT23 CLB3
96 SYNC CLB4_OUT16 CLB4
97 SYNC CLB4_OUT17 CLB4
98 SYNC CLB4_OUT18 CLB4
99 SYNC CLB4_OUT19 CLB4
100 SYNC CLB4_OUT20 CLB4
101 SYNC CLB4_OUT21 CLB4
102 SYNC CLB4_OUT22 CLB4
103 SYNC CLB4_OUT23 CLB4
104 SYNC ERAD event 0 CPU2.ERAD
105 SYNC ERAD event 1 CPU2.ERAD
106 SYNC ERAD event 2 CPU2.ERAD
107 SYNC ERAD event 3 CPU2.ERAD
108 SYNC ERAD event 4 CPU2.ERAD
109 SYNC ERAD event 5 CPU2.ERAD
110 SYNC ERAD event 6 CPU2.ERAD

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Table 9-1. Global Signals and Mux Selection (continued)

Global Input Mux Bit
SYNC/ASYNC Signal Name Instance Name
Position
111 SYNC ERAD event 7 CPU2.ERAD
112 SYNC PING_FRAME_TAG_MATCH FSIRXA
113 SYNC DATA_FRAME_TAG_MATCH FSIRXA
114 SYNC ERROR_FRAME_TAG_MATCH FSIRXA
115 SYNC PING_FRAME_TAG_MATCH FSIRXB
116 SYNC DATA_FRAME_TAG_MATCH FSIRXB
117 SYNC ERROR_FRAME_TAG_MATCH FSIRXB
118 ASYNC ECAT_SOF ETHERCAT
119 ASYNC ECAT_EOF ETHERCAT
120 ASYNC SPICLK(OUT) SPIC
121 ASYNC SPISOMI(IN) SPIC
122 ASYNC SPISTE(OUT) SPIC
123 ASYNC SPICLK(OUT) SPID
124 ASYNC SPISOMI(IN) SPID
125 ASYNC SPISTE(OUT) SPID
ECAT_SYNC0
126 ASYNC (SYNC0 should not be gated off if EtherCAT is ETHERCAT
allocated to CM)
ECAT_SYNC1
127 ASYNC (SYNC1 should not be gated off if EtherCAT is ETHERCAT
allocated to CM).

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Table 9-2. Local Signals and Mux Selection

Bit
SYNC/ASYNC Signal Name Instance Name Instance Name Instance Name Instance Name
Position
CLB1 CLB2 CLB3 CLB
0 Global Mux input Global Mux input Global Mux input Global Mux input Global Mux input
1 ASYNC DCAEVT1 EPWM1 EPWM2 EPWM3 EPWM4
2 ASYNC DCAEVT2 EPWM1 EPWM2 EPWM3 EPWM4
3 ASYNC DCBEVT1 EPWM1 EPWM2 EPWM3 EPWM4
4 ASYNC DCBEVT2 EPWM1 EPWM2 EPWM3 EPWM4
5 ASYNC DCAH EPWM1 EPWM2 EPWM3 EPWM4
6 ASYNC DCAL EPWM1 EPWM2 EPWM3 EPWM4
7 ASYNC DCBH EPWM1 EPWM2 EPWM3 EPWM4
8 ASYNC DCBL EPWM1 EPWM2 EPWM3 EPWM4
9 ASYNC OST EPWM1 EPWM2 EPWM3 EPWM4
10 ASYNC CBC EPWM1 EPWM2 EPWM3 EPWM4
11 ASYNC ECAPIN ECAP1 ECAP2 ECAP3 ECAP4
12 SYNC ECAP_OUT ECAP1 ECAP2 ECAP3 ECAP4
13 SYNC ECAP_OUT_EN ECAP1 ECAP2 ECAP3 ECAP4
14 SYNC CEVT1 ECAP1 ECAP2 ECAP3 ECAP4
15 SYNC CEVT2 ECAP1 ECAP2 ECAP3 ECAP4
16 SYNC CEVT3 ECAP1 ECAP2 ECAP3 ECAP4
17 SYNC CEVT4 ECAP1 ECAP2 ECAP3 ECAP4
18 ASYNC EQEPA EQEP1 EQEP2 EQEP3
19 ASYNC EQEPB EQEP1 EQEP2 EQEP3
20 ASYNC EQEPI EQEP1 EQEP2 EQEP3
21 ASYNC EQEPS EQEP1 EQEP2 EQEP3
22 SYNC CPU1.TBCLKSYNC CPU1.TBCLKSYNC CPU1.TBCLKSYNC CPU1.TBCLKSYNC CPU1.TBCLKSYNC
23 SYNC CPU2.TBCLKSYNC CPU2.TBCLKSYNC CPU2.TBCLKSYNC CPU2.TBCLKSYNC CPU2.TBCLKSYNC
24 SYNC CPU1.HALT CPU1.HALT CPU1.HALT CPU1.HALT CPU1.HALT
25 ASYNC SPISIMO(OUT) SPIA SPIB SPIC SPID
26 ASYNC SPI Clock (IN) SPIA SPIB SPIC SPID
27 ASYNC SPISIMO(IN) SPIA SPIB SPIC SPID
28 ASYNC SPI STE(IN) SPIA SPIB SPIC SPID
29 ASYNC SCI TX SCI1 SCI2 SCI1 SCI2
30 ASYNC SPISOMI(OUT) SPIA SPIB SPIC SPID
31 SYNC Local prescaled clock CLB1 CLB2 CLB3 CLB4
32 ASYNC PWMA EPWM9 EPWM9 EPWM9 EPWM9
33 ASYNC PWMA_OE EPWM9 EPWM9 EPWM9 EPWM9
34 ASYNC PWMB EPWM9 EPWM9 EPWM9 EPWM9
35 ASYNC PWMB_OE EPWM9 EPWM9 EPWM9 EPWM9
36 ASYNC PWMA EPWM10 EPWM10 EPWM10 EPWM10
37 ASYNC PWMA_OE EPWM10 EPWM10 EPWM10 EPWM10
38 ASYNC PWMB EPWM10 EPWM10 EPWM10 EPWM10
39 ASYNC PWMB_OE EPWM10 EPWM10 EPWM10 EPWM10
40 ASYNC PWMA EPWM11 EPWM11 EPWM11 EPWM11
41 ASYNC PWMA_OE EPWM11 EPWM11 EPWM11 EPWM11
42 ASYNC PWMB EPWM11 EPWM11 EPWM11 EPWM11
43 ASYNC PWMB_OE EPWM11 EPWM11 EPWM11 EPWM11
44 ASYNC PWMA EPWM12 EPWM12 EPWM12 EPWM12
45 ASYNC PWMA_OE EPWM12 EPWM12 EPWM12 EPWM12
46 ASYNC PWMB EPWM12 EPWM12 EPWM12 EPWM12
47 ASYNC PWMB_OE EPWM12 EPWM12 EPWM12 EPWM12
48 ASYNC INPUT1 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
49 ASYNC INPUT2 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR

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Table 9-2. Local Signals and Mux Selection (continued)

Bit
SYNC/ASYNC Signal Name Instance Name Instance Name Instance Name Instance Name
Position
50 ASYNC INPUT3 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
51 ASYNC INPUT4 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
52 ASYNC INPUT5 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
53 ASYNC INPUT6 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
54 ASYNC INPUT7 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
55 ASYNC INPUT8 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
56 ASYNC INPUT9 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
57 ASYNC INPUT10 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
58 ASYNC INPUT11 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
59 ASYNC INPUT12 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
60 ASYNC INPUT13 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
61 ASYNC INPUT14 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
62 ASYNC INPUT15 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
63 ASYNC INPUT16 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
CLB5 CLB6 CLB7 CLB8
0 GLB_MUX_OUT CLB5 CLB6 CLB7 CLB8
1 ASYNC DCAEVT1 EPWM5 EPWM6 EPWM7 EPWM8
2 ASYNC DCAEVT2 EPWM5 EPWM6 EPWM7 EPWM8
3 ASYNC DCBEVT1 EPWM5 EPWM6 EPWM7 EPWM8
4 ASYNC DCBEVT2 EPWM5 EPWM6 EPWM7 EPWM8
5 ASYNC DCAH EPWM5 EPWM6 EPWM7 EPWM8
6 ASYNC DCAL EPWM5 EPWM6 EPWM7 EPWM8
7 ASYNC DCBH EPWM5 EPWM6 EPWM7 EPWM8
8 ASYNC DCBL EPWM5 EPWM6 EPWM7 EPWM8
9 ASYNC OST EPWM5 EPWM6 EPWM7 EPWM8
10 ASYNC CBC EPWM5 EPWM6 EPWM7 EPWM8
11 ASYNC ECAPIN[0] ECAP3 ECAP4 ECAP5 ECAP6
12 SYNC ECAP_OUT ECAP3 ECAP4 ECAP5 ECAP6
13 SYNC ECAP_OUT_EN ECAP3 ECAP4 ECAP5 ECAP6
14 SYNC CEVT1 ECAP3 ECAP4 ECAP5 ECAP6
15 SYNC CEVT2 ECAP3 ECAP4 ECAP5 ECAP6
16 SYNC CEVT3 ECAP3 ECAP4 ECAP5 ECAP6
17 SYNC CEVT4 ECAP3 ECAP4 ECAP5 ECAP6
FSI_DATA_PKT_
18 SYNC FSIRXC FSIRXD FSIRXE FSIRXF
RCVD
FSI_ERROR_PKT_
19 SYNC FSIRXC FSIRXD FSIRXE FSIRXF
RCVD
FSI_PING_PKT_
20 SYNC FSIRXC FSIRXD FSIRXE FSIRXF
RCVD
21 SYNC CPU2.HALT CPU2.HALT CPU2.HALT CPU2.HALT CPU2.HALT
22 SYNC CPU1.TBCLKSYNC CPU1.TBCLKSYNC CPU1.TBCLKSYNC CPU1.TBCLKSYNC CPU1.TBCLKSYNC
23 SYNC CPU2.TBCLKSYNC CPU2.TBCLKSYNC CPU2.TBCLKSYNC CPU2.TBCLKSYNC CPU2.TBCLKSYNC
24 SYNC CPU1.HALT CPU1.HALT CPU1.HALT CPU1.HALT CPU1.HALT
25 ASYNC SPISIMO(OUT) SPIC SPID SPIC SPID
26 ASYNC SPI Clock (IN) SPIC SPID SPIC SPID
27 ASYNC SPISIMO(IN) SPIC SPID SPIC SPID
28 ASYNC SPI STE(IN) SPIC SPID SPIC SPID
29 ASYNC SCI TX SCI3 SCI4 SCI3 SCI4
30 ASYNC SPISOMI(OUT) SPIC SPID SPIC SPID
31 SYNC Local prescaled clock CLB5 CLB6 CLB7 CLB8
32 ASYNC PWMA EPWM13 EPWM13 EPWM13 EPWM13
33 ASYNC PWMAOE EPWM13 EPWM13 EPWM13 EPWM13

SPRUII0B – May 2019 – Revised May 2020 Configurable Logic Block (CLB) 1131
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Table 9-2. Local Signals and Mux Selection (continued)

Bit
SYNC/ASYNC Signal Name Instance Name Instance Name Instance Name Instance Name
Position
34 ASYNC PWMB EPWM13 EPWM13 EPWM13 EPWM13
35 ASYNC PWMBOE EPWM13 EPWM13 EPWM13 EPWM13
36 ASYNC PWMA EPWM14 EPWM14 EPWM14 EPWM14
37 ASYNC PWMAOE EPWM14 EPWM14 EPWM14 EPWM14
38 ASYNC PWMB EPWM14 EPWM14 EPWM14 EPWM14
39 ASYNC PWMBOE EPWM14 EPWM14 EPWM14 EPWM14
40 ASYNC PWMA EPWM15 EPWM15 EPWM15 EPWM15
41 ASYNC PWMAOE EPWM15 EPWM15 EPWM15 EPWM15
42 ASYNC PWMB EPWM15 EPWM15 EPWM15 EPWM15
43 ASYNC PWMBOE EPWM15 EPWM15 EPWM15 EPWM15
44 ASYNC PWMA EPWM16 EPWM16 EPWM16 EPWM16
45 ASYNC PWMAOE EPWM16 EPWM16 EPWM16 EPWM16
46 ASYNC PWMB EPWM16 EPWM16 EPWM16 EPWM16
47 ASYNC PWMBOE EPWM16 EPWM16 EPWM16 EPWM16
48 ASYNC INPUT1 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
49 ASYNC INPUT2 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
50 ASYNC INPUT3 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
51 ASYNC INPUT4 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
52 ASYNC INPUT5 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
53 ASYNC INPUT6 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
54 ASYNC INPUT7 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
55 ASYNC INPUT8 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
56 ASYNC INPUT9 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
57 ASYNC INPUT10 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
58 ASYNC INPUT11 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
59 ASYNC INPUT12 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
60 ASYNC INPUT13 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
61 ASYNC INPUT14 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
62 ASYNC INPUT15 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR
63 ASYNC INPUT16 CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR CLB INPUT XBAR

NOTE: For the signals marked as ASYNC, the input filter synchronizer must be enabled.

1132 Configurable Logic Block (CLB) SPRUII0B – May 2019 – Revised May 2020
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The GPREG is accessible by the CPU and the bits of this register can be used as BOUNDARY INPUTs
for the CLB Tiles. For example, CLB1's GPREG[0] can be used as BOUNDARY IN0 (Cell Input 0) for the
corresponding CLB Tile.
In order to connect multiple tiles to each other, the user can either use the CLBx OUT4/5 and connect it to
CLBy BOUNDARY INz through the CLB X-BAR and the Global Signals Mux.
Another option is to connect the CLBx OUT0-7 to a GPIO and then use the INPUT X-BAR to bring the
signal back in to the device and connect it to the CLBy BOUNDARY INz through the CLB X-BAR and the
Global Signals Mux.
In order to use GPIOs as inputs to the CLB, the user must utilize the Input X-BAR and the CLB X-BAR.
Figure 9-5 shows how GPIOs can be used as inputs to the CLB tiles.

Figure 9-5. GPIO to CLB Tile Connections

GPIO0 Asynchronous
to Synchronous Input X-BAR
GPIOx Sync. + Qual

INPUT1 ± INPUT6
Other Sources CLBx TILE
OUT4/5

CLB INPUT X-BAR CLB X-BAR

AUXSIG0 ± AUXSIG7
Other Sources
CLB

CLB TILE1

GPREG CELL
CLB Global Signals
IN0-7

Local OUT 0-7

Signals

.
.
. CLB Tile Outputs
INPUT1 ± INPUT16 x Intersect other Peripherals
x OUTPUT X-BAR
CLB TILEx

GPREG CELL

IN0-7

Local OUT 0-7

Signals

All CLB Tile Outputs

CLB OUTPUT X-BAR

GPIO MUX

SPRUII0B – May 2019 – Revised May 2020 Configurable Logic Block (CLB) 1133
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9.3.3 CLB Output Selection

The eight outputs of the CLB are replicated to create 16 output signals. Each of these 16 outputs has a
separate enable bit defined in the CLB output enable register, CLB_OUT_EN_REG. The CLB outputs go
to the ePWM, eCAP, eQEP and the crossbar module in the device. This allows the user to enhance the
functionality of these modules with the CLB. Figure 9-6 shows the CLB outputs.
Starting with CLB Type 2, the eight outputs that were replicated to create the 16 output signals (shown in
Figure 9-6) are replicated twice more to generate a total of 32 outputs (this is not shown in the figure).
Some of these new outputs can be used for TILE to TILE connection through the CLB Global Mux inputs.

Figure 9-6. CLB Outputs

CLBx_OUT0

CLBx_OUT1

CLBx_OUT2

CLBx_OUT3
8 CLB
outputs
CLBx_OUT4

CLBx_OUT5

CLBx_OUT6

CLBx_OUT7

CLBx_OUT8

CLBx_OUT9

CLBx_OUT10

CLBx_OUT11

CLBx_OUT12

CLBx_OUT13

CLBx_OUT14

CLBx_OUT15

1134 Configurable Logic Block (CLB) SPRUII0B – May 2019 – Revised May 2020
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9.3.4 Peripheral Signal Multiplexer

Each CLB output signal passes through an external multiplexer that intersects a specific peripheral signal.
The output of the multiplexer is connected to the destination of the original peripheral signal and the
default multiplexer setting is that the peripheral signal is passed through. The multiplexer is controlled by a
bit in the CLB output enable register CLB_OUT_EN.
Table 9-3 shows the allocation of peripheral signals and the CLB outputs with which they are multiplexed.

Table 9-3. Peripheral Signal Multiplexer Table

CLB Instance CLB Output Signal Peripheral Signal Peripheral Name
CLB1
CLB1 CLB1_OUT0_0 PWMA EPWM1
CLB1 CLB1_OUT1_0 PWMA_OE EPWM1
CLB1 CLB1_OUT2_0 PWMB EPWM1
CLB1 CLB1_OUT3_0 PWMB_OE EPWM1
CLB1 CLB1_OUT4_0 AQ_PWMA EPWM1
CLB1 CLB1_OUT5_0 AQ_PWMB EPWM1
CLB1 CLB1_OUT6_0 DB_PWMA EPWM1
CLB1 CLB1_OUT7_0 DB_PWMB EPWM1
CLB1 CLB1_OUT0_1 QCLK EQEP1
CLB1 CLB1_OUT1_1 QDIR EQEP1
CLB1 CLB1_OUT2_1 QB EQEP1
CLB1 CLB1_OUT3_1 QA EQEP1
CLB1 CLB1_OUT4_1 - All XBARs (CLB, OUTPUT, EPWM)
CLB1 CLB1_OUT5_1 - All XBARs (CLB, OUTPUT, EPWM)
CLB1 CLB1_OUT6_1 ECAPIN 16 ECAP1, ECAP2
CLB1 CLB1_OUT7_1 ECAPIN 17 ECAP1, ECAP2
CLB1 CLB_OUT16 Global Mux
CLB1 CLB_OUT17 Global Mux
CLB1 CLB_OUT18 Global Mux
CLB1 CLB_OUT19 Global Mux
CLB1 CLB_OUT20 Global Mux
CLB1 CLB_OUT21 SPISTE(OUT) SPIA,Global Mux
CLB1 CLB_OUT22 SPISIMO(OUT) SPIA,Global Mux
CLB1 CLB_OUT23 SPISOMI(OUT) SPIA,Global Mux
CLB1 CLB_OUT24 SPICLK(IN) SPIA
CLB1 CLB_OUT25 SPISIMO(IN) SPIA
CLB1 CLB_OUT26 SPISTE(IN) SPIA
CLB1 CLB_OUT27 RX SCI1
CLB1 CLB_OUT28 ECAPOUT_EN ECAP1
CLB1 CLB_OUT29 ECAPOUT ECAP1
CLB1 CLB_OUT30 EXT_TRIG_40, PING_TRIG_40 FSITXA,FSITXB
CLB1 CLB_OUT31 EXT_TRIG_41, PING_TRIG_41 FSITXA,FSITXB
CLB2
CLB2 CLB2_OUT0_0 PWMA EPWM2
CLB2 CLB2_OUT1_0 PWMA_OE EPWM2
CLB2 CLB2_OUT2_0 PWMB EPWM2
CLB2 CLB2_OUT3_0 PWMB_OE EPWM2
CLB2 CLB2_OUT4_0 AQ_PWMA EPWM2
CLB2 CLB2_OUT5_0 AQ_PWMB EPWM2
CLB2 CLB2_OUT6_0 DB_PWMA EPWM2
CLB2 CLB2_OUT7_0 DB_PWMB EPWM2
CLB2 CLB2_OUT0_1 QCLK EQEP2
CLB2 CLB2_OUT1_1 QDIR EQEP2

SPRUII0B – May 2019 – Revised May 2020 Configurable Logic Block (CLB) 1135
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Table 9-3. Peripheral Signal Multiplexer Table (continued)

CLB Instance CLB Output Signal Peripheral Signal Peripheral Name
CLB2 CLB2_OUT2_1 QB EQEP2
CLB2 CLB2_OUT3_1 QA EQEP2
CLB2 CLB2_OUT4_1 - All XBARs (CLB, OUTPUT, EPWM)
CLB2 CLB2_OUT5_1 - All XBARs (CLB, OUTPUT, EPWM)
CLB2 CLB2_OUT6_1 ECAPIN 16 ECAP3, ECAP4, ECAP5
CLB2 CLB2_OUT7_1 ECAPIN 17 ECAP3, ECAP4, ECAP6
CLB2 CLB_OUT16 Global Mux
CLB2 CLB_OUT17 Global Mux
CLB2 CLB_OUT18 Global Mux
CLB2 CLB_OUT19 Global Mux
CLB2 CLB_OUT20 Global Mux
CLB2 CLB_OUT21 SPISTE(OUT) SPIB,Global Mux
CLB2 CLB_OUT22 SPISIMO(OUT) SPIB,Global Mux
CLB2 CLB_OUT23 SPISOMI(OUT) SPIB,Global Mux
CLB2 CLB_OUT24 SPICLK(IN) SPIB
CLB2 CLB_OUT25 SPISIMO(IN) SPIB
CLB2 CLB_OUT26 SPISTE(IN) SPIB
CLB2 CLB_OUT27 RX SCI2
CLB2 CLB_OUT28 ECAPOUT_EN ECAP2
CLB2 CLB_OUT29 ECAPOUT ECAP2
CLB2 CLB_OUT30 EXT_TRIG_42, PING_TRIG_42 FSITXA,FSITXB
CLB2 CLB_OUT31 EXT_TRIG_43, PING_TRIG_43 FSITXA,FSITXB
CLB3
CLB3 CLB3_OUT0_0 PWMA EPWM3
CLB3 CLB3_OUT1_0 PWMA_OE EPWM3
CLB3 CLB3_OUT2_0 PWMB EPWM3
CLB3 CLB3_OUT3_0 PWMB_OE EPWM3
CLB3 CLB3_OUT4_0 AQ_PWMA EPWM3
CLB3 CLB3_OUT5_0 AQ_PWMB EPWM3
CLB3 CLB3_OUT6_0 DB_PWMA EPWM3
CLB3 CLB3_OUT7_0 DB_PWMB EPWM3
CLB3 CLB3_OUT0_1 QA EQEP3
CLB3 CLB3_OUT1_1 QB EQEP3
CLB3 CLB3_OUT2_1 QDIR EQEP3
CLB3 CLB3_OUT3_1 QCLK EQEP3
CLB3 CLB3_OUT4_1 - All XBARs (CLB, OUTPUT, EPWM)
CLB3 CLB3_OUT5_1 - All XBARs (CLB, OUTPUT, EPWM)
CLB3 CLB3_OUT6_1 ECAPIN 16 HRCAP6, HRCAP7
CLB3 CLB3_OUT7_1 ECAPIN 17 HRCAP6, HRCAP8
CLB3 CLB_OUT16 Global Mux
CLB3 CLB_OUT17 Global Mux
CLB3 CLB_OUT18 Global Mux
CLB3 CLB_OUT19 Global Mux
CLB3 CLB_OUT20 Global Mux
CLB3 CLB_OUT21 SPISTE(OUT) SPIC,Global Mux
CLB3 CLB_OUT22 SPISIMO(OUT) SPIC,Global Mux
CLB3 CLB_OUT23 SPISOMI(OUT) SPIC,Global Mux
CLB3 CLB_OUT24 SPICLK(IN) SPIC
CLB3 CLB_OUT25 SPISIMO(IN) SPIC
CLB3 CLB_OUT26 SPISTE(IN) SPIC
CLB3 CLB_OUT27 RX SCI3

1136Configurable Logic Block (CLB) SPRUII0B – May 2019 – Revised May 2020
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Table 9-3. Peripheral Signal Multiplexer Table (continued)

CLB Instance CLB Output Signal Peripheral Signal Peripheral Name
CLB3 CLB_OUT28 ECAPOUT_EN ECAP3
CLB3 CLB_OUT29 ECAPOUT ECAP3
CLB3 CLB_OUT30 EXT_TRIG_44, PING_TRIG_44 FSITXA,FSITXB
CLB3 CLB_OUT31 EXT_TRIG_45, PING_TRIG_45 FSITXA,FSITXB
CLB4
CLB4 CLB4_OUT0_0 PWMA EPWM4
CLB4 CLB4_OUT1_0 PWMA_OE EPWM4
CLB4 CLB4_OUT2_0 PWMB EPWM4
CLB4 CLB4_OUT3_0 PWMB_OE EPWM4
CLB4 CLB4_OUT4_0 AQ_PWMA EPWM4
CLB4 CLB4_OUT5_0 AQ_PWMB EPWM4
CLB4 CLB4_OUT6_0 DB_PWMA EPWM4
CLB4 CLB4_OUT7_0 DB_PWMB EPWM4
CLB4 CLB4_OUT0_1 QA EQEP4
CLB4 CLB4_OUT1_1 QB EQEP4
CLB4 CLB4_OUT2_1 QDIR EQEP4
CLB4 CLB4_OUT3_1 QCLK EQEP4
CLB4 CLB4_OUT4_1 - All XBARs (CLB, OUTPUT, EPWM)
CLB4 CLB4_OUT5_1 - All XBARs (CLB, OUTPUT, EPWM)
CLB4 CLB4_OUT6_1 ECAPIN 18 HRCAP6, HRCAP7
CLB4 CLB4_OUT7_1 ECAPIN 19 HRCAP6, HRCAP8
CLB4 CLB_OUT16 Global Mux
CLB4 CLB_OUT17 Global Mux
CLB4 CLB_OUT18 Global Mux
CLB4 CLB_OUT19 Global Mux
CLB4 CLB_OUT20 Global Mux
CLB4 CLB_OUT21 SPISTE(OUT) SPID,Global Mux
CLB4 CLB_OUT22 SPISIMO(OUT) SPID,Global Mux
CLB4 CLB_OUT23 SPISOMI(OUT) SPID,Global Mux
CLB4 CLB_OUT24 SPICLK(IN) SPID,Global Mux
CLB4 CLB_OUT25 SPISIMO(IN) SPID
CLB4 CLB_OUT26 SPISTE(IN) SPID
CLB4 CLB_OUT27 RX SCI4
CLB4 CLB_OUT28 ECAPOUT_EN ECAP4
CLB4 CLB_OUT29 ECAPOUT ECAP4
CLB4 CLB_OUT30 EXT_TRIG_46, PING_TRIG_46 FSITXA,FSITXB
CLB4 CLB_OUT31 EXT_TRIG_47, PING_TRIG_47 FSITXA,FSITXB
CLB5
CLB5 CLB5_OUT0_0 PWMA EPWM5
CLB5 CLB5_OUT1_0 PWMA_OE EPWM5
CLB5 CLB5_OUT2_0 PWMB EPWM5
CLB5 CLB5_OUT3_0 PWMB_OE EPWM5
CLB5 CLB5_OUT4_0 AQ_PWMA EPWM5
CLB5 CLB5_OUT5_0 AQ_PWMB EPWM5
CLB5 CLB5_OUT6_0 DB_PWMA EPWM5
CLB5 CLB5_OUT7_0 DB_PWMB EPWM5
CLB5 CLB5_OUT0_1 - -
CLB5 CLB5_OUT1_1 - -
CLB5 CLB5_OUT2_1 - -
CLB5 CLB5_OUT3_1 - -
CLB5 CLB5_OUT4_1 - All XBARs (CLB, OUTPUT, EPWM)

SPRUII0B – May 2019 – Revised May 2020 Configurable Logic Block (CLB) 1137
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Table 9-3. Peripheral Signal Multiplexer Table (continued)

CLB Instance CLB Output Signal Peripheral Signal Peripheral Name
CLB5 CLB5_OUT5_1 - All XBARs (CLB, OUTPUT, EPWM)
CLB5 CLB5_OUT6_1 ECAPIN 18 ECAP1, ECAP2
CLB5 CLB5_OUT7_1 ECAPIN 19 ECAP1, ECAP2
CLB5 CLB_OUT16 Global Mux
CLB5 CLB_OUT17 Global Mux
CLB5 CLB_OUT18 Global Mux
CLB5 CLB_OUT19 Global Mux
CLB5 CLB_OUT20 Global Mux
CLB5 CLB_OUT21 Global Mux
CLB5 CLB_OUT22 Global Mux
CLB5 CLB_OUT23 Global Mux
CLB5 CLB_OUT24
CLB5 CLB_OUT25 SEL_TDM_PATH FSITXA
CLB5 CLB_OUT26
CLB5 CLB_OUT27
CLB5 CLB_OUT28 ECAPOUT_EN ECAP5
CLB5 CLB_OUT29 ECAPOUT ECAP5
CLB5 CLB_OUT30 EXT_TRIG_48, PING_TRIG_48 FSITXA, FSITXB
CLB5 CLB_OUT31 EXT_TRIG_49, PING_TRIG_49 FSITXA, FSITXB
CLB6
CLB6 CLB6_OUT0_0 PWMA EPWM6
CLB6 CLB6_OUT1_0 PWMA_OE EPWM6
CLB6 CLB6_OUT2_0 PWMB EPWM6
CLB6 CLB6_OUT3_0 PWMB_OE EPWM6
CLB6 CLB6_OUT4_0 AQ_PWMA EPWM6
CLB6 CLB6_OUT5_0 AQ_PWMB EPWM6
CLB6 CLB6_OUT6_0 DB_PWMA EPWM6
CLB6 CLB6_OUT7_0 DB_PWMB EPWM6
CLB6 CLB6_OUT0_1 - -
CLB6 CLB6_OUT1_1 - -
CLB6 CLB6_OUT2_1 - -
CLB6 CLB6_OUT3_1 - -
CLB6 CLB6_OUT4_1 - All XBARs (CLB, OUTPUT, EPWM)
CLB6 CLB6_OUT5_1 - All XBARs (CLB, OUTPUT, EPWM)
CLB6 CLB6_OUT6_1 ECAPIN 18 ECAP3
CLB6 CLB6_OUT7_1 ECAPIN 19 ECAP3
CLB6 CLB_OUT16 Global Mux
CLB6 CLB_OUT17 Global Mux
CLB6 CLB_OUT18 Global Mux
CLB6 CLB_OUT19 Global Mux
CLB6 CLB_OUT20 Global Mux
CLB6 CLB_OUT21 Global Mux
CLB6 CLB_OUT22 Global Mux
CLB6 CLB_OUT23 Global Mux
CLB6 CLB_OUT24
CLB6 CLB_OUT25 SEL_TDM_PATH FSITXB
CLB6 CLB_OUT26
CLB6 CLB_OUT27
CLB6 CLB_OUT28 ECAPOUT_EN ECAP6
CLB6 CLB_OUT29 ECAPOUT ECAP6
CLB6 CLB_OUT30 EXT_TRIG_50, PING_TRIG_50 FSITXA, FSITXB

1138Configurable Logic Block (CLB) SPRUII0B – May 2019 – Revised May 2020
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Table 9-3. Peripheral Signal Multiplexer Table (continued)

CLB Instance CLB Output Signal Peripheral Signal Peripheral Name
CLB6 CLB_OUT31 EXT_TRIG_51, PING_TRIG_51 FSITXA, FSITXB
CLB7
CLB7 CLB7_OUT0_0 PWMA EPWM7
CLB7 CLB7_OUT1_0 PWMA_OE EPWM7
CLB7 CLB7_OUT2_0 PWMB EPWM7
CLB7 CLB7_OUT3_0 PWMB_OE EPWM7
CLB7 CLB7_OUT4_0 AQ_PWMA EPWM7
CLB7 CLB7_OUT5_0 AQ_PWMB EPWM7
CLB7 CLB7_OUT6_0 DB_PWMA EPWM7
CLB7 CLB7_OUT7_0 DB_PWMB EPWM7
CLB7 CLB7_OUT0_1 - -
CLB7 CLB7_OUT1_1 - -
CLB7 CLB7_OUT2_1 - -
CLB7 CLB7_OUT3_1 - -
CLB7 CLB7_OUT4_1 - All XBARs (CLB, OUTPUT, EPWM)
CLB7 CLB7_OUT5_1 - All XBARs (CLB, OUTPUT, EPWM)
CLB7 CLB7_OUT6_1 ECAPIN 18 ECAP4
CLB7 CLB7_OUT7_1 ECAPIN 19 ECAP4
CLB7 CLB_OUT16 Global Mux
CLB7 CLB_OUT17 Global Mux
CLB7 CLB_OUT18 Global Mux
CLB7 CLB_OUT19 Global Mux
CLB7 CLB_OUT20 Global Mux
CLB7 CLB_OUT21 Global Mux
CLB7 CLB_OUT22 Global Mux
CLB7 CLB_OUT23 Global Mux
CLB7 CLB_OUT24
CLB7 CLB_OUT25
CLB7 CLB_OUT26
CLB7 CLB_OUT27
CLB7 CLB_OUT28 ECAPOUT_EN ECAP7
CLB7 CLB_OUT29 ECAPOUT ECAP7
CLB7 CLB_OUT30
CLB7 CLB_OUT31
CLB8
CLB8 CLB8_OUT0_0 PWMA EPWM8
CLB8 CLB8_OUT1_0 PWMA_OE EPWM8
CLB8 CLB8_OUT2_0 PWMB EPWM8
CLB8 CLB8_OUT3_0 PWMB_OE EPWM8
CLB8 CLB8_OUT4_0 AQ_PWMA EPWM8
CLB8 CLB8_OUT5_0 AQ_PWMB EPWM8
CLB8 CLB8_OUT6_0 DB_PWMA EPWM8
CLB8 CLB8_OUT7_0 DB_PWMB EPWM8
CLB8 CLB8_OUT0_1 - -
CLB8 CLB8_OUT1_1 - -
CLB8 CLB8_OUT2_1 - -
CLB8 CLB8_OUT3_1 - -
CLB8 CLB8_OUT4_1 - All XBARs (CLB, OUTPUT, EPWM)
CLB8 CLB8_OUT5_1 - All XBARs (CLB, OUTPUT, EPWM)
CLB8 CLB8_OUT6_1 ECAPIN 18 ECAP5
CLB8 CLB8_OUT7_1 ECAPIN 19 ECAP5

SPRUII0B – May 2019 – Revised May 2020 Configurable Logic Block (CLB) 1139
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Table 9-3. Peripheral Signal Multiplexer Table (continued)

CLB Instance CLB Output Signal Peripheral Signal Peripheral Name
CLB8 CLB_OUT16 Global Mux
CLB8 CLB_OUT17 Global Mux
CLB8 CLB_OUT18 Global Mux
CLB8 CLB_OUT19 Global Mux
CLB8 CLB_OUT20 Global Mux
CLB8 CLB_OUT21 Global Mux
CLB8 CLB_OUT22 Global Mux
CLB8 CLB_OUT23 Global Mux
CLB8 CLB_OUT24
CLB8 CLB_OUT25
CLB8 CLB_OUT26
CLB8 CLB_OUT27
CLB8 CLB_OUT28
CLB8 CLB_OUT29
CLB8 CLB_OUT30
CLB8 CLB_OUT31

Figure 9-7. Peripheral Signal Multiplexer

CLB_OEN[n]

PERIPHERAL
SIGNAL 0
MULTIPLEXED
OUTPUT
SIGNAL
CLBx_OUTn 1

For example, if the CLB1 OUT0 must override the EPWM1A signal, the OUPTUT ENABLE bit for OUT0
must be set.

9.4 CLB Tile

The purpose of the CLB tile is to provide the logic reconfiguration capability of the CLB. The CLB tile
contains the following submodules:
• Counter
The counter submodule can be configured either as an adder, a counter, or a shifter. When functioning
as an adder, it can either add or subtract. When functioning as a counter, it can count up or count
down. When functioning as a shifter, it can shift left or shift right. The counter event inputs, as well as
the reset input, may be freely connected to any of the other submodules in the same tile. There are
three counters in each tile.
• LUT4
The LUT4 submodule has a 4-input look-up table functionality and is capable of realizing any
combinatorial Boolean equation of up to four inputs. There are three LUT4 submodules in each CLB
tile.
• FSM
The Finite State Machine (FSM) submodule can be configured either as a single four-state finite state
machine, or as two independent two-state finite state machines. The FSM accepts two external inputs,
and generates two state outputs and one combinational output. When not used as a state machine, the
FSM submodule can accept two external inputs and function as a 4-input LUT. There are three FSM
submodules in each CLB tile.

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• Output LUT
The output LUT is a 3-input lookup table submodule capable of realizing any combinatorial Boolean
equation of up to three inputs. There are eight such blocks in a CLB tile, each associated with one of
the tile outputs.
• Asynchronous Output Conditioning Block
The primary purpose of the Asynchronous Output Conditioning (AOC) block is to provide
asynchronous conditioning capabilities on the TILE outputs or directly on the inputs of the TILE.
• High Level Controller
The High Level Controller (HLC) submodule is an event-driven block that can handle up to four
concurrent events. The event can be an activity on any of the other block outputs. A predefined set of
operations is executed when each event occurs. The HLC also provides a data exchange and interrupt
mechanism to the CPU subsystem. There are four working registers (R0, R1, R2, and R3) which can
be used for basic operations, and to modify or set up values for the three counter blocks. Unlike the
other submodules, there is only one HLC in each CLB tile.
• Configurable Switch Block
The configurable switch block provides dynamic connectivity between all of the blocks listed above.
Submodules can be connected by the user, with the sole restriction that they must not form a
combinational loop within the tile.
A CLB tile consists of three sets each of the counter block, FSM, and LUT4, one high-level controller, and
eight output LUT blocks. The submodule numbering is shown in Figure 9-8.
The functionality of the LUT submodules is configured using a register field containing the binary pattern
of the output of the desired look-up table. For example, a 4-input LUT has 16 possible input permutations,
each of which corresponds to a desired binary 0 or 1 at its output. The register field would therefore be
16-bits in length, with each bit representing the desired result of a binary pattern. Input pattern sequences
start at 0000 and continue sequentially to 1111. A similar method is used to encode the 16-bit state
equations in the FSM submodule.

Figure 9-8. CLB Tile Submodules

LUT3_0
High Level Controller Counter_0 LUT4_0 FSM_0
(HLC)

LUT3_1

Counter_1 LUT4_1 FSM_1 CLB

Outputs

External Reconfigurable
Inputs Switch Block
8 Counter_2 LUT4_2 FSM_2
LUT3_7

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9.4.1 Static Switch Block

The Static Switch Block provides the configurable connectivity between the submodules in the CLB tile.
The outputs of all the submodules and the eight external inputs are connected to a common internal bus
inside the tile. Every input port has a 32-to-1 multiplexer and an associated 5-bit selection value that
allows the user to select one of the inputs on the bus. The only restrictions are certain signals (described
below) that are tied off in the design to prevent creation of accidental combinatorial loops.

Table 9-4. Output Table

Bit Position Signal Connection Comment
0 Always ‘0’ This select value will be used to tie an input to ‘0’.
1 COUNTER_0 MATCH2
2 COUNTER_0 ZERO
3 COUNTER_0 MATCH1
4 FSM_0 STATE_BIT_0
5 FSM_0 STATE_BIT_1
6 FSM_0 LUT output
7 LUT4_0 output
8 Always ‘1’ This select value will be used to tie an input to ‘1’.
9 COUNTER_1 MATCH2
10 COUNTER_1 ZERO
11 COUNTER_1 MATCH1
12 FSM_1 STATE_BIT_0
13 FSM_1 STATE_BIT_1
14 FSM_1 LUT output
15 LUT4_1 output
16 Always ‘0’
17 COUNTER_2 MATCH2
18 COUNTER_2 ZERO
19 COUNTER_2 MATCH1
20 FSM_2 STATE_BIT_0
21 FSM_2 STATE_BIT_1
22 FSM_2 LUT output
23 LUT4_2 output
24 External Input 0
25 External Input 1
26 External Input 2
27 External Input 3
28 External Input 4
29 External Input 5
30 External Input 6
31 External Input 7

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Table 9-5. Input Table

Module Name Port Name Description
Counter Block RESET Acts as an active high reset when used as a counter
MODE_0 Acts as a enable when used as a counter. The counter will count only
when this input is ‘1’.
MODE_1 Acts as a direction control when used as a counter. If this input is ‘1’, then
the counter counts up else, it counts down.
LUT IN0 Input 0 of the 4-input LUT.
IN1 Input 1 of the 4-input LUT.
IN2 Input 2 of the 4-input LUT.
IN3 Input 3 of the 4-input LUT.
FSM EXT_IN0 Input 0 of the FSM block.
EXT_IN1 Input 1 of the FSM block.
EXTRA_EXT_IN0 Extra external Input 0 of the FSM block. This input matters only if it is
configured in the LUT mode.
EXTRA_EXT_IN1 Extra external Input 1 of the FSM block. This input matters only if it is
configured in the LUT mode.

The static switch block allows the user to define the input connection of any submodule to come from any
of the outputs in Table 9-4. It is therefore easy to create a combinatorial loop. In order to prevent this,
certain paths are broken in the input path of each submodule. These port positions are tied to '0', as
shown in Table 9-6.

Table 9-6. Ports Tied Off to Prevent Combinatorial Loops

Module Name Ports of Input MUX Tied Off to ‘0’ to Prevent Combinational Loops
LUT_0 LUT_0 , LUT_1 and LUT_2 output, FSM_0, FSM_1 and FSM_2 output.
FSM_0 LUT_1 and LUT_2 output, FSM_0, FSM_1 and FSM_2 output.
LUT_1 LUT_1 and LUT_2 output, FSM_1 and FSM_2 output.
FSM_1 LUT_2 output, FSM_1 and FSM_2 output.
LUT_2 LUT_2 output, FSM_2 output.
FSM_2 FSM_2 output.

9.4.2 Counter Block

9.4.2.1 Counter Description

The counter block is a complex functional submodule that can be configured either as a counter, an adder,
or a shifter. Apart from the normal operational control, this block has a dedicated EVENT input, which can
trigger an addition, subtraction or shift operation, or load data into the counter register. The inputs to the
counter sub are shown in Figure 9-9.

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Figure 9-9. Counter Block

RESET

ZERO
MODE 0
These inputs can be
driven by outputs of These outputs drive
other blocks or by MATCH1
MODE 1 inputs on other blocks
external inputs

MATCH2
EVENT

Counter Block
MATCH1 REF

MATCH2 REF Counter

These inputs are Value
controlled by LOAD VALUE
registers

Static Controls
for ADD/SHIFT/
DIR

9.4.2.2 Counter Operation

At the heart of the counter block is a 32-bit count register. This register can either be loaded statically
before counting commences, or dynamically at run time. The operation of the counter submodule is
determined by the inputs described below. Note that each of the inputs can be connected to the outputs of
any of the other blocks in the CLB tile. These connections are made by configuring the configurable switch
block.
The counter inputs are as follows.
• RESET: This is the highest priority input and takes precedence over all other inputs. The input is level
sensitive and as long as it remains high, the counter will reset to 0 on the next clock cycle.
• MODE_0: This input is an enable for the counter. The counter begins counting (up or down depending
on the MODE_1 setting) only when this input is high. If this input is low, then no counting takes place.
• MODE_1: This input is the direction control for the counter. If this input is high, then the counter will
increment on every clock cycle where it sees MODE_0 to be high. If this input is low, then the counter
decrements for every clock cycle it sees MODE_0 high. The counter wraps around to 0x00000000
after 0xFFFFFFFF when counting up. The counter wraps around to 0xFFFFFFFF after 0x00000000
when counting down. The only exception to this is when an EVENT occurs at exactly the same time,
causing a different value to be loaded into the counter.
• EVENT: This input is defined for the purpose of triggering actions in the counter based on certain
events. The event itself can be any of the outputs of the other blocks or an external input to the tile.
The counter’s static control inputs define the behavior of the counter on an active event. An active
event is defined as a rising edge on the EVENT input. The counter can be configured to perform one of
the following actions:
– Load a predefined 32-bit value from the LOAD VALUE register into the count register
– Shift the contents of the counter register left or right by a predefined amount between 0 and 31
– Add or subtract a predefined 32-bit value. Addition and subtraction are treated as 32-bit unsigned
operations and there is no saturation.
Note that the effect of a rising edge on the EVENT input only lasts for one cycle. On the next cycle, the
counter operation will continue based on the MODE_0, MODE_1, and RESET inputs.

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MATCH1 REF and MATCH2 REF are 32-bit reference values that are used to generate the MATCH1 and
MATCH2 outputs. The MATCH1 output becomes active high whenever the counter register value matches
the 32-bit MATCH1 REF value. MATCH2 behaves in a similar manner in relation to the MATCH2 REF
register. The reference values for MATCH1 and MATCH2 can either be setup once before the start of
operation, or can be modified dynamically. The High Level Controller can load desired values into the
MATCH1 REF and MATCH2 REF registers.
Note that the counter load and match registers are not memory-mapped. For more information, see
Table 9-13.
The three logic outputs of the counter block are as follows:
• ZERO: This output goes high whenever the counter register is 0.
• MATCH1: This output goes high whenever the counter register is equal to the MATCH1 REF input
register.
• MATCH2: This output goes high whenever the counter register is equal to the MATCH2 REF input
register.
The operation of the counter block is controlled by the CFG_MISC_CTRL register. The following three bits
of this register are relevant for each counter. The “x” below refers to the counter instance; 0, 1, or 2. For
more information, see the CLB_MISC_CONTROL register description located in Section 9.6.
• COUNT_EVENT_CTRL_x: This bit defines whether the counter performs an addition or a shift on an
event. A value of 0 means that on an event, the counter will just load the static value; 1 means and
add/shift operation will be performed.
• COUNT_ADD_SHIFT_x. 1 means add, 0 means shift.
• COUNT_DIR_x. 1 means left shift or add. 0 means right shift or subtract.
Table 9-7 shows the logical operation of the counter block in terms of the inputs and control register bits.
Count up and down modes are the normal operation with EVENT = 0. The operations on the CNTVAL
register are as follows:
Load: CNTVAL = EVENT_LOAD_VAL
Shift right: CNTVAL = CNTVAL >> EVENT_LOAD_VAL
Shift left: CNTVAL = CNTVAL << EVENT_LOAD_VAL
Subtract: CNTVAL = CNTVAL - EVENT_LOAD_VAL
Add: CNTVAL = CNTVAL + EVENT_LOAD_VAL

Table 9-7. Counter Block Operating Modes

Action on
EVENT MODE_0 MODE_1 COUNT_EVENT_CTRL_x COUNT_ADD_SHIFT_x COUNT_DIR_x CNTVAL
0 0 0 X X X None
0 0 1 X X X None
0 1 0 X X X Count down
0 1 1 X X X Count up
1 X X 0 X X Load
1 X X 1 0 0 Shift right
1 X X 1 0 1 Shift left
1 X X 1 1 0 Subtract
1 X X 1 1 1 Add

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9.4.2.3 Serializer Mode

Starting with CLB Type 2, the Counter module can operate as a serializer. In this mode of operation, this
module acts as a shift register (also referred to as a serializer). In serializer mode of operation, the EVENT
input is used to shift one bit of data into the serializer. Either of MATCH1 and MATCH2 can be configured
to send out the shift register data.Using the MATCH1/2_TAP_SEL bit of
CLB_COUNT_MATCH_TAP_SEL, any bit position of the counter can be brought out on the
MATCH1/MATCH2 outputs. The shifting and direction of the counter in this mode is controlled by
MODE_0(enable) and MODE_1(direction).
To enable the Serializer mode, CLB_MISC_CONTROL.COUNT_SERIALIZER_0 (for Counter 0) must be
set.

9.4.2.4 Linear Feedback Shift Register (LFSR) Mode

Starting with CLB Type 2, the Counter module can operate as a linear feedback shift register. By
configuring the characteristics of the LFSR, the counter module can be used to compute the CRC on a
serial bit stream. The polynomial for LFSR is in the MATCH2 reference register. The feedback bit position
is in the MATCH1 reference register.
To enable the Serializer mode, CLB_MISC_CONTROL.COUNT_SERIALIZER_0 (for Counter 0) must be
set along with COUNT0_LFSR_EN.
There are two types of LSFR which can be selected by changing MODE1 value (0 or 1). These are show
in Figure 9-10.

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Figure 9-10. LFSR Modes

Structure for LFSR Type 1 (MODE_1 = 0)
CNT_VAL is the 32-ELW FRXQWHU¶V DFWLYH UHJLVWHU
CNT_VAL_next is the 32-bit value to be written into CNT_VAL on the next active cycle
(clock edge when MODE_0 == 1)
LFSR_MSB = MATCH1_REF[4:0]
Poly[31:0] is MATCH2_REF which acts as the CRC polynomial

LFSR_MSB

EVENT Poly[31] Poly[30] Poly[0]

(serial input)

CNT_VAL[30] CNT_VAL[29] µ0¶

CNT_VAL_next[31] CNT_VAL_next[30] CNT_VAL_next[0]

Structure for LFSR Type 2 (MODE_1 = 1)

CNT_VAL is the 32-bit counter register
CNT_VAL_next is the 32-bit value to be written into CNT_VAL on the next active cycle
(clock edge when MODE_0 == 1)
LFSR_MSB = MATCH1_REF[4:0]
Poly[31:0] is MATCH2_REF which acts as the CRC polynomial

LFSR_MSB

Poly[31] Poly[30] Poly[0]

CNT_VAL[30] CNT_VAL[29] EVENT

(serial input)

CNT_VAL_next[31] CNT_VAL_next[30] CNT_VAL_next[0]

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9.4.3 FSM Block

The Finite State Machine (FSM) block provides the ability to build programmable finite state machines with
up to four states. It has two register bits and two external inputs, and can be programmed either as two 2-
state machines or as a single 4-state machines. For additional flexibility, there are two auxiliary inputs
(EXTRA_EXT_IN0 and EXTRA_EXT_IN1) that can be used to create larger combinational functions by
giving up a state functionality. The structure of the FSM is shown in Figure 9-11.

Figure 9-11. FSM Block

EXTRA_EXT_IN1
Output LUT FSM_LUT_OUT
These inputs can EXTRA_EXT_IN0
be driven by
outputs of other
blocks or by EXT_IN1
S0
external inputs Next State
LUT
EXT_IN0

16-bit S0 next S1
state function Next State
LUT

These inputs are

16-bit S1 next
controlled by S0
state function FSM_S0
registers

16-bit S1 FSM_S1
FSM_LUT_OUT
state function

The signals and functionality of the FSM block are:

• EXT_IN0 and EXT_IN1: These are the two external inputs that can be used to control the output
FSM_LUT_OUT or either of the states S0 and S1.
• S0 and S1 are two state bits that have independent state control equations.
• 16-bit S0 equation defines a function (EXT_IN1, EXT_IN0, S1, S0). The four bits in the order defined
are used as an index into the 16-bit register to decide the next state of S0.
• 16-bit S1 equation defines a function (EXT_IN1, EXT_IN0, S1, S0). The four bits in the order defined
are used as an index into the 16-bit register to decide the next state of S1.
• 16-bit output equation defines a function (EXT_IN1, EXT_IN0, S1, S0). The four bits in the order
defined are used as an index into the 16-bit register to decide the output value of FSM_LUT_OUT. An
additional level of configurability is provided such that FSM_LUT_OUT can use extra inputs in case the
states S0 and S1 are unused.
One extra bit is used to select EXTRA_EXT_IN0 instead of S0. One extra bit is used to select
EXTRA_EXT_IN1 instead of S1. Using these, one can effectively build 3-input or a 4-input LUT for the
FSM_LUT_OUT by giving up one or two state bits, respectively.
The CFG_MISC_CTRL register controls the operation of the FSM block. Two bits in this register are used
for each FSM Block to determine whether the FSM output LUT function uses the state variable S0/S1, or
the corresponding extra external input signal FSM_EXTRA_EXT_INx. ‘0’ means use the state bit, and ‘1’
means use the FSM_EXTRA_EXT_IN0 / FSM_EXTRA_EXT_IN1 signal.

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Figure 9-12. FSM LUT Block

EXTRA_EXT_IN1

These inputs can EXTRA_EXT_IN0

be driven by
outputs of other This output can
EXT_IN1 FSM
blocks or by drive inputs of
LUT FSM_LUT_OUT
external inputs other blocks
Block
EXT_IN0

This input is 16-bit output

controlled by a function
register

9.4.4 LUT4 Block

This is a simple four input Look-Up table (LUT) block with inputs IN0, IN1, IN2, and IN3. Any combinatorial
Boolean equation using the four inputs can be realized by programming the 16-bit control register
associated with each LUT4 block. For more information, see the LUT4 register descriptions located in
Section 9.6.

Figure 9-13. LUT4 Block

IN0

IN1
These inputs can be
driven by outputs of
other blocks or by
IN2 This output can drive
external inputs LUT4 OUT inputs of other blocks
Block
IN3

This input is controlled 16-bit output

by a register function

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9.4.5 Output LUT Block

The output LUT block is very similar in functionality to the LUT4 block, except that it has three inputs.
Unlike the other sub blocks, the outputs of these blocks are meant to go out of the tile and hence they
cannot be used by any other block within the tile. Any combinatorial function of the three inputs can be
realized by the output LUT block. For more information, see the output LUT register descriptions located in
Section 9.6.

Figure 9-14. Output LUT Block

These inputs can IN0

be driven by
outputs of other IN1
blocks or by
external inputs This output goes
IN2 Output out of the CLB tile.
LUT OUT It cannot drive
Block inputs of other
blocks

This input is 16-bit output

controlled by a function
register

9.4.6 Asynchronous Output Conditioning (AOC) Block

The logic in the AOC block is organized into three stages with the inputs passing through different types of
logic modification at each stage before proceeding to the next level. This is shown in Figure 9-15.
There are 8 inputs to this block. Each of these 8 inputs can pick the corresponding BOUNDARY input to
the CLB or the CLB TILE output (for example the INPUT 0 of the AOC block can choose between CLB
BOUNDARY INPUT0 and CLB TILE OUTPUT 0). If the CLB TILE OUTPUT 0 is selected, it is always
registered before being sent to the subsequent asynchronous signal conditioning stages. In each of the
three stages, there is always an option to do nothing and just send the signal as is to the next stage
(bypass).
Stage 1 : The input signal can be inverted before sending it to the next stage.
Stage 2 : The signal coming from Stage 1 can be GATED with a gating control signal. The gating
control signal can either be from a software register or can be any of the CLB TILE outputs. The
GATING function can be a logical AND, OR or XOR.
Stage 3 : The input signal can be used to either set or clear the output on the rising edge of the signal.
This is a purely asynchronous set/clear that occurs without needing any clocks. The release control
signal, when high, will restore the output to it’s default state (HIGH if asynchronous clear is selected
and LOW if asynchronous set is selected). The release control signal can be either from a software
register or can be any of the CLB TILE outputs. Optionally, instead of any of the asynchronous
set/clear operation, the input signal can just be delayed by a clock cycle.

The interaction of the CLB TILE and the AOC block is shown in Figure 9-16.

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Figure 9-15. AOC Block

CLB_OUTPUT_COND_CTRL_0.HW_RLS_CTRL_SEL

S/W Release control

CLB_IN_MUX_SEL_0.SW_RLS_CTRL_0
SET

8 CLB D Q

OUTPUTs
CLR Q

CLB_OUTPUT_COND_CTRL_0.SEL_RELEASE_CTRL

CLB_OUTPUT_COND_CTRL_0.LEVEL_2_SEL

CLB_OUTPUT_COND_CTRL_0.HW_GATING_CTRL_SEL

S/W Gate control

CLB_IN_MUX_SEL_0.SW_GATING_CTRL_0 CLB_OUTPUT_COND_CTRL_0.LEVEL_3_SEL
SET

8 CLB D Q

OUTPUTs
CLR Q

CLB_OUTPUT_COND_CTRL_0.ASYNC_COND_EN
CLB_OUTPUT_COND_CTRL_0.SEL_GATING_CTRL

CLB_OUTPUT_COND_CTRL_0.LEVEL_1_SEL

Stage 1 Stage 2 Stage 3

CLB_OUTPUT_COND_CTRL_0.SEL_RAW_IN SET
SET
S Q
BOUNDARY OUT[0]
CLB_OUT[0]
R CLR Q
BOUNDARY IN[0]
CLEAR
SET
S Q

OUTLUT[0]
R CLR Q
D
SET
Q BYPASS MUX

CLR Q
DELAY
SET
D Q

CLR Q

The input can be either be Stage 1 Stage 2 Stage 3

the BOUNDARY IN[0] or the Two options Four options Four options
BOUNDARY OUT[0]. 1. Bypass Signal 1. Bypass Signal 1. Bypass Signal
This figure is shown for IN[0]/ 2. Invert signal 2. Signal AND Gating_control 2. Signal causes async SET
OUT[0]. The same logic exists 3. Signal OR Gating_control 3. Signal causes async CLR
for all eight IN/OUTs 4. Signal XOR Gating_control 4. Signal delayed by 1 clock

Gating control for Stage 2 can either Release control for Stage 3 can either
be through S/W or a delayed version be through S/W or a delayed version
of one of the 8 CLB outputs of one of the 8 CLB outputs

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Figure 9-16. AOC Block and The CLB TILE

IN0 ± IN7

CLB_OUT

0 OUTLUT0 0
1 OUTLUT1 1 0, 8, 16, 24

BOUNDARY OUT
BOUNDARY IN

1, 9, 17, 25
2 OUTLUT2 2 2,10,18,26
Input from GPREG/Global/ 3 OUTLUT3 Asynchronous Output 3 3,11,19,27
CLB TILE
Local Mux 4 OUTLUT4 Conditioning (AOC) Block 4 4,12,20,28
5 OUTLUT5 5 5,13,21,29
6,14,22,30
6 OUTLUT6 6 7,15,23,31
7 HLC OUTLUT7 7

Note:
CLB_OUT0_1 is the same as CLB_OUT8 or
CLB_OUT4_2 is the same as CLB_OUT20

OUT0 ± OUT7 (delayed by 1 cycle)

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9.4.7 High Level Controller (HLC)

The High Level Controller (HLC) is significantly more complex than the other blocks in the CLB tile. It
performs two main functions:
• Provides a means of communication and data exchange with the rest of the device.
• Provides a programmable, event-based action system, which performs computation, manipulation of
logic functionality, and data movement. In other words, events can be configured to trigger a
predefined set of actions in the CLB tile, or to initiate data exchange with the rest of the device.
The architecture of the HLC is shown in Figure 9-17. It is an event-based system capable of handling up
to four simultaneous events that can be selected from any outputs of the other blocks within the tile or
from an external input.

Figure 9-17. High Level Controller Block

Event 0

Event bus Event 1

containing outputs Each event has a
Event Processing Block
of all the other Cell dedicated address
sub-blocks and Event 2 Instruction Memory
space with up to 8
external inputs instructions

Event 3

R0 R2 Push data to
Global access path shared memory
for CPU system Initiated by the
interface to write to event processing
the registers and R1 R3 block
instruction
Pull data from
memory.
shared memory

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9.4.7.1 High Level Controller Events

Each of the four HLC events has a dedicated address from which instructions are executed. Event 0 is the
highest priority and Event 3 is the lowest priority. Events are selected from the set of signals shown in
Table 9-8. The lowest numbered event (Event 0) has the highest priority, and the highest numbered event
(Event 3) has the lowest priority.

Table 9-8. HLC Event List

Index HLC Event Mux
0 Always ‘0’
1 COUNTER_0 MATCH2
2 COUNTER_0 ZERO
3 COUNTER_0 MATCH1
4 FSM_0 STATE_BIT_0
5 FSM_0 STATE_BIT_1
6 FSM_0 LUT output
7 LUT4_0 output
8 Always ‘1’
9 COUNTER_1 MATCH2
10 COUNTER_1 ZERO
11 COUNTER_1 MATCH1
12 FSM_1 STATE_BIT_0
13 FSM_1 STATE_BIT_1
14 FSM_1 LUT output
15 LUT4_1 output
16 Always ‘0’
17 COUNTER_2 MATCH2
18 COUNTER_2 ZERO
19 COUNTER_2 MATCH1
20 FSM_2 STATE_BIT_0
21 FSM_2 STATE_BIT_1
22 FSM_2 LUT output
23 LUT4_2 output
24 External Input 0
25 External Input 1
26 External Input 2
27 External Input 3
28 External Input 4
29 External Input 5
30 External Input 6
31 External Input 7

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Additional HLC inputs are avaialble starting with Type 2 CLB and later. These inputs can be selected by
choosing the alternate MUX options for the HLC module (HLC_ALT_MUX_SEL_n = 1) shown in Table 9-
9.

Table 9-9. HLC ALT Event List

Index HLC Event Mux
0 CLB_OUT_0
1 CLB_OUT_1
2 CLB_OUT_2
3 CLB_OUT_3
4 CLB_OUT_4
5 CLB_OUT_5
6 CLB_OUT_6
7 CLB_OUT_7
8 CLB_OUT_0.INVERTED
9 CLB_OUT_1.INVERTED
10 CLB_OUT_2.INVERTED
11 CLB_OUT_3.INVERTED
12 CLB_OUT_4.INVERTED
13 CLB_OUT_5.INVERTED
14 CLB_OUT_6.INVERTED
15 CLB_OUT_7.INVERTED
16 CLB_ASYNC_OUT_0
17 CLB_ASYNC_OUT_1
18 CLB_ASYNC_OUT_2
19 CLB_ASYNC_OUT_3
20 CLB_ASYNC_OUT_4
21 CLB_ASYNC_OUT_5
22 CLB_ASYNC_OUT_6
23 CLB_ASYNC_OUT_7
24 CLB_ASYNC_OUT_0.INVERTED
25 CLB_ASYNC_OUT_1.INVERTED
26 CLB_ASYNC_OUT_2.INVERTED
27 CLB_ASYNC_OUT_3.INVERTED
28 CLB_ASYNC_OUT_4.INVERTED
29 CLB_ASYNC_OUT_5.INVERTED
30 CLB_ASYNC_OUT_6.INVERTED
31 CLB_ASYNC_OUT_7.INVERTED

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9.4.7.2 High Level Controller Instructions

The instruction memory supports up to eight instructions per event. Each instruction sequence gets
triggered on the rising edge of the corresponding event. Starting with CLB Type 2, the option to trigger the
execution of instructions using both falling edge and rising edge is available.
The HLC memory supports up to eight instructions per event, starting at the beginning of the fixed address
range shown in Table 9-10. An instruction sequence is triggered on the rising edge of the corresponding
event. If two or more events occur simultaneously, the associated instruction sequences will each be
executed sequentially in priority order.

Table 9-10. HLC Instruction Address Ranges

Address Instructions for
00000 to 00111 Event 0
01000 to 01111 Event 1
10000 to 10111 Event 2
11000 to 11111 Event 3

The instruction format is shown in Table 9-11.

Table 9-11. Instruction Format

Last Instruction Bit 5-Bit Opcode 3-Bit Source 3-Bit Destination
This bit set to 1 will stop MOV 00000 Source can be R0, R1, R2, Destination can be R0, R1, R2, R3, C0,
execution after the current T1_MOV 00001 R3, C0, C1, C2. C1, C2.
instruction. T2_MOV 00010
Note that for ADD/SUB instructions, only
PUSH 00011
R0 to R3 can be the destination.
PULL 00100
ADD 00101
SUB 00110
INTR 00111

R0, R1, R2, and R3 are four 32-bit general purpose registers in the HLC. C0, C1, and C2 are three
counter registers present in the CLB tile. <Src> is used to indicate the source and <Dest> is used to
indicate the destination.
• MOV <Src> <Dest>
This instruction moves <Src> to <Dest>. Both <Src> and <Dest> can be any of R0, R1, R2, R3, C0,
C1, or C2.
• MOV_T1 <Src> <Dest>
This instruction moves <Src> to the Match1 register of the <Dest> counter. <Src> can be any of the
registers R0, R1, R2, R3, or the counter values associated with C0, C1, or C2. <Dest> is the Match1
register of any of the counters C0, C1, or C2. Examples are:
– This instruction moves the count value in C1 into register R0.
MOV_T1 C1 R0
– This instruction moves the value in R2 into the Match1 register of counter C0.
MOV_T1 R2 C0
• MOV_T2 <Src> <Dest>
This instruction is similar to “MOV_T1”, above. It moves <Src> to the Match2 register of the <Dest>
counter. <Src> can be any of the registers R0, R1, R2, R3, or the counter values associated with C0,
C1, or C2. <Dest> is the Match2 register of any of the counters C0, C1, or C2.
• ADD <Src> <Dest>
This instruction performs an unsigned 32-bit addition. <Dest> = <Dest> + <Src>. Both <Src> and
<Dest> can be R0, R1, R2, R3, C0, C1, or C2.

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• SUB <Src> <Dest>

This instruction performs an unsigned 32-bit subtraction. <Dest> = <Dest> - <Src> Both <Src> and
<Dest> can be R0, R1, R2, R3, C0, C1, or C2.
• PUSH <Src>
This instruction transfers data from <Src> to the data exchange push memory buffer in the CPU
interface. <Src> can be any of R0, R1, R2, R3, C0, C1, or C2. The PUSH instruction is used as seen
from the High Level Controller and pushes data into an internal 4 word FIFO.
• PULL <Dest>
This instruction transfers data from to the data exchange pull memory buffer in the CPU interface to
the <Dest> register. <Dest> can be any of R0, R1, R2, R3, C0, C1, or C2. The PULL instruction is
used as seen from the High Level Controller and a PULL operation reads (pulls) data from an internal
4-word FIFO.
• INTR <6-bit constant>
This instruction will flag an interrupt through the CPU interface. The 6-bit constant is stored in the
interrupt flag register CLB_INTR_TAG_REG.

NOTE: Starting with CLB Type 2, NMI can be generated by the CLB. This feature is DISABLED by
default and must be enabled (CLB_LOAD_EN.NMI_EN).

9.4.7.3 <Src> and <Dest>

Three bits are used to encode the <Src> and <Dest> registers as shown in Table 9-12.

Table 9-12. HLC Register Encoding

Bits Register
000 R0
001 R1
010 R2
011 R3
100 C0
101 C1
110 C2

9.4.7.4 Operation of the PUSH and PULL Instructions (overflow and underflow detection)
The PUSH and PULL operations of the HLC are intended for data exchange with the host system. There
are separate FIFO buffers for PUSH and PULL operations. For example, a series of PUSH operations will
write to successive locations in a linearly mapped memory buffer. The PUSH buffer is mapped at address
offset 0x200 and the PULL buffer is mapped at address offset 0x300.
The CPU can read from and write to the PUSH and PULL buffers respectively, in order to exchange data
with the HLC. Data pushed by the HLC is read by the CPU from the PUSH buffers. Data sent from the
CPU to the HLC will be written by the CPU to the PULL buffer and will be read by the HLC using the
PULL instruction.
There are separate PUSH and PULL address pointers that increment each time the HLC performs a
PUSH or PULL operation. These address pointers are also memory-mapped so that the CPU can
determine their value. They are also writable and can be reset by the CPU can at any time.
Overflow and underflow detection is done by simply reading the values of the PUSH and PULL address
pointers.
In the CLB module of the device, the depth of the PUSH and PULL FIFOs is four 32-bit words each. If the
CPU starts a fresh data transfer to the PULL buffers and sees the address pointer greater than four, then
an underflow has occurred since the HLC has pulled more data than the number of words written by the
CPU into the buffer.
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9.5 CPU Interface

9.5.1 Register Description

There are three classes of registers that are used to control and configure the CLB tile. This specification
only describes the offset addresses of the registers. The absolute register addresses will be different for
each CLB tile. The three instances of the various blocks (LUT4, FSM, and Counter Block) are numbered
0,1, and 2.
• Logic configuration registers (0x000 – 0x0FF)
These registers control the core reconfiguration logic for the tile. All registers in this group are
EALLOW protected and also protected by the LOCK register.
• Top level control registers (0x100 – 0x1FF)
These registers are used for top level and device related control of the CLB. These registers typically
control mux selects for inputs, global enables, and so forth, and are accessible by normal memory
mapped access. Some of these registers have EALLOW and LOCK protection.
• Data exchange registers (0x200 – 0x3FF)
These registers are used to exchange data between the CLB and the rest of the device. They are
accessible by normal memory mapped access and no EALLOW or LOCK protection exists.

NOTE: EALLOW protection means that the write access to the register will be enabled only when
the EALLOW instruction has been executed prior to the write access. The complementary
EDIS instruction disables access to all registers protected in this way. For more information,
see Section 9.6.

9.5.2 Non-Memory Mapped Registers

The memory mapped CLB registers are described later in this document, however many of the CLB
resources including counters, the instruction memory of the High Level controller, and the HLC general
purpose registers (R0 through R3) are only indirectly accessible through a local interface bus and are not
memory mapped. These registers are accessible through the two memory mapped registers
CLB_LOAD_DATA and CLB_LOAD_ADDR.
The user loads the data to be written into the CLB_LOAD_DATA register, then loads the appropriate
address into CLB_LOAD_ADDR to determine where this data is written. Writing a ‘1’ to bit position 0 in the
CLB_LOAD_EN register then causes an internal write operation to be triggered. The address allocation for
the CLB_LOAD_ADDR register is shown in Table 9-13.

Table 9-13. Non-Memory Mapped Register Addresses

Address (Binary) Resource
000000 to 000010 Counter 0 to 2 load value
000100 to 000110 Counter 0 to 2 Match1 value
001000 to 001010 Counter 0 to 2 Match2 value
001100 to 001111 R0 to R3 of High Level controller
100000 to 100111 Instructions for Event 0
101000 to 101111 Instructions for Event 1
110000 to 110111 Instructions for Event 2
111000 to 111111 Instructions for Event 3

Use the following steps to load the value 0x11223344 into the general purpose R0 register:
1. Write 0x11223344 to CLB_LOAD_DATA.
2. Write 0xc to CLB_LOAD_ADDR.
3. Write 0x1 to CLB_LOAD_EN.

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NOTE: Even though HLC registers are accessible by the CPU, the user application code needs to
ensure that no other CLB internal logics are updating the same HLC register at the same
time, causing a race condition.

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9.6 CLB Registers

This section describes the Configurable Logic Block Registers.

9.6.1 CLB Base Addresses

This is the Configurable Logic Block Base Address Table.

Table 9-14. CLB Base Address Table (C28)

Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU2 DMA CLA
Instance Structure Protected

CLB_LOGIC_CONFIG CLB1_LOGICCFG_BA
Clb1LogicCfgRegs 0x0000_3000 YES YES - YES -
_REGS SE
CLB_LOGIC_CONTR CLB1_LOGICCTL_BA
Clb1LogicCtrlRegs 0x0000_3100 YES YES - YES -
OL_REGS SE
CLB_DATA_EXCHAN CLB1_DATAEXCH_BA
Clb1DataExchRegs 0x0000_3180 YES YES - YES -
GE_REGS SE
CLB_LOGIC_CONFIG CLB2_LOGICCFG_BA
Clb2LogicCfgRegs 0x0000_3200 YES YES - YES -
_REGS SE
CLB_LOGIC_CONTR CLB2_LOGICCTL_BA
Clb2LogicCtrlRegs 0x0000_3300 YES YES - YES -
OL_REGS SE
CLB_DATA_EXCHAN CLB2_DATAEXCH_BA
Clb2DataExchRegs 0x0000_3380 YES YES - YES -
GE_REGS SE
CLB_LOGIC_CONFIG CLB3_LOGICCFG_BA
Clb3LogicCfgRegs 0x0000_3400 YES YES - YES -
_REGS SE
CLB_LOGIC_CONTR CLB3_LOGICCTL_BA
Clb3LogicCtrlRegs 0x0000_3500 YES YES - YES -
OL_REGS SE
CLB_DATA_EXCHAN CLB3_DATAEXCH_BA
Clb3DataExchRegs 0x0000_3580 YES YES - YES -
GE_REGS SE
CLB_LOGIC_CONFIG CLB4_LOGICCFG_BA
Clb4LogicCfgRegs 0x0000_3600 YES YES - YES -
_REGS SE
CLB_LOGIC_CONTR CLB4_LOGICCTL_BA
Clb4LogicCtrlRegs 0x0000_3700 YES YES - YES -
OL_REGS SE
CLB_DATA_EXCHAN CLB4_DATAEXCH_BA
Clb4DataExchRegs 0x0000_3780 YES YES - YES -
GE_REGS SE
CLB_LOGIC_CONFIG CLB5_LOGICCFG_BA
Clb5LogicCfgRegs 0x0000_3800 YES YES - YES -
_REGS SE
CLB_LOGIC_CONTR CLB5_LOGICCTL_BA
Clb5LogicCtrlRegs 0x0000_3900 YES YES - YES -
OL_REGS SE
CLB_DATA_EXCHAN CLB5_DATAEXCH_BA
Clb5DataExchRegs 0x0000_3980 YES YES - YES -
GE_REGS SE
CLB_LOGIC_CONFIG CLB6_LOGICCFG_BA
Clb6LogicCfgRegs 0x0000_3A00 YES YES - YES -
_REGS SE
CLB_LOGIC_CONTR CLB6_LOGICCTL_BA
Clb6LogicCtrlRegs 0x0000_3B00 YES YES - YES -
OL_REGS SE
CLB_DATA_EXCHAN CLB6_DATAEXCH_BA
Clb6DataExchRegs 0x0000_3B80 YES YES - YES -
GE_REGS SE
CLB_LOGIC_CONFIG CLB7_LOGICCFG_BA
Clb7LogicCfgRegs 0x0000_3C00 YES YES - YES -
_REGS SE
CLB_LOGIC_CONTR CLB7_LOGICCTL_BA
Clb7LogicCtrlRegs 0x0000_3D00 YES YES - YES -
OL_REGS SE
CLB_DATA_EXCHAN CLB7_DATAEXCH_BA
Clb7DataExchRegs 0x0000_3D80 YES YES - YES -
GE_REGS SE
CLB_LOGIC_CONFIG CLB8_LOGICCFG_BA
Clb8LogicCfgRegs 0x0000_3E00 YES YES - YES -
_REGS SE
CLB_LOGIC_CONTR CLB8_LOGICCTL_BA
Clb8LogicCtrlRegs 0x0000_3F00 YES YES - YES -
OL_REGS SE
CLB_DATA_EXCHAN CLB8_DATAEXCH_BA
Clb8DataExchRegs 0x0000_3F80 YES YES - YES -
GE_REGS SE

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9.6.2 CLB_LOGIC_CONFIG_REGS Registers

Table 9-15 lists the CLB_LOGIC_CONFIG_REGS registers. All register offset addresses not listed in
Table 9-15 should be considered as reserved locations and the register contents should not be modified.

Table 9-15. CLB_LOGIC_CONFIG_REGS Registers

Offset Acronym Register Name Write Protection Section
2h CLB_COUNT_RESET Counter Block RESET EALLOW, LOCK Go
4h CLB_COUNT_MODE_1 Counter Block MODE_1 EALLOW, LOCK Go
6h CLB_COUNT_MODE_0 Counter Block MODE_0 EALLOW, LOCK Go
8h CLB_COUNT_EVENT Counter Block EVENT EALLOW, LOCK Go
Ah CLB_FSM_EXTRA_IN0 FSM Extra EXT_IN0 EALLOW, LOCK Go
Ch CLB_FSM_EXTERNAL_IN0 FSM EXT_IN0 EALLOW, LOCK Go
Eh CLB_FSM_EXTERNAL_IN1 FSM_EXT_IN1 EALLOW, LOCK Go
10h CLB_FSM_EXTRA_IN1 FSM Extra_EXT_IN1 EALLOW, LOCK Go
12h CLB_LUT4_IN0 LUT4_0/1/2 IN0 input source EALLOW, LOCK Go
14h CLB_LUT4_IN1 LUT4_0/1/2 IN1 input source EALLOW, LOCK Go
16h CLB_LUT4_IN2 LUT4_0/1/2 IN2 input source EALLOW, LOCK Go
18h CLB_LUT4_IN3 LUT4_0/1/2 IN3 input source EALLOW, LOCK Go
1Ch CLB_FSM_LUT_FN1_0 LUT function for FSM Unit 1 and Unit 0 EALLOW, LOCK Go
1Eh CLB_FSM_LUT_FN2 LUT function for FSM Unit 2 EALLOW, LOCK Go
20h CLB_LUT4_FN1_0 LUT function for LUT4 block of Unit 1 and 0 EALLOW, LOCK Go
22h CLB_LUT4_FN2 LUT function for LUT4 block of Unit 2 EALLOW, LOCK Go
24h CLB_FSM_NEXT_STATE_0 FSM Next state equations for Unit 0 EALLOW, LOCK Go
26h CLB_FSM_NEXT_STATE_1 FSM Next state equations for Unit 1 EALLOW, LOCK Go
28h CLB_FSM_NEXT_STATE_2 FSM Next state equations for Unit 2 EALLOW, LOCK Go
2Ah CLB_MISC_CONTROL Static controls for Ctr,FSM EALLOW, LOCK Go
2Ch CLB_OUTPUT_LUT_0 Inp Sel, LUT fns for Out0 EALLOW, LOCK Go
2Eh CLB_OUTPUT_LUT_1 Inp Sel, LUT fns for Out1 EALLOW, LOCK Go
30h CLB_OUTPUT_LUT_2 Inp Sel, LUT fns for Out2 EALLOW, LOCK Go
32h CLB_OUTPUT_LUT_3 Inp Sel, LUT fns for Out3 EALLOW, LOCK Go
34h CLB_OUTPUT_LUT_4 Inp Sel, LUT fns for Out4 EALLOW, LOCK Go
36h CLB_OUTPUT_LUT_5 Inp Sel, LUT fns for Out5 EALLOW, LOCK Go
38h CLB_OUTPUT_LUT_6 Inp Sel, LUT fns for Out6 EALLOW, LOCK Go
3Ah CLB_OUTPUT_LUT_7 Inp Sel, LUT fns for Out7 EALLOW, LOCK Go
3Ch CLB_HLC_EVENT_SEL Event Selector register for the High Level EALLOW, LOCK Go
controller
3Eh CLB_COUNT_MATCH_TAP_SEL Counter tap values for match1 and match2 EALLOW, LOCK Go
outputs
40h CLB_OUTPUT_COND_CTRL_0 Output conditioning control for output 0 EALLOW, LOCK Go
42h CLB_OUTPUT_COND_CTRL_1 Output conditioning control for output 1 EALLOW, LOCK Go
44h CLB_OUTPUT_COND_CTRL_2 Output conditioning control for output 2 EALLOW, LOCK Go
46h CLB_OUTPUT_COND_CTRL_3 Output conditioning control for output 3 EALLOW, LOCK Go
48h CLB_OUTPUT_COND_CTRL_4 Output conditioning control for output 4 EALLOW, LOCK Go
4Ah CLB_OUTPUT_COND_CTRL_5 Output conditioning control for output 5 EALLOW, LOCK Go
4Ch CLB_OUTPUT_COND_CTRL_6 Output conditioning control for output 6 EALLOW, LOCK Go
4Eh CLB_OUTPUT_COND_CTRL_7 Output conditioning control for output 7 EALLOW, LOCK Go
50h CLB_MISC_ACCESS_CTRL Miscellaneous Access and enable control EALLOW, LOCK Go
51h CLB_SPI_DATA_CTRL_HI CLB to SPI buffer control High EALLOW, LOCK Go

Complex bit access types are encoded to fit into small table cells. Table 9-16 shows the codes that are
used for access types in this section.

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Table 9-16. CLB_LOGIC_CONFIG_REGS Access Type

Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1C W Write
1C 1 to clear
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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9.6.2.1 CLB_COUNT_RESET Register (Offset = 2h) [reset = 0h]

CLB_COUNT_RESET is shown in Figure 9-18 and described in Table 9-17.
Return to the Summary Table.
Counter Block RESET

Figure 9-18. CLB_COUNT_RESET Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEL_2 SEL_1 SEL_0
R/W1C-0h R/W-0h R/W-0h R/W-0h

Table 9-17. CLB_COUNT_RESET Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14-10 SEL_2 R/W 0h Counter reset select inputs for unit 2. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
9-5 SEL_1 R/W 0h Counter reset select inputs for unit 1. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
4-0 SEL_0 R/W 0h Counter reset select inputs for unit 0. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn

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9.6.2.2 CLB_COUNT_MODE_1 Register (Offset = 4h) [reset = 0h]

CLB_COUNT_MODE_1 is shown in Figure 9-19 and described in Table 9-18.
Return to the Summary Table.
Counter Block MODE_1

Figure 9-19. CLB_COUNT_MODE_1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEL_2 SEL_1 SEL_0
R/W1C-0h R/W-0h R/W-0h R/W-0h

Table 9-18. CLB_COUNT_MODE_1 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14-10 SEL_2 R/W 0h Counter MODE_1 select inputs for unit 2. See the Static Switch
Block Output Mux Table.
Reset type: SYSRSn
9-5 SEL_1 R/W 0h Counter MODE_1 select inputs for unit 1. See the Static Switch
Block Output Mux Table.
Reset type: SYSRSn
4-0 SEL_0 R/W 0h Counter MODE_1 select inputs for unit 0. See the Static Switch
Block Output Mux Table.
Reset type: SYSRSn

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9.6.2.3 CLB_COUNT_MODE_0 Register (Offset = 6h) [reset = 0h]

CLB_COUNT_MODE_0 is shown in Figure 9-20 and described in Table 9-19.
Return to the Summary Table.
Counter Block MODE_0

Figure 9-20. CLB_COUNT_MODE_0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEL_2 SEL_1 SEL_0
R/W1C-0h R/W-0h R/W-0h R/W-0h

Table 9-19. CLB_COUNT_MODE_0 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14-10 SEL_2 R/W 0h Counter MODE_0 select inputs for unit 2. See the Static Switch
Block Output Mux Table.
Reset type: SYSRSn
9-5 SEL_1 R/W 0h Counter MODE_0 select inputs for unit 1. See the Static Switch
Block Output Mux Table.
Reset type: SYSRSn
4-0 SEL_0 R/W 0h Counter MODE_0 select inputs for unit 0. See the Static Switch
Block Output Mux Table.
Reset type: SYSRSn

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9.6.2.4 CLB_COUNT_EVENT Register (Offset = 8h) [reset = 0h]

CLB_COUNT_EVENT is shown in Figure 9-21 and described in Table 9-20.
Return to the Summary Table.
Counter Block EVENT

Figure 9-21. CLB_COUNT_EVENT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEL_2 SEL_1 SEL_0
R/W1C-0h R/W-0h R/W-0h R/W-0h

Table 9-20. CLB_COUNT_EVENT Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14-10 SEL_2 R/W 0h Counter event select inputs for unit 2. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
9-5 SEL_1 R/W 0h Counter event select inputs for unit 1. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
4-0 SEL_0 R/W 0h Counter event select inputs for unit 0. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn

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9.6.2.5 CLB_FSM_EXTRA_IN0 Register (Offset = Ah) [reset = 0h]

CLB_FSM_EXTRA_IN0 is shown in Figure 9-22 and described in Table 9-21.
Return to the Summary Table.
FSM Extra EXT_IN0

Figure 9-22. CLB_FSM_EXTRA_IN0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEL_2 SEL_1 SEL_0
R/W1C-0h R/W-0h R/W-0h R/W-0h

Table 9-21. CLB_FSM_EXTRA_IN0 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14-10 SEL_2 R/W 0h FSM block extra external IN0 select inputs for unit 2. See the Static
Switch Block Output Mux Table.
Reset type: SYSRSn
9-5 SEL_1 R/W 0h FSM block extra external IN0 select inputs for unit 1. See the Static
Switch Block Output Mux Table.
Reset type: SYSRSn
4-0 SEL_0 R/W 0h FSM block extra external IN0 select inputs for unit 0. See the Static
Switch Block Output Mux Table.
Reset type: SYSRSn

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9.6.2.6 CLB_FSM_EXTERNAL_IN0 Register (Offset = Ch) [reset = 0h]

CLB_FSM_EXTERNAL_IN0 is shown in Figure 9-23 and described in Table 9-22.
Return to the Summary Table.
FSM EXT_IN0

Figure 9-23. CLB_FSM_EXTERNAL_IN0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEL_2 SEL_1 SEL_0
R/W1C-0h R/W-0h R/W-0h R/W-0h

Table 9-22. CLB_FSM_EXTERNAL_IN0 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14-10 SEL_2 R/W 0h FSM block EXT_IN0 select input for unit 2. See the Static Switch
Block Output Mux Table.
Reset type: SYSRSn
9-5 SEL_1 R/W 0h FSM block EXT_IN0 select input for unit 1. See the Static Switch
Block Output Mux Table.
Reset type: SYSRSn
4-0 SEL_0 R/W 0h FSM block EXT_IN0 select input for unit 0. See the Static Switch
Block Output Mux Table.
Reset type: SYSRSn

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9.6.2.7 CLB_FSM_EXTERNAL_IN1 Register (Offset = Eh) [reset = 0h]

CLB_FSM_EXTERNAL_IN1 is shown in Figure 9-24 and described in Table 9-23.
Return to the Summary Table.
FSM_EXT_IN1

Figure 9-24. CLB_FSM_EXTERNAL_IN1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEL_2 SEL_1 SEL_0
R/W1C-0h R/W-0h R/W-0h R/W-0h

Table 9-23. CLB_FSM_EXTERNAL_IN1 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14-10 SEL_2 R/W 0h FSM block EXT_IN1 select input for unit 2. See the Static Switch
Block Output Mux Table.
Reset type: SYSRSn
9-5 SEL_1 R/W 0h FSM block EXT_IN1 select input for unit 1. See the Static Switch
Block Output Mux Table.
Reset type: SYSRSn
4-0 SEL_0 R/W 0h FSM block EXT_IN1 select input for unit 0. See the Static Switch
Block Output Mux Table.
Reset type: SYSRSn

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9.6.2.8 CLB_FSM_EXTRA_IN1 Register (Offset = 10h) [reset = 0h]

CLB_FSM_EXTRA_IN1 is shown in Figure 9-25 and described in Table 9-24.
Return to the Summary Table.
FSM Extra_EXT_IN1

Figure 9-25. CLB_FSM_EXTRA_IN1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEL_2 SEL_1 SEL_0
R/W1C-0h R/W-0h R/W-0h R/W-0h

Table 9-24. CLB_FSM_EXTRA_IN1 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14-10 SEL_2 R/W 0h FSM block extra external IN1 select inputs for unit 2. See the Static
Switch Block Output Mux Table.
Reset type: SYSRSn
9-5 SEL_1 R/W 0h FSM block extra external IN1 select inputs for unit 1. See the Static
Switch Block Output Mux Table.
Reset type: SYSRSn
4-0 SEL_0 R/W 0h FSM block extra external IN1 select inputs for unit 0. See the Static
Switch Block Output Mux Table.
Reset type: SYSRSn

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9.6.2.9 CLB_LUT4_IN0 Register (Offset = 12h) [reset = 0h]

CLB_LUT4_IN0 is shown in Figure 9-26 and described in Table 9-25.
Return to the Summary Table.
LUT4_0/1/2 IN0 input source

Figure 9-26. CLB_LUT4_IN0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEL_2 SEL_1 SEL_0
R/W1C-0h R/W-0h R/W-0h R/W-0h

Table 9-25. CLB_LUT4_IN0 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14-10 SEL_2 R/W 0h LUT4 block IN0 select inputs for unit 2. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
9-5 SEL_1 R/W 0h LUT4 block IN0 select inputs for unit 1. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
4-0 SEL_0 R/W 0h LUT4 block IN0 select inputs for unit 0. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn

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9.6.2.10 CLB_LUT4_IN1 Register (Offset = 14h) [reset = 0h]

CLB_LUT4_IN1 is shown in Figure 9-27 and described in Table 9-26.
Return to the Summary Table.
LUT4_0/1/2 IN1 input source

Figure 9-27. CLB_LUT4_IN1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEL_2 SEL_1 SEL_0
R/W1C-0h R/W-0h R/W-0h R/W-0h

Table 9-26. CLB_LUT4_IN1 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14-10 SEL_2 R/W 0h LUT4 block IN1 select inputs for unit 2. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
9-5 SEL_1 R/W 0h LUT4 block IN1 select inputs for unit 1. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
4-0 SEL_0 R/W 0h LUT4 block IN1 select inputs for unit 0. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn

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9.6.2.11 CLB_LUT4_IN2 Register (Offset = 16h) [reset = 0h]

CLB_LUT4_IN2 is shown in Figure 9-28 and described in Table 9-27.
Return to the Summary Table.
LUT4_0/1/2 IN2 input source

Figure 9-28. CLB_LUT4_IN2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEL_2 SEL_1 SEL_0
R/W1C-0h R/W-0h R/W-0h R/W-0h

Table 9-27. CLB_LUT4_IN2 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14-10 SEL_2 R/W 0h LUT4 block IN2 select inputs for unit 2. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
9-5 SEL_1 R/W 0h LUT4 block IN2 select inputs for unit 1. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
4-0 SEL_0 R/W 0h LUT4 block IN2 select inputs for unit 0. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn

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9.6.2.12 CLB_LUT4_IN3 Register (Offset = 18h) [reset = 0h]

CLB_LUT4_IN3 is shown in Figure 9-29 and described in Table 9-28.
Return to the Summary Table.
LUT4_0/1/2 IN3 input source

Figure 9-29. CLB_LUT4_IN3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEL_2 SEL_1 SEL_0
R/W1C-0h R/W-0h R/W-0h R/W-0h

Table 9-28. CLB_LUT4_IN3 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14-10 SEL_2 R/W 0h LUT4 block IN3 select inputs for unit 2. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
9-5 SEL_1 R/W 0h LUT4 block IN3 select inputs for unit 1. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
4-0 SEL_0 R/W 0h LUT4 block IN3 select inputs for unit 0. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn

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9.6.2.13 CLB_FSM_LUT_FN1_0 Register (Offset = 1Ch) [reset = 0h]

CLB_FSM_LUT_FN1_0 is shown in Figure 9-30 and described in Table 9-29.
Return to the Summary Table.
LUT function for FSM Unit 1 and Unit 0

Figure 9-30. CLB_FSM_LUT_FN1_0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FN1 FN0
R/W-0h R/W-0h

Table 9-29. CLB_FSM_LUT_FN1_0 Register Field Descriptions

Bit Field Type Reset Description
31-16 FN1 R/W 0h FSM block LUT output function for unit 1
Reset type: SYSRSn
15-0 FN0 R/W 0h FSM block LUT output function for unit 0
Reset type: SYSRSn

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9.6.2.14 CLB_FSM_LUT_FN2 Register (Offset = 1Eh) [reset = 0h]

CLB_FSM_LUT_FN2 is shown in Figure 9-31 and described in Table 9-30.
Return to the Summary Table.
LUT function for FSM Unit 2

Figure 9-31. CLB_FSM_LUT_FN2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FN1
R/W1C-0h R/W-0h

Table 9-30. CLB_FSM_LUT_FN2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R/W1C 0h Reserved
15-0 FN1 R/W 0h LUT4 output function for unit 2
Reset type: SYSRSn

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9.6.2.15 CLB_LUT4_FN1_0 Register (Offset = 20h) [reset = 0h]

CLB_LUT4_FN1_0 is shown in Figure 9-32 and described in Table 9-31.
Return to the Summary Table.
LUT function for LUT4 block of Unit 1 and 0

Figure 9-32. CLB_LUT4_FN1_0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FN1 FN0
R/W-0h R/W-0h

Table 9-31. CLB_LUT4_FN1_0 Register Field Descriptions

Bit Field Type Reset Description
31-16 FN1 R/W 0h LUT4 output function for unit 1
Reset type: SYSRSn
15-0 FN0 R/W 0h LUT4 output function for unit 0
Reset type: SYSRSn

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9.6.2.16 CLB_LUT4_FN2 Register (Offset = 22h) [reset = 0h]

CLB_LUT4_FN2 is shown in Figure 9-33 and described in Table 9-32.
Return to the Summary Table.
LUT function for LUT4 block of Unit 2

Figure 9-33. CLB_LUT4_FN2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FN1
R/W1C-0h R/W-0h

Table 9-32. CLB_LUT4_FN2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R/W1C 0h Reserved
15-0 FN1 R/W 0h LUT4 output function for unit 2
Reset type: SYSRSn

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9.6.2.17 CLB_FSM_NEXT_STATE_0 Register (Offset = 24h) [reset = 0h]

CLB_FSM_NEXT_STATE_0 is shown in Figure 9-34 and described in Table 9-33.
Return to the Summary Table.
FSM Next state equations for Unit 0

Figure 9-34. CLB_FSM_NEXT_STATE_0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S1 S0
R/W-0h R/W-0h

Table 9-33. CLB_FSM_NEXT_STATE_0 Register Field Descriptions

Bit Field Type Reset Description
31-16 S1 R/W 0h FSM next state function for S1, unit0
Reset type: SYSRSn
15-0 S0 R/W 0h FSM next state function for S0, unit0
Reset type: SYSRSn

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9.6.2.18 CLB_FSM_NEXT_STATE_1 Register (Offset = 26h) [reset = 0h]

CLB_FSM_NEXT_STATE_1 is shown in Figure 9-35 and described in Table 9-34.
Return to the Summary Table.
FSM Next state equations for Unit 1

Figure 9-35. CLB_FSM_NEXT_STATE_1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S1 S0
R/W-0h R/W-0h

Table 9-34. CLB_FSM_NEXT_STATE_1 Register Field Descriptions

Bit Field Type Reset Description
31-16 S1 R/W 0h FSM next state function for S1, unit1
Reset type: SYSRSn
15-0 S0 R/W 0h FSM next state function for S0, unit1
Reset type: SYSRSn

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9.6.2.19 CLB_FSM_NEXT_STATE_2 Register (Offset = 28h) [reset = 0h]

CLB_FSM_NEXT_STATE_2 is shown in Figure 9-36 and described in Table 9-35.
Return to the Summary Table.
FSM Next state equations for Unit 2

Figure 9-36. CLB_FSM_NEXT_STATE_2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S1 S0
R/W-0h R/W-0h

Table 9-35. CLB_FSM_NEXT_STATE_2 Register Field Descriptions

Bit Field Type Reset Description
31-16 S1 R/W 0h FSM next state function for S1, unit2
Reset type: SYSRSn
15-0 S0 R/W 0h FSM next state function for S0, unit2
Reset type: SYSRSn

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9.6.2.20 CLB_MISC_CONTROL Register (Offset = 2Ah) [reset = 0h]

CLB_MISC_CONTROL is shown in Figure 9-37 and described in Table 9-36.
Return to the Summary Table.
Static controls for Ctr,FSM

Figure 9-37. CLB_MISC_CONTROL Register

31 30 29 28 27 26 25 24
RESERVED COUNT2_LFS COUNT1_LFS COUNT0_LFS
R_EN R_EN R_EN
R-0-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
COUNT2_MAT COUNT1_MAT COUNT0_MAT COUNT2_MAT COUNT1_MAT COUNT0_MAT FSM_EXTRA_ FSM_EXTRA_
CH2_TAP_EN CH2_TAP_EN CH2_TAP_EN CH1_TAP_EN CH1_TAP_EN CH1_TAP_EN SEL1_2 SEL0_2
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
FSM_EXTRA_ FSM_EXTRA_ FSM_EXTRA_ FSM_EXTRA_ COUNT_SERIA COUNT_SERIA COUNT_SERIA COUNT_EVEN
SEL1_1 SEL0_1 SEL1_0 SEL0_0 LIZER_2 LIZER_1 LIZER_0 T_CTRL_2
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
COUNT_DIR_2 COUNT_ADD_ COUNT_EVEN COUNT_DIR_1 COUNT_ADD_ COUNT_EVEN COUNT_DIR_0 COUNT_ADD_
SHIFT_2 T_CTRL_1 SHIFT_1 T_CTRL_0 SHIFT_0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-36. CLB_MISC_CONTROL Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R-0 0h Reserved
26 COUNT2_LFSR_EN R/W 0h Defines if Counter 2 should operate in LFSR mode. This should be
set to 1 only if it is in the SERIALIZER mode.
0 = Selects normal serializer operation
1 = Selects LFSR mode of operation
Reset type: SYSRSn
25 COUNT1_LFSR_EN R/W 0h Defines if Counter 1 should operate in LFSR mode. This should be
set to 1 only if it is in the SERIALIZER mode.
0 = Selects normal serializer operation
1 = Selects LFSR mode of operation
Reset type: SYSRSn
24 COUNT0_LFSR_EN R/W 0h Defines if Counter 0 should operate in LFSR mode. This should be
set to 1 only if it is in the SERIALIZER mode.
0 = Selects normal serializer operation
1 = Selects LFSR mode of operation
Reset type: SYSRSn
23 COUNT2_MATCH2_TAP_ R/W 0h Defines if the Match2 output should come from the match unit or
EN tapped from a bit position of the counter
0 = Selects Match2 comaprison output
1 = Selects Bit position defined by Match2_Tap_val
Reset type: SYSRSn
22 COUNT1_MATCH2_TAP_ R/W 0h Defines if the Match2 output should come from the match unit or
EN tapped from a bit position of the counter
0 = Selects Match2 comaprison output
1 = Selects Bit position defined by Match2_Tap_val
Reset type: SYSRSn
21 COUNT0_MATCH2_TAP_ R/W 0h Defines if the Match2 output should come from the match unit or
EN tapped from a bit position of the counter
0 = Selects Match2 comaprison output
1 = Selects Bit position defined by Match2_Tap_val
Reset type: SYSRSn

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Table 9-36. CLB_MISC_CONTROL Register Field Descriptions (continued)

Bit Field Type Reset Description
20 COUNT2_MATCH1_TAP_ R/W 0h Defines if the Match1 output should come from the match unit or
EN tapped from a bit position of the counter
0 = Selects Match1 comaprison output
1 = Selects Bit position defined by Match1_Tap_val
Reset type: SYSRSn
19 COUNT1_MATCH1_TAP_ R/W 0h Defines if the Match1 output should come from the match unit or
EN tapped from a bit position of the counter
0 = Selects Match1 comaprison output
1 = Selects Bit position defined by Match1_Tap_val
Reset type: SYSRSn
18 COUNT0_MATCH1_TAP_ R/W 0h Defines if the Match1 output should come from the match unit or
EN tapped from a bit position of the counter
0 = Selects Match1 comaprison output
1 = Selects Bit position defined by Match1_Tap_val
Reset type: SYSRSn
17 FSM_EXTRA_SEL1_2 R/W 0h Defines which input should be selected for the FSM LUT of UNIT 2
0 = Selects State S1 for the FSM LUT
1 = Selects EXTRA_EXT_IN1 for the FSM LUT
Reset type: SYSRSn
16 FSM_EXTRA_SEL0_2 R/W 0h Defines which input should be selected for the FSM LUT of UNIT 2
0 = Selects State S0 for the FSM LUT
1 = Selects EXTRA_EXT_IN0 for the FSM LUT
Reset type: SYSRSn
15 FSM_EXTRA_SEL1_1 R/W 0h Defines which input should be selected for the FSM LUT of UNIT 1
0 = Selects State S1 for the FSM LUT
1 = Selects EXTRA_EXT_IN1 for the FSM LUT
Reset type: SYSRSn
14 FSM_EXTRA_SEL0_1 R/W 0h Defines which input should be selected for the FSM LUT of UNIT 1
0 = Selects State S0 for the FSM LUT
1 = Selects EXTRA_EXT_IN0 for the FSM LUT
Reset type: SYSRSn
13 FSM_EXTRA_SEL1_0 R/W 0h Defines which input should be selected for the FSM LUT of UNIT 0
0 = Selects State S1 for the FSM LUT
1 = Selects EXTRA_EXT_IN1 for the FSM LUT
Reset type: SYSRSn
12 FSM_EXTRA_SEL0_0 R/W 0h Defines which input should be selected for the FSM LUT of UNIT 0
0 = Selects State S0 for the FSM LUT
1 = Selects EXTRA_EXT_IN0 for the FSM LUT
Reset type: SYSRSn
11 COUNT_SERIALIZER_2 R/W 0h Controls if the Counter of UNIT 2 is the Serialzer mode or not.
0 = Normal mode
1 = Serializer mode
Reset type: SYSRSn
10 COUNT_SERIALIZER_1 R/W 0h Controls if the Counter of UNIT 1 is the Serialzer mode or not.
0 = Normal mode
1 = Serializer mode
Reset type: SYSRSn
9 COUNT_SERIALIZER_0 R/W 0h Controls if the Counter of UNIT 0 is the Serialzer mode or not.
0 = Normal mode
1 = Serializer mode
Reset type: SYSRSn
8 COUNT_EVENT_CTRL_2 R/W 0h Controls the actions on an EVENT for UNIT2.
0 = No add or shift, but load the predefined value
1 = Based on other bits, add/shift with the predefined value
Reset type: SYSRSn
7 COUNT_DIR_2 R/W 0h Controls add/shift direction for UNIT 2
0 = right shift or subtract
1 = left shift or add
Reset type: SYSRSn

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Table 9-36. CLB_MISC_CONTROL Register Field Descriptions (continued)

Bit Field Type Reset Description
6 COUNT_ADD_SHIFT_2 R/W 0h Controls whether the UNIT 2 counter will do an ADD or a SHIFT on
an EVENT.
0 =Shift
1 = ADD
Reset type: SYSRSn
5 COUNT_EVENT_CTRL_1 R/W 0h Controls the actions on an EVENT for UNIT1.
0 = No add or shift, but load the predefined value
1 = Based on other bits, add/shift with the predefined value
Reset type: SYSRSn
4 COUNT_DIR_1 R/W 0h Controls add/shift direction for UNIT 1
0 = right shift or subtract
1 = left shift or add
Reset type: SYSRSn
3 COUNT_ADD_SHIFT_1 R/W 0h Controls whether the UNIT 1 counter will do an ADD or a SHIFT on
an EVENT.
0 = Shift
1 = ADD
Reset type: SYSRSn
2 COUNT_EVENT_CTRL_0 R/W 0h Controls the actions on an EVENT for UNIT1.
0 = No add or shift, but load the predefined value
1 = Based on other bits, add/shift with the predefined value
Reset type: SYSRSn
1 COUNT_DIR_0 R/W 0h Controls add/shift direction for UNIT 0
0 = right shift or subtract
1 = left shift or add
Reset type: SYSRSn
0 COUNT_ADD_SHIFT_0 R/W 0h Controls whether the UNIT 0 counter will do an ADD or a SHIFT on
an EVENT.
0 = Shift
1 = ADD
Reset type: SYSRSn

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9.6.2.21 CLB_OUTPUT_LUT_0 Register (Offset = 2Ch) [reset = 0h]

CLB_OUTPUT_LUT_0 is shown in Figure 9-38 and described in Table 9-37.
Return to the Summary Table.
Inp Sel, LUT fns for Out0

Figure 9-38. CLB_OUTPUT_LUT_0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FN IN2 IN1 IN0
R/W1C-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-37. CLB_OUTPUT_LUT_0 Register Field Descriptions

Bit Field Type Reset Description
31-23 RESERVED R/W1C 0h Reserved
22-15 FN R/W 0h Output function for output LUT
Reset type: SYSRSn
14-10 IN2 R/W 0h Select value for IN2 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
9-5 IN1 R/W 0h Select value for IN1 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
4-0 IN0 R/W 0h Select value for IN0 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn

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9.6.2.22 CLB_OUTPUT_LUT_1 Register (Offset = 2Eh) [reset = 0h]

CLB_OUTPUT_LUT_1 is shown in Figure 9-39 and described in Table 9-38.
Return to the Summary Table.
Inp Sel, LUT fns for Out1

Figure 9-39. CLB_OUTPUT_LUT_1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FN IN2 IN1 IN0
R/W1C-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-38. CLB_OUTPUT_LUT_1 Register Field Descriptions

Bit Field Type Reset Description
31-23 RESERVED R/W1C 0h Reserved
22-15 FN R/W 0h Output function for output LUT
Reset type: SYSRSn
14-10 IN2 R/W 0h Select value for IN2 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
9-5 IN1 R/W 0h Select value for IN1 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
4-0 IN0 R/W 0h Select value for IN0 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn

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9.6.2.23 CLB_OUTPUT_LUT_2 Register (Offset = 30h) [reset = 0h]

CLB_OUTPUT_LUT_2 is shown in Figure 9-40 and described in Table 9-39.
Return to the Summary Table.
Inp Sel, LUT fns for Out2

Figure 9-40. CLB_OUTPUT_LUT_2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FN IN2 IN1 IN0
R/W1C-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-39. CLB_OUTPUT_LUT_2 Register Field Descriptions

Bit Field Type Reset Description
31-23 RESERVED R/W1C 0h Reserved
22-15 FN R/W 0h Output function for output LUT
Reset type: SYSRSn
14-10 IN2 R/W 0h Select value for IN2 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
9-5 IN1 R/W 0h Select value for IN1 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
4-0 IN0 R/W 0h Select value for IN0 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn

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9.6.2.24 CLB_OUTPUT_LUT_3 Register (Offset = 32h) [reset = 0h]

CLB_OUTPUT_LUT_3 is shown in Figure 9-41 and described in Table 9-40.
Return to the Summary Table.
Inp Sel, LUT fns for Out3

Figure 9-41. CLB_OUTPUT_LUT_3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FN IN2 IN1 IN0
R/W1C-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-40. CLB_OUTPUT_LUT_3 Register Field Descriptions

Bit Field Type Reset Description
31-23 RESERVED R/W1C 0h Reserved
22-15 FN R/W 0h Output function for output LUT
Reset type: SYSRSn
14-10 IN2 R/W 0h Select value for IN2 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
9-5 IN1 R/W 0h Select value for IN1 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
4-0 IN0 R/W 0h Select value for IN0 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn

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9.6.2.25 CLB_OUTPUT_LUT_4 Register (Offset = 34h) [reset = 0h]

CLB_OUTPUT_LUT_4 is shown in Figure 9-42 and described in Table 9-41.
Return to the Summary Table.
Inp Sel, LUT fns for Out4

Figure 9-42. CLB_OUTPUT_LUT_4 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FN IN2 IN1 IN0
R/W1C-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-41. CLB_OUTPUT_LUT_4 Register Field Descriptions

Bit Field Type Reset Description
31-23 RESERVED R/W1C 0h Reserved
22-15 FN R/W 0h Output function for output LUT
Reset type: SYSRSn
14-10 IN2 R/W 0h Select value for IN2 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
9-5 IN1 R/W 0h Select value for IN1 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
4-0 IN0 R/W 0h Select value for IN0 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn

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9.6.2.26 CLB_OUTPUT_LUT_5 Register (Offset = 36h) [reset = 0h]

CLB_OUTPUT_LUT_5 is shown in Figure 9-43 and described in Table 9-42.
Return to the Summary Table.
Inp Sel, LUT fns for Out5

Figure 9-43. CLB_OUTPUT_LUT_5 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FN IN2 IN1 IN0
R/W1C-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-42. CLB_OUTPUT_LUT_5 Register Field Descriptions

Bit Field Type Reset Description
31-23 RESERVED R/W1C 0h Reserved
22-15 FN R/W 0h Output function for output LUT
Reset type: SYSRSn
14-10 IN2 R/W 0h Select value for IN2 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
9-5 IN1 R/W 0h Select value for IN1 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
4-0 IN0 R/W 0h Select value for IN0 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn

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9.6.2.27 CLB_OUTPUT_LUT_6 Register (Offset = 38h) [reset = 0h]

CLB_OUTPUT_LUT_6 is shown in Figure 9-44 and described in Table 9-43.
Return to the Summary Table.
Inp Sel, LUT fns for Out6

Figure 9-44. CLB_OUTPUT_LUT_6 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FN IN2 IN1 IN0
R/W1C-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-43. CLB_OUTPUT_LUT_6 Register Field Descriptions

Bit Field Type Reset Description
31-23 RESERVED R/W1C 0h Reserved
22-15 FN R/W 0h Output function for output LUT
Reset type: SYSRSn
14-10 IN2 R/W 0h Select value for IN2 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
9-5 IN1 R/W 0h Select value for IN1 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
4-0 IN0 R/W 0h Select value for IN0 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn

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9.6.2.28 CLB_OUTPUT_LUT_7 Register (Offset = 3Ah) [reset = 0h]

CLB_OUTPUT_LUT_7 is shown in Figure 9-45 and described in Table 9-44.
Return to the Summary Table.
Inp Sel, LUT fns for Out7

Figure 9-45. CLB_OUTPUT_LUT_7 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FN IN2 IN1 IN0
R/W1C-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-44. CLB_OUTPUT_LUT_7 Register Field Descriptions

Bit Field Type Reset Description
31-23 RESERVED R/W1C 0h Reserved
22-15 FN R/W 0h Output function for output LUT
Reset type: SYSRSn
14-10 IN2 R/W 0h Select value for IN2 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
9-5 IN1 R/W 0h Select value for IN1 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn
4-0 IN0 R/W 0h Select value for IN0 of output LUT. See the Static Switch Block
Output Mux Table.
Reset type: SYSRSn

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9.6.2.29 CLB_HLC_EVENT_SEL Register (Offset = 3Ch) [reset = 0h]

CLB_HLC_EVENT_SEL is shown in Figure 9-46 and described in Table 9-45.
Return to the Summary Table.
Event Selector register for the High Level controller

Figure 9-46. CLB_HLC_EVENT_SEL Register

31 30 29 28 27 26 25 24
RESERVED
R-0-0h
23 22 21 20 19 18 17 16
ALT_EVENT3_ ALT_EVENT2_ ALT_EVENT1_ ALT_EVENT0_ EVENT3_SEL
SEL SEL SEL SEL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
EVENT3_SEL EVENT2_SEL EVENT1_SEL
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
EVENT1_SEL EVENT0_SEL
R/W-0h R/W-0h

Table 9-45. CLB_HLC_EVENT_SEL Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R-0 0h Reserved
23 ALT_EVENT3_SEL R/W 0h Defines selection of alternate inputs for EVENT3
Reset type: SYSRSn
22 ALT_EVENT2_SEL R/W 0h Defines selection of alternate inputs for EVENT2
Reset type: SYSRSn
21 ALT_EVENT1_SEL R/W 0h Defines selection of alternate inputs for EVENT1
Reset type: SYSRSn
20 ALT_EVENT0_SEL R/W 0h Defines selection of alternate inputs for EVENT0
Reset type: SYSRSn
19-15 EVENT3_SEL R/W 0h 5 bit select value for EVENT3 of the High Level Controller. See the
Static Switch Block Output Mux Table.
Reset type: SYSRSn
14-10 EVENT2_SEL R/W 0h 5 bit select value for EVENT2 of the High Level Controller. See the
Static Switch Block Output Mux Table.
Reset type: SYSRSn
9-5 EVENT1_SEL R/W 0h 5 bit select value for EVENT1 of the High Level Controller. See the
Static Switch Block Output Mux Table.
Reset type: SYSRSn
4-0 EVENT0_SEL R/W 0h 5 bit select value for EVENT0 of the High Level Controller. See the
Static Switch Block Output Mux Table.
Reset type: SYSRSn

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9.6.2.30 CLB_COUNT_MATCH_TAP_SEL Register (Offset = 3Eh) [reset = 0h]

CLB_COUNT_MATCH_TAP_SEL is shown in Figure 9-47 and described in Table 9-46.
Return to the Summary Table.
Counter tap values for match1 and match2 outputs

Figure 9-47. CLB_COUNT_MATCH_TAP_SEL Register

31 30 29 28 27 26 25 24
RESERVED COUNT2_MATCH2 COUNT1_MATCH2
R-0-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
COUNT1_MATCH2 COUNT0_MATCH2
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED COUNT2_MATCH1 COUNT1_MATCH1
R-0-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
COUNT1_MATCH1 COUNT0_MATCH1
R/W-0h R/W-0h

Table 9-46. CLB_COUNT_MATCH_TAP_SEL Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0 0h Reserved
30-26 COUNT2_MATCH2 R/W 0h 5 bit MUX Select for Match2 Tap for Counter Unit 2
Reset type: SYSRSn
25-21 COUNT1_MATCH2 R/W 0h 5 bit MUX Select for Match2 Tap for Counter Unit 1
Reset type: SYSRSn
20-16 COUNT0_MATCH2 R/W 0h 5 bit MUX Select for Match2 Tap for Counter Unit 0
Reset type: SYSRSn
15 RESERVED R-0 0h Reserved
14-10 COUNT2_MATCH1 R/W 0h 5 bit MUX Select for Match1 Tap for Counter Unit 2
Reset type: SYSRSn
9-5 COUNT1_MATCH1 R/W 0h 5 bit MUX Select for Match1 Tap for Counter Unit 1
Reset type: SYSRSn
4-0 COUNT0_MATCH1 R/W 0h 5 bit MUX Select for Match1 Tap for Counter Unit 0
Reset type: SYSRSn

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9.6.2.31 CLB_OUTPUT_COND_CTRL_0 Register (Offset = 40h) [reset = 0h]

CLB_OUTPUT_COND_CTRL_0 is shown in Figure 9-48 and described in Table 9-47.
Return to the Summary Table.
Output conditioning control for output 0

Figure 9-48. CLB_OUTPUT_COND_CTRL_0 Register

31 30 29 28 27 26 25 24
RESERVED
R/W1C-0h
23 22 21 20 19 18 17 16
RESERVED
R/W1C-0h
15 14 13 12 11 10 9 8
RESERVED ASYNC_COND SEL_RAW_IN HW_RLS_CTR HW_GATING_ SEL_RELEASE_CTRL
_EN L_SEL CTRL_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
7 6 5 4 3 2 1 0
SEL_GATING_CTRL LEVEL_3_SEL LEVEL_2_SEL LEVEL_1_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 9-47. CLB_OUTPUT_COND_CTRL_0 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14 ASYNC_COND_EN R/W1C 0h Controls whether the output will pass through the asynchronous
conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path
Reset type: SYSRSn
13 SEL_RAW_IN R/W1C 0h Controls whether the CELL outputs or inputs are sent to the output
conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.
Reset type: SYSRSn
12 HW_RLS_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control
Reset type: SYSRSn
11 HW_GATING_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control
Reset type: SYSRSn
10-8 SEL_RELEASE_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Release control.
Reset type: SYSRSn
7-5 SEL_GATING_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Gating control.
Reset type: SYSRSn
4-3 LEVEL_3_SEL R/W1C 0h Controls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of
the output
10 Rising edge of Input signal will cause asynchronous SET of the
output
11 Input Signal delayed by 1 clock cycle will be sent to the output
Reset type: SYSRSn

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Table 9-47. CLB_OUTPUT_COND_CTRL_0 Register Field Descriptions (continued)

Bit Field Type Reset Description
2-1 LEVEL_2_SEL R/W1C 0h Controls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level
Reset type: SYSRSn
0 LEVEL_1_SEL R/W1C 0h First level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level
Reset type: SYSRSn

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9.6.2.32 CLB_OUTPUT_COND_CTRL_1 Register (Offset = 42h) [reset = 0h]

CLB_OUTPUT_COND_CTRL_1 is shown in Figure 9-49 and described in Table 9-48.
Return to the Summary Table.
Output conditioning control for output 1

Figure 9-49. CLB_OUTPUT_COND_CTRL_1 Register

31 30 29 28 27 26 25 24
RESERVED
R/W1C-0h
23 22 21 20 19 18 17 16
RESERVED
R/W1C-0h
15 14 13 12 11 10 9 8
RESERVED ASYNC_COND SEL_RAW_IN HW_RLS_CTR HW_GATING_ SEL_RELEASE_CTRL
_EN L_SEL CTRL_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
7 6 5 4 3 2 1 0
SEL_GATING_CTRL LEVEL_3_SEL LEVEL_2_SEL LEVEL_1_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 9-48. CLB_OUTPUT_COND_CTRL_1 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14 ASYNC_COND_EN R/W1C 0h Controls whether the output will pass through the asynchronous
conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path
Reset type: SYSRSn
13 SEL_RAW_IN R/W1C 0h Controls whether the CELL outputs or inputs are sent to the output
conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.
Reset type: SYSRSn
12 HW_RLS_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control
Reset type: SYSRSn
11 HW_GATING_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control
Reset type: SYSRSn
10-8 SEL_RELEASE_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Release control.
Reset type: SYSRSn
7-5 SEL_GATING_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Gating control.
Reset type: SYSRSn
4-3 LEVEL_3_SEL R/W1C 0h Controls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of
the output
10 Rising edge of Input signal will cause asynchronous SET of the
output
11 Input Signal delayed by 1 clock cycle will be sent to the output
Reset type: SYSRSn

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Table 9-48. CLB_OUTPUT_COND_CTRL_1 Register Field Descriptions (continued)

Bit Field Type Reset Description
2-1 LEVEL_2_SEL R/W1C 0h Controls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level
Reset type: SYSRSn
0 LEVEL_1_SEL R/W1C 0h First level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level
Reset type: SYSRSn

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9.6.2.33 CLB_OUTPUT_COND_CTRL_2 Register (Offset = 44h) [reset = 0h]

CLB_OUTPUT_COND_CTRL_2 is shown in Figure 9-50 and described in Table 9-49.
Return to the Summary Table.
Output conditioning control for output 2

Figure 9-50. CLB_OUTPUT_COND_CTRL_2 Register

31 30 29 28 27 26 25 24
RESERVED
R/W1C-0h
23 22 21 20 19 18 17 16
RESERVED
R/W1C-0h
15 14 13 12 11 10 9 8
RESERVED ASYNC_COND SEL_RAW_IN HW_RLS_CTR HW_GATING_ SEL_RELEASE_CTRL
_EN L_SEL CTRL_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
7 6 5 4 3 2 1 0
SEL_GATING_CTRL LEVEL_3_SEL LEVEL_2_SEL LEVEL_1_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 9-49. CLB_OUTPUT_COND_CTRL_2 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14 ASYNC_COND_EN R/W1C 0h Controls whether the output will pass through the asynchronous
conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path
Reset type: SYSRSn
13 SEL_RAW_IN R/W1C 0h Controls whether the CELL outputs or inputs are sent to the output
conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.
Reset type: SYSRSn
12 HW_RLS_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control
Reset type: SYSRSn
11 HW_GATING_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control
Reset type: SYSRSn
10-8 SEL_RELEASE_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Release control.
Reset type: SYSRSn
7-5 SEL_GATING_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Gating control.
Reset type: SYSRSn
4-3 LEVEL_3_SEL R/W1C 0h Controls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of
the output
10 Rising edge of Input signal will cause asynchronous SET of the
output
11 Input Signal delayed by 1 clock cycle will be sent to the output
Reset type: SYSRSn

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Table 9-49. CLB_OUTPUT_COND_CTRL_2 Register Field Descriptions (continued)

Bit Field Type Reset Description
2-1 LEVEL_2_SEL R/W1C 0h Controls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level
Reset type: SYSRSn
0 LEVEL_1_SEL R/W1C 0h First level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level
Reset type: SYSRSn

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9.6.2.34 CLB_OUTPUT_COND_CTRL_3 Register (Offset = 46h) [reset = 0h]

CLB_OUTPUT_COND_CTRL_3 is shown in Figure 9-51 and described in Table 9-50.
Return to the Summary Table.
Output conditioning control for output 3

Figure 9-51. CLB_OUTPUT_COND_CTRL_3 Register

31 30 29 28 27 26 25 24
RESERVED
R/W1C-0h
23 22 21 20 19 18 17 16
RESERVED
R/W1C-0h
15 14 13 12 11 10 9 8
RESERVED ASYNC_COND SEL_RAW_IN HW_RLS_CTR HW_GATING_ SEL_RELEASE_CTRL
_EN L_SEL CTRL_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
7 6 5 4 3 2 1 0
SEL_GATING_CTRL LEVEL_3_SEL LEVEL_2_SEL LEVEL_1_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 9-50. CLB_OUTPUT_COND_CTRL_3 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14 ASYNC_COND_EN R/W1C 0h Controls whether the output will pass through the asynchronous
conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path
Reset type: SYSRSn
13 SEL_RAW_IN R/W1C 0h Controls whether the CELL outputs or inputs are sent to the output
conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.
Reset type: SYSRSn
12 HW_RLS_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control
Reset type: SYSRSn
11 HW_GATING_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control
Reset type: SYSRSn
10-8 SEL_RELEASE_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Release control.
Reset type: SYSRSn
7-5 SEL_GATING_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Gating control.
Reset type: SYSRSn
4-3 LEVEL_3_SEL R/W1C 0h Controls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of
the output
10 Rising edge of Input signal will cause asynchronous SET of the
output
11 Input Signal delayed by 1 clock cycle will be sent to the output
Reset type: SYSRSn

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Table 9-50. CLB_OUTPUT_COND_CTRL_3 Register Field Descriptions (continued)

Bit Field Type Reset Description
2-1 LEVEL_2_SEL R/W1C 0h Controls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level
Reset type: SYSRSn
0 LEVEL_1_SEL R/W1C 0h First level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level
Reset type: SYSRSn

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9.6.2.35 CLB_OUTPUT_COND_CTRL_4 Register (Offset = 48h) [reset = 0h]

CLB_OUTPUT_COND_CTRL_4 is shown in Figure 9-52 and described in Table 9-51.
Return to the Summary Table.
Output conditioning control for output 4

Figure 9-52. CLB_OUTPUT_COND_CTRL_4 Register

31 30 29 28 27 26 25 24
RESERVED
R/W1C-0h
23 22 21 20 19 18 17 16
RESERVED
R/W1C-0h
15 14 13 12 11 10 9 8
RESERVED ASYNC_COND SEL_RAW_IN HW_RLS_CTR HW_GATING_ SEL_RELEASE_CTRL
_EN L_SEL CTRL_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
7 6 5 4 3 2 1 0
SEL_GATING_CTRL LEVEL_3_SEL LEVEL_2_SEL LEVEL_1_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 9-51. CLB_OUTPUT_COND_CTRL_4 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14 ASYNC_COND_EN R/W1C 0h Controls whether the output will pass through the asynchronous
conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path
Reset type: SYSRSn
13 SEL_RAW_IN R/W1C 0h Controls whether the CELL outputs or inputs are sent to the output
conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.
Reset type: SYSRSn
12 HW_RLS_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control
Reset type: SYSRSn
11 HW_GATING_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control
Reset type: SYSRSn
10-8 SEL_RELEASE_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Release control.
Reset type: SYSRSn
7-5 SEL_GATING_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Gating control.
Reset type: SYSRSn
4-3 LEVEL_3_SEL R/W1C 0h Controls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of
the output
10 Rising edge of Input signal will cause asynchronous SET of the
output
11 Input Signal delayed by 1 clock cycle will be sent to the output
Reset type: SYSRSn

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Table 9-51. CLB_OUTPUT_COND_CTRL_4 Register Field Descriptions (continued)

Bit Field Type Reset Description
2-1 LEVEL_2_SEL R/W1C 0h Controls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level
Reset type: SYSRSn
0 LEVEL_1_SEL R/W1C 0h First level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level
Reset type: SYSRSn

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9.6.2.36 CLB_OUTPUT_COND_CTRL_5 Register (Offset = 4Ah) [reset = 0h]

CLB_OUTPUT_COND_CTRL_5 is shown in Figure 9-53 and described in Table 9-52.
Return to the Summary Table.
Output conditioning control for output 5

Figure 9-53. CLB_OUTPUT_COND_CTRL_5 Register

31 30 29 28 27 26 25 24
RESERVED
R/W1C-0h
23 22 21 20 19 18 17 16
RESERVED
R/W1C-0h
15 14 13 12 11 10 9 8
RESERVED ASYNC_COND SEL_RAW_IN HW_RLS_CTR HW_GATING_ SEL_RELEASE_CTRL
_EN L_SEL CTRL_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
7 6 5 4 3 2 1 0
SEL_GATING_CTRL LEVEL_3_SEL LEVEL_2_SEL LEVEL_1_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 9-52. CLB_OUTPUT_COND_CTRL_5 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14 ASYNC_COND_EN R/W1C 0h Controls whether the output will pass through the asynchronous
conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path
Reset type: SYSRSn
13 SEL_RAW_IN R/W1C 0h Controls whether the CELL outputs or inputs are sent to the output
conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.
Reset type: SYSRSn
12 HW_RLS_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control
Reset type: SYSRSn
11 HW_GATING_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control
Reset type: SYSRSn
10-8 SEL_RELEASE_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Release control.
Reset type: SYSRSn
7-5 SEL_GATING_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Gating control.
Reset type: SYSRSn
4-3 LEVEL_3_SEL R/W1C 0h Controls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of
the output
10 Rising edge of Input signal will cause asynchronous SET of the
output
11 Input Signal delayed by 1 clock cycle will be sent to the output
Reset type: SYSRSn

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Table 9-52. CLB_OUTPUT_COND_CTRL_5 Register Field Descriptions (continued)

Bit Field Type Reset Description
2-1 LEVEL_2_SEL R/W1C 0h Controls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level
Reset type: SYSRSn
0 LEVEL_1_SEL R/W1C 0h First level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level
Reset type: SYSRSn

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9.6.2.37 CLB_OUTPUT_COND_CTRL_6 Register (Offset = 4Ch) [reset = 0h]

CLB_OUTPUT_COND_CTRL_6 is shown in Figure 9-54 and described in Table 9-53.
Return to the Summary Table.
Output conditioning control for output 6

Figure 9-54. CLB_OUTPUT_COND_CTRL_6 Register

31 30 29 28 27 26 25 24
RESERVED
R/W1C-0h
23 22 21 20 19 18 17 16
RESERVED
R/W1C-0h
15 14 13 12 11 10 9 8
RESERVED ASYNC_COND SEL_RAW_IN HW_RLS_CTR HW_GATING_ SEL_RELEASE_CTRL
_EN L_SEL CTRL_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
7 6 5 4 3 2 1 0
SEL_GATING_CTRL LEVEL_3_SEL LEVEL_2_SEL LEVEL_1_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 9-53. CLB_OUTPUT_COND_CTRL_6 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14 ASYNC_COND_EN R/W1C 0h Controls whether the output will pass through the asynchronous
conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path
Reset type: SYSRSn
13 SEL_RAW_IN R/W1C 0h Controls whether the CELL outputs or inputs are sent to the output
conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.
Reset type: SYSRSn
12 HW_RLS_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control
Reset type: SYSRSn
11 HW_GATING_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control
Reset type: SYSRSn
10-8 SEL_RELEASE_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Release control.
Reset type: SYSRSn
7-5 SEL_GATING_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Gating control.
Reset type: SYSRSn
4-3 LEVEL_3_SEL R/W1C 0h Controls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of
the output
10 Rising edge of Input signal will cause asynchronous SET of the
output
11 Input Signal delayed by 1 clock cycle will be sent to the output
Reset type: SYSRSn

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Table 9-53. CLB_OUTPUT_COND_CTRL_6 Register Field Descriptions (continued)

Bit Field Type Reset Description
2-1 LEVEL_2_SEL R/W1C 0h Controls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level
Reset type: SYSRSn
0 LEVEL_1_SEL R/W1C 0h First level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level
Reset type: SYSRSn

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9.6.2.38 CLB_OUTPUT_COND_CTRL_7 Register (Offset = 4Eh) [reset = 0h]

CLB_OUTPUT_COND_CTRL_7 is shown in Figure 9-55 and described in Table 9-54.
Return to the Summary Table.
Output conditioning control for output 7

Figure 9-55. CLB_OUTPUT_COND_CTRL_7 Register

31 30 29 28 27 26 25 24
RESERVED
R/W1C-0h
23 22 21 20 19 18 17 16
RESERVED
R/W1C-0h
15 14 13 12 11 10 9 8
RESERVED ASYNC_COND SEL_RAW_IN HW_RLS_CTR HW_GATING_ SEL_RELEASE_CTRL
_EN L_SEL CTRL_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
7 6 5 4 3 2 1 0
SEL_GATING_CTRL LEVEL_3_SEL LEVEL_2_SEL LEVEL_1_SEL
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 9-54. CLB_OUTPUT_COND_CTRL_7 Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R/W1C 0h Reserved
14 ASYNC_COND_EN R/W1C 0h Controls whether the output will pass through the asynchronous
conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path
Reset type: SYSRSn
13 SEL_RAW_IN R/W1C 0h Controls whether the CELL outputs or inputs are sent to the output
conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.
Reset type: SYSRSn
12 HW_RLS_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control
Reset type: SYSRSn
11 HW_GATING_CTRL_SEL R/W1C 0h Controls whether the HW (CELL outputs) or software (GP_REG) will
act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control
Reset type: SYSRSn
10-8 SEL_RELEASE_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Release control.
Reset type: SYSRSn
7-5 SEL_GATING_CTRL R/W1C 0h 3 bit MUX selects which will select one of the 8 CELL outputs for
Gating control.
Reset type: SYSRSn
4-3 LEVEL_3_SEL R/W1C 0h Controls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of
the output
10 Rising edge of Input signal will cause asynchronous SET of the
output
11 Input Signal delayed by 1 clock cycle will be sent to the output
Reset type: SYSRSn

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Table 9-54. CLB_OUTPUT_COND_CTRL_7 Register Field Descriptions (continued)

Bit Field Type Reset Description
2-1 LEVEL_2_SEL R/W1C 0h Controls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level
Reset type: SYSRSn
0 LEVEL_1_SEL R/W1C 0h First level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level
Reset type: SYSRSn

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9.6.2.39 CLB_MISC_ACCESS_CTRL Register (Offset = 50h) [reset = 0h]

CLB_MISC_ACCESS_CTRL is shown in Figure 9-56 and described in Table 9-55.
Return to the Summary Table.
Miscellaneous Access and enable control

Figure 9-56. CLB_MISC_ACCESS_CTRL Register

15 14 13 12 11 10 9 8
RESERVED
R/W1C-0h
7 6 5 4 3 2 1 0
RESERVED BLKEN SPIEN
R/W1C-0h R/W1C-0h R/W1C-0h

Table 9-55. CLB_MISC_ACCESS_CTRL Register Field Descriptions

Bit Field Type Reset Description
15-2 RESERVED R/W1C 0h Reserved
1 BLKEN R/W1C 0h This bit is used to block writes to CLB_OUT_EN
0 Writes to CLB_OUT_EN are allowed
1 Writes to CLB_OUT_EN are blocked
Reset type: SYSRSn
0 SPIEN R/W1C 0h This bit indicates the status of the SPI buffers ability to export CLB
output data.
0 Feature Disabled
1 Feature Enabled
Reset type: SYSRSn

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9.6.2.40 CLB_SPI_DATA_CTRL_HI Register (Offset = 51h) [reset = 0h]

CLB_SPI_DATA_CTRL_HI is shown in Figure 9-57 and described in Table 9-56.
Return to the Summary Table.
CLB to SPI buffer control High

Figure 9-57. CLB_SPI_DATA_CTRL_HI Register

15 14 13 12 11 10 9 8
RESERVED SHIFT
R/W1C-0h R/W1C-0h
7 6 5 4 3 2 1 0
RESERVED STRB
R/W1C-0h R/W1C-0h

Table 9-56. CLB_SPI_DATA_CTRL_HI Register Field Descriptions

Bit Field Type Reset Description
15-13 RESERVED R/W1C 0h Reserved
12-8 SHIFT R/W1C 0h This is a 5 bit value which denotes the first bit position of register R0
from which the Least Significant Bit of the output data should start.
00000 Output data is R0[15:0]
00001 Output data is R0[16:1]
00010 Output data is R0[17:2]
00011 Output data is R0[18:3]
...
...
10000 Output data is R0[31:16]
Reset type: SYSRSn
7-5 RESERVED R/W1C 0h Reserved
4-0 STRB R/W1C 0h This is a 5 bit value which selects one of the HLC_EVENT inputs to
be treated as the data_valid strobe
Reset type: SYSRSn

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9.6.3 CLB_LOGIC_CONTROL_REGS Registers

Table 9-57 lists the CLB_LOGIC_CONTROL_REGS registers. All register offset addresses not listed in
Table 9-57 should be considered as reserved locations and the register contents should not be modified.

Table 9-57. CLB_LOGIC_CONTROL_REGS Registers

Offset Acronym Register Name Write Protection Section
0h CLB_LOAD_EN Global enable & indirect load enable control EALLOW, LOCK Go
(only Global
Enable Bit is
LOCK protected)
2h CLB_LOAD_ADDR Indirect address Go
4h CLB_LOAD_DATA Data for indirect loads Go
6h CLB_INPUT_FILTER Input filter selection for both edge detection and LOCK Go
synchronizers
8h CLB_IN_MUX_SEL_0 Input selection to decide between Signals and LOCK Go
GP register
Ah CLB_LCL_MUX_SEL_1 Input Mux selection for local mux LOCK Go
Ch CLB_LCL_MUX_SEL_2 Input Mux selection for local mux LOCK Go
Eh CLB_BUF_PTR PUSH and PULL pointers Go
10h CLB_GP_REG General purpose register for CELL inputs Go
12h CLB_OUT_EN CELL output enable register Go
14h CLB_GLBL_MUX_SEL_1 Global Mux select for CELL inputs LOCK Go
16h CLB_GLBL_MUX_SEL_2 Global Mux select for CELL inputs LOCK Go
18h CLB_PRESCALE_CTRL Prescaler register control LOCK Go
20h CLB_INTR_TAG_REG Interrupt Tag register Go
22h CLB_LOCK Lock control register EALLOW Go
24h CLB_HLC_INSTR_READ_PTR HLC instruction read pointer Go
26h CLB_HLC_INSTR_VALUE HLC instruction read value Go
2Eh CLB_DBG_OUT_2 Visibility for CLB inputs and final asynchronous Go
outputs
30h CLB_DBG_R0 R0 of High level Controller Go
32h CLB_DBG_R1 R1 of High level Controller Go
34h CLB_DBG_R2 R2 of High level Controller Go
36h CLB_DBG_R3 R3 of High level Controller Go
38h CLB_DBG_C0 Count of Unit 0 Go
3Ah CLB_DBG_C1 Count of Unit 1 Go
3Ch CLB_DBG_C2 Count of Unit 2 Go
3Eh CLB_DBG_OUT Outputs of various units in the Cell Go

Complex bit access types are encoded to fit into small table cells. Table 9-58 shows the codes that are
used for access types in this section.

Table 9-58. CLB_LOGIC_CONTROL_REGS Access

Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
R-1 R Read
-1 Returns 1s
Write Type
W W Write

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Table 9-58. CLB_LOGIC_CONTROL_REGS Access

Type Codes (continued)
Access Type Code Description
W1C W Write
1C 1 to clear
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

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9.6.3.1 CLB_LOAD_EN Register (Offset = 0h) [reset = 0h]

CLB_LOAD_EN is shown in Figure 9-58 and described in Table 9-59.
Return to the Summary Table.
Global enable & indirect load enable control

Figure 9-58. CLB_LOAD_EN Register

15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
RESERVED PIPELINE_EN NMI_EN STOP GLOBAL_EN LOAD_EN
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-59. CLB_LOAD_EN Register Field Descriptions

Bit Field Type Reset Description
15-5 RESERVED R-0 0h Reserved
4 PIPELINE_EN R/W 0h This bit controls pipelining of all the CLB operations in HLC and
Counter blocks. Pipelined operation is enabled when this bit is set to
1.
Reset type: SYSRSn
3 NMI_EN R/W 0h This bit controls the generation of NMI along with the interrupt
whenever a INTR operation is executed by the HLC. NMI generation
is disabled by default. It will be enabled when this bit is set to 1.
Reset type: SYSRSn
2 STOP R/W 0h This bit defines the behaviour of the sequential elements in the
CELL during debug HALTs of the CPU. If this bit is set to 0, the
debug HALT condition is ignored.
Reset type: SYSRSn
1 GLOBAL_EN R/W 0h This bit is a global enable signal for the logic in the CELL. This also
acts as a soft reset for the CELL logic. This bit is normally set after
all the other configuration settings are completed. This bit is LOCK
protected.
Reset type: SYSRSn
0 LOAD_EN R/W 0h A write with this bit set to 1 will pulse the Load Enable signal for the
indirect register loads in the CELL.
Reset type: SYSRSn

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9.6.3.2 CLB_LOAD_ADDR Register (Offset = 2h) [reset = 0h]

CLB_LOAD_ADDR is shown in Figure 9-59 and described in Table 9-60.
Return to the Summary Table.
Indirect address

Figure 9-59. CLB_LOAD_ADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ADDR
R-0-0h R/W-0h

Table 9-60. CLB_LOAD_ADDR Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-0 ADDR R/W 0h These are the address bits used for writing to the indirect address
space of the CELL.
Reset type: SYSRSn

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9.6.3.3 CLB_LOAD_DATA Register (Offset = 4h) [reset = 0h]

CLB_LOAD_DATA is shown in Figure 9-60 and described in Table 9-61.
Return to the Summary Table.
Data for indirect loads

Figure 9-60. CLB_LOAD_DATA Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W-0h

Table 9-61. CLB_LOAD_DATA Register Field Descriptions

Bit Field Type Reset Description
31-0 DATA R/W 0h This register holds the 32-bit data for writing to the indirect address
space of the CELL.
Reset type: SYSRSn

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9.6.3.4 CLB_INPUT_FILTER Register (Offset = 6h) [reset = 0h]

CLB_INPUT_FILTER is shown in Figure 9-61 and described in Table 9-62.
Return to the Summary Table.
Input filter selection for both edge detection and synchronizers

Figure 9-61. CLB_INPUT_FILTER Register

31 30 29 28 27 26 25 24
PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
SYNC7 SYNC6 SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
FIN7 FIN6 FIN5 FIN4
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
FIN3 FIN2 FIN1 FIN0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-62. CLB_INPUT_FILTER Register Field Descriptions

Bit Field Type Reset Description
31 PIPE7 R/W 0h Enable pipelining for Input 7
Reset type: SYSRSn
30 PIPE6 R/W 0h Enable pipelining for Input 6
Reset type: SYSRSn
29 PIPE5 R/W 0h Enable pipelining for Input 5
Reset type: SYSRSn
28 PIPE4 R/W 0h Enable pipelining for Input 4
Reset type: SYSRSn
27 PIPE3 R/W 0h Enable pipelining for Input 3
Reset type: SYSRSn
26 PIPE2 R/W 0h Enable pipelining for Input 2
Reset type: SYSRSn
25 PIPE1 R/W 0h Enable pipelining for Input 1
Reset type: SYSRSn
24 PIPE0 R/W 0h Enable pipelining for Input 0
Reset type: SYSRSn
23 SYNC7 R/W 0h Synchronizer Select Control for Input 7
Reset type: SYSRSn
22 SYNC6 R/W 0h Synchronizer Select Control for Input 6
Reset type: SYSRSn
21 SYNC5 R/W 0h Synchronizer Select Control for Input 5
Reset type: SYSRSn
20 SYNC4 R/W 0h Synchronizer Select Control for Input 4
Reset type: SYSRSn
19 SYNC3 R/W 0h Synchronizer Select Control for Input 3
Reset type: SYSRSn
18 SYNC2 R/W 0h Synchronizer Select Control for Input 2
Reset type: SYSRSn
17 SYNC1 R/W 0h Synchronizer Select Control for Input 1
Reset type: SYSRSn

1218 Configurable Logic Block (CLB) SPRUII0B – May 2019 – Revised May 2020
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Table 9-62. CLB_INPUT_FILTER Register Field Descriptions (continued)

Bit Field Type Reset Description
16 SYNC0 R/W 0h Synchronizer Select Control for Input 0
Reset type: SYSRSn
15-14 FIN7 R/W 0h Input filter selection for CELL Input 7
2 bits are used to define the edge filtering .
00 : No filtering
01 : Rising edge detect
10 : Falling edge detect
11 : Any edge detect
Reset type: SYSRSn
13-12 FIN6 R/W 0h Input filter selection for CELL Input 6
2 bits are used to define the edge filtering .
00 : No filtering
01 : Rising edge detect
10 : Falling edge detect
11 : Any edge detect
Reset type: SYSRSn
11-10 FIN5 R/W 0h Input filter selection for CELL Input 5
2 bits are used to define the edge filtering .
00 : No filtering
01 : Rising edge detect
10 : Falling edge detect
11 : Any edge detect
Reset type: SYSRSn
9-8 FIN4 R/W 0h Input filter selection for CELL Input 4
2 bits are used to define the edge filtering .
00 : No filtering
01 : Rising edge detect
10 : Falling edge detect
11 : Any edge detect
Reset type: SYSRSn
7-6 FIN3 R/W 0h Input filter selection for CELL Input 3
2 bits are used to define the edge filtering .
00 : No filtering
01 : Rising edge detect
10 : Falling edge detect
11 : Any edge detect
Reset type: SYSRSn
5-4 FIN2 R/W 0h Input filter selection for CELL Input 2
2 bits are used to define the edge filtering .
00 : No filtering
01 : Rising edge detect
10 : Falling edge detect
11 : Any edge detect
Reset type: SYSRSn
3-2 FIN1 R/W 0h Input filter selection for CELL Input 1
2 bits are used to define the edge filtering .
00 : No filtering
01 : Rising edge detect
10 : Falling edge detect
11 : Any edge detect
Reset type: SYSRSn
1-0 FIN0 R/W 0h Input filter selection for CELL Input 0
2 bits are used to define the edge filtering .
00 : No filtering
01 : Rising edge detect
10 : Falling edge detect
11 : Any edge detect
Reset type: SYSRSn

SPRUII0B – May 2019 – Revised May 2020 Configurable Logic Block (CLB) 1219
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9.6.3.5 CLB_IN_MUX_SEL_0 Register (Offset = 8h) [reset = 0h]

CLB_IN_MUX_SEL_0 is shown in Figure 9-62 and described in Table 9-63.
Return to the Summary Table.
Input selection to decide between Signals and GP register

Figure 9-62. CLB_IN_MUX_SEL_0 Register

31 30 29 28 27 26 25 24
SW_GATING_ SW_GATING_ SW_GATING_ SW_GATING_ SW_GATING_ SW_GATING_ SW_GATING_ SW_GATING_
CTRL_7 CTRL_6 CTRL_5 CTRL_4 CTRL_3 CTRL_2 CTRL_1 CTRL_0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
SW_RLS_CTR SW_RLS_CTR SW_RLS_CTR SW_RLS_CTR SW_RLS_CTR SW_RLS_CTR SW_RLS_CTR SW_RLS_CTR
L_7 L_6 L_5 L_4 L_3 L_2 L_1 L_0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0-0h
7 6 5 4 3 2 1 0
SEL_GP_IN_7 SEL_GP_IN_6 SEL_GP_IN_5 SEL_GP_IN_4 SEL_GP_IN_3 SEL_GP_IN_2 SEL_GP_IN_1 SEL_GP_IN_0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-63. CLB_IN_MUX_SEL_0 Register Field Descriptions

Bit Field Type Reset Description
31 SW_GATING_CTRL_7 R/W 0h Software gating control for output 7 of the asynchronous output
conditioning block
Reset type: SYSRSn
30 SW_GATING_CTRL_6 R/W 0h Software gating control for output 6 of the asynchronous output
conditioning block
Reset type: SYSRSn
29 SW_GATING_CTRL_5 R/W 0h Software gating control for output 5 of the asynchronous output
conditioning block
Reset type: SYSRSn
28 SW_GATING_CTRL_4 R/W 0h Software gating control for output 4 of the asynchronous output
conditioning block
Reset type: SYSRSn
27 SW_GATING_CTRL_3 R/W 0h Software gating control for output 3 of the asynchronous output
conditioning block
Reset type: SYSRSn
26 SW_GATING_CTRL_2 R/W 0h Software gating control for output 2 of the asynchronous output
conditioning block
Reset type: SYSRSn
25 SW_GATING_CTRL_1 R/W 0h Software gating control for output 1 of the asynchronous output
conditioning block
Reset type: SYSRSn
24 SW_GATING_CTRL_0 R/W 0h Software gating control for output 0 of the asynchronous output
conditioning block
Reset type: SYSRSn
23 SW_RLS_CTRL_7 R/W 0h Software release control for output 7 of the asynchronous output
conditioning block
Reset type: SYSRSn
22 SW_RLS_CTRL_6 R/W 0h Software release control for output 6 of the asynchronous output
conditioning block
Reset type: SYSRSn

1220 Configurable Logic Block (CLB) SPRUII0B – May 2019 – Revised May 2020
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Table 9-63. CLB_IN_MUX_SEL_0 Register Field Descriptions (continued)

Bit Field Type Reset Description
21 SW_RLS_CTRL_5 R/W 0h Software release control for output 5 of the asynchronous output
conditioning block