International Journal of Trend in Scientific Research and Development (IJTSRD)

Volume 4 Issue 5, July-August 2020 Available Online: www.ijtsrd.com e-ISSN: 2456 – 6470

FPGA Implementation of QPSK Modulator and

Transmit Channelizer for Satellite Communication
Apoorva T R, Deepika Sankari G, Santhosh B
Department of Telecommunication, Dayananda Sagar College of Engineering, Bengaluru, Karnataka, India

ABSTRACT How to cite this paper: Apoorva T R |

The main objective of this project is to design & implement a Verilog design of Deepika Sankari G | Santhosh B "FPGA
QPSK Digital Modulator based on the Xilinx FPGA. In recent years, Digital Implementation of QPSK Modulator and
modulation has become less complex, more secure and more efficient in long Transmit Channelizer for Satellite
distance transmission such as in satellite communication. Here, a 1Mbps QPSK Communication"
modulator is designed for satellite communication applications. The input data Published in
generated using a PRBS generator and is then scrambled using a scrambler International Journal
and a symbol mapper. The symbol mapper, maps the binary data to IQ of Trend in Scientific
symbols. A Root Raised Cosine filter is designed for interpolating the signals Research and
after which a CIC filter is used for interpolating the signals to the DAC Development (ijtsrd),
sampling frequency. The DAC output is IQ modulated and up converted to an ISSN: 2456-6470, IJTSRD31828
L-band RF signal (1.2GHz). Thus, helping in long distance transmission. A basic Volume-4 | Issue-5,
receiver is built to test the transmission characteristics. This consists of a Root August 2020, pp.475-477, URL:
Raised Cosine (RRC) decimator, a Zero-crossing detector and a descrambler. www.ijtsrd.com/papers/ijtsrd31828.pdf

A channelizer is designed at the transmitter which simultaneously up-converts Copyright © 2020 by author(s) and
a number of baseband signals to assemble a set of FDM channels in a single International Journal of Trend in Scientific
sampled data signal stream. Research and Development Journal. This
is an Open Access
KEYWORDS: Quadrature Phase Shifting Keying (QPSK), Pseudo Random Binary article distributed
Sequence (PRBS), Verilog, Field Programmable Gate Array (FPGA) and under the terms of
Channelizer the Creative Commons Attribution
License (CC BY 4.0)
(http://creativecommons.org/licenses/by
/4.0)
I. INTRODUCTION II. QPSK MODULATOR DESIGN
One of the hottest topics that is undergoing immense This paper focuses on the design of a QPSK modulation and a
research and development is satellite communication. transmit channelizer which are simulated on MATLAB for
Satellite communication has many applications one of which functionality and also implemented on the hardware using
is its ability to communicate to long distances in a very less Verilog. The data to be modulated is in the form of a binary
time. When, we talk about long distance communication sequence. Here, a pseudo random binary sequence is
many factors are to be taken in consideration, such as considered. As the name suggests, the sequence is not
security, data rate, channel bandwidth, efficiency and many completely random as it repeats itself after a certain period
more. Modulation places a very important role in these, thus of time. The PRBS is later scrambled for the purpose of
the type of modulation that is selected should well suited for security and to avoid the problem of long sequences of 1’s
one’s requirements. and 0’s. Additive scrambler has the polynomial 1+z14+z15. An
Additive scrambler is used here which requires the initial
Quadrature Phase Shift keying, this form of modulation state of both the scrambler and the descrambler to be the
represents two bits as one and then it is transmitted. This same. The synchronization word used here is of length 15
helps in efficient usage of the available bandwidth. Since bits which is given by “10010101000000”. The scrambled
QPSK symbols are separated with a angle of π/2 fidelity is output is later given to the QPSK symbol generator which
maintained thus offering power efficiency as well. combines two consecutive bits into a symbol. A symbol is of
the form I+jQ where I and Q represents the inphase and
Here a QPSK modulator is built with a pseudo random quadrature components. Thus, the possible bit combinations
sequence as the input which is then encoded using a will have the following symbol representation:
scrambler and then to a QPSK symbol mapper after which
the symbols are interpolated and passed through an RRC TABLE I. QPSK Symbol Generation
filter to obtain a pulse shaped signal. the pulse shaped signal
Input In phase Quadrature Symbol
is again filter with a CIC filter to match the sampling
pair component component representation
frequency of the hard ware.
(0,0) -1 -1 -1-j
The simulation of this modulator is done both in MATLAB (0,1) -1 1 -1+j
and the RTL implementation is done in VIVADO. Using the (1,0) 1 -1 1-j
modulator which was built a Channelizer for the same was (1,1) 1 1 1+j
implemented.

@ IJTSRD | Unique Paper ID – IJTSRD31828 | Volume – 4 | Issue – 5 | July-August 2020 Page 475
 International Journal of Trend in Scientific Research and Development (IJTSRD) @ www.ijtsrd.com eISSN: 2456-6470
Once the symbols are generated, they are mapped onto the counter or a clock divider that is available in Vivado. After
plane with Inphase component along the X-axis and which instances for each module is created as required and
Quadrature component along the Y-axis. Hence there are connected using the wires which were predefined. It is very
four symbols present, one in each quadrant with a important that the size of the output of one module that is
separation of 900. These symbols are later filtered using a connected as the input to the other are same.
Root Raised Cosine Interpolation filter. The filter has a roll-
off factor of 0.25, with a span of 8 and containing 8 samples V. HARDWARE IMPLEMENTATION
per symbol. The symbols are first interpolated by a factor of Here, a Xilinx ZC706 Evaluation Board is used which has a
8, in order to increase the number of samples and also to chip inside, ZynQ XC72045. ZynQ is a SoC (system on chip)
prevent Inter Symbol Interference (ISI). The next step would which is, the system has both the FPGA and an ARM
be to convolute the interpolated signal with the filter co- processor which is dual core. To the Xilinx evaluation board,
efficient. This will result in a pulse shaped signal which can the Analog Devices Evaluation board will be connected
be transmitted through a channel. through the FMC port which has a chip named AD9361. This
evaluation board is called the FM COMMS2. This is a RF
In order to verify, if the same input bits are received after the Transmitter-Receiver which includes ADC, DAC, RF up-
demodulation process, a basic receiver is designed. The first converter and so on. The FM COMMS2 consists of two RF
procedure at the receiver is the Root Raised Cosine transmitter-receiver pairs. Since this paper is based on a
Decimation. Here the first step is to convolute the pulse transmit channelizer, the cable is connected from the
shaped signal with the same filter co-efficient which was transmitter of one of the Tx-Rx pairs to the spectrum
used at the transmitter. After this process, the convolution analyzer.
overheads are filtered out and hence the number of samples
will be same as that obtained after the interpolation process. VI. RESULTS
The next step is the decimation process, where in the Simulation on MATLAB gives us the functionality of the
sampling rate is reduced by decimating by a factor of 8, system. The above process was simulated on MATLAB and
which is the process of getting every eighth sample from the the results are as follows.
output. The output of the decimation process corresponds to
the symbols that were interpolated. The de-mapping of these In MATLAB, the symbols are processed as complex numbers
symbols will result in a binary sequence. This binary with inphase component being the real part and quadrature
sequence is equivalent to the scrambled output. Thus, the component being the imaginary part. Upon QPSK modulation
binary sequence upon descrambling which uses the same the following output is obtained.
synchronization word as the scrambler will give the input
fed to the system which is the Pseudo Random Binary In the output shown in the figure 1, the first figure indicates
Sequence. the PRBS sequence that is fed as the input. The second figure
represents the Root Raised Cosine filter coefficients. The
III. CHANNELIZER DESIGN third figure represents the pulse shaped signal and the last
Bandwidths are very expensive; hence the only wise choice one represents the data recovered.
is to use the available bandwidth to its full potential. This can
be done by using a channelizer that lets us pass many signals
at different frequencies using the same bandwidth that is
available. For simulation, same signals that were generated
using the QPSK modulator will be used. Two signals will be
generated using two different symbol rates. After generation
of two signals, one of the two signals will be multiplied by
different sine waves so that they will have different
frequencies. Here the aim is to create signals that will be
centered at frequencies 400 KHz, 800 KHz,1200KHz and at
1600 KHz. The MATLAB simulation and the RTL synthesis is
shown below in figures 2 and figure 5.
Fig.1. QPSK Modulation and Verification in MATLAB
IV. TESTBENCH
Test benches come in very handy as the input need not to be The pulse shaped signal after being passed through the CIC
individually forced each time, we run a simulation. Thus, filter, as seen in the figure 2, the signal at the center is at a
reducing time and man power required for every simulation symbol rate of 100kHz and the remaining four signals are at
that has to be run. The first step in writing a test bench is to a symbol rate of 200kHz which are multiplied with sine
define all the parameters with their respective sizes, that will waves of frequencies 400kHz,800kHz,1200kHz and 1600kHz
be used includes clock, valid and the other inputs and the respectively and added. This is done in order to transmit all
outputs of each module. the five signals through the same channel with a frequency
separation of 400kHz.
The initial values of reset and valid have to be defined. The
reset is initialized keeping in mind in which condition the
system goes into the reset condition, i.e. if it is active high
then system goes under reset if the input is ‘1’ or if it active
low then the system goes into reset when the input is ‘0’. The
clocks that are needed for each module to run is created
usually using a clock divider which is by simply using a

@ IJTSRD | Unique Paper ID – IJTSRD31828 | Volume – 4 | Issue – 5 | July-August 2020 Page 476
 International Journal of Trend in Scientific Research and Development (IJTSRD) @ www.ijtsrd.com eISSN: 2456-6470

Figure 4: Channelizer

The hardware implementation of the above gives the

following results.
Fig.2. Transmit Channelizer output

In case of Verilog, the QPSK modulation is performed and the

figure 3, shows the pulse shaped signal and the verification
of the process. The output shows the following: reset, clocks
at different frequencies, valid input, Inphase and Quadrature
components of a symbol, and the pulse shaped signal
truncated to 16 bits (I_tx and R_tx),decimated inphase and
quadrature components, bits recovered from the decimated
signal(I and Q bits), scrambled data, combined I and Q bits,
input PRBS and descrambled output in order.

In case of Verilog, the sine waves are generated using the

coefficients obtained in MATLAB and multiplied with the
Figure 5: Spectrum analyzer output
pulse shaped signal having a symbol rate of 200kHz. For the
signal with symbol rate of 100kHz the output of the CIC filter
REFERENCES
serves as the output. In case of Verilog as the inphase and
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quadrature components are dealt with separately, the
Implementation of BPSK and QPSK Modulators using
respective I and Q components of the five signals are added
Address Reverse Accumulators”, IEEE,2016.
separately.
[2] Akhil Khanna, Anju and Harsh Jain” Design and
Synthesis of Bandwidth Efficient QPSK Modulator for
Low Power VLSI Design”, Jaiswal ICECS 2015.
[3] K. Mounica, S. Mohan Das P. Uday Kumar.” A Verilog
Design in FPGA Implementation of Quadrature Phase
Shift Keying (QPSK) Digital Modulator”, International
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[4] Vishakha Pareek School “A Novel Implementation of
QPSK Modulator on FPGA”, 2016.
Fig.3. QPSK Modulation and Verification in VERILOG
[5] Wenmiao Song & Qiongqiong Yao. “Design and
The figure 4 represents the inphase components of the five Implement of QPSK Modem Based on FPGA” IEEE,
signals. As these signals are obtained after multiplying with a 2010.
sine wave, the signal has an envelope of a sine wave. The
[6] Digital Design, an embedded systems Approach using -
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Peter J. Ashenden.
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figure 4. Later, these inphase and quadrature components [7] Digital Signal Processing, 5th edition - by V. K. Ingle and
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