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TUSB4041I
SLLSEK3E – JULY 2015 – REVISED SEPTEMBER 2017

TUSB4041I Four-Port USB 2.0 Hub

1 Features • DM/DP Polarity Swap
•
1 Four Port USB 2.0 Hub • Type C Compatible
• USB 2.0 Hub Features • No Special Driver Requirements; Works
– Multi Transaction Translator (MTT) Hub: Four Seamlessly on any Operating System With USB
Transaction Translators Stack Support
– Four Asynchronous Endpoint Buffers per • 64-Pin HTQFP Package (PAP)
Transaction Translator
2 Applications
• Supports USB Battery Charging
• Computer Systems
– CDP Mode (Upstream Port Connected)
• Docking Stations
– DCP Mode (Upstream Port Unconnected)
• Monitors
– DCP Mode Complies With Chinese
Telecommunications Industry Standard YD/T • Set-Top Boxes
1591-2009
– Supports D+ and D– Divider Mode
3 Description
The TUSB4041I device is a four-port USB 2.0 hub.
• Per Port or Ganged Power Switching and The device provides USB high-speed or full-speed
Overcurrent Notification Inputs connections on the upstream port. The device also
• OTP ROM, Serial EEPROM or I2C and SMBus provides USB high-speed, full-speed, or low-speed
Slave Interface for Custom Configurations: connections on the downstream ports. When the
– VID and PID upstream port is connected to an electrical
environment that only supports high-speed, full-
– Customizable Ports speed, and low-speed connections, the USB high-
– Manufacturer and Product Strings (not by OTP speed, full-speed and low-speed connectivity is
ROM) enabled on the downstream ports. When the
– Serial Number (not by OTP ROM) upstream port is connected to an electrical
environment that only supports full-speed or low-
• Application Feature Selection Using Pin Selection speed connections, the USB high-speed connectivity
or EEPROM, I2C, or SMBus Slave Interface are disabled on the downstream ports.
• Provides 128-Bit Universally Unique Identifier
(UUID) Device Information(1)
• Supports On-Board and In-System OTP and PART NUMBER PACKAGE BODY SIZE (NOM)
EEPROM Programming Through the USB 2.0 TUSB4041I HTQFP (64) 10.00 mm × 10.00 mm
Upstream Port (1) For all available packages, see the orderable addendum at
• Single Clock Input, 24-MHz Crystal or Oscillator the end of the data sheet.

Type A
Port
USB2
WebCAM
Personal
Computer TUSB4041I
USB 1.1
Mouse

TI USB 1.1
Keyboard

USB 2.0 Connection USB 2.0 Hub USB 2.0 Device

USB 1.x Connection USB 2.0 Port USB 1.1 Device

Copyright © 2016, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.5 Register Maps ......................................................... 16
2 Applications ........................................................... 1 9 Application and Implementation ........................ 29
3 Description ............................................................. 1 9.1 Application Information............................................ 29
4 Revision History..................................................... 2 9.2 Typical Application .................................................. 29
5 Description (continued)......................................... 3 10 Power Supply Recommendations ..................... 36
10.1 TUSB4041I Power Supply .................................... 36
6 Pin Configuration and Functions ......................... 4
10.2 Downstream Port Power ....................................... 36
7 Specifications......................................................... 8
10.3 Ground .................................................................. 36
7.1 Absolute Maximum Ratings ...................................... 8
7.2 ESD Ratings ............................................................ 8 11 Layout................................................................... 37
11.1 Layout Guidelines ................................................. 37
7.3 Recommended Operating Conditions....................... 9
11.2 Layout Example .................................................... 38
7.4 Thermal Information .................................................. 9
7.5 3.3-V I/O Electrical Characteristics ........................... 9 12 Device and Documentation Support ................. 39
7.6 Power-Up Timing Requirements............................. 10 12.1 Documentation Support ........................................ 39
7.7 Hub Input Supply Current ....................................... 10 12.2 Receiving Notification of Documentation Updates 39
12.3 Community Resource............................................ 39
8 Detailed Description ............................................ 11
12.4 Trademarks ........................................................... 39
8.1 Overview ................................................................. 11
12.5 Electrostatic Discharge Caution ............................ 39
8.2 Functional Block Diagram ....................................... 11
12.6 Glossary ................................................................ 39
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 15 13 Mechanical, Packaging, and Orderable
Information ........................................................... 39

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (July 2017) to Revision E Page

• Changed smbusRst From: Bit 6 To: Bit 1, and cfgActive1 From: Bit 5 To: Bit 0 Table 25 ................................................. 28

Changes from Revision C (September 2016) to Revision D Page

• Deleted paragraph: "Each bit corresponds directly to a downstream port. For example: used0 corresponds to
downstream port 1, used1 corresponds to downstream port 2, and so on. All combinations are supported with the
exception of both ports 1 and 3 marked as disabled." from Table 12 .................................................................................. 21

Changes from Revision B (December 2015) to Revision C Page

• Added SMBUS Programming current to Hub Input Supply Current .................................................................................... 10

• Added NOTE to the SMBus Slave Operation section ......................................................................................................... 15
• Added text "This device will always report the XORed PID LSB value of 0x42" to the Description of Table 7 .................. 18

Changes from Revision A (September 2015) to Revision B Page

• Changed the configuration of the PWRCTL_POL pin (R17) in the Clock, Reset, and Miscellaneous section .................... 34

Changes from Original (July 2015) to Revision A Page

• Changed pin number for USB_DP_DN1 and USB_DP_DN2 in the Pin Functions table ...................................................... 6

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5 Description (continued)
The TUSB4041I device supports per-port or ganged power switching and overcurrent protection. The device also
supports battery charging applications.
An individually port-power-controlled hub switches power on or off to each downstream port as requested by the
USB host. Also when an individually port-power-controlled hub senses an overcurrent event, only power to the
affected downstream port is switched off.
A ganged hub switches on power to all of the downstream ports when power is required to be on for any port.
The power to the downstream ports is not switched off unless all ports are in a state that allows power to be
removed. Also, when a ganged hub senses an overcurrent event, power to all downstream ports are switched
off.
The TUSB4041I device downstream ports provide support for battery charging applications by providing USB
battery charging downstream-port (CDP) handshaking support. The device also supports a dedicated charging-
port (DCP) mode when the upstream port is not connected. The DCP mode is compliant with the USB battery
charging specification and Chinese Telecommunications Industry Standard YD/T 1591-2009. Also, an automatic
mode provides transparent support for BC devices and devices supporting divider-mode charging solutions when
the upstream port unconnected.
The TUSB4041I device provides pin-strap configuration for some features including battery charging support,
and also provides customization though OTP ROM, I2C EEPROM, or through an I2C and SMBus slave interface
for PID, VID, and custom port and phy configurations. Custom string support is also available when using an I2C
EEPROM or the I2C and SMBus slave interface.
The device is available in a 64-pin PAP package and is offered in a industrial version for operation over the
temperature range of –40°C to 85°C.

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6 Pin Configuration and Functions

PAP Package
64-Pin HTQFP With PowerPAD™
Top View

USB_DM_DN2

USB_DM_DN1
USB_DP_DN2

USB_DP_DN1
VDD33
RSVD
RSVD

RSVD
RSVD

RSVD
RSVD

RSVD
RSVD
VDD

VDD
NC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

USB_DP_DN3 49 32 USB_R1
USB_DM_DN3 50 31 VDD33
RSVD 51 30 XI
RSVD 52 29 XO
VDD 53 28 NC
RSVD 54 27 RSVD
RSVD 55 26 RSVD
USB_DP_DN4 56 25 VDD
USB_DM_DN4 57 24 RSVD
RSVD 58 23 RSVD
RSVD 59 22 USB_DM_UP
VDD 60 21 USB_DP_UP
RSVD 61 20 VDD33
RSVD 62 19
VDD
VDD 63 18 GRSTz
PWRCTL4/BATEN4 64 17 TEST

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PWRCTL3/BATEN3
VDD33
PWRCTL2/BATEN2
PWRCTL1/BATEN1
SDA/SMBDAT
SCL/SMBCLK
SMBUSz
FULLPWRMGMTz/SMBA1
PWRCTL_POL
GANGED/SMBA2/HS_UP
OVERCUR4z
OVERCUR3z
AUTOENz/HS_SUSPEND
OVERCUR1z
OVERCUR2z
USB_VBUS

NC = No internal connection

Pin Functions
PIN
I/O (1) TYPE (1) DESCRIPTION
NAME NO.
CLOCK AND RESET SIGNALS
Global power reset. This reset brings all of the TUSB4041I device internal registers to
GRSTz 18 I PU the default state. When the GRSTz pin is asserted, the device is completely
nonfunctional.
Crystal input. This pin is the crystal input for the internal oscillator. The input may
XI 30 I — alternately be driven by the output of an external oscillator. When using a crystal, a 1-
MΩ feedback resistor is required between the XI and XO pins.

(1) I = Input, O = Output, I/O = Input/output, PU = Internal pullup resistor, PD = Internal pulldown resistor, and PWR = Power signal
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Pin Functions (continued)

PIN
I/O (1) TYPE (1) DESCRIPTION
NAME NO.
Crystal output. This pin is the crystal output for the internal oscillator. If the XI pin is
XO 29 O — driven by an external oscillator, this pin may be left unconnected. When using a
crystal, a 1-MΩ feedback resistor is required between the XI and XO pins.
USB UPSTREAM SIGNALS
USB_DM_UP 22 I/O — USB high-speed differential transceiver (negative)
USB_DP_UP 21 I/O — USB high-speed differential transceiver (positive)
I — Precision resistor reference. Connect a 9.53-kΩ ±1% resistor between the USB_R1
USB_R1 32
pin and ground.
I — USB upstream port power monitor. The VBUS detection requires a voltage divider.
USB_VBUS 16 The signal USB_VBUS must be connected to VBUS through a 90.9-kΩ ±1% resistor
and to ground through a 10-kΩ ±1% resistor from the signal to ground.
USB DOWNSTREAM SIGNALS
USB port 1 overcurrent detection. This pin is used to connect the overcurrent output
of the downstream port power switch for port 1.
0 = An overcurrent event occurred.
OVERCUR1z 14 I PU 1 = An overcurrent event has not occurred.
This pin can be left unconnected if power management is not implemented. If power
management is enabled, the necessary external circuitry should be determined by the
power switch.
USB port 2 overcurrent detection. This pin is used to connect the overcurrent output
of the downstream port power switch for port 2.
0 = An overcurrent event occurred.
OVERCUR2z 15 I PU 1 = An overcurrent event has not occurred.
If power management is not implemented, leave this pin unconnected. If power
management is enabled, the necessary external circuitry should be determined by the
power switch.
USB port 3 overcurrent detection. This pin is used to connect the overcurrent output
of the downstream port power switch for port 3.
0 = An overcurrent event occurred.
OVERCUR3z 12 I PU 1 = An overcurrent event has not occurred.
This pin can be left unconnected if power management is not implemented. If power
management is enabled, the necessary external circuitry should be determined by the
power switch.
USB port 4 overcurrent detection. This pin is used to connect the overcurrent output
of the downstream port power switch for port 4.
0 = An overcurrent event occurred.
OVERCUR4z 11 I PU 1 = An overcurrent event has not occurred.
This pin can be left unconnected if power management is not implemented. If power
management is enabled, the necessary external circuitry should be determined by the
power switch.
USB port 1 power-on control for downstream power and battery charging enable. The
pin is used for control of the downstream power switch for port 1.
The value of the pin is sampled at the deassertion of reset to determine the value of
PWRCTL1/BATEN1 4 I/O PD the battery charging support for port 1 as indicated in the Battery Charging Support
Register:
0 = Battery charging not supported
1 = Battery charging supported
USB port 2 power-on control for downstream power and battery charging enable. The
pin is used for control of the downstream power switch for port 2.
The value of the pin is sampled at the deassertion of reset to determine the value of
PWRCTL2/BATEN2 3 I/O PD the battery charging support for Port 2 as indicated in the Battery Charging Support
Register:
0 = Battery charging not supported
1 = Battery charging supported

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Pin Functions (continued)

PIN
I/O (1) TYPE (1) DESCRIPTION
NAME NO.
USB port 3 power-on control for downstream power and battery charging enable. The
pin is used for control of the downstream power switch for port 3.
The value of the pin is sampled at the deassertion of reset to determine the value of
PWRCTL3/BATEN3 1 I/O PD the battery charging support for Port 3 as indicated in the Battery Charging Support
Register:
0 = Battery charging not supported
1 = Battery charging supported
USB port 4 power-on control for downstream power and battery charging enable. The
pin is used for control of the downstream power switch for port 4.
The value of the pin is sampled at the deassertion of reset to determine the value of
PWRCTL4/BATEN4 64 I/O PD the battery charging support for Port 4 as indicated in the Battery Charging Support
Register:
0 = Battery charging not supported
1 = Battery charging supported
USB_DM_DN1 34
USB_DM_DN2 42
I/O — USB high-speed differential transceiver (negative)
USB_DM_DN3 50
USB_DM_DN4 57
USB_DP_DN1 33
USB_DP_DN2 41
I/O — USB high-speed differential transceiver (positive)
USB_DP_DN3 49
USB_DP_DN4 56
I2C AND SMBus SIGNALS
I2C clock/SMBus clock. The function of this pin depends on the setting of the
SMBUSz input.
When SMBUSz = 1, this pin functions as the serial clock interface for an I2C
SCL/SMBCLK 6 I/O PD EEPROM.
When SMBUSz = 0, this pin functions as the serial clock interface for an SMBus
host.
This pin can be left unconnected if external interface not implemented.
I2C data/SMBus data. The function of this pin depends on the setting of the SMBUSz
input.
When SMBUSz = 1, this pin functions as the serial data interface for an I2C
SDA/SMBDAT 5 I/O PD EEPROM.
When SMBUSz = 0, this pin functions as the serial data interface for an SMBus
host.
This pin can be left unconnected if the external interface is not implemented.
I2C/SMBus mode select. The value of the pin is sampled at the deassertion of reset
set I2C or SMBus mode as follows:
1 = I2C mode selected
0 = SMBus mode selected
SMBUSz 7 I/O PU
This pin can be left unconnected if the external interface is not implemented.
After reset, this signal is driven low by the TUSB4041I. Because of this behavior, TI
recommends not to tie directly to supply, but instead pull up or pull down using
external resistor.

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Pin Functions (continued)

PIN
I/O (1) TYPE (1) DESCRIPTION
NAME NO.
TEST AND MISCELLANEOUS SIGNALS
Automatic charge mode enable/HS suspend status
The value of the pin is sampled at the deassertion of reset to determine if automatic
mode is enabled as follows:
0 = Automatic mode is enabled on ports that are enabled for battery charging when
the hub is unconnected. Note that CDP is not supported on port 1 when operating
AUTOENz/ in automatic mode.
13 I/O PU
HS_SUSPEND 1 = Automatic mode is disabled.
This value is also used to set the autoEnz bit in the Battery Charging Support
Register.
After reset, this signal indicates the high-speed USB Suspend status of the upstream
port if enabled through the Additional Feature Configuration Register. When enabled,
a value of 1 indicates the connection is suspended.
Full power management enable/SMBus address bit 1
The value of the pin is sampled at the deassertion of reset to set the power switch
control follows:
0 = Power switching and overcurrent inputs supported
1 = Power switching and overcurrent inputs not supported
Full power management is the ability to control power to the downstream ports of the
TUSB4041I device using PWRCTL[4:1]/BATEN[4:1].
FULLPWRMGMTz/
8 I/O PD
SMBA1 When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus
slave address bit 1.
This pin can be left unconnected if full power management and SMBus are not
implemented.
After reset, this signal is driven low by the TUSB4041I. Because of this behavior, TI
recommends not to tie directly to supply, but instead pull up or pull down using an
external resistor.
Note: Power switching must be supported for battery charging applications.
Ganged operation enable/SMBus address bit 2/HS connection status upstream port
The value of the pin is sampled at the deassertion of reset to set the power switch
and overcurrent detection mode as follows:
0 = Individual power control supported when power switching is enabled
1 = Power control gangs supported when power switching is enabled
GANGED/SMBA2/
10 I/O PD When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus
HS_UP
slave address bit 2.
After reset, this signal indicates the high-speed USB connection status of the
upstream port if enabled through the Additional Feature Configuration Register. When
enabled, a value of 1 indicates the upstream port is connected to a high-speed USB
capable port.
Note: Individual power control must be enabled for battery charging applications.
Power control polarity.
The value of the pin is sampled at the deassertion of reset to set the polarity of
PWRCTL_POL 9 I/O PU PWRCTL[4:1].
0 = PWRCTL polarity is active low
1 = PWRCTL polarity is active high
23, 24,
26, 27,
35, 36,
38, 39,
43, 44,
RSVD I/O Reserved. For internal use only and leave unconnected on the PCB.
46, 47,
51, 52,
54, 55,
58, 59,
61, 62

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Pin Functions (continued)

PIN
I/O (1) TYPE (1) DESCRIPTION
NAME NO.
TEST 17 I PD This pin is reserved for factory test.
POWER AND GROUND SIGNALS
28
NC — — No connection, leave floating
40
19
25
37
VDD 45 — PWR 1.1-V power rail
53
60
63
2
20
VDD33 — PWR 3.3-V power rail
31
48
Thermal Pad — — Ground. The thermal pad must be connected to ground.

7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
MIN MAX UNIT
VDD steady-state supply voltage –0.3 1.4 V
Supply voltage
VDD33 steady-state supply voltage –0.3 3.8 V
USB_VBUS pin –0.3 1.4 V
Voltage XI pins –0.3 2.45 V
All other pins –0.3 3.8 V
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed as Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated as Recommended Operating Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±4000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1000
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
(1)
VDD 1.1-V supply voltage 0.99 1.1 1.26 V
VDD33 3.3-V supply voltage 3 3.3 3.6 V
V(USB_VBUS) Voltage at USB_VBUS pin 0 1.155 V
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 105 °C

(1) A 1.05-V, 1.1-V, or 1.2-V supply may be used as long as minimum and maximum supply conditions are met.

7.4 Thermal Information

TUSB4041I
THERMAL METRIC (1) PAP (HTQFP) UNIT
64 PINS
RθJA Junction-to-ambient thermal resistance 26.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 11.5 °C/W
RθJB Junction-to-board thermal resistance 10.4 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 10.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.6 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7.5 3.3-V I/O Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER OPERATION TEST CONDITIONS MIN TYP MAX UNIT
(1)
VIH High-level input voltage VDD33 2 VDD33 V
JTAG pins only 0 0.55
VIL Low-level input voltage (1) VDD33 V
Other pins 0 0.8
VI Input voltage 0 VDD33 V
VO Output voltage (2) 0 VDD33 V
tt Input transition time (tr and tf) 0 25 ns
Vhys Input hysteresis (3) 0.13 x VDD33 V
VOH High-level output voltage VDD33 IOH = –4 mA 2.4 V
VOL Low-level output voltage VDD33 IOL = 4 mA 0.4 V
IOZ High-impedance, output current (2) VDD33 VI = 0 to VDD33 ±20 µA
High-impedance, output current
IOZ(P) with internal pullup or pulldown VDD33 VI = 0 to VDD33 ±250 µA
resistor (4)
II Input current (5) VDD33 VI = 0 to VDD33 ±15 µA

(1) Applies to external inputs and bidirectional buffers.

(2) Applies to external outputs and bidirectional buffers.
(3) Applies to GRSTz.
(4) Applies to pins with internal pull-ups and pull-downs.
(5) Applies to external input buffers.

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7.6 Power-Up Timing Requirements

MIN NOM MAX UNIT
td1 VDD33 stable before VDD stable (1) See (2)
ms
td2 VDD and VDD33 stable before deassertion of GRSTz 3 ms
tsu_io Setup for MISC inputs (3) sampled at the deassertion of GRSTz 0.1 µs
(3)
thd_io Hold for MISC inputs sampled at the deassertion of GRSTz 0.1 µs
tVDD33_RAMP VDD33 supply ramp requirements 0.2 100 ms
tVDD_RAMP VDD supply ramp requirements 0.2 100 ms

(1) An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay
counting from both power supplies being stable to the de-assertion of GRSTz.
(2) The VDD33 and VDD have no power-on relationship unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable
minimum of 10 μs before the VDD33.
(3) MISC pins sampled at de-assertion of GRSTz: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN[4:1], and AUTOENz.

td2

GRSTz

VDD33

td1

VDD

tsu_io thd_io
MISC_IO

Figure 1. Power-Up Timing Requirements

7.7 Hub Input Supply Current

Typical values measured at TA = 25°C
VDD33 VDD
PARAMETER UNIT
3.3 V 1.1 V
LOW POWER MODES
Power on (after reset) 2.3 28 mA
Upstream disconnect 2.3 28 mA
Suspend 2.5 33 mA
ACTIVE MODES (US STATE AND DS STATE)
2.0 host / 1 HS device 45 63 mA
2.0 host / 4 HS devices 76 86 mA
SMBUS Programming current 79 225 mA

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8 Detailed Description

8.1 Overview
The TUSB4041I device is a four-port USB 2.0 hub. The device provides USB high-speed and full-speed
connections on the upstream port and provides USB high-speed, full-speed, or low-speed connections on the
downstream ports. When the upstream port is connected to an electrical environment that only supports high-
speed connections. USB high-speed connectivity is enabled on the downstream ports. When the upstream port
is connected to an electrical environment that only supports full-speed and low-speed connections. USB high-
speed connectivity is disabled on the downstream ports.

8.2 Functional Block Diagram

USB_DM_UP
USB_DP_UP

USB_VBUS
USB_R1

VDD33 VBUS
Power
VDD
Distribution Detect
VSS

USB 2.0 Hub

XI
Oscillator
XO
USB_DM_DN1

USB_DM_DN2

USB_DM_DN3

USB_DM_DN4
USB_DP_DN1

USB_DP_DN2

USB_DP_DN3

USB_DP_DN4

Clock
and
GRSTz
Reset
Distribution

TEST
GANGED/SMBA2/HS_UP
FULLPWRMGMTz/SMBA1
PWRCTL_POL
SMBUSz
AUTOENz/HS_SUSPEND
SCL/SMBCLK
Control OTP
SDA/SMBDAT
Registers ROM
OVERCUR1z GPIO
PWRCTL1/BATEN1 I2C
SMBUS
OVERCUR2z
PWRCTL2/BATEN2

OVERCUR3z
PWRCTL3/BATEN3

OVERCUR4z
PWRCTL4/BATEN4

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8.3 Feature Description

8.3.1 Battery Charging Features
The TUSB4041I device provides support for USB battery charging. Battery charging support may be enabled on
a per port basis through the REG_6h(batEn[3:0]).
Battery charging support includes both CDP and DCP modes. The DCP mode is compliant with the Chinese
Telecommunications Industry Standard YD/T 1591-2009.
In addition to standard DCP mode, the TUSB4041I device provides a mode (AUTOMODE), which automatically
provides support for DCP devices and devices that support custom charging indication. When in AUTOMODE,
the port automatically switches between a divider mode and the DCP mode depending on the portable device
connected. The divided mode places a fixed DC voltage on the ports DP and DM signals, which allows some
devices to identify the capabilities of the charger. The default divider mode indicates support for up to 10 W. The
divider mode can be configured to report a legacy current setting (up to 5 W) through
REG_Ah(HiCurAcpModeEn).
The battery charging mode for each port is dependent on the state of Reg_6h(batEn[n]), the status of the VBUS
input, and the state of REG_Ah(autoModeEnz) upstream port as identified in Table 1.

Table 1. TUSB4041I Battery Charging Modes

BC MODE PORT x
batEn[n] VBUS autoModeEnz
(x = n + 1)
0 Don’t care Don’t care Don’t Care
0 Automode (1) (2)
<4 V
1 1 DCP (3) (4)
>4 V Don’t care CDP (3)

(1) Auto-mode automatically selects divider-mode or DCP mode.

(2) Divider mode can be configured for legacy current mode through register settings.
(3) Attached USB device is USB battery-charging specification revision 1.2 compliant
(4) Chinese Telecommunications Industry Standard YD/T 1591-2009

8.3.2 USB Power Management

The TUSB4041I device can be configured for power-switched applications using either per-port or ganged
power-enable controls and overcurrent status inputs.
Power switch support is enabled by REG_5h(fullPwrMgmtz), and the per-port or ganged mode is configured by
REG_5h(ganged).
The TUSB4041I device supports both active-high and active-low power-enable controls. The PWRCTL[4:1]
polarity is configured by REG_Ah(pwrctlPol).

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8.3.3 One-Time Programmable Configuration

The TUSB4041I device allows device configuration through one-time programmable (OTP) non-volatile memory.
The programming of the OTP is supported using vendor-defined USB device requests. Contact TI for details
using the OTP features
Table 2 lists features that can be configured using the OTP.

Table 2. OTP Configurable Features

CONFIGURATION REGISTER
BIT FIELD DESCRIPTION
OFFSET
REG_01h [7:0] Vendor ID LSB
REG_02h [7:0] Vendor ID MSB
REG_03h [7:0] Product ID LSB
REG_04h [7:0] Product ID MSB
Port-removable configuration for downstream ports 1. OTP configuration is
REG_07h [0]
inverse of rmbl[3:0], that is 1 = not removable, 0 = removable.
Port-removable configuration for downstream ports 2. OTP configuration is
REG_07h [1]
inverse of rmbl[3:0], that is 1 = not removable, 0 = removable.
Port-removable configuration for downstream ports 3. OTP configuration is
REG_07h [2]
inverse of rmbl[3:0], that is 1 = not removable, 0 = removable.
Port-removable configuration for downstream ports 4. OTP configuration is
REG_07h [3]
inverse of rmbl[3:0], that is 1 = not removable, 0 = removable.
REG_0Ah [3] Enable device attach detection
REG_0Ah [4] High-current divider mode enable
REG_0Bh [0] USB 2.0 port polarity configuration for downstream ports 1
REG_0Bh [1] USB 2.0 port polarity configuration for downstream ports 2
REG_0Bh [2] USB 2.0 port polarity configuration for downstream ports 3
REG_0Bh [3] USB 2.0 port polarity configuration for downstream ports 4
REG_F0h [3:1] USB power switch power-on delay

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8.3.4 Clock Generation

The TUSB4041I device accepts a crystal input to drive an internal oscillator or an external clock source. If a clock
is provided to the XI pin instead of a crystal, the XO pin is left open. Otherwise, if a crystal is used, the
connection must follow these guidelines. Because the XI and XO pins are coupled to other leads and supplies on
the PCB, keep traces as short as possible and away from any switching leads. Minimize the capacitance
between the XI and XO pins by shielding C1 and C2 with the clean ground lines.

R1
10 M

XI

XO

24 MHz

CL1 CL2

Copyright © 2016, Texas Instruments Incorporated

Figure 2. TUSB4041I Clock

8.3.5 Crystal Requirements

The crystal must be fundamental mode with load capacitance of 12 to 24 pF and frequency stability rating of
±100 PPM or better. To ensure proper startup oscillation condition, TI recommends a maximum crystal
equivalent series resistance (ESR) of 50 Ω. If a crystal source is used, use a parallel load capacitor. The exact
load capacitance value used depends on the crystal vendor. Refer to application note Selection and Specification
for Crystals for Texas Instruments USB 2.0 Devices (SLLA122) for details on how to determine the load
capacitance value.

8.3.6 Input Clock Requirements

When using an external clock source such as an oscillator, the reference clock should have a frequency stability
of ±100 PPM or better and have less than 50-ps absolute peak-to-peak jitter. Tie XI to the 1.8-V clock source,
and leave XO floating.

8.3.7 Power-Up and Reset

The TUSB4041I device does not have specific power-sequencing requirements with respect to the core power
(VDD) or I/O and analog power (VDD33). The core power (VDD) or I/O power (VDD33) can be powered up for an
indefinite period of time while the other is not powered up if all of the following constraints are met:
• Observe all maximum ratings and recommended operating conditions.
• Observe all warnings about exposure to maximum rated and recommended conditions, particularly junction
temperature. These apply to power transitions and normal operation.
• Limit bus contention to 100 hours over the projected lifetime of the device while VDD33 is powered-up.
• Do not exceed the ratings listed in the Absolute Maximum Ratings table for bus contention while VDD33 is
powered-down.
A supply bus is powered-up when the voltage is within the recommended operating range. A supply bus is
powered-down when it is below that range, and either stable or in transition.
The device requires a minimum reset duration of 3 ms. This reset duration is defined as the time when the power
supplies are in the recommended operating range to the deassertion of the GRSTz pin. Generate the reset pulse
using a programmable-delay supervisory device or using an RC circuit.

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8.4 Device Functional Modes

8.4.1 External Configuration Interface
The TUSB4041I device supports a serial interface for configuration register access. The device can be
configured by an attached I2C EEPROM or accessed as a slave by an SMBus-capable host controller. The
external interface is enabled when both the SCL/SMBCLK and SDA/SMBDAT pins are pulled up to 3.3 V at the
deassertion of reset. The mode, I2C master or SMBus slave, is determined by the state of SMBUSz pin at reset.

8.4.2 I2C EEPROM Operation

The TUSB4041I device supports a single-master, standard mode (100 kb/s) connection to a dedicated I2C
EEPROM when the I2C interface mode is enabled. In I2C mode, the TUSB4041I device reads the contents of the
EEPROM at bus address 1010000b using 7-bit addressing starting at address 0.
If the value of the EEPROM contents at byte 00h equals 55h, the TUSB4041I device loads the configuration
registers according to the EEPROM map. If the first byte is not 55h, the TUSB4041I device exits the I2C mode
and continues execution with the default values in the configuration registers. The hub does not connect on the
upstream port until the configuration is completed. If the hub detected an unprogrammed EEPROM (value other
than 55h), the hub enters programming mode and a programming endpoint within the hub is enabled.

NOTE
The bytes located above offset Ah are optional. The requirement for data in those
addresses is dependent on the options configured in the Device Configuration Register
and Device Configuration Register 2.

For details on I2C operation, refer to the UM10204 I2C-bus Specification and User Manual.

8.4.3 SMBus Slave Operation

When the SMBus interface mode is enabled, the TUSB4041I device supports read block and write block
protocols as a slave-only SMBus device.
The TUSB4041I device slave address is 1000 1xyz, where:
• x is the state of GANGED/SMBA2/HS_UP pin at reset
• y is the state of FULLPWRMGMTz/SMBA1 pin at reset
• z is the read-write (R/W) bit; 1 = read access, 0 = write access
If the TUSB4041I device is addressed by a host using an unsupported protocol, the device does not respond.
The TUSB4041I device waits indefinitely for configuration by the SMBus host and does not connect on the
upstream port until the SMBus host indicates configuration is complete by clearing the CFG_ACTIVE bit.
For details on SMBus requirements, refer to the System Management Bus (SMBus) Specification.

NOTE
During the SMBUS configuration the hub may draw an extra current, this extra current
consumption will end as soon as the CFG_ACTIVE bit is cleared. For more information
refer to Hub Input Supply Current section in this datasheet.

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8.5 Register Maps

8.5.1 Configuration Registers
The internal configuration registers are accessed on byte boundaries. The configuration register values are
loaded with defaults, but can be overwritten when the TUSB4041I device is in I2C or SMBus mode.

Table 3. Memory Map

BYTE ADDRESS CONTENTS EEPROM CONFIGURABLE
00h ROM Signature Register No
01h Vendor ID LSB Yes
02h Vendor ID MSB Yes
03h Product ID LSB Yes
04h Product ID MSB Yes
05h Device Configuration Register Yes
06h Battery Charging Support Register Yes
07h Device Removable Configuration Register Yes
08h Port Used Configuration Register Yes
09h Reserved Yes, program to 00h
0Ah Device Configuration Register 2 Yes
0Bh USB 2.0 Port Polarity Control Register Yes
0Ch to 0Fh Reserved No
10h to 1Fh UUID Byte [15:0] No
20h to 21h LangID Byte [1:0] Yes, if customStrings is set
22h Serial Number String Length Yes, if customSerNum is set
23h Manufacturer String Length Yes, if customStrings is set
24h Product String Length Yes, if customStrings is set
25h to 2Fh Reserved No
30h to 4Fh Serial Number String Byte [31:0] Yes, if customSerNum is set
50h to 8Fh Manufacturer String Byte [63:0] Yes, if customStrings is set
90h to CFh Product String Byte [63:0] Yes, if customStrings is set
D0 to DFh Reserved No
F0h Additional Feature Configuration Register Yes
F1 to F7h Reserved No
F8h Device Status and Command Register No
F9 to FFh Reserved No

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8.5.2 ROM Signature Register

Offset = 0h
Figure 3. ROM Signature Register
7 6 5 4 3 2 1 0
romSignature
RW-0

Table 4. ROM Signature Register Field Descriptions

Bit Field Type Reset Description

ROM signature register

The TUSB4041I device uses this register in I2C mode to validate whether the
7:0 romSignature RW 0 attached EEPROM has been programmed. The first byte of the EEPROM is
compared to the mask 55h and if not a match, the TUSB4041I device aborts the
EEPROM load and executes with the register defaults.

8.5.3 Vendor ID LSB Register

Offset = 1h, reset = 51h
Figure 4. Vendor ID LSB Register
7 6 5 4 3 2 1 0
vendorIdLsb[7] vendorIdLsb[6] vendorIdLsb[5] vendorIdLsb[4] vendorIdLsb[3:1] vendorIdLsb[0]
R/RW-0 R/RW-1 R/RW-0 R/RW-1 R/RW-0 R/RW-1

Table 5. Vendor ID LSB Register Field Descriptions

Bit Field Type Reset Description
7 vendorIdLsb[7] R/RW 0 Vendor ID LSB
6 vendorIdLsb[6] R/RW 1 Least significant byte of the unique vendor ID assigned by the USB-IF; the
5 vendorIdLsb[5] R/RW 0 default value of this register is 51h representing the LSB of the TI Vendor ID
0451h. The value may be overwritten to indicate a customer vendor ID.
4 vendorIdLsb[4] R/RW 1
This field is R/W unless the OTP ROM VID and OTP ROM PID values are non-
3:1 vendorIdLsb[3:1] R/RW 0 zero. If both values are non-zero, the value when reading this register will
0 vendorIdLsb[0] R/RW 1 reflect the OTP ROM value.

8.5.4 Vendor ID MSB Register

Offset = 2h, reset = 04h
Figure 5. Vendor ID MSB Register
7 6 5 4 3 2 1 0
vendorIdMsb[7:3] vendorIdMsb[2] vendorIdMsb[1:0]
R/RW-0 R/RW-1 R/RW-0

Table 6. Vendor ID MSB Register Field Descriptions

Bit Field Type Reset Description
7:3 vendorIdMsb[7:3] R/RW 0 Vendor ID MSB
2 vendorIdMsb[2] R/RW 1 Most significant byte of the unique vendor ID assigned by the USB-IF; the default
value of this register is 04h representing the MSB of the TI Vendor ID 0451h. The
value may be overwritten to indicate a customer vendor ID.
1:0 vendorIdMsb[1:0] R/RW 0 This field is R/W unless the OTP ROM VID and OTP ROM PID values are non-zero.
If both values are non-zero, the value when reading this register shall reflect the
OTP ROM value.

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8.5.5 Product ID LSB Register

Offset = 3h, reset = 40h
Figure 6. Product ID LSB Register
7 6 5 4 3 2 1 0
productIdLsb[7] productIdLsb[6] productIdLsb[5:0]
R/RW-0 R/RW-1 R/RW-0

Table 7. Product ID LSB Register Field Descriptions

Bit Field Type Reset Description
7 productIdLsb[7] R/RW 0 Product ID LSB.
6 productIdLsb[6] R/RW 1 The default value of this register is 40h representing the LSB of the product
ID assigned by TI. The value reported in the USB 2.0 device descriptor is
the value of this register bit wise XORed with 00000010b. This device will
always report the XORed PID LSB value of 0x42. The value may be
5:0 productIdLsb[5:0] R/RW 0 overwritten to indicate a customer product ID.
This field is R/W unless the OTP ROM VID and OTP ROM PID values are
non-zero. If both values are non-zero, the value when reading this register
will reflect the OTP ROM value.

8.5.6 Product ID MSB Register

Offset = 4h, reset = 81h
Figure 7. Product ID MSB Register
7 6 5 4 3 2 1 0
productIdMsb[7] productIdMsb[6:1] productIdMsb[0]
R/RW-1 R/RW-0 R/RW-1

Table 8. Product ID MSB Register Field Descriptions

Bit Field Type Reset Description
7 productIdMsb[7] R/RW 1 Product ID MSB
6:1 productIdMsb[6:1] R/RW 0 Most significant byte of the product ID assigned by TI; the default value of this
register is 81h representing the MSB of the product ID assigned by TI. The
value may be overwritten to indicate a customer product ID.
0 productIdMsb[0] R/RW 1 This field is R/W unless the OTP ROM VID and OTP ROM PID values are
non-zero. If both values are non-zero, the value when reading this register will
reflect the OTP ROM value.

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8.5.7 Device Configuration Register

Offset = 5h
Figure 8. Device Configuration Register
7 6 5 4 3 2 1 0
customStrings customSernum RSVD RSVD ganged fullPwrMgmtz RSVD RSVD
RW-0 RW-0 RW-0 R-1 RW-X RW-X RW-0 R-0

Table 9. Device Configuration Register Field Descriptions

Bit Field Type Reset Description

Custom strings enable

This bit controls the ability to write to the Manufacturer String Length, Manufacturer
String, Product String Length, Product String, and Language ID registers
0 = The Manufacturer String Length, Manufacturer String, Product String
7 customStrings RW 0 Length, Product String, and Language ID registers are read only.
1 = The Manufacturer String Length, Manufacturer String, Product String
Length, Product String, and Language ID registers may be loaded by
EEPROM or written by SMBus.
The default value of this bit is 0.

Custom serial number enable

This bit controls the ability to write to the serial number registers.
0 = The Serial Number String Length and Serial Number String registers are
6 customSernum RW 0 read only.
1 = Serial Number String Length and Serial Number String registers may be
loaded by EEPROM or written by SMBus.
The default value of this bit is 0.
5 RSVD RW 0 Reserved.
4 RSVD R 1 Reserved. This bit is reserved and returns 1 when read.

Ganged
This bit is loaded at the deassertion of reset with the value of the
GANGED/SMBA2/HS_UP pin.
0 = Each port is individually power switched and enabled by the
PWRCTL[4:1]/BATEN[4:1] pins.
3 ganged RW X
1 = The power switch control for all ports is ganged and enabled by the
PWRCTL[4:1]/BATEN1 pin.
When the TUSB4041I device is in I2C mode, the TUSB4041I device loads this bit
from the contents of the EEPROM.
When the TUSB4041I device is in SMBUS mode, the value may be overwritten by
an SMBus host.

Full power management

This bit is loaded at the deassertion of reset with the value of the
FULLPWRMGMTz/SMBA1 pin.
0 = Port power switching status reporting is enabled
2 fullPwrMgmtz RW X
1 = Port power switching status reporting is disabled
When the TUSB4041I device is in I2C mode, the TUSB4041I device loads this bit
from the contents of the EEPROM.
When the TUSB4041I device is in SMBUS mode, the value may be overwritten by
an SMBus host.

Reserved
1 RSVD RW 0
This field is reserved and should not be altered from the default.

Reserved
0 RSVD R 0
This field is reserved and returns 0 when read.

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8.5.8 Battery Charging Support Register

Offset = 6h
Figure 9. Battery Charging Support Register
7 6 5 4 3 2 1 0
RSVD batEn[3:0]
R-0 RW-X

Table 10. Battery Charging Support Register Field Descriptions

Bit Field Type Reset Description

Reserved
7:4 RSVD R 0
Read only, returns 0 when read.

Battery Charger Support. The bits in this field indicate whether the downstream port
implements the charging port features.
0 = The port is not enabled for battery charging support features
1 = The port is enabled for battery charging support features
3:0 batEn[3:0] RW X Each bit corresponds directly to a downstream port, that is batEn0 corresponds to
downstream port 1, and batEN1 corresponds to downstream port 2.
The default value for these bits are loaded at the deassertion of reset with the value
of PWRCTL/BATEN[3:0].
When in I2C/SMBus mode the bits in this field may be overwritten by EEPROM
contents or by an SMBus host.

8.5.9 Device Removable Configuration Register

Offset = 7h
Figure 10. Device Removable Configuration Register
7 6 5 4 3 2 1 0
customRmbl RSVD rmbl[3:0]
RW-0 R-0 RW-X

Table 11. Device Removable Configuration Register Field Descriptions

Bit Field Type Reset Description

Custom removable
This bit controls the ability to write to the port removable bits.
7 customRmbl RW 0 0 = rmbl[3:0] are read only, and the values are loaded from the OTP ROM.
1 = rmbl[3:0] are R/W and can be loaded by EEPROM or written by SMBus.
This bit may be written simultaneously with rmbl[3:0].

Reserved
6:4 RSVD R 0
Read only, returns 0 when read

Removable
The bits in this field indicate whether a device attached to downstream ports 4
through 1 are removable or permanently attached.
0 = The device attached to the port is not removable.
3:0 rmbl[3:0] RW X 1 = The device attached to the port is removable.
Each bit corresponds directly to a downstream port n + 1, For example: rmbl0
corresponds to downstream port 1, rmbl1 corresponds to downstream port 2, and
so on.
This field is read only unless the customRmbl bit is set to 1. Otherwise, the value of
this field reflects the inverted values of the OTP ROM non_rmb[3:0] field.

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8.5.10 Port Used Configuration Register

Offset = 8h
Figure 11. Port Used Configuration Register
7 6 5 4 3 2 1 0
RSVD used[3:0]
R-0 RW-1

Table 12. Port Used Configuration Register Field Descriptions

Bit Field Type Reset Description

Reserved
7:4 RSVD R 0
Read only

Used
The bits in this field indicate whether a port is enabled.
3:0 used[3:0] RW 1
0 = The port is disabled.
1 = The port is enabled.

8.5.11 Device Configuration Register 2

Offset = Ah
Figure 12. Device Configuration Register 2
7 6 5 4 3 2 1 0
RSVD customBCfeatu pwrctlPol HiCurAcpMode cpdEN RSVD autoModeEnz RSVD
res En
R-0 RW-0 RW-X R/RW-0 R/RW-0 RW-0 RW-X R-0

Table 13. Device Configuration Register 2 Field Descriptions

Bit Field Type Reset Description

Reserved
7 RSVD R 0
Read only, returns 0 when read.

Custom battery charging feature enable

This bit controls the ability to write to the battery charging feature configuration
controls.
0 = The HiCurAcpModeEn and cpdEN bits are read only and the values
6 customBCfeatures RW 0
are loaded from the OTP ROM.
1 = The HiCurAcpModeEn and cpdEN, bits are R/W and can be loaded
by EEPROM or written by SMBus from this register.
This bit may be written simultaneously with HiCurAcpModeEn and cpdEN.

Power enable polarity

This bit is loaded at the deassertion of reset with the value of the
PWRCTL_POL pin.
0 = PWRCTL polarity is active low.
5 pwrctlPol RW X
1 = PWRCTL polarity is active high.
When the TUSB4041I device is in I2C mode, the TUSB4041I device loads this
bit from the contents of the EEPROM.
When the TUSB4041I device is in SMBUS mode, the value may be
overwritten by an SMBus host.

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Table 13. Device Configuration Register 2 Field Descriptions (continued)

Bit Field Type Reset Description

High-current ACP mode enable

This bit enables the high-current tablet charging mode when the automatic
battery charging mode is enabled for downstream ports.
0 = High-current divider mode disabled. Legacy current divider mode
4 HiCurAcpModeEn R/RW 0 enabled.
1 = High-current divider mode enabled
This bit is read only unless the customBCfeatures bit is set to 1. If
customBCfeatures is 0, the value of this bit reflects the value of the
OTP ROM HiCurAcpModeEn bit.

Enable device attach detection

This bit enables device attach detection (such as a cell-phone detect) when
auto mode is enabled.

3 cpdEN RRW 0 0 = Device attach detect is disabled in auto mode.

1 = Device attach detect is enabled in auto mode.
This bit is read only unless the customBCfeatures bit is set to 1. If
customBCfeatures is 0, the value of this bit reflects the value of the OTP ROM
cpdEN bit.
2 RSVD RW 0 Reserved

Automatic mode enable (1)

This bit is loaded at the deassertion of reset with the value of the
AUTOENz/HS_SUSPEND pin.
The automatic mode only applies to downstream ports with battery charging
1 autoModeEnz RW X enabled when the upstream port is not connected. Under these conditions:
0 = Automatic mode battery charging features are enabled.
1 = Automatic mode is disabled; only battery-charging DCP mode is
supported.

Reserved
0 RSVD R 0
Read only, returns 0 when read.

(1) When the upstream port is connected, battery charging 1.2 CDP mode will be supported on all ports that are enabled for battery
charging support regardless of the value of this bit, with the exception of port 1. CDP on port 1 is not supported when automatic mode is
enabled.

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8.5.12 USB 2.0 Port Polarity Control Register

Offset = Bh
Figure 13. USB 2.0 Port Polarity Control Register
7 6 5 4 3 2 1 0
customPolarity RSVD p4_usb2pol p3_usb2pol p2_usb2pol p1_usb2pol p0_usb2pol
RW-0 R-0 R/RW-0 R/RW-0 R/RW-0 R/RW-0 R/RW-0

Table 14. USB 2.0 Port Polarity Control Register Field Descriptions
Bit Field Type Reset Description

Custom USB 2.0 polarity

This bit controls the ability to write the p[4:0]_usb2pol bits.
0 = The p[4:0]_usb2pol bits are read only, and the values are loaded from the
7 customPolarity RW 0 OTP ROM.
1 = The p[4:0]_usb2pol bits are R/W and can be loaded by EEPROM or written
by SMBus from this register.
This bit may be written simultaneously with the p[4:0]_usb2pol bits

Reserved
6:5 RSVD R 0
Read only, returns 0 when read

Downstream port 4 DM/DP polarity

This bit controls the polarity of the port.
0 = USB 2.0 port polarity is as shown in the pinout.
4 p4_usb2pol R/RW 0
1 = USB 2.0 port polarity is swapped from that shown in the pinout (that is, DM
becomes DP, and DP becomes DM).
This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0, the
value of this bit reflects the value of the OTP ROM p4_usb2pol bit.

Downstream port 3 DM/DP polarity

This bit controls the polarity of the port.
0 = USB 2.0 port polarity is as shown in the pinout.
3 p3_usb2pol R/RW 0
1 = USB 2.0 port polarity is swapped from that shown in the pinout (that is, DM
becomes DP, and DP becomes DM).
This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0, the
value of this bit reflects the value of the OTP ROM p3_usb2pol bit.

Downstream port 2 DM/DP polarity

This bit controls the polarity of the port.
0 = USB 2.0 port polarity is as shown in the pinout.
2 p2_usb2pol R/RW 0
1 = USB 2.0 port polarity is swapped from that shown in the pinout (that is, DM
becomes DP, and DP becomes DM).
This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0, the
value of this bit reflects the value of the OTP ROM p2_usb2pol bit.

Downstream port 1 DM/DP polarity

This bit controls the polarity of the port.
0 = USB 2.0 port polarity is as shown in the pinout.
1 p1_usb2pol RRW 0
1 = USB 2.0 port polarity is swapped from that shown in the pinout (that is, DM
becomes DP, and DP becomes DM).
This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0, the
value of this bit reflects the value of the OTP ROM p1_usb2pol bit.

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Table 14. USB 2.0 Port Polarity Control Register Field Descriptions (continued)
Bit Field Type Reset Description

Upstream port DM/DP polarity

This bit controls the polarity of the port.
0 = USB 2.0 port polarity is as shown in the pinout.
0 p0_usb2pol R/RW 0
1 = USB 2.0 port polarity is swapped from that shown in the pinout (that is, DM
becomes DP, and DP becomes DM).
This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0, the
value of this bit reflects the value of the OTP ROM p0_usb2pol bit.

8.5.13 UUID Byte N Register

Offset = 10h-1Fh
Figure 14. UUID Byte N Register
7 6 5 4 3 2 1 0
uuidByte[n]
R-X

Table 15. UUID Byte N Register Field Descriptions

Bit Field Type Reset Description

UUID byte N
7:0 uuidByte[n] R X The UUID returned in the Container ID descriptor. The value of this register is
provided by the device and meets the UUID requirements of the Internet
Engineering Task Force (IETF) RFC 4122 A UUID URN Namespace.

8.5.14 Language ID LSB Register

Offset = 20h, reset = 09h
Figure 15. Language ID LSB Register
7 6 5 4 3 2 1 0
langIdLsb[7:4] langIdLsb[3] langIdLsb[2:1] langIdLsb[0]
R/RW-0 R/RW-1 R/RW-0 R/RW-1

Table 16. Language ID LSB Register Field Descriptions

Bit Field Type Reset Description
7:4 langIdLsb[7:4] R/RW 0 Language ID least significant byte
3 langIdLsb[3] R/RW 1 This register contains the value returned in the LSB of the LANGID code in string
2:1 langIdLsb[2:1] R/RW 0 index 0. The TUSB4041I device only supports one language ID. The default
value of this register is 09h representing the LSB of the LangID 0409h indicating
English United States.
0 langIdLsb[0] R/RW 1 When the customStrings bit is set to 1, this field may be overwritten by the
contents of an attached EEPROM or by an SMBus host.

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8.5.15 Language ID MSB Register

Offset = 21h, reset = 04h
Figure 16. Language ID MSB Register
7 6 5 4 3 2 1 0
langIdMsb[7:3] langIdMsb[2] langIdMsb[1:0]
R/RW-0 R/RW-1 R/RW-0

Table 17. Language ID MSB Register Field Descriptions

Bit Field Type Reset Description
7:3 langIdMsb[7:3] R/RW 0 Language ID most significant byte
2 langIdMsb[2] R/RW 1 This register contains the value returned in the MSB of the LANGID code in
string index 0. The TUSB4041I device only supports one language ID. The
default value of this register is 04h representing the MSB of the LangID 0409h
1:0 langIdMsb[1:0] R/RW 0 indicating English United States.
When the customStrings bit is set to 1, this field may be overwritten by the
contents of an attached EEPROM or by an SMBus host.

8.5.16 Serial Number String Length Register

Offset = 22h
Figure 17. Serial Number String Length Register
7 6 5 4 3 2 1 0
RSVD serNumStringL serNumStringLen[4:3] serNumStringLen[2:0]
en[5]
R-0 R/RW-0 R/RW-1 R/RW-0

Table 18. Serial Number String Length Register Field Descriptions

Bit Field Type Reset Description

Reserved
7:6 RSVD R 0
Read only, returns 0 when read.
5 serNumStringLen[5] R/RW 0 Serial number string length
4:3 serNumStringLen[4:3] R/RW 1 The string length in bytes for the serial number string. The default value is
18h indicating that a 24-byte serial number string is supported. The
maximum string length is 32 bytes.
When the customSernum bit is set to 1, this field may be overwritten by the
2:0 serNumStringLen[2:0] R/RW 0 contents of an attached EEPROM or by an SMBus host.
When the field is non-zero, a serial number string of serNumbStringLen
bytes is returned at string index 1 from the data contained in the Serial
Number String registers.

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8.5.17 Manufacturer String Length Register

Offset = 23h
Figure 18. Manufacturer String Length Register
7 6 5 4 3 2 1 0
RSVD mfgStringLen
R-0 R/RW-0

Table 19. Manufacturer String Length Register Field Descriptions

Bit Field Type Reset Description

Reserved
7 RSVD R 0
Read only, returns 0 when read

Manufacturer string length

The string length in bytes for the manufacturer string. The default value is 0,
indicating that a manufacturer string is not provided. The maximum string length is 64
bytes.
6:0 mfgStringLen R/RW 0
When the customStrings bit is set to 1, this field may be overwritten by the contents of
an attached EEPROM or by an SMBus host.
When the field is non-zero, a manufacturer string of mfgStringLen bytes is returned at
string index 3 from the data contained in the Manufacturer String registers.

8.5.18 Product String Length Register

Offset = 24h
Figure 19. Product String Length Register
7 6 5 4 3 2 1 0
RSVD prodStringLen
R-0 R/RW-0

Table 20. Product String Length Register Field Descriptions

Bit Field Type Reset Description

Reserved
7 RSVD R 0
Read only, returns 0 when read.

Product string length

The string length in bytes for the product string. The default value is 0, indicating
that a product string is not provided. The maximum string length is 64 bytes.
6:0 prodStringLen R/RW 0 When the customStrings bit is set to 1, this field may be overwritten by the contents
of an attached EEPROM or by an SMBus host.
When the field is non-zero, a product string of prodStringLen bytes is returned at
string index 3 from the data contained in the Product String registers.

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8.5.19 Serial Number String Registers

Offset = 30h-4Fh
Figure 20. Serial Number String Registers
7 6 5 4 3 2 1 0
serialNumber[n]
R/RW-X

Table 21. Serial Number String Registers Field Descriptions

Bit Field Type Reset Description

Serial Number byte N

7:0 serialNumber[n] R/RW X The serial number returned in the Serial Number string descriptor at string index 1.
The default value of these registers is assigned by TI. When customSernum is 1,
these registers may be overwritten by EEPROM contents or by an SMBus host.

8.5.20 Manufacturer String Registers

Offset = 50h-8Fh
Figure 21. Manufacturer String Registers
7 6 5 4 3 2 1 0
mfgStringByte[n]
R/W-0

Table 22. Manufacturer String Registers Field Descriptions

Bit Field Type Reset Description

Manufacturer string byte N

These registers provide the string values returned for string index 3 when
7:0 mfgStringByte[n] R/W 0 mfgStringLen is greater than 0. The number of bytes returned in the string is
equal to mfgStringLen.
The programmed data should be in UNICODE UTF-16LE encodings as defined
by the Unicode Standard, Worldwide Character Encoding, Version 5.0.

8.5.21 Product String Byte N Register

Offset = 90h-CFh
Figure 22. Product String Byte N Register
7 6 5 4 3 2 1 0
prodStringByte[n]
R/RW-0

Table 23. Product String Byte N Register Field Descriptions

Bit Field Type Reset Description

Product string byte N

These registers provide the string values returned for string index 2 when
7:0 prodStringByte[n] R/RW 0 prodStringLen is greater than 0. The number of bytes returned in the string is
equal to prodStringLen.
The programmed data should be in UNICODE UTF-16LE encodings as defined by
the Unicode Standard, Worldwide Character Encoding, Version 5.0.

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8.5.22 Additional Feature Configuration Register

Offset = F0h
Figure 23. Additional Feature Configuration Register
7 6 5 4 3 2 1 0
RSVD stsOutputEn pwronTime RSVD
R-0 R/RW-0 R/W-0 R/W-0

Table 24. Additional Feature Configuration Register Field Descriptions

Bit Field Type Reset Description

Reserved
7:5 RSVD R 0
Read only, returns 0 when read.
4 RSVD R/RW 0 Reserved.

Power-on delay time

When OTP ROM pwronTime field is all 0, this field sets the delay time from the
removal disable of PWRCTL to the enable of PWRCTL when transitioning battery
charging modes. For example, when disabling the power on a transition from a
3:1 pwronTime RW 0
custom charging mode to dedicated charging port mode. The nominal timing is
defined as follows:
TPWRON_EN = (pwronTime + 1) x 200 ms (1)
This field may be overwritten by EEPROM contents or by an SMBus host.
0 RSVD RW 0 Reserved

8.5.23 Device Status and Command Register

Offset = F8h
Figure 24. Device Status and Command Register
7 6 5 4 3 2 1 0
RSVD smbusRst cfgActive
R-0 W1S-0 W1C-0

Table 25. Device Status and Command Register Field Descriptions

Bit Field Type Reset Description

Reserved
7:2 RSVD R 0
Read only, returns 0 when read

SMBus interface reset

1 smbusRst W1S 0 This bit loads the registers back to their GRSTz values.
This bit is set by writing a 1 and is cleared by hardware on completion of the reset. A
write of 0 has no effect.

Configuration active
This bit indicates that configuration of the TUSB4041I device is currently active. The
bit is set by hardware when the device enters the I2C or SMBus mode. The
0 cfgActive W1C 0 TUSB4041I device does not connect on the upstream port while this bit is 1.
When in the SMBus mode, this bit must be cleared by the SMBus host to exit the
configuration mode and allow the upstream port to connect.
The bit is cleared by a writing 1. A write of 0 has no effect.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TUSB4041I device is a four-port USB 2.0 hub. The provides USB high-speed and full-speed connections on
the upstream port and provides USB high-speed, full-speed, or low-speed connections on the downstream port.
The TUSB4041I device can be used in any application that requires additional USB-compliant ports. For
example, a specific notebook may only have two downstream USB ports. By using the TUSB4041I device, the
notebook can increase the downstream port count to five.

9.2 Typical Application

A common application for the TUSB4041I device is as a self-powered standalone USB-hub product. The product
is powered by an external 5-V DC power adapter. In this application, using a USB cable, the upstream port of the
TUSB4041I device is plugged into a USB host controller. The downstream ports of the TUSB4041I device are
exposed to users for connecting USB hard drives, cameras, flash drives, and so forth.

USB
DC Type B
Power Connector

US Port

TUSB4041I

USB USB
Power Switch Power Switch

DS Port 1 DS Port 2 DS Port 3 DS Port 4

USB Type A USB Type A USB Type A USB Type A

Connector Connector Connector Connector

Copyright © 2016, Texas Instruments Incorporated

Figure 25. Discrete USB Hub Product

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Typical Application (continued)

9.2.1 Design Requirements
For this design example, use the parameters listed in Table 26.

Table 26. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VDD supply 1.1 V
VDD33 supply 3.3 V
Upstream port USB support (HS, FS) HS, FS
Downstream port 1 USB support (HS, FS, LS) HS, FS, LS
Downstream port 2 USB support (HS, FS, LS) HS, FS, LS
Downstream port 3 USB support (HS, FS, LS) HS, FS, LS
Downstream port 4 USB support (HS, FS, LS) HS, FS, LS
Number of removable downstream ports 4
Number of non-removable downstream ports 0
Full power management of downstream ports Yes (FULLPWRMGMTZ = 0)
Individual control of downstream port power switch Yes (GANGED = 0)
Power switch enable polarity Active high (PWRCTL_POL = 1)
Battery charge support for downstream port 1 Yes
Battery charge support for downstream port 2 Yes
Battery charge support for downstream port 3 Yes
Battery charge support for downstream port 4 Yes
I2C EEPROM support No
24-MHz clock source Crystal

9.2.2 Detailed Design Procedure

9.2.2.1 Upstream Port Implementation

R1 90.9 KΩ U1A
10
0402 R2 GANGED/SMBA2/HS_UP
C1 1% 10 KΩ 1% 8
10 µF 0402 FULLPWRMGMTZ/SMBA1
1%
Type B USB-Shield 16
USB_VBUS R3 R4
6 +5V 1 VBUS 4.7 KΩ 4.7 KΩ
DM 2 USB_DM_UP 22
USB_DM_UP
DP 3 USB_DP_UP 21
USB_DP_UP
5 GND 4

TUSB4041I_PAP
J1

C2 C3 R5
0.1 µF 0.001 µF 1 MΩ

Copyright © 2016, Texas Instruments Incorporated

Figure 26. Upstream Port Implementation

The upstream of the TUSB4041I device is connected to a USB2 Type B connector. This particular example has
GANGED pin and FULLPWRMGMTZ pin pulled low, which results in individual power support each downstream
port. The VBUS signal from the USB2 Type B connector is feed through a voltage divider. The purpose of the
voltage divider is to make sure the level meets USB_VBUS input requirements

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9.2.2.2 Downstream Port 1 Implementation

BOARD_3P3V

R6 FB1
POPULATE 4.7K DN1_VBUS VBUS_DS1
FOR BC SUPPORT DN1_VBUS
220 @ 100MHZ C4
0.1uF J2
U1B 1
VBUS
34 USB_DM_DN1 2
USB_DM_DN1 DM
33 USB_DP_DN1 3
USB_DP_DN1 DP
4
GND
5
4 SHIELD1
PWRCTL1/BATEN1 PWRCTRL1_BATEN1 6
14 SHIELD2
OVERCUR1Z OVERCUR1Z
USB2_TYPEA
R7 C5 C6
TUSB4041I_PAP 1M 0.001uF 0.1uF

Copyright © 2016, Texas Instruments Incorporated

Figure 27. Downstream Port 1 Implementation

The downstream port 1 of the TUSB4041I device is connected to a USB2 type A connector. With BATEN1 pin
pulled up, battery charge support is enabled for Port 1. If battery charge support is not needed, then uninstall the
pullup resistor on BATEN1.

9.2.2.3 Downstream Port 2 Implementation

BOARD_3P3V

FB2
R8 DN2_VBUS VBUS_DS2
POPULATE DN2_VBUS
4.7 KΩ
FOR BC SUPPORT 220 at 100 MHz C7
0.1 µF
J3
U1C 1
VBUS
42 USB_DM_DN2 2
USB_DM_DN2 DM
41 USB_DP_DN2 3
USB_DP_DN2 DP
4
GND
5
3 SHIELD1
PWRCTL2/BATEN2 PWRCTRL2_BATEN2 6
15 SHIELD2
OVERCUR2Z OVERCUR2Z
R9 C9 USB2_TYPEA
1 MΩ 0.001 µF C8
TUSB4041I_PAP 0.1 µF

Copyright © 2016, Texas Instruments Incorporated

Figure 28. Downstream Port 2 Implementation

The downstream port 2 of the TUSB4041I device is connected to a USB2 type A connector. With BATEN2 pin
pulled up, battery charge support is enabled for port 2. If battery charge support is not needed, then uninstall the
pullup resistor on BATEN2.

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9.2.2.4 Downstream Port 3 Implementation

BOARD_3P3V

FB3
R10 VBUS_DS3
POPULATE DN3_VBUS
4.7 KΩ
FOR BC SUPPORT 220 at 100 MHz C10
0.1 µF
J4
U1D 1
VBUS
50 USB_DM_DN3 2
USB_DM_DN3 DM
49 USB_DP_DN3 3
USB_DP_DN3 DP
4
GND
5
1 SHIELD1
PWRCTL3/BATEN3 PWRCTRL3_BATEN3 6
12 SHIELD2
OVERCUR3Z OVERCUR3Z
R11 C11 USB2_TYPEA
1 MΩ 0.001 µF C12
TUSB4041I_PAP 0.1 µF

Copyright © 2016, Texas Instruments Incorporated

Figure 29. Downstream Port 3 Implementation

The downstream port3 of the TUSB4041I device is connected to a USB2 type A connector. With BATEN3 pin
pulled up, battery charge support is enabled for port 3. If battery charge support is not needed, then uninstall the
pullup resistor on BATEN3.

9.2.2.5 Downstream Port 4 Implementation

BOARD_3P3V

FB4
R12 VBUS_DS4
POPULATE DN4_VBUS
4.7 KΩ
FOR BC SUPPORT 220 at 100 MHZ C13
0.1 µF
J5
U1E 1
VBUS
57 USB_DM_DN4 2
USB_DM_DN4 DM
56 USB_DP_DN4 3
USB_DP_DN4 DP
4
GND
5
64 SHIELD1
PWRCTL4/BATEN4 PWRCTRL4_BATEN4 6
11 SHIELD2
OVERCUR4Z OVERCUR4Z
R13 C15 USB2_TYPEA
1 MΩ 0.001 µF C14
TUSB4041I_PAP 0.1 µF

Copyright © 2016, Texas Instruments Incorporated

Figure 30. Downstream Port 4 Implementation

The downstream port 4 of the TUSB4041I device is connected to a USB2 Type A connector. With BATEN4 pin
pulled up, Battery Charge support is enabled for Port 4. If Battery Charge support is not needed, then uninstall
the pullup resistor on BATEN4.

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9.2.2.6 VBUS Power Switch Implementation

BOARD_3P3V BOARD_3P3V

BOARD_5V
R19 R20
10K 10K
0402 0402
C42 5% 5%
0.1uF
U2
2 9 DN1_VBUS
3 IN OUT1 DN1_VBUS
IN 10
4 FAULT1Z OVERCUR1Z
PWRCTRL1_BATEN1
PWRCTRL1_BATEN1 EN1 8 DN2_VBUS
5 OUT2 DN2_VBUS
PWRCTRL2_BATEN2
PWRCTRL2_BATEN2 EN2 6
1 FAULT2Z OVERCUR2Z
11 GND 7 ILIM1
PAD ILIM C43 C45

TPS2561 0.1uF + C44 0.1uF + C46

R21 150uF 150uF
25.5K
0402
5%

Limiting DS Port VBUS current to 2.2A per port.

BOARD_3P3V BOARD_3P3V

BOARD_5V
R22 R23
10K 10K
0402 0402
C47 5% 5%
0.1uF
U3
2 9 DN3_VBUS
3 IN OUT1 DN3_VBUS
IN 10
4 FAULT1Z OVERCUR3Z
PWRCTRL3_BATEN3 EN1 8 DN4_VBUS
5 OUT2 DN4_VBUS
PWRCTRL4_BATEN4 EN2 6
1 FAULT2Z OVERCUR4Z
11 GND 7 ILIM2
PAD ILIM C48 C50

TPS2561 0.1uF + C49 0.1uF + C51

R24 150uF 150uF
25.5K
0402
5%

Limiting DS Port VBUS current to 2.2A per port.

Copyright © 2016, Texas Instruments Incorporated

Figure 31. VBUS Power Switch Implementation

This particular example uses TI's TPS2561 dual-channel precision adjustable current-limited power switch. For
details on this power switch or other power switches available from TI, refer to www.ti.com.

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9.2.2.7 Clock, Reset, and Miscellaneous

The PWRCTL_POL is left unconnected which results in active-high power enable (PWRCTL1, PWRCTL2,
PWRCTL3, and PWRCTL4) for a USB VBUS power switch. The 1-µF capacitor on the GRSTN pin can only be
used if the VDD11 supply is stable before the VDD33 supply. Depending on the supply ramp of the two supplies,
the user may need to adjust the capacitor.
U1F
5
C29 18 SDA/SMBDAT
1 µF GRSTZ 6
SCL/SMBDAT
7
SMBUSZ
30 13
XI AUTOENZ/HS_SUSPEND
9
R14 1M PWRCTL_POL
17
TEST
Y1 29 32
XO USB_R1
R15
9.53 KΩ R16 R18
TUSB4041I_PAP 0402 4.7 KΩ 4.7 KΩ
1%
24 MHz
C30 C31
18 pF 18 pF

Copyright © 2016, Texas Instruments Incorporated

Figure 32. Clock, Reset, and Miscellaneous

9.2.2.8 TUSB4041I Power Implementation

BOARD_1P1V

VDD11
FB5

C16 C17 C18 C19 C20 C21 C22

C23 220 at 100 MHz
0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 10 µF
19
25
37
45
53
60
63

U1G
23
VDD
VDD
VDD
VDD
VDD
VDD
VDD

24 RSVD
26 RSVD
27 RSVD
35 RSVD
36 RSVD
38 RSVD
39 RSVD
43 RSVD
44 RSVD
46 RSVD
47 RSVD 2
51 RSVD VDD33 20
52 RSVD VDD33 31 VDD33 BOARD_3P3V
54 RSVD VDD33 48
55 RSVD VDD33 FB6
58 RSVD
59 RSVD
RSVD C24 C25 C26 C27
THERMAL_PAD

61 C28 220 at 100 MHz

62 RSVD 0.1 µF 0.1 µF 0.1 µF 0.1 µF 10 µF
RSVD
28
40 NC
NC
65

TUSB4041I_PAP

Copyright © 2016, Texas Instruments Incorporated

Figure 33. TUSB4041I Power Implementation

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9.2.3 Application Curves

Figure 34. High-Speed Upstream Port Figure 35. High-Speed Downstream Port 1

Figure 36. High-Speed Downstream Port 2 Figure 37. High-Speed Downstream Port 3

Figure 38. High-Speed Downstream Port 4

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10 Power Supply Recommendations

10.1 TUSB4041I Power Supply

The user should implement VDD as a single power plane, as well as VDD33.
• The VDD pins of the TUSB4041I supply 1.1-V (nominal) power to the core of the TUSB4041I device. This
power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
• The DC resistance of the ferrite bead on the core power rail can affect the voltage provided to the device
because of the high current draw on the power rail. The user may need to adjust the output of the core
voltage regulator to account for this, or select a ferrite bead with low DC resistance (less than 0.05 Ω).
• The VDD33 pins of the TUSB4041I device supply 3.3-V power rail to the I/O of the TUSB4041I device. This
power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
• All power rails require a 10-µF capacitor or 1-µF capacitors for stability and noise immunity. These bulk
capacitors can be placed anywhere on the power rail. Place the smaller decoupling capacitors as close to the
TUSB4041I power pins as possible with an optimal grouping of two capacitors of differing values per pin.

10.2 Downstream Port Power

• A source capable of supplying 5 V and up to 500 mA per port must supply the downstream port power,
VBUS. The TUSB4041I signals can control the downstream port power switches. Leaving the downstream
port power as always enabled is also possible.
• The VBUS of each downstream port requires a large-bulk low-ESR capacitor of 22 µF or larger to limit in-rush
current.
• TI recommends the ferrite beads on the VBUS pins of the downstream USB port connections for both ESD
and EMI reasons. A 0.1-µF capacitor on the USB connector side of the ferrite provides a low-impedance path
to ground for fast rise time ESD current that might have coupled onto the VBUS trace from the cable.

10.3 Ground
TI recommends to use only one board ground plane in the design which provides the best image plane for signal
traces running above the plane. Connect the thermal pad of the TUSB4041I and any of the voltage regulators to
this plane with vias. An earth or chassis ground is implemented only near the USB port connectors on a different
plane for EMI and ESD purposes.

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11 Layout

11.1 Layout Guidelines

Use the layout guidelines listed in this section for proper PCB layout design.

11.1.1 Placement
• Place a 9.53-kΩ ±1% resistor connected to pin USB_R1 as close as possible to the TUSB4041I device.
• Place a 0.1-µF capacitor as close as possible on each VDD and VDD33 power pin.
• The ESD and EMI protection devices (if used) should also be placed as close as possible to the USB
connector.
• If a crystal is used, it must be placed as close as possible to the XI and XO pins of the TUSB4041I device.
• Place voltage regulators as far away as possible from the TUSB4041I device, the crystal, and the differential
pairs.
• In general, the user should place the large bulk capacitors associated with each power rail as close as
possible to the voltage regulators.

11.1.2 Package Specific

• The TUSB4041I device package has a 0.5-mm pin pitch.
• The TUSB4041I device package has a 4.64-mm × 4.64-mm thermal pad. This thermal pad must be
connected to ground through a system of vias.
• Solder mask all vias under device, except for those connected to the thermal pad, to avoid any potential
issues with thermal pad layouts.

11.1.3 Differential Pairs

This section describes the layout recommendations for all the TUSB4041I device differential pairs: USB_DP_XX,
USB_DM_XX.
• The differential pairs must be designed with a differential impedance of 90 Ω ± 10%.
• To minimize crosstalk, TI recommends to keep high-speed signals away from each other. Each pair should
be separated by at least 5 times the signal trace width. Separating with ground as depicted in the layout
example also helps minimize crosstalk.
• Route all differential pairs on the same layer adjacent to a solid ground plane.
• Do not route differential pairs over any plane split.
• Adding test points causes impedance discontinuity and therefore negatively impacts signal performance. If
test points are used, place them in series and symmetrically. Do not place them in a manner that causes stub
on the differential pair.
• Avoid 90° turns in trace. Keep the use of bends in differential traces to a minimum. When bends are used, the
number of left and right bends should be as equal as possible and the angle of the bend should be ≥135°.
This guideline minimizes any length mismatch caused by the bends and therefore minimize the impact bends
have on EMI.
• Minimize the trace lengths of the differential pair traces. Eight inches is the maximum recommended trace
length for USB 2.0 differential pair signals. Longer trace lengths require very careful routing to assure proper
signal integrity.
• Match the etch lengths of the differential pair traces (that is DP and DM). The USB 2.0 differential pairs
should not exceed 50 mils relative trace length difference.
• Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure
that the same via type and placement are used for both signals in a pair. Place any vias used as close as
possible to the TUSB4041I device.
• To ease routing of the USB 2.0 DP and DM pair, the polarity of these pins can be swapped. If this is done,
set the appropriate Px_usb2pol register, where x = 0, 1, 2, 3, or 4.
• Do not place power fuses across the differential pair traces.

Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 37

Product Folder Links: TUSB4041I
TUSB4041I
SLLSEK3E – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com

11.2 Layout Example

TI USB2 HUB

USB2 DP/DM

USB2 TYPE B
Connector

Figure 39. Example Routing of Upstream Port

USB2 DP/DM

TI USB2 HUB

USB2 TYPE A
Connector

Figure 40. Example Routing of Downstream Port

38 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated

Product Folder Links: TUSB4041I

 TUSB4041I
www.ti.com SLLSEK3E – JULY 2015 – REVISED SEPTEMBER 2017

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation see the following:
• Selection and Specification of Crystals for Texas Instruments USB 2.0 Devices, SLLA122
• TPS2561 Dual-Channel Precision Adjustable Current-limited Power Switches, SLVS930
• TUSB4041PAP Evaluation Module, SLLU227

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates — go to the product folder for your device on ti.com. In the
upper right-hand corner, click the Alert me button to register and receive a weekly digest of product information
that has changed (if any). For change details, check the revision history of any revised document.

12.3 Community Resource

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 39

Product Folder Links: TUSB4041I
TUSB4041I
SLLSEK3E – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com

PACKAGE OUTLINE
PAP0064M SCALE 1.500
PowerPAD TM
- 1.2 mm max height
PLASTIC
PLASTICQUAD
QUADFLATPACK
FLATPACK

PIN 1 ID 10.2
B
9.8
A 64 49

1 48

12.2
TYP
10.2 11.8
9.8

16 33

17
32
0.27
64X
0.17
0.08 C A B 60X 0.5

4X 7.5

SEE DETAIL A 1.2 MAX

C

SEATING PLANE
0.08
0.09-0.20
TYP

0 MIN

(0.15) TYP 0.25

NOTE 4 GAGE PLANE (1)

4.44 0.15
3.64 0 -7 0.75 0.05
0.45

DETAIL A
DETAIL A
SCALE: 12

EXPOSED TYPICAL
(0.15) TYP THERMAL PAD
NOTE 4

4221602/A 07/2014
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026, variation ACD.
4. Strap features may not be present,

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40 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated

Product Folder Links: TUSB4041I

 TUSB4041I
www.ti.com SLLSEK3E – JULY 2015 – REVISED SEPTEMBER 2017

EXAMPLE BOARD LAYOUT

PAP0064M PowerPAD TM - 1.2 mm max height
PLASTIC QUAD FLATPACK

( 8) NOTE 7
( 4.44)
SOLDER MASK
OPENING
SYMM

64 49 SOLDER MASK
DEFINED PAD

64X (1.5)

1
48

64X (0.3)

(0.5)
TYP
SYMM

(11.4)

60X (0.5)
(1)
TYP
16 33

( 0.2) TYP
VIA

17 32 METAL COVERED
BY SOLDER MASK
SEE DETAIL
(0.5) TYP (1) TYP

(11.4)

LAND PATTERN EXAMPLE

SCALE:6X

0.05 MAX
ALL AROUND

METAL

SOLDER MASK
OPENING

NON SOLDER MASK

DEFINED
4221602/A 07/2014

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slm002) and SLMA004 (www.ti.com/lit/slma004).
8. Size of metal pad may vary due to creepage requirement.

www.ti.com
Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 41
Product Folder Links: TUSB4041I
TUSB4041I
SLLSEK3E – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com

EXAMPLE STENCIL DESIGN

PAP0064M PowerPAD TM - 1.2 mm max height
PLASTIC QUAD FLATPACK

( 4.44)
BASED ON
0.127 THICK STENCIL SYMM SEE TABLE FOR
DIFFERENT OPENINGS
64 49 FOR OTHER STENCIL
THICKNESSES

64X (1.5)

1
48

64X (0.3)

SYMM
(11.4)

60X (0.5)

16 33

METAL COVERED
BY SOLDER MASK

17 32

(11.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 5X5
0.127 4.44 X 4.44 (SHOWN)
0.152 4.06 X 4.06
0.178 3.75 X 3.75

4221602/A 07/2014

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.

www.ti.com
42 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated

Product Folder Links: TUSB4041I

 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2017

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TUSB4041IPAP ACTIVE HTQFP PAP 64 160 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 TUSB4041I
& no Sb/Br)
TUSB4041IPAPR ACTIVE HTQFP PAP 64 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 TUSB4041I
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2017

OTHER QUALIFIED VERSIONS OF TUSB4041I :

• Automotive: TUSB4041I-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Aug-2018

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TUSB4041IPAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Aug-2018

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TUSB4041IPAPR HTQFP PAP 64 1000 367.0 367.0 55.0

Pack Materials-Page 2
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