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Lecture 10 Combinational Circuits Decoder Part-II

The document discusses combinational circuits and decoders. It covers the enable input on decoders, which allows the outputs to be turned on or off. A 4-to-16 binary decoder is presented that connects two 3-to-8 decoders using enable lines. Decoder circuits using NAND gates are also shown, including a 2-to-4 decoder with an active-low enable input. The document provides examples of how decoders are used in applications like data multiplexing and memory address decoding.

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Haris Ali
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57 views

Lecture 10 Combinational Circuits Decoder Part-II

The document discusses combinational circuits and decoders. It covers the enable input on decoders, which allows the outputs to be turned on or off. A 4-to-16 binary decoder is presented that connects two 3-to-8 decoders using enable lines. Decoder circuits using NAND gates are also shown, including a 2-to-4 decoder with an active-low enable input. The document provides examples of how decoders are used in applications like data multiplexing and memory address decoding.

Uploaded by

Haris Ali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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MIRPUR UNIVERSITY OF SCIENCE AND TECHNOLOGY (MUST), MIRPUR

DEPARTMENT OF COMPUTER SCIENCE & INFORMATION TECHNOLOGY


INTRO TO COMPUTER ARCHITECTURE
MCS-125

Lecture 15: Combinational Circuits – Decoder (Part-II)

Mr. Abdul Ghafoor


(Lecturer)

Date: April 26, 2020


LECTURE CONTENTS

1. Decoder ENABLE input

2. 4-to-6 Binary Decoder

3. Decoder with NAND

4. References

Subject Name MCS-125 Intro to Computer Architecture 3


DECODER ENABLE INPUT
• Enable input must be ON for the decoder to function, otherwise its outputs
assume a single "disabled" output code word.

• Decoding is necessary in applications such as data multiplexing,


7 segment display and memory address decoding.

• Some binary decoders have an additional input labeled "Enable“ that controls the
outputs from the device. This allows the decoders outputs to be turned "ON“ or
"OFF".

MCS-125 Intro to Computer Architecture 4


DECODER ENABLE INPUT
An alternative way of looking at the decoder circuit is to
– inputs A, B and C as address signals. Each combination of
A, B or C defines a unique address which can access allocation
having that address.

– Enable Line:

If enable = 0, decoder is off. It means all output lines are zero

If enable = 1, decoder is on and depending on input, the corresponding


output line is 1, all other lines are 0.

MCS-125 Intro to Computer Architecture 5


DECODER ENABLE INPUT
• In this table, note that whenever
EN=0, the outputs are always 0,
regardless of inputs S1 and S0.
We can abbreviate the table by
writing x’s in the input columns
for S1 and S0

• Truth table

MCS-125 Intro to Computer Architecture 6


4-TO-16 BINARY DECODER
• Decoders with enable inputs can be connected together to form a larger decoder
circuit.
• We can connect two 3-to-8 Binary Decoders to form 4-to-16 Binary Decoders
using the Enable Line as follows:

MCS-125 Intro to Computer Architecture 7


4-TO-16 BINARY DECODER
• When E=0
- The top decoder is enabled and the other is disabled.
- The bottom decoder outputs all 0’s, and the top eight outputs generate minterm
0000 to 0111.
• When E=1
- The enable conditions are reversed: The bottom decoder outputs generate minterm
1000 to 1111,
- The outputs of the top decoder are all 0s.
• This example demonstrates the usefulness of enable inputs in decoders and other
combinational logic components.
• In general, enable inputs are a convenient feature for interconnecting two or more
standard components for the purpose of combining them into a similar function with
more inputs and outputs.

MCS-125 Intro to Computer Architecture 8


DECODER WITH NAND
• The circuit operates with complemented outputs and a complement enable
input.

• The decoder is enabled when E is equal to 0 (i.e active-low enable). As


indicated by the truth table, only one output can be equal to 0 at any given time;
all other outputs are equal to 1.

• The output whose value is equal to 0 represents the Minterm selected by inputs
A and B.

• The circuit is disabled when E is equal to 1, regardless of the values of the other
two inputs. When the circuit is disabled, none of the outputs are equal to 0 and
none of the Minterms are selected.

MCS-125 Intro to Computer Architecture 9


2-to4 BINARY DECODER WITH NAND
• A 2-to-4 decoder with an enable input constructed with NAND gates:
(a) Truth Table: (b) Combinational Circuit:

MCS-125 Intro to Computer Architecture 10


REFERENCE

1. Introduction to Computer Architecture by M. Morris Mano,


Chapter 2, Digital Components, Section 2.2 Decoders

MCS-125 Intro to Computer Architecture 11


THANKS

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