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Introduction To Verilog Lab-2

The document provides Verilog code examples for: 1) Adding two 4-bit binary numbers and determining overflow 2) Generating the 2's complement of a 4-bit binary number 3) Subtracting two 4-bit binary numbers by calculating the 2's complement of the subtrahend and adding it to the minuend.

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Rohan sharma
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70 views2 pages

Introduction To Verilog Lab-2

The document provides Verilog code examples for: 1) Adding two 4-bit binary numbers and determining overflow 2) Generating the 2's complement of a 4-bit binary number 3) Subtracting two 4-bit binary numbers by calculating the 2's complement of the subtrahend and adding it to the minuend.

Uploaded by

Rohan sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Introduction to Verilog

Lab-2
1. Write a Verilog code to implement A + B. Assume that A and B are 4 Bit
Binary numbers. There are two outputs, SUM of 4 bits and OVERFLOW
of 1 bit. The overflow bit denotes the cases when the sum is greater
than 15.

module addercomp(a,b, sum, overflow);

input [3:0] a;
input [3:0] b;
output [3:0] sum;
output reg overflow;
wire [4:0] tempadd;

assign tempadd = a+b;


always @( tempadd)
begin
if(tempadd[4]==1) overflow =1;
else overflow = 0;
end
assign sum = tempadd[3:0];
endmodule
2. Assume that A is a 4 Bit Binary Number. Write the Verilog code to
generate B, that is 2’s complement representation of -A.

module two_com(
input [3:0] a,
output [3:0] out
);
assign out = ~b + 1;
endmodule
3. Write a Verilog code to implement A – B. Assume that A and B are 4 Bit
Binary numbers given as inputs and A > B. You cannot directly use
subtraction in the code. Compute the substation using 2’s complement
representation.

module two_compadder(
input [3:0] a,
input [3:0] b,
output [3:0] out
);

wire [3:0] complement;


assign complement = ~b + 1;
assign out = a + complement;
endmodule

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