International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) - 2016

CMOS Design of 5-Stage Ring Oscillator as

1
Temperature Sensor 3
Deepak Rasaily 2
Rajesh Mehra Uday Rai
ME Scholar ECE, NITTTR Associate Prof. ECE, NITTTR ME Scholar ECE, NITTTR
Chandigarh, UT, India Chandigarh, UT, India Chandigarh, UT, India
[email protected] [email protected] [email protected]

Abstract: Ring oscillator is versatile devise based on phase shift produced to be 2 and unity voltage gain.
CMOS designed for temperature sensor to replace the The Power consumption will increase as the chip area
conventional temperature sensor for optimized the and the number of stages of the ring oscillator increase.
application specific circuits which are vulnerable in
temperature variations. Sensors like RTD, Thermocouple,
Number of stages be denoted by P, then delay
Therimoristor and IC are often used within electronic generated in each gate is tx hence total delay will
systems to monitor temperature and provide protection be 2Ptx, where tx=tr+tf, tr is rise time and tf is fall time
from excessive temperature excursions which are bulkier, of the pulse produced by each gate [3]. Voltage
costly, complicated interface circuit, and un precise signal controlled Oscillator constructed using invertors is
conditioning. We tried to implement integrated primary building block in proposed temperature sensor
temperature sensor within the Die therein we may however ring counter needs optimization in its various
estimate and control the Temperature with Ring parameters. Paper presented here has following section
oscillator. Proposed Ring Oscillator gives frequency of 1- outlined as below:
3.12 GHz, with tuning range of approximately 81% and
Power consumptions of around 0.054mW. Section I: Proposed Block Diagram.
Section II: 5-stage ring Oscillator.
Index Terms; Ring generators, MOSFETs, CMOS
integrated circuits, Frequency response, .Inverters, Jitter, Section III: Proposed Schematic.
layout, Counting Circuits.
Section VI: Result and Comparison.
INTRODUCTION Section V: Conclusion.
Odd number of NOT gate is used to make Ring Section I: Proposed Block Diagram.
oscillator which oscillates between two vale Fig-1 Shows the proposed block diagram for
representing true and False. Invertor resenting the NOT temperature display after sensing from the die area. It
gate are connected in chain where output of the last uses 5 stage Ring counter (Negative Skew), buffer,
stage is feedback to first stage. Because a single Counter, Register and calibrated unit showing
inverter computes the logical NOT of its input, it can be temperature as count.
shown that the last output of a chain of an odd number
of inverters is the logical NOT of the first input. The
final output is asserted a finite amount of time after the Power Supply
first input is asserted and the feedback of the last output
to the input causes oscillation. [1]
Register Count
Ring Oscillator with even number of inverter stage is Counter Temperature
not functional for this purpose. The last output in this
case is the same as the input. Major issue in Ring
oscillator is Gate delay which is inversely proportional
to output frequency.Varition in input voltage changes Buffer 5-Stage RO
the parameters like peak to peak voltages, time period
and consequently output frequency [2]-[4]. Block
diagram proposedwith ring oscillator is shown in Fig-1. Fig-1
N-stage single ended ring counter has feedback given Proposed ring oscillator generates a clock signal which
to input from odd invertor gate. Ring Oscillator can be is proportional to the change in temperature. A negative
made with number of stages included in odd number. skew five stage ring oscillator and with 4-digit tunable
Principle of working is same as all oscillator inputs makes the ring oscillator frequency-tunable. The
i.e.Barkhausen Criteria. As per Barkhausen Criteria buffer makes sure that the number of its rising edge is
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 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) - 2016

counted by the counter. The register saves the counter

output at every positive edge of the external clock. The
difference between two successive outputs of the
register indicates the temperature [2]-[4].

Parameters of Interest in RO.

1. Frequency of Oscillation for proposed 5 stage ring
oscillator is f0= [7] Where

and Or we
may use general rule to find the frequency of
oscillation as fOSC= where N is number of
inverter stage in the oscillator design and is
delay caused by each inverter [1].

2. Vout=v0{1+a(t)}Sin[2šf0t+݊(t)] (2) where

Fig-2
a(t) and ݊(t) are function of time [8].
3. Power dissipations, Pavg=VDDIavg [7]
4. JITTER: It is the interval between two times of
maximum effect (or minimum effect) of a signal
property that varies regularly with time. It is
defined as- t= - (4) where
f0and

5. Tuning range:Generally Voltage controlled

oscillator are designed to achieve range of
frequency starting from minimum value to some Fig-3
extended value when input voltage is changed. Design proposes negative skew for improving the
This is called tenability of oscillator circuit which
frequency response of circuit [5].Negative delay has
we do in conventional oscillator by varying the
been added in the circuit to compensate the high to low
parameter like R, L, and C etc. In ring oscillator we
have Tuning range as follows [10]: transitions. Further alternative device can be added on
the same circuit to make it tunable however it increases
Tuning Range % = 100%,
power dissipation and phase noise [6]. Output
where , Waveform with frequency versus Vdd is shown in Fig-
are maximum and minimum 4.
frequency respectively [7].

Section-II 5-stage Ring Oscillator

Fig 2 shows 5 stage ring oscillator composed of

network of nMOS and pMOS transistor. As shown,
feedback of 5thstage is given back to 1st stage to obtain
oscillation of desired frequency. Circuit drawn in
180nm technology with VDD of 1.8v in Cadence.Foscis
frequency of oscillation however the mobility of charge
career in nMOS transistor is 2 or 3 times greater than
pMOS transistor hence circuit has limited transient
response.
Fig-4Vdd versus output Frequency.

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 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) - 2016

Section III: Proposed Schematic.

Voltage regulator is not part of proposed circuit in sink
and source node hence charges re-cycling is done by
voltage Vmiddle so that power consumption between top
and bottom circuit in the ring oscillator is balanced. As
we increase the supply voltage the frequency of
oscillation will increase but in parallel it increases the
power consumption in the circuit. Also increase in
temperature increases power consumption which
needs to balance by equalizing with bottom circuit by
adjustment of voltage Vmiddle .De coupling capacitor is Fig-7
connected between intermediate node and ground for
appropriate value voltage Vmiddle so that balancing in Output of the counter block is pass to register where it
the top and bottom circuit is maintained. It also is saved to produce result at every rising edge of the
stabilizes to correct value to achieve the objective. input clock pulse given [9]. The current output of
register is subtracted from previous and after adding
The counter block is designed free running without several value to it finale output representing the current
reset signal hence every previous block contains temperature in circuit is displayed which is target
current quantization noise which gives first order temperature. Count temperature block in Fig-1 can be
noise[10]. directly calibrated to show target temperature where 10-
bit output of register is feed in it.

Section IV: Result and Comparisons

After 5-satge ring oscillator is designed as proposed in

Fig-2 and Simulation is done we observed following
parameters:

SLNO Parameter of Interest Practical Values

Fig-5 1bit Counter. 1 CMOS Technology 180nm

Fig-5 shows 1-bit D flip-flop with output Q given to 2 Vdd 3.3V

register. Input to the counter will be from Buffer unit.
Buffer circuit is used to raise the power level of 3 No of inverter stages 5

oscillator output. Circuit designed to enhance the low 4 Frequency 1 to 3.12 GHz
voltage level to full scale so that counter could detect
the rising edge of the every cycle produced in ring 5 Jitter <24ps
oscillator.Fig-6 shows small buffer circuit which
6 Power consumption 0.054mW
operates at higher switching rate and drives the counter
at its edge. 7 Tuning range 81%

8 Vout (Peak to peak) 0.0482-3.010 v

Table-1
Properties of nMOS and pMOS.
SLNO Parameter Practical Values

1 Total Width 2μm

2 Finger Width 2μm

3 Threshold 800nM

4 S/D Metal Width 400nM

Fig-6: Buffer Circuit

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on-chip interconnect using current mode signaling

5 Drain Diffusion Area 1.2p scheme,Information Communication and Embedded
Systems (ICICES), 2013 International Conference,pp.803-
6 Source Diffusion Area 1.2p 808,Feb 2013.
[ 2] Sung-Sik Woo, Jung-Hyup Lee, and SeongHwan Cho ʊA
7 Area ratio 20% Ring Oscillator-based Temperature Sensor for U-Healthcare
in 0.13 CMOS, IEEE International SOC Design
conference (ISOCC) 978-1-4244-50350/2009.
Table-2
[ 3] W.Y. Chung, Y.D. Lee, S.J. Jung, ʊA Wireless Sensor
Table-1 shows all the required parameter for the 5-stage Network Compatible Wearable U-healthcare Monitoring
System Using Integrated ECG, Accelerometer and SpO2,
ring oscillator performed and evaluated in Cadence Engineering in Medicine and Biology Society, pp. 1529-
simulation envioronment.Technology used is 180nm 1532, 2008.
[10] where five nMOS and five pMOS is taken to make [ 4] J.A. Paradiso, T. Starner, ʊEnergy scavenging for mobile
5 stage ring oscillator. Frequency of oscillation and wireless electronics, IEEE Pervasive Computing, vol. 4,
pp.18-27, 2005.
observed is less than 1GHz in the voltage range from 0-
[ 5] ShrutiSuman, Prof. B.P. Singh ,Ring Oscillator Based
3.3V.power consumption is better i.e 0.054mW and CMOS Temperature Sensor Design,IJSTR,Vol.1,Issue
Jitter is observed to be within the permissible limit. 4,May 2012
Tuning range is excellent i.e.81%.Jitter has been [ 6] E. Socher, S. M. Beer, and Y. Nemirovsky, ʊTemperature
suppressed to optimum value at 24ps.Table-2 shows the sensitivity of SOI-CMOS transistors for use in uncooled
thermal sensing, IEEE Trans. Electron Devices, vol. 52, no.
properties of CMOS devices i.e. nMOS and pMOS with 12, pp. 2784–2790, Dec. 2005.
their optimum values. [ 7] V. Leonov, T. Torfs, P. Fiorini, C. Van Hoof,
ʊThermoelectric Converters of Human Warmth for Self-
Powered Wireless Sensor Nodes,IEEE Sensors Journal, vol.
Parameter [ 11 ] [12] Proposed 7, pp. 650-657, 2007.
[ 8] MK Mandal& BC Sarkar-Ring Oscillator: Characteristics
and Application, IJPAP, Vol.48, pp.136-145, February
LC/Ring LC Ring Ring 2010.
[ 9] A.Sharma,R.Mehra-Area and Power efficient CMOS adder
Technology 65nm 50nm 0.18um design by Hybridizing PTL and GDI
Technique,IJCA,66(4),pp.15-22.
No. of stages - 5 5 [ 10] R.Verma, R.Mehra-4 input Decimal Adder using 90nm
CMOS Technology, IOSR Journal of Engineering 3 (5), 48-
51.
Frequency 4.65- [ 11] MostafaSavediOskooei, AliAfzali-Kusha, S.M Atarodi. “A
0.7-2.56G 1 to 3.12 GHz
range(Hz) 5.89G High-Speed and Low-Power Voltage Controlled Oscillator
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Operating voltage 1.3V 1V 1.8V [ 12] Nidhi Thakur- Design of Low power, Low Jitter Ring
Oscillator Using 50 nm CMOS Technology, International
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Power Issue 3, March -2012
4.8mW 0.064mW 0.054mW
consumption

Tuning range - 72% 81%

Authors:
[1]
Jitter - 39.8pS <24ps

Table-3
Section V: Conclusion
Table-3 presents the comparison of three different ring Deepak Rasailyis presently associated
oscillator with different parameter values and proposed with the Department of Electronics and Communication
ring oscillator with appropriate values suitable for many Engineering at Centre for Computer and
applications. Parameters estimated here provide better Communication Technology (CCCT-Govt.Polytechnic)
solution for the measurement and control of Chisopani, South Sikkim, India as a Senior Lecturer
temperature with optimum devices and its property since 2003 to till date. He is ME-Scholar atNational
chosen for the implementation as temperature sensor. Institute of Technical Teachers’ Training & Research,
Area ratio is very less; power consumption is within Chandigarh, India. He Worked as Project Scientist in
permissible limit and can be easily implemented at low the Department of Science and Technology, Govt.of
cost. Sikkim prior to Lecturer in CCCT. His areas of interest
References are PLC and Robotics, Microprocessors and
Microcontroller and Digital Signal Processing.
[ 1] Prabhakaran.J,Ravi.V, A low power and high performance [2]

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 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) - 2016

Dr. Rajesh Mehra: Dr. Mehra is

currently associated with Electronics and
Communication Engineering Department of National
Institute of Technical Teachers’ Training & Research,
Chandigarh, India since 1996. He has received his
Doctor of Philosophy in Engineering and Technology
from Panjab University, Chandigarh, India in 2015.
Dr. Mehra received his Master of Engineering from
PunjabUniversity, Chandigarh, India in 2008 and
Bachelor of Technology from NIT, Jalandhar, India in
1994. Dr. Mehra has 20 years of academic and
industry experience. He has more than 250 papers in
his credit which are published in refereed International
Journals and Conferences. Dr. Mehra has 55 ME
thesis in his credit. He has also authored one book on
PLC & SCADA. His research areas are Advanced
Digital Signal Processing, VLSI Design, FPGA
System Design, Embedded System Design, and
Wireless & Mobile Communication. Dr. Mehra is
member of IEEE and ISTE.

[3]

Mr. Uday Kumar Rai: Mr. Uday is

currently working as Senior Lecturer in Electronics &
communication Engineering Department at Sikkim
Polytechnic (Center for Computer and Communication
Technology), Chisopani in Sikkim, India since 2003.
He is pursuing his ME from ECE Department NITTTR,
Chandigarh. He has received his Bachelor of
Engineering from NIT Bhopal, Madhya Pradesh in the
year 1993. Mr. Uday has 19 years of academic and
industry experience.

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