International Journal of Engineering Research & Technology (IJERT)

ISSN: 2278-0181
Vol. 3 Issue 2, February - 2014

VHDL Implementation of Reversible Full Adder

using PERES Gate

Md. Riyaj 1, Anshul Gangwar2, Gagan Goyal3

M-tech ScholarSuresh Gyan Vihar University, Jaipur,India 1,
M-tech ScholarSuresh Gyan Vihar University, Jaipur,India 2,
M-tech Scholar Jaipur National University, Jaipur,India3

Abstract— In low power vlsi design and power optimization and T is the absolute temperature at which the operation is
reversible logic method is being used more frequently. It is also performed.
the fundamental need for the emerging field of the quantum To reduce the power dissipation and to prevent the loss of
computing ,Digital signal processing and communications. The information reversible logic is used it has application[3] in
use of reversible logic in vlsi design has many advantages because different field like as in field of low power computing
it reduces number of gates and garbage outputs. When we use a
quantum computing optical computing and other encoding
logically irreversible gate we dissipate energy into the
environment. The loss of energy equals to the information loss.
computing technologies.
One bit information lost dissipates KT ln2 of energy. By In a reversible circuit the input vector can be reconstructed
reversible logic we can reduce power dissipation. In reversible from the output vector. Not only outputs can be calculated
logic number of input equals to the number of outputs. i.e k*k. from the input but also the inputs can be reconstructed the
All the outputs are not used as input to other gate is called number of input and output are equal. It finds application in
garbage output. This paper presents quantum implementation low power CMOS design, optical computing , DNA
and combinational circuit of all basic reversible gates and its computing quantum computing, nano technology,
RT
VHDL code. All reversible logic gates are verified bioinformatics and thermodynamic technology . in quantum
andsimulatedbyXilinx8.2i.
circuits reversible logic gates are used. Fanout and feedback is
not permitted in reversible logic gates.
IJE

Keywords— Reversible logic,NOT gate,FEYNMAN gate, NOT gate is the simplest 1*1 reversible gate . An example of a
PERES gate ,VHDL CODE,TR gate 2*2 reversible gate is controlled gate(CNOT).Examples for
3*3 reversible gates are F,TG,PG and TR gate.
I. INTRODUCTION The performance of the reversible gate is calculated by
To increase the speed the clock frequency must be increased. calculating the quantum cost by counting the number of V, V+
In VLSI systems increase in number of transistors makes the and CNOT gates. Some properties of V and V+ quantum gates
system complex which[1] further increase the power are given below:
consumed by the system. Moreover any Boolean function can V*V=NOT
be implemented by using logic of reversible logic gates as it V* V+ =V+ * V= -1
has already been proved. V+ * V = NOT
When an input is applied to the reversible gate, a logical
II. BASIC REVERSIBLE GATE
operation is performed and also there is los+s of some
information which is dissipated as heat.So we can conclude A. NOT Gate
that power dissipiation is the main concern for both producers The reversible 1*1 gate[4] is NOT gate with zero quantum
and consumers. A reversible logic gate gives a unique output cost is as shown below.
pattern for for each input pattern. It has k-inputs and k-
outputs, hence denoted by k*k. In reversible logic gates we
have one more aspect to focus on than that of number of gates
,is the number of garbage outputs. Garbage

outputs are those outputs from a reversible ciruit that are not
used as an output.
In low power VLSI design another problem is the solution of Fig 1 Quantum implementation of NOT gate
Landaver’s principle. It states that logical [2]computation of

irreversible gates generate KT*log2 Joules of heat energy on

loss of every bit of information. K is the Bpltzman constant

IJERTV3IS20334 www.ijert.org 622

 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 3 Issue 2, February - 2014

architecture ckt of feynman is

begin
X <= P;
Y <=P xor Q;
end ckt;
C. PERES GATE
The reversible 3*3 gate with quantum cost of four having
Fig 2 1*1 NOT GATE
mapping input (P,Q,R) to output(X,Y,Z) is as shown in figure.

Fig 7 Quantum implementation of PERES gate

Fig 3 Combinational circuit of NOT gate
VHDL CODE
library ieee;
use ieee std_logic.1164.all;
entity not is
port(A : in std_logic;
m :out std_logic);
end not;
RT

B. FEYNMAN/CNOT GATE
The reversible 2*2 gate with quantum cost of one having
mapping [5]input (P,Q) to output(X,Y) is as shown in figure.
IJE

Fig 8 3*3 PERES gate

Fig 4 Quantum implementation of FEYNMAN gate

Fig 5 2*2 FEYNMAN gate

Fig 9 Combinational circuit of PERES GATE

VHDL CODE
library ieee;
Fig 6 Combinational circuit of FEYNMAN gate use ieee std_logic.1164.all;
VHDL CODE entity peres is
library ieee; port(P,Q,R : in std_logic;
use ieee std_logic.1164.all; X,Y,Z :out std_logic);
entity feynman is end peres;
port(P,Q : in std_logic; architecture prs of peres is
X,Y :out std_logic); signal S1: std_logic
end feynman;

IJERTV3IS20334 www.ijert.org 623

 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 3 Issue 2, February - 2014

begin III. PURPOSED PERES FULL ADDER

X <= P;
S1 <= P and Q;
Y <= P xor Q;
Z <= S1 xor R;
end prs;
2.4 TR GATE

Fig 13 PERES full adder

Fig 10 Quantum implementation of TR gate Fig 14 Combinational crcuit of PERES full adder .

VHDL CODE
Library ieee;
USE ieee std_logic_1164 all;
USE ieee numeric_std. all;
Entity FA is
Port (P: in std_logic;
Fig 11 3*3 TR gate Q: in std_logic;
RT
Cin: in std_logic;
Zero: in std_logic;
X: out std_logic;
IJE

Y: out std_logic;
S: out std_logic;
Cout: out std_logic;
End FA ;
Architecture behavioral of FA is
Signal T1 :std_logic;
Fig 12 Combinational circuit of TR gate Signal T2 :std_logic;
VHDL CODE Begin
library ieee; T1 <= P xor Q
use ieee std_logic.1164.all; T2 <= (P xor Q) xor zero;
entity trgate is X <= P;
aport(P,Q,R : in std_logic; Y <= T1;
X,Y,Z :out std_logic); S <= T1 xor Cin;
end trgate; Cout <= (T1 and Cin) xor T2;
architecture tr of trgate is End FA
signal Bbar,S1: std_logic;
begin IV. RESULT
X <= P; The purposed PERES full adder as shown in figre 13&14 are
S1 <= P and Qbar; implemented and resulted by using VHDL and simulated in
Y <= P xor Q; Xilinx 8.2 i. The RTL schematic diagram and simulated
Z <= S1 xor R; results shown in figre 15 and figure 16 respectively.
end tr;

IJERTV3IS20334 www.ijert.org 624

 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 3 Issue 2, February - 2014

Fig 15(A) RTL schematic diagram for PERES full adder

Fig 16(A) Test Bench Waveform & simulation with results

RT
IJE

Fig 15(B) RTL schematic diagram for PERES full adder

Fig 16(B) Test Bench Waveform & simulation with results

V. CONCLUSION
Reversible gate are used to implement arithmatic circuit using
full adder. The main focus of this paper is the proposal of new
reversible 4*4 PERES gate. The purposed PERES gate is used
to design full adder. It is proved that the purposed PERES full
adder is better than the existing counterparts in literature in
terms of garbage outputs. By using purposed PERES full
adder we can design large reversible systems. Here we can

IJERTV3IS20334 www.ijert.org 625

 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 3 Issue 2, February - 2014

calculate the power consumption and compare it with the REFERENCES

irreversible full adder. 1. T. Nagababu ― A low power adder using reversible logic gates ― IJERT
Volume 1 issue 3 Nov 2012
ACKNOWLEDGEMENT 2. Homework report ―reversible adder implementation in VHDL
3. Mr Devendra goyal ―VHDL implementation of reversible logic gates.
I wish to express my thanks to Mr. Rashid Hussain H.O.D 4. Rangaraju H.G. ―LOW POWER REVERSIBLE PARALLEL BINARY
electronics and communication Suresh Gyan Vihar university ADDER
jaipur and my colleague. 5. V. Kanalakannan ―Design of adder /subtractor circuits based on based
on reversible logic gate IJAREEIE vol 2 issue8 august 2013
6. Prashanth N.G. ―design and synthesis of fault tolerent full
adder/subtractor using reversible logic gates‖ IJERA vol 3 issue 4 july –
aug 2013.
7. A. Kamraj ―design of 8-bit arithmatic processor unit based on reversible
logic‖ Global journals volume 13 issue 10 2013
8. Lakshmi viswanath ―Design and analysis of 16 bit reversible ALU‖
IOSRJCE volume 1 Issue 1 june 2012
9. Md. Sajjad hussain ―design of control unit for low power ALU with a
barrel shifter using reversible logic‖ IJEBEA @2013
10. Ravish Aradhya ―design of control unit for low power ALU with a
barrel shifter using reversible logic‖ IJSER volume 2 issue 9 september
2011.

RT
IJE

IJERTV3IS20334 www.ijert.org 626