Integrated Electronics

8th Semester session (16-20)

By: Hassan Jafri

 Course Outline

 Planned 48 one hour lectures

 25 topics covered

Ser CLO Domain Taxonomy level PLO

Design and analyze differential

1 Cognitive 3 3
amplifiers
To understand, identify and define
2 CMOS technology, fabrication and Cognitive 3 1
design

3 Design pulse and switching circuits, Cognitive 3 3

Design and analyze operational

4 Cognitive 3 3
amplifiers

Build and implement small operational

5 Psycho motor 2 3
amplifier based circuits
 List of Topics

1 Introduction to pulse, transistor switches and amplifiers

2 Introduction to PMOS and NMOS
3 Introduction to Differential amplifier
4 Introduction to Operational amplifier 17 Output stage design
5 DC analysis of Differential Amplifier 18 Working of operational amplifier
6 AC analysis of Differential Amplifier 19 DC analysis of Operational Amplifier
7 Design of Differential Amplifier 20 AC analysis of Operational Amplifier
8 Introduction to CMOS, BiCMOS 21 Discussions
9 Fabrication of MOS transistors 22 Application of Op-amps
10 Movie: cleanroom fabrication 23 Schmitt trigger
11 Discussions 24 Analogue circuit interface
12 CMOS logic 25 Digital circuit interface
13 DTL, TTL, ECL, 12L
14 Pulse and Switching circuit
15 Multivibrator circuits
16 Current sources
 Teaching methodology

 Learn by doing it
 You all have to work very hard
 It does not matter whether you sleep 6 hours or less or
have no time for meal
 Least learning in the lectures by instructor (proven by
100000’s of scientific studies)
 Best methods
 Peer tutorage
 Group study
 Project work
 We will employ all these methods of teaching
 Hardware Projects

Week Due
Projects
date Description
1 Design and build Comparator circuit Switch its output at certain input
2 Design inverting amplifier With transistors and with Op-amp IC
3 Design Non-Inverting amplifier With transistors and with Op-amp IC
4 ADC- Analogue to Digital converter With operational amplifier (no ADC IC)
5 DAC- Digital to analogue converter With operational amplifier (no ADC IC)
6 Dual Voltage regulator Any design with discrete components
Switched Capacitor Voltage
7 converters Any design with discrete components
Single frequency function generator (sine and
8 Design of simple function generator square wave)
9 Phase lock loop With an application
10 Frequency synthesizer With an application
 Projects

 Need to be submitted with a technical manual

 Describe in detail (What, Why, How)
 Use Cu board
 No projects are accepted on breadboard or Vero board
 Engrave your roll number on each project
 Soldiering should be professional
 Also design a circuit to demonstrate the capability of your
project
 (think how can you showcase it)
 Assignments

 Will be distributed during lectures

 No copy paste (in case of copy paste there will be
very serious consequences)
 Due date is final (final means it’s a deadline which has
to be met at any cost)
Introduction to
a) Pulse
b)Transistor switches and
amplifiers
c) NMOS and PMOS FET

Topic 1 and 2
 Basics

 There are two worlds

 Analogue
 Digital

 These two worlds can not understand each other

unless there is ADC or DAC is interfacing them

Integrated Electronics by: Engr. Dr. Hassan Jafri

 Basic -II

 Most natural quantities 

analog and vary continuously.
 Analog systems  handle
higher power

 Digital systems  process,

store, and transmit data more
efficiently
 but can only assign discrete
values to each point

Integrated Electronics by: Engr. Dr. Hassan Jafri

 Binary Digits

 Binary system (either 0 or 1)

 Bit (comes from binary digit)
 Digital circuits:
 1 represents HIGH voltage
 0 represents LOW voltage
 Groups of bits (combinations of 0s and 1s) are called
codes
 Being used to represent numbers, letters, symbols, (i.e.
ASCII code), instructions, and etc.

Integrated Electronics by: Engr. Dr. Hassan Jafri

 Logic Levels

 The voltages used to represent

a 1 and 0 are called logic levels.
 Ideally, there is only HIGH (1) and VH(max)
LOW (0). HIGH
(binary 1)
 Practically, there must be VH(min)
thresholds to determine which Not allowed
one is HIGH or LOW or neither of
them. VL(max)
LOW
 CMOS (binary 0)
VL(min)
 (2V to 3.3V  HIGH)
 (0V. To 0.8V  LOW)
Integrated Electronics by: Engr. Dr. Hassan Jafri
 Digital Waveforms
 Voltage levels that are changing back and forth between
HIGH and LOW
 (Ideal) pulse

HIGH HIGH

LOW LOW
t0 t1 t0 t1
Positive-going pulse Negative-going pulse

 At t0  leading edge, at t1  trailing edge

Integrated Electronics by: Engr. Dr. Hassan Jafri
 Non-Ideal Pulse
Overshoot
Ringing Droop

90%

tw
Amplitude 50%
Pulse width

10%

tr tf Undershoot
Rise time Fall time
Integrated Electronics by: Engr. Dr. Hassan Jafri
 Waveform Characteristics
 Waveforms = series of pulses (called pulse train)
 Periodic

T1 T2 T3
 Period (T) = T1 = T2 = T3 = … = Tn
 Frequency (f) = 1/T
 Nonperiodic

Integrated Electronics by: Engr. Dr. Hassan Jafri

 Waveform & Binary Information
Bit
time
1
clock
0

1
A
0
Bit 1 0 1 0 0 1 1 0 0 1 0 1
sequence
represente
d by
waveform
A

Integrated Electronics by: Engr. Dr. Hassan Jafri

 Data Transfer

 Binary data are transferred in two ways:

 Serial – bits are sent one bit at a time
 Parallel – all the bits in a group are sent out on separate
lines at the same time (one line for each bit)
 Serial over Parallel
 Advantage: less transmission line
 Disadvantage: takes more time

Integrated Electronics by: Engr. Dr. Hassan Jafri

 Assignment (daily)

Please
Revise and submit AC and DC
analysis of a BJT transistor
 Resource (internet)

Integrated Electronics by: Engr. Dr. Hassan Jafri

 Introduction to Transistors

 Three terminal devices

 Current flows from one terminal to other while third
terminal controls it

 Transistor is used as switch (for digital world)

 Transistor is used as an amplifier (for Analogue world)

Integrated Electronics by: Engr. Dr. Hassan Jafri

 Types of Transistors
 Bipolar Junction Transistor (BJT)

 Field Effect Transistors (FET)

 Power Transistors
 Power electronics (not in the scope of this course)

Integrated Electronics by: Engr. Dr. Hassan Jafri

 BJT Introduction

 Bipolar Junction Transistors (BJT)

 three “sandwiched” semiconductor layers
 The three layers are connected to collector
(C), emitter (E), and base (B) pins
 Current supplied to the base controls the
amount of current that flows through the
collector and emitter

Integrated Electronics by: Engr. Dr. Hassan Jafri

 BJT Characteristic Curves
Output Characteristic
 collector current (IC) is nearly independent of the collector-emitter
voltage (VCE), and instead depends on the base current (IB)

IB4

IB3

IB2

IB1

Integrated Electronics by: Engr. Dr. Hassan Jafri

 BJT Applications
BJT Switch
 Offer lower cost and substantial reliability over conventional mechanical
relays.
 Transistor operates purely in a saturated or cutoff state (on/off)
 This can prove very useful for digital applications (small current controls
a larger current)

Integrated Electronics by: Engr. Dr. Hassan Jafri

 BJT Applications
BJT Amplifier

Integrated Electronics by: Engr. Dr. Hassan Jafri

 FET Basics

 Electric Field

 Voltage Controlled

 FET includes three distinct pieces

 Drain
 Source
 Gate

Integrated Electronics by: Engr. Dr. Hassan Jafri

 FET versus BJT?

Same: Difference:
 Applications: amplifier, • Voltage vs Current Input
switch, etc. • Unipolar vs Bipolar
 Relies on PNP or NPN • Noise
junctions to allow current
flow • Higher input impedance
• Fragile and low gain bandwidth
 Types of Field-Effect
Transistors

Type Function
Junction Field-Effect Transistor Uses reversed biased p-n junction to separate gate
(JFET) from body
Metal-Oxide-Semiconductor FET
(MOSFET) Uses insulator (usu. SiO2) between gate and body
Insulated Gate Bipolar Transistor
(IGBT) Similar to MOSFET, but different main channel
Organic Field-Effect Transistor
(OFET) Uses organic semiconductor in its channel
Nanoparticle Organic Memory FET Combines the organic transistor and gold
(NOMFET) nanoparticles

Integrated Electronics by: Engr. Dr. Hassan Jafri

 JFET

 Reverse Biased PN-junction

 Depletion mode devices
 Creates a potential gradient
to restrict current flow.
(Increases overall
resistance)

http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/jfet.html

Integrated Electronics by: Engr. Dr. Hassan Jafri

 JFET

 N-channel JFET

 P-channel JFET uses same principles but

 Channel current is positive due to holes instead of electron
donors
 Polarity of biasing voltage must be reversed Integrated Electronics by: Engr. Dr. Hassan Jafri
 MOSFET
Similar to JFET p-channel

 A single channel of single

doped SC material with
terminals at end n-channel

 Gate surrounds channel with MOSFET MOSFET

doping that is opposite of the enhanced mode depleted mode

channel, making the PNP or

NPN type
 BUT, the MOSFET uses an
insulator to separate gate
from body, while JFET uses a
reverse-bias p-n junction
How does a MOSFET work?

No Voltage to Gate Voltage to Gate

Source Drain Source Drain

n n

Simplified Notation

No current flow “Short” allows current flow

Integrated Electronics by: Engr. Dr. Hassan Jafri

 nMOS Transistor

 Four terminals: gate, source, drain, body

 Gate – oxide – body stack looks like a capacitor
 Gate and body are conductors
 SiO2 (oxide) is a very good insulator
 Called metal – oxide – semiconductor (MOS) capacitor
 Even though gate is
no longer made of metal Source Gate Drain
Polysilicon
SiO2

n+ n+

p bulk Si
 nMOS Operation

 Body is commonly tied to ground (0 V)

 When the gate is at a low voltage:
 P-type body is at low voltage
 Source-body and drain-body diodes are OFF
 No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si
 nMOS Operation Cont.

 When the gate is at a high voltage:

 Positive charge on gate of MOS capacitor
 Negative charge attracted to body
 Inverts a channel under gate to n-type
 Now current can flow through n-type silicon from source
through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si
 pMOS Transistor
 Similar, but doping and voltages reversed
 Body tied to high voltage (VDD)
 Gate low: transistor ON
 Gate high: transistor OFF
 Bubble indicates inverted behavior

Source Gate Drain

Polysilicon
SiO2

p+ p+

n bulk Si
 Power Supply Voltage
 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
 High VDD would damage modern tiny transistors
 Lower VDD saves power

 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

Integrated Electronics by: Engr. Dr. Hassan Jafri

 MOSFET as Switches

 We can view MOS transistors as electrically

controlled switches
 Voltage at gate controls path from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
Integrated Electronics by: Engr. Dr. Hassan Jafri
 Thanks

 Be prepared for work

Integrated Electronics by: Engr. Dr. Hassan Jafri