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Hardware Cache Computer Data Main Memory Processor Core Memory Locations Instruction Data Caches

A CPU cache is a hardware cache located close to the CPU that stores frequently used data from main memory to reduce access time. Modern CPUs have multiple cache levels, including L1, L2, and sometimes L3 caches. The L1 cache is split into separate instruction and data caches. Higher cache levels like L2 and L3 are larger and shared across CPU cores. Caches improve performance by providing faster access to commonly used instructions and data.

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32 views1 page

Hardware Cache Computer Data Main Memory Processor Core Memory Locations Instruction Data Caches

A CPU cache is a hardware cache located close to the CPU that stores frequently used data from main memory to reduce access time. Modern CPUs have multiple cache levels, including L1, L2, and sometimes L3 caches. The L1 cache is split into separate instruction and data caches. Higher cache levels like L2 and L3 are larger and shared across CPU cores. Caches improve performance by providing faster access to commonly used instructions and data.

Uploaded by

Danu Oprea
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as RTF, PDF, TXT or read online on Scribd
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A CPU cache[70] is a hardware cache used by the central processing unit (CPU) of a computer to

reduce the average cost (time or energy) to access data from the main memory. A cache is a
smaller, faster memory, closer to a processor core, which stores copies of the data from frequently
used main memory locations. Most CPUs have different independent caches,
including instruction and data caches, where the data cache is usually organized as a hierarchy of
more cache levels (L1, L2, L3, L4, etc.).

All modern (fast) CPUs (with few specialized exceptions[71]) have multiple levels of CPU caches. The
first CPUs that used a cache had only one level of cache; unlike later level 1 caches, it was not split
into L1d (for data) and L1i (for instructions). Almost all current CPUs with caches have a split L1
cache. They also have L2 caches and, for larger processors, L3 caches as well. The L2 cache is
usually not split and acts as a common repository for the already split L1 cache. Every core of
a multi-core processor has a dedicated L2 cache and is usually not shared between the cores. The
L3 cache, and higher-level caches, are shared between the cores and are not split. An L4 cache is
currently uncommon, and is generally on dynamic random-access memory (DRAM), rather than
on static random-access memory (SRAM), on a separate die or chip. That was also the case
historically with L1, while bigger chips have allowed integration of it and generally all cache levels,
with the possible exception of the last level. Each extra level of cache tends to be bigger and be
optimized differently.

Other types of caches exist (that are not counted towards the "cache size" of the most important
caches mentioned above), such as the translation lookaside buffer (TLB) that is part of the memory
management unit (MMU) that most CPUs have.

Caches are generally sized in powers of two: 4, 8, 16 etc. KiB or MiB (for larger non-L1) sizes,
although the IBM z13 has a 96 KiB L1 instruction cache.[72]

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