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D
RTL8211F(D)(I) UTP <=> RGMII D

QFN-40 Pin Reference Schematic

Page Index
P1. Title Page
C
P2. Ethernet PHY C

B B

REVISION HISTORY
RTL8211F(D)(I) UTP <=> RGMII QFN-40 Pin Reference Schematic V1.0

RTL8211F(D)(I) UTP <=> RGMII QFN-40 Pin Reference Schematic V1.01

* Change the value of C5/C6 for RTL8211FDI/FI application.

RTL8211F(D)(I) UTP <=> RGMII QFN-40 Pin Reference Schematic V1.02

* Fix the name of the path.
A Realtek Semiconductor Corp. A
No.2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Title
RTL8211F(D)(I) UTP <=> RGMII QFN-40 Pin Reference Schematic: Index

Size Document Number Rev

A RTL8211F(D)(I) UTP <=> RGMII QFN-40 Pin Reference Schematic 1.02

Date: Thursday, December 24, 2015 Sheet 1 of 2

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RJ45 & Transformer RSET Crystal Case LEDs Configuration

CON1 U2 R30 0 (NC)
R7 2.49K 1% XTAL_OUT
Reserved for EMI DVDD33
2 11 DA+ 13 12 MDI0+ RSET
1 FGND2 DA+ 12 DA- 14 MX4- TD4- 11 MDI0- Y1 R31 0 D1 R32 510
FGND1 DA- 13 DB+ 15 MX4+ TD4+ 10 XTAL_IN LED0/CFG_EXT
4 DB+ 14 DC+ 16 MCT4 TCT4 9 MDI1+
3 GH1 DC+ 15 DC- 17 MX3- TD3- 8 MDI1- C14 25MHz C15 C16 R33 510 (NC)

CHASSISGND
LED0
GH2 DC- 16 DB- 18 MX3+ TD3+ 7
DB- 17 DD+ 19 MCT3 TCT3 6 MDI2+ 27pF 27pF 100pF (NC)
DD+ 18 20 MX2- TD2- 5 MDI2-

D
DD- 21
22
MX2+
MCT2
MX1-
TD2+
TCT2
TD1-
4
3 MDI3+
PLL Clock Out D
RJ45S1X1 DD- 23 2 MDI3-
24 MX1+ TD1+ 1 R34 0
MCT1 TCT1
Reserved for EMI Reserved for EMI DVDD33
GST_5009 U3 External clock Case LED1/CFG_LDO0
R35 0 (NC) D2 R36 510 (NC)

75
75
75
75
C19 R46 0 (NC) 2
C20 0.1uF C21 0.1uF CLKOUT 1 GND2 3
0.01uF CLKGND3 4 C17 R37 510 LED1
C26 GND4 5
GND5 EXT_CLK_25M R8 0 (NC) XTAL_OUT 100pF (NC)

R42
R43
R44
R45
22pF (NC) SMA
C22 0.1uF C23 0.1uF
The transformer center tap (optional)
C24 must be short together XTAL_IN R38 0
CHASSISGND

CHASSISGND

C25 PLL Free run clock output. Reserved for EMI DVDD33
1000pF/2KV
R39 0 (NC) D3 R40 510 (NC)
GND

GND

1000pF/2KV LED2/CFG_LDO1
SMA Connector is reserved for measurement.
CHASSISGND The XTAL_IN needs to be connected to GND C18
(optional) R41 510 LED2
CAP close to PHY. Reserved for EMI. (optional) if the external 25MHz clock used. 100pF (NC)

PHY RESET/INTB Enable/Disable PLL @ ALDPS LED Resistances Setting

CFG_EXT=1'b1 R30(NC), R31, R32, R33(NC)

LED2/CFG_LDO1
LED1/CFG_LDO0
CFG_EXT=1'b0 R30, R31(NC), R32(NC), R33

XTAL_OUT

LED0/CFG_EXT
DVDD33 DVDDRG

XTAL_IN
CLKOUT
AVDD33

AVDD10
CFG_LDO0=1'b1 R34(NC), R35, R36, R37(NC)

RSET

INTB
R9 4.7K
INTB R28 4.7K RXD2/PLLOFF R29 4.7K (NC) CFG_LDO0=1'b0 R34, R35(NC), R36(NC), R37
C R10 4.7K CFG_LDO1=1'b1 R38(NC), R39, R40, R41(NC) C
PHYRSTB U1

40
39
38
37
36
35
34
33
32
31
Pull-up to disable PLL @ ALDPS mode.
CFG_LDO1=1'b0 R38, R39(NC), R40(NC), R41

AVDD33 40

AVDD10 38

LED2/CFG_LDO1
LED1/CFG_LDO0
XTAL_IN
RSET

CLKOUT

LED0/CFG_EXT
XTAL_OUT/EXT_CLK

INTB/PMEB
41

RGMII TXC/RXC Delay Config. MDIO

EGND
3.3V Power Supply
MDI0+ 1 30 REGOUT
DVDDRG MDI0- 2 MDI[0]+
MDI[0]-
REG_OUT
DVDD33 29
29 DVDD33 VDD33 AVDD33
AVDD10 3 28 DVDDRG
MDI1+ 4 AVDD10 3 DVDD_RG 27 RXC/PHYAD1
R12 4.7K RXD1/TXDLY R13 4.7K (NC) DVDDRG MDI1- 5 MDI[1]+
MDI[1]-
RXC/PHYAD1
RXCTL/PHYAD2
26 RXCTL/PHYAD2 R1 0 AVDD33
R14 4.7K RXD0/RXDLY R15 4.7K (NC) R11 1.5K MDI2+ 6 25 RXD0/RXDLY
MDIO MDI2- 7 MDI[2]+ RXD0/RXDLY 24 RXD1/TXDLY C1 C2
AVDD10 8 MDI[2]- RXD1/TXDLY 23 RXD2/PLLOFF
MDI3+ 9 AVDD10 8 RXD2/PLLOFF 22 RXD3/PHYAD0 0.1uF 0.1uF
MDI3- 10 MDI[3]+ RXD3/PHYAD0 21 DVDD10
Close to PHY PIN11 and PIN40 for Analog Power
MDI[3]- DVDD10 21
Pull-up for additional 2ns delay to TXC/RXC for data latching. RTL8211F(D)(I)
DVDD33

AVDD33 11
PHYRSTB
RGMII Voltage Config. RGMII Power Source CFG_EXT CFG_LDO[1:0] R2 0 DVDD33

TXCTL
MDIO
TXD3
TXD2
TXD1
TXD0
MDC

TXC
C3 C4
External 3.3V (default) 1'b1 2'b00 Reserved for EMI.
0.1uF 4.7uF X5R/X7R Close to PHY PIN29 for Digital Power & SWR
External 2.5V 1'b1 2'b01 (optional)

11
12
13
14
15
16
17
18
19
20
DVDD33 External 1.8V 1'b1 2'b10
R16 4.7K (NC) LED0/CFG_EXT R17 4.7K
External 1.5V 1'b1 2'b11

PHYRSTB
R18 4.7K LED1/CFG_LDO0 R19 4.7K (NC)

AVDD33
LED2/CFG_LDO1

TXCTL
R20 4.7K R21 4.7K (NC)
Internal 2.5V 1'b0 2'b01

MDIO
TXD3
TXD2
TXD1
TXD0
B

MDC
B

TXC
Internal 1.8V 1'b0 2'b10 Switching Regulator
Internal 1.5V 1'b0 2'b11
R3 0 (NC)
DVDD10
PHY Address Config. PHY Address PHYAD[2:0] REGOUT R4 0
C8
DVDD10

C5 (NC) L1 C6 C7
0 3'b000 2.2uH/1A 0.1uF
0.1uF 4.7uF X7R 0.1uF
1 (default) 3'b001 Reserved for EMI.
DVDDRG 2 3'b010 (optional)
R22 4.7K (NC) RXD3/PHYAD0 R23 4.7K
3 3'b011 Note 7* Note 6* AVDD10
R24 4.7K RXC/PHYAD1 R25 4.7K (NC)
R26 4.7K RXCTL/PHYAD2 R27 4.7K (NC) R5 0 AVDD10
4 3'b100 For LDO mode For SWR mode C9 C10 C11
5 3'b101 0.1uF 0.1uF 0.1uF
6 3'b110 Note 1: The Trace length between L1 and PHY Pin 30 must be within 0.5 cm,
C6 and C7 to L1 must be within 0.5cm.
7 3'b111
Note 2: Bypass CAPs close to PHY DVDD10/AVDD10 power pins.
RGMII RX Filter Network RGMII Power Note 3: Any inductance or bead except L1 is not allowed on the path from REGOUT to DVDD10/AVDD10.

DVDD33 Note 4: R3 is reserved to change the DVDD10/AVDD10 supply source to LDO mode (RTL8211FD).

RXC/PHYAD1 R47 0
Note 1: R6 is not needed for ONLY 3.3V RGMII application, Note 5: No design change of PCB model is needed if R3 is reserved. If only RTL8211FD used for particular
RXC_N R6 and DVDDRG can be connected directly to DVDD33. PCB model, directly short REGOUT to DVDD10/AVDD10.
A C27 A
Close to PHY. Reserved for EMI. 0 DVDDRG Note 2: DVDDRG must be short (or R6 be mounted) to Note 6: If RTL8211FI is selected, the C6 should be replaced as 10uF X7R capacitor for industrial grade
22pF (NC) (optional) DVDDRG DVDD33 if the external RGMII 3.3V is selected. application. Please refer to the datasheet for other industrial grade information.
RXD0/RXDLY R48 0 C12 C13 Note 3: R6 must be removed if the internal or external Note 7: If RTL8211FDI is selected, the C5 should be replaced for industrial grade application and the value
RXD0_N
RXD1/TXDLY R49 0 0.1uF 4.7uF 2.5V/1.8V/1.5V RGMII is selected. is still under testing.
RXD1_N
RXD2/PLLOFF R50 0 Note 4: CAPs must be closed to pin28 for EMI consideration.
RXD2_N Realtek Semiconductor Corp.
RXD3/PHYAD0 R51 0 No.2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
RXD3_N Title
RXCTL/PHYAD2 R52 0 RTL8211F(D)(I) UTP <=> RGMII QFN-40 Pin Reference Schematic: PHY
RXCTL_N
Size Document Number Rev
C RTL8211F(D)(I) UTP <=> RGMII QFN-40 Pin Reference Schematic 1.02

Date: Thursday, December 24, 2015 Sheet 2 of 2

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