11001101011010

10101010101010
10101010111010
01010011101101
010101

SAR ADC’s and Delta Sigma ADC’s:

Different Architectures for Different Applications

1
Selecting ADC Topology
ADC Topology Data Rate Resolution Comments

SAR • Easy to Use

≤ 4 Msps ≤ 16-bit
ADS7xxx • Zero Latency
≤ 1.25 Msps ≤ 18-bit
ADS8xxx • Low Power

Delta-Sigma
ADS10xx/11xx ≤ 4 Ksps > 24-bit
• High Resolution
ADS12xxx ≤ 4 Msps ≤ 24-bit
• High Integration
ADS13xxx ≤ 10 Msps ≤ 16-bit
ADS16xx

≤ 200 Msps ≤ 16-bit • Higher Speed

Pipeline ≤ 250 Msps ≤ 14-bit • Higher Power
≤ 1000 Msps ≤ 12-bit
2
Selecting ADC Topology
ADC Topology Data Rate Resolution Comments

SAR • Easy to Use

≤ 4 Msps ≤ 16-bit
ADS7xxx • Zero Latency
≤ 1.25 Msps ≤ 18-bit
ADS8xxx • Low Power

Delta-Sigma
ADS10xx/11xx ≤ 4 Ksps > 24-bit
• High Resolution
ADS12xxx ≤ 4 Msps ≤ 24-bit
• High Integration
ADS13xxx ≤ 10 Msps ≤ 16-bit
ADS16xx

≤ 200 Msps ≤ 16-bit • Higher Speed

Pipeline ≤ 250 Msps ≤ 14-bit • Higher Power
≤ 1000 Msps ≤ 12-bit
3
Selecting ADC Topology
ADC Topology Data Rate Resolution Comments

SAR • Easy to Use

≤ 4 Msps ≤ 16-bit
ADS7xxx • Zero Latency
≤ 1.25 Msps ≤ 18-bit
ADS8xxx • Low Power

Delta-Sigma
ADS10xx/11xx ≤ 4 Ksps > 24-bit
• High Resolution
ADS12xxx ≤ 4 Msps ≤ 24-bit
• High Integration
ADS13xxx ≤ 10 Msps ≤ 16-bit
ADS16xx

≤ 200 Msps ≤ 16-bit • Higher Speed

Pipeline ≤ 250 Msps ≤ 14-bit • Higher Power
≤ 1000 Msps ≤ 12-bit
4
Selecting ADC Topology
ADC Topology Data Rate Resolution Comments

SAR • Easy to Use

≤ 4 Msps ≤ 16-bit
ADS7xxx • Zero Latency
≤ 1.25 Msps ≤ 18-bit
ADS8xxx • Low Power

Delta-Sigma
ADS10xx/11xx ≤ 4 Ksps > 24-bit
• High Resolution
ADS12xxx ≤ 4 Msps ≤ 24-bit
• High Integration
ADS13xxx ≤ 10 Msps ≤ 16-bit
ADS16xx

≤ 200 Msps ≤ 16-bit • Higher Speed

Pipeline ≤ 250 Msps ≤ 14-bit • Higher Power
≤ 1000 Msps ≤ 12-bit
5
SAR vs. Delta-Sigma
What is the ADC actually converting?

SAR 

SAR ADC takes “snapshots”  ADC calculates an average

Each conversion command captures the The signal is sampled continuously
signal level, at that point in time, onto the
sample/hold
6
SAR vs. Delta-Sigma
How does the ADC control happen?

• SAR conversions have Start Conversion Signal

• Delta-Sigma is always sampling/converting

SAR Converter
Start Conversion
Conversion Done

Delta-Sigma Converter
Input Sampling
Conversion Done

7
How Does a SAR ADC Work?
• Similar to a balance scale

? 1
½ ¼ 8
How Does a SAR ADC Work?
• Similar to a balance scale

1
½ ¼ 9
How Does a SAR ADC Work?
• Similar to a balance scale

1
½ ¼ 10
How Does a SAR ADC Work?
• Similar to a balance scale

The MSB is determined first

1
?
MSB
1

½ ¼ 11
How Does a SAR ADC Work?
• Similar to a balance scale
The test is repeated for each
Binary weighted bit

? 1
½
MSB Mid
1 0

¼ 12
How Does a SAR ADC Work?
• Similar to a balance scale

The LSB is determined last

? 1
¼
MSB Mid LSB
1 0 1

½ 13
Typical Topology of a SAR ADC

14
SAR ADC Acquisition Phase

VIN
DAC
SAMPLE & HOLD

Data Register
COMPARATOR S1 S2
VIN SAR
C
N-bit Search
DAC

15
SAR ADC Acquisition Phase

VIN
DAC
SAMPLE & HOLD
Data Register
S1 S2
VIN SAR
COMPARATOR

C
VIN
1/2 LSB N-bit Search
DAC

VCSH(t)

VSH0

t0 tAQ Time
16
SAR ADC Acquisition Phase

VIN
DAC
SAMPLE & HOLD

COMPARATOR

VIN
1/2 LSB

VCSH(t) t

VCSH (t )  VCSH (t0 )  [VIN  VCSH (t0 )]  (1  e 
)
VSH0

  RS1  CSH
t0 tAQ Time
17
SAR ADC Conversion Phase
FS

Bit = 0 Analog
3/4FS Bit = 0
Bit = 1 Bit = 0 Input

Bit = 1
VDAC

1/2FS
TEST TEST TEST TEST TEST
MSB MSB -1 MSB -2 MSB -3 LSB

1/4FS

0
Time
DAC Output Digital Output Code = 10100
18
SAR ADCs
• Very Popular Topology SAR ADC
• Attractive in “Point in Time” or Multiplexed Measurements
• Advantages
– “no latency”
• input is sampled once
• “balancing” done internally
– good tradeoff between speed, resolution and power
• Speed: DC to 4MSPS
• Resolution: 8 to 18 bits; and moving towards higher resolutions
• TI Part Numbers:
– ADS7xxx
– ADS8xxx
19
Delta Sigma Topology

Analog Delta Sigma

Delta-Sigma
Input Modulator
Modulator

Digital
Digital Digital
Decimator
Filter Decimator Output
Filter

Digital Decimating Filter

20
 Delta Sigma Topology (2)

High frequency, 1 bit PCM data stream

SAMPLING RATE (Fs)
Analog Delta Sigma
Delta-Sigma
Input Modulator
Modulator
(Samples at High Frequency)

Digital
Digital Digital
Decimator
Filter Decimator Output
Filter

Digital Decimating Filter

21
Delta Sigma Topology (3)

High frequency, 1 bit PCM data stream

SAMPLING RATE (Fs)
Analog Delta Sigma
Delta-Sigma
Input Modulator
Modulator
Input Oversampling

Digital
Digital Digital
Decimator
Filter Decimator Output
Filter

Digital Decimating Filter DATA RATE (Fd)

Lower data rate, very high
resolution digital output

22
 Oversampling (1)

Power
Ideal N-Bit ADC
Input SNR= 6.02 N + 1.76 dB
Signal
Average Noise
Floor

DC fs/2 fs

Average Noise energy

distributed from DC to
fs/2

23
 Oversampling (2)

Oversampling
Digital Low Pass
Power Power filter
Ideal N-Bit ADC
Input SNR= 6.02 N + 1.76 dB
Signal SNR= 6.02 N + 1.76 dB +10 log (OSR)

Average Noise
Floor
Average Noise
Floor

DC fs/2 fs DC K fs/2 K fs
Average Noise energy distributed over a
Average Noise energy
distributed from DC to
wider range from DC to K fs/2
fs/2 – On a Delta-Sigma Converter, the analog input is
sampled at a Frequency much higher than the
Nyquist rate
24
Delta Sigma Modulator

Delta Sigma
Modulator

Digital
Decimato
Filter
r

25
First Order Delta-Sigma Modulator (1)

Noise Shaping

Quantization
Noise
ei

Input + Integrator
Signal ∑ (Low-Pass) ∑ Yi
Xi A(f)=1/f 1-Bit
-
ADC

1-Bit
DAC

26
First Order Delta-Sigma Modulator (2)

Noise Shaping Quantization

Noise
ei

Input + Integrator
Signal ∑ (Low-Pass) ∑ Yi
Xi A(f)=1/f 1-Bit
-
ADC

1-Bit
DAC

𝑌= 𝑋−𝑌 𝐴 𝑓 +𝑒 𝑛 (1)

𝑓 1
𝑌=𝑒 𝑛 +𝑋 (2)
1+𝑓 1+𝑓
Noise Signal
Transfer Transfer
Function Function 27
First Order Delta-Sigma Modulator (3)

Noise Shaping Quantization

Noise
ei

Input + Integrator
Signal ∑ (Low-Pass) ∑ Yi
Xi A(f)=1/f 1-Bit
-
ADC

1-Bit
DAC

𝑌= 𝑋−𝑌 𝐴 𝑓 +𝑒 𝑛 (1)
Signal

Magnitude
𝑓 1
𝑌=𝑒 𝑛 +𝑋 (2)
1+𝑓 1+𝑓
Noise Signal Quantization
Transfer Transfer Noise
Function Function 28
First Order Delta-Sigma Modulator (4)

Noise Shaping

Modulator Output:
TIME DOMAIN

Believe it or not, the sine

wave is in there!
Signal

0
(drawing is approximate)

29
First Order Delta-Sigma Modulator (5)

Noise Shaping

Modulator Output:
TIME DOMAIN

Believe it or not, the sine

wave is in there!
Signal

0
(drawing is approximate)

30
First Order Delta-Sigma Modulator (6)

Noise Shaping

Modulator Output: Modulator Output:

TIME DOMAIN FREQUENCY DOMAIN

Believe it or not, the sine

wave is in there! SIGNAL
Signal

0
(drawing is approximate) Fs
QUANTIZATION
NOISE

31
Higher Order Delta-Sigma Modulators

Third Order
 Modulator

Second Order
 Modulator

First Order
 Modulator

Frequency FS
32
Delta-Sigma A/D Signal Path

Delta Sigma
Modulator

Digital
Decimator
Filter

33
Modulator Noise Shaping and Digital Filter (1)

 Modulator
Noise Shaping

Frequency FS
34
Modulator Noise Shaping and Digital Filter (2)

 Modulator
Noise Shaping

Frequency FS
35
Modulator Noise Shaping and Digital Filter (3)

Filter set by  Modulator

Oversampling Noise Shaping
Ratio

Frequency FS
36
Digital Filter

• Digital filter architecture determines overall ADC response.

• Common filters: “Sinc” and “Flat Passband”

Sinc Filter Flat Passband Filter

37
Sinc Digital Filter
• Typically used for DC
measurements, or slow moving
signals Sinc filter response

Advantages 0

• Economical silicon area, easy to Sinc 1

Sinc 3

implement -20
Sinc 5

– Low cost
– Low power
• Low latency -40

Attentuation, dB
• Filter notches can target specific
frequencies (ex. 50/60 Hz) -60

Disadvantages
• Pass band signal droop -80

• Weak Stop band attenuation for

Fdata
low-order Sinc filters
-100
0 1 2 3 4 5 6
Frequency (x Fdata)

38
Sinc Digital Filter Settling
Uncertainty of Analog Edge 
4 Data Cycles

0 1 2 3 0 1 2 3
Fdata periods
3 full cycles 3 full cycles
Analog Inputs

4 cycles
Valid data Valid data

Settling time for an input step change, Sinc3 filter

Need n cycles to settle for a Sincn filter

39
 Delta Sigma: Zero Cycle Latency (1)

Single Cycle
Conversion
N+0 N+1 N+2
Analog IN N+3

N-1 N+0 N+1 N+2 N+3

Data OUT
Data
Invalid

• Zero cycle Latency =

– Zero latency
– Single cycle conversion
– Single cycle settling
– No Latency 40
 Delta-Sigma: Zero Cycle Latency (2)

Single Cycle
Conversion
N+0 N+1 N+2
Analog IN N+3

N-1 N+0 N+1 N+2 N+3

Data OUT
Data
Invalid
“Hidden Conversions”
• Zero cycle Latency =
– Zero cycle latency
– Single cycle conversion
– Single cycle settling
– No Latency 41
Flat Pass Band Filter
Advantages
• Frequency Response
• Very low ripple pass band
Low Ripple Passband
• Sharp Nyquist transition band
• Large stopband attenuation: lower than
-100dB (simplify aliasing requirement)
• Frequency response scalable with master
clock 100dB stop band
Disadvantages
• Large area – Costly
• Higher-order / high-tap filter – large latency

42
Delta-Sigma: Flat Passband Digital Filter Settling
• The latency of the filter depends on the number of delay blocks used
• Flat Passband filters require a lot delay blocks to maintain desired AC response
• Many Delta-Sigma Converters incorporate filters with programmable settings:
– Optimize for lower latency, power consumption or for AC performance/higher resolution

Modulator delay delay delay delay delay

Data
Input

Σ
FIR filter block
topology Digital Filter
Output
43
ΔΣ ADCs: Simplifying the Signal Chain (1)

CT Passive Network +
Protection In +
R1 Out Processor
ADC
ADC Drive
MUX
Passive Network +
R2
Circuitry
Protection

Signal Iso
Sensor Gain Stage Mux ADC Drive ADC
Conditioning
and
Protection MCU

44
ΔΣ ADCs: Simplifying the Signal Chain (2)

CT Passive Network +
Protection In +
R1 Out Processor
ADC
ADC Drive
MUX
Passive Network +
R2
Circuitry
Protection

Signal Iso
Sensor Gain Stage Mux ADC Drive ADC
Conditioning
and
Protection MCU

Delta-Sigma ADCs integrate many signal chain elements into one device
45
Delta-Sigma ADC’s
• Highest Resolution and High Stability with moderate power consumption
• Incorporate a Digital Filter
• Frequency Response, and Latency dependent on Digital Filter
• Typically Highly Integrated devices:
– Digital Filter, Buffer, PGA, MUX, Vref, Calibration/diagnostics
• Typically Requires Configuration of Registers

ΔΣ ADC

46
SAR ADCs
• Very Popular Topology SAR ADC
• Attractive in “Point in Time” or Multiplexed Measurements
• Advantages
– “no latency”
• input is sampled once
• “balancing” done internally
– good tradeoff between speed, resolution and power
• Speed: DC to 4MSPS
• Resolution: 8 to 18 bits; and moving towards higher resolutions
• TI Part Numbers:
– ADS7xxx
– ADS8xxx
47
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48