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9.unit IX Programming Devices

The document discusses several types of programmable devices: PLA, PAL, CPLD, and FPGA. It provides details on the characteristics of each: PALs have a programmable AND array and fixed OR array, producing a sum-of-products expression, while PLAs have programmable AND and OR arrays. CPLDs contain multiple SPLD blocks and programmable interconnects to implement complex logic functions. FPGAs contain programmable logic blocks and interconnects that can be configured to perform different combinational and sequential logic functions.

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Prashant Sarraf
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53 views25 pages

9.unit IX Programming Devices

The document discusses several types of programmable devices: PLA, PAL, CPLD, and FPGA. It provides details on the characteristics of each: PALs have a programmable AND array and fixed OR array, producing a sum-of-products expression, while PLAs have programmable AND and OR arrays. CPLDs contain multiple SPLD blocks and programmable interconnects to implement complex logic functions. FPGAs contain programmable logic blocks and interconnects that can be configured to perform different combinational and sequential logic functions.

Uploaded by

Prashant Sarraf
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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By : Er.Jaikishan Kumar (M.

Tech-CSE)
▪ Introduction to various programmable devices
1. PLA
2. PAL
3. CPLD
4. FPGA
▪

▪
▪ A PAL (programmable array logic) consists of a programmable array of AND gates that
connects to a fixed array of OR gates. Generally, PALs are implemented with fuse process
technology and are, therefore, one-time programmable (OTP).

▪ The PAL structure allows any sum-of-products (SOP) logic expression with a defined
number of variables to be implemented.

▪ A simple PAL structure is shown in Figure 10–1 for two input variables and one output;
most PALs have many inputs and many outputs. As you learned earlier, a programmable
array is essentially a grid or matrix of conductors that form rows and columns with a
programmable link at each cross point. Each programmable link, which is a fuse in the
case of a PAL, is called a cell. Each row is connected to the input of an AND gate, and
each column is connected to an input variable or its complement. By programming the
presence or absence of a fuse connection, any combination of input variables or
complements can be applied to an AND gate to form any desired product term. The AND
gates are connected to an OR gate, creating a sum-of-products (SOP) output.
▪ The GAL is essentially a PAL that can be reprogrammed. It has the same type of
AND/ OR organization that the PAL does.
▪ The basic difference is that a GAL uses a reprogrammable process technology,
such as EEPROM(E2CMOS), instead of fuses, as shown in Figure 10–3.
▪ A macrocell generally consists of one OR gate and some associated output logic. The
macrocells vary in complexity, depending on the particular type of PAL or GAL. A
microcell can be configured for combinational logic, registered logic, or a
combination of both. Registered logic means that there is a flip-flop in the macrocell
to provide for sequential logic functions.
▪ The complex programmable logic device (CPLD) is basically a single device
containing multiple SPLDs and providing more capacity for larger logic designs
▪ SPLD array in a CPLD as a LAB (logic array block), Other designations are sometimes used,
such as function block, logic block, or generic block .

▪ The programmable interconnections are generally called the PIA (programmable


interconnect array) although some manufacturers, such as Xilinx, use the term AIM
(advanced interconnect matrix) or a similar designation. The LABs and the interconnections
between LABs are programmed using software.

▪ A CPLD can be programmed for complex logic functions based on the SOP structure of the
individual LABs (actually SPLDs). Inputs can be connected to any of the LABs, and their
outputs can be interconnected to any other LABs via the PIA.

▪ Most programmable logic manufacturers make a series of CPLDs that range in density,
process technology, power consumption, supply voltage, and speed. Manufacturers usually
specify CPLD density in terms of macrocells or logic array blocks. Densities can range
from tens of macrocells to over 1500 macrocells in packages with up to several hundred pins.
As PLDs become more complex, maximum densities will increase. Most CPLDs are
reprogrammable and use EEPROM or SRAM process technology for the programmable links.
▪ The PAL has a programmable AND array followed by a fixed OR array and produces an
SOP expression
▪ The PAL has a programmable AND array followed by a fixed OR array and produces an
SOP expression, as shown by the example in Figure 10–18(a).
▪ The PLA has a programmable AND array followed by a programmable OR array, as
shown by the example in Figure 10–18(b).
▪ Shared expander : A shared expander is used to increase the number of product
terms from a macrocell by ANDing additional sum terms (complemented product
terms) from other macrocells.

▪ Parallel expander:Parallel expander is used to increase the number of product


terms from a macrocell by ORing unused product terms from other macrocells in a
LAB.

NUTSHELL: A PLA has a programmable AND array and a programmable OR array. A


PAL has a fixed OR array.
A field-programmable gate array (FPGA) is an integrated circuit designed to be
configured by a customer or a designer after manufacturing – hence the term "field-
programmable".

The FPGA configuration is generally specified using a hardware description


language (HDL), similar to that used for an application-specific integrated
circuit (ASIC).

FPGAs contain an array of programmable logic blocks, and a hierarchy of


"reconfigurable interconnects" that allow the blocks to be "wired together", like
many logic gates that can be inter-wired in different configurations
▪ Logic blocks can be configured to perform complex combinational functions, or
merely simple logic gates like AND and XOR. In most FPGAs, logic blocks also
include memory elements, which may be simple flip-flops or more complete
blocks of memory.

▪ Many FPGAs can be reprogrammed to implement different logic functions,allowing


flexible reconfigurable computing as performed in computer software.

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