INTEGRATED CIRCUITS

DATA SHEET

SAA5281
Integrated Video input processor
and Teletext decoder (IVT1.8*)
Preliminary specification 1996 Nov 04
Supersedes data of June 1994
File under Integrated Circuits, IC02
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

FEATURES
• Complete Teletext and VPS decoding in a single
package
• Built-in 8K × 8 memory for up to 8 page storage
• Enhanced mode allows 7 Fastext pages and 8 pages of
TOP to be captured
• Ability to request only subtitle pages DESCRIPTION
• Acquisition and decoding of VPS data The IVT1.8* is a single-chip Teletext decoder IC for
• Data valid output available to indicate reception of decoding 625-line based World System Teletext
error-free VPS or packet 8/30/2 data transmissions. The device is based on IVT1.0VPS and has
reception facilities for the 5 MHz biphase VPS signal. It is
• Software and hardware compatible with SAA5246 and
intended for use in video recorders, in particular to
SAA5248
implement the VPT facility (VCR programming via
• Meshing display within boxes Teletext). With suitable software both VPT standards
• Separate data checking algorithms and pointers for (EBU PDC System A and System B) can be
each acquisition channel accommodated to allow operation from any European VPT
transmission. Automatic processing of packet 26
• 24 : 18 Hamming checker
transmissions is also possible. No external memory is
• Automatic packet 26 extension character processing required as an 8K × 8 DRAM is included on-chip for up to
• Indication of Line 23 for external use 8 page storage. An enhanced mode allows 7 Fastext
pages to be stored, with one chapter used to store
• 13.5 MHz clock output to drive external microcontroller
extension packets.
• Detection of Spanish transmissions to disable
flicker-stopper
• Compatible with Philips’ one-chip TV IC (TDA836X) for
scan-locking applications.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

VDD supply voltage 4.5 5.0 5.5 V
IDD supply current − 75 150 mA
Vsync sync voltage amplitude 0.1 0.3 0.6 V
Vvid(p-p) video input voltage amplitude 0.7 1.0 1.4 V
(peak-to-peak value)
fxtal crystal frequency − 27 − MHz
Tamb operating ambient temperature −20 − +70 °C

ORDERING INFORMATION

PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
SAA5281P DIP48 plastic shrink dual in-line package; 32 leads (400 mil) SOT240-1
SAA5281ZP SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1
SAA5281GP QFP64 plastic quad flat package; 64 leads SOT319-2
(lead length 1.95 mm); body 14 × 20 × 2.8 mm

1996 Nov 04 2
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

BLOCK DIAGRAM

handbook, full pagewidth

BLAN RGBREF
V DD1 VDD2
Y COR R G B

1 10 22 19 20 18 15 16 17

DRAM
POWER-ON REFRESH 8K x 8
RESET AND DRAM
DISPLAY
TIMING

ODD/EVEN 21
(or DV)

24 TO 18 PACKET 26 MEMORY
HAMMING PROCESSING INTERFACE
DECODER ENGINE

TELETEXT
AQUISITION 24
SDA
AND DECODING I 2 C-BUS
INTERFACE 23
SCL
VPS
ACQUISITION
AND
DECODING
SERIAL-TO 44
TIMING LINE 23
-PARALLEL
CONVERTER SAA5281 CHAIN

DATA SLICER TELETEXT DISPLAY CLOCK

AND CLOCK OR PHASE-LOCKED VCR/FFB
REGENERATOR LOOP 13
VPS CONTROL

11
6 POL
REF CLK O/P
37
ANALOG INPUT
9 ANALOG ANALOG 27 MHz
TO CLAMP 4
IREF REFERENCE OUTPUT CLOCK OSCGND
DIGITAL AND SYNC
GENERATOR BUFFER GENERATOR
CONVERTER SEPARATOR

5 14 25 8 7 12 36 2 3
MBD783
CVBS BLACK STTV/LFB CLK EN OSCIN
V SS1 VSS2 V SS3 OSCOUT

Fig.1 Block diagram; pin numbers for DIP48 (SOT240-1).

1996 Nov 04 3
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

PINNING

PIN
SYMBOL DESCRIPTION
SOT240-1 SOT247-1 SOT319-2
VDD1 1 52 11 +5 V supply 1
OSCOUT 2 1 13 27 MHz crystal oscillator output
OSCIN 3 2 14 27 MHz crystal oscillator input
OSCGND 4 3 15 0 V crystal oscillator ground
VSS1 5 4 and 5 16 0 V ground
REF+ 6 6 18 positive reference voltage for ADC; this pin should be connected
to ground via a 100 nF capacitor
BLACK 7 8 19 video black level storage input/output; this pin should be
connected to ground via a 100 nF capacitor
CVBS 8 9 20 composite video input; a positive-going 1 V (peak-to-peak) input
is required, connected via a 100 nF capacitor
IREF 9 10 21 reference current input, connected to ground via a 27 kΩ resistor
VDD2 10 11 22 +5 V supply 2
POL 11 12 23 STTV/LFB/FFB polarity selection input
STTV/LFB 12 13 24 sync to TV output line flyback input; function controlled by an
internal register bit (scan sync mode)
VCR/FFB 13 14 27 PLL time constant switch/field input; function controlled by an
internal register bit (scan sync mode)
VSS2 14 15 28 0 V ground; connected to VSS1 for normal operation
R 15 16 30 dot rate character output of the RED colour information
G 16 17 32 dot rate character output of the GREEN colour information
B 17 18 33 dot rate character output of the BLUE colour information
RGBREF 18 19 34 input DC voltage to define the output high level on the RGB pins
BLAN 19 20 35 dot rate fast blanking output
COR 20 21 36 programmable output to provide contrast reduction of the TV
picture for mixed text and picture displays or when viewing
newsflash/subtitle pages;
open-drain output
ODD/EVEN 21 22 37 in ODD/EVEN mode a 25 Hz output synchronized with the CVBS
(or DV) input field sync pulses to produce a non-interlaced display by
adjustment of the vertical deflection currents; in DV mode a VPT
data valid signal is used to indicate reception of error-free VPS or
8/30 format 2 data
Y 22 23 38 dot rate character output of teletext foreground colour information;
open-drain output
SCL 23 24 39 serial clock input for I2C-bus; it can still be driven HIGH during
power-down of the device
SDA 24 25 40 serial data port for the I2C-bus, open-drain output; it can still be
driven HIGH during power-down of the device
VSS3 25 26 44 0 V ground

1996 Nov 04 4
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

PIN
SYMBOL DESCRIPTION
SOT240-1 SOT247-1 SOT319-2
i.c. 26 to 35, 27 to 32, 1 to 3, internally connected; normally open-circuit
38 to 43, 35 to 38, 5 to 8,
45 to 48 41 to 46, 45 to 53,
48 to 51 55, 61,
63 to 64
CLK EN 36 39 56 clock enable input to enable the clock output (CLP O/P pin 37);
internal pull-down normally disables clock
CLK O/P 37 40 59 13.5 MHz clock output to drive an external microcontroller
LINE 23 44 47 4 output for indication of Line 23 for use with external circuitry
n.c. − 7, 33, 34 9, 10, 12, not connected; normally open-circuit
17, 25, 26,
29, 31,
41 to 43,
54, 57, 58,
60, 62

1996 Nov 04 5
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

handbook, halfpage
OSCOUT 1 52 V DD1
handbook, halfpage
VDD1 1 48 i.c. OSCIN 2 51 i.c.

OSCOUT 2 47 i.c. OSCGND 3 50 i.c.

OSCIN 3 46 i.c. V SS1 4 49 i.c.

OSCGND 4 45 i.c. V SS1 5 48 i.c.

V SS1 5 44 LINE 23 REF+ 6 47 LINE 23

REF+ 6 43 i.c. n.c. 7 46 i.c.

BLACK 7 42 i.c. BLACK 8 45 i.c.

CVBS 8 41 i.c. CVBS 9 44 i.c.

IREF 9 40 i.c. IREF 10 43 i.c.

V DD2 10 39 i.c. V DD2 11 42 i.c.

POL 11 38 i.c. POL 12 41 i.c.

SAA5281
STTV/LFB 12 37 CLK O/P STTV/LFB 13 40 CLK O/P
SAA5281
VCR/FFB 13 36 CLK EN VCR/FFB 14 39 CLK EN

V SS2 14 35 i.c. V SS2 15 38 i.c.

R 15 34 i.c. R 16 37 i.c.

G 16 33 i.c. G 17 36 i.c.

B 17 32 i.c. B 18 35 i.c.

RGBREF 18 31 i.c. RGBREF 19 34 n.c.

BLAN 19 30 i.c. BLAN 20 33 n.c.

COR 20 29 i.c. COR 21 32 i.c.

ODD/EVEN 28
21 i.c. ODD/EVEN 22 31 i.c.
(or DV)
(or DV)
Y 22 27 i.c. Y 23 30 i.c.

SCL 23 26 i.c. SCL 24 29 i.c.

SDA 24 25 V SS3 SDA 25 28 i.c.

MBD784 V SS3 26 27 i.c.

MBD785

Fig.2 Pin configuration; SOT240-1 (DIP48). Fig.3 Pin configuration; SOT247-1 (SDIP52).

1996 Nov 04 6
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

59 CLK O/P
handbook, full pagewidth

56 CLK EN
62 n.c.

60 n.c.

58 n.c.

57 n.c.

54 n.c.
64 i.c.

63 i.c.

61 i.c.

55 i.c.

53 i.c.

52 i.c.
i.c. 1 51 i.c.

i.c. 2 50 i.c.

i.c. 3 49 i.c.

LINE 23 4 48 i.c.

i.c. 5 47 i.c.

i.c. 6 46 i.c.

i.c. 7 45 i.c.

i.c. 8 44 VSS3

n.c. 9 43 n.c.

n.c. 10 SAA5281 42 n.c.

VDD1 11 41 n.c.

n.c. 12 40 SDA

OSCOUT 13 39 SCL

OSCIN 14 38 Y

OSCGND 15 37 ODD/EVEN
(or DV)
VSS1 16 36 COR

n.c. 17 35 BLAN

REF+ 18 34 RGBREF

BLACK 19 33 B
CVBS 20

IREF 21

VDD2 22

POL 23

STTV/LFB 24

n.c. 25

n.c. 26

VCR/FFB 27

VSS2 28

n.c. 29

R 30

n.c. 31

G 32

MBH665

Fig.4 Pin configuration; SOT319-2 (QFP64).

1996 Nov 04 7
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

QUALITY AND RELIABILITY

This device will meet Philips Semiconductors General Quality Specification for Business group “Consumer Integrated
Circuits SNW-FQ-611-Part E”. The principal requirements are shown in Tables 1 to 4.

Group A
Table 1 Acceptance tests per lot

TEST REQUIREMENTS(1)
Mechanical cumulative target: <100 ppm
Electrical cumulative target: <100 ppm

Group B
Table 2 Processability tests (by package family)

TEST REQUIREMENTS(1)
Solderability <7% LTPD
Mechanical <15% LTPD
Solder heat resistance <15% LTPD

Group C
Table 3 Reliability tests (by process family)

TEST CONDITIONS REQUIREMENTS(1)

Operational life 168 hours at Tj = 150 °C <1500 FPM; equivalent to
<100 FITS at Tj = 70 °C
Humidity life temperature, humidity, bias <2000 FPM
1000 hours, 85 °C, 85% RH
(or equivalent test)
Temperature cycling performance Tstg(min) to Tstg(max) <2000 FPM

Table 4 Reliability tests (by device type)

TEST CONDITIONS REQUIREMENTS(1)
ESD and latch-up ESD Human body model <15% LTPD
2000 V, 100 pF, 1.5 kΩ
ESD Machine model <15% LTPD
200 V, 200 pF, 0 Ω
latch-up 100 mA, 1.5 × VDD <15% LTPD
(absolute maximum)

Notes to Tables 1 to 4
1. ppm = fraction of defective devices, in parts per million.
LTPD = Lot Tolerance Percent Defective.
FPM = fraction of devices failing at test condition, in Failures Per Million.
FITS = Failures In Time Standard.

1996 Nov 04 8
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

LIMITING VALUES
In accordance with Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER MIN. MAX. UNIT
VDD supply voltage (all supplies) −0.3 +6.5 V
VI input voltage (any input) −0.3 VDD + 0.5 V
VO output voltage (any output) −0.3 VDD + 0.5 V
IO output current (each output) − ±10 mA
IIOK DC input or output diode current − ±20 mA
Tamb operating ambient temperature −20 +70 °C

CHARACTERISTICS
VDD = 5 V ±10%; Tamb = −20 to +70 °C; pin numbers refer DIP48 package; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies
VDD supply voltage 4.5 5.0 5.5 V
IDDtot total supply current − 75 150 mA
Inputs
CVBS
Vsync sync voltage amplitude 0.1 0.3 0.6 V
Vburst(p-p) colour burst amplitude 0.0 0.3 4.0 V
(peak-to-peak value)
td(sync) delay from CVBS to TCS −150 0 +150 ns
output from STTV buffer
(nominal video, average of
leading/trailing edge)
∆td(sync) change in sync delay between 0 − 25 ns
all black and all white video
input at nominal levels
Vvid(p-p) video input voltage amplitude 0.7 1.0 1.4 V
(peak-to-peak value)
Vdat(text) teletext data voltage amplitude 0.29 0.46 0.71 V
∆f/f display PLL capture range ±7 − − %
Zsource source impedance − − 250 Ω
VI input switching voltage level of 1.7 2.0 2.3 V
sync separator
ZI input impedance 2.5 5.0 − kΩ
CI input capacitance − − 10 pF
IREF
Rgnd resistor to ground − 27 − kΩ
Vi input voltage − 0.5VDD − V

1996 Nov 04 9
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

POL
VIL LOW level input voltage −0.3 − +0.8 V
VIH HIGH level input voltage 2.0 − VDD + 0.5 V
ILI input leakage current VI = 0 to VDD −10 − +10 µA
CI input capacitance − − 10 pF
LFB
VIL LOW level input voltage −0.3 − tbf V
VIH HIGH level input voltage tbf − VDD + 0.5 V
ILI input leakage current VI = 0 to VDD −10 − +10 µA
IImax maximum input current note 1 −1 − +1 mA
tdLFB delay between LFB front edge − 250 − ns
and input video line sync
VCR/FFB
VIL LOW level input voltage −0.3 − +0.8 V
VIH HIGH level input voltage 2.0 − VDD + 0.5 V
ILI input leakage current VI = 0 to VDD −10 − +10 µA
IImax maximum input current note 1 −1 − +1 mA
RGBREF
VIL LOW level input voltage −0.3 − VDD V
ILI input leakage current VI = 0 to VDD −10 − +10 µA
SCL
VIL LOW level input voltage −0.3 − +1.5 V
VIH HIGH level input voltage 3.0 − VDD + 0.5 V
ILI input leakage current VI = 0 to VDD −10 − +10 µA
CI input capacitance − − 10 pF
fclk clock frequency 0 − 100 kHz
tr input rise time between 10% and 90% − − 2 µs
tf input fall time between 90% and 10% − − 2 µs
Inputs/outputs
CRYSTAL OSCILLATOR (OSCIN; OSCOUT)
Vosc(p-p) oscillator voltage amplitude − 1.0 − V
(peak-to-peak value)
Gv small signal voltage gain − 1.0 −
Gm mutual conductance 5.0 − − mS
CI input capacitance − − 10 pF
Cfb feedback capacitance − 1 − pF

1996 Nov 04 10
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

BLACK
Cblack storage capacitor to ground − 100 − nF
Vblack black level voltage for nominal 1.8 2.15 2.5 V
sync amplitude
ILI input leakage current VI = 0 to VDD −10 − +10 µA
SDA (OPEN-DRAIN INPUT/OUTPUT)
VIL LOW level input voltage −0.3 − +1.5 V
VIH HIGH level input voltage 3.0 − VDD + 0.5 V
VOL LOW level output voltage IOL = 3 mA 0 − 0.5 V
ILI input leakage current VI = 0 to VDD −10 − +10 µA
CI input capacitance − − 10 pF
CL load capacitance − − 400 pF
tr input rise time between 10% and 90% − − 2 µs
tf input fall time between 90% and 10% − − 2 µs
tf output fall time between 3 V and 1 V − − 200 ns
Outputs
STTV
Gsttv gain of STTV relative to video 0.9 1.0 1.1
input
Vtcs TCS voltage amplitude 0.2 0.3 0.45 V
∆Vtcs DC shift between TCS output − − 0.15 V
and nominal video output
IO output drive current − − 3.0 mA
CL load capacitance − − 100 pF
R, G AND B
VOL LOW level output voltage IOL = 2 mA 0 − 0.2 V
VOH HIGH level output voltage IOH = −1.6 mA; VRGBREF VRGBREF VRGBREF V
VRGBREF < VDD − 2 V; − 0.25 + 0.5
note 2
|Zo| output impedance − − 200 Ω
CL load capacitance − − 50 pF
tr output rise time between 10% and 90% − − 20 ns
tf output fall time between 90% and 10% − − 20 ns
BLAN
VOL LOW level output voltage IOL = 1.6 mA 0 − 0.4 V
VOH HIGH level output voltage IOH = − 0.2 mA 1.1 − − V
IOH = 0 mA − − 2.8 V
CL load capacitance − − 50 pF
tr output rise time between 10% and 90% − − 20 ns
tf output fall time between 90% and 10% − − 20 ns

1996 Nov 04 11
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

ODD/EVEN OR DV
VOL LOW level output voltage IOL = 1.6 mA 0 − 0.4 V
VOH HIGH level output voltage IOH = −1.6 mA VDD − 0.4 − VDD V
CL load capacitance − − 120 pF
tr output rise time between 0.6 V and − − 50 ns
2.2 V
tf output fall time between 0.6 V and − − 50 ns
2.2 V
COR AND Y (OPEN-DRAIN OUTPUTS)
VOH HIGH level pull-up output − − VDD V
voltage
VOL LOW level output voltage IOL = 2 mA 0 − 0.4 V
IOL = 5 mA 0 − 1.0 V
CL load capacitance − − 25 pF
tf output fall time load resistor of 1.2 kΩ − − 50 ns
to VDD; measured
between VDD − 0.5 V
and 1.5 V
ILO output leakage current VI = 0 to VDD −10 − +10 µA
tskew skew delay between display − − 20 ns
outputs R, G, B, COR, Y and
BLAN
I2C-bus timing (see Fig.5)
tLOW SCL clock LOW time 4.0 − − µs
tHIGH SCL clock HIGH time 4.0 − − µs
tSU;DAT data set-up time 250 − − ns
tHD;DAT data hold time 170 − − ns
tSU;STO set-up time from clock HIGH 4.0 − − µs
to STOP
tBUF START set-up time following a 4.0 − − µs
STOP
tHD;STA START hold time 4.0 − − µs
tSU;STA START set-up time following a 4.0 − − µs
clock LOW-to-HIGH transition
Notes
1. This current is the maximum allowed into the inputs when line and field flyback signals are connected to these inputs.
Series current limiting resistors must be used to limit the input currents to ±1 mA.
2. Voltage level VOH for R, G and B outputs is taken to be the mean value during the output HIGH time. If higher R, G
and B voltage VOH levels are required RGBREF voltage level may be raised and a pull-up resistor used at each of
these pins provided current specification (IOL) is not exceeded.

1996 Nov 04 12
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

handbook, full pagewidth

SDA

t BUF t LOW tf

SCL

t HD;STA t HIGH
tr
t HD;DAT
t SU;DAT

SDA

MBC764
t SU;STA
t SU;STO

Fig.5 I2C-bus timing.

TIMING CHAIN

LSP
handbook, full pagewidth
(TCS)
0 4.66 64 µs
40 µs

R, G, B, Y
display period
(1)

0 16.67 56.67 µs

lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced)

R, G, B, Y
(1) display period

0 41 291 312
line numbers
MLA662 - 1

(1) Also BLAN in character and box blanking.

Fig.6 Display output timing (a) line rate (b) field rate.

1996 Nov 04 13
 0 4.66 64 µs

1996 Nov 04
LSP
(Line Sync Pulse)

64 µs
Philips Semiconductors

0 2.33 32 34.33

EP
(Equalizing Pulse)

0 27.33 32 59.33 64 µs

BP
(Broad Pulse)
Teletext decoder (IVT1.8*)

621 622 623 624 625

(308) (309) (310) (311) (312) 1 2 3 4 5 6 7
Integrated Video input processor and

TCS interlaced

14
309 310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) 320 (7)

TCS interlaced

308 309 310 311 312 1 2 3 4 5 6 7

TCS non-interlaced

MLA037 - 2

LSP, EP and BP are combined to give TCS as shown. All timings are measured from falling edge of LSP.
Line numbers placed in the middle of the line.
handbook, full pagewidth

Equivalent count numbers in brackets.

Fig.7 Composite sync waveforms.

SAA5281
Preliminary specification
 FIRST FIELD START (EVEN)
621 622 623 624 625
(308) (309) (310) (311) (312) 1 2 3 4 5 6 7

1996 Nov 04
TCS interlaced
Philips Semiconductors

ODD / EVEN output

(normal sync mode) 2 µs

ODD / EVEN output

(normal sync mode 48 µs
when VCS to SCS
mode active)
Teletext decoder (IVT1.8*)

ODD / EVEN output 30 µs (1)

(slave sync mode)

SECOND FIELD START (ODD)

Integrated Video input processor and

309 310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) 320 (7)

15
TCS interlaced

ODD / EVEN output 2 µs

(normal sync mode)

ODD / EVEN output

(normal sync mode
when VCS to SCS 16 µs
mode active)

ODD / EVEN output

(slave sync mode) 30 µs (1)

MLA416 - 2

Line numbers placed in the middle of the line.

Equivalent count numbers in brackets.
(1) Or 62 µs if Register 1 D2.D1.D0 equals 1 1 1.
handbook, full pagewidth

Fig.8 ODD/EVEN timing.

SAA5281
Preliminary specification
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

ON-CHIP MEMORY
Page memory organization
The organization of the page memory is illustrated by Fig.9. The IVT1.8* provides an additional row as compared with
first generation decoders; this brings the display format up to 40 characters by 25 rows. Rows 0 to 23 form the teletext
page; row 24 is the extra row available for software generated status messages and FLOF/FASTEXT prompt
information.

handbook, full pagewidth

fixed character
written by IVT hardware:
alphanumerics white for normal; 8 characters
7 characters alphanumerics green when looking always rolling
for status for display page (time)
ROW
7 1 24 8 0
1
24 characters from page header 2
rolling when display page looked for 3
4

MAIN PAGE DISPLAY AREA

5
to
20

21
PACKET X / 22 22
PACKET X / 23 23
PACKET X / 24 STORED HERE IF R0D7 = 1 24
10 14 25
10 bytes for if enabled 14 bytes reserved in
MBD789
received chapter 5 for VPS data
page information

Fig.9 Basic page memory organization.

REMARK TO Fig.9 Row 25

Row 0 The first 10 bytes of row 25 contain control data relating to
the received page as shown in Table 5. The remaining
Row 0 is for the page header. The first seven characters
14 bytes are free for use by the microcomputer.
(0 to 6) are free for status messages. Character 8 is an
alphanumeric white or green control character, written
automatically by IVT1.8* to give a green rolling header
when a page is being looked for. The last eight characters
are for rolling time.

1996 Nov 04 16
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Table 5 Row 25 received control data format

ROW 25
D0 PU0 PT0 MU0 MT0 HU0 HT0 C7 C11 MAG0 0
D1 PU1 PT1 MU1 MT1 HU1 HT1 C8 C12 MAG1 0
D2 PU2 PT2 MU2 MT2 HU2 C5 C9 C13 MAG2 0
D3 PU3 PT3 MU3 C4 HU3 C6 C10 C14 0 0
D4 HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER FOUND 0
D5 0 0 0 0 0 0 0 0 0 PBLF
D6 0 0 0 0 0 0 0 0 0 0
D7 0 0 0 0 0 0 0 0 0 0
Column 0 1 2 3 4 5 6 7 8 9

Table 6 Page number and sub-code for Table 5

BIT NAME DESCRIPTION
Page number
MAG magazine
PU page units
PT page tens
PBLF page being looked for
FOUND LOW for page has been found
HAM.ER Hamming error in corresponding byte
Page sub-code
MU minutes units
MT minutes tens
HU hours units
HT hours tens
C4 to C14 transmitted control bits

1996 Nov 04 17
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Extension packet memory organization

When in normal extension packet enabled mode the rows of information are organized as illustrated in Fig.10.
Row 23 of the extension page, as shown in Fig.10, contains packet 8/30. Packet 8/30 is mapped into the IVT1.8* memory
as follows:
8 / 30 / 0 and 8 / 30 / 1 to Chapter 4 Row 23
8 / 30 / 2 and 8 / 30 / 3 to Chapter 5 Row 23
8 / 30 / 4 to 8 / 30 / 15 to Chapter 6 Row 23.

ROW
handbook, full pagewidth

0
PACKETS X/26/0 to X/26/14 to
14

PACKET X/28/2 15
16
PACKETS X/27/0 to X/27/1
17
18
PACKETS X/27/4 to X/27/5
19
PACKET X/24 IF R0D7 = 0 20
PACKET X/25 21
PACKET X/28/0 22
PACKET 8/30 23
PACKET X/28/1 24

RESERVED (1) 25

MBD791

(1) Row 25 reserved for VPS data in Chapter 5.

Fig.10 Organization of the extension memory.

1996 Nov 04 18
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

ENHANCED MODE
In enhanced mode, the number of extension packets captured is reduced to the minimum required for FASTEXT
operation. The first seven chapters can then be used for storage, using the system of pointers. The arrangement of
extension packets is shown in Fig.11.
When in enhanced mode and extension packets are disabled, normal 8-page mode is in operation, but the X/26 engine
is enabled (unlike normal 8-page mode).

handbook, halfpage ROW

CHAPTER 0 PACKET 24 0
CHAPTER 0 PACKETS 27 / 0 1
CHAPTER 1 PACKET 24 2
CHAPTER 1 PACKETS 27 / 0 3
CHAPTER 2 PACKET 24 4
CHAPTER 2 PACKETS 27 / 0 5
CHAPTER 3 PACKET 24 6
CHAPTER 3 PACKETS 27 / 0 7
CHAPTER 4 PACKET 24 8
CHAPTER 4 PACKETS 27 / 0 9
CHAPTER 5 PACKET 24 10
CHAPTER 5 PACKETS 27 / 0 11
CHAPTER 6 PACKET 24 12
CHAPTER 6 PACKETS 27 / 0 13
not used 14
not used 15
PACKETS 8 / 30 / 0,1 16
PACKETS 8 / 30 / 2,3 17
PACKETS 8 / 30 / 4 to 15 18
not used 19 to 24
MBD788

Fig.11 Organization of the extension memory in enhanced mode.

1996 Nov 04 19
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

VPT data memory organization They are Word 15 (reserved) and Word 4 (Program
Source Identification, ASCII sequential) which may be
To simplify the software for dual-standard VPT decoders,
useful for future applications. Details of the memory
the VPS data from line 16 is stored in row 25 of Chapter 5
organization are shown in Fig.12.
of the page memory, and is aligned to match the
packet 8/30 format 2 data as far as possible. The 8/30 The stored data can be read from memory via the I2C-bus
format 2 packet is Hamming coded and by setting the in the normal way. Multiple reception/majority error
appropriate register control bit the data is stored after correction of the VPS data is the responsibility of the
hardware Hamming correction. There are 4 data bits control software, the device simply stores the data as
stored in each column address of memory with an transmitted after biphase decoding.
additional Hamming error bit. The data equivalent to the
As both VPS and 8/30/2 signals are stored in separate
VPS signal is found in columns 12 to 19.
memory locations, it is possible to deal with future
Although the VPS data is not Hamming protected, it is situations where both System A and System B
stored with 4 data bits per column address in the same transmissions may be present on the same TV channel,
way with an additional biphase error bit. The extra space the defaults and level of service chosen by the control
in Row 25 is allocated to two more Line 16 words. software.

handbook, full pagewidth

column 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

8/30/2 D initial page b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25

VPS received page information B11 B12 B13 B14 B15

column 20 21 22 23 24 25 26 27 28 29 30 11 12 13 14 15 16 17 18 19

8/30/2 status display

VPS B4 B5 MBD787

Fig.12 Detailed memory organization.

1996 Nov 04 20
 Register maps
IVT1.8* mode registers R0 to R13 are shown in Table 7. R0 to R10, R12 and R13 are WRITE only; R11 is READ/WRITE, R11B is read only.
Register map (R3), for page requests, is shown in detail in Table 11.

1996 Nov 04
Table 7 Register map (notes 1 to 4)

REGISTER
D7 D6 D5 D4 D3 D2 D1 D0
Philips Semiconductors

NAME No.
Advanced control 0 X/24 POS FREE RUN AUTO DISABLE CBB SLAVE DISABLE VCR MODE R11/R11B
PLL ODD/EVEN HDR ROLL SYNC ODD/EVEN SELECT
Mode 1 VCS TO SCS 7 + P/ 8-BIT ACQ ON/OFF EXT PKT DEW/ FULL TCS ON T1 T0
ENABLE FIELD
Page request 2 HAM CHECK BANK ACQ CCT A1 ACQ CCT A0 0 SC2 SC1 SC0
Teletext decoder (IVT1.8*)

address 27, 8/30 SELECT A2

Page request data 3 − − − PRD4 PRD3 PRD2 PRD1 PRD0
Display chapter 4 − − − − FREEZE A2 A1 A0
HEADER
ONLY
Integrated Video input processor and

Display control 5 BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PON OUT PON IN

21
(normal)
Display control 6 BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PON OUT PON IN
(newsflash /subtitle)
Display mode 7 STATUS CURSOR ON CONCEAL/ TOP/BTM SINGLE/ BOX ON 24 BOX ON 1 BOX ON 0
BTM/TOP REVEAL ON HALF DOUBLE to 23
HEIGHT
Active chapter 8 − − − VPS ENABLE CLEAR MEM A2 A1 A0
Cursor row 9 − − − R4 R3 R2 R1 R0
Cursor column 10 − − C5 C4 C3 C2 C1 C0
Cursor data 11 D7 D6 D5 D4 D3 D2 D1 D0
Device status 11B 625/525 ROM VER R4 ROM VER R3 ROM VER R2 ROM VER ROM TEXT VCS
SYNC R1 VER R0 SIGNAL SIGNAL
QUALITY QUALITY
Advanced control 2A 12 H3 H2 H1 H0 S3 S2 S1 S0
Advanced control 2B 13 ENHANC CURSOR MESHING VPS ENABLE POINTS HAM DISABLE AUTO
MODE FREEZE/ ENABLE ENABLE CHECK PKT X/26 DISPLAY
DEVICE 24 : 18 PKT X/24
SAA5281

IDENT
Preliminary specification
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Notes to Table 7
1. The dash (−) indicates these bits are inactive and must be written to logic 0 for future compatibility.
2. Certain registers are auto-incremented following an I2C-bus transmission byte. These are Register R0 to R3,
R4 to R7 and R8 to R12 or R13.
3. All bits in Registers R0 to R13 are cleared to logic 0 on power-up except bits D0 and D1 of Registers R1, R5 and R6
which are set to logic 1.
4. All memory is cleared to space (00100000) on power-up, except Row 0 Column 7 Chapter 0, which is alpha white
(00000111) as the acquisition circuit is enabled but all pages are on hold.

Table 8 Register description

REGISTER BIT D0 TO D7 FUNCTION
R0 AVANCED CONTROL - auto-increments to Register 1
R11/R11B SELECT Selects reading of R11 if LOW or R11B if HIGH.
VCR MODE If logic 1 selects short time constant mode of PLL.
DISABLE ODD/EVEN Forces ODD/EVEN output LOW when logic 1 (see Table 9).
CBB SLAVE SYNC When set will modify internal slave sync timing to allow connection to sandcastle of
Philips one-chip TV IC (TDA8362).
DISABLE HDR ROLL Stops the display update of rolling time and green rolling header during page
requests when logic 1. Time updates on page reception only.
AUTO ODD/EVEN If logic 1 then ODD/EVEN output only active when no TV picture displayed
(see Table 9).
FREE RUN PLL Will force the display PLL to free run at 6 MHz when logic 1.
X/24 POS Automatic display of FASTEXT prompt row when logic 1. Will also cause Row 24
data transmitted by packet 26 to be written to display, rather than extension
memory.
R1 MODE - auto-increments to Register 2
T0, T1 Interlace/non-interlace 312/313 line control (see Table 10).
TCS ON Text composite sync or direct sync select (see Table 10 for FFB mode selection).
DEW/FULL FIELD Field-flyback or full-channel mode.
EXT PKT ENABLE Enables reception and storage of extension packets when logic 1.
ACQ ON/OFF Acquisition circuits turned off when logic 1.
7 + P/8-BIT 7 bits with parity checking or 8-bit mode.
VCS TO SCS Connects VCS from video sync separator to display field sync detector to enable
stable display of 60 Hz status messages when logic 1.
R2 PAGE REQUEST ADDRESS - auto-increments to Register 3
SC0 to SC2 Start column for page request data (see Table 11).
0 Must be logic 0 for normal operation.
ACQ CCT A0, A1 Selects one of four acquisition circuits.
BANK SELECT A2 Selects bank of four pages being addressed for acquisition.
HAM CHECK 27, 8/30 8/4 Hamming check packet 27 and 8/30 data.
R3 PAGE REQUEST DATA - does not auto-increment
PRD0 to PRD4 See Table 11.

1996 Nov 04 22
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

REGISTER BIT D0 TO D7 FUNCTION

R4 DISPLAY CHAPTER - auto-increments to Register 5
A0 to A2 Selects one of 8 display chapters.
FREEZE HEADER ONLY Freezes the rolling header, but (unlike R0D4) allows the time to roll.
R5 NORMAL DISPLAY CONTROL - auto-increments to Register 6
R6 NEWSFLASH/SUBTITLE DISPLAY CONTROL - auto-increments to Register 7; note 1
PON Picture on.
TEXT Text on.
COR Contrast reduction on.
BKGND Background colour on.
R7 DISPLAY MODE - does not auto-increment
BOX ON 0 Boxing function allowed on Row 0.
BOX ON 1 to 23 Boxing function allowed on Rows1 to 23.
BOX ON 24 Boxing function allowed on Row 24.
SINGLE/DOUBLE HEIGHT To display double height text.
TOP/BTM HALF To select bottom half of page when DOUBLE HEIGHT is logic 1.
CONCEAL/REVEAL ON To reveal concealed text.
CURSOR ON To display cursor.
STATUS BTM/TOP Row 25 displayed above or below the main text.
R8 ACTIVE CHAPTER - auto-increments to Register 9
A0 to A2 Active chapter for data written to or read from memory via the I2C-bus.
CLEAR MEM When set to logic 1, clears the display memory. This bit is automatically reset.
VPS ENABLE VPS acquisition enabled when logic 1.
R9 CURSOR ROW - auto-increments to Register 10
R0 to R4 Active row for data written to or read from memory via the I2C-bus.
R10 CURSOR COLUMN - auto-increments to Register 11 or 11B
C0 to C5 Active column for data written to or read from memory via the I2C-bus.
R11 CURSOR DATA - does not auto-increment
D0 to D7 Data read from/written to memory via I2C-bus, at location pointed to by R9 and
R10. This location automatically increments each time R11 is accessed.
R11B DEVICE STATUS - does not auto-increment
VCS SIGNAL QUALITY Indicates that the video signal quality is good and PLL is phase-locked to input
video when logic 1.
TEXT SIGNAL QUALITY If a good teletext signal is being received then logic 1.
ROM VER R0 to R4 Indicated language/ROM variant. For Western European is logic 0. R3 and R4 are
set HIGH if R13 D6 is logic 1.
625/525 SYNC If the input video is a 525 line signal then logic 1.
R12 ADVANCED CONTROL 2A - does not auto-increment
S0 to S3, H0 to H3 Each acquisition channel can be programmed to process its page in one of four
ways as shown in Table 12.

1996 Nov 04 23
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

REGISTER BIT D0 TO D7 FUNCTION

R13 ADVANCED CONTROL 2B - does not auto-increment
AUTO DISPLAY PKT X/24 Status row will show the contents of the row of the extension memory (packet 24)
when logic 1.
DISABLE PKT X/26 Output taken from processing engine written to the display memory when logic 0.
Operates independent of the acquisition.
HAM CHECK 24 : 18 When logic 1 all packet 26 data is stored in extension memory unchecked.
POINTS ENABLE Enable for acquisition pointers when logic 1.
VPS ENABLE VPS acquisition enabled when logic 1.
MESHING ENABLE Enables meshing display function in box mode.
CURSOR FREEZE/ When logic 1, cursor position not updated even if active row and column change.
DEVICE IDENT This bit will also cause R3 and R4 of the ROM code in Register R11B to be set
HIGH. This allows software to identify the device as an IVT1.8*. An internal ‘1.8
mode’ flag is also set, which enables the operation of R0D4, R4D4 and the subtitle
bit in R3.
ENHANC MODE When logic 1, extension packet data is mapped into the last chapter. Only packet
24, 27/0 and 8/30 are stored. Chapters 0 to 6 can then be used for page storage. If
extension packets are not enabled, 8 pages are stored as normal, but X/26 engine
is enabled.
Note
1. These functions have IN and OUT referring to inside and outside the boxing function respectively.

Table 9 ODD/EVEN selection

AUTO DISABLE
RESULT
ODD/EVEN ODD/EVEN
0 0 ODD/EVEN output continuous
0 1 ODD/EVEN statically LOW
1 1 ODD/EVEN active only when no TV picture displayed
1 1 DV output to indicate reception of error-free 8/30/format 2 packet or VPS line

Table 10 Interlace/non-interlace 312/313 line control and ODD/EVEN field detection option

TCS ON
T1 T0 RESULT
FFB MODE(1)
X 0 0 interlaced 312.5/312.5 lines
X 0 1 non-interlaced 312/313 lines (note 2)
X 1 0 non-interlaced 312/313 lines (note 2)
0 1 1 SCS (scan composite sync) mode: FFB leading edge in first broad pulse of field
1 1 1 SCS (scan composite sync) mode: FFB leading edge in second broad pulse of field

Notes
1. X = don't care.
2. Reverts to interlaced mode if a newsflash or subtitle is being displayed.

1996 Nov 04 24
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Table 11 Register map for page requests (R3); notes 1 to 6

START
PRD4 PRD3 PRD2 PRD1 PRD0
COLUMN
0 DO CARE
Magazine HOLD MAG2 MAG1 MAG0
1 DO CARE
Page tens PT3 PT2 PT1 PT0
2 DO CARE
Page units PU3 PU2 PU1 PU0
3 DO CARE
Hours tens SUBTITLE X HT1 HT0
4 DO CARE
Hours units HU3 HU2 HU1 HU0
5 DO CARE
Minutes tens X MT2 MT1 MT0
6 DO CARE
Minutes units MU3 MU2 MU1 MU0
7 X X CH2 CH1 CH0

Notes
1. Abbreviations are as given in Table 6 except for DO CARE bits and CH = chapter address for acquisition chapter.
2. When the DO CARE bit is set to logic 1 this means the corresponding digit is to be taken into account for page
requests. If the DO CARE bit is set to logic 0 the digit is ignored. This allows, for example, normal or timed page
selection.
3. If HOLD is set LOW, the page is held and not updated.
4. Columns auto-increment on successive I2C-bus transmission bytes.
5. The SUBTITLE bit is only present when the device is in ‘1.8 mode’ (i.e. R13D6 has been set HIGH).
6. X = don’t care.

Table 12 Acquisition channel programming

H0 to H3(1) S0 to S3(1) CHECKING ALGORITHM FOR ACQUISITION CHANNEL X

0 0 7-bit + parity for whole page
0 1 8-bit for whole page
1 0 8/4 Hamming check for whole page
mixed 8/4 Hamming (columns 0 to 7, 20 to 27) and 7-bit + parity
1 1
(columns 8 to 19, 28 to 39)

Note
1. These register bits operate in conjunction with 7 + P/ 8-BIT (Register 1, Bit D6) which will over-ride the choice of data
checker if set, setting all channels to 8-bit only. If this bit is not set H0 to H3 and S0 to S3 will determine the data
checking (default to 7-bit + parity).

1996 Nov 04 25
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

CLOCK SYSTEMS frequency, and reduces the power dissipation in the quartz
crystal. It is capable of oscillating with both fundamental
Crystal oscillator
and third overtone mode crystals. External components
The crystal is a conventional Colpitts 3-pin design should be used to suppress the fundamental output of the
operating at 27 MHz. The oscillator is sinusoidal and third overtone as illustrated in Fig.13. The crystal
linear, with a controlled output amplitude. This reduces the characteristics are given in Table 13.
radiated and conducted level of the 27 MHz fundamental

handbook, full pagewidth

VDD1
1 (52) SAA5281

OSCOUT 2 (1)
15 pF 8.2 pF 100 nF
CRYSTAL
OSCILLATOR
1 nF 3.3 µH
OSCIN 3 (2)

27 MHz
3.3 kΩ 3rd
overtone OSCGND
4 (3)

MBD786

Fig.13 Crystal oscillator application diagram for SOT240-1; pins in parenthesis are for SOT247-1.

Table 13 Crystal characteristics (see Fig.13)

SYMBOL PARAMETER TYP. MAX. UNIT

Crystal (27 MHz, 3rd overtone)
C1 series capacitance 1.7 − pF
C0 parallel capacitance 5.2 − pF
CL load capacitance 20 − pF
Rr resonance resistance − 50 Ω
R1 series resistance 20 − Ω
Xa ageing − ±5 × 10−6 year−1
Xj adjustment tolerance − ±25 × 10−6
Xd drift − ±25 × 10−6

1996 Nov 04 26
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

CHARACTER SETS Meshing

The WST specification allows the selection of national This is an alternative method of displaying teletext
character sets via the page header transmission bits, subtitles, or similar boxed text superimposed on the TV
C12 to C14. The basic 96 character sets differ only in picture and operates by showing reduced contrast TV
13 national option characters as indicated in the pictures in place of the (black) background within the
Tables 21, 22 and 23 with reference to their table position boxed area. The Meshing effect is produced by toggling
in the basic character matrix illustrated in Table 20. the BLAN signal from IVT at pixel rate. By starting at the
The IVT1.8* automatically decodes transmission bits same point each field, and toggling the start position each
C12 to C14. Tables 14, 15 and 16 illustrate the character line, a chequered pattern will result. This allows movement
matrixes. to be seen behind the text information. The MESH
OFF/ON bit in Register 13 D5 controls this function.
Character bytes are listed as transmitted from b1 to b7.
Normally at zero, compatibility with IVT1.0 is maintained.

MLA663
handbook, full pagewidth

alphanumerics and alphanumerics alphanumerics or alphanumerics

graphics 'space' character blast-through character
character 1011010 alphanumerics 1111111
0000010 character
0001001

contiguous separated separated contiguous

graphics character graphics character graphics character graphics character
0110111 0110111 1111111 1111111
background display
= colour = colour

Fig.14 Character format.

1996 Nov 04 27
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Table 14 SAA5281P/E character data input decoding, West European languages; notes 1 to 9
For character version number (11000) see Register 11B.

handbook, full
B pagewidth
b8 0 0 0 or 1 0 0 or 1 0 0 0 0 0 1 1 1 1 1 1
I
T b7 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1
S b6 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1
b5 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1
b 4 b 3 b2 b 1
column
r 0 1 2 2a 3 3a 4 5 6 6a 7 7a 8 9 12 13 14 15
o
w alpha -
numerics graphics
0 0 0 0 0
black black

alpha -
graphics
0 0 0 1 1 numerics
red
red

alpha - graphics
0 0 1 0 2 numerics green
green

alpha - graphics
0 0 1 1 3 numerics yellow
yellow

alpha -
graphics
0 1 0 0 4 numerics
blue
blue

alpha -
graphics
0 1 0 1 5 numerics
magenta
magenta

alpha -
graphics
0 1 1 0 6 numerics
cyan cyan

(2)
alpha - graphics
0 1 1 1 7 numerics white
white

conceal
1 0 0 0 8 flash display

(2) (2)
contiguous
1 0 0 1 9 steady
graphics

(2)
separated
1 0 1 0 10 end box
graphics

(1)

1 0 1 1 11 start box ESC

(2) (2)
normal black
1 1 0 0 12 back -
height
ground

new
double back -
1 1 0 1 13 height ground
(1)
hold
1 1 1 0 14 SO graphics

(1) (2)
release
1 1 1 1 15 SI graphics

MBA429

1996 Nov 04 28
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Table 15 SAA5281P/H character data input decoding, East European languages; notes 1 to 9
For character version number (11001) see Register 11B.

handbook, full
B pagewidth
b8 0 0 0 or 1 0 0 or 1 0 0 0 0 0 1 1 1 1 1 1
I
T b7 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1
S b6 0 0 1 1 1 1 0 0 1 0 0 0 0 1 1
1
b5 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1
b b b b
4 3 2 1
column
r 0 1 2 2a 3 3a 4 5 6 6a 7 7a 8 9 12 13 14 15
o
w alpha -
numerics graphics
0 0 0 0 0 black
black

alpha -
numerics graphics
0 0 0 1 1 red
red

alpha - graphics
0 0 1 0 2 numerics green
green

alpha - graphics
0 0 1 1 3 numerics yellow
yellow

alpha -
numerics graphics
0 1 0 0 4 blue
blue

alpha - graphics
0 1 0 1 5 numerics magenta
magenta

alpha -
graphics
0 1 1 0 6 numerics
cyan cyan

(2)
alpha - graphics
0 1 1 1 7 numerics white
white

conceal
1 0 0 0 8 flash display

(2) (2)

1 0 0 1 9 steady contiguous
graphics

(2)
separated
1 0 1 0 10 end box graphics

(1)
1 0 1 1 11 start box ESC

(2) (2)
normal black
1 1 0 0 12 back -
height
ground

new
double back -
1 1 0 1 13
height ground
(1)
hold
1 1 1 0 14 SO
graphics

(1) (2)
release
1 1 1 1 15 SI graphics

MLA961

1996 Nov 04 29
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Table 16 SAA5281P/T character data input decoding, West European and Turkish languages; notes 1 to 9
For character version number (11010) see Register 11B.

handbook, full
B pagewidth
b8 0 0 0 or 1 0 0 or 1 0 0 0 0 0 1 1 1 1 1 1
I
T b7 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1
S b6 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1
b5 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1
b 4 b 3 b2 b 1
column
r 0 1 2 2a 3 3a 4 5 6 6a 7 7a 8 9 12 13 14 15
o
w alpha -
numerics graphics
0 0 0 0 0
black black

alpha -
graphics
0 0 0 1 1 numerics
red
red

alpha - graphics
0 0 1 0 2 numerics green
green

alpha - graphics
0 0 1 1 3 numerics yellow
yellow

alpha -
graphics
0 1 0 0 4 numerics
blue
blue

alpha -
graphics
0 1 0 1 5 numerics
magenta
magenta

alpha -
graphics
0 1 1 0 6 numerics
cyan cyan

(2)
alpha - graphics
0 1 1 1 7 numerics white
white

conceal
1 0 0 0 8 flash display

(2) (2)
contiguous
1 0 0 1 9 steady
graphics

(2)
separated
1 0 1 0 10 end box
graphics

(1)
1 0 1 1 11 start box ESC

(2) (2)
normal black
1 1 0 0 12 back -
height
ground

new
double back -
1 1 0 1 13 height ground
(1)
hold
1 1 1 0 14 SO graphics

(1) (2)
release
1 1 1 1 15 SI graphics

MBA431

1996 Nov 04 30
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Table 17 SAA5281P/R character data input decoding, Baltic and Cyrillic languages; notes 1 to 9
For character version number (00101) see Register 11B.

B b8 0 0 0 or 1 0 0 or 1 0 0 0 0 0 1 1 1 1 1 1
I
T b7 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1
S b6 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1
b5 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1
b b b b
4 3 2 1
column
r 0 1 2 2a 3 3a 4 5 6 6a 7 7a 8 9 12 13 14 15
o
w alpha -
graphics
0 0 0 0 0 numerics
black
black

alpha - graphics
0 0 0 1 1 numerics
red
red

alpha - graphics
0 0 1 0 2 numerics green
green

alpha - graphics
0 0 1 1 3 numerics yellow
yellow

alpha -
numerics graphics
0 1 0 0 4
blue blue

alpha - graphics
0 1 0 1 5 numerics magenta
magenta

alpha -
handbook, full pagewidth numerics graphics
0 1 1 0 6 cyan
cyan
(2)
alpha - graphics
0 1 1 1 7 numerics white
white

conceal
1 0 0 0 8 flash display

(2) (2)

1 0 0 1 9 steady contiguous
graphics

(2)
separated
1 0 1 0 10 end box
graphics

1 0 1 1 11 start box TWIST

(2) (2)
black
1 1 0 0 12 normal
back -
height
ground

new
double back -
1 1 0 1 13 height ground

(1)
hold
1 1 1 0 14 SO
graphics

(1) (2)
release
1 1 1 1 15 SI graphics

MBA648 - 1

1996 Nov 04 31
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Table 18 SAA5281P/L character data input decoding, Arabic and Hebrew languages; notes 1 to 9
For character version number (00100) see Register 11B.

B b8 0 0 0 or 1 0 0 or 1 0 0 0 0 0 or 1 0 0 or 1 1 1 1 1 1 1
I
T b7 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1
S b6 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1
b5 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1
b b b b
4 3 2 1
column
r 0 1 2 2a 3 3a 4 5 6 6a 7 7a 8 9 12 13 14 15
o
w alpha -
graphics
0 0 0 0 0 numerics
black black

alpha -
graphics
0 0 0 1 1 numerics
red red

alpha - graphics
0 0 1 0 2 numerics green
green

alpha - graphics
0 0 1 1 3 numerics yellow
yellow

alpha -
4 numerics graphics
0 1 0 0
blue blue

alpha - graphics
0 1 0 1 5 numerics magenta
magenta

alpha -
handbook, full 0pagewidth numerics graphics
1 1 0 6 cyan
cyan
(2)
alpha - graphics
0 1 1 1 7 numerics white
white

conceal
1 0 0 0 8 flash display

(2) (2)
1 0 0 1 9 steady contiguous
graphics

(2)
separated
1 0 1 0 10 end box graphics

1 0 1 1 11 start box TWIST

(2) (2)
black
1 1 0 0 12 normal
back -
height
ground

new
double back -
1 1 0 1 13 height ground
(1)
hold
1 1 1 0 14 SO
graphics

(1) (2)
release
1 1 1 1 15 SI graphics

MLA963 - 1

1996 Nov 04 32
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Table 19 SAA5281P/K character data input decoding, French and Arabic languages; notes 1 to 9
For character version number (00100) see Register 11B.

B b8 0 0 0 or 1 0 0 or 1 0 0 0 0 0 or 1 0 0 or 1 1 1 1 1 1 1
I
T b7 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1
S b6 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1
b5 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1
b b b b
4 3 2 1
column
r 0 1 2 2a 3 3a 4 5 6 6a 7 7a 8 9 12 13 14 15
o
w alpha -
numerics graphics
0 0 0 0 0 black
black

alpha -
numerics graphics
0 0 0 1 1 red
red

alpha - graphics
0 0 1 0 2 numerics green
green

alpha - graphics
0 0 1 1 3 numerics yellow
yellow

alpha -
numerics graphics
0 1 0 0 4 blue
blue

alpha - graphics
0 1 0 1 5 numerics magenta
magenta

alpha -
graphics
handbook, full0 pagewidth
1 1 0 6 numerics
cyan cyan

(2)
alpha - graphics
0 1 1 1 7 numerics white
white

conceal
1 0 0 0 8 flash display

(2) (2)

1 0 0 1 9 steady contiguous
graphics

(2)
separated
1 0 1 0 10 end box graphics

1 0 1 1 11 start box TWIST

(2) (2)
normal black
1 1 0 0 12 back -
height
ground

new
double back -
1 1 0 1 13
height ground

(1)
hold
1 1 1 0 14 SO graphics

(1) (2)
release
1 1 1 1 15 SI
graphics

MLA972 - 1

1996 Nov 04 33
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Notes to Tables 14, 15, 16, 17, 18 and 19

1. These control characters are reserved for compatibility with other data codes.
2. These control characters are presumed before each row begins.
3. Control characters shown in Columns 0 and 1 are normally displayed as spaces.
4. Characters may be referred to by column and row (for example 2/5 refers to %).
5. Black represents displayed colour. White represents background.
6. The SAA5281 national option characters are illustrated in Tables 21, 22 and 23.
7. Characters 8/6, 8/7, 9/5, 9/6 and 9/7 are special characters for combining with character 8/5 (E, H and T codes only).
Characters 5/12, 5/13, 5/14 and 5/15 are combined with 5/11 (S code only).
8. National option characters will be displayed according to the setting of control bits C12 to C14. These will be mapped
into the basic code table into positions shown in Tables 21, 22 and 23.
9. Columns 2a, 3a, 6a and 7a are displayed in graphics mode.

1996 Nov 04 34
 Table 20 SAA5281 basic character matrix; note 1

1996 Nov 04
2/0 2/8 3/0 3/8 4/0 4/8 5/0 5/8 6/0 6/8 7/0 7/8

NC NC
Philips Semiconductors

2/1 2/9 3/1 3/9 4/1 4/9 5/1 5/9 6/1 6/9 7/1 7/9

2/2 2/10 3/2 3/10 4/2 4/10 5/2 5/10 6/2 6/10 7/2 7/10
Teletext decoder (IVT1.8*)

2/3 2/11 3/3 3/11 4/3 4/11 5/3 5/11 6/3 6/11 7/3 7/11

NC NC NC
Integrated Video input processor and

2/4 2/12 3/4 3/12 4/4 4/12 5/4 5/12 6/4 6/12 7/4 7/12

35
NC NC NC

2/5 2/13 3/5 3/13 4/5 4/13 5/5 5/13 6/5 6/13 7/5 7/13

NC NC

2/6 2/14 3/6 3/14 4/6 4/14 5/6 5/14 6/6 7/6 7/14

NC NC

2/7 2/15 3/7 3/15 4/7 4/15 5/7 5/15 6/7 6/15 7/7 7/15

NC

MLA630
full pagewidth

Note
SAA5281

1. Where NC = national option character position.

Preliminary specification
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Table 21 SAA5281P/E national option character set

handbook, full pagewidth (1)

PHCB CHARACTER POSITION (COLUMN / ROW)
LANGUAGE
C12 C13 C14 2 / 3 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6/0 7 / 11 7 / 12 7 / 13 7 / 14

ENGLISH 0 0 0

GERMAN 0 0 1

SWEDISH 0 1 0

ITALIAN 0 1 1

FRENCH 1 0 0

SPANISH 1 0 1

MLB458

(1) PHCB are the Page Header Control Bits. Other combinations default to English.

Table 22 SAA5281P/H national option character set

handbook, full pagewidth (1)

PHCB CHARACTER POSITION (COLUMN / ROW)
LANGUAGE
C12 C13 C14 2 / 3 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6/0 7 / 11 7 / 12 7 / 13 7 / 14

POLISH 0 0 0

GERMAN 0 0 1

SWEDISH 0 1 0

SERBO-CROAT 1 0 1

CZECHOSLOVAKIA 1 1 0

RUMANIAN 1 1 1

MLA966

(1) PHCB are the Page Header Control Bits. Other combinations default to German. Only the above characters change with the PHCB. All other
characters in the basic set are shown in Table 20.

1996 Nov 04 36
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Table 23 SAA5281P/T national option character set

andbook, full pagewidth (1)

PHCB CHARACTER POSITION (COLUMN / ROW)
LANGUAGE
C12 C13 C14 2 / 3 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6/0 7 / 11 7 / 12 7 / 13 7 / 14

ENGLISH 0 0 0

GERMAN 0 0 1

TURKISH 1 1 0

ITALIAN 0 1 1

FRENCH 1 0 0

SPANISH 1 0 1

MBA430

(1) PHCB are the Page Header Control Bits. Other combinations default to English. Only the above characters change with the PHCB. All other
characters in the basic set are shown in Table 20.

1996 Nov 04 37
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Table 24 SAA5281P/R national option character set

handbook, full pagewidth (1)

PHCB CHARACTER POSITION (COLUMN / ROW)
LANGUAGE
C12 C13 C14 2 / 3 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6 / 0 7 / 11 7 / 12 7 / 13 7 / 14

ESTONIAN 0 1 0

LETTISH /
LITHUANIAN 0 1 1

RUSSIAN 1 0 0
2 3 4 5 6 7

10

11

12

13

14

15
MEA597

(1) PHCB are the Page Header Control Bits. Other combinations default to Estonian.

1996 Nov 04 38
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Table 25 SAA5281P/K national option character set

2 3 4 5 6 7 2 3 4 5 6 7

0 0

1 1

2 2

3 3

4 4

5 5

6 6

7 7

handbook, full pagewidth

8 8

9 9

10 10

11 11

12 12

13 13

14 14

15 15

LANGUAGE FRENCH ARABIC

(1)
PHCB
1 0 0 1 1 1
(C12, C13, C14)

MLA968 - 1

(1) PHCB are the Page Header Control Bits. Other combinations default to French.

1996 Nov 04 39
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

Table 26 SAA5281P/L national option character set

2 3 4 5 6 7 2 3 4 5 6 7

0 0

1 1

2 2

3 3

4 4

5 5

6 6

7 7

handbook, full pagewidth

8 8

9 9

10 10

11 11

12 12

13 13

14 14

15 15

LANGUAGE HEBREW/ENGLISH ARABIC

(1)
PHCB
1 0 1 1 1 1
(C12, C13, C14)

MLA967

(1) PHCB are the Page Header Control Bits. Other combinations default to Hebrew English.

1996 Nov 04 40
 5V
handbook, full pagewidth 10 µF 100 nF SDA SCL
22 nF

1 52 1 40

1996 Nov 04
OSCOUT V DD1 P1.0 VDD 5V
15 220 220
8.2 Ω Ω
3.3 µH pF pF 2 39
2 51 P1.1 P0.0
OSCIN i.c.
3.3 27 MHz 3rd 3 38
kΩ overtone P1.2 P0.1
3 50 link
OSCGND i.c. 4.7 kΩ
Philips Semiconductors

options 4 37
4 49 P1.3 P0.2
V SS1 i.c. 5V
5 36
5 48 P1.4
V SS1 i.c. 4.7 kΩ P0.3
100 nF 6
APPLICATION INFORMATION

6 47 35
REF+ LINE 23 LINE 23 P1.5 P0.4
7 46 7 34
n.c. i.c.
100 nF SCL P0.5
8 45
BLACK i.c. 8 33
100 nF SDA P0.6
9 44
Teletext decoder (IVT1.8*)

CVBS CVBS i.c. 1 µF 83C654

9 32
27 kΩ 5V RST P0.7
10 43
IREF i.c.
10 31
11 42 P3.0 EA 5V
5V V DD2 i.c.
100 33 11 30
nF µF PDI P3.1 ALE
12 41
POL i.c.
12 29
13 40 P3.2 PSEN
SYNC STTV/LFB CLK O/P
13 28
Integrated Video input processor and

1.5 kΩ
14 39 PL out P3.3 P2.7
VCR/FFB CLK EN 5V

41
330 nF 14 27
PON P3.4 P2.6
15
SAA5281 38
V SS2 i.c. 15 26
P3.5 P2.5
1 kΩ 16 37
R R i.c. 16 25
P3.6 P2.4
17 36
G G i.c. 17 24
18 35 P3.7 P2.3
B B i.c.
18 23
19 34 XTAL2 P2.2
RGBREF n.c.
20 33 19 22
BLAN BLAN n.c. XTAL1 P2.1
21 32 470 Ω
COR COR i.c. 20 21
V SS P2.0
22 31
ODD/EVEN ODD/EVEN i.c.
23 30
Y i.c.
5V 5V
24 29 1 8
SCL i.c.
25 28
SDA i.c. address 2 7 56
select PCF8572 kΩ
26 27
V SS3 i.c. 3 PCF8582 6

4 5 3.3
nF

MBD790

Fig.15 Application diagram for SDIP52, SOT247-1.

SAA5281
Preliminary specification
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

PACKAGE OUTLINES

DIP48: plastic dual in-line package; 48 leads (600 mil) SOT240-1

seating plane

D ME

A2 A

L A1

c
Z e w M
b1
(e 1)
b
48 25 MH

pin 1 index

1 24

0 5 10 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT
A A1 A2
b b1 c D (1) E (1) e e1 L ME MH w Z (1)
max. min. max. max.
1.4 0.53 0.36 62.60 14.22 3.90 15.88 18.46
mm 4.9 0.36 4.06 2.54 15.24 0.254 2.1
1.14 0.38 0.23 61.60 13.56 3.05 15.24 15.24
0.055 0.021 0.014 2.46 0.56 0.15 0.63 0.73
inches 0.19 0.014 0.16 0.10 0.60 0.01 0.083
0.045 0.015 0.009 2.42 0.53 0.12 0.60 0.60

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION

92-11-17
SOT240-1
95-01-25

1996 Nov 04 42
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

SDIP52: plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1
seating plane

D ME

A2 A

L
A1
c
Z e w M (e 1)
b1
MH

b
52 27

pin 1 index
E

1 26

0 5 10 mm
scale

DIMENSIONS (mm are the original dimensions)

UNIT
A A1 A2
b b1 c D (1) E (1) e e1 L ME MH w Z (1)
max. min. max. max.
1.3 0.53 0.32 47.9 14.0 3.2 15.80 17.15
mm 5.08 0.51 4.0 1.778 15.24 0.18 1.73
0.8 0.40 0.23 47.1 13.7 2.8 15.24 15.90

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION

90-01-22
SOT247-1
95-03-11

1996 Nov 04 43
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT319-2

c
y
X

51 33 A
52 32 ZE

e Q
A2
E HE A
A1 (A 3)

θ
wM
pin 1 index Lp
bp L

64 20 detail X
1 19

w M ZD v M A
e bp

D B
HD v M B

0 5 10 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y Z D (1) Z E (1) θ
o
0.25 2.90 0.50 0.25 20.1 14.1 24.2 18.2 1.0 1.4 1.2 1.2 7
mm 3.20 0.25 1 1.95 0.2 0.2 0.1
0.05 2.65 0.35 0.14 19.9 13.9 23.6 17.6 0.6 1.2 0.8 0.8 0o

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION

92-11-17
SOT319-2
95-02-04

1996 Nov 04 44
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

SOLDERING with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
Introduction
5 seconds.
There is no soldering method that is ideal for all IC
The device may be mounted up to the seating plane, but
packages. Wave soldering is often preferred when
the temperature of the plastic body must not exceed the
through-hole and surface mounted components are mixed
specified maximum storage temperature (Tstg max). If the
on one printed-circuit board. However, wave soldering is
printed-circuit board has been pre-heated, forced cooling
not always suitable for surface mounted ICs, or for
may be necessary immediately after soldering to keep the
printed-circuits with high population densities. In these
temperature within the permissible limit.
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology. Repairing soldered joints
A more in-depth account of soldering ICs can be found in
Apply a low voltage soldering iron (less than 24 V) to the
our “IC Package Databook” (order code 9398 652 90011).
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
Soldering by dipping or by wave
soldering iron bit is less than 300 °C it may remain in
The maximum permissible temperature of the solder is contact for up to 10 seconds. If the bit temperature is
260 °C; solder at this temperature must not be in contact between 300 and 400 °C, contact may be up to 5 seconds.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

1996 Nov 04 45
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

NOTES

1996 Nov 04 46
Philips Semiconductors Preliminary specification

Integrated Video input processor and

SAA5281
Teletext decoder (IVT1.8*)

NOTES

1996 Nov 04 47
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

© Philips Electronics N.V. 1996 SCA52

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Printed in The Netherlands 537021/1200/02/pp48 Date of release: 1996 Nov 04 Document order number: 9397 750 01461