Mixed-Signal-Electronics
PD Dr.-Ing. Stephan Henzler
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Chapter 8
Oversampled Converters
Sigma-Delta Modulator
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Quantization Noise in A/D-Converters
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Linear Model of Quantization Noise
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Quantization Noise and Oversampling
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Quantization Noise and Oversampling
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Quantization Noise and Oversampling
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Feasibility of Oversampling
Goal: Implement ADC (12bit, 44kHz BW) by 1 bit quantizer
with oversampling
12 bit
Same SNR with 1 bit quantizer:
Sampling frequency:
Conclusion: Even medium resolution and low bandwidth
leads to unacceptably high OSR
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Oversampling with Noise Shaping
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First Order Noise Shaping
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First Order Noise Shaping
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1. Order ΣΔ-Modulator
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1. Order ΣΔ-Modulator
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Calculation of Signal-to-Noise Ratio
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Calculation of Signal-to-Noise Ratio
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SC Implementation of 1. Order
ΣΔ Modulator
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Comparison Nyquist Rate vs. SD AD
Nyquist Rate ADCs Sigma Delta ADCs
High voltage domain resolution Low voltage domain resolution
in extreme case only 1 bit
Low time domain resolution High time domain resolution
fs fNyquist ( x 2-10) fs >> fNyquist ( x 64-512)
Low to medium resolution Very high resolution
..(high) up to 20 bit
Result can be directly used Large decimation filter required
One output symbol = one sample One sample distributed over many
output symbols
Medium speed requirements for all Very high speed requirements for
circuit block OpAmps, DAC, etc.
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