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Mixed-Signal-Electronics: PD Dr.-Ing. Stephan Henzler

The document discusses different types of analog-to-digital converter architectures including counting, weighted, and flash operations. It describes the successive approximation register (SAR) converter architecture including its use of a digital-to-analog converter (DAC) and comparator. The document discusses the charge redistribution SAR converter operation in phases of input tracking, holding, and SAR evaluation. It also describes algorithmic analog-to-digital converters that use a constant comparator threshold and voltage increment/decrement amount to double the remainder voltage in each iteration step.

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Ahmed Hamouda
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37 views36 pages

Mixed-Signal-Electronics: PD Dr.-Ing. Stephan Henzler

The document discusses different types of analog-to-digital converter architectures including counting, weighted, and flash operations. It describes the successive approximation register (SAR) converter architecture including its use of a digital-to-analog converter (DAC) and comparator. The document discusses the charge redistribution SAR converter operation in phases of input tracking, holding, and SAR evaluation. It also describes algorithmic analog-to-digital converters that use a constant comparator threshold and voltage increment/decrement amount to double the remainder voltage in each iteration step.

Uploaded by

Ahmed Hamouda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
You are on page 1/ 36

Mixed-Signal-Electronics

PD Dr.-Ing. Stephan Henzler

Stephan Henzler Mixed-Signal-Electronics 2011/12 1


Chapter 6
Nyquist Rate
Analog-to-Digital Converters

Stephan Henzler Mixed-Signal-Electronics 2011/12 2


Analog-to-Digital Converter Families
Architecture Variant Speed Precision
Counting Operation single/dual slope integration low high
Weighted Operation successive approximation
algorithmic converter medium medium
w/wo redundancy, callibration
Flash Operation • direct flash
• multi-stage flash
high low to medium
• interpolating flash
• folding flash
Oversampling -modulation, i.e. noise shaping
• discrete time low to medium high
• continuous time
Time based emerging tbd. tbd.

 Sampling frequency can be further increased by


– pipelining
– time interleaving, i.e. parallelization

Stephan Henzler Mixed-Signal-Electronics 2011/12 3


General ADC Model

Linear model
 often very useful
 limitations as quantization
noise is de-correlated from
signal
 Input signal must change
– sufficiently fast
– sufficiently strong

Stephan Henzler Advanced Integrated Circuit Design 2011/12 4


Dual-Slope Analog-to-Digital Converter

Stephan Henzler Mixed-Signal-Electronics 2011/12 5


Dual-Slope Analog-to-Digital Converter

Stephan Henzler Mixed-Signal-Electronics 2011/12 6


Iterative Analog-to-Digital Converters

Tracking ADC
Successive Approximation ADC
Algorithmic ADC
Pipeline ADC

Stephan Henzler Mixed-Signal-Electronics 2011/12 7


Tracking ADCs

Stephan Henzler Advanced Integrated Circuit Design 2011/12 8


Converter with Successive Approximation
 What would you ask if you had N questions to find out the
approximate value of the input voltage?

1. Is it positive or
negative?

NEGATIVE

2. Is it in the upper or
lower negative region?

UPPER

3. …

Stephan Henzler Mixed-Signal-Electronics 2011/12 9


Converter with Successive Approximation
 This is a binary search technique:
Partition the interval where the input voltage is located in two sub-intervals and
check whether the voltage lies in the upper or lower part

Stephan Henzler Mixed-Signal-Electronics 2011/12 10


Converter with Successive Approximation

Stephan Henzler Mixed-Signal-Electronics 2011/12 11


Converter with Successive Approximation (cont)

 ADC is mainly a DAC and a comparator


(These are the critical building blocks)
 Conversion principle:
Make DAC voltage equal to input voltage, minimize error
 Depending on the voltage comparison the bits in the SAR
register are iteratively set or reset

Stephan Henzler Mixed-Signal-Electronics 2011/12 12


Modified SAR Algorithm

 Also based on binary search


technique

 Comparison against zero

 More suited for


implementation,
e.g. charge redistribution

Stephan Henzler Mixed-Signal-Electronics 2011/12 13


Modified SAR Algorithm

Stephan Henzler Mixed-Signal-Electronics 2011/12 14


Charge Redistribution SAR Converter
Phase I: Input Tracking

Stephan Henzler Mixed-Signal-Electronics 2011/12 15


Charge Redistribution SAR Converter
Phase II: Hold

Stephan Henzler Mixed-Signal-Electronics 2011/12 16


Charge Redistribution SAR Converter
Phase III: SAR Evaluation

Stephan Henzler Mixed-Signal-Electronics 2011/12 17


Charge Redistribution SAR Converter
Phase III: SAR Evaluation

Stephan Henzler Mixed-Signal-Electronics 2011/12 18


Add-On Material

Hybrid SAR Converters


 Search can be done with different
references
 Same idea as for DACs
– monotonous resistor string for MSBs
– binary weighted cap array for LSBs

1. Charge caps to -vin


2. Binary search in resistive
network: vx = -vin + vres
3. Interpolate in between two
subsequent taps of resistor
string by charge redistribution
Stephan Henzler Mixed-Signal-Electronics 2011/12 19
More Details on SAR and Algorithmic ADC
 Architectural Considerations on SAR

 Pipelined SAR

 Redundant SAR Remember:


The goal is to make this
error voltage
equal to zero

Stephan Henzler Advanced Integrated Circuit Design 2011/12 20


Detailed SAR Architecture
 Let’s look at the DAC in detail …

 Thermometer Coding
 Each DAC has same error contribution
 Remainder:

Aaron Buchwald, Pipelined A/D Converters: The Basics, ISSCC 2008

Stephan Henzler Advanced Integrated Circuit Design 2011/12 21


Binary Weighted SAR

 Binary weighting is desirable to reduce number of sub-DACs

 Remainder:

 Error contribution due to DAC mismatch scales with binary


weigting of reference

Stephan Henzler Advanced Integrated Circuit Design 2011/12 22


Binary Weighted SAR

Stephan Henzler Advanced Integrated Circuit Design 2011/12 23


Weighted SAR with Distributed Gain

 Binary weighting can be achieved also by using equal DACs


with a single reference voltage but with gain / scaling
elements
 Due to scaling MSB DAC is most critical
 Linear transformation enables distributed gain

Stephan Henzler Advanced Integrated Circuit Design 2011/12 24


Algorithmic Analog-to-Digital Converter

 Comparator threshold constant

 Voltage increment/decrement
constant

 remainder is doubled in each


iteration step
 accurate x2 circuit required

Stephan Henzler Mixed-Signal-Electronics 2011/12 25


Algorithmic Analog-to-Digital Converter

Stephan Henzler Mixed-Signal-Electronics 2011/12 26


Robertson Diagram

Stephan Henzler Mixed-Signal-Electronics 2011/12 27


Illustration in Robertson Diagram

2. 3. 4.
1. 5.

Stephan Henzler Mixed-Signal-Electronics 2011/12 28


Lecturer Page Version

Algorithmic Analog-to-Digital Converter

ADC

DAC

 Long conversion time


N cycles per inout sample

Stephan Henzler Mixed-Signal-Electronics 2011/12 29


Add-On Material

Voltage Doubling in Algorithmic Converter


V2

V1

 Sample remainder Verr together with opamp offset voltage


 Amplifier configured as voltage follower
 C2 charged to amplifier offset voltage
Stephan Henzler Mixed-Signal-Electronics 2011/12 30
Add-On Material

Voltage Doubling in Algorithmic Converter


V2

V1

 Disconnect input, discharge C1


 Transfer charge of C1 to C2
Stephan Henzler Mixed-Signal-Electronics 2011/12 31
Add-On Material

Voltage Doubling in Algorithmic Converter


V2

V1

 Disconnect C2, charge Q2 unchanged


 Sample input again

Stephan Henzler Mixed-Signal-Electronics 2011/12 32


Add-On Material

Voltage Doubling in Algorithmic Converter


V2

V1

 Combine charge on C1, offset compensated,


 Four clock cycles required!
Stephan Henzler Mixed-Signal-Electronics 2011/12 33
Weighted SAR with Distributed Gain

 Algorithmic converter in unfolded implementation


 Long conversion time
N x TADC + N x TDAC
 Speed-up by insertion of ADC and S&H in each stage
 pipelining: high throughput at the price of latency

Stephan Henzler Advanced Integrated Circuit Design 2011/12 34


Pipelined ADC 1

 Going for pipelined-ADC means


– cut the feed-back loop
– add a sample-and hold at the output of each stage to store
the remainder, i.e. the stage quantization error
– add a comparator, i.e. coarse ADC at input of each stage

Stephan Henzler Advanced Integrated Circuit Design 2011/12 35


Pipelined ADC 2

Stephan Henzler Mixed-Signal-Electronics 2011/12 36

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