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Flip Flops: Digital Logic Design Lab

This document provides information about digital logic design lab covering topics like flip flops, sequential circuits, and different types of flip flops. It discusses that sequential circuits consist of combinational circuits with feedback and are classified as synchronous or asynchronous. Synchronous circuits are clocked using a system clock while asynchronous circuits' output is affected by input changes. It also describes the basic flip flop types including R-S, J-K, D, and T flip flops, explaining their functionality and implementations.

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112 views23 pages

Flip Flops: Digital Logic Design Lab

This document provides information about digital logic design lab covering topics like flip flops, sequential circuits, and different types of flip flops. It discusses that sequential circuits consist of combinational circuits with feedback and are classified as synchronous or asynchronous. Synchronous circuits are clocked using a system clock while asynchronous circuits' output is affected by input changes. It also describes the basic flip flop types including R-S, J-K, D, and T flip flops, explaining their functionality and implementations.

Uploaded by

Astitav chauhan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ECE 233

DIGITAL LOGIC DESIGN LAB

Flip Flops
Course Instructor
Dr. Daljeet Singh
Domain: Wireless Communication
School of Electronics and Electrical Engineering
Lovely Professional University
Sequential circuits

It consists of a combinational circuit to which storage


elements are connected to form a feed back path.
Classification
Sequential circuits are classified in two main categories depending on
timing of their signals.
1. Synchronous or clocked sequential circuits
2. Asynchronous or un-clocked sequential circuits.
Synchronous or clocked sequential circuits
• A sequential circuit whose behavior can be defined from the
knowledge of its signals at discrete instants of time is referred to as a
synchronous sequential circuit.
• In such circuits, the memory elements are affected only at discrete
instants of time.
• The synchronization is obtained by a timing device, called a system
clock (or a master-clock generator) which generates a periodic train of
clock pulses. The outputs are affected only with the application of
clock pulse.
Asynchronous or un-clocked sequential
circuits.
• A sequential circuit whose behavior depends upon the sequence in
which the input signals change is referred to as an asynchronous
sequential circuit.
• The output is affected whenever there is a change in the inputs.
• The commonly used memory elements in such circuits are time delay
devices.
• These circuits may be regarded as combinational circuits with feed
back.
• These circuits are faster than synchronous sequential circuits.
However, in an asynchronous circuit, events are allowed to occur
without any synchronization.
Flip-Flops
• simplest kind of sequential circuit is a memory cell that has only two
states.
• It can be either a 0 or 1.
• Such two state sequential circuits are called flip-flops because they
flip from one state to another and then flop back.

• A flip-flop is also known as bistable multivibrator, latch or toggle.


Types of Flip-Flops
• Flip-Flops are of different types depending on how their inputs and
clock pulses cause transition between two states.
• There are 4 basic types
1. S – R (Set-Reset)/R-S flip – flop
2. J-K flip-flop
3. D (delay)flip-flop
4. T (trigger or Toggle)flip-flop
R-S Flip-Flop
• The S – R flip –flop has two inputs, namely
• SET (S) and
• RESET (R), and
• two outputs
• Q and Q′.

The two outputs are complement to each other. The R-S flip-flop can be
easily implemented using NOR gates or NAND gates.
The D – Flip-Flop
• In a clocked R-S flip-flop two input signals are required to drive the
flip-flop which is a disadvantage with many digital circuits.
• In some events, both the input signals become high which is again an
undesirable condition.
• So these drawbacks of clocked R-S flip-flop are overcome in D (delay)
flip-flop.
• It is nothing but a clocked R-S flip-flop with an inverter in the R input.
• The added inverter reduces the number of inputs from two to one.
The J – K Flip-Flop
• The J-K flip-flop is very versatile and is perhaps the most widely used
type of flip-flop.
• The J and K designations for the inputs have no known significance
except that they are adjacent letters in the alphabet.
• The functioning of J-K flop-flop is identical to that of the R-S flip-flop
in RESET, SET, and no change conditions of operation.
• The difference is that the J-K flip-flop has no invalid state as does the
R-S flip-flop.
• Therefore, the J-K flip-flop is a very versatile device that finds wide
application in digital devices such as counters, registers, arithmetic
logic units, and other digital systems. In J-K flip-flop clocked R-S flip-
flop along with two AND gates are used
T – Flip-Flop
• This flip-flop is basically a J-K flip-flop.
• This is also called Trigger or Toggle flip-flop.
• This has only a single data input(T), a clock input and two outputs Q
and Q′.
• The T-type flipflop is obtained from a J-K flip-flop by connecting its J
and K inputs together.
• The designation T comes from the ability of the flip-flop to “toggle” or
complement its state.
Thanks

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