SAA5540PS Philips

INTEGRATED CIRCUITS
DATA SHEET
SAA55xx
TV microcontrollers with Closed
Captioning (CC) and On-Screen
Display (OSD)
Preliminary specification 1999 Aug 02
File under Integrated Circuits, IC02
Philips Semiconductors Preliminary specification
TV microcontrollers with Closed Captioning (CC)

SAA55xx
and On-Screen Display (OSD)
CONTENTS 15.1 I2C-bus port selection

16 MEMORY INTERFACE
1 FEATURES
16.1 Memory structure
2 GENERAL DESCRIPTION
16.2 Memory mapping
3 QUICK REFERENCE DATA 16.3 Addressing memory
4 ORDERING INFORMATION 16.4 Page clearing
5 BLOCK DIAGRAM 17 DATA CAPTURE
6 PINNING INFORMATION 17.1 Data Capture features
6.1 Pinning 18 DISPLAY
6.2 Pin description 18.1 Display features
7 MICROCONTROLLER 18.2 Display modes
18.3 Display feature descriptions
7.1 Microcontroller features
18.4 Character and attribute coding
8 MEMORY ORGANIZATION 18.5 Screen and global controls
8.1 ROM bank switching 18.6 Text display controls
8.2 RAM organisation 18.7 Display positioning
8.3 Data memory 18.8 Character set
8.4 SFR memory 18.9 ROM addressing
8.5 Character set feature bits 18.10 Redefinable characters
8.6 External (auxiliary) memory 18.11 Display synchronization
9 REDUCED POWER MODES 18.12 Video/Data switch (Fast Blanking) polarity
18.13 Video/data switch adjustment
9.1 Idle mode 18.14 RGB brightness control
9.2 Power-down mode
18.15 Contrast reduction
9.3 Standby mode
19 MEMORY MAPPED REGISTERS (MMR)
10 I/O FACILITY
20 LIMITING VALUES
10.1 I/O ports
10.2 Port type 21 CHARACTERISTICS
10.3 Port alternative functions 22 QUALITY AND RELIABILITY
10.4 LED support 23 APPLICATION INFORMATION
11 INTERRUPT SYSTEM 24 ELECTROMAGNETIC COMPATIBILITY
11.1 Interrupt enable structure (EMC) GUIDELINES
11.2 Interrupt enable priority 25 PACKAGE OUTLINES
11.3 Interrupt vector address
26 SOLDERING
11.4 Level/edge interrupt
26.1 Introduction to soldering through-hole mount
12 TIMER/COUNTER
packages
13 WATCHDOG TIMER 26.2 Soldering by dipping or by solder wave
13.1 Watchdog Timer operation 26.3 Manual soldering
14 PULSE WIDTH MODULATORS 26.4 Suitability of through-hole mount IC packages
for dipping and wave soldering methods
14.1 PWM control
14.2 Tuning Pulse Width Modulator (TPWM) 27 DEFINITIONS
14.3 TPWM control 28 LIFE SUPPORT APPLICATIONS
14.4 Software ADC (SAD) 29 PURCHASE OF PHILIPS I2C COMPONENTS
15 I2C-BUS SERIAL I/O
1999 Aug 02 2

SAA55xx
1 FEATURES
• Single-chip microcontroller with integrated On-Screen
Display (OSD)
• One Time Programmable (OTP) memory for both
Program ROM and character sets
• Single power supply: 3.0 to 3.6 V
2 GENERAL DESCRIPTION
• 5 V tolerant digital inputs and I/O
The SAA55xx OSD only family of devices are a derivative
• 29 I/O port via individual addressable controls of the Philips industry standard 80C51 microcontroller and
• Programmable I/O for push-pull, open-drain and are intended for use as the central control mechanism in a
quasi-bidirectional television receiver. They provide control functions for the
• Two port lines with 8 mA sink (at <0.4 V) capability, for television system, On-Screen Display (OSD) and some
direct drive of Light Emitting Diode (LED) versions include an integrated data capture function.
• Single crystal oscillator for microcontroller, OSD and The main differences between the OSD only family and the
data capture SAA55xx Text/CC family of baseline devices are:
• Power reduction modes: Standby, Idle and Power-down • Program ROM size: 16 to 64-kbyte
• Byte level I2C-bus up to 200 kHz with dual port I/O • Display DRAM size: 1.25-kbyte (1 page Text OSD or
(Slave mode up to 400 kHz) CC/OSD)
• 32 Dynamically Redefinable Characters for OSDs • Auxiliary DRAM size: 0.75-kbyte
• Special graphic characters allowing four colours per • No teletext data capture (Closed Caption only)
character • Additional power saving mode (Standby).
• Selectable character height 9, 10, 13 and 16 TV lines
• Pin compatibility throughout family
• Operating temperature: −20 to +70°C
1999 Aug 02 3

SAA55xx
3 QUICK REFERENCE DATA
SYMBOL PARAMETER MIN. TYP. MAX. UNIT

Supply
VDDX any supply voltage (VDD to VSS) 3.0 3.3 3.6 V
IDDP periphery supply current; note 1 1 − − mA
IDDC core supply current − 12 18 mA
IDDC(id) Idle mode core supply current − 383 600 µA
IDDC(pd) Power-down mode core supply current − 666 900 µA
IDDC(stb) Standby mode core supply current − 5.1 9 mA
IDDA analog supply current − 45 48 mA
IDDA(id) Idle mode analog supply current − 444 700 µA
IDDA(pd) Power-down mode analog supply current − 433 700 µA
IDDA(stb) Standby mode core supply current − 809 950 µA
fxtal Fundamental mode nominal frequency − 12 − MHz
Tamb operating ambient temperature −20 − +70 °C
Tstg storage temperature −55 − +125 °C
Note
1. Peripheral supply current is dependent on external components and voltage levels on I/Os.
4 ORDERING INFORMATION
PACKAGE(2)
TYPE NUMBER(1) ROM RAM CC OSD
NAME DESCRIPTION VERSION
SAA5500PS/nnnn SDIP52 plastic shrink dual in-line SOT247-1 16-kbyte 256-byte no Standard
SAA5501PS/nnnn package; 52 leads (600 mil) 32-kbyte 512-byte no Standard
SAA5540PS/nnnn 16-kbyte 256-byte yes Enhanced
SAA5502PS/nnnn 48-kbyte 256-byte no Standard
SAA5503PS/nnnn 64-kbyte 512-byte no Standard
SAA5543PS/nnnn 64-kbyte 1-kbyte yes Enhanced
Notes
1. ‘nnnn’ is a four digit number uniquely referencing the microcontroller program mask.
2. For details of the LQFP100 package, please contact your local regional sales office for availability.
1999 Aug 02 4

SAA55xx
5 BLOCK DIAGRAM
handbook, full pagewidth TV CONTROL

I2C-bus, general I/O AND
INTERFACE
ROM MICROPROCESSOR SRAM

(16 TO 64-KBYTE) (80C51) (256-BYTE)
DRAM MEMORY
(UP TO 2-KBYTE) INTERFACE
R
DATA G
CVBS DISPLAY
CAPTURE B
VDS
DATA VSYNC
DISPLAY
CVBS CAPTURE
TIMING HSYNC
TIMING
GSA005
Fig.1 Block diagram (top level architecture).
1999 Aug 02 5

SAA55xx
6 PINNING INFORMATION
6.1 Pinning
handbook, halfpage
P2.0/TPWM 1 52 P1.5/SDA1
P2.1/PWM0 2 51 P1.4/SCL1
P2.2/PWM1 3 50 P1.7/SDA0
P2.3/PWM2 4 49 P1.6/SCL0
P2.4/PWM3 5 48 P1.3/T1
P2.5/PWM4 6 47 P1.2/INT0
P2.6/PWM5 7 46 P1.1/T0
P2.7/PWM6 8 45 P1.0/INT1
P3.0/ADC0 9 44 VDDP
P3.1/ADC1 10 43 RESET
P3.2/ADC2 11 42 XTALOUT
P3.3/ADC3 12 41 XTALIN
VSSC 13 40 OSCGND
SAA55xx
P0.0 14 39 VDDC
P0.1 15 38 VSSP
P0.2 16 37 VSYNC
P0.3 17 36 HSYNC
P0.4 18 35 VDS
P0.5 19 34 R
P0.6 20 33 G
P0.7 21 32 B
VSSA 22 31 VDDA
CVBS0 23 30 P3.4/PWM7
CVBS1 24 29 COR
SYNC_FILTER 25 28 VPE
IREF 26 27 FRAME
MBK951
Fig.2 SDIP52 pin configuration.
1999 Aug 02 6

SAA55xx
100 P2.0/TPWM
98 P2.6/PWM5
97 P2.5/PWM4
96 P2.4/PWM3
95 P2.3/PWM2
94 P2.2/PWM1
93 P2.1/PWM0
84 P1.5/SDA1
82 P1.7/SDA0
83 P1.4/SCL1
81 P1.6/SCL0
79 P1.2/INT0
76 P1.0/INT1
80 P1.3/T1
78 P1.1/T0
99 n.c.
92 n.c.
91 n.c.
90 n.c.
89 n.c.
88 n.c.
87 n.c.
86 n.c.
85 n.c.
77 n.c.
handbook, full pagewidth
P2.7/PWM6 1 75 VDDP
P3.0/ADC0 2 74 n.c.
n.c. 3 73 RESET
P3.1/ADC1 4 72 n.c.
P3.2/ADC2 5 71 XTALOUT
P3.3/ADC3 6 70 XTALIN
n.c. 7 69 OSCGND
n.c. 8 68 n.c.
n.c. 9 67 n.c.
n.c. 10 66 n.c.
VSSC 11 65 n.c.
VSSP 12 64 n.c.
P0.5 13 SAA55xx 63 VDDC
n.c. 14 62 VPE_2
n.c. 15 61 n.c.
P0.0 16 60 VSSP
P0.1 17 59 P3.6
P0.2 18 58 n.c.
n.c. 19 57 n.c.
n.c. 20 56 n.c.
n.c. 21 55 VSYNC
P0.3 22 54 P3.5
n.c. 23 53 HSYNC
P0.4 24 52 VDS
P3.7 25 51 n.c.
n.c. 26
n.c. 27
P0.6 28
P0.7 29
VSSA 30
CVBS0 31
CVBS1 32
n.c. 33
SYNC_FILTER 34
IREF 35
n.c. 36
n.c. 37
n.c. 38
n.c. 39
n.c. 40
FRAME 41
VPE 42
COR 43
P3.4/PWM7 44
VDDA 45
B 46
G 47
R 48
n.c. 49
n.c. 50
GSA001
Fig.3 LQFP100 pin configuration.
1999 Aug 02 7

SAA55xx
6.2 Pin description

Table 1 SDIP52 and LQFP100 packages
PIN
SYMBOL TYPE DESCRIPTION
SDIP52 LQFP100
P2.0/TPWM 1 100 I/O Port 2. 8-bit programmable bidirectional port with
P2.1/PWM0 2 93 I/O alternative functions.
P2.2/PWM1 3 94 I/O P2.0/TPWM is the output for the 14-bit high precision
P2.3/PWM2 4 95 I/O PWM. P2.1/PWM0 to P2.7/PWM6 are the outputs for
the 6-bit PWMs 0 to 6.
P2.4/PWM3 5 96 I/O
P2.5/PWM4 6 97 I/O
P2.6/PWM5 7 98 I/O
P2.7/PWM6 8 1 I/O
P3.0/ADC0 9 2 I/O Port 3. 8-bit programmable bidirectional port with
P3.1/ADC1 10 4 I/O alternative functions.
P3.2/ADC2 11 5 I/O P3.0/ADC0 to P3.3/ADC3 are the inputs for the
P3.3/ADC3 12 6 I/O software ADC facility. P3.4/PWM7 is the output for the
6-bit PWM7. P3.5 to P3.7 have no alternative
P3.4/PWM7 30 44 I/O
functions and are only available with the LQFP100
P3.5 − 54 I/O package.
P3.6 − 59 I/O
P3.7 − 25 I/O
VSSC 13 11 − core ground
P0.0 14 16 I/O Port 0. 8-bit programmable bidirectional port.
P0.1 15 17 I/O P0.5 and P0.6 have 8 mA current sinking capability for
P0.2 16 18 I/O direct drive of LEDs.
P0.3 17 22 I/O
P0.4 18 24 I/O
P0.5 19 13 I/O
P0.6 20 28 I/O
P0.7 21 29 I/O
VSSA 22 30 − analog ground
CVBS0 23 31 I Composite Video Baseband Signal (CVBS) input. A
positive-going 1 V (peak-to-peak) input is required.
CVBS1 24 32 I Connected via a 100 nF capacitor.
SYNC_FILTER 25 34 I CVBS sync filter input. This pin should be connected
to VSSA via a 100 nF capacitor.
IREF 26 35 I Reference current input for analog circuits, connected
to VSSA via a 24 KΩ resistor.
FRAME 27 41 O De-interlace output synchronised with the VSYNC
pulse to produce a non-interlaced display by
adjustment of the vertical deflection circuits.
VPE 28 42 I OTP programming voltage
1999 Aug 02 8

SAA55xx
PIN
SYMBOL TYPE DESCRIPTION
SDIP52 LQFP100
COR 29 43 O Open-drain, active LOW output which allows selective
contrast reduction of the TV picture to enhance a
mixed mode display.
VDDA 31 45 − +3.3 V analog power supply
B 32 46 O Pixel rate output of the BLUE colour information.
G 33 47 O Pixel rate output of the GREEN colour information.
R 34 48 O Pixel rate output of the RED colour information.
VDS 35 52 O Video/data switch push-pull output for dot rate fast
blanking.
HSYNC 36 53 I Schmitt triggered input TTL version of the horizontal
sync pulse. The polarity of this pulse is programmable
by register bit TXT1.H POLARITY.
VSYNC 37 55 I Schmitt triggered input for a TTL version of the vertical
sync pulse. The polarity of this pulse is programmable
by register bit TXT1.V POLARITY.
VSSP 38 12, 60 − periphery ground
VDDC 39 63 − +3.3 V core power supply
OSCGND 40 69 − crystal oscillator ground
XTALIN 41 70 I 12 MHz crystal oscillator input
XTALOUT 42 71 O 12 MHz crystal oscillator output
RESET 43 73 I If the reset input is HIGH for at least 2 machine cycles
(24 oscillator periods) while the oscillator is running,
the device is reset. This pin should be connected to
VDDP via a capacitor.
VDDP 44 75 − +3.3 V periphery power supply
P1.0/INT1 45 76 I/O Port 1. 8-bit programmable bidirectional port with
P1.1/T0 46 78 I/O alternative functions.
P1.2/INT0 47 79 I/O P1.0/INT1 is external interrupt 1 which can be
P1.3/T1 48 80 I/O triggered on the rising and falling edge of the pulse.
P1.1/T0 is the Counter/Timer 0. P1.2/INT0 is external
P1.6/SCL0 49 81 I/O
interrupt 0. P1.3/T1 is the Counter/Timer 1.
P1.7/SDA0 50 82 I/O P1.6/SCL0 is the serial clock input for the I2C-bus and
P1.4/SCL1 51 83 I/O P1.7/SDA0 is the serial data port for the I2C-bus.
P1.5/SDA1 52 84 I/O P1.4/SCL1 is the serial clock input for the I2C-bus and
P1.5/SDA1 is the serial data port for the I2C-bus.
VPE_2 − 62 I OTP programming voltage
n.c. − 3, 7 to 10, 14, 15, 19 to 21, − not connected
23, 26, 27, 33, 36 to 40,
49 to 51, 56 to 58, 61,
64 to 68, 72, 74, 77,
85 to 92, 99
1999 Aug 02 9

SAA55xx
7 MICROCONTROLLER 8 MEMORY ORGANIZATION

The functionality of the microcontroller used on this device The device has the capability of a maximum of 64-kbyte
is described here with reference to the industry standard Program ROM and 2-kbyte Data RAM internally.
80C51 microcontroller. A full description of its functionality
can be found in the “Painter 1 Hardware System 8.1 ROM bank switching
Specification and Tentative Device Specification
As the Program ROM does not exceed 64 kbytes in any of
(Painter1.1/1.10)”.
the OSD only variants, ROM bank switching is not
required.
7.1 Microcontroller features
The memory and security bits are structured as shown in
• 80C51 microcontroller core standard instruction set and
Fig.4.
timing
• 1 µs machine cycle The OSD only security bits are set as shown in Fig.5 for
production programmed devices.
• Maximum 64K × 8-bit program ROM
The OSD only security bits are set as shown in Fig.6 for
• 2 × 8-bit auxiliary RAM, maximum of 1.25 kbytes
production blank devices.
required for display
• Interrupt controller for individual enable/disable with two 8.2 RAM organisation
level priority
The Internal Data RAM is organized into two areas, Data
• Two 16-bit timer/counter registers
memory and Special Function Registers (SFRs).
• Watchdog Timer
• Auxiliary RAM page pointer 8.3 Data memory
• 16-bit data pointer The Data memory is 256 × 8-bit, and occupies the address
• Standby, Idle and Power-down modes range 00H to FFH when using indirect addressing and
00H to 7FH when using direct addressing. The SFRs
• 29 general I/O lines
occupy the address range 80H to FFH and are accessible
• Eight 6-bit Pulse Width Modulator (PWM) outputs for using direct addressing only.
control of TV analog signals
The lower 128 bytes of Data memory are mapped as
• One 14-bit PWM for Voltage Synthesis Tuner (VST) shown in Fig.8.
control
The lowest 24 bytes are grouped into 4 banks of
• 8-bit Analog-to-Digital Converter (ADC) with four
8 registers, the next 16 bytes above the register banks
multiplexed inputs
form a block of bit addressable memory space.
• 2 high current outputs for directly driving LEDs
The upper 128 bytes are not allocated for any special area
• I2C-bus byte level bus interface with dual ports.
or functions.
1999 Aug 02 10

SAA55xx
handbook, full pagewidth MEMORY SECURITY BITS INTERACTION
PROGRAM ROM USER ROM PROGRAMMING VERIFY

(ENABLE/DISABLE) (ENABLE/DISABLE)
USER ROM
(64K x 8-BIT)
CHARACTER ROM USER ROM PROGRAMMING VERIFY

USER ROM
(9K x 12-BIT)
GSA006
Fig.4 Memory and security bit structures.
handbook, full pagewidth MEMORY SECURITY BITS SET
USER ROM PROGRAMMING VERIFY

PROGRAM ROM
DISABLED ENABLED
CHARACTER ROM
DISABLED ENABLED
GSA007
Fig.5 Security bits for production devices.
1999 Aug 02 11

SAA55xx
handbook, full pagewidth MEMORY SECURITY BITS SET
USER ROM PROGRAMMING VERIFY

PROGRAM ROM
ENABLED ENABLED
CHARACTER ROM
ENABLED ENABLED
GSA008
Fig.6 Security bits for production blank devices.
handbook, halfpage SPECIAL

DATA
FUNCTION
MEMORY
REGISTERS
FFH
accessible accessible
by indirect by direct
upper 128 bytes
addressing addressing
only only
80H
7FH
accessible
by direct
lower 128 bytes
and indirect
addressing
00H MBK956
Fig.7 Internal data memory.
1999 Aug 02 12

SAA55xx
handbook, halfpage 7FH
30H
2FH
bit-addressable space
(bit addresses 00H to 7FH)
20H
R7 1FH
R0 18H
R7 17H
R0 10H 4 banks of 8 registers

R7 0FH (R0 to R7)
R0 08H
R7 07H
R0 0 MGM677
Fig.8 Lower 128 bytes of internal RAM.
1999 Aug 02 13
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1999 Aug 02 8.4 SFR memory
Philips Semiconductors
The Special Function Register (SFR) space is used for port latches, timer, peripheral control, acquisition control, display control, etc. These registers
can only be accessed by direct addressing. Sixteen of the addresses in the SFR space are both bit and byte addressable. The bit addressable SFRs
are those whose address ends in 0H or 8H. A summary of the SFR map in address order is shown in Table 2.
A description of each of the SFR bits is shown in Table 3 which presents the SFRs in alphabetical order.
Table 2 SFR memory map

ADD R/W NAME 7 6 5 4 3 2 1 0 RESET
80H R/W PO P07 P06 P05 P04 P03 P02 P01 P00 FFH
81H R/W SP SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 07H
82H R/W DPL DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0 00H
83H R/W DPH DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0 00H
87H R/W PCON 0 ARD RFI WLE GF1 GF0 PD IDL 00H
88H R/W TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H
89H R/W TMOD GATE C/T M1 M0 GATE C/T M1 M0 00H
8AH R/W TL0 TL07 TL06 TL05 TL04 TL03 TL02 TL01 TL00 00H
8BH R/W TL1 TL17 TL16 TL15 TL14 TL13 TL12 TL11 TL10 00H
14
8CH R/W TH0 TH07 TH06 TH05 TH04 TH03 TH02 TH01 TH00 00H
8DH R/W TH1 TH17 TH16 TH15 TH14 TH13 TH12 TH11 TH10 00H
90H R/W P1 P17 P16 P15 P14 P13 P12 P11 P10 FFH
96H R/W P0CFGA P0CFGA7 P0CFGA6 P0CFGA5 P0CFGA4 P0CFGA3 P0CFGA2 P0CFGA1 P0CFGA0 FFH
97H R/W P0CFGB P0CFGB7 P0CFGB6 P0CFGB5 P0CFGB4 P0CFGB3 P0CFGB2 P0CFGB1 P0CFGB0 00H
98H R/W SADB 0 0 0 DC_COMP SAD3 SAD2 SAD1 SAD0 00H
9EH R/W P1CFGA P1CFGA7 P1CFGA6 P1CFGA5 P1CFGA4 P1CFGA3 P1CFGA2 P1CFGA1 P1CFGA0 FFH
9FH R/W P1CFGB P1CFGB7 P1CFGB6 P1CFGB5 P1CFGB4 P1CFGB3 P1CFGB2 P1CFGB1 P1CFGB0 00H
A0H R/W P2 P27 P26 P25 P24 P23 P22 P21 P20 FFH
A6H R/W P2CFGA P2CFGA7 P2CFGA6 P2CFGA5 P2CFGA4 P2CFGA3 P2CFGA2 P2CFGA1 P2CFGA0 FFH
Preliminary specification
A7H R/W P2CFGB P2CFGB7 P2CFGB6 P2CFGB5 P2CFGB4 P2CFGB3 P2CFGB2 P2CFGB1 P2CFGB0 00H
A8H R/W IE EA EBUSY ES2 ECC ET1 EX1 ET0 EX0 00H
SAA55xx
B0H R/W P3 P37 P36 P35 P34 P33 P32 P31 P30 FFH
B2H R/W TXT18 NOT3 NOT2 NOT1 NOT0 0 0 BS1 BS0 00H
B3H R/W TXT19 TEN TC2 TC1 TC0 0 0 TS1 TS0 00H
B4H R/W TXT20 DRCS OSD 0 0 OSD LANG OSD LAN2 OSD LAN1 OSD LAN0 00H
ENABLE PLANES ENABLE
1999 Aug 02

B5H R/W TXT21 DISP DISP CHAR CHAR I2C PORT 1 CC ON I2C PORT 0 CC/TXT 02H
LINES1 LINES0 SIZE1 SIZE0
B6H R TXT22 GPF7 GPF6 GPF5 GPF4 GPF3 GPF2 GPF1 GPF0 XXH
B7H R/W CCLIN 0 0 0 CS4 CS3 CS2 CS1 CS0 15H
B8H R/W IP 0 PBUSY PES2 PCC PT1 PX1 PT0 PX0 00H
B9H R/W TXT17 0 FORCE FORCE FORCE FORCE SCREEN SCREEN SCREEN 00H
ACQ1 ACQ0 DISP1 DISP0 COL2 COL1 COL0
BEH R/W P3CFGA P3CFGA7 P3CFGA6 P3CFGA5 P3CFGA4 P3CFGA3 P3CFGA2 P3CFGA1 P3CFGA0 FFH
BFH R/W P3CFGB P3CFGB7 P3CFGB6 P3CFGB5 P3CFGB4 P3CFGB3 P3CFGB2 P3CFGB1 P3CFGB0 00H
C0H R/W TXT0 (reserved) (reserved) AUTO (reserved) (reserved) DISABLE (reserved) (reserved) 00H
0 0 FRAME 0 0 FRAME 0 0
C1H R/W TXT1 (reserved) (reserved) (reserved) (reserved) (reserved) FIELD H V 00H
0 0 0 0 0 POLARITY POLARITY POLARITY
C4H R/W TXT4 OSD BANK QUAD EAST/WES DISABLE B MESH C MESH TRANS SHADOW 00H
ENABLE WIDTH T DOUBLE ENABLE ENABLE ENABLE ENABLE
ENABLE HEIGHT
C5H R/W TXT5 BKGND BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE PICTURE 03H
15
OUT ON OUT ON IN
C6H R/W TXT6 BKGND BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE PICTURE 03H
OUT ON OUT ON IN
C7H R/W TXT7 (reserved) CURSOR (reserved) (reserved)0 DOUBLE BOX ON 24 BOX ON BOX ON 0 00H
0 ON 0 HEIGHT 1 − 23
C8H R/W TXT8 (reserved) FLICKER (reserved) DISABLE PKT 26 WSS WSS ON CVBS1/ 00H
0 STOP ON 0 SPANISH RECEIVED RECEIVED CVBS0
C9H R/W TXT9 CURSOR CLEAR (reserved) R4 R3 R2 R1 R0 00H
FREEZE MEMORY 0
CAH R/W TXT10 0 0 C5 C4 C3 C2 C1 C0 00H
CBH R/W TXT11 D7 D6 D5 D4 D3 D2 D1 D0 00H
CCH R TXT12 525/625 ROM VER4 ROM VER3 ROM VER2 ROM VER1 ROM VER0 1 VIDEO XXXX
SYNC SIGNAL XX1X
QUALITY
SAA55xx
D0H R/W PSW C AC F0 RS1 RS0 OV − P 00H
D2H R/W TDACL TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0 00H
D3H R/W TDACH TPWE 1 TD13 TD12 TD11 TD10 TD9 TD8 40H
1999 Aug 02

D4H R/W PWM7 PW7E 1 PW7V5 PW7V4 PW7V3 PW7V2 PW7V1 PW7V0 40H
D7H R CCDAT1 CCD17 CCD16 CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 00H
D8H R/W S1CON CR2 ENSI STA STO SI AA CR1 CR0 00H
D9H R S1STA STAT4 STAT3 STAT2 STAT1 STAT0 0 0 0 F8H
DAH R/W S1DAT DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0 00H
DBH R/W S1ADR ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 GC 00H
DCH R/W PWM3 PW3E 1 PW3V5 PW3V4 PW3V3 PW3V2 PW3V1 PW3V0 40H
DDH R/W PWM4 PW4E 1 PW4V5 PW4V4 PW4V3 PW4V2 PW4V1 PW4V0 40H
DEH R/W PWM5 PW5E 1 PW5V5 PW5V4 PW5V3 PW5V2 PW5V1 PW5V0 40H
DFH R/W PWM6 PW6E 1 PW6V5 PW6V4 PW6V3 PW6V2 PW6V1 PW6V0 40H
E0H R/W ACC ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0 00H
E4H R/W PWM2 PW2E 1 PW2V5 PW2V4 PW2V3 PW2V2 PW2V1 PW2V0 40H
E7H R CCDAT2 CCD27 CCD26 CCD25 CCD24 CCD23 CCD22 CCD21 CCD20 00H
16
E8H R/W SAD VHI CH1 CH0 ST SAD7 SAD6 SAD5 SAD4 00H
F0H R/W B B7 B6 B5 B4 B3 B2 B1 B0 00H
F7H W WDTKEY WKEY7 WKEY6 WKEY5 WKEY4 WKEY3 WKEY2 WKEY1 WKEY0 00H
F8H R/W TXT13 (reserved) PAGE 525 (reserved) (reserved) (reserved) (reserved) (reserved) XXXX
0 CLEARING DISPLAY 0 0 0 0 0 XXX0
FAH R/W XRAMP XRAMP7 XRAMP6 XRAMP5 XRAMP4 XRAMP3 XRAMP2 XRAMP1 XRAMP0 00H
FBH R/W ROMBK STANDBY 0 0 0 0 0 (reserved) (reserved) 00H
0 0
FFH R/W WDT WDV7 WDV6 WDV5 WDV4 WDV3 WDV2 WDV1 WDV0 00H
SAA55xx

SAA55xx
Table 3 SFR bit description

BIT FUNCTION
Accumulator (ACC)
ACC7 to ACC0 accumulator value
B Register (B)
B7 to B0 B register value
CC data byte 1 (CCDAT1)
CCD17 to CCD10 closed caption first data byte
CC data byte 2 (CCDAT2)
CCD26 to CCD20 closed caption second data byte
CC line (CCLIN)
CS4 to CS0 closed caption slice line using 525-line number
Data Pointer High byte (DPH)
DPH7 to DPH0 data pointer high byte, used with DPL to address auxiliary memory
Data pointer Low byte (DPL)
DPL7 to DPL0 data pointer low byte, used with DPH to address auxiliary memory
Interrupt Enable Register (IE)
EA disable all interrupts (logic 0), or use individual interrupt enable bits (logic 1)
EBUSY enable BUSY interrupt
ES2 enable I2C-bus interrupt
ECC enable closed caption interrupt
ET1 enable Timer 1 interrupt
EX1 enable external interrupt 1
ET0 enable Timer 0 interrupt
EX0 enable external interrupt 0
Interrupt Priority Register (IP)
PBUSY priority EBUSY interrupt
PES2 priority ES2 Interrupt
PCC priority ECC interrupt
PT1 priority Timer 1 interrupt
PX1 priority external interrupt 1
PT0 priority Timer 0 interrupt
PX0 priority external interrupt 0
Port 0 (P0)
P07 to P00 Port 0 I/O register connected to external pins
1999 Aug 02 17

SAA55xx
BIT FUNCTION
Port 1 (P1)
Port 2 (P2)
Port 3 (P3)
P37 to P30 Port 3 I/O register connected to external pins; P37 to P35 are only available with
the LQFP100 package
Port 0 Configuration A (P0CFGA) and Port 0 Configuration B (P0CFGB)
P0CFGA<7:0> and P0CFGB<7:0> These two registers are used to configure Port 0 pins. For example, the I/O
configuration of Port 0 pin 3 is controlled using bit 3 in both P0CFGA and
P0CFGB. P0CFGB<x>/P0CFGA<x>:
00 = P0.x in open-drain configuration
01 = P0.x in quasi-bidirectional configuration
10 = P0.x in high-impedance configuration
11 = P0.x in push-pull configuration
configuration of Port 2 pin 3 is controlled by using bit 3 in both P2CFGA and
10 = P2.x high-impedance configuration
11 = P2.x push-pull configuration
1999 Aug 02 18

SAA55xx
BIT FUNCTION
Power Control Register (PCON)
ARD auxiliary RAM disable, all MOVX instructions access the external data memory
RFI disable ALE during internal access to reduce radio frequency interference
WLE Watchdog Timer enable
GF1 general purpose flag
GF0 general purpose flag
PD Power-down mode activation bit
IDL Idle mode activation bit
Program Status Word (PSW)
C carry bit
AC auxiliary carry bit
F0 flag 0, general purpose flag
RS1 to RS0 register bank selector bits; RS<1:0>:
00 = Bank 0 (00H to 07H)
01 = Bank 1 (08H to 0FH)
10 = Bank 2 (10H to 17H)
11 = Bank 3 (18H to 1FH)
OV overflow flag
P parity bit
Pulse Width Modulator 0 Control Register (PWM0)
PW0E activate this PWM (logic 1)
PW0V5 to PW0V0 pulse width modulator high time
1999 Aug 02 19

SAA55xx
BIT FUNCTION
ROM Bank (ROMBK)
STBY Standby mode enabled (logic 1)
I2C-bus Slave Address Register (S1ADR)
ADR6 to ADR0 I2C-bus slave address to which the device will respond
GC enable I2C-bus general call address (logic 1)
I2C-bus Control Register (S1CON)
CR2 to CR0 clock rate bits; CR<2:0>:
000 = 100 kHz bit rate
001 = 3.75 kHz bit rate
ENSI enable I2C-bus interface (logic 1)
STA START flag. When this bit is set in slave mode, the hardware checks the I2C-bus
and generates a START condition if the bus is free or after the bus becomes free.
If the device operates in master mode it will generate a repeated START
condition.
STO STOP flag. If this bit is set in a master mode a STOP condition is generated.
A STOP condition detected on the I2C-bus clears this bit. This bit may also be set
in slave mode in order to recover from an error condition. In this case no STOP
condition is generated to the I2C-bus, but the hardware releases the SDA and
SCL lines and switches to the not selected receiver mode. The STOP flag is
cleared by the hardware.
1999 Aug 02 20

SAA55xx
BIT FUNCTION
SI Serial Interrupt flag. This flag is set and an interrupt request is generated, after
any of the following events occur:
• A START condition is generated in master mode
• The own slave address has been received during AA = 1
• The general call address has been received while S1ADR.GC and AA = 1
• A data byte has been received or transmitted in master mode (even if arbitration
is lost)
• A data byte has been received or transmitted as selected slave
• A STOP or START condition is received as selected slave receiver or
transmitter. While the SI flag is set, SCL remains LOW and the serial transfer is
suspended. SI must be reset by software.
AA Assert Acknowledge flag. When this bit is set, an acknowledge is returned
after any one of the following conditions:
• Own slave address is received
• General call address is received (S1ADR.GC = 1)
• A data byte is received, while the device is programmed to be a master receiver
• A data byte is received, while the device is selected slave receiver.
When the bit is reset, no acknowledge is returned. Consequently, no interrupt is
requested when the own address or general call address is received.
I2C-bus Data Register (S1DAT)
DAT7 to DAT0 I2C-bus data
I2C-bus Status Register (S1STA)
STAT4 to STAT0 I2C-bus interface status
Software ADC Register (SAD)
VHI analog input voltage greater than DAC voltage (logic 1)
CH1 to CH0 ADC input channel select; CH<1:0>:
00 = ADC3
01 = ADC0
10 = ADC1
11 = ADC2
ST(1) initiate voltage comparison between ADC input channel and SAD value
SAD7 to SAD4 4 MSBs of DAC input word
Software ADC Control Register (SADB)
DC_COMP enable DC comparator mode (logic 1)
SAD3 to SAD0 4 LSBs of SAD value
Stack Pointer (SP)
SP7 to SP0 stack pointer value
1999 Aug 02 21

SAA55xx
BIT FUNCTION
Timer/Counter Control Register (TCON)
TF1 Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by
hardware when processor vectors to interrupt routine.
TR1 Timer 1 run control bit. Set/cleared by software to turn timer/counter on/off.
TF0 Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by
hardware when processor vectors to interrupt routine.
TR0 Timer 0 run control bit. Set/cleared by software to turn timer/counter on/off.
IE1 Interrupt 1 edge flag (both edges generate flag). Set by hardware when
external interrupt edge detected. Cleared by hardware when interrupt processed.
IT1 Interrupt 1 type control bit. Set/cleared by software to specify edge/LOW level
triggered external interrupts.
IE0 Interrupt 0 edge l flag. Set by hardware when external interrupt edge detected.
Cleared by hardware when interrupt processed.
IT0 Interrupt 0 type flag. Set/cleared by software to specify falling edge/LOW level
triggered external interrupts.
14-bit PWM MSB Register (TDACH)
TPWE activate this 14-bit PWM (logic 1)
TD13 to TD8 6 MSBs of 14-bit number to be output by the 14-bit PWM
14-bit PWM LSB Register (TDACL)
TD7 to TD0 8 LSBs of 14-bit number to be output by the 14-bit PWM
Timer 0 High byte (TH0)
TH07 to TH00 Timer 0 high byte
Timer 1 High byte (TH1)
TH17 to TH10 Timer 1 high byte
Timer 0 Low byte (TL0)
TL07 to TL00 Timer 0 low byte
Timer 1 Low byte (TL1)
TL17 to TL10 Timer 1 low byte
Timer/Counter Mode Control (TMOD)
GATE gating control Timer/Counter 1
C/T Counter/Timer 1 selector
M1 to M0 mode control bits timer/counter 1; M<1:0>:
00 = 8-bit timer or 8-bit counter with divide-by-32 prescaler
01 = 16-bit time interval or event counter
10 = 8-bit time interval or event counter with automatic reload upon overflow;
reload value stored in TH1
11 = stopped
GATE gating control Timer/Counter 0
C/T Counter/Timer 0 selector
1999 Aug 02 22

SAA55xx
BIT FUNCTION
M1 to M0 mode control bits timer/counter 0; M<1:0>:
00 = 8-bit timer or 8-bit counter with divide-by-32 prescaler
01 = 16-bit time interval or event counter
10 = 8-bit time interval or event counter with automatic reload upon overflow;
reload value stored in TH0
11 = one 8-bit time interval or event counter and one 8-bit time interval counter
Text Register 0 (TXT0)
AUTO FRAME frame output is switched off automatically if any video displayed (logic 1)
DISABLE FRAME force frame output to be LOW (logic 1)
FIELD POLARITY VSYNC pulse in second half of line during even field (logic 1)
H POLARITY HSYNC reference edge is negative going (logic 1)
V POLARITY VSYNC reference edge is negative going (logic 1)
OSD BANK ENABLE alternate OSD location available via graphic attribute, additional 32 location
(logic 1)
QUAD WIDTH ENABLE enable display of quadruple width characters (logic 1)
EAST/WEST eastern character selection of character codes A0H to FFH (logic 1)
DISABLE DOUBLE HEIGHT disable normal decoding of double height characters (logic 1)
B MESH ENABLE enable meshing of black background (logic 1)
C MESH ENABLE enable meshing of coloured background (logic 1)
TRANS ENABLE display black background as video (logic 1)
SHADOW ENABLE display shadow/fringe (default SE black) (logic 1)
BKGND OUT background colour displayed outside teletext boxes (logic 1)
BKGND IN background colour displayed inside teletext boxes (logic 1)
COR OUT COR active outside teletext and OSD boxes (logic 1)
COR IN COR active inside teletext and OSD boxes (logic 1)
TEXT OUT text displayed outside teletext boxes (logic 1)
TEXT IN text displayed inside teletext boxes (logic 1)
PICTURE ON OUT video displayed outside teletext boxes (logic 1)
PICTURE ON IN video displayed inside teletext boxes (logic 1)
BKGND OUT background colour displayed outside teletext boxes (logic 1)
BKGND IN background colour displayed inside teletext boxes (logic 1)
COR OUT COR active outside teletext and OSD boxes (logic 1)
COR IN COR active inside teletext and OSD boxes (logic 1)
TEXT OUT text displayed outside teletext boxes (logic 1)
TEXT IN text displayed inside teletext boxes (logic 1)
PICTURE ON OUT video displayed outside teletext boxes (logic 1)
1999 Aug 02 23

SAA55xx
BIT FUNCTION
PICTURE ON IN video displayed inside teletext boxes (logic 1)
CURSOR ON display cursor at position given by TXT9 and TXT10 (logic 1)
DOUBLE HEIGHT display each character as twice normal height (logic 1)
BOX ON 24 enable display of teletext boxes in memory row 24 (logic 1)
BOX ON 1 − 23 enable display of teletext boxes in memory row 1 to 23 (logic 1)
BOX ON 0 enable display of teletext boxes in memory row 0 (logic 1)
FLICKER STOP ON disable ‘Flicker Stopper’ circuitry (logic 1)
DISABLE SPANISH disable special treatment of Spanish packet 26 characters (logic 1)
PKT 26 RECEIVED(2) packet 26 data has been processed (logic 1)
WSS RECEIVED(2) wide screen signalling data has been processed (logic 1)
WSS ON enable acquisition of WSS data (logic 1)
CVBS1/CVBS0 select CVBS1 as source for device (logic 1)
CURSOR FREEZE lock cursor at current position (logic 1)
CLEAR MEMORY(1) clear memory block pointed to by TXT15
R4 to R0(2) current memory row value
C5 to C0(3) current memory column value
D7 to D0 data value written or read from memory location defined by TXT9, TXT10 and
TXT15
525/625 SYNC(4) 525-line CVBS signal is being received (logic 1)
ROM VER4 to ROM VER0 mask programmable identification for character set
VIDEO SIGNAL QUALITY acquisition can be synchronised to CVBS (logic 1)
PAGE CLEARING software or power-on page clear in progress (logic 1)
525 DISPLAY 525-line synchronisation for display (logic 1)
FORCE ACQ1 to FORCE ACQ0 FORCE ACQ<1:0>:
00 = automatic selection
01 = force 525 timing, force 525 teletext standard
1999 Aug 02 24

SAA55xx
BIT FUNCTION
FORCE DISP1 to FORCE DISP0 FORCE DISP<1:0>:
00 = automatic selection
01 = force display to 525 mode (9 lines per row)
10 = force display to 625 mode (10 lines per row)
11 = not valid (default to 625 mode)
SCREEN COL2 to SCREEN COL0 Defines colour to be displayed instead of TV picture and black background; these
bits are equivalent to the RGB components. SCREEN COL<2:0>:
000 = transparent
001 = CLUT entry 9
010 = CLUT entry 10
011 = CLUT entry 11
100 = CLUT entry 12
101 = CLUT entry 13
110 = CLUT entry 14
111 = CLUT entry 15
NOT3 to NOT0 national option table selection, maximum of 31 when used with EAST/WEST bit
BS1 to BS0 basic character set selection
TEN enable twist character set (logic 1)
TC2 to TC0 language control bits (C12, C13 and C14) that has twisted character set
TS1 to TS0 twist character set selection
DRCS ENABLE re-map column 9 to DRCS in TXT mode (logic 1)
OSD PLANES character code columns 8 and 9 defined as double plane characters (logic 1)
OSD LANG ENABLE enable use of OSD LAN<2:0> to define language option for display, instead of
C12, C13 and C14
OSD LAN2 to OSD LAN0 alternative C12, C13 and C14 bits for use with OSD menus
DISP LINES1 to DISP LINES0 the number of display lines per character row; DISP LINES<1:0>:
00 = 10 lines per character (defaults to 9 lines in 525 mode)
01 = 13 lines per character
10 = 16 lines per character
11 = reserved (logic 1)
CHAR SIZE1 to CHAR SIZE0 character matrix size; CHAR SIZE<1:0>:
00 = 10 lines per character (matrix 12 × 10)
11 = reserved
I2C PORT 1 enable I2C-bus Port 1 selection (P1.5/SDA1 and P1.4/SCL1) (logic 1)
1999 Aug 02 25

SAA55xx
BIT FUNCTION
CC ON closed caption acquisition on (logic 1)
I2C PORT 0 enable I2C-bus Port 0 selection (P1.7/SDA0 and P1.6/SCL0) (logic 1)
CC/TXT display configured for CC mode (logic 1)
GPF7 to GPF5 general purpose register, bits defined by mask programmable bits
GPF4 reserved
GPF3 PWM0, PWM1, PWM2 and PWM3 output on Port 2.1 to Port 2.4 respectively
(logic 1)
GPF2 enable closed caption acquisition (logic 1)
GPF1 and GPF0 reserved
Watchdog Timer (WDT)
WDV7 to WDV0 Watchdog Timer period
Watchdog Timer Key (WDTKEY)
WKEY7 to WKEY0(5) Watchdog Timer Key value
XRAMP
XRAMP7 to XRAMP0 internal RAM access upper byte address
Notes
1. This flag is set by software and reset by hardware.
2. Valid range TXT mode 0 to 24.
3. Valid range TXT mode 0 to 39.
4. Only valid when VIDEO SIGNAL QUALITY is set.
5. Must be set to 55H to disable Watchdog Timer when active.
1999 Aug 02 26

SAA55xx
8.5 Character set feature bits

Features available on the OSD only devices are reflected in a specific area of the Character ROM. These sections of the
Character ROM are mapped to two Special Function Registers: TXT22 and TXT12. Character ROM address 09FEH is
mapped to SFR TXT22 as shown in Table 4. Character ROM address 09FFH is mapped to SFR TXT12 as shown in
Table 6.
Table 4 Character ROM - TXT22 mapping

U = used; X = reserved
MAPPED ITEMS 11 10 9 8 7 6 5 4 3 2 1 0
Character ROM X X X X X X X X U U X X
address 09FEH
Mapped to TXT22 − − − − 7 6 5 4 3 2 1 0
Table 5 Description of Character ROM address 09FEH bits

BIT DESCRIPTION
0 to 1 reserved; normally all set to logic 1
2 1 = enable CC acquisition
0 = disable CC acquisition
3 1 = PWM0, PWM1, PWM2 and PWM3 output routed to Port 2.1 to Port 2.4 respectively
0 = PWM0, PWM1, PWM2 and PWM3 output routed to Port 3.0 to Port 3.3 respectively
Table 6 Character ROM - TXT12 mapping

U = used; X = reserved
MAPPED ITEMS 11 10 9 8 7 6 5 4 3 2 1 0
Character ROM X X X X X X X X X X X X
address 09FFH
Mapped to TXT12 − − − − − − − 6 5 4 3 2
Table 7 Description of Character ROM address 09FFH bits

BIT DESCRIPTION
1999 Aug 02 27

SAA55xx
8.6 External (auxiliary) memory 8.6.1 AUXILIARY RAM PAGE SELECTION

The normal 80C51 external memory area has been The Auxiliary RAM page pointer is used to select one of
mapped internally to the device, this means that the MOVX the 256 pages within the Auxiliary RAM, not all pages are
instruction accesses memory internal to the device. allocated; refer to Fig.9 for further detail. A page consists
of 256 consecutive bytes.
handbook, halfpage
7FFFH FFFFH
8C00H
8BFFH
DYNAMICALLY
REDEFINABLE
CHARACTERS
8800H
87FFH
DISPLAY REGISTERS
87F0H
2400H
23FFH 871FH
DISPLAY RAM CLUT
FOR 8700H
TEXT OSD (1)
2000H
845FH
DISPLAY RAM
02FFH FOR
DATA RAM CLOSED CAPTION (1)
0000H 8000H
GSA009
lower 32 kbytes upper 32 kbytes
(1) Display RAM for Closed Caption and Text is shared.
Fig.9 Auxiliary RAM allocation.
1999 Aug 02 28

SAA55xx
handbook, full pagewidth FFH FFFFH
00H SFR XRAMP = FFH FF00H

FFH FEFFH
00H SFR XRAMP = FEH FE00H
MOVX @ Ri,A MOVX @ DPTR,A

MOVX A, @ Ri MOVX A, @ DPTR
FFH 01FFH
00H SFR XRAMP = 01H 0100H

FFH 00FFH
00H SFR XRAMP = 00H 0000H

MBK958
Fig.10 Indirect addressing of Auxiliary RAM.
1999 Aug 02 29

SAA55xx
9 REDUCED POWER MODES • The third method of terminating Idle mode is with an
external hardware reset. Since the oscillator is running,
There are three power saving modes: Standby, Idle and
the hardware reset need only be active for two machine
Power-down, incorporated into the OSD only device.
cycles (24 clocks at 12 MHz) to complete the reset
When utilizing any of these modes, power to the device
operation. Reset defines all SFRs and Display memory
(VDDP, VDDC and VDDA) should be maintained, since power
to an initialized state, but maintains all other RAM
saving is achieved by clock gating on a section by section
values. Code execution commences with the Program
basis.
Counter set to ‘0000’.
9.1 Idle mode
9.2 Power-down mode
During Idle mode, Acquisition, Display and the Central
In Power-down mode the crystal oscillator is stopped.
Processing Unit (CPU) sections of the device are disabled.
The contents of all SFRs and Data memory are
The following functions remain active:
maintained, However, the contents of the Auxiliary/Display
• Memory interface memory are lost. The port pins maintain the values defined
• I2C-bus interface by their associated SFRs. Since the output values on RGB
• Timer/Counters and VDS are maintained the display output must be made
inactive before entering Power-down mode.
• Watchdog Timer
The Power-down mode is activated by setting the PD bit in
• Pulse Width Modulators.
the PCON register. It is advised to disable the Watchdog
To enter Idle mode the IDL bit in the PCON register must Timer prior to entering Power-down.
be set. The Watchdog Timer must be disabled prior to
There are three methods of exiting Power-down mode:
entering the Idle mode to prevent the device being reset.
Once in Idle mode, the crystal oscillator continues to run, • An external interrupt provides the first mechanism for
but the internal clock to the CPU, Acquisition and Display waking from Power-down. Since the clock is stopped,
are gated out. However, the clocks to the Memory external interrupts need to be set level sensitive prior to
interface, I2C-bus interface, timer/counters, Watchdog entering Power-down. The interrupt is serviced, and
Timer and Pulse Width Modulators are maintained. following the instruction RETI, the next instruction to be
The CPU state is frozen along with the status of all SFRs, executed will be the one after the instruction that put the
internal RAM contents are maintained, as are the device device into Power-down mode.
output pin values. • A second method of exiting power-down is via an
Since the output values on Red Green Blue (RGB) and the interrupt generated by the SAD DC Compare circuit.
Video Data Switch (VDS) are maintained the display When the device is configured in this mode, detection of
a certain analog threshold at the input to the SAD may
output must be disabled before entering this mode.
be used to trigger wake-up of the device i.e. TV Front
There are three methods to recover from Idle mode: Panel Key-press. As above, the interrupt is serviced,
• Assertion of an enabled interrupt will cause the IDL bit to and following the instruction RETI, the next instruction to
be cleared by hardware, thus terminating Idle mode. be executed will be the one following the instruction that
The interrupt is serviced, and following the instruction put the device into the Power-down.
RETI, the next instruction to be executed will be the one • The third method of terminating the Power-down mode
after the instruction that put the device into Idle mode. is with an external hardware reset. Reset defines all
• A second method of exiting the Idle mode is via an SFRs and Display memory, but maintains all other RAM
interrupt generated by the Software Analog-to-Digital values. Code execution commences with the Program
(SAD) DC Compare circuit. When the device is Counter set to ‘0000’.
configured in this mode, detection of an analog
threshold at the input to the SAD may be used to trigger
wake-up of the device i.e. TV Front Panel Key-press.
As above, the interrupt is serviced, and following the
instruction RETI, the next instruction to be executed will
be the one following the instruction that put the device
into Idle mode.
1999 Aug 02 30

SAA55xx
9.3 Standby mode 10.2.1 OPEN-DRAIN

When Standby mode is entered both Acquisition and The open-drain configuration can be used for bidirectional
Display sections are disabled. The following functions operation of a port. It requires an external pull-up resistor,
remain active: the pull-up voltage has a maximum value of 5.5 V, to allow
• 80C51 core connection of the device into a 5 V environment.
• Memory interface Note that the I2C-bus ports (P1.4, P1.5, P1.6 and P1.7)
can only be configured as open-drain.
• I2C-bus interface
• Timer/Counters 10.2.2 QUASI-BIDIRECTIONAL
• Watchdog Timer
The quasi-bidirectional configuration is a combination of
• Software ADC open-drain and push-pull. It requires an external pull-up
• Pulse Width Modulators resistor to VDDP (nominally 3.3 V). When a signal transition
from LOW-to-HIGH is output from the device, the pad is
To enter Standby mode, the STANDBY control bit in the
put into push-pull configuration for one clock cycle
ROMBK SFR (bit 7) must be set. It can be used in
(166 ns) after which the pad goes into open-drain
conjunction with either Idle or Power-down modes to
configuration. This configuration is used to speed up the
switch between power saving modes. This mode enables
edges of signal transitions. This is the default state of
the 80C51 core to decode either IR remote commands or
operation of the pads after reset.
receive I2C-bus commands without the device being fully
powered.
10.2.3 HIGH-IMPEDANCE
The Standby state is maintained upon exit from either the The high-impedance configuration can be used for input
Idle mode or Power-down mode. No wake-up from only operation of the port. When using this configuration
Standby is necessary as the 80C51 core remains the two output transistors are turned off.
operational.
Since the output values on RGB and VDS are maintained 10.2.4 PUSH-PULL
the display output must be disabled before entering this The push-pull configuration can be used for output only.
mode. In this configuration the signal is driven to either 0 V or
VDDP, which is nominally 3.3 V.
10 I/O FACILITY
10.3 Port alternative functions
10.1 I/O ports
Ports 1, 2 and 3 are shared with alternative functions to
The SAA55xx devices have 29 I/O lines, each is enable control of external devices and circuitry.
individually addressable, or form 3 parallel 8-bit The alternative functions are enabled by setting the
addressable ports which are Port 0, Port 1 and Port 2. appropriate SFR and also writing a logic 1 to the port bit
Port 3 has 5-bit parallel I/Os only.
that the function occupies.
10.2 Port type 10.4 LED support
All individual ports can be programmed to function in one
Port pins P0.5 and P0.6 have a 8 mA current sinking
of four I/O configurations: open-drain, quasi-bidirectional,
capability to enable LEDs in series with current limiting
high-impedance and push-pull. The I/O configuration is
resistors to be driven directly, without the need for
selected using two associated Port Configuration additional buffering circuitry.
Registers: PnCFGA and PnCFGB (where n = port number
0, 1, 2 or 3); see Table 3.
1999 Aug 02 31

SAA55xx
11 INTERRUPT SYSTEM If requests of the same priority level are received

simultaneously, an internal polling sequence determines
The device has six interrupt sources, each of which can be
which request is serviced. Thus, within each priority level
enabled or disabled. When enabled each interrupt can be
there is a second priority structure determined by the
assigned one of two priority levels. There are four
polling sequence as defined in Table 8.
interrupts that are common to the 80C51, two of these are
external interrupts (EX0 and EX1) and the other two are
Table 8 Interrupt priority (within same level)
timer interrupts (ET0 and ET1). In addition to the
conventional 80C51, one application specific interrupt is PRIORITY WITHIN INTERRUPT
SOURCE
incorporated internal to the device which has following LEVEL VECTOR
functionality:
EX0 highest 0003H
• Display Busy interrupt (EBUSY). An interrupt is
ET0 − 000BH
generated when the display enters either a Horizontal or
Vertical Blanking Period. i.e. indicates when the EX1 − 0013H
microcontroller can update the display RAM without ET1 − 001BH
causing undesired effects on the screen. This interrupt ES2 − 002BH
can be configured in one of two modes using the MMR
EBUSY lowest 0033H
Configuration (address 87FFH, bit TXT/V):
– Text Display Busy. An interrupt is generated on each 11.3 Interrupt vector address
active horizontal display line when the Horizontal
Blanking Period is entered The processor acknowledges an interrupt request by
executing a hardware generated LCALL to the appropriate
– Vertical Display Busy. An interrupt is generated on
servicing routine. The interrupt vector addresses for each
each vertical display field when the Vertical Blanking
source are shown in Table 8.
period is entered.
11.4 Level/edge interrupt
11.1 Interrupt enable structure
The external interrupt can be programmed to be either
Each of the individual interrupts can be enabled or
level-activated or transition-activated by setting or clearing
disabled by setting or clearing the relevant bit in the
the IT0/IT1 bits in the Timer Control SFR (TCON).
Interrupt Enable Register (IE). All interrupt sources can
also be globally disabled by clearing the EA bit (IE.7).
Table 9 External interrupt activation
11.2 Interrupt enable priority ITx LEVEL EDGE
Each interrupt source can be assigned one of two priority 0 active LOW −
levels. The interrupt priorities are defined by the Interrupt 1 − INT0 = negative edge
Priority Register (IP). A low priority interrupt can be INT1 = positive and negative edge
interrupted by a high priority interrupt, but not by another
low priority interrupt. A high priority interrupt can not be
interrupted by any other interrupt source. If two requests of The external interrupt INT1 differs from the standard
different priority level are received simultaneously, the 80C51 interrupt in that it is activated on both edges when
request with the highest priority level is serviced. in edge sensitive mode. This is to allow software pulse
width measurement for handling remote control inputs.
1999 Aug 02 32

SAA55xx

H1 highest priority level 1
EX0
L1 highest priority level 0
H2
ET0
L2
H3
EX1
L3
H4
ET1
L4
H5
ES2
L5
H6 lowest priority level 1

EBUSY
L6 lowest priority level 0
GSA033
interrupt source global priority
source enable enable control
SFR IE<0:6> SFR IE.7 SFR IP<0:6>
Fig.11 Interrupt structure.
1999 Aug 02 33

SAA55xx
12 TIMER/COUNTER The 8-bit timer is incremented every ‘t’ seconds where:

1 1
Two 16-bit timers/counters are incorporated Timer 0 and t = 12 × 2048 × -------- = 12 × 2048 × ---------------------6- = 2.048 ms
f osc 12 × 10
Timer 1. Both can be configured to operate as either timers
or event counters. 13.1 Watchdog Timer operation
In Timer mode, the register is incremented on every The Watchdog operation is activated when the WLE bit in
machine cycle. It is therefore counting machine cycles. the Power Control SFR (PCON) is set. The Watchdog can
Since the machine cycle consists of twelve oscillator be disabled by software by loading the value 55H into the
periods, the count rate is 1⁄12fosc = 1 MHz. Watchdog Timer Key SFR (WDTKEY). This must be
performed before entering the Idle or Power-down mode to
In Counter mode, the register is incremented in response
prevent exiting the mode prematurely.
to a negative transition at its corresponding external pin T0
or T1. Since the pins T0 and T1 are sampled once per Once activated the Watchdog Timer SFR (WDT) must be
machine cycle, it takes two machine cycles to recognise a reloaded before the timer overflows. The WLE bit must be
transition, this gives a maximum count rate of set to enable loading of the WDT SFR, once loaded the
1⁄ f
24 osc = 0.5 MHz. WLE bit is reset by hardware, this is to prevent erroneous
software from loading the WDT SFR.
There are six Special Function Registers used to control
the timers/counters. These are: TCON, TMOD, TL0, TH0, The value loaded into the WDT defines the Watchdog
TL1 and TH1. Interval (WI).
The timer/counter function is selected by control bits C/T in WI = ( 256 – WDT ) × t = ( 256 – WDT ) × 2.048 ms
the Timer Mode SFR (TMOD). These two Timer/Counters
The range of intervals is from WDT = 00H which gives
have four operating modes, which are selected by bit-pairs
524 ms to WDT = FFH which gives 2.048 ms.
(M1 and M0) in TMOD. Detail of the modes of operation is
given in “Handbook IC20, 80C51-Based 8-bit
Microcontrollers”. 14 PULSE WIDTH MODULATORS
TL0 and TH0 are the actual Timer/Counter registers for The device has eight 6-bit Pulse Width Modulated (PWM)
Timer 0. TL0 is the low byte and TH0 is the high byte. outputs for analog control of e.g. volume, balance, bass,
TL1 and TH1 are the actual Timer/Counter registers for treble, brightness, contrast, hue and saturation. The PWM
Timer 1. TL1 is the low byte and TH1 is the high byte. outputs generate pulse patterns with a repetition rate of
21.33 µs, with the high time equal to the PWM SFR value
multiplied by 0.33 µs. The analog value is determined by
13 WATCHDOG TIMER
the ratio of the high time to the repetition time, a D.C.
The Watchdog Timer is a counter that once in an overflow voltage proportional to the PWM setting is obtained by
state forces the microcontroller into a reset condition. means of an external integration network (low-pass filter).
The purpose of the Watchdog Timer is to reset the
microcontroller if it enters an erroneous processor state 14.1 PWM control
(possibly caused by electrical noise or RFI) within a
The relevant PWM is enabled by setting the PWM enable
reasonable period of time. When enabled, the Watchdog
bit PWxE in the PWMx Control Register (where x = 0 to 7).
circuitry will generate a system reset if the user program
The high time is defined by the value PWxV<5:0>.
fails to reload the Watchdog Timer within a specified length
of time known as the Watchdog Interval (WI).
The Watchdog Timer consists of an 8-bit counter with an
11-bit prescaler. The prescaler is fed with a signal whose
frequency is 1⁄12fosc (1 MHz for 12 MHz oscillator).
1999 Aug 02 34

SAA55xx
14.2 Tuning Pulse Width Modulator (TPWM) The resolution of the DAC voltage with a nominal value is
3.3⁄ ≈ 13 mV. The external analog voltage has a lower
256
The device has a single 14-bit PWM that can be used for
value equivalent to VSSA and an upper value equivalent to
Voltage Synthesis Tuning. The method of operation is
VDDP − Vtn, where Vtn is the threshold voltage for an N type
similar to the normal PWM except that the repetition period
Metal Oxide Semiconductor transistor. The reason for this
is 42.66 µs.
is that the input pins for the analog signals (P3.0 to P3.3)
are 5 V tolerant for normal port operations, i.e. when not
14.3 TPWM control
used as analog input. To protect the analog multiplexer
Two SFRs are used to control the TPWM, they are TDACL and comparator circuitry from the 5 V, a series transistor is
and TDACH. The TPWM is enabled by setting the used to limit the voltage. This limiting introduces a voltage
TPWE bit in the TDACH SFR. The most significant bits drop equivalent to Vtn (≈0.6 V) on the input voltage.
TD<13:7> alter the high period between 0 and 42.33 µs. Therefore, for an input voltage in the range VDDP to
The seven least significant bits TD<6:0> extend certain VDDP − Vtn the SAD returns the same comparison value.
pulses by a further 0.33 µs, e.g. if TD<6:0> = 01H then
1 in 128 periods will be extended by 0.33 µs, if 14.4.3 SAD DC COMPARATOR MODE
TD<6:0> = 02H then 2 in 128 periods will be extended.
The SAD module incorporates a DC Comparator mode
The TPWM will not start to output a new value until TDACH which is selected using the DC_COMP control bit in the
has been written to. Therefore, if the value is to be SADB SFR. This mode enables the microcontroller to
changed, TDACL should be written before TDACH. detect a threshold crossing at the input to the selected
analog input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or
14.4 Software ADC (SAD) P3.3/ADC3) of the software ADC. A level sensitive
interrupt is generated when the analog input voltage level
Four successive approximation Analog-to-Digital
at the pin falls below the analog output level of the SAD
Converters can be implemented in software by making use
DAC.
of the on-board 8-bit Digital-to-Analog Converter and
Analog Comparator. This mode is intended to provide the device with a
wake-up mechanism from Power-down or Idle mode when
14.4.1 SAD CONTROL a key-press on the front panel of the TV is detected.
The control of the required analog input is done using the The following software sequence should be used when
channel select bits CH<1:0> in the SAD SFR, this selects utilizing this mode for Power-down or Idle:
the required analog input to be passed to one of the inputs 1. Disable INT1 using the IE SFR.
of the comparator. The second comparator input is
generated by the DAC whose value is set by the bits 2. Set INT1 to level sensitive using the TCON SFR.
SAD<7:0> in the SAD and SADB SFRs. A comparison 3. Set the DAC digital input level to the desired threshold
between the two inputs is made when the start compare bit level using SAD/SADB SFRs and select the required
ST in the SAD SFR is set, this must be at least one input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or
instruction cycle after the SAD<7:0> value has been set. P3.3/ADC3) using CH<1:0> in the SAD SFR.
The result of the comparison is given on VHI one 4. Enter DC Compare mode by setting the DC_COMP
instruction cycle after the setting of ST. enable bit in the SADB SFR.
5. Enable INT1 using the IE SFR.
14.4.2 SAD INPUT VOLTAGE
6. Enter Power-down/Idle mode. Upon wake-up the SAD
The external analog voltage that is used for comparison should be restored to its conventional operating mode
with the internally generated DAC voltage does not have by disabling the DC_COMP control bit.
the same voltage range. The DAC has a lower reference
level of VSSA and an upper reference level of VDDP.
1999 Aug 02 35

SAA55xx
handbook, halfpage VDDP
ADC0
ADC1
MUX
4:1
ADC2
ADC3
CH<1:0> VHI
SAD<3:0>
8-BIT
DAC
SADB<3:0>
MBK960
Fig.12 SAD block diagram.
1999 Aug 02 36

SAA55xx
15 I2C-BUS SERIAL I/O 16.1 Memory structure
The I2C-bus consists of a serial data (SDA) line and a The memory is partitioned into two distinct areas, the
serial clock (SCL) line. The definition of the I2C-bus dedicated Auxiliary RAM area, and the Display RAM area.
protocol can be found in the document “The I2C-bus and The Display RAM area when not being used for Data
how to use it (including specification)”. This document may Capture or Display can be used as an extension to the
be ordered using the code 9398 393 40011. auxiliary RAM area.
The device operates in four modes: 16.1.1 AUXILIARY RAM

• Master transmitter
The Auxiliary RAM is not initialised at power-up.
• Master receiver The contents of the Auxiliary RAM area, and the Display
• Slave transmitter RAM are maintained during Standby and Idle modes, but
• Slave receiver. are lost if Power-down mode is entered.
The microcontroller peripheral is controlled by the Serial 16.1.2 DISPLAY RAM

Control SFR (S1CON) and its status is indicated by the
Status SFR (S1STA). Information is transmitted/received The Display RAM (Block 0 only) is initialised on power-up
to/from the I2C-bus using the Data SFR (S1DAT) and the to a value of 20H. The contents of the Display RAM are
Slave Address SFR (S1ADR) is used to configure the maintained when entering Idle mode. If Idle mode is exited
slave address of the peripheral. using an interrupt then the contents are unchanged, if Idle
mode is exited using a reset then the contents are
The byte level I2C-bus serial port is identical to the I2C-bus re-initialised to 20H.
serial port on the P8xCE558, except for the clock rate
selection bits CR<2:0> in S1CON. The operation of the 16.2 Memory mapping
subsystem is described in detail in the “P8xCE558 data
sheet”. The dedicated Auxiliary RAM area occupies 0.75 kbytes,
with an address range from 0000H to 0300H.The Display
RAM occupies 1.25 kbytes with an address range from
15.1 I2C-bus port selection
2000H to 24FFH for TXT mode and 8000H to 84FFH for
Two I2C-bus ports are available SCL0/SDA0 and CC mode. The two modes although having different
SCL1/SDA1. The selection of the port is done using address ranges occupy the same physical DRAM area.
TXT21.I2C PORT 0 and TXT21.I2C PORT 1. When the
port is enabled, any information transmitted from the 16.3 Addressing memory
device goes onto the enabled port. Any information
The memory can be addressed by the microcontroller in
transmitted to the device can only be acted on if the port is
two ways, either directly using a MOVX command, or via
enabled.
Special Function Registers depending on what address is
If both ports are enabled then data transmitted from the required.
device is seen on both ports, however data transmitted to
The dedicated Auxiliary RAM, and Display memory in the
the device on one port can not be seen on the other port.
range 8000H to 86FFH, can only be accessed using the
MOVX command.
16 MEMORY INTERFACE
The Display memory in the range 2000H to 23FFH can
The memory interface controls access to the embedded either be directly accessed using the MOVX, or via the
DRAM, refreshing of the DRAM and page clearing. Special Function Registers.
The DRAM is shared between Data Capture, display and
microcontroller sections.
The Data Capture section uses the DRAM to store
acquired information that has been requested. The display
reads from the DRAM information and converts it into RGB
values. The microcontroller uses the DRAM as embedded
auxiliary RAM.
1999 Aug 02 37

SAA55xx
16.3.1 TXT DISPLAY MEMORY SFR ACCESS 16.4 Page clearing

The Display memory when in TXT mode (see Fig.14) is Page clearing is performed on request from the
configured as 40 columns wide by 25 rows and occupies microcontroller under the control of the embedded
1K × 8 bits of memory. The row and column is selected software.
using TXT9.R<4:0> and TXT10.C<5:0>. The data at the
At power-on and reset the Text Display memory (from
selected position can be read or written using
2000H to 23FFH) is cleared to the value of 20H.
TXT11.D<7:0>.
The TXT13.PAGE CLEARING bit will be set while this
Whenever a read or write is performed on TXT11, the row takes place.
values stored in TXT9 and column value stored in TXT10
are automatically incremented. For rows 0 to 24 the 16.4.1 DATA CAPTURE PAGE CLEAR
column value is incremented up to a maximum of 39, at
Not present in the SAA55xx OSD only devices.
which point it resets to a logic 0 and increments the row
counter value. When row 25 column 23 is reached the
16.4.2 SOFTWARE PAGE CLEAR
values of the row and column are both reset to logic 0.
The software can also initiate a page clear, by setting the
Writing values outside of the valid range for TXT9 or
TXT9.CLEAR MEMORY bit. The CLEAR MEMORY bit is
TXT10 will cause undetermined operation of the
not latched so the software does not have to reset it after
auto-incrementing function for accesses to TXT11.
it has been set.
16.3.2 TXT DISPLAY MEMORY MOVX ACCESS Only one page can be cleared in a TV line so if the
software requests a page clear it will be carried out on the
It is important for the generation of OSD displays, that use
next TV line on which the Data Capture hardware does not
this mode of access, to understand the mapping of the
force the page to be cleared. A flag, TXT13.PAGE
MOVX address onto the display row and column value.
CLEARING, is provided to indicate that a software
This mapping of row and column onto address is shown in
requested page clear is being carried out. The flag is set
Table 10. The values shown are added onto a base
when a logic 1 is written into the TXT9.CLEAR MEMORY
address for the required memory block (see Fig.13) to give
bit and is reset when the page clear has been completed.
a 16-bit address.
Inventory page clearing in not present in the SAA55xx
OSD only devices.
Table 10 Column and row to MOVX address (lower 10 bits of address)

ROW COL.0 ... COL.23 ... COL.31 COL.32 ... COL.39
Row 0 000H ... 017H ... 01FH 3F8H ... 3FFH
Row 1 020H ... 037H ... 03FH 3F0H ... 3F7H
... ... ... ... ... ... ... ... ...
Row 23 2E0H ... 3F7H ... 2FFH 340H ... 347H
Row 24 300H ... 317H ... 31FH 338H ... 33FH
Row 25 320H ... 337H ... ...
1999 Aug 02 38

SAA55xx
lower 32 kbytes upper 32 kbytes

handbook, halfpage 7FFFH FFFFH
23FFH
TEXT DISPLAY
2000H
86FFH
86FFH
AUXILIARY CC DISPLAY
0000H 8000H
GSA011
Fig.13 DRAM memory mapping.
1999 Aug 02 39

SAA55xx
handbook, full pagewidth Column

0 10 20 30 39
Row 0
1 C
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 control data
non-displayable data
0 9 10 23
(byte 10 reserved)
active position TXT9.R<4:0> = 01H, TXT10.C<5:0> = 0AH, TXT11 = 43H
MBK962
Fig.14 TXT memory map.
1999 Aug 02 40

SAA55xx
17 DATA CAPTURE 17.1.4 DATA CAPTURE TIMING

The Data Capture section takes in the analog Composite The Data Capture timing section uses the synchronisation
Video and Blanking Signal (CVBS), and from this extracts information extracted from the CVBS signal to generate
the required data, which is then decoded and stored in the required horizontal and vertical reference timings.
memory.
The timing section automatically recognizes and selects
The extraction of the data is performed in the digital the appropriate timings for either 625 (50 Hz)
domain. The first stage is to convert the analog synchronisation or 525 (60 Hz) synchronisation.
CVBS signal into a digital form. This is done using an
A flag TXT12.VIDEO SIGNAL QUALITY is set when the
ADC sampling at 12 MHz. The data and clock recovery is
timing section is locked correctly to the incoming CVBS
then performed by a Multi-Rate Video Input Processor
signal. When TXT12.VIDEO SIGNAL QUALITY is set
(MulVIP). From the recovered data and clock, the serial
another flag TXT12.525/625 SYNC can be used to identify
Closed Captioning data is converted to parallel and stored
the standard.
as two bytes per line. The extracted data is stored in
SFR locations.
17.1.5 LINE 21 DATA SERVICES
17.1 Data Capture features The Line 21 Data Services is transmitted on line 21 of a
525-line broadcast system and is used for Captioning
• Two CVBS inputs
information, Text information and Extended Data Services.
• Data Capture for Line 21 Data Service Full Details can be found in “Recommended Practise for
• Video Signal Quality Detector. Line 21 Data Service EIA-608”.
Closed Caption Line 21 data is only acquired when
17.1.1 CVBS SWITCH TXT21.CC ON bit is set.
The CVBS switch is used to select the required analog Two bytes of data are stored per field in SFRs, the first bye
input depending on the value of TXT8.CVBS1/CVBS0. is stored in CCDAT1 and the second byte is stored in
CCDAT2. The contents of each CCDAT register are reset
17.1.2 ANALOG-TO-DIGITAL CONVERTER to 00H at the start of the Closed Caption line defined by
The output of the CVBS switch is passed to a differential CCLIN.CS<4:0>. At the end of the Closed Caption line an
to single ended converter, although in this device it is used interrupt is generated if IE.ECC is active.
in single ended configuration with a reference. The analog The processing of the Closed Caption data to convert into
output of the differential to single ended converter is a displayable format is performed by software.
converted into a digital representation by a full-flash ADC
with a sampling rate of 12 MHz.
17.1.3 MULTI-RATE VIDEO INPUT PROCESSOR

The multi-rate video input processor is a Digital Signal
Processor designed to extract the data and recover the
clock from a digitized CVBS signal. The only data and
clock standard that can be recovered in the OSD only
devices is Closed Caption at a data rate of approximately
503.5 kHz.
1999 Aug 02 41

SAA55xx
handbook, full pagewidth CVBS0 CVBS1
CVBS
SWITCH
CVBS
SYNC
ADC SYNC_FILTER
SEPARATOR
data<7:0> VCS
DATA SLICER
ACQUISITION
AND
TIMING
CLOCK RECOVERY
TTC TTD
ACQUISITION
FOR
CC/WSS GSA010
output data to SFRs
Fig.15 Data Capture block diagram.
18 DISPLAY • Globally selectable scan lines per row 9, 10, 13 or 16

The display section is based on the requirements for US • Globally selectable character matrix (H × V) 12 × 9,
Closed Caption. There are some enhancements for use 12 × 10, 12 × 13 or 12 × 16
with locally generated On-Screen Displays. • Italics
The display section reads the contents of the Display • Soft colours using CLUT with 4096 colour palette
memory and interprets the control/character codes. From • Underline
this information and other global settings, the display
• Overline
produces the required RGB signals and video/data (Fast
Blanking) signal for a TV signal processing device. • Fringing (shadow) selectable from N-S-E-W direction
The display is synchronised to the TV signal processing • Fringe colour selectable

device by way of horizontal and vertical sync signals • Meshing of defined area
provided by external circuits (Slave Sync mode). From • Contrast reduction of defined area
these signals all display timings are derived.
• Cursor
18.1 Display features • Special Graphics characters with two planes, allowing
four colours per character
• Teletext style OSD and Enhanced OSD modes
• 32 software redefinable On-Screen Display characters
• US Closed Caption features
• 4 WST character sets (G0/G2) in single device
• Serial and Parallel display attributes (e.g. Latin, Cyrillic, Greek, Arabic)
• Single/double/quadruple width and height for characters • G1 Mosaic graphics, Limited G3 Line drawing
• Scrolling of display region characters
• Variable flash rate controlled by software • WST character sets and Closed (including extended)
Caption character set in a single device.
1999 Aug 02 42

SAA55xx
handbook, full pagewidth CLK VSYNC

HSYNC
DISPLAY
TIMING
address
address PARALLEL/SERIAL
MICROPROCESSOR FUNCTION
data data CONVERTER
INTERFACE REGISTERS
control AND FRINGING
address
address DISPLAY DATA ATTRIBUTE

to memory interface
ADDRESSING HANDLING
data
from memory interface
data
DATA
CLUT RAM
BUFFER
data
CHARACTER
ROM
AND CHARACTER
DRCs address FONT DAC DAC DAC
ADDRESSING
MBK965 R G B FB
Fig.16 Display block diagram.
1999 Aug 02 43

SAA55xx
18.2 Display modes TXT: This attribute is set by the control character ‘flash’
(08H) and remains valid until the end of the row or until
The display section has two distinct modes with different
reset by the control character ‘steady’ (09H).
features available in each. The two modes are:
• TXT: This is the display configured for WST with 18.3.2 BOXES
additional serial and global attributes. The display is
configured as a fixed 25 rows with 40 characters per CC: This attribute is valid from the time set until end of row
row. In the OSD only family this mode can only be or otherwise modified if set with Serial Mode 0. If set with
utilised for display of Text style OSD, no Teletext Data Serial Mode 1, then it is set from the next character
Capture is present. onwards.
• CC: This is the display configured as the US Closed In Text mode (within CC mode) the background colour is
Caption mode. The display is configured as a maximum displayed regardless of the setting of the box attribute bit.
of 16 rows with a maximum of 48 characters per row. Boxes take effect only during mixed mode, where boxes
are set in this mode the background colour is displayed.
In both of the above modes the character matrix, and Character locations where boxes are not set show
TV lines per row can be defined. There is an option of
video/screen colour (depending on the setting in the
9, 10, 13 and 16 TV lines per display row, and a character
MMR Display Control) instead of the background colour.
matrix (H × V) of 12 × 9, 12 × 10, 12 × 13 or 12 × 16. Not all
combinations of TV lines per row and maximum display TXT: Two types of boxes exist, the teletext box and the
rows give a sensible OSD display, since there is a limited OSD box. The teletext box is activated by the ‘start box’
number of TV scan lines available. control character (0BH). Two start box characters are
required to begin a teletext box, with the box starting
Special Function Register TXT21 and memory mapped between the 2 characters. The box ends at the end of the
registers are used to control the mode selection.
line or after a ‘end box’ control character.
18.3 Display feature descriptions TXT mode can also use OSD boxes, they are started using
size, implying OSD control characters (BCH, BDH, BEH
All display features are now described in detail for both and BFH). The box starts after the control character (set
TXT and CC modes. after) and ends either at the end of the row or at the next
size implying OSD character (set at).
18.3.1 FLASH
The attributes flash, teletext box, conceal, separate
Flashing causes the foreground colour pixel to be
graphics, twist and hold graphics are all reset at the start
displayed as the background pixels.The flash frequency is
of an OSD box, as they are at the start of the row.
controlled by software setting and resetting the MMR
OSD boxes are only valid in TV mode which is defined by
Status (see Table 28) at the appropriate interval.
TXT5 = 03H and TXT6 = 03H.
CC: This attribute is valid from the time set (see Table 16)
until the end of the row or until otherwise modified.
1999 Aug 02 44

SAA55xx
18.3.3 SIZE Three vertical sizes are available normal (×1), double (×2)
and quadruple (×4). The control characters ‘normal size’
The size of the characters can be modified in both the
(0CH/BCH) enable normal size, the ‘double height’ or
horizontal and vertical directions.
‘double size’ (0DH/BDH/0FH/BFH) enable double height
CC: Two sizes are available in both the horizontal and characters. Quadruple height characters are achieved by
vertical directions. The sizes available are normal (×1), using double height characters and setting the global
double (×2) height/width and any combination of these. attributes TXT7.DOUBLE HEIGHT (expand) and
The attribute setting is always valid for the whole row. TXT7.BOTTOM/TOP.
Mixing of sizes within a row is not possible.
If double height characters are used in Teletext mode,
TXT: Three horizontal sizes are available normal (×1), single height characters in the lower row of the double
double (×2) and quadruple (×4). The control characters height character are automatically disabled.
‘normal size’ (0CH/BCH) enables normal size, the ‘double
width’ or ‘double size’ (0EH/BEH/0FH/BFH) enables 18.3.4 ITALIC
double width characters.
CC: This attribute is valid from the time set until the end of
Any two consecutive combination of ‘double width’ or the row or otherwise modified. The attribute causes the
‘double size’ (0EH/BEH/0FH/BFH) activates quadruple character foreground pixels to be offset horizontally by
width characters, provided quadruple width characters are 1 pixel per 4 scan lines (interlaced mode). The base is the
enabled by TXT4.QUAD WIDTH ENABLE. bottom left character matrix pixel. The pattern of the
character is indented as shown in Fig.17.
TXT: The Italic attribute is not available.
handbook, full pagewidth 12 × 16 character matrix 12 × 13 character matrix 12 × 10 character matrix

0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10
0
1 indented by 7/6/4
2
3 indented by 6/5/3
4
5 indented by 5/4/2
6
7 indented by 4/3/1
8
9 indented by 3/2/0
10
11 indented by 2/1
12
13 indented by 1/0
14
15 indented by 0
MBK970
Field 1
Field 2
Fig.17 Italic characters.
1999 Aug 02 45

SAA55xx
18.3.5 COLOURS 18.3.7 BACKGROUND COLOUR

A CLUT (Colour Look-Up Table) with 16 colour entries is CC: This attribute is valid from the time set until end of row
provided. The colours are programmable out of a palette or otherwise modified if set with Serial Mode 0. If set with
of 4096 (4 bits per R, G and B). The CLUT is defined by Serial Mode 1, then the colour is set from the next
writing data to a RAM that resides in the MOVX address character onwards.
space of the 80C51.
The background colour can be chosen from all 16 CLUT
entries.
Table 11 CLUT colour values
TXT: The control character ‘new background’ (1DH) is
RED<3:0> GREEN<3:0 BLUE<3:0> COLOUR
used to change the background colour to the current
(B11 TO B8) >(B7 TO B4) (B3 TO B0) ENTRY
foreground colour. The selection is immediate (set at) and
0000 0000 0000 0 remains valid until the end of the row or until otherwise
0000 0000 1111 1 modified.
.... .... .... ..
The Text background control characters map to the CLUT
1111 1111 0000 14 entries as shown in Table 13.
1111 1111 1111 15
Table 13 Background CLUT mapping
18.3.6 FOREGROUND COLOUR
CONTROL DEFINED
CLUT ENTRY
CC: The foreground colour can be chosen from 8 colours CODE COLOUR
on a character-by-character basis. Two sets of 8 colours 00H + 1DH black 8
are provided. A serial attribute switches between the
01H + 1DH red 9
banks (see Table 16, Serial Mode 1, bit 7). The colours are
the CLUT entries 0 to 7 or 8 to 15. 02H + 1DH green 10
03H + 1DH yellow 11
TXT: The foreground colour is selected via a control
04H + 1DH blue 12
character (see Table 16). The colour control characters
05H + 1DH magenta 13
take effect at the start of the next character (set-after) and
remain valid until the end of the row, or until modified by a 06H + 1DH cyan 14
control character. Only 8 foreground colours are available. 07H + 1DH white 15
The text foreground control characters map to the CLUT

18.3.8 BACKGROUND DURATION
entries is shown in Table 12.
The attribute when set takes effect from the current
Table 12 Foreground CLUT mapping position until the end of the text display defined in the MMR
Text Area End.
CONTROL DEFINED
CLUT ENTRY
CODE COLOUR CC: The background duration attribute (see Table 16,
00H black 0 Serial Mode 1, bit 8) in combination with the End Of Row
attribute (see Table 16, Serial Mode 1, bit 9) forces the
01H red 1
background colour to be displayed on the row until the end
02H green 2 of the text area is reached.
03H yellow 3
TXT: This attribute is not available.
04H blue 4
05H magenta 5
06H cyan 6
07H white 7
1999 Aug 02 46

SAA55xx
18.3.9 UNDERLINE CC: The fringe attribute (see Table 16, Serial Mode 0,
bit 9) is valid from the time set until the end of the row or
The underline attribute causes the characters to have the
otherwise modified.
bottom scan line of the character cell forced to foreground
colour, including spaces. If background duration is set, TXT: The display of fringing in TXT mode is controlled by
then underline is set until the end of the text area. the TXT4.SHADOW ENABLE bit.
CC: The underline attribute (see Table 16, Serial Mode When set, all the alphanumeric characters being displayed
0/1, bit 4) is valid from the time set until the end of row or are shadowed, graphics characters are not shadowed.
otherwise modified.
18.3.13 MESHING
The attribute effects the background colour being
18.3.10 OVERLINE displayed. Alternate pixels are displayed as the
background colour or video.The structure is offset by
The overline attribute causes the characters to have the
1 pixel from scan line to scan line, thus achieving a
top scan line of the character cell forced to foreground
checker board display of the background colour and video.
colour, including spaces. If background duration is set,
An example of meshing is shown in Fig.19.
then overline is set until the end of the text area.
CC: The setting of the MSH bit in MMR Display Control
CC: The overline attribute (see Table 16, Serial Mode 0/1,
has the effect of meshing any background colour.
bit 5) is valid from the time set until end of row or otherwise
modified. Overlining of italic characters is not possible. TXT: There are two meshing attributes one that only
affects black background colours TXT4.B MESH ENABLE
and a second that only affects backgrounds other than
black TXT4.C MESH ENABLE. A black background is
18.3.11 END OF ROW
defined as CLUT entry 8, a non-black background is
CC: The number of characters in a row is flexible and can defined as CLUT entry 9 to 15.
be determined by the end of row attribute (see Table 16,
Serial Mode 1, bit 9). However, the maximum number of 18.3.14 CURSOR
character positions displayed is determined by the setting
The cursor operates by reversing the background and
of the MMR Text Position Horizontal and MMR Text Area
foreground colours in the character position pointed to by
End.
the active cursor position. The cursor is enabled using
Note that when using the end of row attribute the next TXT7.CURSOR ON. When active, the row the cursor
character location after the attribute should always be appears on is defined by TXT9.R<4:0> and the column is
occupied by a ‘space’. defined by TXT10.C<5:0>. The position of the cursor can
be fixed using TXT9.CURSOR FREEZE. The cursor
TXT: This attribute is not available, row length is fixed at
display is shown in Fig.20.
40 characters.
CC: The valid range for row is 0 to 15. The valid range for
18.3.12 FRINGING column is 0 to 47. The cursor remains rectangular at all
times, its shape is not affected by italic attribute, therefore
A fringe (shadow) can be defined around characters.
it is not advised to use the cursor with italic characters.
The fringe direction is individually selectable in any of the
North, South, East and West direction using the TXT: The valid range for row positioning is 0 to 24.
MMR Fringing Control. The colour of the fringe can also be The valid range for column is 0 to 39.
defined as one of the entries in the CLUT, again using
MMR Fringing Control. An example of south and
south-west fringing is shown in Fig.18.
1999 Aug 02 47

SAA55xx
MBK972
Fig.18 South and south-west fringing.
MBK973
Fig.19 Meshing and Meshing/fringing (south + west).
AB C D E F
MBK971
Fig.20 Cursor display.
1999 Aug 02 48

SAA55xx
18.3.15 SPECIAL GRAPHICS CHARACTERS Table 14 Special character colour allocation

CC/TXT: Several special characters are provided for PLANE 1 PLANE 0 COLOUR ALLOCATION
improved OSD effects. These characters provide a choice 0 0 background colour
of four colours within a character cell. The total number of
0 1 foreground colour
special graphics characters is limited to 16. They are
1 0 CLUT entry 6
stored in the character codes 8XH and 9XH of the
character table (32 ROM characters), or in the DRCs 1 1 CLUT entry 7
which overlay character codes 8XH and 9XH. Each
special graphics character uses two consecutive normal If the screen colour is transparent (implicit in mixed mode)
characters. and inside the object the box attribute is set, then the
Fringing, underline and overline is not possible for special object is surrounded by video. If the box attribute is not set
graphics characters. Special graphics characters are the background colour inside the object will also be
activated when TXT20.OSD PLANES = 1. displayed as transparent.
handbook, full pagewidth background colour serial attribute background colour

"set at" (Mode 0) "set after" (Mode 1)
VOLUME
background colour foreground colour

normal character
foreground colour 7 foreground colour 6
special character MGK550
This example could also be done with 8 special characters.
Fig.21 Special character example.
1999 Aug 02 49

SAA55xx
18.4 Character and attribute coding Table 15 Parallel character coding

This section describes the character and attribute coding BITS DESCRIPTION
for each mode. 0 to 7 8 bit character code
8 to 10 3 bits for 8 foreground colours
18.4.1 CC MODE
11 mode bit: 0 = Parallel code
Character coding is split into character oriented attributes
(parallel) and character group coding (serial). The serial 18.4.2 TXT MODE
attributes take effect either at the position of the attribute
(set at), or at the following location (set after) and remain Character coding is in a serial format, with only one
effective until either modified by a new serial attribute or attribute being changed at any single location. The serial
until the end of the row. A serial attribute is represented as attributes take effect either at the position of the attribute
a space (the space character itself however is not used for (set at), or at the following location (set after). The attribute
this purpose), the attributes that are still active, remains effective until either modified by new serial
e.g. overline and underline will be visible during the display attributes or until the end of the row.
of the space. The default settings at the start of a row are:
The default setting at the start of a row is: • Foreground colour white (CLUT address 7)
• ×1 size • Background colour black (CLUT address 8)
• Flash off • Horizontal size ×1, vertical size ×1 (normal size)
• Overline off • Alphanumeric on
• Underline off • Contiguous mosaic graphics
• Italics off • Release mosaics
• Display mode = superimpose • Flash off
• Fringing off • Box off
• Background colour duration = 0 • Conceal off
• End of row = 0. • Twist off.
The coding is done in 12-bit words. The codes are stored The attributes have individual codes which are defined in
sequentially in the Display memory. A maximum of the basic character table (see Fig.22).
768 character positions can be defined for a single display.
1999 Aug 02 50

SAA55xx
Table 16 Serial character coding

DESCRIPTION
BIT SERIAL MODE 0 SERIAL MODE 1
(SET AT) CHAR.POS. 1 (SET AT) CHAR.POS. >1 (SET AFTER)
0 to 3 4 bits for 16 background colours 4 bits for 16 background colours 4 bits for 16 background colours
4 Underline switch: Horizontal size: Underline switch:
0 = underline off 0 = normal 0 = underline off
1 = underline on 1 = ×2 1 = underline on
5 Overline switch: Vertical size: Overline switch:
0 = overline off 0 = normal 0 = overline off
1 = overline on 1 = ×2 1 = overline on
6 Display mode: Display mode: Display mode:
0 = superimpose 0 = superimpose 0 = superimpose
1 = boxing 1 = boxing 1 = boxing
7 Flash switch: Foreground colour switch: Foreground colour switch:
0 = flash off 0 = Bank 0 (colours 0 to 7) 0 = Bank 0 (colours 0 to 7)
1 = flash on 1 = Bank 1 (colours 8 to 15) 1 = Bank 1 (colours 8 to 15)
8 Italics switch Background colour duration: Background colour duration (set
0 = italics off 0 = stop BGC at):
1 = italics on 1 = set BGC to end of row 0 = stop BGC
1 = set BGC to end of row
9 Fringing switch: End of row: End of row (set at):
0 = fringing off 0 = continue row 0 = continue row
1 = fringing on 1 = end row 1 = end row
10 Switch for serial coding: Switch for serial coding: Switch for serial coding
0 = mode 0 0 = mode 0 0 = mode 0
1 = mode 1 1 = mode 1 1 = mode 1
11 Mode bit: Mode bit: Mode bit:
1 = serial code 1 = serial code 1 = serial code
1999 Aug 02 51
1999 Aug 02
E/W = 0 E/W = 1

B b7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
I
T b6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1
S b5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1
b4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1
b3 b2 b1 b0
column
r 0 1 2 2a 3 3a 4 5 6 6a 7 7a 8 8a 9 9a A B C D E F D E F
o
w back-
alpha graphics nat nat
0 0 0 0 0 OSD OSD OSD OSD ground
black black opt opt black
alpha graphics back

0 0 0 1 1 red red OSD OSD OSD OSD ground
red
graphics back-
alpha
0 0 1 0 2 green green OSD OSD OSD OSD ground
green
alpha graphics nat back-

0 0 1 1 3 yellow yellow OSD OSD OSD OSD ground
opt
yellow
alpha graphics back-

nat OSD OSD OSD OSD
0 1 0 0 4 ground
blue blue opt
blue
alpha graphics back-

0 1 0 1 5 magenta OSD OSD OSD OSD ground
magenta
magenta
back-
alpha graphics
0 1 1 0 6 OSD OSD OSD OSD ground
cyan cyan
cyan
alpha back-
graphics
0 1 1 1 7 white OSD OSD OSD OSD ground
white
white
52
conceal
1 0 0 0 8 flash display OSD OSD OSD OSD
1 0 0 1 9 steady contiguous
OSD OSD OSD OSD
graphics
separated
1 0 1 0 A end box OSD OSD OSD OSD
graphics
nat nat
1 0 1 1 B start box twist OSD OSD OSD OSD
opt opt
black normal
normal nat nat
1 1 0 0 C back - OSD OSD OSD OSD size
height opt opt
ground OSD
new double
double back - nat nat
1 1 0 1 D OSD OSD OSD OSD height
height opt opt
ground OSD
double
double hold nat nat
1 1 1 0 E OSD OSD OSD OSD width
width graphics opt opt
OSD
double
double release nat
1 1 1 1 F OSD OSD OSD OSD size
size graphics opt OSD
MBK974
SAA55xx
nat
character dependent on the language of page, refer to National Option characters
opt
OSD customer definable On-Screen Display character
Fig.22 TXT basic character set (Pan-European).


SAA55xx
18.5 Screen and global controls 18.5.3 DISPLAY MODES

A number of attributes are available that affect the whole CC: When attributes superimpose or boxing (see
display region, and cannot be applied selectively to Table 16, Serial Mode 0/1, bit 6) are set, the resulting
regions of the display. display depends on the setting of the following screen
control mode bits in the MMR Display Control.
18.5.1 TV SCAN LINES PER ROW
TXT: The display mode is controlled by the bits in the
The number of TV scan lines per field used for each TXT5 and TXT6 registers. There are three control
display row can be defined, the value is independent of the functions - Text on, Background on and Picture on.
character size being used. The number of lines can be Separate sets of bits are used inside and outside teletext
either 10, 13 or 16 per display row. The number of TV scan boxes so that different display modes can be invoked.
lines per row is defined TXT21.DISP LINES<1:0>. TXT6 is used if the newsflash (C5) or subtitle (C6) bits in
row 25 of the basic page memory are set otherwise TXT5
A value of 9 lines per row can be achieved if the display is
is used. This allows the software to set up the type of
forced into 525-line display mode by
display required on newsflash and subtitle pages (e.g. text
TXT17.FORCE DISP<1:0>, or if the device is in 10 line
inside boxes, TV picture outside) this will be invoked
mode and the automatic detection circuitry within display
without any further software intervention when such a
finds 525-line display syncs.
page is acquired.
18.5.2 CHARACTER MATRIX (H X V) When teletext box control characters are present in the
display page memory, the appropriate box control bit must
There are three different character matrices available,
be set, TXT7.BOX ON 0, TXT7.BOX ON 1 − 23 or
these are 12 x 10, 12 x 13 and 12 x 16. The selection is
TXT7.BOX ON 24. This allows the display mode to be
made using TXT21.CHAR SIZE<1:0> and is independent
different inside the teletext box compared to outside.
of the number of display lines per row.
These bits are present to allow boxes in certain areas of
If the character matrix is less than the number of TV scan the screen to be disabled. The use of teletext boxes for
lines per row then the matrix is padded with blank lines. If OSD messages has been superseded in this device by the
the character matrix is greater than the number of TV scan OSD box concept, but these bits remain to allow teletext
lines then the character is truncated. boxes to be used, if required.
Table 17 Display modes

MOD 0 MOD 1 DISPLAY MODE DESCRIPTION
0 0 Video Disables all display activities, sets the RGB to true black and VDS to video.
1 0 Full Text Displays screen colour at all locations not covered by character foreground
or background colour. The box attribute has no effect.
0 1 Mixed Screen Colour Displays screen colour at all locations not covered by character foreground,
within boxed areas or, background colour.
1 1 Mixed Video Mixed Video mode displays video at all locations not covered by character
foreground, within boxed areas or, background colour.
Table 18 TXT display control bits

PICTURE ON TEXT ON BACKGROUND ON EFFECT
0 0 X Text mode, black screen
0 1 0 Text mode, background always black
0 1 1 Text mode
1 0 X Video mode
1 1 0 Mixed text and TV mode
1 1 1 Text mode, TV picture outside text area
18.5.4 SCREEN COLOUR
1999 Aug 02 53

SAA55xx
Screen colour is displayed from 10.5 ms to 62.5 ms after 18.6.2 DISPLAY MAP
the active edge of the HSYNC input and on TV lines
The display map allows a flexible allocation of data in the
23 to 310 inclusive, for a 625-line display, and lines
memory to individual rows.
17 to 260 inclusive for a 525-line display.
Sixteen words are provided in the display memory for this
CC: The screen colour is defined by the MMR Display
purpose. The lower 10 bits address the first word in the
Control and points to a location in the CLUT table.
memory where the row data starts. This value is an offset
The screen colour covers the full video width. It is visible
in terms of 16-bit words from the start of Display memory
when the Full Text or Mixed Screen Colour mode is set
(8000H). The most significant bit enables the display when
and no foreground or background pixels are being
not within the scroll (dynamic) area.
displayed.
The display map memory is fixed at the first 16 words in
TXT: The register bits TXT17.SCREEN COL<2:0> can be
the Closed Caption display memory.
used to define a colour to be displayed in place of
TV picture and the black background colour. If the bits are
Table 19 Display map bit allocation
all set to zero, the screen colour is defined as ‘transparent’
and TV picture and background colour are displayed as BIT FUNCTION
normal. Otherwise the bits define CLUT entries 9 to 15.
11 Text display enable, valid outside soft
scroll area. 0 = disable; 1 = enable.
18.6 Text display controls
10 This bit is reserved, should be set to
18.6.1 TEXT DISPLAY CONFIGURATION (CC MODE) logic 0.
Two types of areas are possible. The one area is static and 9 to 0 Pointer to row data.
the other is dynamic. The dynamic area allows scrolling of
a region to take place. The areas cannot cross each other.
Only one scroll region is possible.
1999 Aug 02 54

SAA55xx
Display memory Text area ROW
0 0
display
1 possible 1
2 2
3 3
4 4
5 10
6 soft scrolling 11
display Enable
7 display possible 3
map bit = 0
entries 8 4
9 9
10 10
11 11
12 12
13 display 13
14 possible 14
15 15
MBK966
display
data
Fig.23 Display map and data pointers.
1999 Aug 02 55

SAA55xx
18.6.3 SOFT SCROLL ACTION If the number of rows allocated to the scroll counter is
larger than the defined visible scroll area, this allows parts
The dynamic scroll region is defined by the MMR Scroll
of rows at the top and bottom to be displayed during the
Area, MMR Scroll Range, MMR Top Scroll line and the
scroll function. The registers can be written throughout the
MMR Status. The scroll area is enabled when the SCON
field and the values are updated for display with the next
bit is set in MMR Status.
field sync. Care should be taken that the register pairs are
The position of the soft scroll area window is defined using written to by the software in the same field.
the Soft Scroll Position (SSP<3:0>), and the height of the
Only a region that contains only single height rows or only
window is defined using the Soft Scroll Height (SSH<3:0>)
double height rows can be scrolled.
both are in MMR Scroll Range. The rows that are scrolled
through the window are defined using the Start Scroll Row TXT: The display is organised as a fixed size of 25 rows
(STS<3:0>) and the Stop Scroll Row (SPS<3:0>) both are (0 to 24) of 40 columns (0 to 39), This is the standard size
in MMR Scroll Area. for teletext transmissions. The control data in row 25 is not
displayed but is used to configure the display page
The soft scrolling function is done by modifying the Scroll
correctly.
Line (SCL<3:0>) in MMR Top Scroll Line. and the first
scroll row value SCR<3:0> in the MMR Status.
handbook, full pagewidth ROW

0 usable for start scroll row
1 OSD display STS<3:0> e.g. 3
soft scroll position 2
pointer SSP<3:0> e.g. 6 3
should not be used
4
for OSD display
5
6
soft scroll height 7 soft scrolling area
SSH<3:0> e.g. 4 8
9
10 should not be used
11 for OSD display
12
13 usable for start scroll row
14 OSD display SPS<3:0> e.g. 11
15
MBK967
Fig.24 Soft scroll area.
1999 Aug 02 56

SAA55xx
handbook, full pagewidth 0-63

ROW lines
0 row0
1
2
row1 P01 NBC
3 row2
4 row3 scroll area
5 row4 offset
6 row5
7 row6
8 row7
9 row8
Closed Captioning data row n
10
Closed Captioning data row n+1
11 visible area
12 for scrolling
13
14 row13
15 row14
MBK977
Fig.25 CC text areas.
1999 Aug 02 57

SAA55xx

0 39
Row 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 control data
non-displayable data
0 9 10 23
byte 10 reserved
MBK968
Fig.26 TXT text area.
1999 Aug 02 58

SAA55xx
18.7 Display positioning The screen colour extends over a large vertical and
horizontal range so that no offset is needed. The text area
The display consists of the screen colour covering the
is offset in both directions relative to the vertical and
whole screen and the text area that is placed within the
horizontal sync pulses.
visible screen area.
handbook, full pagewidth horizontal sync
screen colour 6 lines

offset = 8 µs offset
text
vertical
offset
SCREEN COLOUR AREA
horizontal
sync
delay vertical
TEXT AREA sync
0.25 character text area start

offset
text area end
56 µs MGL150
Fig.27 Display area positioning.
1999 Aug 02 59

SAA55xx
18.7.1 SCREEN COLOUR DISPLAY AREA Note that the Text Position Vertical Register should not be
set to 00H as the Display Busy interrupt is not generated
This area is covered by the screen colour. The screen
in these circumstances.
colour display area starts with a fixed offset of 8 µs from
the leading edge of the horizontal sync pulse in the
18.8 Character set
horizontal direction. A vertical offset is not necessary.
To facilitate the global nature of the device the character
Table 20 Screen colour display area set has the ability to accommodate a large number of
characters, which can be stored in different matrices.
POSITION 525-LINE
Horizontal Start at 8 µs after leading edge of 18.8.1 CHARACTER MATRICES
horizontal sync for 56 µs.
The character matrices that can be accommodated in both
Vertical Line 9, Field 1 (321, Field 2) to leading display modes are:
edge of vertical sync (line numbering
using 625 standard). (H × V × planes) 12 × 9 × 1, 12 × 10 × 1, 12 × 13 × 1,
12 × 16 × 1.
18.7.2 TEXT DISPLAY AREA These modes allow two colours per character position.
The text area can be defined to start with an offset in both In CC mode two additional character matrices are
the horizontal and vertical direction. available to allow four colours per character.
Table 21 Text display area (H × V × planes) 12 × 13 × 2, 12 × 16 × 2.

The characters are stored physically in ROM in a matrix of
POSITION DESCRIPTION
size either 12 × 10 or 12 × 16.
Horizontal Up to 48 full sized characters per row.
Start position setting from 8 to 64 18.8.2 CHARACTER SET SELECTION
characters from the leading edge of
horizontal sync. Fine adjustment in Four character sets are available in the device. A set can
quarter characters. consist of alphanumeric characters as required by the
WST or US Closed Captioning, Customer definable
Vertical 256 lines (nominal 41 to 297). Start
On-Screen Display characters, and Special Graphic
position setting from leading edge of
characters.
vertical sync, legal values are
4 to 64 lines (line numbering using CC: Only a single character set can be used for display
625 standard). and this is selected using the Basic Set selection
TXT18.BS<1:0>. When selecting a character set in
CC mode, the Twist Set selection TXT19.TS<1:0> should
The horizontal offset is set in the MMR Text Area Start.
be set to the same value as TXT18.BS<1:0> for correct
The offset is done in full width characters using TAS<5:0>
operation.
and quarter characters using HOP<1:0> for fine setting.
The values 00H to 08H for TAS<5:0> will result in a TXT: Two character sets can be displayed at once. These
corrupted display. are the basic G0 set or the alternative G0 set (Twist Set).
The basic set is selected using TXT18.BS<1:0>.
The width of the text area is defined in the MMR Text Area
The alternative/twist character set is defined by
End Register by setting the end character value
TXT19.TS<1:0>. Since the alternative character set is an
TAE<5:0>. This number determines where the
option it can be enabled or disabled using TXT19.TEN,
background colour of the Text Area will end if set to extend
and the language code that is defined for the alternative
to the end of the row. It will also terminate the character
set is defined by TXT19.TC<2:0>.
fetch process thus eliminating the necessity of a row end
attribute. This entails however writing to all positions. The National option table is selected using
TXT18.NOT<3:0>. A maximum of 31 National option
The vertical offset is set in the MMR Text Position Vertical.
tables can be defined when combined with the
The offset value VOL<5:0> is done in number of TV scan
EAST/WEST control bit located in register TXT4.
lines.
1999 Aug 02 60

SAA55xx
An example of the character set selection and definitions

is show in Table 22.
An example of the National option reference table is shown
in Table 23. Only a certain number of national options will
be relevant for each of the Character sets.
Table 22 Character set selection

BS1/TS1 BS0/TS0 CHARACTER SET EXAMPLE LANGUAGE
0 0 Set 0 Latin
0 1 Set 1 Greek
1 0 Set 2 −
1 1 Set 3 Closed Caption
Table 23 National option selection

C12 C13 C14 NOT<3:0> = 0000 NOT<3:0> = 0001 NOT<3:0> = 0010 ... NOT<3:0> = 1110
0 0 0 English Polish English ... Polish
0 0 1 German German German ... German
0 1 0 Swedish Swedish Swedish ... Estonian
0 1 1 Italian Italian Italian ... Lettish
1 0 0 French French French ... Russian
1 0 1 Spanish − Spanish ... Serb-Croat
1 1 0 Czech Czech Turkish ... Czech
1 1 1 − − − ... −
1999 Aug 02 61

SAA55xx
18.9 ROM addressing

Three ROMs are used to generate the correct pixel information. The first contains the National option look-up table, the
second contains the Basic character look-up table and the third contains the Character pixel information.
Although these are individual ROMs, since they do not need to be accessed simultaneously they are all combined into
a single ROM unit.
2400H
CHARACTER PIXEL DATA

(71680 × 12-BIT) 0800H
LOOK-UP SET 3
0600H
≅ 710 TEXT
OR LOOK-UP SET 2
430 TEXT + 176 CC
0400H
0800H LOOK-UP SET 1

0200H
LOOK-UP
BASIC + NATIONAL OPTION
LOOK-UP SET 0
2048 LOCATIONS
0000H 0000H
MBK978
Fig.28 ROM organisation.
1999 Aug 02 62

SAA55xx
18.9.1 CHARACTER TABLE

CC: The character table is shown in Fig.29.
TXT: One of the character set options (Pan-European: Latin) is shown in Fig.22.

Character code columns (bits 4 to 7)
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 ® SP 0 @ P ú p
1 ˚ ! 1 A Q a q
2 1/2 " 2 B R b r
3 ¿ # 3 C S c s
Character code rows (bits 0 to 3)
4 ™ $ 4 D T d t
5 ¢ % 5 E U e u
6 £ & 6 F V f v
7 ´ 7 G W g w
8 à ( 8 H X h x
9 _ ) 9 I Y i y
A è á : J Z j z
B â + ; K [ k ç
C ê , < L é l
D î - = M ] m Ñ
E ô . > N Í n ñ
F û / ? O ó o n
MBK976
Special characters in column 8 and 9
Additional table locations for normal characters
Table locations for normal characters
Fig.29 Closed Caption character table.
1999 Aug 02 63

SAA55xx
18.10 Redefinable characters The remapping of the standard OSD to the DRCs is
activated when the TXT20.DRCS ENABLE bit is set.
A number of Dynamically Redefinable Characters (DRCs)
The selection of Normal or Special OSD symbols is
are available. These are mapped onto the normal
defined by the TXT20.OSD PLANES.
character codes, and replace the predefined ROM value.
Each character is stored in a matrix of 12 × 16 × 1
There are 32 DRCs, the first 16 occupy the character
(V × H × planes), this allows for all possible character
codes 80H to 8FH, the second 16 occupy the locations
matrices to be defined within a single location.
90H to 9FH. This allows for 32 DRCs or 16 Special DRCs.

address (HEX) character code
8800
CHARACTER 0 80H
881F
8820 character 0 address (HEX)
CHARACTER 1 81H 00
A
01
883F 02
8840 03
04
CHARACTER 2 82H 05
885F 06
07
08
09
0A
0B
0C
8BC0 0D
0E
CHARACTER 30 9EH 0F
8BDF
12 bits
8BE0
CHARACTER 31 9FH
8BFF MBK969
Fig.30 Organisation of DRC RAM.
1999 Aug 02 64

SAA55xx
18.11 Display synchronization Table 25 RGB brightness

The horizontal and vertical synchronizing signals from the BRI3 TO BRI0 RGB BRIGHTNESS
TV deflection are used as inputs. Both signals can be 0000 lowest value
inverted before being delivered to the Phase Selector
... ...
section.
1111 highest value
CC: The polarity is controlled using either VPOL or HPOL
bits in the MMR Text Position Vertical. 18.15 Contrast reduction
TXT: The TXT1.H POLARITY and TXT1.V POLARITY bits CC: This feature is not available in CC mode.
control the polarity.
TXT: The COR bits in SFRs TXT5 and TXT6 control when
A line locked 12 MHz clock is derived from the 12 MHz free the COR output of the device is activated (i.e. pulled
running oscillator by the Phase Selector. This line locked LOW). This output is intended to act on the TV’s display
clock is used to clock the whole of the Display block. circuits to reduce contrast of the video when it is active.
The horizontal and vertical sync signals are synchronized The result of contrast reduction is to improve the
with the 12 MHz clock before being used in the display readability of the text in a mixed teletext and video display.
section. The bits in the TXT5 and TXT6 SFRs allow the display to
be set up so that, for example, the areas inside teletext
18.12 Video/Data switch (Fast Blanking) polarity boxes will be contrast reduced when a subtitle is being
The polarity of the video/data (Fast Blanking) signal can be displayed but that the rest of the screen will be displayed
inverted. The polarity is set with the VDSPOL bit in the as normal video.
MMR RGB Brightness.
19 MEMORY MAPPED REGISTERS (MMR)
Table 24 Fast blanking signal polarity
The memory mapped registers are used to control the
VDSPOL VDS CONDITION display. The registers are mapped into the microcontroller
0 1 RGB display MOVX address space, starting at address 87F0H and
0 0 Video display extending to 87FFH.
1 0 RGB display
1 1 Video display Table 26 MMR address summary
REGISTER MEMORY
18.13 Video/data switch adjustment FUNCTION
NUMBER ADDRESS
To take into account the delay between the RGB values 0 87F0H Display Control
and the VDS signal due to external buffering, the 1 87F1H Text Position Vertical
VDS signal can be moved in relation to the RGB signals.
2 87F2H Text Area Start
The VDS signal can be set to be either a clock cycle before
3 87F3H Fringing Control
or after the RGB signal, or coincident with the RGB signal.
This is done using VDEL<2:0> in the MMR Configuration. 4 87F4H Text Area End
5 87F5H Scroll Area
18.14 RGB brightness control 6 87F6H Scroll Range
A brightness control is provided to allow the RGB upper 7 87F7H RGB Brightness
output voltage level to be modified. The nominal value is 8 87F8H Status
1 V into a 150 Ω resistor, but can be varied between 9 87F9H reserved
0.7 V and 1.2 V. 10 87FAH reserved
The brightness is set in MMR RGB Brightness. 11 87FBH reserved
12 87FCH HSYNC Delay
13 87FDH VSYNC Sync Delay
14 87FEH Top Scroll Line
15 87FFH Configuration
1999 Aug 02 65

SAA55xx
Table 27 MMR map

87F0 R/W Display SRC3 SRC2 SRC1 SRC0 − MSH MOD1 MOD0 00H
Control
87F1 R/W Text Position VPOL HPOL VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 00H
Vertical
87F2 R/W Text Area HOP1 HOP0 TAS5 TAS4 TAS3 TAS2 TAS1 TAS0 00H
Start
87F3 R/W Fringing FRC3 FRC2 FRC1 FRC0 FRDN FRDE FRDS FRDW 00H
Control
87F4 R/W Text Area − − TAE5 TAE4 TAE3 TAE2 TAE1 TAE0 00H
End
87F5 R/W Scroll Area SSH3 SSH2 SSH1 SSH0 SSP3 SSP2 SSP1 SSP0 00H
87F6 R/W Scroll Range SPS3 SPS2 SPS1 SPS0 STS3 STS2 STS1 STS0 00H
87F7 R/W RGB VDSPOL − − − BRI3 BRI2 BRI1 BRI0 00H
Brightness
87F8 R Status BUSY FIELD SCON FLR SCR3 SCR2 SCR1 SCR0 00H
W − − SCON FLR SCR3 SCR2 SCR1 SCR0 00H
87FC R/W HSYNC − HSD6 HSD5 HSD4 HSD3 HSD3 HSD1 HSD0 00H
Delay
87FD R/W VSYNC − VSD6 VSD5 VSD4 VSD3 VSD2 VSD1 VSD0 00H
Delay
87FE R/W Top Scroll − − − − SCL3 SCL2 SCL1 SCL0 00H
Line
87FF R/W Configuration CC VDEL2 VDEL1 VDEL0 TXT/V − − − 00H
1999 Aug 02 66

SAA55xx
Table 28 MMR bit definition

REGISTER BIT FUNCTION
Display Control
SRC3 to SRC0 screen colour definition
MSH meshing all background colours (logic 1)
MOD1 to MOD0 00 = Video
01 = Full Text
10 = Mixed Screen Colour
11 = Mixed Video
Text Position Vertical
VPOL inverted input polarity (logic 1)
HPOL inverted input polarity (logic 1)
VOL5 to VOL0 display start vertical offset from VSYNC (lines)
Text Area Start
HOP1 to HOP0 fine horizontal offset in quarter of characters
TAS5 to TAS0 text area start
Fringing Control
FRC3 to FRC0 fringing colour, value address of CLUT
FRDN fringe in north direction (logic 1)
FRDE fringe in east direction (logic 1)
FRDS fringe in south direction (logic 1)
FRDW fringe in west direction (logic 1)
Text Area End
TAE5 to TAE0 text area end, in full characters
Scroll Area
SSH3 to SSH0 soft scroll height
SSP3 to SSP0 soft scroll position
Scroll Range
SPS3 to SPS0 stop scroll row
STS3 to STS0 start scroll row
RGB Brightness
VDSPOL VDS polarity
0 = RGB (1), Video (0)
1 = RGB (0), Video (1)
BRI3 to BRI0 RGB brightness control
1999 Aug 02 67

SAA55xx
REGISTER BIT FUNCTION

Status read
BUSY access to display memory could cause display problems (logic 1)
FIELD even field (logic 1)
FLR active flash region background only displayed (logic 1)
SCR3 to SCR0 first scroll row
Status write
SCON scroll area enabled (logic 1)
FLR active flash region background colour only displayed (logic 1)
SCR3 to SCR0 first scroll row
HSYNC Delay
HSD6 to HSD0 HSYNC delay, in full size characters
VSYNC Delay
VSD6 to VSD0 VSYNC delay in number of 8-bit 12 MHz clock cycles
Top Scroll Line
SCL3 to SCL0 top line for scroll
Configuration
CC closed caption mode (logic 1)
VDEL2 to VDEL0 pixel delay between VDS and RGB output
000 = VDS switched to video, not active
001 = VDS active one pixel earlier then RGB
010 = VDS synchronous to RGB
100 = VDS active one pixel after RGB
TXT/V BUSY signal switch; horizontal (logic 1)
1999 Aug 02 68

SAA55xx
20 LIMITING VALUES
In accordance with Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDDX supply voltage (all supplies) −0.5 +4.0 V
VI input voltage (any input) note 1 −0.5 VDD + 0.5 or 4.1 V
VO output voltage (any output) note 1 −0.5 VDD + 0.5 V
IO output current (each output) − ±10 mA
IIOK DC input or output diode current − ±20 mA
Tamb operating ambient temperature −20 +70 °C
Tstg storage temperature −55 +125 °C
Note
1. This maximum value refers to 5 V tolerant I/Os and may be 6 V maximum, but only when VDD is present.
21 CHARACTERISTICS
VDD = 3.3 V ± 10%; VSS = 0 V; Tamb = −20 to +70 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies
VDDX any supply voltage (VDD to VSS) 3.0 3.3 3.6 V
IDDP Periphery supply current note 1 1 − − mA
IDDC core supply current − 12 18 mA
IDDC(id) Idle mode core supply current − 383 600 µA
IDDC(pd) Power-down mode core supply − 666 900 µA
current
IDDC(stb) Standby mode core supply − 5.1 9 mA
current
IDDA analog supply current − 45 48 mA
IDDA(id) Idle mode analog supply current − 444 700 µA
IDDA(pd) Power-down mode analog supply − 433 700 µA
current
IDDA(stb) Standby mode analog supply − 809 950 µA
current
Digital inputs
RESET
VIL LOW-level input voltage − − 1.34 V
VIH HIGH-level input voltage 1.49 − 5.5 V
Vhys hysteresis voltage of Schmitt 0.44 − 0.58 V
trigger input
ILI input leakage current VI = 0 − − 0.17 µA
Rpd equivalent pull-down resistance VI = VDD 55.73 70.71 92.45 kΩ
1999 Aug 02 69

SAA55xx

HSYNC AND VSYNC
trigger input
ILI input leakage current VI = 0 to VDD − − 0.00 µA
Digital outputs
FRAME, VDS
VOL LOW-level output voltage IOL = 3 mA − − 0.13 V
VOH HIGH-level output voltage IOH = 3 mA 2.84 − − V
tr output rise time 10% to 90%; 7.50 8.85 10.90 ns
CL = 70 pF
tf output fall time 10% to 90%; 6.70 7.97 10.00 ns
CL = 70 pF
COR (OPEN-DRAIN OUTPUT)
VOH HIGH-level pull-up output voltage IOL = −3 mA; 2.84 − − V
push-pull
tf output rise time 10% to 90%; 7.20 8.64 11.10 ns
CL = 70 pF
output fall time 10% to 90%; 4.90 7.34 9.40 ns
CL = 70 pF
Digital input/outputs
P0.0 TO P0.4, P0.7, P1.0 TO P1.1, P2.1 TO P2.7, P3.0 TO P3.7
trigger input
VOH HIGH-level output voltage IOH = −4 mA 2.81 − 5.50 V
push-pull
CL = 70 pF
push-pull
CL = 70 pF
1999 Aug 02 70

SAA55xx

P1.2, P1.3 AND P2.0
trigger input
push-pull
CL = 70 pF
push-pull
CL = 70 pF
P0.5 AND P0.6
Vhys hysteresis of Schmitt trigger input 0.42 − 0.58 V
push-pull
CL = 70 pF
push-pull
CL = 70 pF
P1.4 TO P1.7 (OPEN-DRAIN)
trigger input
CL = 70 pF
Analog inputs
CVBS0 AND CVBS1
Vsync sync voltage amplitude 0.1 0.3 0.6 V
Vvid(p-p) video input voltage amplitude 0.7 1.0 1.4 V
(peak-to-peak value)
Zsource source impedance 0 − 250 Ω
1999 Aug 02 71

SAA55xx

VIH HIGH-level input voltage 3.0 − VDDA + 0.3 V
CI input capacitance − − 10 pF
IREF
Rgnd resistor to ground resistor − 24 − kΩ
tolerance 2%
ADC0 TO ADC3
VIH HIGH-level input voltage − − VDDA V
VPE
VIH HIGH-level input voltage − − 9.0 V
Analog outputs
R, G AND B
IOL output current (Black Level) VDDA = 3.3 V −10 − +10 µA
IOH output current (maximum VDDA = 3.3 V 6.0 6.67 7.3 mA
Intensity) Intensity level
code = 15 dec
output current (70% of full VDDA = 3.3 V 4.2 4.7 5.1 mA
Intensity) Intensity level
code = 0 dec
Rload load resistor to VSSA resistor − 150 − Ω
tolerance 5%
CL load capacitance − − 15 pF
Analog input/output
SYNC_FILTER
Csync storage capacitor to ground − 100 − nF
Vsync sync filter level voltage for 0.35 0.55 0.75 V
nominal sync amplitude
Crystal oscillator
XTALIN
VIL LOW-level input voltage VSSA − − V
VIH HIGH-level input voltage − − VDDA V
XTALOUT
CO output capacitance − − 10 pF
1999 Aug 02 72

SAA55xx

Crystal specification; notes 2 and 3
fxtal nominal frequency fundamental − 12 − MHz
mode
CL crystal load capacitance − − 30 pF
C1 crystal motional capacitance Tamb = 25 °C − − 20 fF
Rr resonance resistance Tamb = 25 °C − − 60 Ω
Cosc capacitors at XTALIN, XTALOUT Tamb = 25 °C − note 4 − pF
C0 crystal holder capacitance Tamb = 25 °C − − note 5 pF
Txtal temperature range −20 +25 +85 °C
Xj adjustment tolerance Tamb = 25 °C − − ±50 × 10−6
Xd drift − − ±100 × 10−6
Notes
1. Peripheral current is dependent on external components and voltage levels on I/Os.
2. Crystal order number 4322 143 05561.
3. If the 4322 143 05561 crystal is not used, then the formulae in the crystal specification should be used. Where
CIO = 7 pF, the mean of the capacitances due to the chip at XTALIN and at XTALOUT. Cext is a value for the mean
of the stray capacitances due to the external circuit at XTALIN and XTALOUT. The maximum value for the crystal
holder capacitance is to ensure start-up − Cosc may need to be reduced from the initially selected value.
4. C osc(typ) = 2C L – ( C IO – C ext )
1
5. C 0(max) = 35 – --- ( C osc + C IO + C ext )
2
1999 Aug 02 73

SAA55xx
Table 29 I2C-bus characteristics

FAST-MODE I2C-bus
SYMBOL PARAMETER UNIT
MIN. MAX.
fSCL SCL clock frequency 0 400 kHz
tBUF bus free time between a STOP and START condition 1.3 − µs
tHD;STA hold time (repeated) START condition. After this period, the first 0.6 − µs
clock pulse is generated.
tLOW LOW period of the SCL clock 1.3 − µs
tHIGH HIGH period of the SCL clock 0.6 − µs
tSU;STA set up time for a repeated START condition 0.6 − µs
tHD;DAT data hold time; notes 1 and 2 0 0.9 µs
tSU;DAT data set up time; note 3 100 − ns
tr rise time of both SDA and SCL signals; note 4 20 300 ns
tf fall time of both SDA and SCL signals; note 4 20 300 ns
tSU;STO set up time for STOP condition 0.6 − µs
Cb capacitive load for each bus line − 400 pF
Notes
1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL
signal) in order to bridge the undefined region of the falling edge of SCL.
2. The maximum fHD;DAT has only to be met if the device does not stretch the LOW period tLOW of the SCL signal.
3. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line
is released.
4. Cb = total capacitance of one bus line in pF.
1999 Aug 02 74

SAA55xx
22 QUALITY AND RELIABILITY

This device will meet Philips Semiconductors General Quality Specification for Business group “Consumer Integrated
Circuits SNW-FQ-611-Part E”. The principal requirements are shown in Tables 30 to 33.
Table 30 Acceptance tests per lot

TEST REQUIREMENTS
Mechanical cumulative target: <80 ppm
Electrical cumulative target: <100 ppm
Table 31 Processability tests (by package family)

TEST REQUIREMENTS
Solderability 0/16 on all lots
Mechanical 0/15 on all lots
Solder heat resistance 0/15 on all lots
Table 32 Reliability tests (by process family)

TEST CONDITIONS REQUIREMENTS
Operational life 168 hours at Tj = 150 °C <1000 FPM at Tj = 150 °C
Humidity life temperature, humidity, bias 1000 hours, <2000 FPM
85 °C, 85% RH (or equivalent test)
Temperature cycling Tstg(min) to Tstg(max) <2000 FPM
performance
Table 33 Reliability tests (by device type)

TEST CONDITIONS REQUIREMENTS
ESD and latch-up ESD Human body model 100 pF, 1.5 kW 2000 V
ESD Machine model 200 pF, 0 W 200 V
latch-up 100 mA, 1.5 × VDD (absolute maximum)
Notes to Tables 30 to 33
1. ppm = fraction of defective devices, in parts per million.
2. FPM = fraction of devices failing at test condition, in Failures Per Million.
3. FITS = Failures In Time Standard.
1999 Aug 02 75
dbook, full pagewidth

1999 Aug 02
23 APPLICATION INFORMATION
40 V VDD VDD
A0 VDD
A1 RC
Vtune PH2369 EEPROM
VDD VDD A2 PCF8582E SCL
VSS SDA
47 µF 100 nF
VDD
VSS VSS VSS
VSS
VDD VSS
P2.0/TPWM P1.5/SDA1
1 52
P2.1/PWM0 P1.4/SCL1
brightness 2 51
P2.2/PWM1 P1.7/SDA0
contrast 3 50
P2.3/PWM2 P1.6/SCL0 TV
saturation 4 49 control
P2.4/PWM3 P1.3/T1 signals
hue 5 48
P2.5/PWM4 P1.2/INT0
volume (L) 6 47
P2.6/PWM5 P1.1/T0
volume (R) 7 46
P2.7/PWM6 P1.0/INT1
8 45
VSS VDDP VDD
P3.0/ADC0 IR
9 44
Vafc 10 µF RECEIVER
P3.1/ADC1 RESET VDD
AV status 10 43
P3.2/ADC2 XTALOUT
11 42
12 MHz
P3.3/ADC3 XTALIN
12 41 VDD
76
program+
VSSD OSCGND 56 pF
13 40
VSS VDD 100 nF 47 µF
P0.0 SAA55xx VDDC
program− VHF-L 14 39
VSSP VSS
P0.1
VHF-H 15 38
P0.2 VSS
TV control VSYNC
menu UHF 16 37 field flyback
signals
P0.3 HSYNC
17 36 line flyback
P0.4 VDS
18 35
minus(−)
P0.5 R
19 34
VDD 1 kΩ P0.6 33 G
plus(+) 20
P0.7 32 B
VSS 1 kΩ 21
VSSA VDDA VDD to TV’s
31
VSS 22 150 Ω VDD display
CVBS0 P3.4/PWM7 circuits
30
23
100 nF CVBS1 COR
24 29 VSS
100 nF SYNC_FILTER VPE
CVBS (IF)
25 28
VSS
CVBS (SCART) IREF FRAME
26 27
SAA55xx
100 nF 24 kΩ
MBK980
VSS
Fig.31 Application diagram.


SAA55xx
24 ELECTROMAGNETIC COMPATIBILITY (EMC) Using a device socket will unfortunately add to the area
GUIDELINES and inductance of the external bypass loop.
Optimization of circuit return paths and minimisation of A ferrite bead or inductor with resistive characteristics at
common mode emission will be assisted by using a double high frequencies may be utilised in the supply line close to
sided printed-circuit board (PCB) with low inductance the decoupling capacitor to provide a high impedance.
ground plane. To prevent pollution by conduction onto the signal lines
(which may then radiate) signals connected to the
On a single-sided PCB a local ground plane under the
VDD supply via a pull up resistor should not be connected
whole Integrated Circuit (IC) should be present as shown
to the IC side of this ferrite component.
in Fig.32. This should be connected by the widest possible
connection back to the PCB ground connection, and bulk OSCGND should be connected only to the crystal load
electrolytic decoupling capacitor. It should preferably not capacitors and not the local or circuit ground.
connect to other grounds on the way, and no wire links
Physical connection distances to associated active
should be present in this connect. The use of wire links
devices should be short.
increases ground bounce by introducing inductance into
the ground. Output traces should be routed with close proximity to
mutually coupled ground return paths.
The supply pins can be decoupled at the pin to the ground
plane under the IC. This is easily accomplished using
surface mount capacitors, which are more effective than
leaded components at high frequency.
handbook, full pagewidth GND +3.3 V

electrolytic decoupling capacitor (2 µF)
other ferrite beads

GND
connections
VDDC
VDDP
VDDA
SM decoupling capacitors (10 to 100 nF)

VSSP
under-IC GND plane under-IC GND plane

GND connection
note: no wire links
IC
VSSC VSSA MBK979
Fig.32 Power supply connections for EMC.
1999 Aug 02 77

SAA55xx
25 PACKAGE OUTLINES
SDIP52: plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1
seating plane
D ME
A2 A
L
A1
c
Z e w M (e 1)
b1
MH
b
52 27
pin 1 index
E
1 26
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A A1 A2
b b1 c D (1) E (1) e e1 L ME MH w Z (1)
max. min. max. max.
1.3 0.53 0.32 47.9 14.0 3.2 15.80 17.15
mm 5.08 0.51 4.0 1.778 15.24 0.18 1.73
0.8 0.40 0.23 47.1 13.7 2.8 15.24 15.90
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
90-01-22
SOT247-1
95-03-11
1999 Aug 02 78

SAA55xx
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
c
y
X
A
75 51
76 50
ZE
E HE A A2 (A 3)
A1
w M
θ
bp
Lp
L
pin 1 index
100 detail X
26
1 25
ZD v M A
e w M
bp
D B
HD v M B
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y Z D (1) Z E (1) θ
o
1.6 0.20 1.5 0.28 0.18 14.1 14.1 16.25 16.25 0.75 1.15 1.15 7
mm 0.25 0.5 1.0 0.2 0.12 0.1
0.05 1.3 0.16 0.12 13.9 13.9 15.75 15.75 0.45 0.85 0.85 0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
95-12-19
SOT407-1
97-08-04
1999 Aug 02 79

SAA55xx
26 SOLDERING The total contact time of successive solder waves must not
exceed 5 seconds.
26.1 Introduction to soldering through-hole mount
packages The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
This text gives a brief insight to wave, dip and manual
specified maximum storage temperature (Tstg(max)). If the
soldering. A more in-depth account of soldering ICs can be
printed-circuit board has been pre-heated, forced cooling
found in our “Data Handbook IC26; Integrated Circuit
may be necessary immediately after soldering to keep the
Packages” (document order number 9398 652 90011).
temperature within the permissible limit.
Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit 26.3 Manual soldering
board.
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
26.2 Soldering by dipping or by solder wave
2 mm above it. If the temperature of the soldering iron bit
The maximum permissible temperature of the solder is is less than 300 °C it may remain in contact for up to
260 °C; solder at this temperature must not be in contact 10 seconds. If the bit temperature is between
with the joints for more than 5 seconds. 300 and 400 °C, contact may be up to 5 seconds.
26.4 Suitability of through-hole mount IC packages for dipping and wave soldering methods
SOLDERING METHOD
PACKAGE
DIPPING WAVE
DBS, DIP, HDIP, SDIP, SIL suitable suitable(1)
Note
1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
1999 Aug 02 80

SAA55xx
27 DEFINITIONS
Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
28 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
29 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Aug 02 81

SAA55xx
NOTES
1999 Aug 02 82

SAA55xx
NOTES
1999 Aug 02 83
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Finland: Sinikalliontie 3, FIN-02630 ESPOO, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +358 9 615 800, Fax. +358 9 6158 0920 Tel. +27 11 471 5401, Fax. +27 11 471 5398
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, South America: Al. Vicente Pinzon, 173, 6th floor,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 04547-130 SÃO PAULO, SP, Brazil,
Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +55 11 821 2333, Fax. +55 11 821 2382
Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Spain: Balmes 22, 08007 BARCELONA,
Hungary: see Austria Tel. +34 93 301 6312, Fax. +34 93 301 4107
India: Philips INDIA Ltd, Band Box Building, 2nd floor, Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Tel. +91 22 493 8541, Fax. +91 22 493 0966 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Indonesia: PT Philips Development Corporation, Semiconductors Division, Tel. +41 1 488 2741 Fax. +41 1 488 3263
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14, Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
Tel. +353 1 7640 000, Fax. +353 1 7640 200 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, Tel. +66 2 745 4090, Fax. +66 2 398 0793
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Tel. +39 039 203 6838, Fax +39 039 203 6800 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Tel. +82 2 709 1412, Fax. +82 2 709 1415 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +1 800 234 7381, Fax. +1 800 943 0087
Tel. +60 3 750 5214, Fax. +60 3 757 4880 Uruguay: see South America
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Vietnam: see Singapore
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors, Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1999 SCA 67

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands 545004/01/pp84 Date of release: 1999 Aug 02 Document order number: 9397 750 05737

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INTEGRATED CIRCUITS

TV microcontrollers with Closed Captioning (CC)

CONTENTS 15.1 I2C-bus port selection

TV microcontrollers with Closed Captioning (CC)

TV microcontrollers with Closed Captioning (CC)

3 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

TV microcontrollers with Closed Captioning (CC)

handbook, full pagewidth TV CONTROL

ROM MICROPROCESSOR SRAM

Fig.1 Block diagram (top level architecture).

TV microcontrollers with Closed Captioning (CC)

Fig.2 SDIP52 pin configuration.

TV microcontrollers with Closed Captioning (CC)

Fig.3 LQFP100 pin configuration.

TV microcontrollers with Closed Captioning (CC)

6.2 Pin description

TV microcontrollers with Closed Captioning (CC)

TV microcontrollers with Closed Captioning (CC)

7 MICROCONTROLLER 8 MEMORY ORGANIZATION

TV microcontrollers with Closed Captioning (CC)

handbook, full pagewidth MEMORY SECURITY BITS INTERACTION

PROGRAM ROM USER ROM PROGRAMMING VERIFY

CHARACTER ROM USER ROM PROGRAMMING VERIFY

Fig.4 Memory and security bit structures.

handbook, full pagewidth MEMORY SECURITY BITS SET

USER ROM PROGRAMMING VERIFY

Fig.5 Security bits for production devices.

TV microcontrollers with Closed Captioning (CC)

handbook, full pagewidth MEMORY SECURITY BITS SET

USER ROM PROGRAMMING VERIFY

Fig.6 Security bits for production blank devices.

handbook, halfpage SPECIAL

Fig.7 Internal data memory.

TV microcontrollers with Closed Captioning (CC)

handbook, halfpage 7FH

R0 10H 4 banks of 8 registers

Fig.8 Lower 128 bytes of internal RAM.

1999 Aug 02 8.4 SFR memory

Table 2 SFR memory map

and On-Screen Display (OSD)

and On-Screen Display (OSD)

TV microcontrollers with Closed Captioning (CC)

Table 3 SFR bit description

TV microcontrollers with Closed Captioning (CC)

TV microcontrollers with Closed Captioning (CC)

TV microcontrollers with Closed Captioning (CC)

TV microcontrollers with Closed Captioning (CC)

TV microcontrollers with Closed Captioning (CC)

TV microcontrollers with Closed Captioning (CC)

TV microcontrollers with Closed Captioning (CC)

TV microcontrollers with Closed Captioning (CC)

TV microcontrollers with Closed Captioning (CC)

TV microcontrollers with Closed Captioning (CC)

8.5 Character set feature bits

Table 4 Character ROM - TXT22 mapping

Table 5 Description of Character ROM address 09FEH bits