CEG2131

Computer Architecture I
Section A: Prof. A. AlDaher
Section B: Prof. Misbah Islam

FINAL Exam, Dec 16, 2005

Duration: 3 Hours
Total marks: 100, Weighted Marks: 40

CLOSED BOOK: No notes or texts permitted

PLEASE PROVIDE THE FOLLOWI_______________ First Name: ___________________

Signature: ______________________

Instructions:
For use of grader
1. Please write down your SECTION Number. A 20
2. No notes or texts are permitted. You have to abide by the B 30
University’s regulations regarding the conduct of exams. C 30
3. You may use the back of the pages for any side work that D 20
will not be marked. Total 100
4. Calculators are not allowed.
5. You can refer to the Appendix, ARC Reference
page for Assembly language instruction,
instruction and ALU codes and Microinstruction
word formats.
6. Write down any assumptions that you may make.

page 1 of 12
Part A: Arithmetic (20)
Assuming a system with a 6-bit biased exponent (i.e. excess 32) and a 10-bit two’s complement
mantissa. Perform the following operation.
157.3
- 12.6

By completing the following steps (give your answer for each step, each step has 2 marks)

(i) convert 157.3 to binary

100 111 01 . 010 01

(ii) Normalize the fixed-point binary number (place the radix point immediately to the left of the
leftmost, nonzero digit in the fraction)

0.10 011 101 010 01 X 28

(iii) Round the mantissa to 10 bits.

0.100 111 011

(iv) Write how the floating point number would be stored

101 000 010 011 101 1

(v) Convert 12.6 to normalized floating point number and rounded to 10 bits.

0.110 010 011 X 24

(vi) Form the two’s complement of the mantissa for the 12.6

1.001 101 101

(vii) Equalize exponents

1.111 100 110 X 28

(ix) Perform addition and give your final restult

0.100 100 001 X 28 = 100 100 00 . 1

(x) Convert your result into decimal and compare to exact answer.

Your result = …144.5………………………………..

Exact result = …144.7……………………………..

page 2 of 12
Part B: ARC Instruction Set Architecture and Assembly Language (30)
Q2. (20) Subroutine and Linkages

The code in ARC assembler language of a main program Myprg is given below. It loads
two numbers num1 and num2 and passes these as arguments to a subroutine Mysub
that subtracts these numbers, stores the result onto the stack and returns to Myprog.

.begin
.org 0x1000 ! Start loading program at 4096
%sp equ %r14 ! Let %sp represent %r14
Myprg: ld [num1], %r1 ! %r1  0xDEF
ld [num2], %r2 ! %r2  0xABC
addcc %sp, - 4, %sp ! create space on the stack
st %r1, %sp ! push 0xDEF onto the stack
addcc %sp, - 4, %sp ! create space on the stack
st %r2, %sp ! push 0xABC onto the stack
call MySub ! Jump to Mysub
ld %sp, %r3 ! Store in r3 contents pointed to by sp
num1: 0xDEF
num2: 0xABC
.end

.begin
.org 0x1100 ! Start loading subroutine at 4096+100
Mysub: ld %r14, %r8 ! Pop 0xABC from stack
addcc %r14, 4, %r14 ! Go to down the stack
ld %r14, %r7 ! Pop 0xDEF from stack
subcc %r8, %r7, %r9 ! %r9  %r8 - %r7 0xABC – 0xDEF = -0x222
st %r9, %r14 ! store -0x222 in %r14
jmpl %r15+4, %r0 ! Return to main at ld %sp, %r3 instruction
.end

a. (8) Provide meaningful comments wherever indicated by !

page 3 of 12
b. (8) Assuming that at the start of Myprog the stack pointer register (%r14 ) is
pointing to location 0x4000 and the stack base is 0x5000, show the contents of
the stack
i. Before the call is made from Myprog to Mysub.

0
Free Area

%r15
0xABC
0xDEF
%sp 
Stack
stack base 

232 – 4 

ii. Upon exit from Mysub.

0
Free Area

-0x222
%sp 
Stack
stack base 

232 – 4 

c. (4) What is the contents of register %r3 upon return from Mysub? - 0x222

page 4 of 12
Q3: (10) Multi Address Instructions

The following table gives the instructions available for Three-Address, Two-Address and
the One-Address architecture machine:

Available Instructions
Three-Address Two-Address One-Address
SUB a, b, c ! c  a - b MOV a, b ! b  a LD a ! Acc  a
DIV a, b, c ! c  a/b SUB a, b ! b  b –a ST a ! a  Acc
DIV a, b ! b  b/a SUB a ! Acc  Acc - a
DIV a ! Acc  Acc / a

a. Using the above instructions write down three programs to compute the function
X = (Z / (Y-W)) - Z.

b. Compute the size of your program in bytes. Assume 16-bit opcodes, 32-bit operands
and addresses, and that data is moved to and from memory in 32-bit chunks.

Program to compute X = (Z / (Y-W)) - Z

Three-Address Two-Address One-Address
52 54 40

page 5 of 12
PART C: Data Path and Control (30)
Q4: (10) Micro-programmed Control Unit

Refer to the following microcode segment for the ARC computer:

Address Micro Code Operation

0: R[ir]  AND(R[pc], R[pc]); READ;

1: DECODE;
/ addcc
1600: IF T[IR[13]] THEN GOTO 1602;
1601: R[Rd]  ADDCC (R[rs1], R[rs2]));
GOTO 2047;
1602: R[temp0]  SEXT13 (R[ir]);
1603: R[rd]  ADDCC(R[rs1], R[temp0]);
GOTO 2047;

a. (2) What is the purpose of the AND operation at Line 0?

To put the PC onto the A bus that is connected to the Address
Register of the main Memory, in enable fetching of the
next instruction into the IR

b. (8) What will be the assembled microcode in Microcode memory corresponding to

lines 1600 to 1603. (Look up the Reference section on the last page)

1600: 000000 0 000000 0 000000 0 00 0101 101 11001000010

1601: 000000 1 000000 1 000000 1 00 0011 110 11111111111
1602: 100101 0 000000 0 100001 0 00 1100 000 00000000000
1603: 000000 0 000000 0 000000 0 00 0101 101 11001000110

1600:

1601:

1602:

1603

page 6 of 12
Q5. (20) Hard-wired implementation of Control Signals

The following is the HDL description of the control unit of a small-scale ARC computer.
It has four 32-bit general purpose registers and one 32-bit instruction register.

Module: Small_ARC_Control_Unit
INPUTS:
OUTPUTS:
MEMORY: Rs1 [32], Rs2 [32], Rd[32], ir[32], temp0[32].

! Fetch Instruction from Program Memory at addr = PC

0: ir  AND (PC, PC); READ  1;

! If bit 13 of Ir is set then transfer ir 0:12 bit values

! to register temp0 else transfer the contents of Rs2 to temp0

1: temp0  { SIMM13 (ir) CONDITIONED ON ir [13:],

Rs2 CONDITIONED ON ir[13:]’ };

! If bit31, bit30 = ‘10’ , then it is an Arithmetic Operation

! If bit31, bit30 = ‘11’ then it is memory Read Operation.

2: GOTO { 3 CONDITIONED ON ir[31:] x ir[30:]’,

4 CONDITIONED ON ir[31:] x ir[30:] }.

! Perform the Arithmetic Operation ADD or AND after decoding

! bits 19:24 of ir.

3: Rd  {ADDCC (Rs1, temp0) CONDITIONED ON XNOR ( ir[19:24], 111000)

ANDCC (Rs1, temp0) CONDITIONED ON XNOR ( ir[19:24], 010001)};
GOTO 6.

! Calculate address in the Data memory

4: temp0  ADDCC (Rs1, temp0);
GOTO 5.

! Set up address on the ABus, issue READ command

! and load Register Rd with the contents at the memory address
5: Rd  ANDCC (temp0, temp0); READ  1;
GOTO 6.

! Increment PC by 4 to get to the next instruction

! in the Program Memory
6: PC  INCPC (PC);
GOTO 0.

END SEQUENCE.
END Small_ARC_Control_Unit.

a. (2) How many flip flops will be needed for the state machine for this control unit,
if ONE-HOT encoding approach is employed.
______7_______

page 7 of 12
b. (10) Draw the control unit flip flops and the interconnectivity between them

D Q D Q D Q D Q D Q

FF0 FF1 FF2 FF3 FF6

D Q D Q

FF4 FF5

c. (8) How will you generate the hardwired control signal for the

1. (2) Read operation

= CS0 + CS5

2. (3) Rs2 Selector signal

= CS1. IR[13:]’

3. (3) Rd Selector signal

= CS3 + CS5

page 8 of 12
PART D: Memory Systems (20)
Q6: Memory System Design

Given that RAM chips of type (4 word x 4-bit) shown above are available.
Using these chips draw the diagrams for

a. (7) A 4 word by 12-bit memory system

Answer: identical to 7.3

b. (7) A 16 word by 4-bit memory system

Identical to 7.4

page 9 of 12
c. (6) A Read Only Memory ROM should contain the following words.

Location Value
00 1001
01 1110
10 1010
11 0101

Using OR gates and one 2-to-4 Decoder design the circuit for this ROM.

OR OR OR OR

00
01
10
11
MUX

page 10 of 12
Appendix: ARC Reference Page:
a. ARC Instruction Formats:

b. ALU Function Codes:

ALU Function ALU Condition
A3 A2 A1 A0 Operation Code change
1 0 0 0 ADDCC (A, B) yes
0 1 0 1 ANDCC (A, B) yes
1 0 1 1 SIMM13 (A) no

c,ARC Memory Instruction Register Format (41 bits)

d,Microprogram Memory Address:

page 11 of 12
e: ALU Function Codes:

f: COND field for the Microword

page 12 of 12