CEG 2131 - Fall 2006 - Final

CEG2131 Final exam Page 1 of 16
Université d’Ottawa University of Ottawa

Faculté de genie Faculty of Engineering
École d’ingénierie et de School of Information

technologies de l’information Technology and Engineering
CEG2131A&B Computer Architecture I
Name (surname, first name):____________________________________
Number:___________________________________________________
Please circle CEG2131A CEG2131B
Examiners: Professor A. H. G. Al-Dhaher
Final Examination, December 14, 2006 Time allowed: 3 hours
Notes:
• You may use the back of the pages for any side work. This will not be
marked.
• No notes or texts are permitted. You have to abide by the University’s
regulations regarding the conduct of exams.
• Calculators are not allowed
• Instruction formats and PSR format for the ARC, microcode format and
decode format for microinstruction address are given on page 13.
• ARC ALU operations and COND table are given on page 14.
• Microprogram for the ARC is given on page 15 & 16.
Question 1 (20 marks):

The following 10 questions are a multiple-choice type. Circle the correct answer.
1. Converting (011011)2 to base 16 is equal to:
(a) 1B
(b) 33
(c) 27
(d) None of these
2. Converting (305)10 to three BCD digit is equal to:

(a) 0011 0000 0101
(b) 011 000 101
(c) 0101 0000 0011
(d) None of these
3. The decimal equivalent of the four-bit two’s complement 1111 is equal to:
(a) - 8
(b) – 1
(c) 1
(d) None of these
4. The ARC architecture uses 32 bit integer data type. Each integer is stored as a
collection of bytes. ARC uses:
(a) big-endian format
(b) little-endian format
(c) Both little-endian and big-endian format
(d) None of these
5. In ARC architecture the state of the processor is given by:

(a) PC
(b) SP
(c) Link register
(d) SPR
6. In ARC architecture srl instruction is used to:

(a) Shifts the content of a register to the right and fill the bit to the left with 0s
(b) Shifts the content of a register to the right and copy the last bit
(c) Shifts the content of a register to the right and ignore the bits to the left
(d) None of these
7. In the memory format of ARC instructions for the st instruction the source register is
given by:
(a) register %rd
(b) register %rs1
(c) the addition of %rs1 and %rs2
(d) sim13
8. In ARC architecture, the ALU operation RSHIFT5 (A) do:

(a) Shift the operand on A bus to the right by 5 bits, copying the left most
significant bit into the 5 new bits on the left
(b) Shift the operand on A bus to the right by 5 bits, putting zeros into the 5 new
bits on the left
(c) Shift the operand on A bus to the right by 5 bits, putting ones into the 5 new bits
on the left
(d) None of the above
9. Register transfer language (RTL) is a low level HDL. Each statement consists of:
(a) Data portion and transfer portion.
(b) Transfer portion of many registers.
(c) Line number and transfer portion
(d) None of these.
10. For 64K memory locations you need:

(a) 8 address lines
(b) 10 address lines
(c) 32 address lines
(d) None of the above

Part A (12 marks)
(i) Represent .254 x 103 in a normalized base 8 floating point format with a sign bit,
followed by a 3-bit excess 4 exponent, followed by four base 8 digits.
Solution:
Step #1: Convert to the target base.
.254 x 103 = 25410. Using the remainder method, we find that 25410 = 376 x 80:
254/8 = 31 R 6
31/8 = 3 R 7
3/8 = 0 R 3
Step #2: Normalize: 376 x 80 = .376 x 83.
Step #3: Fill in the bit fields, with a positive sign (sign bit = 0), an exponent of 3 + 4 = 7
(excess 4), and 4-digit fraction = .3760:
0 111 . 011 111 110 000
The radix point may not be written explictly in the bit pattern.
(ii) Write the IEEE 754 single precision bit pattern for +0:
0 00000000 0000 0000 0000 0000 0000 000
(iii) Add (173)10 and (827)10 in signed BCD use the necessary digits in the result.
0001 0111 0011

1000 0010 0111
0001 0000 0000 0000

Part B (8 marks):
Show the process of serial unsigned multiplication for 1101 (multiplicand) multiplied by
1010 (multiplier).
1101
C A Q Comments
1010

Part A (10 marks)
Given two unsigned numbers stored in memory locations X and Y. Write ARC assembly
program to perform XOR operation on these numbers, divide the result by 4 and store the
final result in memory location Z.
Solution:
.begin
org 2048
ld [X] , %r1
ld [Y] , %r2
orncc %r1, %r0, %r3 !complement X
orncc %r2 , %r0 , %r4 !complement Y
andcc %r1, %r4, %r5 ! X Y’
andcc %r3, %r2, %r6 !X’ Y
orcc %r5 , %r6, %r7 ! X Y’ + X’ Y
st %r7 , [Z]
jmpl %r15 + 4 , %r0
.end
Part B (10 marks)

Given two unsigned numbers stored in registers %r1 and %r2. Add these two numbers
and store the result in register %r3. Use the method of subroutine linkage using stack.
Solution:

Part A (10 marks)

On microprogram of ARC line 1604 to 1607 are:
Write the microcode for these lines.
Line 1604
000000 0 000000 0 000000 00 0 0101 101 1100 1000

110
Line 1605
000000 1 000000 1 000000 100 0000 110 1111 1111

111
Line 1606
100101 0 000000 0 100001 0 0 0 1011 000 0000 0000 000
Line 1607
000000 1 100001 0 000000 1 0 0 0000 110 1111 1111 111

Part B (10 marks)

Extend the ARC instruction set to include a new instruction which performs the operation
exclusive NOR on the operands and sets the condition codes accordingly. Name this new
instruction as xnorcc. This new assembler instruction is an Arithmetic format instruction
with op3 field is 010011. Write the microprogram that implements this new instruction
and give comments for each line of cod.
Solution:
A B XOR XNOR
0 0 0 1
1 0 1 0
0 1 1 0
1 1 0 1
XNOR = AB + A B
let rs1 = A, rs2 = B
1612: IF IR[13] THEN GOTO 1614; /is second source operand
/immediate
1613: R[temp0] ← R[rs2]; /get B operand in temp0
GOTO 1615;
1614: R[temp0] ← SIMM13(R[ir]); /Sim B and put it in temp0
1615: R[temp1] ← R[rs1]; GOTO21;
21: R[temp2] ← NOR(R[temp0], R[temp0]); /get complement of B in temp2
22: R[temp3] ← NOR(R[temp1], R[temp1]); /get complement of A in temp3
23: R[temp1] ← AND(R[temp1], R[temp0]); /temp get AND (A,B)
24: R[temp2] ← AND(R[temp3], R[temp2]); temp2 gets AND(A , B)
25: R[rd] ← ORCC(R[temp1], R[temp2]);

CEG2131 Final exam Page 10 of
16

A microprocessor based system is to be designed with:
16Kbyte of ROM starting at address 0 and using 4Kbyte chips
8Kbyte of RAM located at address following the ROM block and using 8Kbyte chip
Eight memory mapped peripheral each requires 32Kbyte in the 256byte range following
the RAM block
(a) Draw the memory map of the system use hexadecimal format to define the
memory range for each of these blocks
(b) Draw the circuit for the address decoder.
Solution:
ROM1 4K 0000-0FFF
ROM2 4K 1000-1FFF
ROM3 4K 2000-2FFF
ROM4 4K 3000-3FFF
RAM 8K 4000-5FFF
P1 32K 6000-601F
P2 32K 6020-603F
P3 32K 6040-605F
P4 32K 6060-607F
P5 32K 6080-609F
P6 32K 60A0-60BF
P7 32K 60C0-60DF
P8 32K 60E0-60FF
ROM line A12-A13 for selection and A0-A11 for memory location
RAM line A14 = 1 and A13 = 0 and A0 to A12 for memory location
P1 to P8 A13 =1 and A14 =1, A5 to A7 for selection, A0 to A4 for memory location

16
16
16
Instruction formats and PSR format for the ARC

16
ARC ALU operations
And the COND table

16
Microprogram for the ARC (continues on next page)

16
Microprogram for the ARC (continued from previous page)

CEG 2131 - Fall 2006 - Final

Uploaded by

Copyright:

Available Formats

CEG 2131 - Fall 2006 - Final

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

CEG 2131 - Fall 2006 - Final

Uploaded by

Copyright:

Available Formats

CEG2131 Final exam Page 1 of 16

Université d’Ottawa University of Ottawa

École d’ingénierie et de School of Information

CEG2131A&B Computer Architecture I

Name (surname, first name):____________________________________

Please circle CEG2131A CEG2131B

Examiners: Professor A. H. G. Al-Dhaher

Final Examination, December 14, 2006 Time allowed: 3 hours

Question 1 (20 marks):

2. Converting (305)10 to three BCD digit is equal to:

5. In ARC architecture the state of the processor is given by:

6. In ARC architecture srl instruction is used to:

8. In ARC architecture, the ALU operation RSHIFT5 (A) do:

10. For 64K memory locations you need:

Question 2 (20 marks):

0 00000000 0000 0000 0000 0000 0000 000

0001 0111 0011

0001 0000 0000 0000

Question 3 (20 marks):

Part A (10 marks)

Part B (10 marks)

Question 4 (20 marks):

Part A (10 marks)

Write the microcode for these lines.

000000 0 000000 0 000000 00 0 0101 101 1100 1000

000000 1 000000 1 000000 100 0000 110 1111 1111

100101 0 000000 0 100001 0 0 0 1011 000 0000 0000 000

000000 1 100001 0 000000 1 0 0 0000 110 1111 1111 111

Part B (10 marks)

let rs1 = A, rs2 = B

1612: IF IR[13] THEN GOTO 1614; /is second source operand

1613: R[temp0] ← R[rs2]; /get B operand in temp0

1614: R[temp0] ← SIMM13(R[ir]); /Sim B and put it in temp0

1615: R[temp1] ← R[rs1]; GOTO21;

21: R[temp2] ← NOR(R[temp0], R[temp0]); /get complement of B in temp2

22: R[temp3] ← NOR(R[temp1], R[temp1]); /get complement of A in temp3

23: R[temp1] ← AND(R[temp1], R[temp0]); /temp get AND (A,B)

24: R[temp2] ← AND(R[temp3], R[temp2]); temp2 gets AND(A , B)

25: R[rd] ← ORCC(R[temp1], R[temp2]);

Question 5 (20 marks):

P1 to P8 A13 =1 and A14 =1, A5 to A7 for selection, A0 to A4 for memory location

Instruction formats and PSR format for the ARC

ARC ALU operations

And the COND table

Microprogram for the ARC (continues on next page)

Microprogram for the ARC (continued from previous page)

You might also like