CEG2136: Computer Architecture I

CEG2536: Architecture des Ordinateurs I

FINAL EXAMINATION
Profs. Voicu Z. Groza and Naim M. Rahmani
• Closed book exam. All electronic devices including calculators are not allowed.
• If in doubt how to interpret a question, make an assumption and elaborate your solution
based on this hypothesis. Explain all your assumptions and well define the symbols used.
• If you finish 10 minutes or less before the due time, remain seated until the end of the exam.
Question
Consider the following logic diagram:

a) What is the C4, S3, S2, S1,

S0 value if:
(1) Register A = 1101, Register
B = 0110, and M=0
(2) Register A = 1101, Register
B = 0110, and M=1
Write your calculations and
results in the last two columns
of the following table
b) Given that registers A, B and S contain signed numbers in 2’s complement representation,
convert the binary numbers A3 A2 A1 A0, B3 B2 B1 B0 and S3 S2 S1 S0 to decimal, and write
your results and calculations in the following table:
A3 A2 A1 A0 B3B2B1B0 a) b) c) Are the results provided by the
(binary/ (binary/ S3 S2 S1 S0 S3 S2 S1 S0 logic circuit correct?, i.e., are they in
M C4
decimal) decimal) (binary) (decimal) accord with the results you obtain if
you do the same operations yourself
A=1101 = -|A| 0110 Carry: c4c3c2c1c0
|A|=-1101= 11000 S=A+B
2’s compl(1101) = + 6 0 1 1101 S=-3+6 CORRECT!
|A|=0011 = 3 +0110 =0011=+3
A = -3 =(1)0011
Carry : 1 0 011 S = A – B A -B = -3 – 6 = -9
0110 1101 S = -3 – 6 => Overflow, since the result
1101 1 1
=+6 +1001 = 0111= should be in the domain [-8, +7)
(1)0111 +7 !?
d) Expand your adder with a circuit C4
that can signalize overflow C3 OFL
 Question
Consider the computer of Lab 4, the architecture of which is described in Figure 1 and Tables
1, 2, 3, 4, and 5. The instruction type is determined by the two most significant bits of the 8-
bit register IR, as follows:
X0 = IR(7)’ IR(6)’ denotes a memory-reference instruction (MRI) in direct addressing mode;
X1 = IR(7)’ IR(6) denotes a register-reference instruction (RRI); and
X2 = IR(7) IR(6)’ denotes a memory-reference instruction (MRI) in indirect addressing mode.
Assume that all registers are equipped with 3 control bits for loading the register (LD), increment
by 1 (INC), and reset to zero (CLR).
Find the list of all micro-operations which change the value of register AC and derive the logic
equations
RRI
T7 Y0 : AC ← AC + DR , Symbol Notation (RTL)
T7 Y1 : AC ← DR CLA T3 X1 IR(0): AC ← 0
T7 Y5 : AC ← AC ∧ DR CMA T3 X1 IR(1): AC ← AC
T7 Y6 : AC ← AC – DR ASL T3 X1 IR(2): AC ← ashl AC
T3 X1 IR(0) : AC ← 0 ASR T3 X1 IR(3): AC ← ashr AC
T3 X1 IR(1) : AC ← AC INC T3 X1 IR(4): AC ← AC + 1
T3 X1 IR(2) : AC ← ashl AC
HLT T3 X1 IR(5) : S ← 1
T3 X1 IR(3) : AC ← ashr AC
MRI
T3 X1 IR(4) : AC ← AC + 1
Notation (RTL)
LDAC = T7 (Y0 + Y1 + Y5 + Y6) + Y0 = T6 Y0:DR ← M [AR]
T3[( X1 IR(1) + X1 IR(2) + X1 IR(3)] IR(6)’ IR(1) IR(0)’ T7 Y0:AC← AC + DR
SC← 0
INCAC = T3 X1 IR(0) Y1 = IR(6)’ IR(2) T6 Y1:DR ← M [AR]
T7 Y1:AC← DR, SC← 0
CLRAC = T3 X1 IR(4) Y2 = IR(6)’ IR(3) T6:
T7 Y2:M [AR] ← AC,
SC←0
Y3 = IR(6)’ IR(4) T6 Y3:PC← AR , SC← 0
Y4 = IR(6)’ IR(5) T6 Y4:DR ← M [AR]
T7 Y4:DR ← DR + 1
T8 Y4:M [AR] ← DR
T9 Y4:if (DR= 0)S’ then
(PC← PC+ 1)
T10Y4:if (DR = 0)S’
then(PC← PC+ 1)
T10 Y4:SC← 0
Y5 = T6 Y5:DR ← M [AR]
IR(6)’IR(1)’IR(0) T7 Y5:AC← AC ∧ DR
SC← 0
Y6 = T6 Y6:DR ← M [AR]
IR(6)’ IR(1)’IR(0) T7 Y6:AC← AC − DR
SC← 0

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 Question
Two memory-reference instructions in the Basic Computer are to be changed to the instructions
specified in the following table.
Symbol Opcode Symbolic designation Description in words
ADM 001 Add AC to memory
BNA 011 If ( then Branch if AC is negative
In the following table, write down the necessary micro-operations (in RTL) to perform the
execution phase of each instruction. Note that the execution phase of such type of instructions
starts at T4. See figures 2 and 3 from Annex. Note that the value in AC should not be changed by
the execution of any instruction unless the instruction specifies a change in its content. To this
extent you can use TR to store the content of AC temporary.
Question
Column (3) of the following table shows the
Symbol RTL
content of a memory segment of the Basic
Computer that stores a machine language ADM D1T4:
program and its operands. D1T5:
1. Convert from binary to hexadecimal both the D1T6:
address and the memory contents (columns D1T7:
(1) and (3)) and write your results in columns D1T8: DR ← TR
(2) and (4), respectively. D1T9: AC ← DR, SC ← 0
2. Use Table 6 from Annex to convert the BNA D3T4: If
machine language program (stored in the first then ,
six memory locations) to symbolic operation
codes (assembly language). Use Table 6 from
Annex to convert
the machine language program (stored in the first six memory
locations) to symbolic operation codes (assembly language).
Write the assembly language instructions in the
corresponding cells of column (5) of the above table. Use
hexadecimal representation for the address field of the Symbol
Hex
Symbol
Hex
instructions. code code
3. Fill out the last column (6) of the table with the content of the AND 0 or 8 CIR 7080
accumulator after the execution of each instruction. ADD 1 or 9 CIL 7040
Assembly AC after
Memory Memory
/operands execution LDA 2 or A INC 7020
Address Content
in HEX of instr.
Hex Binary Hex STA 3 or B SPA 7010
Binary (1) (5) (6)
(2) (3) (4)
BUN 4 or C SNA 7008
1000 0001 0111 817 0111 1000 0000 0000 7800 CLA 0000
1000 0001 1000 818 0010 1000 0001 1101 281D LDA 81D 0121 BSA 5 or D SZA 7004
1000 0001 1001 819 0001 1000 0001 1110 181E ADD 81E 0130
ISZ 6 or B SZE 7002
1000 0001 1010 81A 1000 1000 0001 1111 881F AND 81F I 0100
1000 0001 1011 81B 0011 1000 0001 1101 381D STA 81D 0100 CLA 7800 HLT 7001
1000 0001 1100 81C 0111 0000 0000 0001 7001 HLT 0100
CLE 7400 INP F800
1000 0001 1101 81D 0000 0001 0010 0001 0121
1000 0001 1110 81E 0000 0000 0000 1111 000F CMA 7200 OUT F400
1000 0001 1111 81F 0000 1000 0010 0000 0820
CME 7100 SKI F200
1000 0010 0000 820 0000 0001 1100 0100 01C4

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Question

a) Write a subroutine (MUL) in assembly b) This part is independent of part (a).

language that multiplies two positive The coordinates of two 2-dimensional vectors (ax, ay,
numbers by a repeated addition method. For bx, by) are stored at consecutive addresses starting
example, to multiply 6 x 4, the subroutine at F01. Write an assembly language program that
evaluates the product by adding the calculates the scalar (dot) product of two 2-
multiplicand (6) four times (multiplier), i.e., dimensional vectors, assuming that all their
6+6+6+6. coordinates are positive numbers:
Write your program using instructions of the p = ax bx+ay by
Basic Computer given in the Table 6 from the Your program is stored in memory beginning with
Annex. Your subroutine should be stored in location at address 100, and it has to place the
the memory of your Basic Computer product “p” at address F00.
beginning with address A00.
To calculate partial products (ax bx and ay by), you
Before invoking your subroutine MUL, the should call subroutine MUL. Parameters have to be
calling program places: passed as follows:
• the multiplicand (6 in the above example) • memory location 9FF is used to pass a factor, say ax;
in memory location at address 9FF; • the other factor (i.e., bx) is passed to the subroutine
• the multiplier (4 in the above example) in through the accumulator;
the accumulator. • the product ax bx is passed back to your program by
The result (the product of the two numbers) is subroutine MUL through the accumulator.
passed by subroutine to the calling program Solution:
through the accumulator. ORG HEX 100
NOTE: You are allowed to use different CLA /to initialise P = 0
ways to pass parameters, but full explanations STA P
should be provided. LDA AX /prepare ax in MLP
STA MLP
LDA BX /prepare bx in AC
Solution: BSA MUL / call MUL to get ax bx
ORG HEX 9FF ADD P / P <- P + ax bx = 0+ ax bx
MLP, 0000 STA P
MUL, 0000 LDA AY /prepare ay in MLP
CMA STA MUL
INC /initialize CTR to LDA BY /prepare by in AC
STA CTR /“negative multiplier” BSA MUL / call MUL to get ay by
CLA ADD P / P <- P + ay by = ax bx + ay by
LOP, ADD MLP STA P
ISZ CTR HLT
BUN LOP ORG HEX F00
BUN MUL I P
CTR, 0000 AX
AY
BX
BY

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 Data[7..0] 256x 8 Memory Data[7..0]
Address [7..0] Control Unit
Sequence counter
Address register AR (SC) State Register

Program counter PC State Decoder (T)

Stop register
IR[7..0]
Instruction register( IR
Instruction Decoder
DR[7..0] (lab_controller)

Data register DR
Control Register
(Register bank)

ALU Accumulator (AC)

Control commands to
counters , registers , bus
multiplexer and ALU
INPUT Address REGISTER Bus
(OUTA) select
Data[7..0] DIP switches

OUTPUT Data REGISTER 7-segment display

controllers 7-segment
OUTD
displays

Fig. 2. Flowchart for instruction cycle

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Table 1: Starting micro-operations in the instruction cycle of the 8-bit mini computer
Instant Description Notation (RTL)

Load the program counter PC in AR, and increment T0 : AR ← PC

T0 PC
T0 S′ : PC ← PC + 1
Read instruction from memory and put it in the T1 : IR ← M [AR]
T1 instruction register IR
This cycle is not used to allow for the new value of
T2 the instruction to propagate in the controller (nothing)

If X1 => it is a register - reference instruction that will T3 X1 : execute an RRI instruction (Table 4)
T3 be executed now T3 X1 : SC ← 0
If(RRI)
X0 or X2 , read the memory address of the T3 IR(6)’ : AR ← PC
operand and place it in AR, and increment PC.
T3 Recall that (X0 + X2 ) = IR(6)’ T3 IR(6)’ S’ : PC ← PC + 1
T4 Read memory address into AR T4 IR(6)’ : AR ← M [AR]
If indirect addressing, read the operand address from T5 X2 : AR ← M [AR]
T5 memory location pointed to by AR
If direct addressing, don’t do anything, as the operand
T5 address is already in AR since T6 T5 X0 : (nothing)

Execute the memory-reference instructions (MRI)

starting from described in Table 2 (see Table 2)
T6

Table 2: Execution of a memory-reference instruction (MRI) in the 8-bit mini computer

Symbol Notation (RTL)

T6 Y0 : DR ← M [AR]
ADD Y0 = IR(6)’ IR(1) IR(0)’
T7 Y0 : AC ← AC + DR , SC ← 0
T6 Y1 : DR ← M [AR]
LDA Y1 = IR(6)’ IR(2)
T7 Y1 : AC ← DR , SC ← 0
T6 : (cycle not used to allow for the
STA Y2 = IR(6)’ IR(3) address bus to stabilize)
T7 Y2 : M [AR] ← AC , SC ← 0
BUN Y3 = IR(6)’ IR(4) T6 Y3 : PC ← AR , SC ← 0
ISZ (assuming that the T6 Y4 : DR ← M [AR]
next instruction is a T7 Y4 : DR ← DR + 1
memory-reference T8 Y4 : M [AR] ← DR
instruction, stored at 2 Y4 = IR(6)’ IR(5) T9 Y4 : if (DR = 0)S’ then (PC ← PC + 1)
memory locations T10Y4 : if (DR = 0)S’ then (PC ← PC + 1)
further down) T10 Y4 : SC ← 0
T6 Y5 : DR ← M [AR]
AND Y5 = IR(6)’ IR(1)’ IR(0)
T7 Y5 : AC ← AC ∧ DR , SC ← 0
T6 Y6 : DR ← M [AR]
SUB Y6 = IR(6)’ IR(1)’ IR(0)
T7 Y6 : AC ← AC − DR , SC ← 0

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Table 3: Table 6:
Function table of the 8-bit ALU Instructions list of the 16-bit Basic Computer of the textbook
S2 S1 S0 Operation Hex
Symbol Description
code
0 0 0 F = AC + DR
0 0 1 F = AC − DR AND 0 or 8 AND M to AC
0 1 0 F = ashl AC ADD 1 or 9 Add M to AC, carry to E
0 1 1 F = ashr AC LDA 2 or A Load AC from M
1 0 0 F = AC ∧ DR STA 3 or B Store AC in M
1 0 1 F = AC ∨ DR
BUN 4 or C Branch unconditionally to m
1 1 0 F = DR (transfer)
BSA 5 or D Save return address in m and branch
1 1 1 F = AC’ to m + 1
ISZ 6 or B Increment M and skip if zero
Table 4:
Execution of a register-reference CLA 7800 Clear AC
instruction (RRI) of the 8-bit mini CLE 7400 Clear E
computer
Symbol Notation (RTL) CMA 7200 Complement AC

CLA T3 X1 IR(0) : AC ← 0 CME 7100 Complement E

CMA T3 X1 IR(1) : AC ← AC CIR 7080 Circulate right E and AC
ASL T3 X1 IR(2) : AC ← ashl CIL 7040 Circulate left E and AC
AC
T3 X1 IR(3) : AC ← ashr
ASR INC 7020 Increment AC,
AC
T3 X1 IR(4) : AC ← AC
INC SPA 7010 Skip if AC is positive
+
T31X1 IR(5) : S ← 1
HLT
SNA 7008 Skip if AC is negative
Table 5: SZA 7004 Skip if AC is zero
Function table of the 8-bit bus SZE 7002 Skip if E is zero
Register placed on
S2 S1 S0 HLT 7001 Halt computer
the bus
0 0 0 Memory INP F800 Input information and clear flag
0 0 1 AR OUT F400 Output information and clear flag
0 1 0 PC SKI F200 Skip if input flag is on
0 1 1 DR SKO F100 Skip if output flag is on
1 0 0 IR
ION F080 Turn interrupt on
1 0 1 AC
IOF F040 Turn interrupt off
1 1 0 OUTA
1 1 1 None

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 Fig. 3. Basic Computer registers connected to a common bus

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