TPS65163

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LCD Bias Supply With Integrated Level Shifters

Check for Samples :TPS65163

1FEATURES In typical display panel applications, the boost

• 8.6-V to 14.7-V Input Voltage Range converter generates the display panel source voltage,
VS; the buck converter generates the system logic
• 2.8-A Boost Converter Switch Current Limit supply, VLOGIC; and the two charge pump controllers
• Boost Converter Output Voltages up to 18.5 V regulate the external charge pumps generating the
• Boost and Buck Converter Short-Circuit display transistors’ on and off supplies, VGH and VGL.
Protection The level shifters transform the logic-level control
• 1.5-A Buck Converter (3.3 V) Switch Current signals generated by the display timing controller into
Limit the high-level signals needed by the LCD panel. The
nine level-shifter channels are organized in two
• Fixed 750-kHz Switching Frequency for Buck groups, each with its own positive supply voltage
and Boost Converters (VGH). Each channel uses a low-impedance output
• Buck Converter and Boost Converter stage to achieve fast rise and fall times, even when
Soft-Start driving the capacitive loads present in LCD
• Two Charge-Pump Controllers to Regulate VGH applications. Channels 1 to 6 also support gate
voltage shaping.
and VGL
• Control Signal for External High-Side MOSFET The TPS65163 also provides a reset circuit that
Isolation Switch monitors the buck converter output (VLOGIC) and
generates a reset signal for the timing controller
• 9-Channel Level Shifter Organized in Two during power up and power down.
Groups of 7 and 2 Channels (Separate VGH)
A control signal can also be generated to control an
• Gate Shaping (Level Shifter Channels 1 to 6)
external MOSFET isolation switch located between
• Display Panel Discharge Function the output of the boost converter and the display
• Supports VGH Voltages up to 38 V panel.
• Supports VGL Voltages Down to –13 V
Isolation Switch
• Reset Signal With Programmable Reset-Pulse Control GD

Duration
• Thermal Shutdown Boost
VS
Converter
• 48-Pin 7-mm × 7-mm QFN Package
Buck
VLOGIC
Converter
APPLICATIONS
• LCD TVs and Monitors Using GIP Technology Positive Charge VGH
Pump Controller

DESCRIPTION
Negative Charge VGL
Pump Controller
The TPS65163 integrates a boost converter, buck
converter, reset generator, two charge pump
Reset
controllers and a nine-channel level shifter in a single Generator
RST
device.
IN1 to IN9
Level Shifters OUT1 to OUT9
FLK1 to FLK3

Panel Discharge DISCH

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION (1)

TA ORDERING PACKAGE PACKAGE MARKING
–40°C to 85°C TPS65163RGZR 48-Pin 7x7 QFN TPS65163

(1) The device is supplied taped and reeled, with 3000 (TBC) devices per reel.

ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
VIN –0.3 to 20
Supply voltage (2) VGH1, VGH2 –0.3 to 45 V
VGL 0.3 to –15
FBN, FBP, FBB, FB, DLY, CRST, SS, COMP, VL, FLK1–FLK3,
Input voltage (2) –0.3 to 7 V
IN1–IN9, VSENSE
RST –0.3 to 7
SWB, CTRLP, GD, SW, CTRLN –0.3 to 20
Output voltage (2) V
RE –0.3 to 45
OUT1–OUT9, DISCHARGE –15 to 45
GD 1
Output current mA
RE 100
Human-body model 2000 V
ESD rating Machine model 200 V
Charged-device model 700 V
Continuous power dissipation See Dissipation Table W
Operating ambient
–40 to 85 °C
temperature range
Operating junction
–40 to 150 °C
temperature range
Storage temperature range –65 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) With respect to the GND and AGND pins.

DISSIPATION RATINGS
TA ≤ 25°C TA = 70°C TA = 85°C
PACKAGE RθJA
POWER RATING POWER RATING POWER RATING
48-pin QFN 36 °C/W 2.78 W 1.53 W 1.11 W

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
VIN Supply voltage range 8.6 12 14.7 V
VS Boost converter output voltage range VIN + 1 15 18.5 V
CIN Input capacitance 10 20 44 µF
L Boost converter inductance 6.8 10 15 µH
COUT Boost converter output capacitance 40 60 100 µF
L Buck converter inductance 6.8 10 15 µH
COUT Buck converter output capacitance 20 44 100 µF
TA Operating ambient temperature –40 25 85 °C
TJ Operating junction temperature –40 85 125 °C

ELECTRICAL CHARACTERISTICS
VIN = 12 V; VS = 16 V; VLOGIC = 3.3 V; VGH1 = VGH2 = 30 V; VGL = –7 V; TA = –40°C to 85°C; typical values are at 25°C (unless
otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
IIN Supply current 1 15 mA
UVLO UVLO threshold 7.8 8.2 8.5 V
VHYS UVLO hysteresis V
INTERNAL OSCILLATOR
fSW Switching frequency 600 750 900 kHz
VOLTAGE REFERENCE
VREF Voltage reference 1.24 V
BOOST CONVERTER
VS Output voltage Measured after isolation switch VIN+1 18.5 V
VFB Feedback regulation voltage 1.228 1.24 1.252 V
IFB Feedback input bias current VFB = 1.24 V ±0.01 ±1 µA
ILIM Switch current limit 2.8 3.5 4.2 A
ILEAK Switch leakage current VSW = 15 V 10 µA
rDS(ON) Switch ON resistance ISW = ILIM 0.15 0.25 Ω
tSW Switching time Turnon and turnoff 10 ns
Line regulation 9.6 V < VIN < 14.4 V, IS = 750 mA 0.02 %/V
Load regulation VS = 17 V, IS = 100 mA to 1.5 A 0.1 %/A
VOVP Overvoltage threshold 1.03 × VFB V
ISS Soft-start capacitor charge current 11 µA
VFB(SC) Short circuit threshold VFB rising 200 mV
GATE DRIVE SIGNAL
VGD Output low voltage IGD = 500 µA (sinking) 0.5 V
ILK Leakage current VGD = 20 V 0.05 1 µA

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ELECTRICAL CHARACTERISTICS (continued)

VIN = 12 V; VS = 16 V; VLOGIC = 3.3 V; VGH1 = VGH2 = 30 V; VGL = –7 V; TA = –40°C to 85°C; typical values are at 25°C (unless
otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BUCK CONVERTER
VLOGIC Output voltage 3.2 3.3 3.4 V
IFBB Feedback input bias current VFBB = 3.3 V, sourcing (i.e. flowing out of IC). 125 µA
ILIM Switch current limit 1.5 2.1 2.8 A
ILKG Switch leakage current VSWB = 0 V 10 µA
rDS(on) Switch ON resistance 0.21 Ω
tSW Switching time Turnon and turnoff 10 ns
Line regulation VIN = 9.6 V to 14.4 V, ILOGIC = 0.5 A 0.01 %/V
Load regulation ILOGIC = 150 mA to 1.5 A 0.2 %/A
VFB(SC) Short-circuit threshold VFBB rising 1.065 V
VLOGIC rising 3.2
VPG Power-good threshold V
VLOGIC falling 2.9
tSS Soft start time 0.66 ms
POSITIVE CHARGE PUMP CONTROLLER
VFBP Feedback regulation voltage 1.203 1.24 1.277 V
IFBP Feedback input bias current VFBP = 1.24 V ±10 ±100 nA
ICTRLP Base drive current for external
Normal operation 5 mA
transistor
Base drive current for external
ICTRLP(SC) Short-circuit operation 40 55 75 µA
transistor
VIN = 9.6 V to 14.4 V, VGH = 27 V, IGH = 50
Line regulation ±0.1 %/V
mA, including external components
VGH = 27 V, IGH = 0 to 50 mA, including
Load regulation ±1 %/A
external components
NEGATIVE CHARGE PUMP CONTROLLER
VFBN Feedback regulation voltage –36 0 36 mV
IFBN Feedback input bias current VFBP = 1.24 V ±10 ±100 nA
Base drive current for external
ICTRLN Normal operation 2.5 mA
transistor
ICTRLN(SC Base drive current for external
Short-circuit operation 200 300 480 µA
) transistor
VIN = 9.6 V to 14.4 V, VGL = –7 V, IGL = 50
Line regulation ±0.1 %/V
mA, including external components
VGL = –7 V, IGH = 0 to 50 mA, including
Load regulation ±1 %/A
external components
RESET GENERATOR
VOL Output voltage low IOL = 1 mA (sinking) 0.5 V
IOH Output current high VRST = 3.3 V ±1 µA
ICRST Reset delay capacitor charge current 10 µA
VCRST Reset delay threshold voltage 1.24 V
DELAY
IDLY Delay capacitor charge current 10 µA
VDLY Delay threshold voltage 1.24 V
THERMAL SHUTDOWN
TSD Thermal shutdown threshold 150 °C
THYS Thermal shutdown hysteresis 10 °C

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ELECTRICAL CHARACTERISTICS (continued)

VIN = 12 V; VS = 16 V; VLOGIC = 3.3 V; VGH1 = VGH2 = 30 V; VGL = –7 V; TA = –40°C to 85°C; typical values are at 25°C (unless
otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
IGH1 VGH1 supply current IN1 to IN7 = VSENSE = 0 V 0.35 3 mA
IGH2 VGH2 supply current IN8 and IN9 = 0V 0.012 1 mA
IGL VGL supply current IN1 to IN9 = VSENSE = 0 V 0.144 4 mA
UVLO Undervoltage lockout threshold VGH1 rising 10.5 13.5 V
(VGH1)
VHYS Undervoltage lockout hysteresis VGH1 falling 450 mV
(VGH1)
LEVEL SHIFTERS
OUT1 to OUT7, continuous ±15
OUT1 to OUT7, peak ±300
IOUT Output current mA
OUT8 to OUT9, DISCGARGE, continuous ±15
OUT8 to OUT9, DISCHARGE, peak ±150
IN1 to IN9 = 0 V ±1 µA
IIN Input current
IN1 to IN9 = 3.3 V ±1 µA
VIH High level input threshold IN1 to IN9 2 V
VIL Low level input threshold IN1 to IN9 0.5 V
OUT1 to OUT7, IOUT = –10 mA (sinking) 0.1 0.3
VDROPL Output voltage drop low OUT8 to OUT9, DISCHARGE, IOUT = –10 mA 1 V
0.2
(sinking)
OUT1 to OUT7, IOUT = 10 mA (sourcing) 0.15 0.4 V
VDROPH Output voltage drop high OUT8 to OUT9, DISCHARGE, IOUT = 10 mA 0.35 1 V
(sourcing)
OUT1 to OUT7, COUT = 4.7 nF 300 520
tR Rise time ns
OUT8 to OUT9, COUT = 4.7 nF 800 1200
OUT1 to OUT7, COUT = 4.7 nF 200 370
tF Fall time ns
OUT8 to OUT9, COUT = 4.7 nF 500 850
tPH Rising edge, COUT = 150 pF 60
Propagation delay ns
tPL Falling edge, COUT = 150 pF 60
GATE VOLTAGE SHAPING
Propagation delay, gate voltage
tPH FLK falling 100 ns
shaping enabled
Time IN signals must be stable before falling
tSU Set-up time 70 ns
edge of FLK
rDS(on) Resistance between OUT and RE 60 100 Ω
pins
Ilkg Leakage current from RE pin ±1 ±10 µA
DISCHARGE
VSENSE Discharge voltage sense threshold VSENSE falling 1.275 1.5 1.725 V
ISENSE Discharge voltage sense current VSENSE = 2V ±0.1 ±1 µA
VHYS Discharge voltage sense hysteresis VSENSE rising 50 mV

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DEVICE INFORMATION

PIN ASSIGNMENT

CTRLP

COMP
PGND

PGND

FBP
VIN

VIN

SW

SW

GD

FB
VL

45
48

46
47

44

43

42

41

40

39

38

37
SWB 1 36 SS

CTRLN 2 35 CRST

FBN 3 34 DLY

FBB 4 33 AGND

RST 5 32 DISCH

VGL 6 Exposed 31 VSENSE

FLK1 7 Thermal Die 30 VGH1

FLK2 8 29 VGH2

FLK3 9 28 RE

IN1 10 27 OUT1

IN2 11 26 OUT2

IN3 12 25 OUT3
17

21
13

18

19

20

22

23

24
16
14

15
IN4

OUT4
IN6

OUT7

OUT6
IN7

IN8

IN9

OUT9

OUT8
IN5

OUT5

PIN FUNCTIONS
PIN
I/O DESCRIPTION
NAME NO.
AGND 33 P Analog ground
BOOT 48 I Buck converter bootstrap capacitor connection
COMP 37 I Boost converter compensation network connection.
CRST 35 I Reset generator timing capacitor connection.
CTRLN 2 O Base drive signal for an external transistor positive linear regulator
CTRLP 40 O Base drive signal for an external transistor negative linear regulator
DISCH 32 I Panel discharging connection
DLY 34 I Positive charge pump and boost converter delay capacitor connection
FB 38 I Boost regulator feedback. Connect this pin to the center of a resistor divider connected between the
boost converter output and AGND.
FBB 4 I Buck converter feedback connection
FBN 3 I Feedback pin for an external transistor positive linear regulator
FBP 39 I Feedback pin for an external transistor negative linear regulator
FLK1 7 I Flicker clock for level-shifter channels 1 and 4
FLK2 8 1 Flicker clock for level-shifter channels 2 and 5
FLK3 9 I Flicker clock for level-shifter channels 3 and 6
GD 41 O Gate drive signal for the external MOSFET isolation switch
IN1–IN7 10, 11, 12, 13, I Inputs for level-shifter channels 1 through 7 (connected to VGH1)
14, 15, 16
IN8–IN9 17, 18 I Inputs for level-shifter channels 8 and 9 (connected to VGH2)

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PIN FUNCTIONS (continued)

PIN
I/O DESCRIPTION
NAME NO.
OUT7–OUT1 21, 22, 23, 24, O Outputs for level-shifter channels 1 through 7 (connected to VGH1)
25, 26, 27
OUT9–OUT8 19, 20 O Outputs for level-shifter channels 8 and 9 (connected to VGH2)
PGND 44, 45 P Power ground
RE 28 O Gate shaping slope resistor connection
RST 5 O Reset generator open-drain output
SS 36 I Soft-start timing-capacitor connection.
SW 42, 43 O Boost converter switching node
SWB 1 O Buck converter switch node
VGH1 30 P Positive supply voltage for level-shifter channels 1 through 7
VGH2 29 P Positive supply voltage for level-shifter channels 8 and 9
VGL 6 P Negative supply voltage for level-shifter channels 1 through 9
VIN 46, 47 P Supply-voltage connection
VSENSE 31 I Discharge sense voltage
Exposed P Connect to the system GND
thermal die

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TYPICAL CHARACTERISTICS

TABLE OF GRAPHS
FIGURE NO.
BOOST CONVERTER
Efficiency Figure 1
Load Transient Response VIN = 12 V, VS = 15.5 V, IS = 250 mA to 750 mA Figure 2
Line Transient Response VIN = 11.5 V to 12.5 V, VS = 15.5 V, IS = 750 mA Figure 3
Output Voltage Ripple VIN = 12 V, VS = 15.5 V, IS = 500 mA Figure 4
CCM Operation Figure 5
Switch Node (SW) Waveform
DCM Operation Figure 5
BUCK CONVERTER
Efficiency Figure 7
Load Transient Response VIN = 12 V, VLOGIC = 3.3 V, ILOGIC = 250 mA to 500 mA Figure 8
Line Transient Response VIN = 11.5 V to 12.5 V, VLOGIC = 3.3 V, ILOGIC = 500 mA Figure 9
Output Voltage Ripple VIN = 12 V, VLOGIC 3.3 V, ILOGIC = 500 mA Figure 10
CCM Operation Figure 11
Switch Node (SW) Waveform DCM Operation Figure 12
Skip Mode Figure 13
POSITIVE CHARGE PUMP
Load Transient Response VIN = 12 V, VGH = 26 V, IGH = 10 mA to 50 mA Figure 14
Line Transient Response VIN = 11.5 V to 12.5 V, VGH = 26 V, IGH = 50 mA Figure 15
Output Voltage Ripple VIN = 12 V, VGH = 26 V, IGH = 50 mA Figure 16
NEGATIVE CHARGE PUMP
Load Transient Response VIN = 12 V, VGL = –7 V, IGL = 10 mA to 50 mA Figure 17
Line Transient Response VIN = 11.5 V to 12.5 V, VGL = –7 V, IGL = 50 mA Figure 18
Output Voltage Ripple VIN = 12 V, VGL = –7 V, IGL = 50 mA Figure 19
START-UP SEQUENCING
Power-Up Sequencing CDLY = 100 nF Figure 20
Reset Sequencing CDLY = 100 nF, CRST = 22 nF Figure 21
LEVEL SHIFTERS
Channels 1–7, CL = 4.7 nF, rising edge Figure 22
Channels 1–7, CL = 4.7 nF, falling edge Figure 23
Channels 8–9, CL = 4.7 nF, rising edge Figure 24
Output Rise and Fall Time
Channels 8–9, CL = 4.7 nF, falling edge Figure 25
Channels 1–7, RL = 47 Ω, CL = 10 nF, rising edge Figure 26
Channels 1–7, RL = 47 Ω, CL = 10 nF, falling edge Figure 27
IN to OUT, channels 1–7, CL = 150 pF, rising edge Figure 28
IN to OUT, channels 1–7, CL = 150 pF, falling edge Figure 29
Propagation Delay IN to OUT, channels 8–9, CL = 150 pF, rising edge Figure 30
IN to OUT, channels 8–9, CL = 150 pF, falling edge Figure 31
FLK-RE, channels 1–6, CL = 150 pF, RE=1k Figure 32
Channels 1–7, CL = 10 nF Figure 33
Output Current
Channels 8–9, CL = 10 nF Figure 34
Power on Figure 35
Panel Discharge
Power off Figure 36

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BOOST CONVERTER EFFICIENCY

100 BOOST CONVERTER LOAD TRANSIENT RESPONSE
IS = 250 mA TO 750 mA
90

80 VS = 15.5 V,
VGH = 26 V,
70 IGH = 50 mA
Efficiency - %

60
VS
50

40

30

20
IS
10

0
0 0.25 0.5 0.75 1 1.25 1.5
IO - Output Current - mA

Figure 1. Figure 2.

BOOST CONVERTER LINE TRANSIENT RESPONSE BOOST CONVERTER OUTPUT VOLTAGE RIPPLE
VIN = 11.5 V TO 12.5 V IS = 500 mA
VS = 15.5 V,
VIN IS = 750 mA,
VGH = 26 V,
IGH = 50 mA

VS

VS

VS = 15.5 V,
VGH = 26 V,
IGH = 50 mA

Figure 3. Figure 4.

BOOST CONVERTER SWITCH NODE WAVEFORM BOOST CONVERTER SWITCH NODE WAVEFORM
CONTINUOUS CONDUCTION MODE DISCONTINUOUS CONDUCTION MODE
VS = 15.5 V,
VSW VSW IS = 50 mA

IINDUCTOR

VIN = 12 V,
IS = 250 mA IINDUCTOR

Figure 5. Figure 6.

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BUCK CONVERTER EFFICIENCY

100 BUCK CONVERTER LOAD TRANSIENT RESPONSE
ILOGIC = 250mA TO 500mA
90

80

70 VLOGIC
Efficiency - %

60

50

40 ILOGIC

30

20

10 VLOGIC = 12 V,
VGL = -7 V,
0 IGL = 50 mA
0 0.25 0.5 0.75 1 1.25 1.5
IO - Output Current - A

Figure 7. Figure 8.

BUCK CONVERTER LINE TRANSIENT RESPONSE BUCK CONVERTER OUTPUT VOLTAGE RIPPLE
VIN = 11.5 V TO 12.5 V ILOGIC = 500 mA

VLOGIC = 3.3 V
VIN
VGL = -7 V
IGL = 50 mA

VLOGIC = 3.3 V VLOGIC

ILOGIC = 500 mA
VGL = -7 V
IGL = 50 mA

VLOGIC

Figure 9. Figure 10.

BUCK CONVERTER SWITCH NODE WAVEFORM BUCK CONVERTER SWITCH NODE WAVEFORM
CONTINUOUS CONDUCTION MODE DISCONTINUOUS CONDUCTION MODE

VLOGIC = 3.3 V VLOGIC = 3.3 V

ILOGIC = 250 mA ILOGIC = 50 mA
VSWB

VSWB

IINDUCTOR
IINDUCTOR

Figure 11. Figure 12.

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BUCK CONVERTER SWITCH WAVEFORM POSITIVE CHARGE PUMP LOAD TRANSIENT RESPONSE
SKIP MODE IGH = 10 mA to 50 mA

VLOGIC = 3.3 V VS = 15.5 V

ILOGIC = 0 mA IS = 250 mA
VGH = 26 V
VSWB
VGH

IINDUCTOR IGH

Figure 13. Figure 14.

POSITIVE CHARGE PUMP LINE TRANSIENT RESPONSE POSITIVE CHARGE PUMP OUTPUT VOLTAGE RIPPLE
VIN = 11.5 V TO 12.5 V IGH = 50 mA
VS = 15.5 V
VIN IS = 750 mA VS = 15.5 V
VGH = 26 V IS = 750 mA
IGH = 50 mA VGH = 26 V

VGH

VS

Figure 15. Figure 16.

NEGATIVE CHARGE PUMP LOAD TRANSIENT RESPONSE NEGATIVE CHARGE PUMP LINE TRANSIENT RESPONSE
IGL = 10 mA to 50 mA VIN = 11.5 V to 12.5 V

VLOGIC = 3.3 V
VIN
ILOGIC = 250 mA
VGL = -7 V
VGL

VLOGIC = 3.3 V
ILOGIC = 500 mA
VGL = -7 V
IGL = 50 mA
VGL
IGL

Figure 17. Figure 18.

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NEGATIVE CHARGE PUMP OUTPUT VOLTAGE RIPPLE POWER-UP SEQUENCING

IGL = 50 mA
VLOGIC
VLOGIC = 3.3 V
ILOGIC = 250 mA VGL
VGL = -7 V

VGL

VS

VGH

Figure 19. Figure 20.

RESET SEQUENCING LEVEL SHIFTER OUTPUT RISE TIME

CHANNELS 1-7

VIN

VLOGIC
IN
VGL

VGH = 26 V
RESET VGL = -7 V
OUT
COUT = 4.7 nF
tRISE = 288 ns

Figure 21. Figure 22.

LEVEL SHIFTER OUTPUT FALL TIME LEVEL SHIFTER OUTPUT RISE TIME
CHANNELS 1-7 CHANNELS 8-9

VGH = 26 V
IN
VGL = -7 V
COUT = 4.7 nF
tFALL=216 ns
IN
OUT

VGH = 26 V
OUT VGL = -7 V
COUT = 4.7 nF
tRISE = 726 ns

Figure 23. Figure 24.

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LEVEL SHIFTER OUTPUT FALL TIME LEVEL SHIFTER OUTPUT RISE TIME
CHANNELS 8-9 CHANNELS 1-7
VGH = 26 V
IN
VGL = -7 V
COUT = 4.7 nF
tFALL = 500 ns
IN
OUT

VGH = 26 V
OUT VGL = -7 V
CLOAD = 10 nF
RLOAD = 47 Ω

Figure 25. Figure 26.

LEVEL SHIFTER OUTPUT FALL TIME LEVEL SHIFTER PROPAGATION DELAY

CHANNELS 1-7 IN-OUT, LOW-HIGH, CHANNELS 1-7
VGH = 26 V
IN VGL = -7 V
CLOAD = 10 nF
RLOAD = 47 Ω

OUT
IN

VGH = 26 V
VGL = -7 V
CLOAD = 150 pF
OUT tPLH = 28.1 ns

Figure 27. Figure 28.

LEVEL SHIFTER PROPAGATION DELAY LEVEL SHIFTER PROPAGATION DELAY

IN-OUT, HIGH-LOW, CHANNELS 1-7 IN-OUT, LOW-HIGH, CHANNELS 8-9
IN
VGH = 26 V
VGL = -7 V
CLOAD = 150 pF
tPHL = 37.1 ns

IN
OUT

VGH = 26 V
VGL = -7 V
CLOAD = 150 pF
OUT tPLH = 33.5 ns

Figure 29. Figure 30.

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LEVEL SHIFTER PROPAGATION DELAY LEVEL SHIFTER PROPAGATION DELAY

IN-OUT, HIGH-LOW, CHANNELS 8-9 FLK-RE, HIGH-LOW, CHANNELS 1-6
IN
VGH = 26 V VGH = 26 V
RE VGL = -7 V
VGL = -7 V
CLOAD = 150 pF CLOAD = 150 pF
tPHL = 38.3 ns tPHL = 59.9 ns

IN
OUT

Figure 31. Figure 32.

LEVEL SHIFTER OUTPUT CURRENT LEVEL SHIFTER OUTPUT CURRENT

CHANNELS 1-7 CHANNELS 8-9

VGH = 26 V VGH = 26 V
VGL = -7 V VGL = -7 V
CLOAD = 10 nF CLOAD = 10 nF
IPK+=730 mA IPK+ = 248 mA
IPK-=820 mA IPK- = 320 mA

IOUT IOUT

Figure 33. Figure 34.

LEVEL SHIFTER DISCHARGE LEVEL SHIFTER DISCHARGE

DURING POWER-UP DURING POWER-DOWN

VIN

VIN

VDISCHARGE
VDISCHARGE

Figure 35. Figure 36.

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DETAILED DESCRIPTION
GD

SW
SS SW
VIN LDO

VL VL

Boost PGND
Bandgap VREF
Converter PGND
OVP & SCP
Comparator
+ VREF
VIN
- Switching
Enable
+ -

GD -
Enable
FB
CTRLP +
VREF
FBP +
VREF - COMP
Enable
750 kHz
DLY Clock VIN
EN Timer
VIN
CRST
EN
Timer
RST Buck
Q
Converter
S Bootstrap SWB
Latch PG Capacitor

Enable + VREF
FBN + R
- FBB
-
UVLO VL
Z
CTRLN
AGND
VIN -
+ UVLO
VREF

VGH1
FLK1
FLK2 RE
FLK3
IN1 OUT1
IN2 Gate OUT2
Shaping
IN3 OUT3
IN4 OUT4
Level
IN5 Shifters OUT5
IN6 OUT6
IN7 OUT7
VSENSE -
DISCHARGE
VREF +
VGL
VGH2
IN8 Level OUT8
IN9 Shifter OUT9

Figure 37. TPS65163 Internal Block Diagram

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BOOST CONVERTER
The non-synchronous boost converter uses a current-mode topology and operates at a fixed frequency of
750 kHz. The internal block diagram of the boost converter is shown in Figure 38, and a typical application circuit
in Figure 39. External compensation allows designers to optimize performance for individual applications, and is
easily implemented by connecting a suitable capacitor/resistor network between the COMP pin and AGND (see
the Boost Converter Design Procedure section for more details). The boost converter also controls a GD pin that
can be used to drive an external isolation MOSFET.
The boost converter can operate in either continuous conduction mode (CCM) or discontinuous conduction mode
(DCM), depending on the load current. At medium and high load currents, the inductor current is always greater
than zero and the converter operates in CCM; at low load currents, the inductor current is zero during part of
each switching cycle, and the converter operates in DCM. The switch node waveforms for CCM and DCM
operation are shown in Figure 5 and Figure 6. Note that the ringing seen during DCM operation occurs because
of parasitic capacitance in the PCB layout and is quite normal for DCM operation. There is very little energy
contained in the ringing waveform and it does not significantly affect EMI performance.
Equation 1 can be used to calculate the load current below which the boost converter operates in DCM.
(VS - VI N ) VIN
IDCM = ´
2 ´ L ´ ¦ SW VO UT (1)

SW
SW
Current Sampling
&
Slope Compensation
VL

10µA

Current Limit
SS &
Soft-Start

Current
COMP Comparator
+
FBP -
-
1.24V + Error
Amplifier
PGND
+
PGND
1.24V+3% -
Overvoltage
Comparator

- Control Short-Circuit From Positive

Logic Charge Pump
200mV + Short-Circuit
Comparator

CTRLP +
≈(VIN - 2V) -
Boost Enable
Comparator
From Reset
Block

DLY Delay Delay

Variable 1.36ms
GD

750kHz
Oscillator

Figure 38. Boost Converter Internal Block Diagram

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VIN VS

CIN COUTB

COUTA

R1 CFF
SW GD

FB

R2

COMP SS

CSS

CCOMP

RCOMP

Figure 39. Boost Converter Typical Application Circuit

PROTECTION (BOOST CONVERTER)

The boost converter is protected against potentially damaging conditions such as overvoltage and short circuits.
An error condition is detected if the voltage on the converter's FB pin remains below 200 mV for longer than
1.36 ms, in which case the converter stops switching and is latched in the OFF condition. To resume normal
operation, the TPS65163 must be turned off and then turned on again.
Note: Because the positive charge pump is driven from its switch node, an error condition on the boost converter
output also causes the loss of VGH until the circuit recovers.
The boost converter also stops switching while the positive charge pump is in a short-circuit condition. This
condition is not latched, however, and the boost converter automatically resumes normal operation once the
short-circuit condition has been removed from the positive charge pump.

BOOST CONVERTER DESIGN PROCEDURE

Calculate Converter Duty Cycle (Boost Converter)

The simplest way to calculate the boost converter duty cycle is to use the efficiency curve in Figure 1 to
determine the converter efficiency under the anticipated load conditions and insert this value into Equation 2 (1).
Alternatively, a worst-case value (e.g., 90%) can be used for efficiency.
V ´ η
D = 1 - IN
VS (2)
(1) Valid only when boost converter operates in CCM.

where VS is the output voltage of the boost converter.

Calculate Maximum Output Current (Boost Converter)

The maximum output current IS that the boost converter can supply can be calculated using Equation 3. The
minimum specified output current occurs at the maximum duty cycle (which occurs at minimum VIN) and
minimum frequency (600 kHz).
æ VIN ´ D ö
IS = ç ILIM - ÷ ´ (1 - D )
è 2 ´ ¦SW ´ L ø (3)
where ILIM is the minimum specified switch current limit (2.8 A) and ƒSW is the converter switching frequency.
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Calculate Peak Switch Current (Boost Converter)

Equation 4 can be used to calculate the peak switch current occurring in a given application. The worst-case
(maximum) peak current occurs at the minimum input voltage and maximum duty cycle.
IS VIN ´ D
ISW(PK) = +
1 - D 2 ´ ¦ SW ´ L (4)

Inductor Selection (Boost Converter)

The boost converter is designed for use with inductors in the range 6.8 µH to 15 µH. A 10-µH inductor is typical.
Inductors should be capable of supporting at least 125% of the peak current calculated by Equation 4 without
saturating. This ensures sufficient margin to tolerate heavy load transients. Alternatively, a more conservative
approach can be used in which an inductor is selected whose saturation current is greater than the maximum
switch current limit (4.2 A).
Another important parameter is dc resistance, which can significantly affect the overall converter efficiency.
Physically larger inductors tend to have lower dc resistance (DCR) because they can use thicker wire. The type
and core material of the inductor can also affect efficiency, sometimes by as much as 10%. Table 1 shows some
suitable inductors.

Table 1. Boost Converter Inductor Selection

PART NUMBER INDUCTOR VALUE COMPONENT SUPPLIER SIZE (L×W×H, mm) ISAT / DCR
CDRH8D43 10 µH Sumida 8.3 × 8.3 × 4.5 4 A / 29 mΩ
CDRH8D38 10 µH Sumida 8.3 × 8.3 × 4 3 A / 38 mΩ
MSS 1048-103 10 µH Coilcraft 10.5 × 10.5 × 5.1 4.8 A / 26 mΩ
744066100 10 µH Wuerth 10 × 10 × 3.8 4 A / 28 mΩ

Rectifier Diode Selection (Boost Converter)

For highest efficiency, the rectifier diode should be a Schottky type. Its reverse voltage rating should be higher
than the maximum output voltage VS. The average rectified forward current through the diode is the same as the
output current.
ID(AVG) = IS
(5)
A Shottky diode with a 2-A average rectified current rating is adequate for most applications. Smaller diodes can
be used in applications with lower output current; however, the diode must be able to handle the power
dissipated in it, which can be calculated using Equation 6. Table 2 lists some diodes suitable for use in typical
applications.
PD = ID(AVG) ´ VF
(6)

Table 2. Boost Converter Rectifier Diode Selection

PART NUMBER VR / IAVG VF RθJA SIZE COMPONENT SUPPLIER
MBRS320 20 V / 3 A 0.44 V at 3 A 46°C/W SMC International Rectifier
SL22 20 V / 2 A 0.44 V at 2 A 75°C/W SMB Vishay Semiconductor
SS22 20 V / 2 A 0.5 V at 2 A 75°C/W SMB Fairchild Semiconductor

Output Capacitance Selection (Boost Converter)

For best performance, a total output capacitance (COUTA + COUTB in Figure 39) in the range 50 µF to 100 µF is
recommended. At least 20 µF of the total output capacitance should be connected directly to the cathode of the
boost converter rectifier diode, i.e., in front of the isolation switch.

Operating the boost converter with little or no capacitance in front of the isolation switch may cause overvoltage
conditions that reduce reliability of the TPS65163.

Table 3 suggests some output capacitors suitable for use with the boost converter.

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Table 3. Boost Converter Output Capacitor Selection

PART NUMBER VALUE / VOLTAGE RATING COMPONENT SUPPLIER
GRM32ER61E226KE15 22 µF / 25 V Murata
GRM31CR61E106KA12 10 µF / 25 V Murata
UMK325BJ106MM 10 µF / 50 V Taiyo Yuden

Setting the Output Voltage (Boost Converter)

The boost converter output voltage is programmed by a resistor divider according to Equation 7.
æ R ö
VS = VREF ´ ç 1+ 1 ÷
è R2 ø (7)
where VREF is the internal 1.24-V reference of the IC.
A current of the order of 100 µA through the resistor network ensures good accuracy and improves noise
immunity. A good approach is to assume a value of about 12 kΩ for the lower resistor (R2) and then select the
upper resistor (R1) to set the desired output voltage.

Compensation (Boost Converter)

Boost converter external compensation can be fine-tuned for each individual application. Recommended starting
values are 33 kΩ and 1 nF, which introduce a pole at the origin for high dc gain and a zero for good transient
response. The frequency of the zero set by the compensation components can be calculated using Equation 8.
1
¦z =
2 ´ p ´ RCOMP ´ C COMP (8)

Selecting the Soft-Start Capacitor (Boost Converter)

The boost converter features a programmable soft-start function that ramps up the output voltage to limit the
inrush current drawn from the supply voltage. The soft-start duration is set by the capacitor connected between
the SS pin and AGND according to Equation 9.
C ´ VREF
tSS = SS
ISS (9)
where CSS is the capacitor connected between the SS pin and GND, VREF is the internal 1.24-V reference of the
IC, and ISS is the internally generated 10-µA soft-start current.

Selecting the Isolation Switch Gate Drive Components

The isolation switch is controlled by an active-low signal generated by the GD pin. Because this signal is
open-drain, an external pullup resistor is required to turn the MOSFET switch off. If the maximum MOSFET
gate-source voltage rating is less than the maximum VIN, two resistors in series can be used to reduce the
maximum VGS applied to the device. The exact value of the gate drive resistors is not critical: 100 kΩ for both is a
good value to start with.
A capacitor can also be connected in parallel with the top resistor, as illustrated in Figure 39. The effect of this
capacitor is to slow down the speed with which the transistor turns on, thereby limiting inrush current. (Note that
the capacitor also slows down the speed with which the transistor turns off, and therefore the speed with which it
can respond to error conditions.)
Even when trying to limit inrush current, the capacitor must not be too large or the output voltage will rise so
slowly the condition will be interpreted as an error (see the Power Supply Sequencing in Detail section). Typical
values are 10 nF to 100 nF, depending on the transistor used for the isolation switch and the value of the
gate-drive resistors.
Note that even in applications that do not use an isolation switch, an external pullup resistor (typically 100 kΩ)
between GD and VIN is required.

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BUCK CONVERTER
The buck converter is a non-synchronous type that runs at a fixed frequency of 750 kHz. The converter features
integrated soft-start (0.66 ms), bootstrap, and compensation circuits to minimize external component count. The
buck converter internal block diagram is shown in Figure 40, and a typical application circuit in Figure 41.
The output voltage of the buck converter is internally programmed to 3.3 V and is enabled as soon as VIN
exceeds the UVLO threshold. For best performance, the buck converter FB pin should be connected directly to
the positive terminal of the output capacitor(s).
The buck converter can operate in either continuous conduction mode (CCM) or discontinuous conduction mode
(DCM), depending on the load current. At medium and high load currents, the inductor current is always greater
than zero and the converter operates in CCM; at low load currents, the inductor current is zero during part of
each switching cycle, and the converter operates in DCM. The switch node waveforms for CCM and DCM
operation are shown in Figure 11 and Figure 12. Note that the ringing seen during DCM operation occurs
because of parasitic capacitance in the PCB layout and is quite normal for DCM operation. However, there is
little energy contained in the ringing waveform, and it does not significantly affect EMI performance. Equation 10
can be used to calculate the load current below which the buck converter operates in DCM.
(VIN - VLOGIC ) VLOGIC
IDCM = ´
2 ´ L ´ ¦ SW VIN (10)
The buck converter uses a skip mode to regulate VLOGIC at low load currents. This mode allows the converter to
maintain its output at the required voltage while still meeting the requirement of a minimum on-time. The buck
converter enters skip mode when its feedback voltage exceeds the skip-mode threshold (25% above the normal
VFBB regulation voltage). During skip mode, the buck converter switches for a few cycles, then stops switching for
a few cycles, and then starts switching again, and so on, for as long as VFBB remains above the skip-mode
threshold. Output voltage ripple can be higher during skip mode (see Figure 13).

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VIN SWB
VIN SWB

Current Sampling
Bootstrap &
Capacitor
Slope Compensation VL

OVP Pull-Up
Control + Resistor
Logic + 1.24V
-
Current
Comparator Error - FBB
Amplifier

Current Limit
&
Soft-Start

Overvoltage
Comparator
+
- 1.24V+15%

Power Good
Comparator
+
To Reset Block
- 1.24V-3%

Clock/2 + 0.8V

Control Clock/4 + 0.4V

Logic -

750kHz
Oscillator

Clock Selection for Short-Circuit and Soft-Start

Figure 40. Buck Converter Internal Block Diagram

FBB

VIN VIN SWB VLOGIC

Figure 41. Buck Converter Application Circuit

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PROTECTION (BUCK CONVERTER)

To protect against short-circuit conditions, the buck converter automatically limits its output current when the
voltage applied to its FBB pin is less than 1.065 V. To reduce power dissipation in the IC, the buck converter
switches at 25% of its nominal switching frequency as long as VFBB < 1.065 V. When VFBB is between 1.065 V
and 2.13 V, the buck converter switches at 50% of its nominal switching frequency.
Note: Because the negative charge pump is driven from its switch node, a short-circuit condition on the buck
converter output also causes the loss of VGL until the short circuit is removed.
An internal pullup prevents the buck converter from generating excessive output voltages if its FBB pin is left
floating.

Buck Converter Design Procedure

Because the negative charge pump is driven from the buck converter switch node, the effective output current for
design purposes is greater than ILOGIC alone. For best performance, the effective current calculated using
Equation 11 should be used during the design.
VGL ´ IGL
ILOGIC(EFFECTIVE) = ILOGIC +
VLOGIC (11)

Calculate Converter Duty Cycle (Buck Converter)

The simplest way to calculate the converter duty cycle is to use the efficiency curve in Figure 7 to determine the
converter efficiency under the anticipated load conditions and insert this value into Equation 12 (1). Alternatively,
a worst-case value (e.g., 80%) can be used for efficiency.
V
D = LOGIC
VIN ´ η (12)
(1) Valid only when buck converter operates in CCM.

Calculate Maximum Output Current (Buck Converter)

The maximum output current that the buck converter can supply can be calculated using Equation 13. The
minimum specified output current occurs at the minimum duty cycle (which occurs at maximum VIN) and
maximum frequency (900 kHz).
VIN ´ (1 - D)
ILOGIC(EFFECTIVE) = ISW(LIM) - ´ D
2 ´ ¦SW ´ L (13)
Where ISW(LIM) is the minimum specified switch current limit (1.5 A) and ƒSW is the converter switching frequency.

Calculate Peak Switch Current (Buck Converter)

Equation 14 can be used to calculate the peak switch current occurring in a given application. The worst-case
(maximum) peak current occurs at maximum VIN.
VIN ´ (1 - D)
ISW(PK) = ILOGIC(EFFECTIVE) + ´ D
2 ´ ¦SW ´ L (14)

Inductor Selection (Buck Converter)

The buck converter is designed for use with inductors in the range 6.8 µH to 15 µH, and is optimized for 10 µH.
The inductor must be capable of supporting the peak current calculated by Equation 14 without saturating.
Alternatively, a more conservative approach can be used in which an inductor is selected whose saturation
current is greater than the maximum switch current limit (2.25 A).
Another important parameter is dc resistance, which can significantly affect the overall converter efficiency.
Physically larger inductors tend to have lower dc resistance (DCR) due to the use of thicker wire. The type and
core material of the inductor can also affect efficiency, sometimes by as much as 10%. Table 4 shows some
suitable inductors.

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Table 4. Buck Converter Inductor Selection

PART NUMBER INDUCTOR VALUE COMPONENT SUPPLIER SIZE (L×W×H, mm) ISAT / DCR
CDRH8D43 10 µH Sumida 8.3 × 8.3 × 4.5 4 A / 29 mΩ
CDRH8D38 10 µH Sumida 8.3 × 8.3 × 4 3 A / 38 mΩ
MSS 1048-103 10 µH Coilcraft 10.5 × 10.5 × 5.1 4.8 A / 26 mΩ
744066100 10 µH Wuerth 10 × 10 × 3.8 4 A / 28 mΩ

Rectifier Diode Selection (Buck Converter)

To achieve good efficiency, the rectifier diode should be a Schottky type. Its reverse voltage rating should be
higher than the maximum VIN. The average rectified forward current through the diode can be calculated using
Equation 15.
IRECT(AVG) = ILOGIC(EFFECTIVE) ´ (1 - D)
(15)
A Schottky diode with a 2-A average rectified current rating is adequate for most applications. Smaller diodes can
be used in applications with lower output current; however, the diode must be able to handle the power
dissipated in it, which can be calculated using Equation 16.
PRECT = IRECT(AVG) ´ VF
(16)

Table 5. Buck Converter Rectifier Diode Selection

PART NUMBER VR / IAVG VF RθJA SIZE COMPONENT SUPPLIER
MBRS320 20 V / 3 A 0.44 V at 3 A 46°C/W SMC International Rectifier
SL22 20 V / 2 A 0.44 V at 2 A 75°C/W SMB Vishay Semiconductor
SS22 20 V / 2 A 0.5 V at 2 A 75°C/W SMB Fairchild Semiconductor

Output Capacitance Selection (Buck Converter)

To minimize output voltage ripple, the output capacitors should be good-quality ceramic types with low ESR. The
buck converter is stable over a range of output capacitance values, but an output capacitance of 44 µF is a good
starting point for typical applications.

POSITIVE CHARGE PUMP CONTROLLER

The positive charge pump is driven directly from the boost converter switch node and regulated by controlling the
current through an external PNP transistor. An internal block diagram of the positive charge pump is shown in
Figure 42 and a typical application circuit in Figure 43.
During normal operation, the TPS65163 is able to provide up to 5 mA of base current and is designed to work
best with transistors whose dc gain (hFE) is between 100 and 300. The charge pump is protected against short
circuits on its output, which are detected when the voltage on the charge pump feedback pin (VFBP) is below
100 mV. During short-circuit mode, the base current available from the CTRLP pin is limited to 55 µA. Note that if
a short circuit is detected during normal operation, boost converter switching is also halted until VFBP > 100 mV.

NOTE
The emitter of the external PNP transistor should always be connected to VS, the
output of the boost converter at the output side of the isolation switch. The TPS65163
uses the CTRLP pin to sense the voltage across the isolation switch and control boost
converter start-up. Connecting the emitter of the external PNP transistor to any other
voltage (e.g., VIN) prevents proper start-up of the boost converter and positive charge
pump.

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VIN

R
Short-Circuit
R Mode
FBB - 300μA
1.65V
+ Short-Circuit
Comparator
Control
FBN Logic Normal
+ Mode
2.5mA
- Error
Amplifier

CTRLN

Figure 42. Positive Charge Pump Internal Block Diagram

VS VSW

RPULL-UP RFLY

VREF - CTRLP CFLY

+ VGH
ICTRLP
CCOLLECTOR COUT
CFF
R1
FBP

R2

Figure 43. Positive Charge Pump Application Circuit

POSITIVE CHARGE PUMP DESIGN PROCEDURE

Setting the Output Voltage (Positive Charge Pump)

The positive charge pump output voltage is programmed by a resistor divider according to Equation 17.
æ R ö
VGH = VREF ´ ç 1 + 1 ÷
è R 2 ø (17)
where VREF is the internal 1.24-V reference of the TPS65163.
Rearranging Equation 17, the values of R1 and R2 are calculated:
æ VOUT ö
R1 = R 2 ´ ç - 1÷
V
è REF ø (18)
A current of the order of 1 mA through the resistor network ensures good accuracy and increases the circuit's
immunity to noise. It also ensures a minimum load on the charge pump, which reduces output voltage ripple
under no-load conditions. A good approach is to assume a value of about 1.2 kΩ for the lower resistor (R2) and
then select the upper resistor (R1) to set the desired output voltage.

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Note that the maximum voltage in an application is determined by the boost converter output voltage and the
voltage drop across the diodes and PNP transistor. For a typical application in which the positive charge pump is
configured as a voltage doubler, the maximum output voltage is given by Equation 19.
VG H(MA X) = (2 ´ VS ) - (2 × VF ) - VCE
(19)
where VS is the output voltage of the boost converter, VF is the forward voltage of each diode, and VCE is the
collector-emitter voltage of the PNP transistor (recommended to be at least 1 V to avoid transistor saturation).

Selecting the Feed-Forward Capacitor (Positive Charge Pump)

To improve transient performance, a feed-forward capacitor connected across the upper feedback resistor (R1) is
recommended. The feed-forward capacitor modifies the frequency response of the feedback network by adding
the zero, which improves high frequency gain. For typical applications, a zero at 5 kHz is a good place to start, in
which case CFF can be calculated using Equation 20.
1
CFF =
2 ´ p ´ 5 kHz ´ R1 (20)

Selecting the PNP Transistor (Positive Charge Pump)

The PNP transistor used to regulate VGH should have a dc gain (hFE) of at least 100 when its collector current is
equal to the charge pump output current. The transistor should also be able to withstand voltages up to 2 × VS
across its collector-emitter junction (VCE).
The power dissipated in the transistor is given by Equation 21. The transistor must be able to dissipate this
power without its junction becoming too hot. Note that the ability to dissipate power depends on adequate PCB
thermal design.
PQ = éë(2 ´ VS ) - (2 ´ VF ) - VGH ùû ´ IGH
(21)
where IGH is the mean (not RMS) output current drawn from the charge pump.
A pullup resistor is also required between the base and emitter of the transistor. The value of this resistor is not
critical, but it should be large enough not to divert significant current away from the base of the transistor. A
value of 100 kΩ is suitable for most applications.

Selecting the Diodes (Positive Charge Pump)

Small-signal diodes can be used for most low-current applications (<50 mA), and higher-rated diodes for
higher-power applications. The average current through the diode is equal to the output current, so that the
power dissipated in the diode is given by Equation 22.
PD = IGH ´ VF (22)
The peak current through the diode occurs during start-up, and for a few cycles may be as high as a few
amperes. However, this condition typically lasts for <1 ms and can be tolerated by many diodes whose repetitive
current rating is much lower. The reverse voltage rating of the diodes should be equal to 2 × VS.

Table 6. Positive Charge-Pump Diode Selection

PART NUMBER IAVG IPK VR VF COMPONENT SUPPLIER
BAV99W 150 mA 1 A for 1 ms 75 V 1 V at 50 mA NXP
BAT54S 200 mA 600 mA for 1 s 30 V 0.8 V at 100 mA Fairchild Semiconductor
MBR0540 500 mA 5.5 A for 8 ms 40 V 0.51 at 500 mA Fairchild Semiconductor

Selecting the Capacitors (Positive Charge Pump)

For lowest output voltage ripple, low-ESR ceramic capacitors are recommended. The actual value is not critical,
and 1 µF to 10 µF is suitable for most applications. Larger capacitors provide better performance in applications
where large load transient currents are present.

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A flying capacitor in the range 100 nF to 1 µF is suitable for most applications. Larger values experience a
smaller voltage drop by the end of each switching cycle and allow higher output voltages and/or currents to be
achieved. Smaller values tend to be physically smaller and a bit cheaper. For best performance, it is
recommended to include a resistor of a few ohms (2 Ω is a good value to start with) in series with the flying
capacitor to limit peak currents occurring at the instant of switching.
A collector capacitor in the range 100 nF to 1 µF is suitable for most applications. Larger values are more
suitable for high-current applications but can affect stability if they are too big.
A combination of COUT = 10 µF, CFLY = 1 µF, and CCOLLECTOR = 100 nF is a good starting point for most
applications (the final values can be optimized on a case-by-case basis if necessary).

NEGATIVE CHARGE PUMP

The negative charge pump controller uses an external NPN transistor to regulate an external charge pump
circuit. The IC is optimized for use with transistors having a dc gain (hFE) in the range 100 to 300; however, it is
possible to use transistors outside this range, depending on the application requirements. Regulation of the
charge pump is achieved by using the external transistor as a controlled current source whose output depends
on the voltage applied to the FBN pin: the higher the transistor current, the greater the charge transferred to the
output during each switching cycle and therefore the higher (i.e., the more negative) the output voltage. The
internal block diagram of the negative charge pump is shown in Figure 44, and a typical application circuit in
Figure 45.
VIN

R
Short-Circuit
R Mode
FBB - 300μA
1.65V
+ Short-Circuit
Comparator
Control
FBN Logic Normal
+ Mode
2.5mA
- Error
Amplifier

CTRLN

Figure 44. Negative Charge Pump Internal Block Diagram

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VSWB

RFLY

CFLY

- VGL
CTRLN
COUT
+ CCOLLECTOR
RPULL-DOWN
ICTRLN
R1
FBN

R2
RFILTER
VLOGIC

CFILTER

Figure 45. Negative Charge Pump Application Circuit

The TPS65163 contains a circuit to protect the negative charge pump against short circuits on its output. A
short-circuit condition is detected as long as the FBN pin remains above 1.65 V, during which time the charge
pump output current is limited.
To ensure proper start-up under normal conditions, circuit designers should make sure the full load current is not
drawn by the load until the feedback voltage VFBN is below the short-circuit threshold voltage. The value of VGL
beyond which the negative charge pump no longer works in short-circuit mode is given by Equation 23.
æ R1 ö
VGL(SC) = - 1.65 V ´ ç1 - ÷
è R2 ø (23)

NEGATIVE CHARGE PUMP DESIGN PROCEDURE

Setting the Output Voltage (Negative Charge Pump)

The negative charge pump output voltage is programmed by a resistor divider according to Equation 24.
R
VGL = - VLO GIC ´ 1
R2 (24)
Rearranging Equation 25, the values of R1 and R2 are calculated.
VGL
R1 = R2 ´
VLOGIC (25)
A current of the order of 1 mA through the resistor network ensures accuracy and increases the circuit's immunity
to noise. It also ensures a minimum load on the charge pump, which reduces output voltage ripple under no-load
conditions. A good approach is to assume a value of about 3.3 kΩ for the lower resistor (R2) and then select the
upper resistor (R1) to set the desired output voltage.
Note that the maximum voltage in an application is determined by the boost converter output voltage and the
voltage drop across the diodes and NPN transistor. For a typical application in which the negative charge pump
is configured as a voltage inverter, the maximum (i.e., most negative) output voltage is given by Equation 26.
VGL(MAX) = - VIN + (2 ´ VF ) + VCE
(26)
where VF is the forward voltage of each diode and VCE is the collector-emitter voltage of the NPN transistor
(recommended to be at least 1 V to avoid transistor saturation).

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Selecting the NPN Transistor (Negative Charge Pump)

The NPN transistor used to regulate VGL should have a dc gain (hFE) of at least 100 when its collector current is
equal to the charge pump output current. The transistor should also be able to withstand voltages up to VIN
across its collector-emitter junction (VCE).
The power dissipated in the transistor is given by Equation 27. The transistor must be able to dissipate this
power without its junction becoming too hot. Note that the ability to dissipate power depends heavily on adequate
PCB thermal design.
PQ = éë V IN - (2 ´ VF ) - VGL ùû ´ IGL
(27)
where IGL is the mean (not RMS) output current drawn from the charge pump.

Selecting the Diodes (Negative Charge Pump)

Small-signal diodes can be used for most low-current applications (<50 mA) and higher-rated diodes for
higher-power applications. The average current through the diode is equal to the output current, so that the
power dissipated in the diode is given by Equation 28.
PD = IGL × VF
The peak current through the diode occurs during start-up and for a few cycles may be as high as a few
amperes. However, this condition typically lasts for <1 ms and can be tolerated by many diodes whose repetitive
current rating is much lower. The diodes' reverse voltage rating should be equal to at least 2 × VIN.

Table 7. Negative Charge Pump Diode Selection

PART NUMBER IAVG IPK VR VF COMPONENT SUPPLIER
BAV99W 150 mA 1 A for 1 ms 75 V 1 V at 50 mA NXP
BAT54S 200 mA 600 mA for 1 s 30 V 0.8 V at 100 mA Fairchild Semiconductor
MBR0540 500 mA 5.5 A for 8 ms 40 V 0.51 A at 500 mA Fairchild Semiconductor

Selecting the Capacitors (Negative Charge Pump)

For lowest output voltage ripple, low-ESR ceramic capacitors are recommended. The actual value is not critical,
and 1 µF to 10 µF is suitable for most applications. Larger capacitors provide better performance in applications
where large load transient currents are present.
A flying capacitor in the range 100 nF to 1 µF is suitable for most applications. Larger values experience a
smaller voltage drop by the end of each switching cycle and allow higher output voltages and/or currents to be
achieved. Smaller values tend to be physically smaller and a bit cheaper.
A collector capacitor in the range 100 nF to 1 µF is suitable for most applications. Larger values are more
suitable for high-current applications but can affect stability if they are too big.
A combination of COUT = 10 µF, CFLY = 1 µF, and CCOLLECTOR = 100 nF is a good starting point for most
applications (the final values can be optimized on a case-by-case basis if necessary).

POWER-SUPPLY SEQUENCING
Figure 46 shows the power-supply sequencing block diagram. The four supply rails generated by the TPS65163
turn on the following sequence: first VLOGIC, then VGL, then VGH and VS, as shown in Figure 46.
The buck converter turns on when the supply voltage exceeds the undervoltage threshold.
When the internal power-good signal of the buck converter has been asserted, the reset timer starts; after the
reset time is over, RST goes high and the negative charge pump is enabled. This sequence ensures that the
negative charge pump, which is driven by the switch node of the buck converter, does not attempt to draw
current until the T-CON is out of reset and drawing current from VLOGIC.
At the same time as the negative charge pump is enabled, an internal delay timer is started. This timer generates
a delay, after which the boost converter and positive charge pump are enabled. The delay time tDLY is
determined by the capacitor CDLY connected between the DLY pin and AGND according to Equation 29.

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CDLY ´ VREF
tDLY =
IDLY (29)
No special sequencing is implemented during power-down, and all power supplies are disabled if VIN falls below
VUVLO.

To Buck
OUT
Converter
UVLO EN Buck
To Negative
RESET Charge Pump
Reset
PG IN
Generator
RESET

Delay OUT To Boost

IN
Converter

Latched
To Positive
Charge Pump

CRST RST DLY

Figure 46. Power Supply Sequencing Block Diagram

VIN > VUVLO

VIN

VLOGIC VLOGIC > VPG

PG

tRST
RST

VGL

VGH tDLY

VS

Figure 47. Power Supply Sequencing

POWER-SUPPLY SEQUENCING IN DETAIL

The detailed start-up behavior of the boost converter and positive charge pump is illustrated in Figure 48.

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RST tDLY

≈1ms
GD

VS
≈VIN
VS

VIN
VSW

1.24V

VFBP 100mV

VGH

TIME

Figure 48. Boost Converter and Positive Charge Pump Detailed Start-Up Behavior

The isolation switch is enabled when the GD pin goes low, tDLY seconds after RST goes high. When the isolation
switch turns on, VS rises at a rate determined by the RC network controlling the switch's gate and the amount of
capacitance on the output. The TPS65163 senses the rising VS via the CTRLP pin, and 1 ms after GD goes low
checks that VS ≈ VIN. If it is, then the boost converter is enabled. This scheme prevents the boost converter from
switching before the isolation switch is fully enabled, which could otherwise cause overvoltage conditions to
damage the switch node. If VS does not reach ≈VIN within 1 ms of the GD pin going low, the TPS65163 detects
an error condition and the boost converter is not enabled.
The positive charge pump short-circuit mode is enabled when the GD pin goes low. Although the boost converter
is not switching at this point, there is a dc path from VS to VGH, and the output ramps up as current flows into the
collector capacitor and output capacitors. When VFBP reaches 100 mV, the IC determines that no short circuit
exists, and the output current from the CTRLP pin is disabled temporarily. (If there is no significant load
connected to VGH, the output voltage remains almost constant, held up by the output capacitance; if there is a
load, the output voltage decays.) When the boost converter starts switching, normal operation of the positive
charge pump is enabled, and VGH ramps up to its programmed value. (Note that the positive charge pump
implements a soft-start characteristic that ramps the current available from the CTRLP pin over time. This causes
the collector voltage of the regulating PNP to go temporarily negative.)

RESET GENERATOR
The reset generator generates an active low signal that can used to reset the timing controller used in LCD
applications. The RST output is an open-drain type and requires an external pullup resistor. This signal is
typically pulled up to the 3.3-V supply generated by the buck converter, which also supplies the timing controller
I/O functions.
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Reset pulse timing starts when the internal power-good signal of the buck converter is asserted, and its duration
is set by the size of the capacitor connected between the CRST pin and AGND, as described by Equation 30.
C ´ VREF
tRST = RST
IRST (30)
The duration of the reset pulse also affects power-supply sequencing, as the boost converter and positive charge
pump are not enabled until the reset pulse is finished. In applications that do not require a reset signal, the RST
pin can be left floating or tied to AGND. This does not prevent the boost converter or positive charge pump from
starting.
If the CRST pin is left open-circuit, the duration of the reset pulse is close to zero (determined only by the
parasitic capacitance present), and the boost converter and positive charge pump start up instantaneously.
Alternatively, the CRST pin can be used to enable the boost converter and charge pumps by connecting a 3.3-V
logic-level ENABLE signal via a 10-kΩ resistor, as shown in Figure 49. Using this scheme, the buck converter
starts as soon as VIN exceeds the UVLO threshold, but the negative charge pump is not enabled until ENABLE
goes high. The boost converter and positive charge pump are enabled tDLY seconds after ENABLE goes high,
where tDLY is defined by the capacitor connected to the DLY pin. The resulting power-supply sequencing is
shown in Figure 50.

TPS65163

10 kW
ENABLE CRST

Figure 49. Using an ENABLE Signal to Control Boost Converter and Charge Pumps

VIN > VUVLO

VIN

VLOGIC VLOGIC > VPG

ENABLE

RST

VGL

VGH tDLY

VS

Figure 50. Power-Supply Sequencing Using an ENABLE Signal

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Undervoltage Lockout
An undervoltage lockout function inhibits the device if the supply voltage VIN is below the minimum needed for
proper operation.

Thermal Shutdown
A thermal shutdown function automatically disables all LCD bias functions if the device junction temperature
exceeds ≈150°C. The device automatically starts operating again once it has cooled down to ≈140°C.

Level Shifters and Gate Shaping

The nine level-shifter channels in the TPS65163 are divided into two groups. Channels 1 through 7 are powered
from VGH1 and VGL, channels 8 and 9 are powered from VGH2 and VGL. Channels 1 to 6 support gate shaping and
channels 7 through 9 do not. Figure 51 contains a simplified block diagram of one channel with gate voltage
shaping.
VGH1

INX Q1
From Timing
Controller Channel OUTX To LCD panel
FLKX Control
Q2

Q3

VGL RE

RE

Figure 51. Level Shifter Channel with Gate Voltage Shaping

On the rising edge of IN, Q1 turns on, Q2 and Q3 turn off, and OUT is driven to VGH1. On the falling edge of FLK,
Q1 turns off, Q3 is turned on, and the panel now discharges through Q3 and RE (see Figure 52). On the falling
edge of IN, Q2 turns on and Q3 turns off, and OUT is driven to VGL. This sequence is repeated in turn for each
channel.

VLOGIC
INX
GND

VLOGIC
FLKX
GND

VGH1
OUTX
VGL
Gate shaping starts on
falling edge of FLKX Gate shaping stops on
falling edge of INX

Figure 52. Gate Voltage Shaping Timing Diagram

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The alternative configuration shown in Figure 53 can be used to define a minimum gate voltage reached during
gate voltage shaping.
VGH1

INX Q1
From Timing
Controller Channel OUTX To LCD panel
FLKX Control
Q2

VGH1
Q3

RE1
RE
VGL

RE2

Figure 53. Alternative Gate Voltage Shaping Circuit Configuration

In this circuit, resistors RE1 and RE2 define both the rate of change of gate voltage decay and the minimum gate
voltage VMIN. Using the Thevenin equivalent, the operating parameters of Figure 53 are calculated.
RE2
VMIN = VGH1 x
RE1 + RE2 (31)
RE1 x RE2
RE =
RE1 + RE2 (32)

Flicker Clocks
The gate voltage shaping control logic in the TPS65163 allows the device to be used with one, two or three
flicker clock signals, according to the application requirements.
In six-phase applications where one signal controls gate voltage shaping for six CLK channels, the flicker clock
should be connected to FLK1 and the unused pins FLK2 and FLK3 connected to GND.
In six-phase applications where three signals control gate voltage shaping for six CLK channels, the flicker clock
for channels 1 and 4 should be connected to FLK1, the flicker clock for channels 2 and 5 connected to FLK2,
and the flicker clock for channels 3 and 6 connected to FLK3.
In four-phase applications where two signals control gate voltage shaping for four CLK channels, the flicker clock
for phases 1 and 3 should be connected to FLK1, the flicker clock for phases 2 and 4 connected to FLK2, and
the unused FLK3 pin connected to GND. The unused pins IN3 and IN6 should be connected to VLOGIC.
Alternatively, IN3 can be connected to IN2 and IN6 connected to IN5; this arrangement can simplify PCB layout.
Gate voltage shaping is started by the falling edge of the FLK signal(s), which must occur during a valid part of
the clock waveform. For six-phase systems, this means the last 60° of the clock waveform; for four-phase
systems, this means the last 90° of the clock waveform (see Figure 54 and Figure 55). Falling edges of the FLK
signal(s) occurring outside the valid part of the clock waveform are ignored. The rising edge of the FLK signal(s)
has no effect, regardless of when it occurs.

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IN1

IN2

IN3

IN4

IN5

IN6

Figure 54. FLK Falling Edge Validity, Six-Phase Applications

IN1

IN2

IN3

IN4

IN5

IN6

Figure 55. FLK Falling Edge Validity, Four-Phase Applications

Level Shifters Without Gate Voltage Shaping

Channels 7 through 9 do not support gate voltage shaping and are controlled only by the logic level applied to
their INx pin. Figure 56 contains a block diagram of a channel that does not support gate voltage shaping.

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VGH1

Q1

From Timing INX Channel OUTX To LCD panel

Controller Control
Q2

VGL

Figure 56. Block Diagram of Level Shifter Without Gate Voltage Shaping

Panel Discharge
The TPS65163 contains a function for discharging the display panel during power down. The discharge function
comprises a comparator and a level shifter (see Figure 57). During normal operation, the voltage applied to the
VSENSE pin is greater than VREF, the output of the level shifter is low, and the DISCHARGE signal is at VGL.
During power down, when the voltage applied to the VSENSE pin falls below VREF, the level shifter output goes
high and the DISCHARGE signal tracks VGH1 as it discharges (see Figure 35 and Figure 36).
VX
VGH1

R1
VSENSE -
DISCHARGE
1.5V +
R2

VGL

Figure 57. Panel Discharge Function Block Diagram

Suitable values for resistors R1 and R2 in Figure 57 are calculated using Equation 33.
æ V ö
R1 = R2 x ç X - 1÷
è 1.5V ø (33)
where VX is the voltage used to activate/deactivate the discharge function.
For most applications, a value between 1 kΩ and 10 kΩ for R2 can be used (R1 depends on the value of R2 and
the value of VX).

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APPLICATION INFORMATION
SW
10µH SL22 Si2307
(12V) VIN VS (15.6V @ 1.5A)
44µF 30µF 30µF

10nF
100k
100k

SW
SW
1nF
33k
COMP
VIN 15k
GD
VIN
FB

1.3k

100nF DLY
22nF SS FBB
22nF CRST
10µH
RST RST SWB VLOGIC (3.3V @ 1.5A)
SL22 44µF
100nF VL

VGL
2R VGH1
SWB
100nF VGH2
MMBT22222A MMBT2907A BAT54S
VS
BAT54S 100k

100nF
5.1k 100k
10µF 100nF CTRLN 100nF 10µF
20k
FBN CTRLP SW
FBP
2.4k FLK1 FLK1
FLK2 FLK2 1k
VLOGIC
FLK3 FLK3
100nF
10k

VSENSE DISCH DISCH

IN1 IN1 OUT1 OUT1
10k
IN2 IN2 OUT2 OUT2
IN3 IN3 OUT3 OUT3
IN4 IN4 OUT4 OUT4
IN5 IN5 OUT5 OUT5
IN6 IN6 OUT6 OUT6
IN7 IN7 OUT7 OUT7
IN8 IN8 OUT8 OUT8
IN9 IN9 OUT9 OUT9

PGND
1k
PGND RE
AGND

Figure 58. Typical LCD Bias Application Circuit

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 PACKAGE OPTION ADDENDUM

www.ti.com 3-Dec-2010

PACKAGING INFORMATION

Orderable Device Status

(1) Package Type Package Pins Package Qty Eco Plan
(2) Lead/ MSL Peak Temp
(3) Samples
Drawing Ball Finish (Requires Login)
TPS65163RGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR Request Free Samples
& no Sb/Br)
TPS65163RGZT ACTIVE VQFN RGZ 48 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR Purchase Samples
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65163RGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS65163RGZR VQFN RGZ 48 2500 367.0 367.0 38.0

Pack Materials-Page 2
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