BITS Pilani

Pilani Campus

CMOS
Design Manufacturing Process
Why should designer know fab?

• Design performance varies after fab.

• Due to process variations-

Dimensions vary due to shifting of masks,

Dopants diffusing beneath the masks,
Undercutting during wet etching.

• Hence MOS parameters like gm, W, L, ID varies .

So we have to design with sufficient margins.

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Lateral diffusion

Under cutting

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CMOS processing

• N-WELL
• P-WELL
• TWIN-TUB, TRIPLE WELL
• SOI

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Wafer preparation

• Defect free single crystalline lightly doped

WAFER.
• Metallurgical grade silicon-electronic grade
silicon(99.99% pure)
• Single crystalline structure obtained by
melting and then cooling ---Czochralski
method
• Ingot cut into wafers using diamond saw
• Wafers are than polished to mirror finish

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Process involved

• Deposition
• Oxidation
• Etching
• Diffusion/ion implantation

Photolithography

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Layout

vdd
gnd

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CMOS Process
cross sectional diagram n well process

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Lithography
Lithography: process used to transfer patterns to each
layer of the IC
Lithography sequence steps:
• Designer:
– Drawing the layer patterns on a layout editor
• Silicon Foundry:
– Masks generation from the layer patterns in the design
data base
– Printing: transfer the mask pattern to the wafer surface
– Process the wafer to physically pattern each layer of the IC

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Lithography
1. Photoresist coating
Basic sequence Photoresist

• The surface to be patterned is:

SiO2
– spin-coated with photoresist Substrate

– the photoresist is dehydrated in an oven 2. Exposure

Opaque Ultra violet light
(photo resist: light-sensitive organic polymer)
• The photo-resist is exposed to ultra violet Mask

light: Unexposed Exposed

– For a positive photoresist exposed areas

become soluble and non exposed areas
remain hard Substrate

• The soluble photo-resist is chemically 3. Development

removed (development).
– The patterned photoresist will now serve as an
Substrate
etching mask for the SiO2

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1. Photoresist coating
Photoresist

SiO2
Substrate

2. Exposure
Opaque Ultra violet light

Mask

Unexposed Exposed

Substrate

3. Development

Substrate
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Lithography

• The SiO2 is etched away 4. Etching

leaving the substrate exposed:

– the patterned resist is used as the
etching mask Substrate

• Ion Implantation:
5. Ion implant
– the substrate is subjected to
highly energized donor or
acceptor atoms
– The atoms impinge on the surface
and travel below it Substrate

– The patterned silicon SiO2 serves 6. After doping

as an implantation mask
• The doping is further driven
into the bulk by a thermal cycle Substrate
diffusion

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4. Etching

Substrate

5. Ion implant

Substrate

6. After doping

diffusion Substrate

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Lithography
• The lithographic sequence is repeated for
each physical layer used to construct the IC.

• The sequence is always the same:

– Photo-resist application
– Printing (exposure to UV light)
– Development
– Etching

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Lithography
Patterning a layer above the silicon surface
1. Polysilicon deposition 4. Photoresist development
Polysilicon

SiO2
Substrate Substrate
2. Photoresist coating 5. Polysilicon etching
photoresist

Substrate Substrate
3. Exposure UV light
6. Final polysilicon pattern

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Substrate Substrate
Lithography
• Etching: anisotropic etch (ideal)
– Process of removing unprotected resist

material
layer 1
– Etching occurs in all directions
layer 2
– Horizontal etching causes an under
cut
– “preferential” etching can be used to isotropic etch
undercut resist
minimize the undercut
• Etching techniques: layer 1
– Wet etching: uses HF-containing layer 2
etching solutions to remove the
unprotected materials
preferential etch
– Dry or plasma etching: uses undercut resist
ionized gases rendered chemically
active by an RF-generated plasma layer 1
layer 2

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 Physical structure

NMOS physical structure: NMOS layout representation:

– p-substrate  Implicit layers:
– n+ source/drain » oxide layers
– gate oxide (SiO2) » substrate (bulk)
– polysilicon gate  Drawn layers:
– CVD oxide » n+ regions
– metal 1 » polysilicon gate
– Leff< Ldrawn (lateral doping » oxide contact cuts,
effects)
» metal layers

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Physical structure Layout representation Schematic representation

CVD oxide
Poly gate Metal 1

Source Ldrawn Drain Ldrawn G

S D
n+ n+ Wdrawn
Leffective
B
Gate oxide

p-substrate (bulk)
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 Physical structure

PMOS physical structure: PMOS layout representation:

– p-substrate  Implicit layers:
– n-well (bulk) » oxide layers
– p+ source/drain  Drawn layers:
– gate oxide (SiO2) » n-well (bulk)
– polysilicon gate » n+ regions
– CVD oxide, metal 1 » polysilicon gate,
» oxide contact cuts,
» metal layers

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Physical structure Layout representation Schematic representation

CVD oxide
Poly gate Metal 1

Source Ldrawn Drain

Ldrawn G

S D
p+ p+ Wdrawn
Leffective
B
Gate oxide
n-well (bulk) n-well

p-substrate
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VDD
M2
Vin V
M1
View from Top

vin
gnd vdd

S D D S
vout

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Cross sectional diagram

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Layout
gnd

vdd

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CMOS fabrication sequence
0. Start:
– For an n-well process the starting point is a p-type silicon wafer:
– wafer: typically 75 to 230mm in diameter and less than 1mm
thick
1. Epitaxial growth:
– A single p-type single crystal film is grown on the surface of the
wafer by:
• subjecting the wafer to high temperature and a source of dopant
material

– The epi layer is used as the base layer to build the devices
p-epitaxial layer Diameter = 75 to 230mm

< 1mm
P+ -type wafer

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CMOS fabrication sequence
2. N-well Formation:
– PMOS transistors are fabricated in n-well regions
– The first mask defines the n-well regions
– N-well’s are formed by ion implantation or deposition and
diffusion
– Lateral diffusion limits the proximity between structures
– Ion implantation results in shallower wells compatible with
today’s fine-line processes
Physical structure cross section Mask (top view)
n-well mask
Lateral
diffusion

n-well

p-type epitaxial layer

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4. Etching

Substrate

5. Ion implant

Substrate

6. After doping

diffusion Substrate

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N well mask

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CMOS fabrication sequence
3. Active area definition:
– Active area:
• planar section of the surface where transistors are build
• defines the gate region (thin oxide)
• defines the n+ or p+ regions
– A thin layer of SiO2 is grown over the active region and covered with
silicon nitride

Stress-relief oxide Silicon Nitride Active mask

n-well

p-type
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Active mask

The temperature stability of silicon nitride protects the n-channel FETs from the
effects of the high energy levels and currents associated with the ion implant step
used to form the S/D regions of the p-channel FETs.

In contrast, the implant ions readily penetrate the thin stress relief oxide over the
S/D regions of the p-channel FETs
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• Thereafter, a second, silicon nitride layer of controlled thickness is
deposited. Again, it is followed by a dry etch step, but now to expose
the silicon dioxide covering the n-channel FET S/D regions.

• The succeeding n-channel S/D implant similarly penetrates the

silicon dioxide coverings, while the silicon nitride serves as a barrier
for the remaining substrate surface. After S/D implanting is
completed, a highly preferential etchant is used to remove the
remaining silicon nitride, while the areas protected by the relatively
thin layers of silicon dioxide are substantially unaffected.

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CMOS fabrication sequence
4. Isolation:

– Parasitic (unwanted) FET’s exist between unrelated

transistors (Field Oxide FET’s)

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Field Oxide Growth

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Impact of FOX- parasitic MOS
–We have Source and drains which are existing
source and drains of wanted devices
–Second layer is Field oxide
–Gates are metal and poly-silicon interconnects on
top of Fox

–Parastic MOS should not conduct

–So, the threshold voltage of FOX FET’s should be

higher.

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Parasitic FOX device

n+ n+ n+ n+

p-substrate (bulk)
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CMOS fabrication sequence
– FOX FET’s threshold is made high by:
• introducing a channel-stop diffusion that raises the impurity
concentration in the substrate in areas where transistors are not
required
• making the FOX thick
4.1 Channel-stop implant
– The silicon nitride (over n-active) and the photoresist (over n-well)
act as masks for the channel-stop implant

Implant (Boron) channel stop mask = ~(n-well mask)

resit

n-well

p+ channel-stop implant
p-type
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CMOS fabrication sequence
4.2 Local oxidation of silicon (LOCOS)
– The photoresist mask is removed by HF solution
– The SiO2/SiN layers will now act as a masks
– The thick field oxide is then grown by:
• exposing the surface of the wafer to a flow of oxygen-rich gas
– The oxide grows in both the vertical and lateral directions
– This results in an active area smaller than patterned

patterned active area

Field oxide (FOX)

n-well
active area after LOCOS

p-type
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CMOS fabrication sequence
• Silicon oxidation is obtained by:
– Heating the wafer in a oxidizing atmosphere:
• Wet oxidation: water vapor, T = 900 to 1000ºC (rapid process)
• Oxidation consumes silicon
– SiO2 has approximately twice the volume of silicon
– The FOX recedes below the silicon surface by 0.46XFOX

Field oxide

XFOX
0.54 XFOX Silicon surface
0.46 XFOX

Silicon wafer
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CMOS fabrication sequence
5. Gate oxide growth-
Dry oxidation: Pure oxygen, T = 1200ºC (high temperature required to
achieve an acceptable growth rate). Slow process

– The nitride and stress-relief oxide are removed

– The devices threshold voltage is adjusted by:
• adding charge at the silicon/oxide interface
– The well controlled gate oxide is grown with thickness tox. Etching is by
buffered oxide etchant (mixture of NH4F and HF)

n-well

p-type

Gate oxide
tox tox

n-well

p-type 45
CMOS fabrication sequence
6. Polysilicon deposition and patterning
– A layer of polysilicon is deposited over the entire wafer surface
– The polysilicon is then patterned by a lithography sequence
– All the MOSFET gates are defined in a single step
– The polysilicon gate can be doped (n+) while is being deposited to
lower its parasitic resistance (important in high speed fine line
processes)

Polysilicon mask
Polysilicon gate

n-well

p-type

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Poly mask

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Gate Undercutting

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CMOS fabrication sequence
7. NMOS formation
– PMOS shielded
– Photoresist is patterned to define the n+ regions
– Donors (arsenic or phosphorous) are ion-implanted to
dope the n+ source and drain regions
– The process is self-aligned w.r.t gate, no mask required
– The gate is n-type doped

n+ implant (arsenic or phosphorous)

n+ mask

n-well
Photoresist
p-type
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N+ diffusion mask

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 CMOS fabrication sequence
8. PMOS formation
– Photoresist is patterned to cover all but the p+ regions
– A boron ion beam creates the p+ source and drain regions
– The polysilicon serves as a mask to the underlying channel
• This is called a self-aligned process
• It allows precise placement of the source and drain
regions
– During this process the gate gets doped with p-type
impurities
• Since the gate had been doped n-type during deposition, the
final type (n or p) will depend on which dopant is dominant
p+ implant (boron)
p+ mask

n-well
Photoresist
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p-type
P+ diffusion mask

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Poly diodes
N type

P type

Metal clampers are used to short

Or Silicided poly causes two sides to short automatically
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CMOS fabrication sequence
9. Annealing
– After the implants are completed a thermal annealing cycle is
executed
– This allows the impurities to diffuse further into the bulk
– After thermal annealing, it is important to keep the remaining
process steps at as low temperature as possible

n-well
n+ p+
p-type

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CMOS fabrication sequence
10. Contact cuts
– The surface of the IC is covered by a layer of CVD oxide
• The oxide is deposited at low temperature (LTO) to avoid that
underlying doped regions will undergo diffusive spreading
– Contact cuts are defined by etching SiO2 down to the surface to
be contacted
– These allow metal to contact diffusion and/or polysilicon regions
Contact mask

n-well
n+ p+
p-type

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Contact- cut mask

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CMOS fabrication sequence
11. Metal 1
– A first level of metallization is applied to the wafer surface and
selectively etched to produce the interconnects

metal 1 mask
metal 1

n-well
n+ p+
p-type

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Metal mask

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CMOS fabrication sequence
12. Metal 2
– Another layer of LTO CVD oxide is added
– Via openings are created
– Metal 2 is deposited and patterned

metal 2
Via metal 1

n-well
n+ p+
p-type

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CMOS fabrication sequence
13. Over glass and pad openings
– A protective layer is added over the surface:
– The protective layer consists of:
• A layer of SiO2
• Followed by a layer of silicon nitride
– The SiN layer acts as a diffusion barrier against contaminants
(passivation)
– Finally, contact cuts are etched, over metal 2, on the passivation
to allow for wire bonding.

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Wire bonding pad structures

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Micro photograph of fabricated chip

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Enhancements
3 D integration

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Layout of gates

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Circuit Under Design

VDD VDD

M2
M4

Vin Vout Vout2

M1 M3

This two-inverter circuit (of Figure 3.25 in the text) will be

manufactured in a twin-well process.
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Circuit Layout

vdd

gnd

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Start Material

Starting wafer: n-type with

A’ doping level = 10 13/cm3

* Cross-sections will be
shown along vertical line A-A’

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N-well Construction

(1) Oxidize wafer

(2) Deposit silicon nitride
(3) Deposit photo-resist

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N-well Construction

(4) Expose resist using n-well

mask

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N-well Construction

(5) Develop resist

(6) Etch nitride and
(7) Grow thick oxide

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N-well Construction

(8) Implant n-dopants (phosphorus)

(up to 1.5 mm deep)

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P-well Construction

Repeat previous steps

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Grow Gate Oxide

0.055 mm thin

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Grow Thick Field Oxide

0.9 mm thick

Uses Active Area mask

Is followed by
threshold-adjusting implants

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Polysilicon layer

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Source-Drain Implants

n+ source-drain implant
(using n+ select mask)

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Source-Drain Implants

p+ source-drain implant
(using p+ select mask)

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Contact-Hole Definition

(1) Deposit inter-level

dielectric (SiO2) — 0.75 mm

(2) Define contact opening

using contact mask

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Aluminum-1 Layer

Aluminum evaporated
(0.8 mm thick)
followed by other metal
layers and glass

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Advanced multiple Metalization

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 LATCH-UP

Why multiple bulk contacts?

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Latchup in Bulk CMOS

• A byproduct of the Bulk CMOS structure is a pair of

parasitic bipolar transistors.

• The collector of each BJT is connected to the base of

the other transistor in a positive feedback structure.

• A phenomenon called latchup can occur when

(1) both BJT's conduct, creating a low resistance path
between Vdd and GND and

(2) the product of the gains of the two transistors in the

feedback loop, b1 x b2, is just greater than one..
Means sustained latch-up
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The result of latch-up is at the

minimum--- a circuit malfunction,

in the worst case, the destruction of the

device

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 Latch-up

VD D
VDD
Rnwell
p-source
+ + + + + +
p n n p p n
n-well Rnwell

Rpsubs n-source
Rpsubs
p-substrate

(a) Origin of latchup (b) Equivalent circuit

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Positive feedback loop----Equivalent Circuit

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Sources of latchup

• The most likely place for latchup to occur

is in pad drivers, where large voltage
transients and large currents are present.

• Latch-up may begin when Vout drops

below GND due to a noise spike or an
improper circuit hookup

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Preventing latchup

Fab/Design Approaches
Reduce the gain product β1 x β2
– move n-well and n+ source/drain farther apart
increases width of the base of Q2 and reduces gain
beta2 > also reduces circuit density
– buried n+ layer in well reduces gain of Q1
• Reduce the well and substrate resistances, producing
lower voltage drops
– higher substrate doping level reduces Rsub
– reduce Rwell by making low resistance contact to
VDD /GND
– guard rings around p- and/or n-well, with frequent
contacts to the rings, reduces the parasitic
resistances.
• CMOS transistors with guard rings with multiple bulk
contacts 90
CMOS transistors with guard rings

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Systems Approaches

• Make sure power supplies are off before

plugging a board.
• A "hot plug in" of an un-powered circuit
board or module may cause signal pins to
see surge voltages greater than 0.7 V
higher than Vdd, which rises more slowly
to is peak value. When the chip comes up
to full power, sections of it could be
latched. 92
Standrd cell template for avoiding
latchup

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