DR Somashekhar: Indian Institute of Technology Madras, Chennai - 600 036
DR Somashekhar: Indian Institute of Technology Madras, Chennai - 600 036
System Bus
Microprocessor Serial Interface
6 Cannot be used in compact systems Can be used in compact system and hence efficient
7 Power consumption is high. Power consumption is less
1971-1979 Large Scale Integration (LSI) 500-20,000 4 & 8 bit µP, RAM, ROM
1980-1984 Very Large Scale Integration (VLSI) 20,000-1,00,000 DSP, RISC, 16 & 32 bit µP
1985 onwards Ultra Large Scale Integration (ULSI) Above 1,00,000 64 bit µP
Recap
Moore’s Law No. of Transistors in the Processor
Sl. No Processor Data Year of No. of CPU Speed
Length Introduction Transistors
1 4004 4 bits 1971 2250 740 kHz
Computer
Memory
CPU Elements
Interconnections
I/O
Devices
Computer Architecture
Program Memory
Processor Program Memory Processor Data Memory
&
Data Memory
Harvard Architecture
von Neumann Architecture
von Neumann Computer Architecture
Program Memory
Processor
&
Data Memory
• Computer has single storage system (memory) for storing data as well as
program to be executed.
• Processor needs two clock cycles to complete an instruction
• In the first clock cycle the processor gets the instruction from memory and
decodes it. In the next clock cycle the required data is taken from memory.
• For each instruction this cycle repeats and hence needs two cycles to complete
an instruction.
Harvard Computer Architecture
Harvard Architecture
• The computer has two separate memories for storing data and program.
• Processor can complete an instruction in one cycle if appropriate pipelining
strategies are implemented.
• In the first stage of pipeline the instruction to be executed can be taken from
program memory. In the second stage of pipeline data is taken from the data
memory using the decoded instruction or address
• Most of the modern computing architectures are based on Harvard
architecture. But the number of stages in the pipeline varies from system to
system.
John von Neumann Architecture of Computer
• Consists of : CPU; Memory and I/O Devices
(a set of instructions)
Control DATA
STORED PROGRAM
Unit System Bus:
(Address bus; Data Bus and Control Bus)
& 4
PROGRAMME 3
Arithmetic and
Control Unit 2
I/O Devices
• Basic Characteristics of von-Neumann Architecture are
Both Data and Instructions are stored in Read/Write (R/W) Memory
Contents of the R/W memory are accessed by Location (0 to n)
The instructions stored in memory are accessed and executed sequentially
John von Neumann Architecture of Computer
• In this von Neuman architecture, the CPU fetches instructions from the
memory, decodes it (i.e. Interprets the nature of the instruction/command and
develops clock-synchronized steps for execution), generates appropriate
control signals and finally executes it
• The program is stored in consecutive memory locations
• The execution steps are repeated for all the instructions of the program until
the execution is terminated by hardware or software
• The data required may be taken either from memory or from input ports; the
results of the program may be either stored in the memory or transferred out
through the output ports
Origin of
Microprocessors or Micro Processing Unit (MPU)
80286 (i286)
80286
80186
8088
8086
8085
8080
8008
4004 (1971)