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Iqra University Coa/Caal Assignment Due Date 23 May 2020

1. The document contains two questions related to computer architecture. The first question asks to determine the values of registers AX, BX, CX, DX after executing four MOV instructions using given memory locations and register values. 2. The second question asks to draw a timing diagram showing the pipeline stages and execution times for two instructions, and calculate the clock cycles and time to execute the instructions 500 times. The pipeline has 5 stages with different execution times for each stage. 3. The document provides memory location values, register values, instruction details, and pipeline stage details needed to answer the two questions.

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Farrukh Abbasi
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34 views2 pages

Iqra University Coa/Caal Assignment Due Date 23 May 2020

1. The document contains two questions related to computer architecture. The first question asks to determine the values of registers AX, BX, CX, DX after executing four MOV instructions using given memory locations and register values. 2. The second question asks to draw a timing diagram showing the pipeline stages and execution times for two instructions, and calculate the clock cycles and time to execute the instructions 500 times. The pipeline has 5 stages with different execution times for each stage. 3. The document provides memory location values, register values, instruction details, and pipeline stage details needed to answer the two questions.

Uploaded by

Farrukh Abbasi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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IQRA University

COA/CAAl Assignment
Due date 23rd may 2020
Q1- (Related to lecture 12) Given that
[BP] = 5000 [SI] = 0005 [DI]=0100
[6000] = 520A [6005] = 5402 [6100] = 0003 [6015]=065B
[6110] = 003E [5100] = FB05 [5005] = 060B [5000] = 5505
After the following instructions are executed, What will be the value
of registers AX,BX,CX,DX ? DS is a segment register for all instructions
and DS address is not given.

MOV AX,[BP]
MOV DX, [5100]
MOV BX,5[BP]
MOV CX,[BP][DI]

Question 2- (Related to lecture 13 Pipelining)


• A pipeline is designed with 5 stages ( FI DI FO EI WO) having
execution times respectively as 3ns, 2ns, 1ns, 1ns and 2ns. For the
execution of

• Sub R1, R4, R3 -- ------------------- R1=R4-R3

• Add R2, R1, R6 -- --------------------- R2=R1+R6


1-Draw timing diagram showing all the stages and execution
times, and also
2- How much clock cycles/ ns will it take to execute above
instructions 500 times?
Where, FI=fetch instruction
DI = decode instruction
FO =fetch operands
EI = Execute instruction
WO= write operands

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