DEPARTAMENTO DE ELÉCTRICA Y ELECTRÓNICA

CARRERA DE INGENIERÍA EN ELECTRÓNICA Y TELECOMUNICACIONES

Diseño VLSI

NRC: 8417

Laboratorio.

TERCER PARCIAL

Preparatorio.

PROFESOR: ING. PABLO FRANCISCO RAMOS VARGAS

INTEGRANTES:
JONATHAN CHASI
JOSE GUTIERREZ

MAYO-2020
1. TEMA: - Preparatorio memoria SRAM avance.

2. OBJETIVOS:
 Solucionar el problema planteado mediante lenguaje VHDL y Assembler.
 Instanciar una memoria en el proyecto Picoblaze, en el cual se pueda
escribir y leer.
 Presentar el diagrama de tiempo timming para los procesos de lectura y
escritura.
3. DISEÑO.
3.1. Diagrama de bloques

PICO BLAZE

CLK

CE
8
RAM
WE DQ

OE
8
A

DQ

8
 3.2. Diagrama de FLUJO.

3.3. Código del diseño.

Código assembler:

ADDRESS 000

main:
INPUT S0,01
OUTPUT S0,03
INPUT S1,02
OUTPUT S1,04
JUMP main
Codigo TopModule

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:42:06 06/10/2011
-- Design Name:
-- Module Name: TopModule - Behavioral
-- Project Name:
-- Target Devices:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity TopModule is
Port ( --RESET : in STD_LOGIC;
CLK_50MHz : in STD_LOGIC;
-- interrupts
INT : in STD_LOGIC;
--INT_ACK : out STD_LOGIC;
-- output data
CE_b_top : IN Std_Logic;
-- Chip Select
WE_b_top : IN Std_Logic;
-- Write Enable
OE_b_top : IN Std_Logic; -- Output Enable
A_top : IN Std_Logic_Vector(7 downto 0); -- Address Inputs
DQ_top : INOUT Std_Logic_Vector(7 downto 0):=(others=>'Z') -- Read/Write
Data
);
end TopModule;

architecture Behavioral of TopModule is

component embedded_kcpsm3
Port ( port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
read_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
signal wr_stb : std_logic;
signal rd_stb : std_logic;
signal port_id : std_logic_vector(7 downto 0);
signal out_port: std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal mem_addr : std_logic_vector(7 downto 0);
signal data_to_memory : std_logic_vector(7 downto 0);
signal data_from_memory : std_logic_vector(7 downto 0);
signal wr_en : std_logic;
signal mem_en : std_logic;
signal in_proc : std_logic_vector(7 downto 0);
signal out_proc : std_logic_vector(7 downto 0);
signal add_aux : std_logic_vector(7 downto 0);
signal auxi : std_logic_vector(7 downto 0);
signal auxo : std_logic_vector(7 downto 0);
signal auxDQ : std_logic_vector(7 downto 0);
signal aux_w : std_logic_vector(7 downto 0);
signal aux_r : std_logic_vector(7 downto 0);

component CY7C1062_0 port(

CE_b : IN Std_Logic; -- Chip Select
WE_b : IN Std_Logic; -- Write Enable
OE_b : IN Std_Logic; -- Output Enable
A : IN Std_Logic_Vector(7 downto 0); -- Address Inputs
DQ : INOUT Std_Logic_Vector(8-1 downto 0):=(others=>'Z'));
end component;

begin
-- instantiation
Processor: embedded_kcpsm3
port map(
port_id => port_id,
write_strobe => wr_stb,
read_strobe => rd_stb,
out_port => out_port,
in_port => in_port,
interrupt => INT,
--interrupt_ack => INT_ACK,
reset => '0', --RESET,
clk => CLK_50MHz
);
input_ports: process (port_id)
begin
case port_id is
when "00000001" => in_port <= "0000000" & WE_b_top ;
when "00000010" => in_port <= "0000000" & OE_b_top;
--when "00011001" => in_port <= in_proc;
when others => auxi <= "XXXXXXXX";
end case;
end process input_ports;

output_ports: process(port_id)
begin
case port_id is
when "00000011" => aux_w <= out_port;
when "00000100" => aux_r <= out_port;
when others => auxo <= "XXXXXXXX";
-- out_proc <= "XXXXXXXX";
end case;
end process output_ports;
U1: CY7C1062_0 port map(CE_b_top,aux_w(0),aux_r(0),A_top,DQ_top);
end Behavioral;
Codigo Testbench:
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:27:30 08/31/2020
-- Design Name:
-- Module Name: C:/Users/jona0/Desktop/Primera Parte/picoblaze_2020/TEST1M.vhd
-- Project Name: PicoBlaze_ExtMemory
-- Target Device:
-- Tool versions:
-- Description:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY TEST1M IS
END TEST1M;

ARCHITECTURE behavior OF TEST1M IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT TopModule
PORT(
CLK_50MHz : IN std_logic;
INT : IN std_logic;
CE_b_top: IN std_logic;
WE_b_top : IN std_logic;
OE_b_top : IN std_logic;
A_top : IN std_logic_vector(7 downto 0);
DQ_top : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;

--Inputs
signal CLK_50MHz : std_logic := '0';
signal INT : std_logic := '0';
signal CE_b_top : std_logic := '0';
signal WE_b_top : std_logic := '0';
signal OE_b_top : std_logic := '1';
signal A_top : std_logic_vector(7 downto 0) := (others => '0');
 --BiDirs
signal DQ_top : std_logic_vector(7 downto 0);

-- Clock period definitions

constant CLK_50MHz_period : time := 20 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: TopModule PORT MAP (
CLK_50MHz => CLK_50MHz,
INT => INT,
CE_b_top=>CE_b_top,
WE_b_top => WE_b_top,
OE_b_top => OE_b_top,
A_top => A_top,
DQ_top => DQ_top
);

-- Clock process definitions

CLK_50MHz_process :process
begin
CLK_50MHz <= '0';
wait for CLK_50MHz_period/2;
CLK_50MHz <= '1';
wait for CLK_50MHz_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 1 ns;

wait for CLK_50MHz_period*10;

-- insert stimulus here

wait;
end process;

stim_proc1: process
begin
-- hold reset state for 100 ns.
--wait for 250 ns;
--OE_b_top <= '1';
--DQ_top <= "ZZZZZZZZ";
--Selector_top <= "00";
--wait for 50 ns;
CE_b_top <= '0';
WE_b_top <= '0';
A_top <= "00000000";
DQ_top <= X"0F";
wait for 50 ns;
WE_b_top <= '1';
CE_b_top <= '1';
DQ_top <= "ZZZZZZZZ";
wait for 50 ns;
--Selector_top <= "01";
CE_b_top <= '0';
WE_b_top <= '0';
A_top <= "00000001";
DQ_top <= X"F0";
wait for 50 ns;
WE_b_top <= '1';
CE_b_top<= '1';
DQ_top <= "ZZZZZZZZ";
 DQ_top <= X"F0";
wait for 50 ns;
WE_b_top <= '1';
CE_b_top<= '1';
DQ_top <= "ZZZZZZZZ";
wait for 50 ns;
--Selector_top <= "10";
CE_b_top <= '0';
WE_b_top <= '0';
A_top <= "00000010";
DQ_top <= X"FF";
wait for 50 ns;
WE_b_top <= '1';
CE_b_top <= '1';
DQ_top <= "ZZZZZZZZ";
wait for 50 ns;
--Selector_top <= "11";
CE_b_top <= '0';
WE_b_top <= '0';
A_top <= "00000011";
DQ_top <= X"00";
wait for 50 ns;
WE_b_top <= '1';
CE_b_top <= '1';
DQ_top <= "ZZZZZZZZ";
wait for 500 ns;
--Selector_top <= "00";
CE_b_top <= '0';
OE_b_top <= '0';
A_top <= "00000000";
--DQ_top <= "ZZZZZZZZ";
wait for 50 ns;
OE_b_top <= '1';
CE_b_top <= '1';
wait for 50 ns;
--Selector_top <= "01";
CE_b_top <= '0';
OE_b_top <= '0';
A_top <= "00000001";
wait for 50 ns;
OE_b_top <= '1';
CE_b_top <= '1';
wait for 50 ns;
--Selector_top <= "10";
CE_b_top <= '0';
OE_b_top <= '0';
A_top <= "00000010";
wait for 50 ns;
OE_b_top <= '1';
CE_b_top <= '1';
wait for 50 ns;
--Selector_top <= "10";
CE_b_top <= '0';
OE_b_top <= '0';
A_top <= "00000011";
wait for 50 ns;
OE_b_top <= '1';
CE_b_top <= '1';
Simulación:
wait;
end process;
END;
 I LUSTRACIÓN 1 E SCRITURA SOLO DE UNA MEMORIA

ILUSTRACIÓN 2 ESCRITURA DE UNA MEMORIA

En las ilustraciones 1 y 2 se observa que la escritura en la memoria lo realiza de forma
correcta el problema radica en el momento de la lectura de la memoria ya que en la salida
DQ nos aparece “ZZZZZZZZ” y no obtenemos ningún resultado de la escritura como se
observa en la ilustración 3.
 I LUSTRACIÓN 3 LECTURA DE LA MEMORIA

Preparatorio- Corregido

Código Testbench:

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:27:30 08/31/2020
-- Design Name:
-- Module Name: C:/Users/jona0/Desktop/Primera Parte/picoblaze_2020/TEST1M.vhd
-- Project Name: PicoBlaze_ExtMemory
-- Target Device:
-- Tool versions:
-- Description:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.numeric_std.ALL;

ENTITY TEST1M IS
END TEST1M;

ARCHITECTURE behavior OF TEST1M IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT TopModule
PORT(
CLK_50MHz : IN std_logic;
INT : IN std_logic;
CE_b_top: IN std_logic;
WE_b_top : IN std_logic;
OE_b_top : IN std_logic;
 A_top : IN std_logic_vector(7 downto 0);
DQ_top : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK_50MHz : std_logic := '0';
signal INT : std_logic := '0';
signal CE_b_top : std_logic := '0';
signal WE_b_top : std_logic := '0';
signal OE_b_top : std_logic := '1';
signal A_top : std_logic_vector(7 downto 0) := (others => '0');

--BiDirs
signal DQ_top : std_logic_vector(7 downto 0);

-- Clock period definitions

constant CLK_50MHz_period : time := 20 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: TopModule PORT MAP (
CLK_50MHz => CLK_50MHz,
INT => INT,
CE_b_top=>CE_b_top,
WE_b_top => WE_b_top,
OE_b_top => OE_b_top,
A_top => A_top,
DQ_top => DQ_top
);

-- Clock process definitions

CLK_50MHz_process :process
begin
CLK_50MHz <= '0';
wait for CLK_50MHz_period/2;
CLK_50MHz <= '1';
wait for CLK_50MHz_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 20 ns;

wait for CLK_50MHz_period*10;

-- insert stimulus here

wait;
end process;

stim_proc1: process
begin
-- hold reset state for 100 ns.
wait for 250 ns;
 OE_b_top <= '1';
DQ_top <= "ZZZZZZZZ";
--Selector_top <= "00";
wait for 50 ns;
CE_b_top <= '0';
WE_b_top <= '0';
A_top <= "00000000";
DQ_top <= X"0F";
wait for 50 ns;
WE_b_top <= '1';
CE_b_top <= '1';
DQ_top <= "ZZZZZZZZ";
wait for 50 ns;
--Selector_top <= "01";
CE_b_top <= '0';
WE_b_top <= '0';
A_top <= "00000001";
DQ_top <= X"F0";
wait for 50 ns;
WE_b_top <= '1';
CE_b_top<= '1';
DQ_top <= "ZZZZZZZZ";
wait for 50 ns;
--Selector_top <= "10";
CE_b_top <= '0';
WE_b_top <= '0';
A_top <= "00000010";
DQ_top <= X"FF";
wait for 50 ns;
WE_b_top <= '1';
CE_b_top <= '1';
DQ_top <= "ZZZZZZZZ";
wait for 50 ns;
--Selector_top <= "11";
CE_b_top <= '0';
WE_b_top <= '0';
A_top <= "00000011";
DQ_top <= X"00";
wait for 50 ns;
WE_b_top <= '1';
CE_b_top <= '0';
OE_b_top <= '0';
--DQ_top <= "ZZZZZZZZ";
wait for 250 ns;
--Selector_top <= "00";
CE_b_top <= '0';
OE_b_top <= '0';
A_top <= "00000000";
DQ_top <= "ZZZZZZZZ";
wait for 50 ns;
OE_b_top <= '1';
CE_b_top <= '1';
wait for 50 ns;
--Selector_top <= "01";
CE_b_top <= '0';
OE_b_top <= '0';
A_top <= "00000001";
wait for 50 ns;
OE_b_top <= '1';
 CE_b_top <= '1';
wait for 50 ns;
--Selector_top <= "10";
CE_b_top <= '0';
OE_b_top <= '0';
A_top <= "00000010";
wait for 50 ns;
OE_b_top <= '1';
CE_b_top <= '1';
wait for 50 ns;
--Selector_top <= "10";
CE_b_top <= '0';
OE_b_top <= '0';
A_top <= "00000011";
wait for 50 ns;
OE_b_top <= '1';
CE_b_top <= '1';
wait;
end process;
END;

El codigo top module que se realizó en la primera parte es el mismo en este caso ya que el
problema que se tenía en la lectura de la memoria era únicamente los tiempos de lectura y
escritura que se realizó en el testbench por lo cual se corrigió los tiempos y se obtuvo los
resultados correctos como lo podemos visualizar en las siguientes ilustraciones que
representan las simulaciones del trabajo.
Simulaciones:

I LUSTRACIÓN 4 E SCRITURA EN LA MEMORIA

I LUSTRACIÓN 5 LECTURA EN LA MEMORIA

Como podemos observar en la ilustración 4 la escritura se realiza cuando el write y el chip-

enable están en bajo se escribirá en la memoria, si el write, chip-select, read están en alto la
memoria no realizará ninguna actividad ya que solo se puede escribir y leer cuando las
entradas están en bajo.
Mientras que en la ilustración 5 se observa la lectura de la memoria de forma correcta
mostrando los cuatro datos que se guardó en la memoria en diferente dirección de memoria
y después de mostrar los datos en la lectura la salida tendrá el valor de ZZZZZZZZ

Adjunto a estas ilustraciones podemos observar cómo se guardó los datos en la memoria
mediante la ilustración 6.

I LUSTRACIÓN 6 MEMORIA
3.4. Diagrama timming

I LUSTRACIÓN 7 D IAGRAMA TIMMING

4. Conclusiones.
 En el diagrama de tiempo verificó que se demora 5 periodos de reloj para poder
escribir por lo que se tomó en cuenta eso para realizar el testbench.
  En base a la simulación se concluye que los datos ingresados se pueden visualizar
en el diagrama de registro de la memoria.
5. Recomendaciones.
 Es muy importante verificar los tiempos en los que funciona el picoblaze porque
esto puede causar problemas en la simulación.
6. Bibliografía.
 Muñoz, D. (2015). Picoblaze parte2. Recuperado 2020, de
https://www.youtube.com/watch?v=G4w2BqStTaQ&t=423s
 Chapman, K. (2003). KCPSM3 Manual. En KCPSM3 Manual (Vol. Rev7, pp.
1-75). Recuperado de:
https://www.xilinx.com/support/documentation/ip_documentation/ug129.pdf