Low Power Design of A Full Adder Standard Cell

lianping Hu and lun Wang

Faculty of Information Science and Technology
Ningbo University
Ningbo City, China
[email protected]

Abstract-In this paper, a low-power full adder standard cell is structure, it is expected that the proposed full adder standard
introduced in SMIC 130nm CMOS libraries. The full adder cell has lower power than the SMIC 130nm one with the 32
standard cell is optimized to achieve low energy delay product transistors.
(EDP). All circuits are simulated with HSPICE at a SMIC
130nm CMOS technology by a 1.2V supply voltage. The layout, HSPICE simulations have been carried out for the two full
abstract design and standard-cell characters of the low-power adder cells. All circuits are simulated at a SMIC 130nm
full adder are also described. technology by supply voltages 1.2V. In order to simulate the
work environment of full adder cells, the testing platforms are
shown in Fig. 3. The power dissipations of the circuits in the
I. INTRODUCTION
box are tested. In order to assure the fairness of the
Low energy, high speed and small area are three main comparison, the two inverters are paralleled after all outputs to
objectives in IC design. Taday's advanced designs require a act as load capacitances, and the same input is given to these
careful balancing among many competing challenges [ I ]. circuits.
Timing delay remains critical but power and area also are
important for IC designs. Energy consumption in CMOS IC
circuits has two components: dynamic and static energy
dissipations [2, 3]. The dynamic energy dissipation includes A Ab
-1
switching energy due to charging and discharging of load

i
capacitances, and short energy due to a direct-path from AEElB
supply voltage to the ground. The short energy dissipation can
B A0B B
usually be ignored. Static energy dissipation is caused by
leakage currents of MOS devices. Ab A
--,- ---,­
EDP (Energy Delay Product) metric provides a good Bb
compromise between speed and delay, which is written as
Bb
AEEl B
�
EDP = Extdelay' (I) Clb Bb
A full adder is important element in digital circuits [4, 5].
Commercial standard cells are mostly based on standard
s A0B f co

CMOS logic. In this work, a low-power full adder standard

cell is optimized to achieve low EDP. All circuits are Clb
simulated with HSPICE at SMIC130nm CMOS technology.
The layout, abstract design, and standard-cell characters of the
low-power full adder are also described.
Ain �
�A
II. Low POWER FULL ADDER FOR STANDARD CELL

The full adder of the SMIC (Semiconductor

Bin��B
Manufacturing International Corporation) 130nm standard-cell
library uses a TG logic structure with 32 transistors, as shown
Cin �
� CI
in Fig. I. The proposed full adder with 26 transistors for
standard cell is shown in Fig. 2. Because of its simple Figure I. Full adder standard cell in SMIC 130nm CMOS process.

978-1-61284-857-0/11/$26.00 <92011 IEEE

 Ab Bb III. LAYOUT DE SI GN AND POST-LA YOUT SIMULAnONS

The layout of the proposed full adder cell is shown in Fig.

4. The metal lines are placed horizontally at the top and the
bottom for the power supply (Voo) and ground (Vss). The
s layout areas of the two cells are 10.58,.unx3.69J.lm. The two
...--+- H A EBB
=
cells have the same height and length.

The energy delay product of the two full adders is shown

in Table 2 by using post-layout simulations. The proposed full
adder cell has an energy reduction of 12.24%.

The leakage power is shown in Table 3. The leakage of the

proposed full adder cell is lower than SMIC. The average
leakage power consumption achieves a reduction of 33.45%.

Fig. 5 shows the energy consumption per switching from

10MHz to 300MHz. The proposed full adder cell performs
co
lower energy consumption except for low frequencies.

L...-__ Hb = A0B

A in ---[:>0---- A b Bin ---{:>o-- Bb

Cin �
� CI
Figure 4. The layouts of the proposed full adder cell for SMIC I30nm.

Figure 2. The proposed full adder standard cell for SMI C I300m CMOS
process. TABLE II. EDP COMPARISONS OF THE Two FULL ADOER STANOARD-
CELLS UUSING POST-LAYOUT SIMULATIONS.
The energy dissipation and delay of the two full adder cells Energy loss per Propagation EDP
are shown in Table 1. The results show that the proposed full Cells
switchin2 (fJ) delay(ps) (pJs)
adder cell has lower energy consumption and EDP than the SMI C 33.7 183.14 6.17
SMIC one. Compared with the SMIC standard cell, the The proposed 29.6 203.12 6.12

proposed full adder cell has 16.8% energy saves and provides
an EDP reduction of 11.6%, thought its delay is slightly larger TABLE III. LEAKAGE POWER OF THE Two FuLL ADOER CELLS USING
POST-LAYOUT SIMULATIONS (pW).
than the SMIC one
avera
1---------' ABC 000 001 010 011 100 101 110 111
0.64/0.42 ge
0.64/0.42 1 1 SMI C 1704 2196 2048 1896 1653 2055 2055 1835 1912
Ain 1
The
»o-...J.--I
... 836 1206 1530 1248 1214 1474 1474 1219 1272
I propose
Bin Full
)0--+-"'::";';-1
; Adder
60',-------,
Cin --&- SMIC ___ The proposed
50
1 1 S
Of)
_________ ....J
:E
B
40
Figure 3. Test bench of Full Adder cells. .�
� 30
g,

TABLE I. EDP COMPARISONS OF THE Two FuLL ADOER CELLS.

] 20
�
Energy consumption Propagation EDP � 10
Cells L.Ll
per switching (fJ) delay (ps) (pJs)
o L-���----+---�--�
SMIC full 50 100 150 200 250 300 500
28 150.84 4.22
adder
Operation frequency (MHz)
The proposed
23.8 156.75 3.73
full adder Figure 5. Energy consumption comparisons of the two full adder cells.
 IV. ST ANDARD CELL DESIGNS MACRO ADDFHXI_R PIN CO
CLASS CORE; DIRECTION OUTPUT;
The standard-cell design flow is shown in Fig. 6. We use FOREIGN ADD4 0 0;
the stream out function of IC5141 to generate the GDS ORIGIN 0.0000 0.0000; END
database. Then, this database is used to create the auto place SIZE 10.5800BY 3.6900; END CO
and route (P&R) library. Caliber is used to verify layouts and SYMMETRYX Y; PIN S
generate spice netlists. The synthesis library is generated by SITE SMCI3SITE; DIRECTION OUTPUT;
PIN A
using the liberty NCX and HSPICE.
DIRECTION INPUT;
END
After the layout design, the abstract should be created in PORT
END S
library Exchange Format (LEF) for standard cells. An abstract LAYER METAL I ;
PINVDD
RECT 0.1490 1.5120 0.5890
is a high-level representation of a layout or AutoLayout view. DIRECTION INOUT;
2.0470;
The generated abstracts are based on physical layout, logical USE POWER;
END
data, and process technology information, as shown in Fig. 7.
END A
END
It is used in place of full layouts to improve the performance PINB
ENDVDD
of place-and-route tools, such as Cadence Encounter [6]. DIRECTION INPUT;
PINVSS

The final LEF (Library Exchange Format) tech file for the DIRECTION INOUT;
ENDB
USE GROUND;
full adder standard-cell is show in Fig. 8. From the LEF file, PIN CI
we can see that all the Pins are abstracted, and the size is DIRECTION INPUT;
END
10.58,llnx3.69Ilm definition in the LEF file. The place-and­ ENDVSS
route tools can read this file easily. END CI
END ADDFHXI_R

--- ' Figure 8. LEF tech file of the proposed full adder standard cell.
I'
'
- I
- \
f
....... -
'
\
\ Calibre ) To perform characterization, Liberty NCX is used to run
/ \ I
( Virtuoso II " / circuit simulations for the library cells to determine the cell
\
"- /
// '--- behavior. It writes out a description of the cell characteristics
in Liberty format (.lib). The library can then be used for
timing, power, and noise analysis with various tools such as
DesignCompile and PrimeTime. In addition, Liberty NCX can
convert existing libraries from one format to another [7, 8].

For a characterization task, the template file must specify

the SPICE model file name, the SPICE netlist directory, and
the SPICE simulator executable, as shown in Fig. 9. The input
/
)---- ...... , and output library names should also be specified.
/ "-
/ \
Verification
( Liberty NCX& \ After the characterization, we can get a library in liberty
\ HSPICE f format (.lib) that can be used for timing, power analysis with
\ / various tools such as PrimeTime. We can use the Library
'..... ..../
.
Standard-cell library .... _---
Compile tool from Synopsys captures for this liberty file (.lib)
and translates them into Synopsys internal database format
(.db) for synthesis.
Figure 6. The standard cell design flow.

set input_library ..Itypical_1 v2c25.lib

set output_library typical_I v2c25_out.lib
set model_file ..Imodel.typ
set netlist_dir ..Inetlists
set simulator_exec -/hspice/linuxlhspice
set templates true
set output_templates true
set input_template_dir config
set timing true
set power true
set ccs -power false
set compact false
set ccs_timing false
set nlpm true
X Cell Origin _ Vertical Grid D PR Boundary
set nldm true
I:I:1II Horizontal Grid ./ Pin location set variation_leakage ture

Figure 7. Abstract view of the proposed full adder standard cell. Figure 9. Template files of the liberty NCX.
 In order to estimate power information, the 2-bit multiplier
is verified by using PrimeTime. The structure of the 2-bit Eile !Cdi: yjew Ienninal Ta!!s tlelp
multiplier is show in Fig. 10. Fig. 11 (a) and Fig. 11 (b) show
the synthesis results by using DesignCompile with the SMIC
1
full adder (ADDFHXl_SMICI3) and the proposed one pCshell> reporCpower
(ADDFHXl_R), respectively.
Report : Averaged Power

We can use the Report_Power command of PrimeTime to Design : mux2

Version: 0-2010.06-SP3-4
estimate power information, as shown in Fig.l2 and Fig. 13. Date : Wed May 11 03: 21: 22 2011
.. ****** ,.*'. ****** .. *****. **** .. * .. * .. ********

combinational 1. 292e-05 9.400e-07 3.020e-09 1.387e-05 (100.00%)

5, 5, 51 So
At A" sequential 0.0000 0.0000 0.0000 0.0000 ( 0.00%)

X Bl 50
Net Switching Power = 9.400e-07 ( 6.78%)
Al50 A"B, Cell Internal Power = 1. 292e-05 (93.20%)
A1Bl A"Bl Cell Leakage Power = 3.020e-09 ( 0.02%)
ell 0
= 1.387e-05 (100.00%)
5, 5, 51 5,
Figure 13. Power analysis of the synthesis results for the proposed full adder
cell (ADDFHXI_R) using PrimeTime.

Fig. 12 shows the power analysis of the 2-bit multiplier

using SMIC full adder cell, while Fig. 13 shows the power
analysis of the 2-bit multiplier using proposed full adder cell.
As shown in Fig. 12 and Fig. 13, the leakage power and the
total power provide reductions of 32.67% and 3.4%,
respectively.

V. CONCLUSIONS

In this paper, a low power full adder standard cell is

proposed. The full adder standard cell is optimized to achieve
Figure I O. The structrue and schematic of the 2-bit multiplier. low energy delay product (EDP). The standard-cell layout,
abstract design and standard-cell characters are also described.
Cdl R�ft:!L·t:!lll:t:! LlUl.'i:lL'Y The synthesis result indicates the proposed full adder standard
Ul ADDFHXLR typical_lv2c25 39.04
cell is a good choose in low power design.
Ul AUutHXl.J{ typ i c al_lvl a� :JY.U4
U3 AND21C1 typ ic aLlv2c 25 6.79
U4 AND21C1 typical lv2c25 6.79 ACKNOWLEDGMENT
US AND2lCl typica1_1v2c25 6.79
U6 AND2lCi typical_lv2c25 6.79 Project is supported by National Natural Science
Total ( cells (a) lU� . l 4 Foundation of China (No. 61071049), Zhejiang Science and
Cell Reference Library Area Technology Project of China (No. 201OC31116), Scientific
Ul ADDFIIXLSMIC13 typ ica Llv 2c 25 39 .04 Research Fund of Zhejiang Provincial Education Department
U2 ADDFIIXI SMIC13 typical lv2c25 39.04 (No. Z200908632), and Ningbo Natural Science Foundation
U3 AND2Xl typical_lv2c25 6.79
U4 AND2Kl typicaLlv2c25 6.79 (No. 2009A610066).
US AND2Kl Ln,lc.Llv2c25 6.79
Ub ANVlXl typicaLlvla� b.fY

Total 7 cells (1)) 105.24

Figure I I. DesignCompile synthesis results of the 2-bit multiplier using the REFERENCES
SMIC and proposed full adder cells. [ I] Jan M. Rabaey, Digital integrated circuits: a design perspective,
Prentice-Hall, Inc., Upper Saddle River, NJ, 1996.
[2] A. Wang, B. H. Calhoun, and A. P. Chandrakasan., "Sub-threshold
Report : Averaged Power
Design for Ultra Low-Power Systems", Springer, pp. 12-102, 2006.
Design : muxLsmic13
Version: 0-2010. 06-SP3-4 [3] R. Gonzalez, et aI., "Supply and Threshold Voltage Scaling for Low
Date : Wed May 11 03: 43: 53 2011 Power CMOS," JSSC, vol 32 (8), pp. 1210-1216, 1997.
.. * .. *** ** ************** ** ***it* ** *********
[4] M. Stan, "Optimal Voltages and Sizing for Low Power," Intl.Conf. on
combinational 1.301e-05 1.345e-06 4.486e-09 1. 436e-05 (100.00%)
sequential 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
VLSI Design, pp. 428-433, 1999.
[5] N. Zhuang, H. Wu, "A New Design of the CMOS Full Adder", IEEE J.
Net Switching Power = 1.345e-06 ( 9.36%) Solid-State Circuits, Vol. 27, No. 5, pp. 840-844, 1992.
Cell Internal Power = 1.301e-05 (90.60%)
Cell Leakage Power = 4.486e-09 ( 0.03%) [6] Cadence Abstract Generator User Guide, Product Version 5.1.41, July
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Total Power 1. 436e-05 (100.00%) LibertyTM NCX User Guide Version B-2008.12, December 2008.
=
[7]
Figure 12. Power analysis of the synthesis results for SMIC full adder cell [8] Synopsys libertyTM User Guide, Volume I Version 2003.12,
(ADDFHX I_SMIC I3) using PrimeTime. December 2003.