25AA320/25LC320/25C320: 32K Spi Bus Serial EEPROM
25AA320/25LC320/25C320: 32K Spi Bus Serial EEPROM
25AA320/25LC320/25C320: 32K Spi Bus Serial EEPROM
Package Types
PDIP, SOIC TSSOP TSSOP
CS 1 8 VCC CS 1 14 VCC
HOLD 1 8 SCK SO 2 13 HOLD
25XX320
25XX320
25XX320
SO 2 7 HOLD VCC 2 7 SI NC 3 12 NC
NC 4 11 NC
WP 3 6 SCK CS 3 6 VSS 5 10
NC NC
4 5 WP 6 9 SCK
VSS 4 5 SI SO WP
VSS 7 8 SI
*25XX320 is used in this document as a generic part number for the 25AA320/25LC320/25C320 devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
SCK
18 19
High-impedance
SO n+2 n+1 n n n-1
5
don’t care
SI n+2 n+1 n n n-1
HOLD
CS 12
2 11
7
Mode 1,1 8 3
5 6
SI MSB in LSB in
High-impedance
SO
CS
9 10 3
Mode 1,1
SCK Mode 0,0
13
14 15
don’t care
SI
8-pin 14-lead
Name PDIP SOIC Description
TSSOP TSSOP
2.1 Chip Select (CS) The WP pin function is blocked when the WPEN bit in
the Status register is low. This allows the user to install
A low level on this pin selects the device. A high level the 25XX320 in a system with WP pin grounded and
deselects the device and forces it into Standby mode. still be able to write to the Status register. The WP pin
However, a programming cycle which is already functions will be enabled when the WPEN bit is set
initiated or in progress will be completed, regardless of high.
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as 2.4 Serial Input (SI)
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance The SI pin is used to transfer data into the device. It
state, allowing multiple parts to share the same SPI receives instructions, addresses, and data. Data is
bus. A low-to-high transition on CS after a valid write latched on the rising edge of the serial clock.
sequence initiates an internal write cycle. After power-
2.5 Serial Clock (SCK)
up, a low level on CS is required prior to any sequence
being initiated. The SCK is used to synchronize the communication
between a master and the 25XX320. Instructions,
2.2 Serial Output (SO) addresses, or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
The SO pin is used to transfer data out of the 25XX320.
pin is updated after the falling edge of the clock input.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock. 2.6 Hold (HOLD)
2.3 Write-Protect (WP) The HOLD pin is used to suspend transmission to the
25XX320 while in the middle of a serial sequence with-
This pin is used in conjunction with the WPEN bit in the out having to re-transmit the entire sequence again. It
Status register to prohibit writes to the nonvolatile bits must be held high any time this function is not being
in the Status register. When WP is low and WPEN is used. Once the device is selected and a serial
high, writing to the nonvolatile bits in the Status register sequence is underway, the HOLD pin may be pulled
is disabled. All other operations function normally. low to pause further serial communication without
When WP is high, all functions, including writes to the resetting the serial sequence. The HOLD pin must be
nonvolatile bits in the Status register operate normally. brought low while SCK is low, otherwise the HOLD
If the WPEN bit is set, WP low during a Status register function will not be invoked until the next SCK high-to-
write sequence will disable writing to the Status low transition. The 25XX320 must remain selected dur-
register. If an internal write cycle has already begun, ing this sequence. The SI, SCK, and SO pins are in a
WP going low will have no effect on the write. high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
data out
High-impedance
SO 7 6 5 4 3 2 1 0
CS
Twc
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
instruction 16-bit address data byte
SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0
High-impedance
SO
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
instruction 16-bit address data byte 1
SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
data byte 2 data byte 3 data byte n (32 max)
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
CS
0 1 2 3 4 5 6 7
SCK
SI 0 0 0 0 0 1 1 0
High-impedance
SO
CS
0 1 2 3 4 5 6 7
SCK
SI 0 0 0 0 0 1 10 0
High-impedance
SO
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
instruction
SI 0 0 0 0 0 1 0 1
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0
High-impedance
SO
XXXXXXXX 25LC320
XXXXXNNN /PNNN
YYWW YYWW
XXXXXXXX 25LC320
XXXXYYWW I/SNYYWW
NNN NNN
XXXX 5LBX
XYWW IYWW
NNN NNN
XXXXXXXX 25L32
YYWW YYWW
NNN NNN
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard marking consists of Microchip part number, year code, week code, and traceability code. For
device markings beyond this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
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