X20 system

User's Manual

Version: 3.10 (May 2015)

Model no.: MAX20-ENG

All information contained in this manual is current as of its creation/publication. B&R reserves the right to change
the contents of this manual without notice. The information contained herein is believed to be accurate as of
the date of publication; however, Bernecker + Rainer Industrie-Elektronik Ges.m.b.H. makes no warranty, ex-
pressed or implied, with regard to the products or documentation contained within this manual. In addition,
Bernecker + Rainer Industrie-Elektronik Ges.m.b.H. shall not be liable for any incidental or consequential damages
in connection with or arising from the furnishing, performance or use of the product(s) in this documentation. Soft-
ware names, hardware names and trademarks are registered by their respective companies.
 Table of contents

1 General information................................................................................................ 50
1.1 Manual history...............................................................................................................................................50
1.2 Safety notices................................................................................................................................................52
1.2.1 Introduction.............................................................................................................................................. 52
1.2.2 Intended use............................................................................................................................................52
1.2.3 Protection against electrostatic discharge...............................................................................................53
1.2.3.1 Packaging...........................................................................................................................................53
1.2.3.2 Guidelines for proper ESD handling..................................................................................................53
1.2.4 Transport and storage............................................................................................................................. 54
1.2.5 Installation................................................................................................................................................54
1.2.5.1 Inserting and removing I/O modules while the controller is running..................................................54
1.2.6 Operation................................................................................................................................................. 55
1.2.6.1 Protection against touching electrical parts....................................................................................... 55
1.2.7 Environmentally friendly disposal............................................................................................................ 55
1.2.7.1 Separation of materials...................................................................................................................... 55
1.2.8 Organization of safety notices.................................................................................................................55
1.3 Terminology...................................................................................................................................................56

2 System features...................................................................................................... 57
2.1 Setting the standards in automation.............................................................................................................57
2.1.1 More than just I/O................................................................................................................................... 57
2.1.2 3 x 1 = 1..................................................................................................................................................58
2.2 Optimized design.......................................................................................................................................... 59
2.3 Remote backplane........................................................................................................................................ 60
2.4 X20 CPUs..................................................................................................................................................... 61
2.4.1 General information................................................................................................................................. 61
2.4.2 Remote backplane...................................................................................................................................61
2.4.3 B&R Automation Studio...........................................................................................................................62
2.4.4 PC-based technology.............................................................................................................................. 62
2.4.5 Suitable for industrial use........................................................................................................................62
2.5 X20 Compact CPUs......................................................................................................................................63
2.5.1 General information................................................................................................................................. 63
2.5.2 Product range.......................................................................................................................................... 63
2.6 X20 Fieldbus CPUs...................................................................................................................................... 64
2.6.1 General information................................................................................................................................. 64
2.6.2 Product range.......................................................................................................................................... 64
2.6.3 Programming........................................................................................................................................... 64
2.7 For all fieldbuses, integration through standardization................................................................................. 65
2.8 Complete system.......................................................................................................................................... 66
2.8.1 IP67 - then X67....................................................................................................................................... 66
2.8.2 Integrated valve terminal control............................................................................................................. 66
2.9 Easy wiring....................................................................................................................................................67
2.9.1 Install the wires, plug it in, and it's ready to go...................................................................................... 67
2.10 Sophisticated mechanics............................................................................................................................ 68
2.11 Diagnostics.................................................................................................................................................. 69
2.11.1 re LEDs.................................................................................................................................................. 70
2.12 Embedded parameter chip..........................................................................................................................71
2.13 Space for options........................................................................................................................................71
2.14 Flexibility for options................................................................................................................................... 71
2.15 Configurable X2X Link address.................................................................................................................. 72
2.16 Universal 1, 2, 3-wire connections............................................................................................................. 73
2.17 Coated X20 system.................................................................................................................................... 74
2.18 Redundancy................................................................................................................................................ 74
2.19 reACTION technology................................................................................................................................. 74
2.20 X20 system configuration........................................................................................................................... 75
2.20.1 Fieldbus connection...............................................................................................................................76
2.20.2 Connection to X2X Link backplane....................................................................................................... 77

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3 Mechanical and electrical configuration...............................................................78

3.1 Dimensions....................................................................................................................................................78
3.1.1 X20 CPUs with one slot for interface modules....................................................................................... 78
3.1.2 X20 CPUs with three slots for interface modules................................................................................... 78
3.1.3 Compact CPUs and bus controllers........................................................................................................79
3.1.4 Fieldbus CPUs and expandable bus controller.......................................................................................79
3.1.4.1 With an additional slot....................................................................................................................... 79
3.1.4.2 With two additional slots.................................................................................................................... 79
3.1.5 I/O modules............................................................................................................................................. 80
3.1.6 CAD support............................................................................................................................................ 80
3.2 Design support.............................................................................................................................................. 81
3.2.1 Macros for ECAD systems...................................................................................................................... 81
3.2.2 Printing support....................................................................................................................................... 81
3.3 Installation..................................................................................................................................................... 82
3.3.1 Horizontal installation...............................................................................................................................82
3.3.2 Vertical installation...................................................................................................................................83
3.4 Wiring............................................................................................................................................................ 84
3.5 Stress relief using cable ties........................................................................................................................ 84
3.6 Shielding........................................................................................................................................................85
3.6.1 Direct shielding connection..................................................................................................................... 85
3.6.2 X20 cable shield clamp........................................................................................................................... 86
3.6.3 X20 shielding bracket.............................................................................................................................. 87
3.6.4 Shielding via top-hat rail or bus bar........................................................................................................88
3.7 Wiring guidelines for X20 modules with an Ethernet cable..........................................................................89
3.8 The supply concept.......................................................................................................................................90
3.8.1 Bus module rack replacement.................................................................................................................90
3.9 X20 system infrastructure............................................................................................................................. 91
3.10 Bus supply...................................................................................................................................................91
3.11 Potential groups.......................................................................................................................................... 91
3.12 Output modules with supply....................................................................................................................... 92
3.13 Bus receiver with supply.............................................................................................................................92
3.14 Supply module for internal I/O supply........................................................................................................ 92
3.15 Power supply module for internal I/O supply and bus supply.................................................................... 92
3.16 Bus transmitter with supply.........................................................................................................................92
3.17 Internal I/O supply failure (ModuleOk)........................................................................................................92
3.18 X20 system power supply...........................................................................................................................92
3.19 X20 system protection................................................................................................................................ 93
3.19.1 Potential groups.....................................................................................................................................93
3.19.2 Supply via bus transmitter.....................................................................................................................93
3.20 X2X Link supply.......................................................................................................................................... 94
3.20.1 Extended and redundant X2X Link supply............................................................................................94
3.20.2 Example for extended X2X Link supply................................................................................................ 94
3.20.3 Example for redundant X2X Link supply...............................................................................................95
3.21 Safe cutoff................................................................................................................................................... 96
3.21.1 General information............................................................................................................................... 96
3.21.2 Scope of application / Standards referenced........................................................................................96
3.21.3 Intended use..........................................................................................................................................96
3.21.4 Qualified personnel................................................................................................................................96
3.21.5 Application in the X20 system...............................................................................................................97
3.21.5.1 Suitable modules..............................................................................................................................97
3.21.6 General notices..................................................................................................................................... 98
3.21.6.1 Installation notes.............................................................................................................................. 98
3.21.6.2 Timing...............................................................................................................................................98
3.21.6.3 Potential group structure..................................................................................................................99
3.21.6.4 Circuit examples...............................................................................................................................99
3.21.6.5 Wiring notices.................................................................................................................................101
3.21.7 Safety guidelines................................................................................................................................. 102

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3.22 Combining X2X Link systems...................................................................................................................103

3.22.1 General information............................................................................................................................. 103
3.22.2 Connection overviews..........................................................................................................................103
3.22.2.1 Combining X20, X67 and compact I/O system............................................................................. 103
3.22.2.2 Combining X20, X67 and valve terminal connections................................................................... 103
3.22.3 Connection examples.......................................................................................................................... 104
3.22.3.1 X20 system.................................................................................................................................... 104
3.22.3.2 Compact I/O system...................................................................................................................... 104
3.22.3.3 Valve connection............................................................................................................................ 105
3.23 Calculating the power requirements......................................................................................................... 106
3.23.1 Example 1............................................................................................................................................107
3.23.2 Example 2............................................................................................................................................107
3.24 Power supply module power loss.............................................................................................................110
3.24.1 General information............................................................................................................................. 110
3.24.2 Power supply modules without X2X Link supply................................................................................ 111
3.24.3 Power supply module with X2X Link supply....................................................................................... 111
3.24.4 Power supply module for X20 standalone devices............................................................................. 111
3.24.5 Potential distribution modules............................................................................................................. 111
3.24.6 Example............................................................................................................................................... 112
3.24.6.1 Calculating the internal X2X Link power consumption of the X20BR9300.................................... 112
3.24.6.2 Calculating the internal I/O power consumption of the X20BR9300..............................................113
3.24.6.3 Total internal power consumption of the X20BR9300................................................................... 115

4 X20 system modules............................................................................................ 116

4.1 Module overview: Alphabetically.................................................................................................................116
4.2 Module overview: Grouped......................................................................................................................... 121
4.3 Analog input modules................................................................................................................................. 128
4.3.1 Brief information.................................................................................................................................... 128
4.3.2 X20AI1744, X20AI1744-3...................................................................................................................... 129
4.3.2.1 General Information......................................................................................................................... 129
4.3.2.2 Order data........................................................................................................................................ 129
4.3.2.3 Technical data..................................................................................................................................129
4.3.2.4 Status LEDs..................................................................................................................................... 131
4.3.2.5 Pinout............................................................................................................................................... 131
4.3.2.6 Connection examples.......................................................................................................................132
4.3.2.7 Input circuit diagram........................................................................................................................ 133
4.3.2.8 Filter characteristics of the Sigma-Delta ADC................................................................................. 134
4.3.2.9 Effective resolution of the AD converter.......................................................................................... 134
4.3.2.10 Calculation example / Quantization............................................................................................... 135
4.3.2.11 Register description........................................................................................................................136
4.3.3 X20AI2222............................................................................................................................................. 144
4.3.3.1 General information..........................................................................................................................144
4.3.3.2 Order data........................................................................................................................................ 144
4.3.3.3 Technical data..................................................................................................................................144
4.3.3.4 LED status indicators....................................................................................................................... 145
4.3.3.5 Pinout............................................................................................................................................... 146
4.3.3.6 Connection example........................................................................................................................ 146
4.3.3.7 Input circuit diagram........................................................................................................................ 146
4.3.3.8 Register description......................................................................................................................... 147
4.3.4 X20AI2237............................................................................................................................................. 152
4.3.4.1 General information..........................................................................................................................152
4.3.4.2 Order data........................................................................................................................................ 152
4.3.4.3 Technical data..................................................................................................................................152
4.3.4.4 Status LEDs..................................................................................................................................... 154
4.3.4.5 Pinout............................................................................................................................................... 154
4.3.4.6 Connection examples.......................................................................................................................155
4.3.4.7 Input circuit diagram........................................................................................................................ 156

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4.3.4.8 Behavior in the event of a short circuit............................................................................................156

4.3.4.9 Register description......................................................................................................................... 157
4.3.5 X20AI2322............................................................................................................................................. 167
4.3.5.1 General information..........................................................................................................................167
4.3.5.2 Order data........................................................................................................................................ 167
4.3.5.3 Technical data..................................................................................................................................167
4.3.5.4 LED status indicators....................................................................................................................... 168
4.3.5.5 Pinout............................................................................................................................................... 169
4.3.5.6 Connection example........................................................................................................................ 169
4.3.5.7 Input circuit diagram........................................................................................................................ 169
4.3.5.8 Register description......................................................................................................................... 170
4.3.6 X20AI2437............................................................................................................................................. 176
4.3.6.1 General information..........................................................................................................................176
4.3.6.2 Order data........................................................................................................................................ 176
4.3.6.3 Technical data..................................................................................................................................177
4.3.6.4 Status LEDs..................................................................................................................................... 178
4.3.6.5 Pin assignments...............................................................................................................................179
4.3.6.6 Connection examples.......................................................................................................................179
4.3.6.7 Input circuit diagram........................................................................................................................ 179
4.3.6.8 Behavior in the event of a short circuit............................................................................................179
4.3.6.9 Register description......................................................................................................................... 180
4.3.7 X20AI2438............................................................................................................................................. 193
4.3.7.1 General information..........................................................................................................................193
4.3.7.2 Order data........................................................................................................................................ 193
4.3.7.3 Technical data..................................................................................................................................194
4.3.7.4 Status LEDs..................................................................................................................................... 196
4.3.7.5 Pin assignments...............................................................................................................................196
4.3.7.6 Connection examples.......................................................................................................................197
4.3.7.7 Input circuit diagram........................................................................................................................ 197
4.3.7.8 Behavior in the event of a short circuit............................................................................................197
4.3.7.9 Register description......................................................................................................................... 198
4.3.8 X20AI2622............................................................................................................................................. 249
4.3.8.1 General information..........................................................................................................................249
4.3.8.2 Order data........................................................................................................................................ 249
4.3.8.3 Technical data..................................................................................................................................250
4.3.8.4 LED status indicators....................................................................................................................... 251
4.3.8.5 Pinout............................................................................................................................................... 252
4.3.8.6 Connection example........................................................................................................................ 252
4.3.8.7 Input circuit diagram........................................................................................................................ 252
4.3.8.8 Register description......................................................................................................................... 253
4.3.9 X20AI4222............................................................................................................................................. 259
4.3.9.1 General information..........................................................................................................................259
4.3.9.2 Order data........................................................................................................................................ 259
4.3.9.3 Technical data..................................................................................................................................259
4.3.9.4 LED status indicators....................................................................................................................... 260
4.3.9.5 Pinout............................................................................................................................................... 261
4.3.9.6 Connection example........................................................................................................................ 261
4.3.9.7 Input circuit diagram........................................................................................................................ 261
4.3.9.8 Register description......................................................................................................................... 262
4.3.10 X20AI4322........................................................................................................................................... 267
4.3.10.1 General information........................................................................................................................267
4.3.10.2 Order data...................................................................................................................................... 267
4.3.10.3 Technical data................................................................................................................................267
4.3.10.4 LED status indicators..................................................................................................................... 268
4.3.10.5 Pinout............................................................................................................................................. 269
4.3.10.6 Connection example...................................................................................................................... 269
4.3.10.7 Input circuit diagram...................................................................................................................... 269

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4.3.10.8 Register description....................................................................................................................... 270

4.3.11 X20AI4622............................................................................................................................................276
4.3.11.1 General information........................................................................................................................276
4.3.11.2 Order data...................................................................................................................................... 276
4.3.11.3 Technical data................................................................................................................................ 277
4.3.11.4 LED status indicators..................................................................................................................... 278
4.3.11.5 Pinout..............................................................................................................................................279
4.3.11.6 Connection example.......................................................................................................................279
4.3.11.7 Input circuit diagram.......................................................................................................................279
4.3.11.8 Register description........................................................................................................................280
4.3.12 X20AI8221........................................................................................................................................... 286
4.3.12.1 General information........................................................................................................................286
4.3.12.2 Order data...................................................................................................................................... 286
4.3.12.3 Technical data................................................................................................................................286
4.3.12.4 LED status indicators..................................................................................................................... 287
4.3.12.5 Pinout............................................................................................................................................. 288
4.3.12.6 Connection example...................................................................................................................... 288
4.3.12.7 Input circuit diagram...................................................................................................................... 288
4.3.12.8 Register description....................................................................................................................... 289
4.3.13 X20AI8321........................................................................................................................................... 294
4.3.13.1 General information........................................................................................................................294
4.3.13.2 Order data...................................................................................................................................... 294
4.3.13.3 Technical data................................................................................................................................294
4.3.13.4 LED status indicators..................................................................................................................... 295
4.3.13.5 Pinout............................................................................................................................................. 296
4.3.13.6 Connection example...................................................................................................................... 296
4.3.13.7 Input circuit diagram...................................................................................................................... 296
4.3.13.8 Register description....................................................................................................................... 297
4.3.14 X20AP31x1.......................................................................................................................................... 303
4.3.14.1 General information........................................................................................................................303
4.3.14.2 Order data...................................................................................................................................... 304
4.3.14.3 Technical data................................................................................................................................304
4.3.14.4 LED status indicators..................................................................................................................... 306
4.3.14.5 Pinout............................................................................................................................................. 306
4.3.14.6 Current transformer........................................................................................................................307
4.3.14.7 Voltage transformer........................................................................................................................307
4.3.14.8 Input circuit diagram...................................................................................................................... 308
4.3.14.9 Typical connection examples for different mains configurations................................................... 309
4.3.14.10 Register description..................................................................................................................... 313
4.4 Analog output modules............................................................................................................................... 389
4.4.1 Brief information.................................................................................................................................... 389
4.4.2 X20AO2437........................................................................................................................................... 390
4.4.2.1 General information..........................................................................................................................390
4.4.2.2 Order data........................................................................................................................................ 390
4.4.2.3 Technical data..................................................................................................................................390
4.4.2.4 LED status indicators....................................................................................................................... 392
4.4.2.5 Pinout............................................................................................................................................... 392
4.4.2.6 Connection example........................................................................................................................ 393
4.4.2.7 OSP hardware requirements........................................................................................................... 393
4.4.2.8 Output circuit diagram......................................................................................................................393
4.4.2.9 Derating............................................................................................................................................ 394
4.4.2.10 Register description....................................................................................................................... 395
4.4.3 X20AO2438........................................................................................................................................... 401
4.4.3.1 General information..........................................................................................................................401
4.4.3.2 Order data........................................................................................................................................ 401
4.4.3.3 Technical data..................................................................................................................................401
4.4.3.4 LED status indicators....................................................................................................................... 403

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4.4.3.5 Pinout............................................................................................................................................... 404

4.4.3.6 Connection example........................................................................................................................ 404
4.4.3.7 OSP hardware requirements........................................................................................................... 404
4.4.3.8 Output circuit diagram......................................................................................................................405
4.4.3.9 Operation..........................................................................................................................................406
4.4.3.10 Register description....................................................................................................................... 408
4.4.4 X20AO2622........................................................................................................................................... 454
4.4.4.1 General information..........................................................................................................................454
4.4.4.2 Order data........................................................................................................................................ 454
4.4.4.3 Technical data..................................................................................................................................455
4.4.4.4 LED status indicators....................................................................................................................... 456
4.4.4.5 Pinout............................................................................................................................................... 456
4.4.4.6 Connection example........................................................................................................................ 457
4.4.4.7 Output circuit diagram......................................................................................................................457
4.4.4.8 Register description......................................................................................................................... 458
4.4.5 X20AO2632........................................................................................................................................... 460
4.4.5.1 General information..........................................................................................................................460
4.4.5.2 Order data........................................................................................................................................ 460
4.4.5.3 Technical data..................................................................................................................................460
4.4.5.4 LED status indicators....................................................................................................................... 461
4.4.5.5 Pinout............................................................................................................................................... 462
4.4.5.6 Connection example........................................................................................................................ 462
4.4.5.7 Output circuit diagram......................................................................................................................462
4.4.5.8 Register description......................................................................................................................... 463
4.4.6 X20AO2632-1........................................................................................................................................ 467
4.4.6.1 General information..........................................................................................................................467
4.4.6.2 Order data........................................................................................................................................ 467
4.4.6.3 Technical data..................................................................................................................................467
4.4.6.4 LED status indicators....................................................................................................................... 468
4.4.6.5 Pinout............................................................................................................................................... 469
4.4.6.6 Connection example........................................................................................................................ 469
4.4.6.7 Output circuit diagram......................................................................................................................469
4.4.6.8 Register description......................................................................................................................... 470
4.4.7 X20AO4622........................................................................................................................................... 474
4.4.7.1 General information..........................................................................................................................474
4.4.7.2 Order data........................................................................................................................................ 474
4.4.7.3 Technical data..................................................................................................................................474
4.4.7.4 LED status indicators....................................................................................................................... 475
4.4.7.5 Pinout............................................................................................................................................... 476
4.4.7.6 Connection example........................................................................................................................ 476
4.4.7.7 Output circuit diagram......................................................................................................................476
4.4.7.8 Module operation............................................................................................................................. 477
4.4.7.9 Register description......................................................................................................................... 479
4.4.8 X20AO4632........................................................................................................................................... 481
4.4.8.1 General information..........................................................................................................................481
4.4.8.2 Order data........................................................................................................................................ 481
4.4.8.3 Technical data..................................................................................................................................481
4.4.8.4 LED status indicators....................................................................................................................... 482
4.4.8.5 Pinout............................................................................................................................................... 483
4.4.8.6 Connection example........................................................................................................................ 483
4.4.8.7 Output circuit diagram......................................................................................................................483
4.4.8.8 Module operation............................................................................................................................. 484
4.4.8.9 Register description......................................................................................................................... 486
4.4.9 X20AO4632-1........................................................................................................................................ 489
4.4.9.1 General information..........................................................................................................................489
4.4.9.2 Order data........................................................................................................................................ 489
4.4.9.3 Technical data..................................................................................................................................489

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4.4.9.4 LED status indicators....................................................................................................................... 490

4.4.9.5 Pinout............................................................................................................................................... 490
4.4.9.6 Connection example........................................................................................................................ 491
4.4.9.7 Output circuit diagram......................................................................................................................491
4.4.9.8 Module operation............................................................................................................................. 491
4.4.9.9 Register description......................................................................................................................... 494
4.4.10 X20AO4635......................................................................................................................................... 498
4.4.10.1 General information........................................................................................................................498
4.4.10.2 Order data...................................................................................................................................... 498
4.4.10.3 Technical data................................................................................................................................498
4.4.10.4 LED status indicators..................................................................................................................... 499
4.4.10.5 Pinout............................................................................................................................................. 500
4.4.10.6 Connection example...................................................................................................................... 500
4.4.10.7 Output circuit diagram....................................................................................................................500
4.4.10.8 Module operation........................................................................................................................... 501
4.4.10.9 Register description....................................................................................................................... 503
4.5 Bus controllers............................................................................................................................................ 505
4.5.1 Brief information.................................................................................................................................... 506
4.5.2 X20BC0043............................................................................................................................................507
4.5.2.1 General information..........................................................................................................................507
4.5.2.2 Order data........................................................................................................................................ 507
4.5.2.3 Technical data..................................................................................................................................507
4.5.2.4 LED status indicators....................................................................................................................... 508
4.5.2.5 Operating and connection elements................................................................................................ 509
4.5.2.6 CAN bus interface............................................................................................................................509
4.5.2.7 Terminating resistor......................................................................................................................... 510
4.5.2.8 Node number and transfer rate....................................................................................................... 510
4.5.2.9 Automatic transfer rate detection.....................................................................................................511
4.5.2.10 Setting the transfer rate................................................................................................................. 511
4.5.2.11 Deleting parameters....................................................................................................................... 512
4.5.2.12 Additional documentation and import files (EDS).......................................................................... 512
4.5.3 X20BC0043-10...................................................................................................................................... 513
4.5.3.1 General information..........................................................................................................................513
4.5.3.2 Order data........................................................................................................................................ 514
4.5.3.3 Technical data..................................................................................................................................514
4.5.3.4 LED status indicators....................................................................................................................... 515
4.5.3.5 Operating and connection elements................................................................................................ 516
4.5.3.6 CAN bus interface............................................................................................................................516
4.5.3.7 Terminating resistor......................................................................................................................... 516
4.5.3.8 Node number and transfer rate....................................................................................................... 517
4.5.3.9 Automatic transfer rate detection.....................................................................................................517
4.5.3.10 Setting the transfer rate................................................................................................................. 518
4.5.3.11 Save automatic configuration.........................................................................................................519
4.5.3.12 Deleting parameters.......................................................................................................................520
4.5.3.13 Additional documentation and import files (EDS).......................................................................... 520
4.5.4 X20BC0053............................................................................................................................................521
4.5.4.1 General information..........................................................................................................................521
4.5.4.2 Order data........................................................................................................................................ 521
4.5.4.3 Technical data..................................................................................................................................521
4.5.4.4 LED status indicators....................................................................................................................... 522
4.5.4.5 Operating and connection elements................................................................................................ 523
4.5.4.6 DeviceNet interface..........................................................................................................................523
4.5.4.7 Terminating resistor......................................................................................................................... 524
4.5.4.8 Node number................................................................................................................................... 524
4.5.4.9 Automatic transfer rate detection.....................................................................................................525
4.5.4.10 Clearing the parameters................................................................................................................ 525
4.5.4.11 Automatic configuration of the I/O modules...................................................................................526

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4.5.4.12 Additional documentation and import files (EDS).......................................................................... 526

4.5.5 X20BC0063............................................................................................................................................527
4.5.5.1 General information..........................................................................................................................527
4.5.5.2 Order data........................................................................................................................................ 527
4.5.5.3 Technical data..................................................................................................................................528
4.5.5.4 LED status indicators....................................................................................................................... 529
4.5.5.5 State diagnostics via the Status/Error LEDs................................................................................... 529
4.5.5.6 Operating and connection elements................................................................................................ 530
4.5.5.7 PROFIBUS DP interface..................................................................................................................530
4.5.5.8 PROFIBUS DP node number switches........................................................................................... 530
4.5.5.9 Automatic transfer rate detection.....................................................................................................531
4.5.5.10 Additional documentation and import files (EDS).......................................................................... 531
4.5.6 X20BC0073............................................................................................................................................532
4.5.6.1 General information..........................................................................................................................532
4.5.6.2 Order data........................................................................................................................................ 532
4.5.6.3 Technical data..................................................................................................................................532
4.5.6.4 LED status indicators....................................................................................................................... 533
4.5.6.5 Operating and connection elements................................................................................................ 534
4.5.6.6 CAN bus interface............................................................................................................................534
4.5.6.7 Terminating resistor......................................................................................................................... 534
4.5.6.8 Node number and transfer rate....................................................................................................... 535
4.5.6.9 Automatic transfer rate detection.....................................................................................................535
4.5.6.10 SG4................................................................................................................................................ 536
4.5.7 X20BC0083............................................................................................................................................537
4.5.7.1 General information..........................................................................................................................537
4.5.7.2 Order data........................................................................................................................................ 537
4.5.7.3 Technical data..................................................................................................................................538
4.5.7.4 LED status indicators....................................................................................................................... 539
4.5.7.5 Operating and connection elements................................................................................................ 540
4.5.7.6 POWERLINK station number...........................................................................................................540
4.5.7.7 RJ45 ports........................................................................................................................................541
4.5.7.8 SG3.................................................................................................................................................. 541
4.5.7.9 SG4.................................................................................................................................................. 541
4.5.8 X20BC0087............................................................................................................................................542
4.5.8.1 General information..........................................................................................................................542
4.5.8.2 Order data........................................................................................................................................ 542
4.5.8.3 Technical data..................................................................................................................................542
4.5.8.4 LED status indicators....................................................................................................................... 543
4.5.8.5 Operating and connection elements................................................................................................ 544
4.5.8.6 RJ45 ports........................................................................................................................................544
4.5.8.7 Modbus/TCP network address switch............................................................................................. 545
4.5.8.8 Setting the IP address (default value)............................................................................................. 545
4.5.8.9 Automatic IP assignment by a DHCP server.................................................................................. 546
4.5.8.10 Changing the IP address with the network address switches....................................................... 546
4.5.8.11 Information about NetBIOS names................................................................................................ 546
4.5.8.12 Saving an IP address to flash memory......................................................................................... 546
4.5.9 X20BC0088............................................................................................................................................547
4.5.9.1 General information..........................................................................................................................547
4.5.9.2 Order data........................................................................................................................................ 547
4.5.9.3 Technical data..................................................................................................................................547
4.5.9.4 LED status indicators....................................................................................................................... 548
4.5.9.5 Operating and connection elements................................................................................................ 549
4.5.9.6 RJ45 ports........................................................................................................................................549
4.5.9.7 EtherNet/IP address switching positions......................................................................................... 550
4.5.9.8 Setting the IP address (default value)............................................................................................. 550
4.5.9.9 Automatic IP assignment by DHCP server......................................................................................551
4.5.9.10 Changing the IP address with the network address switch...........................................................551

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4.5.9.11 Saving an IP address in flash memory..........................................................................................551

4.5.10 X20BC00E3......................................................................................................................................... 552
4.5.10.1 General information........................................................................................................................552
4.5.10.2 Order data...................................................................................................................................... 552
4.5.10.3 Technical data................................................................................................................................553
4.5.10.4 LED status indicators..................................................................................................................... 554
4.5.10.5 Operating and connection elements.............................................................................................. 555
4.5.10.6 RJ45 ports......................................................................................................................................555
4.5.10.7 Node number switches.................................................................................................................. 556
4.5.10.8 Erasing flash memory.................................................................................................................... 556
4.5.10.9 Web interface................................................................................................................................. 556
4.5.11 X20BC00G3......................................................................................................................................... 558
4.5.11.1 General information........................................................................................................................558
4.5.11.2 Order data...................................................................................................................................... 558
4.5.11.3 Technical data................................................................................................................................ 558
4.5.11.4 LED status indicators..................................................................................................................... 560
4.5.11.5 Operating and connection elements.............................................................................................. 560
4.5.11.6 RJ45 ports...................................................................................................................................... 561
4.5.11.7 EtherCAT network address switch.................................................................................................561
4.5.12 X20BC0143-10.................................................................................................................................... 562
4.5.12.1 General information........................................................................................................................562
4.5.12.2 Order data...................................................................................................................................... 562
4.5.12.3 Technical data................................................................................................................................563
4.5.12.4 LED status indicators..................................................................................................................... 564
4.5.12.5 Operating and connection elements.............................................................................................. 564
4.5.12.6 CAN bus interface..........................................................................................................................565
4.5.12.7 Node number and transfer rate..................................................................................................... 565
4.5.12.8 Automatic transfer rate detection...................................................................................................566
4.5.12.9 Setting the transfer rate................................................................................................................. 566
4.5.12.10 Save automatic configuration.......................................................................................................567
4.5.12.11 Deleting parameters..................................................................................................................... 568
4.5.12.12 Additional documentation and import files (EDS)........................................................................ 568
4.6 Bus controllers System modules................................................................................................................ 569
4.6.1 Brief information.................................................................................................................................... 569
4.6.2 X20BB80................................................................................................................................................570
4.6.2.1 General information..........................................................................................................................570
4.6.2.2 Order data........................................................................................................................................ 570
4.6.2.3 Technical data..................................................................................................................................570
4.6.2.4 Voltage routing................................................................................................................................. 571
4.6.3 X20PS9400............................................................................................................................................572
4.6.3.1 General information..........................................................................................................................572
4.6.3.2 Order data........................................................................................................................................ 572
4.6.3.3 Technical data..................................................................................................................................572
4.6.3.4 LED status indicators....................................................................................................................... 573
4.6.3.5 Pinout............................................................................................................................................... 574
4.6.3.6 Using the service interface.............................................................................................................. 574
4.6.3.7 Connection examples.......................................................................................................................574
4.6.3.8 Derating............................................................................................................................................ 575
4.6.3.9 Register description......................................................................................................................... 576
4.6.4 X20PS9402............................................................................................................................................578
4.6.4.1 General information..........................................................................................................................578
4.6.4.2 Order data........................................................................................................................................ 578
4.6.4.3 Technical data..................................................................................................................................578
4.6.4.4 LED status indicators....................................................................................................................... 579
4.6.4.5 Pinout............................................................................................................................................... 580
4.6.4.6 Connection examples.......................................................................................................................580
4.6.4.7 Derating for bus controller / X2X Link supply..................................................................................581

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4.6.4.8 Register description......................................................................................................................... 582

4.7 Bus modules............................................................................................................................................... 583
4.7.1 Brief information.................................................................................................................................... 583
4.7.2 X20BM01............................................................................................................................................... 584
4.7.2.1 General information..........................................................................................................................584
4.7.2.2 Order data........................................................................................................................................ 584
4.7.2.3 Technical data..................................................................................................................................584
4.7.2.4 Voltage routing................................................................................................................................. 585
4.7.3 X20BM05............................................................................................................................................... 586
4.7.3.1 General information..........................................................................................................................586
4.7.3.2 Order data........................................................................................................................................ 586
4.7.3.3 Technical data..................................................................................................................................586
4.7.3.4 Voltage routing................................................................................................................................. 587
4.7.3.5 Node number switches.................................................................................................................... 587
4.7.4 X20BM11................................................................................................................................................588
4.7.4.1 General information..........................................................................................................................588
4.7.4.2 Order data........................................................................................................................................ 588
4.7.4.3 Technical data..................................................................................................................................588
4.7.4.4 Voltage routing................................................................................................................................. 589
4.7.5 X20BM12............................................................................................................................................... 590
4.7.5.1 General information..........................................................................................................................590
4.7.5.2 Order data........................................................................................................................................ 590
4.7.5.3 Technical data..................................................................................................................................590
4.7.5.4 Voltage routing................................................................................................................................. 591
4.7.6 X20BM15............................................................................................................................................... 592
4.7.6.1 General information..........................................................................................................................592
4.7.6.2 Order data........................................................................................................................................ 592
4.7.6.3 Technical data..................................................................................................................................592
4.7.6.4 Voltage routing................................................................................................................................. 593
4.7.6.5 Node number switches.................................................................................................................... 593
4.7.7 X20BM21............................................................................................................................................... 594
4.7.7.1 General information..........................................................................................................................594
4.7.7.2 Order data........................................................................................................................................ 594
4.7.7.3 Technical data..................................................................................................................................594
4.7.7.4 Voltage routing................................................................................................................................. 595
4.7.8 X20BM31............................................................................................................................................... 596
4.7.8.1 General information..........................................................................................................................596
4.7.8.2 Order data........................................................................................................................................ 596
4.7.8.3 Technical data..................................................................................................................................596
4.7.8.4 Voltage routing................................................................................................................................. 597
4.7.9 X20BM32............................................................................................................................................... 598
4.7.9.1 General information..........................................................................................................................598
4.7.9.2 Order data........................................................................................................................................ 598
4.7.9.3 Technical data..................................................................................................................................598
4.7.9.4 Voltage routing................................................................................................................................. 599
4.8 Bus receivers and Bus transmitters............................................................................................................600
4.8.1 Brief information.................................................................................................................................... 600
4.8.2 X20BR9300............................................................................................................................................601
4.8.2.1 General information..........................................................................................................................601
4.8.2.2 Order data........................................................................................................................................ 601
4.8.2.3 Technical data..................................................................................................................................602
4.8.2.4 LED status indicators....................................................................................................................... 603
4.8.2.5 Pinout............................................................................................................................................... 603
4.8.2.6 Connection examples.......................................................................................................................604
4.8.2.7 Derating............................................................................................................................................ 604
4.8.2.8 Register description......................................................................................................................... 605
4.8.3 X20BT9100............................................................................................................................................ 607

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4.8.3.1 General information..........................................................................................................................607

4.8.3.2 Order data........................................................................................................................................ 607
4.8.3.3 Technical data..................................................................................................................................608
4.8.3.4 LED status indicators....................................................................................................................... 609
4.8.3.5 Pinout............................................................................................................................................... 609
4.8.3.6 Connection examples.......................................................................................................................609
4.8.3.7 Supply via bus transmitter............................................................................................................... 610
4.8.3.8 Connection to next X2X Link I/O node............................................................................................611
4.8.3.9 Register description......................................................................................................................... 612
4.8.4 X20BT9400............................................................................................................................................ 613
4.8.4.1 General information..........................................................................................................................613
4.8.4.2 Order data........................................................................................................................................ 613
4.8.4.3 Technical data..................................................................................................................................614
4.8.4.4 LED status indicators....................................................................................................................... 615
4.8.4.5 Pinout............................................................................................................................................... 615
4.8.4.6 Connection examples.......................................................................................................................615
4.8.4.7 Supply via bus transmitter............................................................................................................... 616
4.8.4.8 Connection between X20 and X67 system..................................................................................... 617
4.8.4.9 Register description......................................................................................................................... 618
4.9 Compact CPUs........................................................................................................................................... 620
4.9.1 Brief information.................................................................................................................................... 621
4.9.2 X20CP0201, X20CP0291, X20CP0292................................................................................................ 622
4.9.2.1 General information..........................................................................................................................622
4.9.2.2 Order data........................................................................................................................................ 623
4.9.2.3 Technical data..................................................................................................................................624
4.9.2.4 LED status indicators....................................................................................................................... 625
4.9.2.5 Operating and connection elements................................................................................................ 625
4.9.2.6 Node number switches.................................................................................................................... 626
4.9.2.7 Ethernet interface (IF2).................................................................................................................... 627
4.9.2.8 Programming the system flash memory.......................................................................................... 628
4.10 Compact CPUs System modules............................................................................................................. 629
4.10.1 Brief information.................................................................................................................................. 629
4.10.2 X20BB22..............................................................................................................................................630
4.10.2.1 General information........................................................................................................................630
4.10.2.2 Order data...................................................................................................................................... 630
4.10.2.3 Technical data................................................................................................................................630
4.10.2.4 Voltage routing............................................................................................................................... 631
4.10.3 X20BB27..............................................................................................................................................632
4.10.3.1 General information........................................................................................................................632
4.10.3.2 Order data...................................................................................................................................... 632
4.10.3.3 Technical data................................................................................................................................632
4.10.3.4 Voltage routing............................................................................................................................... 633
4.10.3.5 Terminating resistor for CAN bus.................................................................................................. 633
4.10.4 X20PS9500..........................................................................................................................................634
4.10.4.1 General information........................................................................................................................634
4.10.4.2 Order data...................................................................................................................................... 634
4.10.4.3 Technical data................................................................................................................................635
4.10.4.4 LED status indicators..................................................................................................................... 636
4.10.4.5 Pinout............................................................................................................................................. 636
4.10.4.6 Connection examples.....................................................................................................................637
4.10.4.7 Derating.......................................................................................................................................... 637
4.10.4.8 Register description....................................................................................................................... 638
4.10.5 X20PS9502..........................................................................................................................................639
4.10.5.1 General information........................................................................................................................639
4.10.5.2 Order data...................................................................................................................................... 639
4.10.5.3 Technical data................................................................................................................................639
4.10.5.4 LED status indicators..................................................................................................................... 641

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4.10.5.5 Pinout............................................................................................................................................. 641

4.10.5.6 Connection examples.....................................................................................................................642
4.10.5.7 Derating for CPU / X2X Link supply..............................................................................................643
4.10.5.8 Register description....................................................................................................................... 644
4.11 Counter modules....................................................................................................................................... 645
4.11.1 Brief information...................................................................................................................................645
4.11.2 X20CM1941......................................................................................................................................... 646
4.11.2.1 General information........................................................................................................................646
4.11.2.2 Order data...................................................................................................................................... 646
4.11.2.3 Technical data................................................................................................................................ 646
4.11.2.4 LED status indicators..................................................................................................................... 648
4.11.2.5 Pinout..............................................................................................................................................648
4.11.2.6 Connection example.......................................................................................................................648
4.11.2.7 Input circuit diagram.......................................................................................................................649
4.11.2.8 Output circuit diagram.................................................................................................................... 649
4.11.2.9 ABR encoder.................................................................................................................................. 650
4.11.2.10 Register description......................................................................................................................651
4.11.3 X20DC1176.......................................................................................................................................... 653
4.11.3.1 General information........................................................................................................................653
4.11.3.2 Order data...................................................................................................................................... 653
4.11.3.3 Technical data................................................................................................................................ 653
4.11.3.4 LED status indicators..................................................................................................................... 655
4.11.3.5 Pinout..............................................................................................................................................655
4.11.3.6 Connection example.......................................................................................................................655
4.11.3.7 Input circuit diagram.......................................................................................................................656
4.11.3.8 Register description........................................................................................................................657
4.11.4 X20DC1178.......................................................................................................................................... 669
4.11.4.1 General information........................................................................................................................669
4.11.4.2 Order data...................................................................................................................................... 669
4.11.4.3 Technical data................................................................................................................................ 669
4.11.4.4 LED status indicators..................................................................................................................... 671
4.11.4.5 Pinout..............................................................................................................................................671
4.11.4.6 Connection example.......................................................................................................................671
4.11.4.7 Input circuit diagram.......................................................................................................................672
4.11.4.8 Output circuit diagram.................................................................................................................... 672
4.11.4.9 Register description........................................................................................................................673
4.11.5 X20DC1196.......................................................................................................................................... 684
4.11.5.1 General information........................................................................................................................684
4.11.5.2 Order data...................................................................................................................................... 684
4.11.5.3 Technical data................................................................................................................................ 684
4.11.5.4 LED status indicators..................................................................................................................... 686
4.11.5.5 Pinout..............................................................................................................................................686
4.11.5.6 Connection example.......................................................................................................................686
4.11.5.7 Input circuit diagram.......................................................................................................................687
4.11.5.8 Register description........................................................................................................................688
4.11.6 X20DC1198.......................................................................................................................................... 694
4.11.6.1 General information........................................................................................................................694
4.11.6.2 Order data...................................................................................................................................... 694
4.11.6.3 Technical data................................................................................................................................ 694
4.11.6.4 LED status indicators..................................................................................................................... 696
4.11.6.5 Pinout..............................................................................................................................................696
4.11.6.6 Connection example.......................................................................................................................696
4.11.6.7 Input circuit diagram.......................................................................................................................697
4.11.6.8 Output circuit diagram.................................................................................................................... 697
4.11.6.9 Register description........................................................................................................................698
4.11.7 X20DC11A6..........................................................................................................................................701
4.11.7.1 General information........................................................................................................................701

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4.11.7.2 Order data...................................................................................................................................... 701

4.11.7.3 Technical data................................................................................................................................ 701
4.11.7.4 LED status indicators..................................................................................................................... 703
4.11.7.5 Pinout..............................................................................................................................................703
4.11.7.6 Connection example.......................................................................................................................703
4.11.7.7 Input circuit diagram.......................................................................................................................704
4.11.7.8 Register description........................................................................................................................705
4.11.8 X20DC1376..........................................................................................................................................717
4.11.8.1 General information........................................................................................................................717
4.11.8.2 Order data...................................................................................................................................... 717
4.11.8.3 Technical data................................................................................................................................ 717
4.11.8.4 LED status indicators..................................................................................................................... 719
4.11.8.5 Pinout..............................................................................................................................................719
4.11.8.6 Connection example.......................................................................................................................719
4.11.8.7 Input circuit diagram.......................................................................................................................720
4.11.8.8 Register description........................................................................................................................721
4.11.9 X20DC137A......................................................................................................................................... 732
4.11.9.1 General information........................................................................................................................732
4.11.9.2 Order data...................................................................................................................................... 732
4.11.9.3 Technical data................................................................................................................................ 732
4.11.9.4 LED status indicators..................................................................................................................... 734
4.11.9.5 Pinout..............................................................................................................................................734
4.11.9.6 Connection example.......................................................................................................................734
4.11.9.7 Input circuit diagram.......................................................................................................................735
4.11.9.8 Register description........................................................................................................................736
4.11.10 X20DC1396........................................................................................................................................747
4.11.10.1 General information...................................................................................................................... 747
4.11.10.2 Order data.................................................................................................................................... 747
4.11.10.3 Technical data.............................................................................................................................. 747
4.11.10.4 LED status indicators................................................................................................................... 749
4.11.10.5 Pinout............................................................................................................................................749
4.11.10.6 Connection example.....................................................................................................................749
4.11.10.7 Input circuit diagram.....................................................................................................................750
4.11.10.8 Register description......................................................................................................................751
4.11.11 X20DC1398........................................................................................................................................ 757
4.11.11.1 General information...................................................................................................................... 757
4.11.11.2 Order data.................................................................................................................................... 757
4.11.11.3 Technical data.............................................................................................................................. 757
4.11.11.4 LED status indicators................................................................................................................... 759
4.11.11.5 Pinout............................................................................................................................................ 759
4.11.11.6 Connection example..................................................................................................................... 759
4.11.11.7 Input circuit diagram..................................................................................................................... 760
4.11.11.8 Output circuit diagram.................................................................................................................. 760
4.11.11.9 Register description...................................................................................................................... 761
4.11.12 X20DC1976........................................................................................................................................764
4.11.12.1 General information...................................................................................................................... 764
4.11.12.2 Order data.................................................................................................................................... 764
4.11.12.3 Technical data.............................................................................................................................. 764
4.11.12.4 LED status indicators................................................................................................................... 766
4.11.12.5 Pinout............................................................................................................................................766
4.11.12.6 Connection example.....................................................................................................................766
4.11.12.7 Input circuit diagram.....................................................................................................................767
4.11.12.8 Register description......................................................................................................................768
4.11.13 X20DC2190........................................................................................................................................780
4.11.13.1 General information...................................................................................................................... 780
4.11.13.2 Order data.................................................................................................................................... 780
4.11.13.3 Technical data.............................................................................................................................. 780

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4.11.13.4 LED status indicators................................................................................................................... 781

4.11.13.5 Pinout............................................................................................................................................782
4.11.13.6 Connection example.....................................................................................................................782
4.11.13.7 Register description......................................................................................................................783
4.11.14 X20DC2395........................................................................................................................................793
4.11.14.1 General information...................................................................................................................... 793
4.11.14.2 Order data.................................................................................................................................... 793
4.11.14.3 Technical data.............................................................................................................................. 794
4.11.14.4 LED status indicators................................................................................................................... 796
4.11.14.5 Pinout............................................................................................................................................796
4.11.14.6 Connection example.....................................................................................................................796
4.11.14.7 Function overview........................................................................................................................ 797
4.11.14.8 Input circuit diagram.....................................................................................................................798
4.11.14.9 Output circuit diagram.................................................................................................................. 798
4.11.14.10 Switching inductive loads........................................................................................................... 799
4.11.14.11 Calculating the period duration.................................................................................................. 799
4.11.14.12 Register description....................................................................................................................800
4.11.15 X20DC2396........................................................................................................................................833
4.11.15.1 General information...................................................................................................................... 833
4.11.15.2 Order data.................................................................................................................................... 833
4.11.15.3 Technical data.............................................................................................................................. 833
4.11.15.4 LED status indicators................................................................................................................... 835
4.11.15.5 Pinout............................................................................................................................................835
4.11.15.6 Connection example.....................................................................................................................835
4.11.15.7 Input circuit diagram.....................................................................................................................836
4.11.15.8 Register description......................................................................................................................837
4.11.16 X20DC2398........................................................................................................................................843
4.11.16.1 General information...................................................................................................................... 843
4.11.16.2 Order data.................................................................................................................................... 843
4.11.16.3 Technical data.............................................................................................................................. 843
4.11.16.4 LED status indicators................................................................................................................... 845
4.11.16.5 Pinout............................................................................................................................................845
4.11.16.6 Connection example.....................................................................................................................845
4.11.16.7 Input circuit diagram.....................................................................................................................846
4.11.16.8 Output circuit diagram.................................................................................................................. 846
4.11.16.9 Register description......................................................................................................................847
4.11.17 X20DC4395........................................................................................................................................850
4.11.17.1 General information...................................................................................................................... 850
4.11.17.2 Order data.................................................................................................................................... 850
4.11.17.3 Technical data.............................................................................................................................. 851
4.11.17.4 LED status indicators................................................................................................................... 853
4.11.17.5 Pinout............................................................................................................................................853
4.11.17.6 Connection example.....................................................................................................................853
4.11.17.7 Function overview........................................................................................................................ 854
4.11.17.8 Input circuit diagram.....................................................................................................................856
4.11.17.9 Output circuit diagram.................................................................................................................. 856
4.11.17.10 Switching inductive loads........................................................................................................... 857
4.11.17.11 Calculating the period duration.................................................................................................. 857
4.11.17.12 Register description....................................................................................................................858
4.12 X20 CPUs................................................................................................................................................. 893
4.12.1 Brief information.................................................................................................................................. 894
4.12.2 X20CP1483 and X20CP1483-1.......................................................................................................... 895
4.12.2.1 General information........................................................................................................................895
4.12.2.2 Order data - X20CP148x............................................................................................................... 896
4.12.2.3 Technical data - X20CP148x.........................................................................................................897
4.12.2.4 X20 CPUs - Status LEDs.............................................................................................................. 900
4.12.2.5 LED status indicators for the integrated power supply.................................................................. 903

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4.12.2.6 Operating and connection elements.............................................................................................. 903

4.12.2.7 Slot for application memory........................................................................................................... 904
4.12.2.8 Operating mode switch.................................................................................................................. 904
4.12.2.9 Reset button...................................................................................................................................904
4.12.2.10 CPU supply.................................................................................................................................. 905
4.12.2.11 RS232 interface (IF1)...................................................................................................................906
4.12.2.12 Ethernet interface (IF2)................................................................................................................ 906
4.12.2.13 POWERLINK interface (IF3)........................................................................................................ 907
4.12.2.14 USB interfaces (IF4 and IF5).......................................................................................................908
4.12.2.15 Slots for interface modules.......................................................................................................... 908
4.12.2.16 Overtemperature cutoff................................................................................................................ 908
4.12.2.17 Data / Real-time clock buffering.................................................................................................. 909
4.12.2.18 Exchanging the lithium battery.................................................................................................... 909
4.12.2.19 Programming the system flash memory...................................................................................... 911
4.12.3 X20CP158x and X20CP358x.............................................................................................................. 912
4.12.3.1 General information........................................................................................................................912
4.12.3.2 Order data - X20CP158x............................................................................................................... 913
4.12.3.3 Technical data - X20CP158x.........................................................................................................914
4.12.3.4 Order data - X20CP358x............................................................................................................... 917
4.12.3.5 X20CP358x - Technical data.........................................................................................................918
4.12.3.6 X20 CPUs - Status LEDs.............................................................................................................. 921
4.12.3.7 LED status indicators for the integrated power supply.................................................................. 924
4.12.3.8 Operating and connection elements.............................................................................................. 925
4.12.3.9 Slot for application memory........................................................................................................... 926
4.12.3.10 Operating mode switch................................................................................................................ 926
4.12.3.11 Reset button................................................................................................................................. 926
4.12.3.12 CPU supply.................................................................................................................................. 927
4.12.3.13 RS232 interface (IF1).................................................................................................................. 928
4.12.3.14 Ethernet interface (IF2)................................................................................................................ 928
4.12.3.15 POWERLINK interface (IF3)........................................................................................................ 929
4.12.3.16 USB interfaces (IF4 and IF5).......................................................................................................930
4.12.3.17 Slots for interface modules.......................................................................................................... 930
4.12.3.18 Overtemperature cutoff................................................................................................................ 930
4.12.3.19 Data / Real-time clock buffering.................................................................................................. 931
4.12.3.20 Exchanging the lithium battery.................................................................................................... 931
4.12.3.21 Programming the system flash memory...................................................................................... 933
4.12.3.22 Information regarding switching from X20CPx48x to X20CPx58x...............................................934
4.13 Digital input modules................................................................................................................................ 935
4.13.1 Brief information.................................................................................................................................. 935
4.13.2 X20DI2371........................................................................................................................................... 936
4.13.2.1 General Information....................................................................................................................... 936
4.13.2.2 Order data...................................................................................................................................... 936
4.13.2.3 Technical data................................................................................................................................937
4.13.2.4 Status LEDs................................................................................................................................... 938
4.13.2.5 Pinout............................................................................................................................................. 938
4.13.2.6 Connection example...................................................................................................................... 938
4.13.2.7 Input circuit diagram...................................................................................................................... 939
4.13.2.8 Input filter....................................................................................................................................... 939
4.13.2.9 Register description....................................................................................................................... 940
4.13.3 X20DI2372........................................................................................................................................... 942
4.13.3.1 General Information....................................................................................................................... 942
4.13.3.2 Order data...................................................................................................................................... 942
4.13.3.3 Technical data................................................................................................................................943
4.13.3.4 Status LEDs................................................................................................................................... 944
4.13.3.5 Pinout............................................................................................................................................. 944
4.13.3.6 Connection example...................................................................................................................... 944
4.13.3.7 Input circuit diagram...................................................................................................................... 945

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4.13.3.8 Input filter....................................................................................................................................... 945

4.13.3.9 Register description....................................................................................................................... 946
4.13.4 X20DI2377........................................................................................................................................... 948
4.13.4.1 General Information....................................................................................................................... 948
4.13.4.2 Order data...................................................................................................................................... 948
4.13.4.3 Technical data................................................................................................................................948
4.13.4.4 Status LEDs................................................................................................................................... 950
4.13.4.5 Pinout............................................................................................................................................. 950
4.13.4.6 Connection example...................................................................................................................... 950
4.13.4.7 Input circuit diagram...................................................................................................................... 951
4.13.4.8 Input filter....................................................................................................................................... 951
4.13.4.9 Register description....................................................................................................................... 952
4.13.5 X20DI2653........................................................................................................................................... 956
4.13.5.1 General Information....................................................................................................................... 956
4.13.5.2 Order data...................................................................................................................................... 956
4.13.5.3 Technical data................................................................................................................................957
4.13.5.4 Status LEDs................................................................................................................................... 958
4.13.5.5 Pinout............................................................................................................................................. 958
4.13.5.6 Connection example...................................................................................................................... 958
4.13.5.7 Input circuit diagram...................................................................................................................... 959
4.13.5.8 Input filter....................................................................................................................................... 959
4.13.5.9 Register description....................................................................................................................... 960
4.13.6 X20DI4371........................................................................................................................................... 962
4.13.6.1 General Information....................................................................................................................... 962
4.13.6.2 Order data...................................................................................................................................... 962
4.13.6.3 Technical data................................................................................................................................962
4.13.6.4 Status LEDs................................................................................................................................... 964
4.13.6.5 Pinout............................................................................................................................................. 964
4.13.6.6 Connection example...................................................................................................................... 964
4.13.6.7 Input circuit diagram...................................................................................................................... 965
4.13.6.8 Input filter....................................................................................................................................... 965
4.13.6.9 Register description....................................................................................................................... 966
4.13.7 X20DI4372........................................................................................................................................... 969
4.13.7.1 General Information....................................................................................................................... 969
4.13.7.2 Order data...................................................................................................................................... 969
4.13.7.3 Technical data................................................................................................................................970
4.13.7.4 Status LEDs................................................................................................................................... 971
4.13.7.5 Pinout............................................................................................................................................. 971
4.13.7.6 Connection example...................................................................................................................... 971
4.13.7.7 Input circuit diagram...................................................................................................................... 972
4.13.7.8 Input filter....................................................................................................................................... 972
4.13.7.9 Register description....................................................................................................................... 973
4.13.8 X20DI4375........................................................................................................................................... 975
4.13.8.1 General Information....................................................................................................................... 975
4.13.8.2 Order data...................................................................................................................................... 975
4.13.8.3 Technical data................................................................................................................................976
4.13.8.4 Status LEDs................................................................................................................................... 977
4.13.8.5 Pinout............................................................................................................................................. 977
4.13.8.6 Connection example...................................................................................................................... 977
4.13.8.7 Input circuit diagram...................................................................................................................... 978
4.13.8.8 Input filter....................................................................................................................................... 978
4.13.8.9 Open circuit and short circuit detection......................................................................................... 978
4.13.8.10 Error status...................................................................................................................................979
4.13.8.11 Timestamp.................................................................................................................................... 979
4.13.8.12 Configuration................................................................................................................................ 979
4.13.8.13 Register description..................................................................................................................... 980
4.13.9 X20DI4653........................................................................................................................................... 986

18 X20 system User's Manual 3.10

 Table of contents

4.13.9.1 General Information....................................................................................................................... 986

4.13.9.2 Order data...................................................................................................................................... 986
4.13.9.3 Technical data................................................................................................................................987
4.13.9.4 Status LEDs................................................................................................................................... 988
4.13.9.5 Pinout............................................................................................................................................. 988
4.13.9.6 Connection example...................................................................................................................... 988
4.13.9.7 Input circuit diagram...................................................................................................................... 989
4.13.9.8 Input filter....................................................................................................................................... 989
4.13.9.9 Register description....................................................................................................................... 990
4.13.10 X20DI4760......................................................................................................................................... 992
4.13.10.1 General Information..................................................................................................................... 992
4.13.10.2 Order data.................................................................................................................................... 992
4.13.10.3 Technical data..............................................................................................................................992
4.13.10.4 Status LEDs................................................................................................................................. 994
4.13.10.5 Pinout........................................................................................................................................... 994
4.13.10.6 Connection example.................................................................................................................... 994
4.13.10.7 Input circuit diagram.................................................................................................................... 995
4.13.10.8 Input filter..................................................................................................................................... 995
4.13.10.9 Examples of possible signal generators...................................................................................... 996
4.13.10.10 Register description................................................................................................................... 997
4.13.11 X20DI6371....................................................................................................................................... 1001
4.13.11.1 General Information....................................................................................................................1001
4.13.11.2 Order data.................................................................................................................................. 1001
4.13.11.3 Technical data............................................................................................................................ 1002
4.13.11.4 Status LEDs............................................................................................................................... 1003
4.13.11.5 Pinout..........................................................................................................................................1003
4.13.11.6 Connection example...................................................................................................................1003
4.13.11.7 Input circuit diagram...................................................................................................................1004
4.13.11.8 Input filter....................................................................................................................................1004
4.13.11.9 Register description....................................................................................................................1005
4.13.12 X20DI6372....................................................................................................................................... 1007
4.13.12.1 General Information................................................................................................................... 1007
4.13.12.2 Order data.................................................................................................................................. 1007
4.13.12.3 Technical data............................................................................................................................1008
4.13.12.4 Status LEDs............................................................................................................................... 1009
4.13.12.5 Pinout......................................................................................................................................... 1009
4.13.12.6 Connection example.................................................................................................................. 1009
4.13.12.7 Input circuit diagram.................................................................................................................. 1010
4.13.12.8 Input filter................................................................................................................................... 1010
4.13.12.9 Register description................................................................................................................... 1011
4.13.13 X20DI6373....................................................................................................................................... 1013
4.13.13.1 General Information................................................................................................................... 1013
4.13.13.2 Order data.................................................................................................................................. 1013
4.13.13.3 Technical data............................................................................................................................1014
4.13.13.4 Status LEDs............................................................................................................................... 1015
4.13.13.5 Pinout......................................................................................................................................... 1015
4.13.13.6 Connection example.................................................................................................................. 1015
4.13.13.7 Input circuit diagram.................................................................................................................. 1016
4.13.13.8 Input filter................................................................................................................................... 1016
4.13.13.9 Register description................................................................................................................... 1017
4.13.14 X20DI6553....................................................................................................................................... 1019
4.13.14.1 General Information................................................................................................................... 1019
4.13.14.2 Order data.................................................................................................................................. 1019
4.13.14.3 Technical data............................................................................................................................1020
4.13.14.4 Status LEDs............................................................................................................................... 1021
4.13.14.5 Pinout......................................................................................................................................... 1021
4.13.14.6 Connection example.................................................................................................................. 1021

X20 system User's Manual 3.10 19

Table of contents

4.13.14.7 Input circuit diagram.................................................................................................................. 1022

4.13.14.8 Input filter................................................................................................................................... 1022
4.13.14.9 Register description................................................................................................................... 1023
4.13.15 X20DI8371....................................................................................................................................... 1025
4.13.15.1 General Information................................................................................................................... 1025
4.13.15.2 Order data.................................................................................................................................. 1025
4.13.15.3 Technical data............................................................................................................................1026
4.13.15.4 Status LEDs............................................................................................................................... 1027
4.13.15.5 Pinout......................................................................................................................................... 1027
4.13.15.6 Connection example.................................................................................................................. 1027
4.13.15.7 Input circuit diagram.................................................................................................................. 1028
4.13.15.8 Input filter................................................................................................................................... 1028
4.13.15.9 Register description................................................................................................................... 1029
4.13.16 X20DI9371....................................................................................................................................... 1031
4.13.16.1 General Information................................................................................................................... 1031
4.13.16.2 Order data.................................................................................................................................. 1031
4.13.16.3 Technical data............................................................................................................................1031
4.13.16.4 Status LEDs............................................................................................................................... 1032
4.13.16.5 Pinout......................................................................................................................................... 1033
4.13.16.6 Connection example.................................................................................................................. 1033
4.13.16.7 Input circuit diagram.................................................................................................................. 1033
4.13.16.8 Input filter................................................................................................................................... 1034
4.13.16.9 Derating for the simultaneity factor............................................................................................1034
4.13.16.10 Register description................................................................................................................. 1035
4.13.17 X20DI9372....................................................................................................................................... 1037
4.13.17.1 General Information................................................................................................................... 1037
4.13.17.2 Order data.................................................................................................................................. 1037
4.13.17.3 Technical data............................................................................................................................1037
4.13.17.4 Status LEDs............................................................................................................................... 1038
4.13.17.5 Pinout......................................................................................................................................... 1039
4.13.17.6 Connection example.................................................................................................................. 1039
4.13.17.7 Input circuit diagram.................................................................................................................. 1039
4.13.17.8 Input filter................................................................................................................................... 1040
4.13.17.9 Derating for the simultaneity factor............................................................................................1040
4.13.17.10 Register description................................................................................................................. 1041
4.13.18 X20DID371...................................................................................................................................... 1043
4.13.18.1 General Information................................................................................................................... 1043
4.13.18.2 Order data.................................................................................................................................. 1043
4.13.18.3 Technical data............................................................................................................................1044
4.13.18.4 Status LEDs............................................................................................................................... 1045
4.13.18.5 Pinout......................................................................................................................................... 1045
4.13.18.6 Connection example.................................................................................................................. 1045
4.13.18.7 Input circuit diagram.................................................................................................................. 1046
4.13.18.8 Input filter................................................................................................................................... 1046
4.13.18.9 Register description................................................................................................................... 1047
4.13.19 X20DIF371.......................................................................................................................................1049
4.13.19.1 General Information................................................................................................................... 1049
4.13.19.2 Order data.................................................................................................................................. 1049
4.13.19.3 Technical data............................................................................................................................1050
4.13.19.4 Status LEDs............................................................................................................................... 1051
4.13.19.5 Pinout......................................................................................................................................... 1051
4.13.19.6 Connection example.................................................................................................................. 1051
4.13.19.7 Input circuit diagram.................................................................................................................. 1052
4.13.19.8 Input filter................................................................................................................................... 1052
4.13.19.9 Register description................................................................................................................... 1053
4.14 Digital mixed modules.............................................................................................................................1055
4.14.1 Brief information.................................................................................................................................1055

20 X20 system User's Manual 3.10

 Table of contents

4.14.2 X20DM9324....................................................................................................................................... 1056

4.14.2.1 General information......................................................................................................................1056
4.14.2.2 Order data.................................................................................................................................... 1056
4.14.2.3 Technical data..............................................................................................................................1056
4.14.2.4 Status LEDs................................................................................................................................. 1058
4.14.2.5 Pinout........................................................................................................................................... 1058
4.14.2.6 Connection example.................................................................................................................... 1058
4.14.2.7 Input circuit diagram.................................................................................................................... 1059
4.14.2.8 Output circuit diagram..................................................................................................................1059
4.14.2.9 Switching inductive loads.............................................................................................................1059
4.14.2.10 Register description................................................................................................................... 1060
4.15 Digital output modules............................................................................................................................ 1063
4.15.1 Brief information.................................................................................................................................1063
4.15.2 Calculation of the additional power dissipation resulting from actuators...........................................1064
4.15.3 X20DO2321....................................................................................................................................... 1066
4.15.3.1 General information......................................................................................................................1066
4.15.3.2 Order data.................................................................................................................................... 1066
4.15.3.3 Technical data..............................................................................................................................1066
4.15.3.4 Status LEDs................................................................................................................................. 1068
4.15.3.5 Pinout........................................................................................................................................... 1068
4.15.3.6 Connection example.................................................................................................................... 1068
4.15.3.7 OSP hardware requirements....................................................................................................... 1068
4.15.3.8 Output circuit diagram..................................................................................................................1069
4.15.3.9 Switching inductive loads.............................................................................................................1069
4.15.3.10 Register description................................................................................................................... 1070
4.15.4 X20DO2322....................................................................................................................................... 1074
4.15.4.1 General information......................................................................................................................1074
4.15.4.2 Order data.................................................................................................................................... 1074
4.15.4.3 Technical data..............................................................................................................................1074
4.15.4.4 Status LEDs................................................................................................................................. 1076
4.15.4.5 Pinout........................................................................................................................................... 1076
4.15.4.6 Connection example.................................................................................................................... 1076
4.15.4.7 OSP hardware requirements....................................................................................................... 1077
4.15.4.8 Output circuit diagram..................................................................................................................1077
4.15.4.9 Switching inductive loads.............................................................................................................1077
4.15.4.10 Register description................................................................................................................... 1078
4.15.5 X20DO2623....................................................................................................................................... 1082
4.15.5.1 General information......................................................................................................................1082
4.15.5.2 Order data.................................................................................................................................... 1082
4.15.5.3 Technical data..............................................................................................................................1083
4.15.5.4 Status LEDs................................................................................................................................. 1084
4.15.5.5 Pinout........................................................................................................................................... 1084
4.15.5.6 Connection example.................................................................................................................... 1085
4.15.5.7 Output circuit diagram..................................................................................................................1085
4.15.5.8 Integrated full-wave control..........................................................................................................1086
4.15.5.9 Register description..................................................................................................................... 1087
4.15.6 X20DO2633....................................................................................................................................... 1091
4.15.6.1 General information......................................................................................................................1091
4.15.6.2 Order data.................................................................................................................................... 1091
4.15.6.3 Technical data..............................................................................................................................1092
4.15.6.4 Status LEDs................................................................................................................................. 1093
4.15.6.5 Pinout........................................................................................................................................... 1093
4.15.6.6 Connection example.................................................................................................................... 1094
4.15.6.7 OSP hardware requirements....................................................................................................... 1094
4.15.6.8 Output circuit diagram..................................................................................................................1094
4.15.6.9 External fuses.............................................................................................................................. 1095
4.15.6.10 Derating...................................................................................................................................... 1095

X20 system User's Manual 3.10 21

Table of contents

4.15.6.11 Operating principle..................................................................................................................... 1095

4.15.6.12 Open line detection.................................................................................................................... 1095
4.15.6.13 Operation with inductive loads...................................................................................................1096
4.15.6.14 Register description................................................................................................................... 1097
4.15.7 X20DO2649....................................................................................................................................... 1106
4.15.7.1 General information......................................................................................................................1106
4.15.7.2 Order data.................................................................................................................................... 1106
4.15.7.3 Technical data..............................................................................................................................1106
4.15.7.4 Status LEDs................................................................................................................................. 1108
4.15.7.5 Pinout........................................................................................................................................... 1108
4.15.7.6 Connection example.................................................................................................................... 1108
4.15.7.7 Output circuit diagram..................................................................................................................1109
4.15.7.8 Electrical service life.................................................................................................................... 1109
4.15.7.9 Register description..................................................................................................................... 1110
4.15.8 X20DO4321....................................................................................................................................... 1112
4.15.8.1 General information......................................................................................................................1112
4.15.8.2 Order data.................................................................................................................................... 1112
4.15.8.3 Technical data..............................................................................................................................1112
4.15.8.4 Status LEDs................................................................................................................................. 1114
4.15.8.5 Pinout........................................................................................................................................... 1114
4.15.8.6 Connection example.................................................................................................................... 1114
4.15.8.7 OSP hardware requirements....................................................................................................... 1114
4.15.8.8 Output circuit diagram..................................................................................................................1115
4.15.8.9 Switching inductive loads.............................................................................................................1115
4.15.8.10 Register description................................................................................................................... 1116
4.15.9 X20DO4322....................................................................................................................................... 1120
4.15.9.1 General information......................................................................................................................1120
4.15.9.2 Order data.................................................................................................................................... 1120
4.15.9.3 Technical data..............................................................................................................................1120
4.15.9.4 Status LEDs................................................................................................................................. 1122
4.15.9.5 Pinout........................................................................................................................................... 1122
4.15.9.6 Connection example.................................................................................................................... 1122
4.15.9.7 OSP hardware requirements....................................................................................................... 1123
4.15.9.8 Output circuit diagram..................................................................................................................1123
4.15.9.9 Switching inductive loads.............................................................................................................1123
4.15.9.10 Register description................................................................................................................... 1124
4.15.10 X20DO4331..................................................................................................................................... 1128
4.15.10.1 General information....................................................................................................................1128
4.15.10.2 Order data.................................................................................................................................. 1128
4.15.10.3 Technical data............................................................................................................................1128
4.15.10.4 Status LEDs............................................................................................................................... 1130
4.15.10.5 Pinout......................................................................................................................................... 1130
4.15.10.6 Connection example.................................................................................................................. 1131
4.15.10.7 OSP hardware requirements..................................................................................................... 1131
4.15.10.8 Output circuit diagram................................................................................................................1131
4.15.10.9 Switching inductive loads...........................................................................................................1132
4.15.10.10 Operation with 2 A................................................................................................................... 1133
4.15.10.11 Register description..................................................................................................................1134
4.15.11 X20DO4332......................................................................................................................................1138
4.15.11.1 General information.................................................................................................................... 1138
4.15.11.2 Order data.................................................................................................................................. 1138
4.15.11.3 Technical data............................................................................................................................ 1138
4.15.11.4 Status LEDs............................................................................................................................... 1140
4.15.11.5 Pinout..........................................................................................................................................1140
4.15.11.6 Connection example...................................................................................................................1141
4.15.11.7 OSP hardware requirements......................................................................................................1141
4.15.11.8 Output circuit diagram................................................................................................................ 1141

22 X20 system User's Manual 3.10

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4.15.11.9 Switching inductive loads (Rev. H0 and higher)........................................................................ 1142

4.15.11.10 Operation with 2 A................................................................................................................... 1143
4.15.11.11 Derating.................................................................................................................................... 1143
4.15.11.12 Register description..................................................................................................................1144
4.15.12 X20DO4529..................................................................................................................................... 1148
4.15.12.1 General information....................................................................................................................1148
4.15.12.2 Order data.................................................................................................................................. 1148
4.15.12.3 Technical data............................................................................................................................1148
4.15.12.4 Status LEDs............................................................................................................................... 1150
4.15.12.5 Pinout......................................................................................................................................... 1150
4.15.12.6 Connection example.................................................................................................................. 1150
4.15.12.7 Output circuit diagram................................................................................................................1151
4.15.12.8 Maximum switching power.........................................................................................................1151
4.15.12.9 Electrical service life.................................................................................................................. 1151
4.15.12.10 Register description................................................................................................................. 1152
4.15.13 X20DO4613..................................................................................................................................... 1154
4.15.13.1 General information....................................................................................................................1154
4.15.13.2 Order data.................................................................................................................................. 1154
4.15.13.3 Technical data............................................................................................................................1155
4.15.13.4 Status LEDs............................................................................................................................... 1156
4.15.13.5 Pinout......................................................................................................................................... 1156
4.15.13.6 Connection example.................................................................................................................. 1157
4.15.13.7 Output circuit diagram................................................................................................................1157
4.15.13.8 Operating principle..................................................................................................................... 1158
4.15.13.9 Operation with inductive loads...................................................................................................1158
4.15.13.10 Register description................................................................................................................. 1159
4.15.14 X20DO4623..................................................................................................................................... 1167
4.15.14.1 General information....................................................................................................................1167
4.15.14.2 Order data.................................................................................................................................. 1167
4.15.14.3 Technical data............................................................................................................................1168
4.15.14.4 Status LEDs............................................................................................................................... 1169
4.15.14.5 Pinout......................................................................................................................................... 1169
4.15.14.6 Connection example.................................................................................................................. 1170
4.15.14.7 Output circuit diagram................................................................................................................1170
4.15.14.8 Integrated full-wave control........................................................................................................1171
4.15.14.9 Register description................................................................................................................... 1172
4.15.15 X20DO4633..................................................................................................................................... 1175
4.15.15.1 General information....................................................................................................................1175
4.15.15.2 Order data.................................................................................................................................. 1175
4.15.15.3 Technical data............................................................................................................................1176
4.15.15.4 Status LEDs............................................................................................................................... 1177
4.15.15.5 Pinout......................................................................................................................................... 1177
4.15.15.6 Connection example.................................................................................................................. 1178
4.15.15.7 OSP hardware requirements..................................................................................................... 1178
4.15.15.8 Output circuit diagram................................................................................................................1178
4.15.15.9 External fuses............................................................................................................................ 1178
4.15.15.10 Derating.................................................................................................................................... 1179
4.15.15.11 Operating principle................................................................................................................... 1179
4.15.15.12 Open line detection.................................................................................................................. 1179
4.15.15.13 Operation with inductive loads.................................................................................................1180
4.15.15.14 Register description................................................................................................................. 1181
4.15.16 X20DO4649..................................................................................................................................... 1190
4.15.16.1 General information....................................................................................................................1190
4.15.16.2 Order data.................................................................................................................................. 1190
4.15.16.3 Technical data............................................................................................................................1190
4.15.16.4 Status LEDs............................................................................................................................... 1192
4.15.16.5 Pinout......................................................................................................................................... 1192

X20 system User's Manual 3.10 23

Table of contents

4.15.16.6 Connection example.................................................................................................................. 1192

4.15.16.7 Output circuit diagram................................................................................................................1193
4.15.16.8 Electrical service life.................................................................................................................. 1193
4.15.16.9 Register description................................................................................................................... 1194
4.15.17 X20DO6321..................................................................................................................................... 1196
4.15.17.1 General information....................................................................................................................1196
4.15.17.2 Order data.................................................................................................................................. 1196
4.15.17.3 Technical data............................................................................................................................1196
4.15.17.4 Status LEDs............................................................................................................................... 1198
4.15.17.5 Pinout......................................................................................................................................... 1198
4.15.17.6 Connection example.................................................................................................................. 1198
4.15.17.7 Output circuit diagram................................................................................................................1199
4.15.17.8 Switching inductive loads...........................................................................................................1199
4.15.17.9 Register description................................................................................................................... 1200
4.15.18 X20DO6322..................................................................................................................................... 1202
4.15.18.1 General information....................................................................................................................1202
4.15.18.2 Order data.................................................................................................................................. 1202
4.15.18.3 Technical data............................................................................................................................1202
4.15.18.4 Status LEDs............................................................................................................................... 1204
4.15.18.5 Pinout......................................................................................................................................... 1204
4.15.18.6 Connection example.................................................................................................................. 1204
4.15.18.7 OSP hardware requirements..................................................................................................... 1205
4.15.18.8 Output circuit diagram................................................................................................................1205
4.15.18.9 Switching inductive loads...........................................................................................................1205
4.15.18.10 Register description................................................................................................................. 1206
4.15.19 X20DO6325..................................................................................................................................... 1210
4.15.19.1 General information....................................................................................................................1210
4.15.19.2 Order data.................................................................................................................................. 1210
4.15.19.3 Technical data............................................................................................................................1210
4.15.19.4 LED status indicators................................................................................................................. 1212
4.15.19.5 Pinout......................................................................................................................................... 1212
4.15.19.6 Connection example.................................................................................................................. 1213
4.15.19.7 OSP hardware requirements..................................................................................................... 1213
4.15.19.8 Output circuit diagram................................................................................................................1213
4.15.19.9 Open line detection.................................................................................................................... 1214
4.15.19.10 Switching inductive loads.........................................................................................................1214
4.15.19.11 Register description..................................................................................................................1215
4.15.20 X20DO6529..................................................................................................................................... 1222
4.15.20.1 General information....................................................................................................................1222
4.15.20.2 Order data.................................................................................................................................. 1222
4.15.20.3 Technical data............................................................................................................................1222
4.15.20.4 Status LEDs............................................................................................................................... 1224
4.15.20.5 Pinout......................................................................................................................................... 1224
4.15.20.6 Connection example.................................................................................................................. 1224
4.15.20.7 Output circuit diagram................................................................................................................1225
4.15.20.8 Maximum switching power.........................................................................................................1225
4.15.20.9 Electrical service life.................................................................................................................. 1225
4.15.20.10 Register description................................................................................................................. 1226
4.15.21 X20DO6639..................................................................................................................................... 1228
4.15.21.1 General information....................................................................................................................1228
4.15.21.2 Order data.................................................................................................................................. 1228
4.15.21.3 Technical data............................................................................................................................1228
4.15.21.4 Status LEDs............................................................................................................................... 1230
4.15.21.5 Pinout......................................................................................................................................... 1230
4.15.21.6 Connection example.................................................................................................................. 1230
4.15.21.7 Output circuit diagram................................................................................................................1231
4.15.21.8 Electrical service life.................................................................................................................. 1231

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4.15.21.9 Register description................................................................................................................... 1232

4.15.22 X20DO8232..................................................................................................................................... 1234
4.15.22.1 General information....................................................................................................................1234
4.15.22.2 Order data.................................................................................................................................. 1234
4.15.22.3 Technical data............................................................................................................................1234
4.15.22.4 Status LEDs............................................................................................................................... 1236
4.15.22.5 Pinout......................................................................................................................................... 1236
4.15.22.6 Connection example.................................................................................................................. 1236
4.15.22.7 Output circuit diagram................................................................................................................1237
4.15.22.8 Switching inductive loads...........................................................................................................1237
4.15.22.9 Operation with 2 A..................................................................................................................... 1239
4.15.22.10 Register description................................................................................................................. 1240
4.15.23 X20DO8322..................................................................................................................................... 1245
4.15.23.1 General information....................................................................................................................1245
4.15.23.2 Order data.................................................................................................................................. 1245
4.15.23.3 Technical data............................................................................................................................1245
4.15.23.4 Status LEDs............................................................................................................................... 1247
4.15.23.5 Pinout......................................................................................................................................... 1247
4.15.23.6 Connection example.................................................................................................................. 1248
4.15.23.7 Output circuit diagram................................................................................................................1248
4.15.23.8 Switching inductive loads...........................................................................................................1249
4.15.23.9 Register description................................................................................................................... 1250
4.15.24 X20DO8323..................................................................................................................................... 1252
4.15.24.1 General Information................................................................................................................... 1252
4.15.24.2 Order data.................................................................................................................................. 1252
4.15.24.3 Technical data............................................................................................................................1253
4.15.24.4 Status LEDs............................................................................................................................... 1254
4.15.24.5 Pinout......................................................................................................................................... 1254
4.15.24.6 Connection example.................................................................................................................. 1254
4.15.24.7 Output circuit diagram................................................................................................................1255
4.15.24.8 Register description................................................................................................................... 1256
4.15.25 X20DO8331..................................................................................................................................... 1260
4.15.25.1 General information....................................................................................................................1260
4.15.25.2 Order data.................................................................................................................................. 1260
4.15.25.3 Technical data............................................................................................................................1260
4.15.25.4 Status LEDs............................................................................................................................... 1262
4.15.25.5 Pinout......................................................................................................................................... 1262
4.15.25.6 Connection example.................................................................................................................. 1262
4.15.25.7 Output circuit diagram................................................................................................................1263
4.15.25.8 Switching inductive loads...........................................................................................................1263
4.15.25.9 Operation with 2 A..................................................................................................................... 1265
4.15.25.10 Register description................................................................................................................. 1266
4.15.26 X20DO8332..................................................................................................................................... 1271
4.15.26.1 General information....................................................................................................................1271
4.15.26.2 Order data.................................................................................................................................. 1271
4.15.26.3 Technical data............................................................................................................................1271
4.15.26.4 Status LEDs............................................................................................................................... 1273
4.15.26.5 Pinout......................................................................................................................................... 1273
4.15.26.6 Connection example.................................................................................................................. 1273
4.15.26.7 Output circuit diagram................................................................................................................1274
4.15.26.8 Switching inductive loads...........................................................................................................1274
4.15.26.9 Operation with 2 A..................................................................................................................... 1276
4.15.26.10 Register description................................................................................................................. 1277
4.15.27 X20DO9321..................................................................................................................................... 1282
4.15.27.1 General information....................................................................................................................1282
4.15.27.2 Order data.................................................................................................................................. 1282
4.15.27.3 Technical data............................................................................................................................1282

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4.15.27.4 Status LEDs............................................................................................................................... 1283

4.15.27.5 Pinout......................................................................................................................................... 1284
4.15.27.6 Connection example.................................................................................................................. 1284
4.15.27.7 Output circuit diagram................................................................................................................1284
4.15.27.8 Switching inductive loads...........................................................................................................1285
4.15.27.9 Register description................................................................................................................... 1286
4.15.28 X20DO9322..................................................................................................................................... 1289
4.15.28.1 General information....................................................................................................................1289
4.15.28.2 Order data.................................................................................................................................. 1289
4.15.28.3 Technical data............................................................................................................................1289
4.15.28.4 Status LEDs............................................................................................................................... 1291
4.15.28.5 Pinout......................................................................................................................................... 1291
4.15.28.6 Connection example.................................................................................................................. 1292
4.15.28.7 Output circuit diagram................................................................................................................1292
4.15.28.8 Switching inductive loads...........................................................................................................1293
4.15.28.9 Register description................................................................................................................... 1294
4.15.29 X20DOD322.....................................................................................................................................1297
4.15.29.1 General information....................................................................................................................1297
4.15.29.2 Order data.................................................................................................................................. 1297
4.15.29.3 Technical data............................................................................................................................1297
4.15.29.4 Status LEDs............................................................................................................................... 1299
4.15.29.5 Pinout......................................................................................................................................... 1299
4.15.29.6 Connection example.................................................................................................................. 1299
4.15.29.7 Output circuit diagram................................................................................................................1300
4.15.29.8 Switching inductive loads...........................................................................................................1300
4.15.29.9 Register description................................................................................................................... 1301
4.15.30 X20DOF322..................................................................................................................................... 1303
4.15.30.1 General information....................................................................................................................1303
4.15.30.2 Order data.................................................................................................................................. 1303
4.15.30.3 Technical data............................................................................................................................1303
4.15.30.4 Status LEDs............................................................................................................................... 1305
4.15.30.5 Pinout......................................................................................................................................... 1305
4.15.30.6 Connection example.................................................................................................................. 1306
4.15.30.7 Output circuit diagram................................................................................................................1306
4.15.30.8 Switching inductive loads...........................................................................................................1307
4.15.30.9 Register description................................................................................................................... 1308
4.16 Digital signal processing modules.......................................................................................................... 1311
4.16.1 Brief information.................................................................................................................................1311
4.16.2 X20CM1201....................................................................................................................................... 1312
4.16.2.1 General information......................................................................................................................1312
4.16.2.2 Order data.................................................................................................................................... 1312
4.16.2.3 Technical data..............................................................................................................................1313
4.16.2.4 LED status indicators................................................................................................................... 1314
4.16.2.5 Pinout........................................................................................................................................... 1315
4.16.2.6 Connection example.................................................................................................................... 1315
4.16.2.7 Input circuit diagram.................................................................................................................... 1315
4.16.2.8 Output circuit diagram..................................................................................................................1316
4.16.2.9 Switching inductive loads.............................................................................................................1316
4.16.2.10 Register description................................................................................................................... 1317
4.16.3 X20DC1073....................................................................................................................................... 1332
4.16.3.1 General information......................................................................................................................1332
4.16.3.2 Order data.................................................................................................................................... 1332
4.16.3.3 Technical data..............................................................................................................................1333
4.16.3.4 LED status indicators................................................................................................................... 1334
4.16.3.5 Pinout........................................................................................................................................... 1334
4.16.3.6 Connection example.................................................................................................................... 1335
4.16.3.7 Analog inputs - Input circuit diagram...........................................................................................1335

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4.16.3.8 Circuit diagram for the encoder supply and LEDs.......................................................................1335

4.16.3.9 Calculating the maximum encoder cable length..........................................................................1336
4.16.4 X20DS1828........................................................................................................................................1337
4.16.4.1 General information......................................................................................................................1337
4.16.4.2 Order data.................................................................................................................................... 1337
4.16.4.3 Technical data..............................................................................................................................1337
4.16.4.4 LED status indicators................................................................................................................... 1339
4.16.4.5 Pinout........................................................................................................................................... 1339
4.16.4.6 Connection example.................................................................................................................... 1340
4.16.4.7 Input diagram for the process data channel (sine-cosine track)..................................................1340
4.16.4.8 Circuit diagram for the parameter channel (RS485 interface)..................................................... 1340
4.16.4.9 Circuit diagram for the encoder supply and LEDs.......................................................................1340
4.16.4.10 Register description................................................................................................................... 1341
4.16.5 X20DS1928........................................................................................................................................1399
4.16.5.1 General information......................................................................................................................1399
4.16.5.2 Order data.................................................................................................................................... 1399
4.16.5.3 Technical data..............................................................................................................................1399
4.16.5.4 Status LEDs................................................................................................................................. 1400
4.16.5.5 Pinout........................................................................................................................................... 1401
4.16.5.6 Connection example.................................................................................................................... 1401
4.16.5.7 Input diagram for the incremental signals (sine-cosine track)..................................................... 1402
4.16.5.8 Input diagram for the serial EnDat interface................................................................................1402
4.16.5.9 Encoder supply scheme and LEDs............................................................................................. 1402
4.16.5.10 Register description................................................................................................................... 1403
4.17 Dummy modules..................................................................................................................................... 1453
4.17.1 Brief information.................................................................................................................................1453
4.17.2 X20IF0000......................................................................................................................................... 1453
4.17.2.1 General information......................................................................................................................1453
4.17.2.2 Order data.................................................................................................................................... 1453
4.17.2.3 Technical data..............................................................................................................................1453
4.17.3 X20ZF0000........................................................................................................................................ 1455
4.17.3.1 General information......................................................................................................................1455
4.17.3.2 Order data.................................................................................................................................... 1455
4.17.3.3 Technical data..............................................................................................................................1456
4.17.3.4 Pinout........................................................................................................................................... 1457
4.17.3.5 Connection example.................................................................................................................... 1457
4.17.4 X20ZF000F........................................................................................................................................ 1457
4.17.4.1 General information......................................................................................................................1457
4.17.4.2 Order data.................................................................................................................................... 1458
4.17.4.3 Technical data..............................................................................................................................1458
4.17.4.4 Pinout........................................................................................................................................... 1459
4.17.4.5 Connection example.................................................................................................................... 1459
4.18 X20 electronics module communication................................................................................................. 1460
4.18.1 Brief information.................................................................................................................................1460
4.18.2 X20CS1011........................................................................................................................................ 1461
4.18.2.1 General information......................................................................................................................1461
4.18.2.2 Order data.................................................................................................................................... 1461
4.18.2.3 Technical data..............................................................................................................................1462
4.18.2.4 LED status indicators................................................................................................................... 1463
4.18.2.5 Pinout........................................................................................................................................... 1464
4.18.2.6 Connection example.................................................................................................................... 1464
4.18.2.7 Configuration button.....................................................................................................................1464
4.18.2.8 Register description..................................................................................................................... 1465
4.18.3 X20CS1012........................................................................................................................................1476
4.18.3.1 General information......................................................................................................................1476
4.18.3.2 Order data.................................................................................................................................... 1476
4.18.3.3 Technical data..............................................................................................................................1477

X20 system User's Manual 3.10 27

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4.18.3.4 LED status indicators................................................................................................................... 1478

4.18.3.5 Pinout........................................................................................................................................... 1478
4.18.3.6 Connection example.................................................................................................................... 1478
4.18.3.7 M-Bus........................................................................................................................................... 1479
4.18.3.8 Register description..................................................................................................................... 1481
4.18.4 X20CS1013........................................................................................................................................1524
4.18.4.1 General information......................................................................................................................1524
4.18.4.2 Order data.................................................................................................................................... 1524
4.18.4.3 Technical data..............................................................................................................................1525
4.18.4.4 LED status indicators................................................................................................................... 1526
4.18.4.5 Pinout........................................................................................................................................... 1526
4.18.4.6 Using an external power supply.................................................................................................. 1526
4.18.4.7 Register description..................................................................................................................... 1527
4.18.5 X20CS1020........................................................................................................................................1533
4.18.5.1 General information......................................................................................................................1533
4.18.5.2 Order data.................................................................................................................................... 1533
4.18.5.3 Technical data..............................................................................................................................1534
4.18.5.4 LED status indicators................................................................................................................... 1535
4.18.5.5 Pinout........................................................................................................................................... 1535
4.18.5.6 Register description..................................................................................................................... 1536
4.18.6 X20CS1030........................................................................................................................................1575
4.18.6.1 General information......................................................................................................................1575
4.18.6.2 Order data.................................................................................................................................... 1575
4.18.6.3 Technical data..............................................................................................................................1576
4.18.6.4 LED status indicators................................................................................................................... 1577
4.18.6.5 Pinout........................................................................................................................................... 1577
4.18.6.6 Terminating resistor..................................................................................................................... 1578
4.18.6.7 Register description..................................................................................................................... 1579
4.18.7 X20CS1070........................................................................................................................................1617
4.18.7.1 General information......................................................................................................................1617
4.18.7.2 Order data.................................................................................................................................... 1617
4.18.7.3 Technical data..............................................................................................................................1618
4.18.7.4 LED status indicators................................................................................................................... 1619
4.18.7.5 Pinout........................................................................................................................................... 1619
4.18.7.6 Terminating resistor..................................................................................................................... 1619
4.18.7.7 Register description..................................................................................................................... 1620
4.18.8 X20CS2770........................................................................................................................................1662
4.18.8.1 General information......................................................................................................................1662
4.18.8.2 Order data.................................................................................................................................... 1662
4.18.8.3 Technical data..............................................................................................................................1663
4.18.8.4 LED status indicators................................................................................................................... 1664
4.18.8.5 Pinout........................................................................................................................................... 1664
4.18.8.6 Terminating resistors....................................................................................................................1664
4.18.8.7 Register description..................................................................................................................... 1665
4.19 Expandable bus controllers.....................................................................................................................1706
4.19.1 Brief information.................................................................................................................................1706
4.19.2 X20BC1083........................................................................................................................................1707
4.19.2.1 General information......................................................................................................................1707
4.19.2.2 Order data.................................................................................................................................... 1708
4.19.2.3 Technical data..............................................................................................................................1709
4.19.2.4 LED status indicators................................................................................................................... 1710
4.19.2.5 Operating and connection elements............................................................................................ 1711
4.19.2.6 POWERLINK node number......................................................................................................... 1711
4.19.2.7 Ethernet interface.........................................................................................................................1711
4.19.2.8 Slot for interface modules............................................................................................................1712
4.19.2.9 Operating netX modules with the X20BC1083 bus controller..................................................... 1712
4.19.2.10 SG3............................................................................................................................................ 1712

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4.19.2.11 SG4.............................................................................................................................................1712
4.19.3 X20BC8083........................................................................................................................................1713
4.19.3.1 General information......................................................................................................................1713
4.19.3.2 Order data.................................................................................................................................... 1713
4.19.3.3 Technical data..............................................................................................................................1714
4.19.3.4 LED status indicators................................................................................................................... 1715
4.19.3.5 Operating and connection elements............................................................................................ 1716
4.19.3.6 POWERLINK station number.......................................................................................................1716
4.19.3.7 Ethernet interface.........................................................................................................................1716
4.19.3.8 Slot for hub expansion modules.................................................................................................. 1716
4.19.3.9 SG3.............................................................................................................................................. 1717
4.19.3.10 SG4............................................................................................................................................ 1717
4.19.4 X20BC8084........................................................................................................................................1718
4.19.4.1 General information......................................................................................................................1718
4.19.4.2 Order data.................................................................................................................................... 1718
4.19.4.3 Technical data..............................................................................................................................1719
4.19.4.4 LED status indicators................................................................................................................... 1720
4.19.4.5 Operating and connection elements............................................................................................ 1721
4.19.4.6 POWERLINK station number.......................................................................................................1721
4.19.4.7 Ethernet interface.........................................................................................................................1721
4.19.4.8 SG3.............................................................................................................................................. 1721
4.19.4.9 SG4.............................................................................................................................................. 1722
4.19.4.10 POWERLINK cable redundancy system................................................................................... 1723
4.19.4.11 Redundant supply voltage..........................................................................................................1730
4.19.5 X20BC80G3.......................................................................................................................................1732
4.19.5.1 General information......................................................................................................................1732
4.19.5.2 Order data.................................................................................................................................... 1733
4.19.5.3 Technical data..............................................................................................................................1733
4.19.5.4 LED status indicators................................................................................................................... 1734
4.19.5.5 Operating and connection elements............................................................................................ 1735
4.19.5.6 RJ45 ports....................................................................................................................................1735
4.19.5.7 EtherCAT network address switch...............................................................................................1736
4.19.5.8 Slot............................................................................................................................................... 1736
4.20 Expandable bus controllers System modules.........................................................................................1737
4.20.1 Brief information.................................................................................................................................1737
4.20.2 X20BB81............................................................................................................................................1738
4.20.2.1 General information......................................................................................................................1738
4.20.2.2 Order data.................................................................................................................................... 1738
4.20.2.3 Technical data..............................................................................................................................1738
4.20.2.4 Voltage routing............................................................................................................................. 1739
4.20.3 X20BB82............................................................................................................................................1740
4.20.3.1 General information......................................................................................................................1740
4.20.3.2 Order data.................................................................................................................................... 1740
4.20.3.3 Technical data..............................................................................................................................1740
4.20.3.4 Voltage routing............................................................................................................................. 1741
4.20.4 X20IF1091-1...................................................................................................................................... 1742
4.20.4.1 General information......................................................................................................................1742
4.20.4.2 Order data.................................................................................................................................... 1742
4.20.4.3 Technical data..............................................................................................................................1743
4.20.4.4 Use with POWERLINK bus controllers........................................................................................1743
4.20.4.5 LED status indicators................................................................................................................... 1744
4.20.4.6 Operating and connection elements............................................................................................ 1744
4.20.4.7 X2X Link interface (IF1)...............................................................................................................1744
4.20.4.8 Firmware.......................................................................................................................................1744
4.21 Fieldbus CPUs........................................................................................................................................ 1745
4.21.1 Brief information.................................................................................................................................1746
4.21.2 X20XC0201, X20XC0202, X20XC0292............................................................................................ 1747

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4.21.2.1 General information......................................................................................................................1747

4.21.2.2 Order data.................................................................................................................................... 1748
4.21.2.3 Technical data..............................................................................................................................1749
4.21.2.4 LED status indicators................................................................................................................... 1750
4.21.2.5 Operating and connection elements............................................................................................ 1751
4.21.2.6 Node number switches................................................................................................................ 1752
4.21.2.7 Ethernet interface (IF2)................................................................................................................ 1753
4.21.2.8 Slot for fieldbus modules............................................................................................................. 1753
4.21.2.9 Programming the system flash memory...................................................................................... 1754
4.22 Fieldbus CPUs System modules............................................................................................................ 1755
4.22.1 Brief information.................................................................................................................................1755
4.22.2 X20BB32............................................................................................................................................1756
4.22.2.1 General information......................................................................................................................1756
4.22.2.2 Order data.................................................................................................................................... 1756
4.22.2.3 Technical data..............................................................................................................................1756
4.22.2.4 Voltage routing............................................................................................................................. 1757
4.22.3 X20BB37............................................................................................................................................1758
4.22.3.1 General information......................................................................................................................1758
4.22.3.2 Order data.................................................................................................................................... 1758
4.22.3.3 Technical data..............................................................................................................................1758
4.22.3.4 Voltage routing............................................................................................................................. 1759
4.22.3.5 Terminating resistor for CAN bus................................................................................................ 1759
4.22.4 X20BB42............................................................................................................................................1760
4.22.4.1 General information......................................................................................................................1760
4.22.4.2 Order data.................................................................................................................................... 1760
4.22.4.3 Technical data..............................................................................................................................1760
4.22.4.4 Voltage routing............................................................................................................................. 1761
4.22.5 X20BB47............................................................................................................................................1762
4.22.5.1 General information......................................................................................................................1762
4.22.5.2 Order data.................................................................................................................................... 1762
4.22.5.3 Technical data..............................................................................................................................1762
4.22.5.4 Voltage routing............................................................................................................................. 1763
4.22.5.5 Terminating resistor for CAN bus................................................................................................ 1763
4.22.6 X20IF1074......................................................................................................................................... 1764
4.22.6.1 General information......................................................................................................................1764
4.22.6.2 Order data.................................................................................................................................... 1764
4.22.6.3 Technical data..............................................................................................................................1765
4.22.6.4 LED status indicators................................................................................................................... 1766
4.22.6.5 Operating and connection elements............................................................................................ 1766
4.22.6.6 Node number switch.................................................................................................................... 1766
4.22.6.7 CAN bus interface........................................................................................................................1767
4.22.6.8 Terminating resistor..................................................................................................................... 1767
4.22.6.9 Firmware.......................................................................................................................................1767
4.23 X20 interface module communication.....................................................................................................1768
4.23.1 Brief information.................................................................................................................................1768
4.23.2 X20IF1020......................................................................................................................................... 1769
4.23.2.1 General information......................................................................................................................1769
4.23.2.2 Order data.................................................................................................................................... 1769
4.23.2.3 Technical data..............................................................................................................................1770
4.23.2.4 LED status indicators................................................................................................................... 1771
4.23.2.5 Operating and connection elements............................................................................................ 1771
4.23.2.6 RS232 interface (IF1).................................................................................................................. 1771
4.23.2.7 Firmware.......................................................................................................................................1771
4.23.3 X20IF1030......................................................................................................................................... 1772
4.23.3.1 General information......................................................................................................................1772
4.23.3.2 Order data.................................................................................................................................... 1772
4.23.3.3 Technical data..............................................................................................................................1773

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4.23.3.4 LED status indicators................................................................................................................... 1774

4.23.3.5 Operating and connection elements............................................................................................ 1774
4.23.3.6 RS485/RS422 interface (IF1).......................................................................................................1774
4.23.3.7 Firmware.......................................................................................................................................1774
4.23.4 X20IF1041-1...................................................................................................................................... 1775
4.23.4.1 General information......................................................................................................................1775
4.23.4.2 Order data.................................................................................................................................... 1775
4.23.4.3 Technical data..............................................................................................................................1776
4.23.4.4 LED status indicators................................................................................................................... 1777
4.23.4.5 Operating and connection elements............................................................................................ 1777
4.23.4.6 CAN bus interface........................................................................................................................1778
4.23.4.7 Terminating resistor..................................................................................................................... 1778
4.23.4.8 Use with POWERLINK bus controllers........................................................................................1778
4.23.4.9 Firmware.......................................................................................................................................1778
4.23.5 X20IF1043-1...................................................................................................................................... 1779
4.23.5.1 General information......................................................................................................................1779
4.23.5.2 Order data.................................................................................................................................... 1779
4.23.5.3 Technical data..............................................................................................................................1780
4.23.5.4 LED status indicators................................................................................................................... 1781
4.23.5.5 Operating and connection elements............................................................................................ 1781
4.23.5.6 CAN bus interface........................................................................................................................1782
4.23.5.7 Terminating resistor..................................................................................................................... 1782
4.23.5.8 Use with POWERLINK bus controllers........................................................................................1782
4.23.5.9 Firmware.......................................................................................................................................1782
4.23.6 X20IF1051-1...................................................................................................................................... 1783
4.23.6.1 General information......................................................................................................................1783
4.23.6.2 Order data.................................................................................................................................... 1783
4.23.6.3 Technical data..............................................................................................................................1784
4.23.6.4 LED status indicators................................................................................................................... 1785
4.23.6.5 Operating and connection elements............................................................................................ 1785
4.23.6.6 DeviceNet interface......................................................................................................................1786
4.23.6.7 Terminating resistor..................................................................................................................... 1786
4.23.6.8 Use with POWERLINK bus controllers........................................................................................1786
4.23.6.9 Firmware.......................................................................................................................................1786
4.23.7 X20IF1053-1...................................................................................................................................... 1787
4.23.7.1 General information......................................................................................................................1787
4.23.7.2 Order data.................................................................................................................................... 1787
4.23.7.3 Technical data..............................................................................................................................1788
4.23.7.4 LED status indicators................................................................................................................... 1788
4.23.7.5 Operating and connection elements............................................................................................ 1789
4.23.7.6 DeviceNet interface......................................................................................................................1790
4.23.7.7 Terminating resistor..................................................................................................................... 1790
4.23.7.8 Use with POWERLINK bus controllers........................................................................................1790
4.23.7.9 Firmware.......................................................................................................................................1790
4.23.8 X20IF1061......................................................................................................................................... 1791
4.23.8.1 General information......................................................................................................................1791
4.23.8.2 Order data.................................................................................................................................... 1791
4.23.8.3 Technical data..............................................................................................................................1792
4.23.8.4 LED status indicators................................................................................................................... 1793
4.23.8.5 Operating and connection elements............................................................................................ 1793
4.23.8.6 PROFIBUS DP interface..............................................................................................................1793
4.23.8.7 Firmware.......................................................................................................................................1793
4.23.9 X20IF1061-1...................................................................................................................................... 1794
4.23.9.1 General information......................................................................................................................1794
4.23.9.2 Order data.................................................................................................................................... 1794
4.23.9.3 Technical data..............................................................................................................................1795
4.23.9.4 LED status indicators................................................................................................................... 1796

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4.23.9.5 Operating and connection elements............................................................................................ 1796

4.23.9.6 PROFIBUS DP interface..............................................................................................................1796
4.23.9.7 Use with POWERLINK bus controllers........................................................................................1797
4.23.9.8 Firmware.......................................................................................................................................1797
4.23.10 X20IF1063....................................................................................................................................... 1798
4.23.10.1 General information....................................................................................................................1798
4.23.10.2 Order data.................................................................................................................................. 1798
4.23.10.3 Technical data............................................................................................................................1799
4.23.10.4 LED status indicators................................................................................................................. 1799
4.23.10.5 Operating and connection elements.......................................................................................... 1800
4.23.10.6 Node number switch.................................................................................................................. 1800
4.23.10.7 PROFIBUS DP interface............................................................................................................1800
4.23.10.8 Firmware.....................................................................................................................................1800
4.23.11 X20IF1063-1.....................................................................................................................................1801
4.23.11.1 General information.................................................................................................................... 1801
4.23.11.2 Order data.................................................................................................................................. 1801
4.23.11.3 Technical data............................................................................................................................ 1802
4.23.11.4 LED status indicators................................................................................................................. 1803
4.23.11.5 Operating and connection elements.......................................................................................... 1803
4.23.11.6 PROFIBUS DP interface............................................................................................................ 1803
4.23.11.7 Use with POWERLINK bus controllers...................................................................................... 1804
4.23.11.8 Firmware.....................................................................................................................................1804
4.23.12 X20IF1065....................................................................................................................................... 1805
4.23.12.1 General information....................................................................................................................1805
4.23.12.2 Order data.................................................................................................................................. 1805
4.23.12.3 Technical data............................................................................................................................1806
4.23.12.4 LED status indicators................................................................................................................. 1807
4.23.12.5 Operating and connection elements.......................................................................................... 1807
4.23.12.6 PROFIBUS DP interface............................................................................................................1807
4.23.12.7 Firmware.....................................................................................................................................1807
4.23.13 X20IF1072....................................................................................................................................... 1808
4.23.13.1 General information....................................................................................................................1808
4.23.13.2 Order data.................................................................................................................................. 1808
4.23.13.3 Technical data............................................................................................................................1809
4.23.13.4 LED status indicators................................................................................................................. 1810
4.23.13.5 Operating and connection elements.......................................................................................... 1810
4.23.13.6 Node number switch.................................................................................................................. 1810
4.23.13.7 CAN bus interface......................................................................................................................1811
4.23.13.8 Terminating resistor................................................................................................................... 1811
4.23.13.9 Firmware.....................................................................................................................................1811
4.23.14 X20IF1082....................................................................................................................................... 1812
4.23.14.1 General information....................................................................................................................1812
4.23.14.2 Order data.................................................................................................................................. 1812
4.23.14.3 Technical data............................................................................................................................1813
4.23.14.4 LED status indicators................................................................................................................. 1814
4.23.14.5 Operating and connection elements.......................................................................................... 1816
4.23.14.6 POWERLINK station number.....................................................................................................1816
4.23.14.7 RJ45 ports..................................................................................................................................1817
4.23.14.8 Firmware.....................................................................................................................................1817
4.23.15 X20IF1082-2.................................................................................................................................... 1818
4.23.15.1 General information....................................................................................................................1818
4.23.15.2 Order data.................................................................................................................................. 1818
4.23.15.3 Technical data............................................................................................................................1819
4.23.15.4 LED status indicators................................................................................................................. 1820
4.23.15.5 Operating and connection elements.......................................................................................... 1822
4.23.15.6 POWERLINK station number.....................................................................................................1822
4.23.15.7 RJ45 ports..................................................................................................................................1823

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4.23.15.8 Firmware.....................................................................................................................................1823
4.23.16 X20IF1086-2.................................................................................................................................... 1824
4.23.16.1 General information....................................................................................................................1824
4.23.16.2 Order data.................................................................................................................................. 1824
4.23.16.3 Technical data............................................................................................................................1825
4.23.16.4 LED status indicators................................................................................................................. 1826
4.23.16.5 "S/E" LED...................................................................................................................................1826
4.23.16.6 Operating and connection elements.......................................................................................... 1828
4.23.16.7 POWERLINK station number.....................................................................................................1828
4.23.16.8 Duplex LC port...........................................................................................................................1829
4.23.16.9 Firmware.....................................................................................................................................1829
4.23.16.10 Wiring guidelines for X20 modules with fiber optic cable........................................................ 1829
4.23.17 X20IF1091....................................................................................................................................... 1830
4.23.17.1 General information....................................................................................................................1830
4.23.17.2 Order data.................................................................................................................................. 1830
4.23.17.3 Technical data............................................................................................................................1831
4.23.17.4 LED status indicators................................................................................................................. 1832
4.23.17.5 Operating and connection elements.......................................................................................... 1832
4.23.17.6 X2X Link interface (IF1).............................................................................................................1832
4.23.17.7 Firmware.....................................................................................................................................1832
4.23.18 X20IF10A1-1....................................................................................................................................1833
4.23.18.1 General information....................................................................................................................1833
4.23.18.2 Order data.................................................................................................................................. 1833
4.23.18.3 Technical data............................................................................................................................1834
4.23.18.4 LED status indicators................................................................................................................. 1835
4.23.18.5 Operating and connection elements.......................................................................................... 1835
4.23.18.6 AS-interface (IF1).......................................................................................................................1835
4.23.18.7 Use with POWERLINK bus controllers......................................................................................1836
4.23.18.8 Firmware.....................................................................................................................................1836
4.23.19 X20IF10D1-1....................................................................................................................................1837
4.23.19.1 General information....................................................................................................................1837
4.23.19.2 Order data.................................................................................................................................. 1837
4.23.19.3 Technical data............................................................................................................................1838
4.23.19.4 LED status indicators................................................................................................................. 1839
4.23.19.5 Operating and connection elements.......................................................................................... 1839
4.23.19.6 Ethernet interface.......................................................................................................................1840
4.23.19.7 Use with POWERLINK bus controllers......................................................................................1840
4.23.19.8 Firmware.....................................................................................................................................1840
4.23.20 X20IF10D3-1....................................................................................................................................1841
4.23.20.1 General information....................................................................................................................1841
4.23.20.2 Order data.................................................................................................................................. 1841
4.23.20.3 Technical data............................................................................................................................1842
4.23.20.4 LED status indicators................................................................................................................. 1843
4.23.20.5 Operating and connection elements.......................................................................................... 1843
4.23.20.6 Ethernet interface.......................................................................................................................1844
4.23.20.7 Use with POWERLINK bus controllers......................................................................................1844
4.23.20.8 Firmware.....................................................................................................................................1844
4.23.21 X20IF10E1-1....................................................................................................................................1845
4.23.21.1 General information....................................................................................................................1845
4.23.21.2 Order data.................................................................................................................................. 1845
4.23.21.3 Technical data............................................................................................................................1846
4.23.21.4 LED status indicators................................................................................................................. 1847
4.23.21.5 Operating and connection elements.......................................................................................... 1847
4.23.21.6 Ethernet interface.......................................................................................................................1848
4.23.21.7 Use with POWERLINK bus controllers......................................................................................1848
4.23.21.8 Firmware.....................................................................................................................................1848
4.23.22 X20IF10E3-1....................................................................................................................................1849

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4.23.22.1 General information....................................................................................................................1849

4.23.22.2 Order data.................................................................................................................................. 1849
4.23.22.3 Technical data............................................................................................................................1850
4.23.22.4 LED status indicators................................................................................................................. 1851
4.23.22.5 Operating and connection elements.......................................................................................... 1851
4.23.22.6 Ethernet interface.......................................................................................................................1851
4.23.22.7 Use with POWERLINK bus controllers......................................................................................1852
4.23.22.8 Firmware.....................................................................................................................................1852
4.23.22.9 Recognizing an invalid connection............................................................................................ 1852
4.23.23 X20IF10G3-1................................................................................................................................... 1853
4.23.23.1 General information....................................................................................................................1853
4.23.23.2 Order data.................................................................................................................................. 1853
4.23.23.3 Technical data............................................................................................................................1854
4.23.23.4 LED status indicators................................................................................................................. 1855
4.23.23.5 Operating and connection elements.......................................................................................... 1855
4.23.23.6 Ethernet interface.......................................................................................................................1856
4.23.23.7 Use with POWERLINK bus controllers......................................................................................1856
4.23.23.8 Firmware.....................................................................................................................................1856
4.23.24 X20IF10X0....................................................................................................................................... 1857
4.23.24.1 General information....................................................................................................................1857
4.23.24.2 Order data.................................................................................................................................. 1857
4.23.24.3 Technical data............................................................................................................................1857
4.23.24.4 LED status indicators................................................................................................................. 1858
4.23.24.5 Operating and connection elements.......................................................................................... 1858
4.23.24.6 Switch positions......................................................................................................................... 1859
4.23.24.7 Firmware.....................................................................................................................................1859
4.23.25 X20IF2181-2.................................................................................................................................... 1860
4.23.25.1 General information....................................................................................................................1860
4.23.25.2 Order data.................................................................................................................................. 1860
4.23.25.3 Technical data............................................................................................................................1860
4.23.25.4 LED status indicators................................................................................................................. 1861
4.23.25.5 Operating and connection elements.......................................................................................... 1864
4.23.25.6 POWERLINK station number.....................................................................................................1864
4.23.25.7 RJ45 ports..................................................................................................................................1864
4.23.25.8 Firmware.....................................................................................................................................1865
4.23.25.9 POWERLINK cable redundancy system................................................................................... 1866
4.23.26 X20IF2772....................................................................................................................................... 1874
4.23.26.1 General information....................................................................................................................1874
4.23.26.2 Order data.................................................................................................................................. 1874
4.23.26.3 Technical data............................................................................................................................1875
4.23.26.4 LED status indicators................................................................................................................. 1876
4.23.26.5 Operating and connection elements.......................................................................................... 1876
4.23.26.6 CAN bus node number.............................................................................................................. 1876
4.23.26.7 Interfaces CAN bus 1 and CAN bus 2 (IF1 and IF2)................................................................ 1877
4.23.26.8 Terminating resistor................................................................................................................... 1877
4.23.26.9 Firmware.....................................................................................................................................1877
4.23.27 X20IF2792....................................................................................................................................... 1878
4.23.27.1 General information....................................................................................................................1878
4.23.27.2 Order data.................................................................................................................................. 1878
4.23.27.3 Technical data............................................................................................................................1879
4.23.27.4 LED status indicators................................................................................................................. 1880
4.23.27.5 Operating and connection elements.......................................................................................... 1880
4.23.27.6 X2X Link interface (IF1).............................................................................................................1880
4.23.27.7 CAN bus node number.............................................................................................................. 1881
4.23.27.8 CAN bus interface......................................................................................................................1881
4.23.27.9 Terminating resistor................................................................................................................... 1881
4.23.27.10 Firmware...................................................................................................................................1881

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4.24 X20 hub system...................................................................................................................................... 1882

4.24.1 Brief information.................................................................................................................................1882
4.24.2 X20ET8819........................................................................................................................................ 1883
4.24.2.1 General information......................................................................................................................1883
4.24.2.2 Order data.................................................................................................................................... 1884
4.24.2.3 Technical data..............................................................................................................................1885
4.24.2.4 LED status indicators................................................................................................................... 1886
4.24.2.5 S/E LED....................................................................................................................................... 1886
4.24.2.6 Operating and connection elements............................................................................................ 1887
4.24.2.7 Operating mode and address switch........................................................................................... 1887
4.24.2.8 RJ45 ports....................................................................................................................................1888
4.24.2.9 Hardware configuration 1.............................................................................................................1889
4.24.2.10 Hardware configuration 2...........................................................................................................1890
4.24.2.11 Hardware configuration 3a......................................................................................................... 1891
4.24.2.12 Hardware configuration 3b.........................................................................................................1891
4.24.2.13 Firmware update........................................................................................................................ 1892
4.24.2.14 Analysis mode............................................................................................................................1893
4.24.2.15 Using trigger inputs.................................................................................................................... 1894
4.24.2.16 Using trigger outputs..................................................................................................................1895
4.24.2.17 B&R recording software............................................................................................................. 1895
4.24.3 X20HB8815........................................................................................................................................1896
4.24.3.1 General information......................................................................................................................1896
4.24.3.2 Order data.................................................................................................................................... 1897
4.24.3.3 Technical data..............................................................................................................................1898
4.24.3.4 LED status indicators................................................................................................................... 1899
4.24.3.5 Operating and connection elements............................................................................................ 1900
4.24.3.6 POWERLINK node number switches.......................................................................................... 1900
4.24.3.7 Ethernet interface.........................................................................................................................1900
4.24.3.8 Slot for hub expansion modules.................................................................................................. 1901
4.24.3.9 Usage examples.......................................................................................................................... 1901
4.24.3.10 SG3............................................................................................................................................ 1903
4.24.3.11 Firmware.....................................................................................................................................1903
4.24.3.12 MTU size.................................................................................................................................... 1903
4.24.3.13 Asynchronous send priority........................................................................................................1903
4.24.4 X20HB8880........................................................................................................................................1904
4.24.4.1 General information......................................................................................................................1904
4.24.4.2 Order data.................................................................................................................................... 1904
4.24.4.3 Technical data..............................................................................................................................1905
4.24.4.4 LED status indicators................................................................................................................... 1906
4.24.4.5 Operating and connection elements............................................................................................ 1906
4.24.4.6 Ethernet interface.........................................................................................................................1906
4.24.4.7 Slot for hub expansion modules.................................................................................................. 1907
4.24.5 X20HB88G0.......................................................................................................................................1908
4.24.5.1 General information......................................................................................................................1908
4.24.5.2 Order data.................................................................................................................................... 1908
4.24.5.3 Technical data..............................................................................................................................1909
4.24.5.4 LED status indicators................................................................................................................... 1910
4.24.5.5 Operating and connection elements............................................................................................ 1910
4.24.5.6 EtherCAT interface.......................................................................................................................1910
4.24.5.7 Network address switch............................................................................................................... 1911
4.24.5.8 Slot for EtherCAT junction module.............................................................................................. 1911
4.25 Motor controllers..................................................................................................................................... 1912
4.25.1 Brief information.................................................................................................................................1912
4.25.2 X20MM2436.......................................................................................................................................1913
4.25.2.1 General information......................................................................................................................1913
4.25.2.2 Order data.................................................................................................................................... 1913
4.25.2.3 Technical data..............................................................................................................................1913

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4.25.2.4 LED status indicators................................................................................................................... 1915

4.25.2.5 Pinout........................................................................................................................................... 1915
4.25.2.6 Connection example.................................................................................................................... 1916
4.25.2.7 Input circuit diagram.................................................................................................................... 1916
4.25.2.8 Output circuit diagram..................................................................................................................1917
4.25.2.9 Protection..................................................................................................................................... 1918
4.25.2.10 Derating...................................................................................................................................... 1918
4.25.2.11 Monitoring the module supply.................................................................................................... 1920
4.25.2.12 Overvoltage cutoff...................................................................................................................... 1920
4.25.2.13 Overtemperature cutoff (at 85°C).............................................................................................. 1920
4.25.2.14 Register description................................................................................................................... 1921
4.25.3 X20MM3332.......................................................................................................................................1930
4.25.3.1 General information......................................................................................................................1930
4.25.3.2 Order data.................................................................................................................................... 1930
4.25.3.3 Technical data..............................................................................................................................1931
4.25.3.4 LED status indicators................................................................................................................... 1932
4.25.3.5 Pinout........................................................................................................................................... 1932
4.25.3.6 Connection example.................................................................................................................... 1932
4.25.3.7 Output circuit diagram..................................................................................................................1933
4.25.3.8 Function description - Motor operation........................................................................................ 1934
4.25.3.9 Protection..................................................................................................................................... 1934
4.25.3.10 Derating...................................................................................................................................... 1935
4.25.3.11 Switching inductive loads (e.g. valves)...................................................................................... 1937
4.25.3.12 Monitoring the module supply....................................................................................................1938
4.25.3.13 Monitoring the module current................................................................................................... 1938
4.25.3.14 Channel monitoring.................................................................................................................... 1938
4.25.3.15 Overtemperature cutoff (at 85°C).............................................................................................. 1938
4.25.3.16 Register description................................................................................................................... 1939
4.25.4 X20MM4331.......................................................................................................................................1944
4.25.4.1 General information......................................................................................................................1944
4.25.4.2 Order data.................................................................................................................................... 1944
4.25.4.3 Technical data..............................................................................................................................1944
4.25.4.4 LED status indicators................................................................................................................... 1946
4.25.4.5 Pinout........................................................................................................................................... 1946
4.25.4.6 Connection example.................................................................................................................... 1946
4.25.4.7 Output circuit diagram..................................................................................................................1947
4.25.4.8 Function description - Motor operation........................................................................................ 1947
4.25.4.9 Protection..................................................................................................................................... 1948
4.25.4.10 Derating...................................................................................................................................... 1948
4.25.4.11 Switching inductive loads (e.g. valves)...................................................................................... 1950
4.25.4.12 Monitoring the module supply....................................................................................................1951
4.25.4.13 Monitoring the module current................................................................................................... 1951
4.25.4.14 Channel monitoring.................................................................................................................... 1951
4.25.4.15 Overtemperature cutoff (at 85°C).............................................................................................. 1951
4.25.4.16 Register description................................................................................................................... 1952
4.25.5 X20MM4456.......................................................................................................................................1956
4.25.5.1 General information......................................................................................................................1956
4.25.5.2 Order data.................................................................................................................................... 1956
4.25.5.3 Technical data..............................................................................................................................1957
4.25.5.4 LED status indicators................................................................................................................... 1958
4.25.5.5 Connection elements................................................................................................................... 1959
4.25.5.6 Connection examples...................................................................................................................1960
4.25.5.7 Possible uses for digital inputs.................................................................................................... 1960
4.25.5.8 Input circuit diagram.................................................................................................................... 1961
4.25.5.9 Output circuit diagram..................................................................................................................1961
4.25.5.10 Protection................................................................................................................................... 1962
4.25.5.11 Monitoring the module supply.................................................................................................... 1963

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4.25.5.12 Overvoltage cutoff...................................................................................................................... 1963

4.25.5.13 Overtemperature cutoff (at 85°C).............................................................................................. 1963
4.25.5.14 Measurement of effective current.............................................................................................. 1963
4.25.5.15 Register description................................................................................................................... 1964
4.25.6 X20SM1426....................................................................................................................................... 1976
4.25.6.1 General information......................................................................................................................1976
4.25.6.2 Order data.................................................................................................................................... 1976
4.25.6.3 Technical data..............................................................................................................................1977
4.25.6.4 LED status indicators................................................................................................................... 1978
4.25.6.5 Pinout........................................................................................................................................... 1978
4.25.6.6 Connection example.................................................................................................................... 1979
4.25.6.7 Connection options for digital inputs............................................................................................1979
4.25.6.8 Input circuit diagram.................................................................................................................... 1979
4.25.6.9 Output circuit diagram..................................................................................................................1980
4.25.6.10 Overvoltage cutoff...................................................................................................................... 1980
4.25.6.11 Overtemperature cutoff (at 85°C)...............................................................................................1980
4.25.6.12 Derating...................................................................................................................................... 1981
4.25.6.13 Register description................................................................................................................... 1983
4.25.7 X20SM1436....................................................................................................................................... 2020
4.25.7.1 General information......................................................................................................................2020
4.25.7.2 Order data.................................................................................................................................... 2020
4.25.7.3 Technical data..............................................................................................................................2021
4.25.7.4 LED status indicators................................................................................................................... 2022
4.25.7.5 Pinout........................................................................................................................................... 2022
4.25.7.6 Connection example.................................................................................................................... 2023
4.25.7.7 Connection options for digital inputs............................................................................................2023
4.25.7.8 Input circuit diagram.................................................................................................................... 2024
4.25.7.9 Output circuit diagram..................................................................................................................2024
4.25.7.10 Overvoltage motor cutoff............................................................................................................2024
4.25.7.11 Overtemperature cutoff (at 85°C)...............................................................................................2025
4.25.7.12 Power supply dimensioning....................................................................................................... 2025
4.25.7.13 Protection................................................................................................................................... 2026
4.25.7.14 Derating...................................................................................................................................... 2027
4.25.7.15 Register description................................................................................................................... 2029
4.26 Other functions........................................................................................................................................2066
4.26.1 Brief information.................................................................................................................................2066
4.26.2 X20CM4810....................................................................................................................................... 2067
4.26.2.1 Order data.................................................................................................................................... 2067
4.26.2.2 Technical data..............................................................................................................................2067
4.26.2.3 General information about the module........................................................................................ 2075
4.26.2.4 Condition monitoring / Oscillation analyses.................................................................................2077
4.26.2.5 Register description..................................................................................................................... 2147
4.26.2.6 FlatStream.................................................................................................................................... 2182
4.26.2.7 X20CM4810 on the fieldbus........................................................................................................ 2204
4.26.2.8 Accessories.................................................................................................................................. 2204
4.26.3 X20CM8281....................................................................................................................................... 2210
4.26.3.1 General information......................................................................................................................2210
4.26.3.2 Order data.................................................................................................................................... 2210
4.26.3.3 Technical data..............................................................................................................................2210
4.26.3.4 LED status indicators................................................................................................................... 2213
4.26.3.5 Pinout........................................................................................................................................... 2213
4.26.3.6 Connection example.................................................................................................................... 2214
4.26.3.7 Input circuit diagram.................................................................................................................... 2214
4.26.3.8 Output circuit diagram..................................................................................................................2215
4.26.3.9 Switching inductive loads.............................................................................................................2215
4.26.3.10 Register description................................................................................................................... 2216
4.26.4 X20CM8323....................................................................................................................................... 2227

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4.26.4.1 General information......................................................................................................................2227

4.26.4.2 Order data.................................................................................................................................... 2227
4.26.4.3 Technical data..............................................................................................................................2227
4.26.4.4 LED status indicators................................................................................................................... 2228
4.26.4.5 Pinout........................................................................................................................................... 2229
4.26.4.6 Connection example.................................................................................................................... 2229
4.26.4.7 Output circuit diagram..................................................................................................................2229
4.26.4.8 Switching inductive loads.............................................................................................................2230
4.26.4.9 Register description..................................................................................................................... 2231
4.26.5 X20DS438A....................................................................................................................................... 2244
4.26.5.1 General information......................................................................................................................2244
4.26.5.2 Order data.................................................................................................................................... 2244
4.26.5.3 Technical data..............................................................................................................................2245
4.26.5.4 LED status indicators................................................................................................................... 2247
4.26.5.5 Pinout........................................................................................................................................... 2247
4.26.5.6 Connection example.................................................................................................................... 2248
4.26.5.7 Input/output circuit diagram..........................................................................................................2248
4.26.5.8 SG3 support................................................................................................................................. 2248
4.26.5.9 Register description..................................................................................................................... 2249
4.26.6 X20PD0011........................................................................................................................................ 2308
4.26.6.1 General information......................................................................................................................2308
4.26.6.2 Order data.................................................................................................................................... 2308
4.26.6.3 Technical data..............................................................................................................................2309
4.26.6.4 LED status indicators................................................................................................................... 2310
4.26.6.5 Pinout........................................................................................................................................... 2310
4.26.6.6 Connection example.................................................................................................................... 2310
4.26.6.7 Register description..................................................................................................................... 2311
4.26.7 X20PD0012........................................................................................................................................2312
4.26.7.1 General information......................................................................................................................2312
4.26.7.2 Order data.................................................................................................................................... 2312
4.26.7.3 Technical data..............................................................................................................................2313
4.26.7.4 LED status indicators................................................................................................................... 2314
4.26.7.5 Pinout........................................................................................................................................... 2314
4.26.7.6 Connection example.................................................................................................................... 2314
4.26.7.7 Register description..................................................................................................................... 2315
4.26.8 X20PD0016........................................................................................................................................2316
4.26.8.1 General information......................................................................................................................2316
4.26.8.2 Order data.................................................................................................................................... 2316
4.26.8.3 Technical data..............................................................................................................................2317
4.26.8.4 LED status indicators................................................................................................................... 2318
4.26.8.5 Pinout........................................................................................................................................... 2318
4.26.8.6 Connection example.................................................................................................................... 2318
4.26.8.7 Register description..................................................................................................................... 2319
4.26.9 X20PD2113........................................................................................................................................ 2320
4.26.9.1 General information......................................................................................................................2320
4.26.9.2 Order data.................................................................................................................................... 2320
4.26.9.3 Technical data..............................................................................................................................2321
4.26.9.4 LED status indicators................................................................................................................... 2322
4.26.9.5 Pinout........................................................................................................................................... 2322
4.26.9.6 Connection examples...................................................................................................................2323
4.26.9.7 Register description..................................................................................................................... 2324
4.26.10 X20PS4951......................................................................................................................................2325
4.26.10.1 General information....................................................................................................................2325
4.26.10.2 Order data.................................................................................................................................. 2325
4.26.10.3 Technical data............................................................................................................................2326
4.26.10.4 LED status indicators................................................................................................................. 2327
4.26.10.5 Pinout......................................................................................................................................... 2327

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4.26.10.6 Connection example.................................................................................................................. 2327

4.26.10.7 Output circuit diagram................................................................................................................2328
4.26.10.8 Register description................................................................................................................... 2329
4.27 Power supply modules............................................................................................................................2330
4.27.1 Brief information.................................................................................................................................2330
4.27.2 X20PS2100........................................................................................................................................2331
4.27.2.1 General information......................................................................................................................2331
4.27.2.2 Order data.................................................................................................................................... 2331
4.27.2.3 Technical data..............................................................................................................................2332
4.27.2.4 LED status indicators................................................................................................................... 2332
4.27.2.5 Pinout........................................................................................................................................... 2333
4.27.2.6 Connection example.................................................................................................................... 2333
4.27.2.7 Shutting the potential group down safely.................................................................................... 2333
4.27.2.8 Register description..................................................................................................................... 2334
4.27.3 X20PS2110........................................................................................................................................ 2335
4.27.3.1 General information......................................................................................................................2335
4.27.3.2 Order data.................................................................................................................................... 2335
4.27.3.3 Technical data..............................................................................................................................2335
4.27.3.4 LED status indicators................................................................................................................... 2336
4.27.3.5 Pinout........................................................................................................................................... 2337
4.27.3.6 Connection example.................................................................................................................... 2337
4.27.3.7 Shutting the potential group down safely.................................................................................... 2337
4.27.3.8 Register description..................................................................................................................... 2338
4.27.4 X20PS3300........................................................................................................................................2340
4.27.4.1 General information......................................................................................................................2340
4.27.4.2 Order data.................................................................................................................................... 2340
4.27.4.3 Technical data..............................................................................................................................2340
4.27.4.4 LED status indicators................................................................................................................... 2341
4.27.4.5 Pinout........................................................................................................................................... 2342
4.27.4.6 Connection examples...................................................................................................................2342
4.27.4.7 Derating........................................................................................................................................ 2343
4.27.4.8 Register description..................................................................................................................... 2344
4.27.5 X20PS3310........................................................................................................................................2346
4.27.5.1 General information......................................................................................................................2346
4.27.5.2 Order data.................................................................................................................................... 2346
4.27.5.3 Technical data..............................................................................................................................2346
4.27.5.4 LED status indicators................................................................................................................... 2347
4.27.5.5 Pinout........................................................................................................................................... 2348
4.27.5.6 Connection examples...................................................................................................................2348
4.27.5.7 Derating........................................................................................................................................ 2349
4.27.5.8 Register description..................................................................................................................... 2350
4.28 X20 redundancy system......................................................................................................................... 2352
4.28.1 Brief information.................................................................................................................................2352
4.28.2 X20HB8884........................................................................................................................................2353
4.28.2.1 General information......................................................................................................................2353
4.28.2.2 Order data.................................................................................................................................... 2353
4.28.2.3 Technical data..............................................................................................................................2353
4.28.2.4 LED status indicators................................................................................................................... 2354
4.28.2.5 Operating and connection elements............................................................................................ 2355
4.28.2.6 POWERLINK station number.......................................................................................................2355
4.28.2.7 Ethernet interface.........................................................................................................................2355
4.28.2.8 POWERLINK cable redundancy system..................................................................................... 2356
4.28.2.9 Redundant supply voltage........................................................................................................... 2364
4.29 System modules for the X20 hub system.............................................................................................. 2366
4.29.1 Brief information.................................................................................................................................2366
4.29.2 X20HB1881........................................................................................................................................2367
4.29.2.1 General information......................................................................................................................2367

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4.29.2.2 Order data.................................................................................................................................... 2367

4.29.2.3 Technical data..............................................................................................................................2368
4.29.2.4 LED status indicators................................................................................................................... 2369
4.29.2.5 Operating and connection elements............................................................................................ 2369
4.29.2.6 Ethernet interface.........................................................................................................................2369
4.29.2.7 Wiring guidelines for X20 modules with fiber optic cable............................................................ 2369
4.29.3 X20HB2880........................................................................................................................................2370
4.29.3.1 General information......................................................................................................................2370
4.29.3.2 Order data.................................................................................................................................... 2370
4.29.3.3 Technical data..............................................................................................................................2371
4.29.3.4 LED status indicators................................................................................................................... 2372
4.29.3.5 Operating and connection elements............................................................................................ 2372
4.29.3.6 Ethernet interface.........................................................................................................................2372
4.29.4 X20HB2881........................................................................................................................................2373
4.29.4.1 General information......................................................................................................................2373
4.29.4.2 Order data.................................................................................................................................... 2373
4.29.4.3 Technical data..............................................................................................................................2374
4.29.4.4 LED status indicators................................................................................................................... 2375
4.29.4.5 Operating and connection elements............................................................................................ 2375
4.29.4.6 Ethernet interfaces....................................................................................................................... 2375
4.29.4.7 Wiring guidelines for X20 modules with fiber optic cable............................................................ 2375
4.29.5 X20HB28G0.......................................................................................................................................2376
4.29.5.1 General information......................................................................................................................2376
4.29.5.2 Order data.................................................................................................................................... 2376
4.29.5.3 Technical data..............................................................................................................................2377
4.29.5.4 LED status indicators................................................................................................................... 2378
4.29.5.5 Operating and connection elements............................................................................................ 2378
4.29.5.6 Ethernet interface.........................................................................................................................2378
4.29.6 X20PS8002........................................................................................................................................2379
4.29.6.1 General information......................................................................................................................2379
4.29.6.2 Order data.................................................................................................................................... 2379
4.29.6.3 Technical data..............................................................................................................................2379
4.29.6.4 LED status indicators................................................................................................................... 2380
4.29.6.5 Pinout........................................................................................................................................... 2380
4.29.6.6 Connection example.................................................................................................................... 2381
4.29.6.7 Derating for the supply................................................................................................................ 2381
4.30 System modules for the X20 redundancy system..................................................................................2382
4.30.1 Brief information.................................................................................................................................2382
4.30.2 X20HB2885........................................................................................................................................2383
4.30.2.1 General information......................................................................................................................2383
4.30.2.2 Order data.................................................................................................................................... 2383
4.30.2.3 Technical data..............................................................................................................................2384
4.30.2.4 LED status indicators................................................................................................................... 2385
4.30.2.5 Operating and connection elements............................................................................................ 2385
4.30.2.6 Ethernet interface.........................................................................................................................2385
4.30.3 X20HB2886........................................................................................................................................2386
4.30.3.1 General information......................................................................................................................2386
4.30.3.2 Order data.................................................................................................................................... 2386
4.30.3.3 Technical data..............................................................................................................................2387
4.30.3.4 LED status indicators................................................................................................................... 2388
4.30.3.5 Operating and connection elements............................................................................................ 2388
4.30.3.6 Ethernet interfaces....................................................................................................................... 2388
4.30.3.7 Wiring guidelines for X20 modules with fiber optic cable............................................................ 2388
4.31 Temperature modules............................................................................................................................. 2389
4.31.1 Brief information.................................................................................................................................2389
4.31.2 Measurement methods...................................................................................................................... 2390
4.31.3 X20AT2222........................................................................................................................................ 2391

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 Table of contents

4.31.3.1 General information......................................................................................................................2391

4.31.3.2 Order data.................................................................................................................................... 2391
4.31.3.3 Technical data..............................................................................................................................2392
4.31.3.4 LED status indicators................................................................................................................... 2394
4.31.3.5 Pinout........................................................................................................................................... 2394
4.31.3.6 Connection example.................................................................................................................... 2394
4.31.3.7 Input circuit diagram.................................................................................................................... 2395
4.31.3.8 Register description..................................................................................................................... 2396
4.31.4 X20AT4222........................................................................................................................................ 2400
4.31.4.1 General information......................................................................................................................2400
4.31.4.2 Order data.................................................................................................................................... 2400
4.31.4.3 Technical data..............................................................................................................................2401
4.31.4.4 LED status indicators................................................................................................................... 2403
4.31.4.5 Pinout........................................................................................................................................... 2403
4.31.4.6 Connection example.................................................................................................................... 2403
4.31.4.7 Input circuit diagram.................................................................................................................... 2404
4.31.4.8 Register description..................................................................................................................... 2405
4.31.5 X20ATA312........................................................................................................................................ 2409
4.31.5.1 General information......................................................................................................................2409
4.31.5.2 Order data.................................................................................................................................... 2409
4.31.5.3 Technical data..............................................................................................................................2409
4.31.5.4 Status LEDs................................................................................................................................. 2411
4.31.5.5 Pinout........................................................................................................................................... 2411
4.31.5.6 Connection example.................................................................................................................... 2412
4.31.5.7 Input circuit diagram.................................................................................................................... 2412
4.31.5.8 Register description..................................................................................................................... 2413
4.31.6 X20ATA492........................................................................................................................................ 2420
4.31.6.1 General information......................................................................................................................2420
4.31.6.2 Order data.................................................................................................................................... 2420
4.31.6.3 Technical data..............................................................................................................................2420
4.31.6.4 Status LEDs................................................................................................................................. 2423
4.31.6.5 Pinout........................................................................................................................................... 2423
4.31.6.6 Connection examples...................................................................................................................2423
4.31.6.7 Input circuit diagram.................................................................................................................... 2426
4.31.6.8 Increased precision...................................................................................................................... 2427
4.31.6.9 Register description..................................................................................................................... 2428
4.31.7 X20ATB312........................................................................................................................................ 2442
4.31.7.1 General information......................................................................................................................2442
4.31.7.2 Order data.................................................................................................................................... 2442
4.31.7.3 Technical data..............................................................................................................................2442
4.31.7.4 Status LEDs................................................................................................................................. 2444
4.31.7.5 Pinout........................................................................................................................................... 2444
4.31.7.6 Connection example.................................................................................................................... 2445
4.31.7.7 Input circuit diagram.................................................................................................................... 2445
4.31.7.8 Register description..................................................................................................................... 2446
4.31.8 X20ATC402........................................................................................................................................2453
4.31.8.1 General information......................................................................................................................2453
4.31.8.2 Order data.................................................................................................................................... 2453
4.31.8.3 Technical data..............................................................................................................................2453
4.31.8.4 Status LEDs................................................................................................................................. 2456
4.31.8.5 Pinout........................................................................................................................................... 2456
4.31.8.6 Connection examples...................................................................................................................2456
4.31.8.7 Input circuit diagram.................................................................................................................... 2458
4.31.8.8 Increased precision...................................................................................................................... 2459
4.31.8.9 X20ATC402 - Register description.............................................................................................. 2460
4.32 Terminal blocks....................................................................................................................................... 2474
4.32.1 Brief information.................................................................................................................................2474

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4.32.2 X20TB06/X20TB12............................................................................................................................ 2475

4.32.2.1 General information......................................................................................................................2475
4.32.2.2 Order data.................................................................................................................................... 2475
4.32.2.3 Technical data..............................................................................................................................2476
4.32.2.4 Contact holding force................................................................................................................... 2476
4.32.3 X20TB1E............................................................................................................................................2477
4.32.3.1 General information......................................................................................................................2477
4.32.3.2 Order data.................................................................................................................................... 2477
4.32.3.3 Technical data..............................................................................................................................2478
4.32.3.4 Contact holding force................................................................................................................... 2478
4.32.4 X20TB1F............................................................................................................................................2479
4.32.4.1 General information......................................................................................................................2479
4.32.4.2 Order data.................................................................................................................................... 2479
4.32.4.3 Technical data..............................................................................................................................2480
4.32.4.4 Contact holding force................................................................................................................... 2480
4.32.5 X20TB32............................................................................................................................................ 2481
4.32.5.1 General information......................................................................................................................2481
4.32.5.2 Order data.................................................................................................................................... 2481
4.32.5.3 Technical data..............................................................................................................................2482
4.32.5.4 Contact holding force................................................................................................................... 2482

5 Coated modules.................................................................................................. 2483

5.1 Module overview: Alphabetical................................................................................................................. 2484
5.2 Module overview: Grouped....................................................................................................................... 2486
5.3 Analog input modules............................................................................................................................... 2488
5.3.1 Brief information.................................................................................................................................. 2488
5.3.2 X20cAI2438......................................................................................................................................... 2489
5.3.2.1 General information........................................................................................................................2489
5.3.2.2 Order data...................................................................................................................................... 2489
5.3.2.3 Technical data................................................................................................................................2490
5.3.3 X20cAI4622......................................................................................................................................... 2492
5.3.3.1 General information........................................................................................................................2492
5.3.3.2 Order data...................................................................................................................................... 2492
5.3.3.3 Technical data................................................................................................................................2493
5.3.4 X20cAI4632......................................................................................................................................... 2495
5.3.4.1 General information........................................................................................................................2495
5.3.4.2 Order data...................................................................................................................................... 2495
5.3.4.3 Technical data................................................................................................................................2496
5.3.5 X20cAI4632-1...................................................................................................................................... 2498
5.3.5.1 General information........................................................................................................................2498
5.3.5.2 Order data...................................................................................................................................... 2498
5.3.5.3 Technical data................................................................................................................................2499
5.3.6 X20cAP3121........................................................................................................................................ 2501
5.3.6.1 General information........................................................................................................................2501
5.3.6.2 Order data...................................................................................................................................... 2501
5.3.6.3 Technical data................................................................................................................................2501
5.4 Analog output modules............................................................................................................................. 2503
5.4.1 Brief information.................................................................................................................................. 2503
5.4.2 X20cAO2437........................................................................................................................................2504
5.4.2.1 General information........................................................................................................................2504
5.4.2.2 Order data...................................................................................................................................... 2504
5.4.2.3 Technical data................................................................................................................................2504
5.4.3 X20cAO2438........................................................................................................................................2506
5.4.3.1 General information........................................................................................................................2506
5.4.3.2 Order data...................................................................................................................................... 2506
5.4.3.3 Technical data................................................................................................................................2507
5.4.4 X20cAO4622........................................................................................................................................2509

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5.4.4.1 General information........................................................................................................................2509

5.4.4.2 Order data...................................................................................................................................... 2509
5.4.4.3 Technical data................................................................................................................................2509
5.4.5 X20cAO4632........................................................................................................................................2511
5.4.5.1 General information........................................................................................................................2511
5.4.5.2 Order data...................................................................................................................................... 2511
5.4.5.3 Technical data................................................................................................................................2511
5.4.6 X20cAO4632-1.................................................................................................................................... 2513
5.4.6.1 General information........................................................................................................................2513
5.4.6.2 Order data...................................................................................................................................... 2513
5.4.6.3 Technical data................................................................................................................................2513
5.5 Bus controllers.......................................................................................................................................... 2515
5.5.1 Brief information.................................................................................................................................. 2515
5.5.2 X20cBC0083........................................................................................................................................2516
5.5.2.1 General information........................................................................................................................2516
5.5.2.2 Order data...................................................................................................................................... 2516
5.5.2.3 Technical data................................................................................................................................2517
5.5.3 X20cBC0087........................................................................................................................................2518
5.5.3.1 General information........................................................................................................................2518
5.5.3.2 Order data...................................................................................................................................... 2518
5.5.3.3 Technical data................................................................................................................................2519
5.5.4 X20cBC0088........................................................................................................................................2520
5.5.4.1 General information........................................................................................................................2520
5.5.4.2 Order data...................................................................................................................................... 2520
5.5.4.3 Technical data................................................................................................................................2521
5.6 Bus controllers System modules.............................................................................................................. 2522
5.6.1 Brief information.................................................................................................................................. 2522
5.6.2 X20cBB80............................................................................................................................................ 2523
5.6.2.1 General information........................................................................................................................2523
5.6.2.2 Order data...................................................................................................................................... 2523
5.6.2.3 Technical data................................................................................................................................2524
5.6.3 X20cPS9400........................................................................................................................................ 2525
5.6.3.1 General information........................................................................................................................2525
5.6.3.2 Order data...................................................................................................................................... 2525
5.6.3.3 Technical data................................................................................................................................2525
5.7 Bus modules............................................................................................................................................. 2527
5.7.1 Brief information.................................................................................................................................. 2527
5.7.2 X20cBM01........................................................................................................................................... 2528
5.7.2.1 General information........................................................................................................................2528
5.7.2.2 Order data...................................................................................................................................... 2528
5.7.2.3 Technical data................................................................................................................................2529
5.7.3 X20cBM11............................................................................................................................................2530
5.7.3.1 General information........................................................................................................................2530
5.7.3.2 Order data...................................................................................................................................... 2530
5.7.3.3 Technical data................................................................................................................................2531
5.7.4 X20cBM12........................................................................................................................................... 2532
5.7.4.1 General information........................................................................................................................2532
5.7.4.2 Order data...................................................................................................................................... 2532
5.7.4.3 Technical data................................................................................................................................2533
5.7.5 X20cBM31........................................................................................................................................... 2534
5.7.5.1 General information........................................................................................................................2534
5.7.5.2 Bestelldaten....................................................................................................................................2534
5.7.5.3 Technical data................................................................................................................................2535
5.7.6 X20cBM32........................................................................................................................................... 2536
5.7.6.1 General information........................................................................................................................2536
5.7.6.2 Order data...................................................................................................................................... 2536
5.7.6.3 Technical data................................................................................................................................2537

X20 system User's Manual 3.10 43

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5.8 Bus receivers and Bus transmitters..........................................................................................................2538

5.8.1 Brief information.................................................................................................................................. 2538
5.8.2 X20cBR9300........................................................................................................................................2539
5.8.2.1 General information........................................................................................................................2539
5.8.2.2 Order data...................................................................................................................................... 2539
5.8.2.3 Technical data................................................................................................................................2539
5.8.3 X20cBT9100........................................................................................................................................ 2541
5.8.3.1 General information........................................................................................................................2541
5.8.3.2 Order data...................................................................................................................................... 2541
5.8.3.3 Technical data................................................................................................................................2542
5.9 Counter modules.......................................................................................................................................2543
5.9.1 Brief information.................................................................................................................................. 2543
5.9.2 X20cDC1198........................................................................................................................................ 2544
5.9.2.1 General information........................................................................................................................2544
5.9.2.2 Order data...................................................................................................................................... 2544
5.9.2.3 Technical data................................................................................................................................2544
5.9.3 X20cDC1396........................................................................................................................................2546
5.9.3.1 General information........................................................................................................................2546
5.9.3.2 Order data...................................................................................................................................... 2546
5.9.3.3 Technical data................................................................................................................................2546
5.9.4 X20cDC2395........................................................................................................................................2548
5.9.4.1 General information........................................................................................................................2548
5.9.4.2 Order data...................................................................................................................................... 2548
5.9.4.3 Technical data................................................................................................................................2549
5.10 X20 CPUs............................................................................................................................................... 2551
5.10.1 Brief information.................................................................................................................................2551
5.10.2 X20cCPx58x...................................................................................................................................... 2552
5.10.2.1 General information......................................................................................................................2552
5.10.2.2 Order data.................................................................................................................................... 2552
5.10.2.3 Technical data..............................................................................................................................2552
5.11 Digital input modules...............................................................................................................................2556
5.11.1 Brief information.................................................................................................................................2556
5.11.2 X20cDI4371........................................................................................................................................2557
5.11.2.1 General information...................................................................................................................... 2557
5.11.2.2 Order data.................................................................................................................................... 2557
5.11.2.3 Technical data.............................................................................................................................. 2557
5.11.3 X20cDI4375........................................................................................................................................2559
5.11.3.1 General information...................................................................................................................... 2559
5.11.3.2 Order data.................................................................................................................................... 2559
5.11.3.3 Technical data.............................................................................................................................. 2560
5.11.4 X20cDI4760........................................................................................................................................2561
5.11.4.1 General information...................................................................................................................... 2561
5.11.4.2 Order data.................................................................................................................................... 2561
5.11.4.3 Technical data.............................................................................................................................. 2561
5.11.5 X20cDI6371........................................................................................................................................2563
5.11.5.1 General information...................................................................................................................... 2563
5.11.5.2 Order data.................................................................................................................................... 2563
5.11.5.3 Technical data.............................................................................................................................. 2564
5.11.6 X20cDI9371........................................................................................................................................2565
5.11.6.1 General information...................................................................................................................... 2565
5.11.6.2 Order data.................................................................................................................................... 2565
5.11.6.3 Technical data.............................................................................................................................. 2566
5.11.7 X20cDI9372........................................................................................................................................2567
5.11.7.1 General information...................................................................................................................... 2567
5.11.7.2 Order data.................................................................................................................................... 2567
5.11.7.3 Technical data.............................................................................................................................. 2568
5.12 Digital mixed modules.............................................................................................................................2569

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5.12.1 Brief information.................................................................................................................................2569

5.12.2 X20cDM9324..................................................................................................................................... 2570
5.12.2.1 General information......................................................................................................................2570
5.12.2.2 Order data.................................................................................................................................... 2570
5.12.2.3 Technical data..............................................................................................................................2570
5.13 Digital output modules............................................................................................................................ 2572
5.13.1 Brief information.................................................................................................................................2572
5.13.2 X20cDO4332..................................................................................................................................... 2573
5.13.2.1 General information......................................................................................................................2573
5.13.2.2 Order data.................................................................................................................................... 2573
5.13.2.3 Technical data..............................................................................................................................2573
5.13.3 X20cDO6321..................................................................................................................................... 2575
5.13.3.1 General information......................................................................................................................2575
5.13.3.2 Order data.................................................................................................................................... 2575
5.13.3.3 Technical data..............................................................................................................................2575
5.13.4 X20cDO6639..................................................................................................................................... 2577
5.13.4.1 General information......................................................................................................................2577
5.13.4.2 Order data.................................................................................................................................... 2577
5.13.4.3 Technical data..............................................................................................................................2577
5.13.5 X20cDO8331..................................................................................................................................... 2579
5.13.5.1 General information......................................................................................................................2579
5.13.5.2 Order data.................................................................................................................................... 2579
5.13.5.3 Technical data..............................................................................................................................2579
5.13.6 X20cDO9321..................................................................................................................................... 2581
5.13.6.1 General information......................................................................................................................2581
5.13.6.2 Order data.................................................................................................................................... 2581
5.13.6.3 Technical data..............................................................................................................................2581
5.13.7 X20cDO9322..................................................................................................................................... 2583
5.13.7.1 General information......................................................................................................................2583
5.13.7.2 Order data.................................................................................................................................... 2583
5.13.7.3 Technical data..............................................................................................................................2583
5.14 Digital signal processing modules.......................................................................................................... 2585
5.14.1 Brief information.................................................................................................................................2585
5.14.2 X20cDS1119...................................................................................................................................... 2586
5.14.2.1 General information......................................................................................................................2586
5.14.2.2 Order data.................................................................................................................................... 2586
5.14.2.3 Technical data..............................................................................................................................2587
5.15 X20 electronics module communication................................................................................................. 2589
5.15.1 Brief information.................................................................................................................................2589
5.15.2 X20cCS1030......................................................................................................................................2590
5.15.2.1 General information......................................................................................................................2590
5.15.2.2 Order data.................................................................................................................................... 2590
5.15.2.3 Technical data..............................................................................................................................2591
5.16 Expandable bus controllers.....................................................................................................................2592
5.16.1 Brief information.................................................................................................................................2592
5.16.2 X20cBC1083......................................................................................................................................2593
5.16.2.1 General information......................................................................................................................2593
5.16.2.2 Order data.................................................................................................................................... 2593
5.16.2.3 Technical data..............................................................................................................................2594
5.16.3 X20cBC8083......................................................................................................................................2595
5.16.3.1 General information......................................................................................................................2595
5.16.3.2 Order data.................................................................................................................................... 2595
5.16.3.3 Technical data..............................................................................................................................2596
5.16.4 X20cBC8084......................................................................................................................................2597
5.16.4.1 General information......................................................................................................................2597
5.16.4.2 Order data.................................................................................................................................... 2597
5.16.4.3 Technical data..............................................................................................................................2598

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5.17 Expandable bus controllers System modules.........................................................................................2599

5.17.1 Brief information.................................................................................................................................2599
5.17.2 X20cBB81.......................................................................................................................................... 2600
5.17.2.1 General information......................................................................................................................2600
5.17.2.2 Order data.................................................................................................................................... 2600
5.17.2.3 Technical data..............................................................................................................................2601
5.17.3 X20cBB82.......................................................................................................................................... 2602
5.17.3.1 General information......................................................................................................................2602
5.17.3.2 Order data.................................................................................................................................... 2602
5.17.3.3 Technical data..............................................................................................................................2603
5.18 X20 hub system...................................................................................................................................... 2604
5.18.1 Brief information.................................................................................................................................2604
5.18.2 X20cHB8880......................................................................................................................................2605
5.18.2.1 General information......................................................................................................................2605
5.18.2.2 Order data.................................................................................................................................... 2605
5.18.2.3 Technical data..............................................................................................................................2606
5.19 Motor controllers..................................................................................................................................... 2607
5.19.1 Brief information.................................................................................................................................2607
5.19.2 X20cMM2436.....................................................................................................................................2608
5.19.2.1 General information......................................................................................................................2608
5.19.2.2 Order data.................................................................................................................................... 2608
5.19.2.3 Technical data..............................................................................................................................2608
5.20 X20 interface module communication.....................................................................................................2610
5.20.1 Brief information.................................................................................................................................2610
5.20.2 X20cIF1030........................................................................................................................................2611
5.20.2.1 General information......................................................................................................................2611
5.20.2.2 Order data.................................................................................................................................... 2611
5.20.2.3 Technical data..............................................................................................................................2612
5.20.3 X20cIF1061-1.................................................................................................................................... 2613
5.20.3.1 General information......................................................................................................................2613
5.20.3.2 Order data.................................................................................................................................... 2613
5.20.3.3 Technical data..............................................................................................................................2614
5.20.4 X20cIF1063-1.................................................................................................................................... 2615
5.20.4.1 General information......................................................................................................................2615
5.20.4.2 Order data.................................................................................................................................... 2615
5.20.4.3 Technical data..............................................................................................................................2616
5.20.5 X20cIF1082-2.................................................................................................................................... 2617
5.20.5.1 General information......................................................................................................................2617
5.20.5.2 Order data.................................................................................................................................... 2617
5.20.5.3 Technical data..............................................................................................................................2618
5.20.6 X20cIF10D3-1....................................................................................................................................2619
5.20.6.1 General information......................................................................................................................2619
5.20.6.2 Order data.................................................................................................................................... 2619
5.20.6.3 Technical data..............................................................................................................................2620
5.20.7 X20cIF10E3-1.................................................................................................................................... 2621
5.20.7.1 General information......................................................................................................................2621
5.20.7.2 Order data.................................................................................................................................... 2621
5.20.7.3 Technical data..............................................................................................................................2622
5.20.8 X20cIF10X0....................................................................................................................................... 2623
5.20.8.1 General information......................................................................................................................2623
5.20.8.2 Order data.................................................................................................................................... 2623
5.20.8.3 Technical data..............................................................................................................................2624
5.20.9 X20cIF2181-2.................................................................................................................................... 2625
5.20.9.1 General information......................................................................................................................2625
5.20.9.2 Order data.................................................................................................................................... 2625
5.20.9.3 Technical data..............................................................................................................................2626
5.21 Other functions........................................................................................................................................2627

46 X20 system User's Manual 3.10

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5.21.1 Brief information.................................................................................................................................2627

5.21.2 X20cPD2113...................................................................................................................................... 2628
5.21.2.1 General information......................................................................................................................2628
5.21.2.2 Order data.................................................................................................................................... 2628
5.21.2.3 Technical data..............................................................................................................................2629
5.22 Power supply modules............................................................................................................................2630
5.22.1 Brief information.................................................................................................................................2630
5.22.2 X20cPS2100...................................................................................................................................... 2631
5.22.2.1 General information......................................................................................................................2631
5.22.2.2 Order data.................................................................................................................................... 2631
5.22.2.3 Technical data..............................................................................................................................2632
5.22.3 X20cPS2110...................................................................................................................................... 2633
5.22.3.1 General information......................................................................................................................2633
5.22.3.2 Order data.................................................................................................................................... 2633
5.22.3.3 Technical data..............................................................................................................................2634
5.22.4 X20cPS3300...................................................................................................................................... 2635
5.22.4.1 General information......................................................................................................................2635
5.22.4.2 Order data.................................................................................................................................... 2635
5.22.4.3 Technical data..............................................................................................................................2635
5.22.5 X20cPS3310...................................................................................................................................... 2637
5.22.5.1 General information......................................................................................................................2637
5.22.5.2 Order data.................................................................................................................................... 2637
5.22.5.3 Technical data..............................................................................................................................2637
5.23 X20 redundancy system......................................................................................................................... 2639
5.23.1 Brief information.................................................................................................................................2639
5.23.2 X20cHB8884......................................................................................................................................2640
5.23.2.1 General information......................................................................................................................2640
5.23.2.2 Order data.................................................................................................................................... 2640
5.23.2.3 Technical data..............................................................................................................................2641
5.24 System modules for the X20 hub system.............................................................................................. 2642
5.24.1 Brief information.................................................................................................................................2642
5.24.2 X20cHB1881......................................................................................................................................2643
5.24.2.1 General information......................................................................................................................2643
5.24.2.2 Order data.................................................................................................................................... 2643
5.24.2.3 Technical data..............................................................................................................................2644
5.24.3 X20cHB2880......................................................................................................................................2645
5.24.3.1 General information......................................................................................................................2645
5.24.3.2 Order data.................................................................................................................................... 2645
5.24.3.3 Technical data..............................................................................................................................2646
5.24.4 X20cHB2881......................................................................................................................................2647
5.24.4.1 General information......................................................................................................................2647
5.24.4.2 Order data.................................................................................................................................... 2647
5.24.4.3 Technical data..............................................................................................................................2648
5.24.5 X20cPS8002...................................................................................................................................... 2649
5.24.5.1 General information......................................................................................................................2649
5.24.5.2 Order data.................................................................................................................................... 2649
5.24.5.3 Technical data..............................................................................................................................2650
5.25 System modules for the X20 redundancy system..................................................................................2651
5.25.1 Brief information.................................................................................................................................2651
5.25.2 X20cHB2885......................................................................................................................................2652
5.25.2.1 General information......................................................................................................................2652
5.25.2.2 Order data.................................................................................................................................... 2652
5.25.2.3 Technical data..............................................................................................................................2653
5.26 Temperature modules............................................................................................................................. 2654
5.26.1 Brief information.................................................................................................................................2654
5.26.2 X20cAT4222.......................................................................................................................................2655
5.26.2.1 General information......................................................................................................................2655

X20 system User's Manual 3.10 47

Table of contents

5.26.2.2 Order data.................................................................................................................................... 2655

5.26.2.3 Technical data..............................................................................................................................2656
5.26.3 X20cAT6402.......................................................................................................................................2658
5.26.3.1 General information......................................................................................................................2658
5.26.3.2 Order data.................................................................................................................................... 2658
5.26.3.3 Technical data..............................................................................................................................2659

6 Accessories......................................................................................................... 2661
6.1 Additional equipment for X20 modules.....................................................................................................2661
6.1.1 Tag holders, terminal locking clips...................................................................................................... 2662
6.1.2 Plain text tags......................................................................................................................................2662
6.1.3 Accessory locking clips....................................................................................................................... 2662
6.2 Locking plates........................................................................................................................................... 2663
6.3 Cable shield clamp................................................................................................................................... 2663
6.4 Shielding bracket.......................................................................................................................................2663
6.5 Terminal labeling.......................................................................................................................................2664
6.6 Labeling tool..............................................................................................................................................2664
6.7 Screwdriver................................................................................................................................................2664
6.8 POWERLINK cables................................................................................................................................. 2665
6.8.1 RJ45 to RJ45...................................................................................................................................... 2665
6.8.2 RJ45 to M12........................................................................................................................................ 2665
6.9 X2X Link cables........................................................................................................................................ 2666
6.9.1 X2X Link connection cable..................................................................................................................2666
6.9.2 Field-assembled...................................................................................................................................2666
6.9.3 General specifications for X2X Link cables........................................................................................ 2666

7 Mechanical handling........................................................................................... 2667

7.1 Solid mechanics........................................................................................................................................ 2667
7.2 Number of connection cycles................................................................................................................... 2667
7.3 Assembling an X20 system...................................................................................................................... 2668
7.3.1 Variant 1.............................................................................................................................................. 2669
7.3.2 Variant 2.............................................................................................................................................. 2672
7.4 Installing the X20 system on the top-hat rail............................................................................................2675
7.5 Removing the X20 system from the top-hat rail.......................................................................................2676
7.5.1 Remove the entire system from the top-hat rail................................................................................. 2676
7.5.2 Removing a block of modules from the top-hat rail............................................................................ 2677
7.6 Expanding an X20 system........................................................................................................................2679
7.7 Installing accessories................................................................................................................................ 2680
7.7.1 Additional locking mechanisms........................................................................................................... 2680
7.7.1.1 Accessory locking clips.................................................................................................................. 2680
7.7.1.2 Terminal locking clip...................................................................................................................... 2681
7.7.2 Plain text tags......................................................................................................................................2683
7.8 Label tags..................................................................................................................................................2684
7.8.1 Labeling the terminal connection........................................................................................................ 2685
7.8.2 Labeling the terminals......................................................................................................................... 2687

8 Standards and certifications..............................................................................2689

8.1 Directives and explanations...................................................................................................................... 2689
8.2 Certifications..............................................................................................................................................2690

Appendix A Abbreviations.................................................................................... 2692

A.1 General information.................................................................................................................................. 2692
A.2 Overview................................................................................................................................................... 2692

Appendix B B&R ID codes.................................................................................... 2693

B.1 General information.................................................................................................................................. 2693
B.2 B&R ID codes sorted by ID code.............................................................................................................2694
48 X20 system User's Manual 3.10
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B.3 B&R ID codes sorted by model number.................................................................................................. 2698

X20 system User's Manual 3.10 49

General information

1 General information

1.1 Manual history

Version Date Comment
3.10 May 2015 Book updated
Existing module groups updated
• Counter modules
• Motor modules
• X20 electronics module communication
• Digital signal processor modules
Chapter "Coated modules" updated
3.00 October 2014 New edition
• All chapters updated
• Register descriptions added for every module
The following groups of modules are still being revised; some modules have not been included in this manual or have
been only partially updated:
• Analog input modules
• Digital signal processor modules
• X20 electronics module communication
• Motor modules
• Other modules
• Temperature modules
• Counter modules
The most up-to-date data sheets for the respective modules can be downloaded from the B&R website.
2.10 March 2009 Book updated
New module groups added
• Expandable bus controllers
• Expandable bus controller system modules
• X20 hub system
• System modules for the X20 hub system
• X20 redundancy system
• System modules for the X20 redundancy system
Existing module groups updated
• Compact CPU system modules
• Fieldbus CPU system modules
• Bus controller system modules
• X20 electronics module communication
• Bus transmitter
• Bus controller
• Digital input modules
• Digital output modules
• Analog input modules
• Temperature modules
• Other modules
• Counter modules
Accessories added
New: Appendix B "B&R ID codes"

Table 1: Manual history

50 X20 system User's Manual 3.10

 General information
Version Date Comment
2.00 July 2007 Book updated
New module groups added
• CPU modules
• Compact CPUs
• Compact CPU system modules
• Fieldbus CPUs
• Fieldbus CPU system modules
• Communication in the X20 IF module
• X20 electronics module communication
• Digital mixed modules
• Other modules
Existing module groups updated
• Bus modules
• Terminal blocks
• Bus controller
• Power supply modules
• Digital input modules
• Digital output modules
• Analog input modules
• Counter modules
Accessories added
1.20 June 2006 First edition

Table 1: Manual history

X20 system User's Manual 3.10 51

General information

1.2 Safety notices

1.2.1 Introduction

Programmable logic controllers, operating and monitoring devices (e.g. industrial PCs, Power Panels, Mobile Pan-
els etc.) as well as the uninterruptible power supplies have all been designed, developed, and produced by B&R for
conventional use in industry. They were not designed, developed and manufactured for any use involving serious
risks or hazards that could lead to death, injury, serious physical damage or loss of any kind without the implemen-
tation of exceptionally stringent safety precautions. In particular, such risks and hazards include the use of these
devices to monitor nuclear reactions in nuclear power plants, their use in flight control or flight safety systems as
well as in the control of mass transportation systems, medical life support systems or weapons systems.
When using programmable logic controllers or operating/monitoring devices as control systems together with a Soft
PLC (e.g. B&R Automation Runtime or comparable product) or Slot PLC (e.g. B&R LS251 or comparable product),
safety precautions relevant to industrial control systems (e.g. the provision of safety devices such as emergency
stop circuits, etc.) must be observed in accordance with applicable national and international regulations. The same
applies for all other devices connected to the system, e.g. drives.
All tasks such as the installation, commissioning and servicing of devices are only permitted to be carried out by
qualified personnel. Qualified personnel are those familiar with the transport, mounting, installation, commissioning
and operation of devices who also have the appropriate qualifications (e.g. IEC 60364). National accident preven-
tion regulations must be observed.
The safety notices, connection descriptions (type plate and documentation) and limit values listed in the technical
data are to be read carefully before installation and commissioning and must be observed.

1.2.2 Intended use

Electronic devices are never completely failsafe. If the programmable control system, operating/monitoring device
or uninterruptible power supply fails, the user is responsible for ensuring that other connected devices, e.g. motors,
are brought to a secure state.

52 X20 system User's Manual 3.10

 General information

1.2.3 Protection against electrostatic discharge

Electrical components that can be damaged by electrostatic discharge (ESD) must be handled accordingly.

1.2.3.1 Packaging

• Electrical components with a housing

… do not require special ESD packaging, but must be handled properly.
(see section "Electrical components with a housing").
• Electrical components without a housing
… are protected by ESD-suitable packaging.

1.2.3.2 Guidelines for proper ESD handling

Electrical components with a housing

• Do not touch the connector contacts on the device (bus data contacts).
• Do not touch the connector contacts on connected cables.
• Do not touch the contact tips on circuit boards.

Electrical components without a housing

The following applies in addition to the points listed under "Electrical components with a housing":
• Any persons handling electrical components or devices with installed electrical components must be
grounded.
• Components are only permitted to be touched on their narrow sides or front plate.
• Components should always be stored in a suitable medium (ESD packaging, conductive foam, etc.).
Information: Metallic surfaces are not suitable storage surfaces!
• Components should not be subjected to electrostatic discharge (e.g. through the use of charged plastics).
• Ensure a minimum distance of 10 cm from monitors and TV sets.
• Measuring instruments and equipment must be grounded.
• Probes on potential-free measuring instruments must be discharged on sufficiently grounded surfaces be-
fore taking measurements.

Individual components
• ESD protective measures for individual components are thoroughly integrated at B&R (conductive floors,
footwear, arm bands, etc.).
• These increased ESD protective measures for individual components are not necessary for customers
handling B&R products.

X20 system User's Manual 3.10 53

General information

1.2.4 Transport and storage

During transport and storage, devices must be protected against undue stress (mechanical loads, temperature,
moisture, corrosive atmospheres, etc.).
Devices contain components sensitive to electrostatic charges that can be damaged by inappropriate handling. It
is therefore necessary to provide the required protective measures against electrostatic discharge when installing
or removing these devices (see also section 1.2.3 "Protection against electrostatic discharge").

1.2.5 Installation

• Installation must be performed according to this documentation using suitable equipment and tools.
• Devices are only permitted to be installed by qualified personnel without voltage applied.
• General safety guidelines and national accident prevention regulations must be observed.
• Electrical installation must be carried out in accordance with applicable guidelines (e.g. line cross sections,
fuses, protective ground connections).
• Take the necessary steps to protect against electrostatic discharges (see section 1.2.3 "Protection against
electrostatic discharge").

1.2.5.1 Inserting and removing I/O modules while the controller is running

I/O modules may be connected and disconnected while the controller is running under the following conditions:
• Connectors are not allowed to carry voltages and must be removed.
• Replacing a module during operation must be supported by the software; otherwise, disconnecting a mod-
ule will cause an emergency stop of the controller.

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1.2.6 Operation

1.2.6.1 Protection against touching electrical parts

To operate programmable logic controllers, operating and monitoring devices, and uninterruptible power supplies,
certain components must carry dangerous voltage levels. Touching one of these parts can result in a life-threatening
electric shock. This could lead to death, severe injury or damage to equipment.
Before turning on the programmable logic controller, operating/monitoring devices or uninterruptible power supply,
the housing must be properly grounded (PE rail). Ground connections must be established even when testing or
operating operating/monitoring devices or the uninterruptible power supply for a short time!
Before turning the device on, all parts that carry voltage must be securely covered. During operation, all covers
must remain closed.

1.2.7 Environmentally friendly disposal

All B&R control components are designed to inflict as little harm on the environment as possible.

1.2.7.1 Separation of materials

It is necessary to separate different materials so the device can undergo an environmentally friendly recycling
process.
Component Disposal
X20 modules Electronic recycling
Cables
Cardboard/paper packaging Paper/Cardboard recycling

Table 2: Environmentally friendly separation of materials

Disposal must comply with applicable legal regulations.

1.2.8 Organization of safety notices

Safety notices in this manual are organized as follows:

Safety notice Description
Danger! Disregarding these safety guidelines and notices can be life-threatening.
Warning! Disregarding these safety guidelines and notices can result in severe injury or substantial damage to equipment.
Caution! Disregarding these safety guidelines and notices can result in injury or damage to equipment.
Information: This information is important for preventing errors.

Table 3: Description of the safety notices used in this documentation

X20 system User's Manual 3.10 55

General information

1.3 Terminology
Term Explanation
SG3 System Generation 3 (SG3) - CPUs with Motorola processors

The following CPUs belong to this series:

• IF161, IP161
• XP152
• CP100, CP104, CP152, CP153, CP200, CP210, CP260, CP430, CP470, CP474, CP476, CP770, CP774
• PP15, PP21, PP35, PP41
SG4 System Generation 4 (SG4) - CPUs with Intel processors

The following CPUs belong to this series:

• CP1583, CP1584, CP1585, CP1586, CP3583, CP3584, CP3585, CP3586
• CP1483, CP1483-1
• CP340, CP360, CP380, CP382, CP570
• PP45, PP65
• PP100/200, PP300/400
• MP100/200
• EC20, EC21
• AC140, AC141
• ARsim, ARwin, ARemb
• APC620, APC700, APC810
SGC System Generation Compact CPUs (SGC) - CPUs with Motorola processors (embedded µP)

The following CPUs belong to this series:

• CP0201, CP0291, CP0292
• XC0201, XC0202, XC0292

Table 4: Terminology

56 X20 system User's Manual 3.10

 System features

2 System features

2.1 Setting the standards in automation

There are many different I/O slice systems. With the X20 system, B&R continues to set standards according to
its motto "Perfection in Automation". Born from experience gained from applications all over the world, numerous
conversations with customers and with the aim for easier, more economical and secure usage, the X20 system is
a universal solution for any automated task in machine and system manufacturing.

Figure 1: Each module is comprised of three basic elements: Terminal block – Electronic module – Bus module

2.1.1 More than just I/O

With its well thought-out details and a sophisticated ergonomic design, the X20 system is more than a remote I/O
system – it's a complete control solution. The X20 system family makes it possible to combine the exact components
needed to meet any application requirements.
• The X20 system is the ideal addition to a standard fieldbus and expands the possibilities of conventional
control systems. Simply connect it, configure it and you're done.
• Teamed up with other B&R components, the X20 system achieves its full potential and allows the imple-
mentation of applications with unimagined performance and flexibility. This type of seamless integration
is a major advantage.

X20 system User's Manual 3.10 57

System features

2.1.2 3 x 1 = 1

Three basic elements make up one module: Terminal block – Electronic module – Bus module
This modularity results in a system that combines the advantages of both rack and I/O slice systems:
• Prewiring without the module
• Hot pluggable electronics
• Extra bus slots for added options

Figure 2: X20 modules are divided into three parts to guarantee the simplest usability
The X20 system delivers 50% more component density, perfected connection technology and optimal gran-
ularity.
• Added value
12 channels with a width of 12.5 mm allow a component density never before achieved with optimal terminal
ergonomics. As a result, the X20 system offers 50% more channels than conventional slice systems. And
this without sacrificing terminal connections.
• Uniformity
Consistent implementation of 1-, 2- or 3-wire connections – no additional jumper terminals needed.
• Granularity
1-channel and 2-channel modules: Maximum flexibility so you only have to pay for what you really need.

58 X20 system User's Manual 3.10

 System features

2.2 Optimized design

X20 modules consist of three submodules to provide maximum ease of use throughout their entire life cycle. This
division into bus module, electronics module and terminal block has several advantages.
• Preconfigured for different machine types
The X20 system bus modules are the basic platform for many machine variations. The design of the ma-
chine determines which electronics modules are used. The software recognizes this design automatically
and makes sure that the right functions are provided where they are needed. Handling a range of different
machine variants couldn't be easier.
• Industrial control cabinet construction
X20 system terminal blocks are separate from the electronics module and make it possible to pre-wire the
entire control cabinet. This is especially ideal for series-produced machines.
• Easy maintenance
X20 modules can be easily exchanged to simplify troubleshooting. The electronic modules can be ex-
changed without interrupting operation. The wiring remains exactly the same thanks to the separate termi-
nal blocks. Being able to quickly replace automation components guarantees reduced down-time.

Simple mounting Diagnostics

Sophisticated top-hat On-site and remote via
rail mounting system for optimal software and
system handling embedded parameter chip

Robust modularity 12-pin terminal block

Direct connection provides maximum
between bus module and component density
terminal block

Extensive product range Push-in terminals

Allows optimal Tool-free
customization for any handling for all standard
task definition connections

Electrical isolation Keying

Safe operation in Seamless plant and
harsh conditions customer coding

Figure 3: Features of the X20 system

X20 system User's Manual 3.10 59

System features

2.3 Remote backplane

The main idea: Remote backplane for a rack system – in other words, the cable is the backplane. All modules are
connected to the uniform backplane (X2X Link). Directly connected X20, X67 or XV modules can each be placed
at a distance of up to 100 m outside the confines of the control cabinet. X2X Link guarantees the highest possible
level of resistance to disturbances based on twisted copper cables.
This not only provides a universal remote backplane which handles the communication between bus modules and
via the X2X Link cable, but makes it possible without converters or any loss in performance. A unique feature of
the X20 is the possibility to later integrate machine options on bus modules that are not yet being used without
having to change the software addressing.

Note:
A 100 m X2X Link cable is available from B&R for custom assembly (model number: X67CA0X99.1000).

X20 system

100 m 100 m

X20 system X20 system X20 system

100 m 100 m 100 m 100 m

XV
X20 system X67 X67 X67

Figure 4: X2X Link - universal backplane based on twisted copper cables

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 System features

2.4 X20 CPUs

2.4.1 General information

The optimally scaled X20 system CPU line satisfies a wide range of needs. It can be implemented anywhere, from
standard applications to the most demanding applications with the highest performance requirements. It can even
master cycle times of 100 µs.
At B&R, RS232, Ethernet and USB are already standard equipment. Network capability and connecting USB de-
vices are therefore possible at no additional cost. In addition, every CPU has a POWERLINK interface for real-time
communication. The possibility to directly connect axes is already integrated. Although the standard features of the
CPUs can handle the majority of applications, there are also up to three multipurpose slots for additional interface
modules.
Because the X20 CPU was designed for top-hat rail installation in a control cabinet, up to 250 X20 I/O modules
– 3000 channels – can be connected directly. This provides the highest performance as well as the advantages
of the remote backplane.

2.4.2 Remote backplane

A power supply integrated in the CPU with I/O supply terminals provides power for the backplane and I/O sensors
and actuators, eliminating the need for additional system components. With a direct I/O connection to an X20 CPU,
you get all the advantages of the remote backplane, i.e. the ability to repeatedly place I/O line sections anywhere
within 100 m using a cable or to add modules with IP67 protection.

100 m 100 m 100 m 100 m 100 m

XV
X20 system X67 X67 X67 X20 system

Figure 5: X20 CPUs - Direct I/O connection to X20 CPU and advantages of remote backplanes

X20 system User's Manual 3.10 61

System features

2.4.3 B&R Automation Studio

B&R Automation Studio is the only programming tool needed for all platforms. It can be used to create application
software in all relevant IEC 61131-3 languages as well as C. Integrated visualization, NC and soft CNC functions
and web server technologies complete the range of powerful features.

2.4.4 PC-based technology

Based on the latest Intel ATOM™ processor technology, X20 CPUs can effectively utilize cycle times down to
100 µs.
An extensive amount of RAM provides the user with unlimited freedom when it comes to application development.
This is complemented by battery-backed nonvolatile SRAM for task-specific data and remanent variables. In the
case of a power failure, variables that have been declared as being remanent are automatically copied from the
fast RAM to the secure SRAM. Data contents are therefore retained after the controller is restarted so that the
process can simply be resumed. A slot for a CompactFlash card is also integrated into the system to hold program
memory or application data such as recipes.

2.4.5 Suitable for industrial use

Providing the highest performance, with many standard interfaces and interface modules for expansions, yet the
dimensions are unbelievably compact. The dimensions of the CPU match those of the X20 modules, which prevents
unnecessary waste of space in the control cabinet.
Fanless operation - a demand the X20 CPUs can satisfy. None of the processors require a fan, which makes them
virtually maintenance-free.

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 System features

2.5 X20 Compact CPUs

2.5.1 General information

With a width of 37.5 mm the X20 Compact CPUs are extremely compact, yet surprisingly powerful. Less powerful
than the PC-based CPUs, there are several models of Compact CPUs available in 2 performance classes.
Compact CPUs are ideal for situations where cycle times in the millisecond range are sufficient and a cost-benefit
analysis plays a decisive role. A range of models with CAN bus and Ethernet can be perfectly adapted to all
requirements, resulting in extremely sleek automation solutions.
The Compact CPU's design and dimensions correspond to the X20 system. The X20 I/O modules are connected
directly to the CPU. These are attached seamlessly to the CPU, making the entire system an extreme space saver
in the control cabinet. Despite the sleek profile, the CPU supply, the X2X Link supply, and the I/O module supply
are integrated in the system. No additional power modules are necessary.
All CPUs have at least two things in common: multitasking capability and programming with B&R Automation Studio
using all relevant IEC61131-3 languages and C.

2.5.2 Product range

The many different variants start with the most space-saving solution, the X20 compact CPU. This module is
equipped with an RS232 online interface and an integrated X20 module connection. Selecting another bus module
also provides an additional onboard CAN bus interface. The upper end of the product range is characterized by
CPUs with a Fast Ethernet interface. The variant with Ethernet is also available with approx. 60% more processing
power.

Figure 6: X20 compact CPUs

X20 system User's Manual 3.10 63

System features

2.6 X20 Fieldbus CPUs

2.6.1 General information

Remote design of I/O systems is one of the standard topologies used in automation solutions for machines and
equipment. In addition, fieldbuses with bus controllers are normally used. Larger topologies or standard fieldbuses
like CANopen, PROFIBUS DP, or DeviceNet can cause relatively long response times.
An input must travel via the bus controller to the CPU before it is processed. The output data must then return on
the same path. This is sufficient for most I/O functions. However, this response time is too long for some functions.
The best solution is for the bus controller to process the data. This type of data preprocessing is usually associated
with limited CPU functionality in the programmable bus controller.
Fieldbus CPUs with integrated fieldbus connections overcome these limitations. Fieldbus CPUs are variations of
Compact CPUs. In addition to these features, there is also the option of connecting fieldbus modules to the left side.
The full CPU functionality of the Compact CPUs plus a plug-in fieldbus module create many more possibilities than
simply data preprocessing. There are enough reserves for relatively complex application processing. Intelligent
substations are another area of use. That means a part of the machine part must continue to function, even when
separated from the main controller.
Based on the Compact CPU platform with up to two plug-in interface modules for the respective fieldbus connection,
this results in a very compact (62.5 mm and 87.5 mm), powerful and intelligent fieldbus controller.

Figure 7: Fieldbus CPU with connected interface module

2.6.2 Product range

As with the Compact CPUs, the new CPUs with fieldbus connection are available in two performance classes.
Depending on the bus module being used, the CPU has an RS232 interface or an RS232 interface plus a CAN
bus interface. The CPU with higher processing power is available with or without an onboard Ethernet interface.
Various fieldbus modules are available.

2.6.3 Programming

All CPUs have several features in common, including integrated connection of X20 modules and system multitask-
ing capability. With B&R Automation Studio, programming can be done in all IEC 61131-3 languages and in C.

64 X20 system User's Manual 3.10

 System features

2.7 For all fieldbuses, integration through standardization

The X20 system is ideally suited for expanding existing control systems using standard fieldbus technology.
For example, a bus controller allows the X20 system to be used as a powerful I/O expansion unit. Standardized
EDS or GSD description files allow X20 system components to be integrated, configured, and programmed in the
programming environment of a non-B&R system.

X20 system X20 system

XV
X20 system
Compact I/O

X20 system X67 X67 X67 X20 system

Figure 8: Expansion of existing control systems using standard fieldbuses and the X20 system

X20 system User's Manual 3.10 65

System features

2.8 Complete system

2.8.1 IP67 - then X67

The X67 is the robust version of the X20 for use outside the control cabinet. The same basic technology, with an ex-
tremely robust housing and 4 to 32 channel modules, guarantees economical solutions in the roughest conditions.

2.8.2 Integrated valve terminal control

The development of the XV system allows for the first time direct and manufacturer-independent control of valve
terminals. A complete digital output module in a size and form comparable with a normal DSUB connector. XV
allows any valve terminal manufacturer to be selected because it is connected directly to the standardized multiple
pin connector on the valve terminal.
Fully integrated in the remote backplane, it rounds off the X20 and X67 for complete automation solutions. One
system, several variations - advantages that pay off. You select your automation components and distribute them
as needed inside and outside the control cabinet.

Figure 9: X20, X67, XV - variations of a single system

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 System features

2.9 Easy wiring

Industrial control cabinet construction streamlines production cycles. Prefabricated cable trees enable faster and
easier assembly directly on the machine or system. The X20 system supports efficient prewiring of the entire control
cabinet using separate terminal blocks. The complete X20 system configuration is mounted in the control cabinet
and connected to the prewired cable trees.
The supply of the X20 modules and the supply of the sensors and actuators do not add any requirements for energy
distribution. The X20 system reduces manual wiring to a minimum.

2.9.1 Install the wires, plug it in, and it's ready to go

Simple, tool-free wiring for fast installation. The X20 system terminal blocks use a fully integrated and proven push-
in connector system. Each terminal can also handle double wire sleeves up to a diameter of 2x 0.75 mm². The
user saves time wiring the system multiple times and distributing the signals.
The wire connections can be removed with a screwdriver. Each terminal also has an access point for a measure-
ment probe. A great deal of thought was given to designing every aspect of the X20 system. Right down to the
wire connectors.

Information:
To avoid damaging the terminals, the X20AC0SD1 B&R screwdriver should be used.
Detached Tool-free
The terminals can be prewired apart from the actual I/O Simple, tool-free wiring for fast installation. The X20 sys-
module. This provides many advantages for control cab- tem terminals use a fully integrated and proven push-
inet construction. Separate manufacturing, just-in-time in connector system. Available with 6-pin and extremely
logistics and the installation of preassembled systems compact 12-pin terminals.
during start-up become reality.

Coded in the system Ergonomic

Factory coding prevents dangerous mix-ups. Coding Component density does not have to negatively affect
guarantees that only parts which are permitted to be ergonomics. With terminal spacing of more than 5 mm,
combined can be combined. Intuitively and without ad- this was handled optimally on the X20 system. Experi-
ditional work. ence gained in the field - used in the field.

Coded in the application Unmistakable

Incorrectly inserting terminals does not necessarily Distinct forms intuitively define various functions, such
damage the electronics, but always causes faulty func- as clearly assigned latching and unlatching functions for
tioning of the system. Application coding prevents this terminals. This prevents errors from the very beginning.
problem.

Labeling Easy servicing

Each terminal is clearly labeled, directly in the plastic. A system's strengths can be seen in its details: In ad-
Additional label tags are available as system acces- dition to the terminal connector and unlocking mecha-
sories including a printer with ECAD connection. nism, each terminal has an access point for a test probe.
You can easily measure the terminal potential without
disconnecting the wire.

X20 system User's Manual 3.10 67

System features

2.10 Sophisticated mechanics

The name B&R stands for many years of experience in developing and manufacturing industrial electronics. But
it's also the mechanics of the X20 system that have been thought through to the last detail. Its robust design, long
guides and strengthened housing guarantee the stability it needs in industrial environments. These features allow
the X20 system to be mounted on a top-hat rail with the same ease as a rack system. They also make it just as
simple to remove it from the rail.
The sophisticated mechanics of the X20 are needed not just to provide this type of handling, but also to be able
to quickly and easily remove I/O slices from the entire system.

Figure 10: Easy mounting on and removal from the top-hat rail
Unlocking mechanism with two positions Defined open position makes the difference
Closed for secure fit on the top-hat rail. Open to remove a module or the entire system.

Removing a single module from the system Mount the entire system as a whole
Remove or reconnect vertically. Or just as easily removing the entire system.

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 System features

2.11 Diagnostics
Outstanding diagnostic options are needed for errors to be found quickly. The X20 system offers several levels
of diagnostics:
• Direct on the module using visual LED displays. Bus status, I/O status and channel states are displayed
in direct relationship to the channels or the function. The different states are displayed in different ways,
e.g. green for OK, red for error.
• Via software in the cyclic data image. With the X20 system, status data does not result in an additional
communication load, which would result in considerable differences between theoretically possible bus
speeds and real requirements during operation. All necessary status data is always transferred cyclically,
with no exceptions.
• Expanded diagnostic data in acyclic data traffic without loss in performance. If a problem occurs, detailed
diagnostic data can be requested from the application by the respective module using an asynchronous
channel. This does not result in additional communication load and cycle times remain unchanged.

Figure 11: Visual diagnostics directly on the module using LED indicators

X20 system User's Manual 3.10 69

System features

2.11.1 re LEDs

Each X20 system module has a LEDs for diagnostics at the top.
The operating state of the module firmware is indicated by the two topmost LEDs r (green) and e (red).
Additional LEDs depend on the module and generally indicate the status of I/O channels. Green LEDs are usually
used for inputs, while yellow is used for outputs. These I/O LED status indicators are only operational in RUN
mode on some modules.
There is a difference between "blinking" and "single flash": when blinking, the LED is on 50% of the time and off
50% of the time; with single flash, the LED only flashes quickly. With "double flash", the LED blinks twice quickly
followed by a pause.
LED r (green) e (red) Description Note
Off Off No power to module Module does not have power.
Single flash On Firmware is not valid Invalid firmware. Occurs when a firmware update has been interrupted.
The firmware is reloaded as soon as the X2X Link master is active again,
but only if the module is also specified in the configuration.
Single flash Off RESET mode Module not yet detected by the X2X Link master
Double flash Off BOOT mode Usually a firmware transfer. Some modules remain in single flash mode
(RESET mode with communi- with a firmware transfer. Depending on the configuration, a firmware
cation) transfer can take several minutes.
Blinking Off PREOPERATIONAL mode Modules whose slot is configured for a different module (or none at all)
remain in PREOPERATIONAL mode. It could be that an incorrect mod-
ule is inserted. An incorrect slot number might be set for bus modules
with node number switches.
On Off RUN mode Everything is OK.
On Blinking RUN mode with an I/O channel An error or warning is present on one or more I/O channels.
error Which channel error on the module is being indicated depends on the
module and can be determined with the respective module description.
On On RUN mode with a module error The module has an error that affects all of its channels.

If no LEDs are lit, then the module is not supplied with power.
If the green r LED is constantly lit and the red e LED is off, then everything is OK.
If the modules remain in a green single flash mode, there is no connection to the X2X Link master, or the X2X Link
master is not yet running. Single flash is output for some modules during a firmware update.
If the module outputs a green double flash, the firmware is being updated. This can take several minutes depending
on the configuration. A firmware update usually only takes place once after the module has been replaced or if
new firmware has been loaded to the master CPU during a project update.
If the modules are blinking green, it means that there are different X2X Link modules in that slot (or none at all).

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 System features

2.12 Embedded parameter chip

Information such as module type, serial number, functionality and version number is contained in the embedded
parameter chip of the X20 module. This information is automatically evaluated by the programming environment
(Automation Studio) and by the application program. This prevents errors during both commissioning and service.
In addition, the system configuration is automated and flexible variations are made possible.
Serial numbers of modules that are defined worldwide are gaining increasing significance in validated systems as
demanded, for example, by the FDA.

2.13 Space for options

The X20 system family makes it possible to combine the exact components necessary depending on the user's de-
mands and individual application requirements. This allows machine options to be implemented easily and flexibly.
Bus modules provide the base, and are more or less a rack replacement. Depending on the option, the necessary
electronics modules are then inserted in the predefined slots.
Addresses are assigned implicitly via the slot. Software that has been developed once is valid for all versions and
does not need to be changed. This is even possible for later machine expansion. The I/O modules are simply
inserted in the defined bus modules, and assigned to the corresponding potential groups and E-stop groups.
To prevent unwanted expansion, each module can be identified and then enabled using the application software.

2.14 Flexibility for options

The implementation of different machine variations using free bus modules is only one of the many features that the
X20 system offers. With the support of B&R Automation Studio, there is an optimized solution using I/O mapping.
What does this mean?
Each I/O configuration is created optimally according to the actual requirements. However, the application software
is designed to handle all potential options. Only the I/O channels that are actually available are configured in the
application program. If an expansion is required, then the additional hardware needed can be easily connected
and the I/O mapping changed. This is done without having to compile the application software.
It doesn't matter where the I/O mapping list is created:
• Manually in B&R Automation Studio
• With tools, e.g. with a database or a table calculation program
• Directly from an ERP system, just like the parts list for the machine
• Automatically in the application software, depending on the hardware used
Machine variation A
The possibilities of the X20 system can be best explained using examples. This is a ma-
chine constellation with two variations, A and B. All of the necessary electronics modules
for machine variation A are shown in the picture to the left. The bus modules needed for
variation B are also present, but without electronic modules.

Machine variation B
Variation B shows the necessary electronic modules but the modules necessary for vari-
ation A are missing. The distribution of the free bus modules for the variations is also
clear: The variable I/O modules can be very easily connected to the required electrically
isolated groups and don't need to be attached in the back. The extensive process of
taking apart the configuration to expand existing electrically isolated groups is also elim-
inated. Simply insert the electronic module and attach the terminal block.

Machine variation A - optimized

The features included in Automation Studio can also be used to achieve completely opti-
mized hardware configurations without losing the advantage of comprehensive applica-
tion software for all variations. As described earlier, simply mapping physical I/O points
to the application program makes it extremely easy to optimize the hardware variations
without even requiring compilation.

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System features

2.15 Configurable X2X Link address

The remote X2X Link backplane, which connects the individual I/O modules with each other, is set up to be self-
addressing. Because of this, it is not necessary to set the node numbers. The module address is assigned according
to its position in the X2X Link line.
In certain cases, e.g. when configurations of modular machines change, it is necessary to define specific module
groups at a fixed address, regardless of the preceding modules in the line.
For this purpose, there are modules in both the X20 system and the X67 system with node number switches that
allow you to set the X2X Link address. All subsequent modules refer to this offset and use it automatically for
addressing purposes.

X20 system

Bus module with

node number switches

X67 system

#10 #11 #12 #30 #31 #20 #21 #22 #50 #51 #52

X2X Link

Figure 12: Setting the X2X Link address

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 System features

2.16 Universal 1, 2, 3-wire connections

Consistent connection types for all requirements – no additional jumper terminals are needed. All connection types
can also be mixed and matched.
Universal 3-wire connections
Integrated supply and ground for sensors and actu-
ators.
DI

Sensor 1

Sensor 2
+24 VDC +24 VDC
GND GND

Universal 2-wire connections

No extra terminals needed.

DI

Sensor 1 Sensor 2

Sensor 3 Sensor 4

Sensor 5 Sensor 6

+24 VDC +24 VDC

GND GND

Universal 1-wire connections

12 channels - unequaled component density
DI

Sensor 1 Sensor 2

Sensor 3 Sensor 4

Sensor 5 Sensor 6

Sensor 7 Sensor 8

Sensor 9 Sensor 10

Sensor 11 Sensor 12

+24 VDC +24 VDC

GND GND

+24 VDC +24 VDC

X20 system User's Manual 3.10 73

System features

2.17 Coated X20 system

The X20 system includes modules with a protective coating for the electronics. These modules are suitable for use
in adverse atmospheric conditions and are protected against condensation and corrosive gases.
Data sheets can be found under 5 "Coated modules".

2.18 Redundancy
The X20 system provides the following forms of redundancy:
• Controller
• Network
• Power supply modules for X20 standalone devices and expandable POWERLINK bus controllers
• X2X Link supply
The first three areas are covered in the "Redundancy for control systems" user's manual. The user's manual is
available in the Downloads section of the B&R website www.br-automation.com.
For a description of the redundant X2X Link supply, see section 3.20 "X2X Link supply".

2.19 reACTION technology

The X20 Compact CPUs and a number of I/O modules are available featuring ultrafast reACTION technology. This
allows the I/O channels integrated in the reACTION module to be controlled with response times down to 1 μs.
This new approach allows extremely time-critical subprocesses to be managed using standard hardware – which
lowers hardware costs by reducing the load on the controller and allowing it to be scaled down.
All of the commands that can be used for reACTION programs are provided as function blocks in special libraries
(e.g. AsIORTI). Programming using the standard Function Block Diagram (FBD) editor in Automation Studio is
compliant with IEC 61131-2.
Documentation for reACTION technology is included in the Automation Studio help system.

74 X20 system User's Manual 3.10

 System features

2.20 X20 system configuration

The X20 system is designed so that can be connected to standard fieldbuses (with a bus controller) or the remote
X2X Link backplane (with a bus receiver). The connection to the next station is made with a bus transmitter. Supply
modules and I/O modules are placed between the bus receiver or bus controller and the bus transmitter as needed.
The power supply system used in the X20 systems is described in the section 3.8 "The supply concept".

Bus Bus Bus Bus Bus Bus

Controller transmitter receiver transmitter receiver transmitter

Open fieldbus

X20 system X20 system X20 system

Sensors Sensors Sensors

Actuators Actuators Actuators

Figure 13: X20 system configuration

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System features

2.20.1 Fieldbus connection

Several bus controllers for standard fieldbus technologies like POWERLINK, DeviceNet, PROFIBUS, CANopen,
ModbusTCP or EtherNet/IP are available to connect X20 modules to existing control systems. Fieldbus configura-
tors transparently integrate the X20 system into the 3rd-party development environment.

Variable
Supplies the bus controller, X2X Link, and internal I/O
Bus controller power supply module X20PS940x
Bus controller fieldbus interface X20BC00xx

For X2X Link and internal I/O supply

Power supply module X20PS211x

Power supply module X20PS331x

Standard bus module X20BM11

Standard bus module X20BM11

Supply bus module X20BM01

Supply bus module X20BM01

Bus controller base X20BB80

X20BT9x00 bus transmitter

For internal I/O supply

I/O modules

Figure 14: X20 system configurator for fieldbus connection

76 X20 system User's Manual 3.10

 Bus receiver X20BR9300

Supply bus module X20BM01

X20 system User's Manual 3.10

Power supply module X20PS211x
For internal I/O supply

Supply bus module X20BM01

2.20.2 Connection to X2X Link backplane

I/O modules
Variable

Standard bus module X20BM11

Power supply module X20PS331x

For X2X Link and internal I/O supply

Supply bus module X20BM01

Figure 15: X20 system configurator for connection to X2X Link backplane
X20BT9x00 bus transmitter

Standard bus module X20BM11

The bus receiver X20BR9300 is used to connect the X20 system directly to the remote X2X Link backplane.
System features

77
Mechanical and electrical configuration

3 Mechanical and electrical configuration

3.1 Dimensions
3.1.1 X20 CPUs with one slot for interface modules

150 +0.2 85
99

Figure 16: Dimensions of the X20 CPUs with one slot

3.1.2 X20 CPUs with three slots for interface modules

200 +0.2 85
99

Figure 17: Dimensions of the X20 CPUs with three slots

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 Mechanical and electrical configuration

3.1.3 Compact CPUs and bus controllers

37.5 +0.2 75

99

Figure 18: Dimensions of the compact CPUs and bus controllers

3.1.4 Fieldbus CPUs and expandable bus controller

3.1.4.1 With an additional slot

62.5 +0.2 75
99

Figure 19: Dimensions of the fieldbus CPUs and expandable bus controller with one additional slot

3.1.4.2 With two additional slots

87.5 +0.2 75
99

Figure 20: Dimensions of the fieldbus CPUs and expandable bus controller with two additional slots

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Mechanical and electrical configuration

3.1.5 I/O modules

12.5 +0.2 75

99

Figure 21: Dimensions of the I/O modules

3.1.6 CAD support

To ensure CAD support, the dimensions are included in the ECAD macros in 2D. STEP data is available to allow
3D viewing.
The STEP data can be found in the Downloads section of the B&R website at www.br-automation.com under the
respective module.

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 Mechanical and electrical configuration

3.2 Design support

3.2.1 Macros for ECAD systems

The electronics in a machine must be designed in a way that optimizes use of available space and materials.
Graphic ECAD systems have proven themselves as the right tool for this job.
Every module in the X20 system is delivered with pre-designed electronic descriptions of the mechanical dimen-
sions, electrical signals and module functions. These macros can be loaded directly to proven ECAD systems. The
wiring plans are automatically applied by the configuration and programming system, Automation Studio. Design
and changes are immediately reflected at all levels of development. This saves time for the more important tasks
and prevents errors right from the start. The accelerated development, programming, maintenance and documen-
tation involved with the X20 system mean lower costs, enhanced quality and increased sales by earlier entry into
the market.

3.2.2 Printing support

System printers and standard identification labels are supported by the appropriate printer software. Printing can
be done manually from table calculations or directly from ECAD software (all methods are supported). The software
and printer systems correspond with the Weidmüller standard.

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Mechanical and electrical configuration

3.3 Installation
A top-hat rail conforming to the EN 60715 standard (TH35-7.5) is required to mount the PLC. The conductive top-
hat rail is fastened to the back wall of the control cabinet.
The complete system including all individual modules is hung in the desired location on the top-hat rail with the
unlocking mechanisms open and locked in place by closing the unlocking mechanisms. Finally, the modules are
equipped with the prewired terminal blocks.

Information:
Only horizontal or vertical mounting orientation is permitted.

3.3.1 Horizontal installation

10 b = n 1) · 12.5 +0.2 10

35
99
40.2

35

1)
n ... Number of modules

Figure 22: X20 system - Horizontal installation

For optimal cooling and air circulation, there must be at least 35 mm free space above the modules. To the left
and right of the X20 system, there must be at least 10 mm of free space. Underneath the modules, 35 mm space
must be left free for I/O and power supply cabling.

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 Mechanical and electrical configuration

3.3.2 Vertical installation

35 99 35

10
· 12.5 +0.2
h = n 1)
10

40.2

1)
n ... Number of modules

Figure 23: X20 system - Vertical installation

For optimal cooling and air circulation, there must be at least 35 mm free space to the left of the modules. Above
and below the X20 system, there must be at least 10 mm of free space. To the right of the modules, 35 mm space
must be left free for I/O and power supply cabling.
The modules must be arranged so that the controller is on the lower end of the system. The temperature range is
limited to -25 to 50°C when modules are mounted vertically.

Information:
The controller must be secured against slipping. An end bracket or ground terminal can be used for
securing.

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Mechanical and electrical configuration

3.4 Wiring
In order to achieve a secure connection in the terminal blocks, wires must be stripped accordingly.

7 to 9 mm

Figure 24: Wire stripping for a secure connection

Information:
The wire stripping length must not be more or less than 7 to 9 mm.

3.5 Stress relief using cable ties

Figure 25: Stress relief using cable ties

The X20 system terminal blocks have slots for the cable ties. If needed, a cable tie can be fed through these slots
to reduce the stress on the cable.
Cable tie dimensions: Width ≤ 4.0 mm
Thickness ≤ 1.2 mm

Figure 26: Slots through which the cable ties are fed

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 Mechanical and electrical configuration

3.6 Shielding
In principle, the shield must be grounded in all shielded cables:
• Analog signals (inputs and outputs)
• Interface modules
• Counter modules
• X2X Link cables
• Fieldbus connections (PROFIBUS DP, CAN bus, etc. )
In general, the following guidelines apply for shielding:
• The X20 top-hat rail must always be mounted to a conductive backplane.
• Shielded cables must be grounded on both sides.

3.6.1 Direct shielding connection

The shield is twisted and connected to the bus module's ground connection using a cable lug (2.8 x 0.5 mm). The
cable is additionally secured to the terminal block using a cable tie (stress relief).

Figure 27: Direct shielding connection

Information:
The ground connection should be made as short and with as little resistance as possible.

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Mechanical and electrical configuration

3.6.2 X20 cable shield clamp

The X20 cable shield clamp (model number X20AC0SG1) is latched to the terminal block and connected to the bus
module's ground connection using a cable lug. Cable ties are used to press the shield against the grounding plate.

Figure 28: Shielding via X20 cable shield clamp

To reduce the EMC emissions most effectively, the cable shield must be as long as possible after the cable tie
(see ① in the diagram above).

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 Mechanical and electrical configuration

3.6.3 X20 shielding bracket

The X20 shielding bracket (model number X20AC0SF9.0010) is installed below the X20 system. The shield is
pressed against the shielding bracket using ground terminals from another manufacturer (e.g. PHOENIX or WAGO)
or a cable tie.
Attaching the shield with a ground terminal Attaching the shield with a cable tie

① ①

Cable duct Cable duct

Table 5: Cable shielding via X20 shielding bracket

To reduce the EMC emissions most effectively, the cable shield must be as long as possible after the cable tie
(see ① in the diagram above).

Content of delivery
• 10 X20 shielding brackets
• Installation template

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Mechanical and electrical configuration

3.6.4 Shielding via top-hat rail or bus bar

Figure 29: Shielding via top-hat rail or bus bar

Grounding terminals from other manufacturers (such as GOGATEC) can be used to achieve shielding right on the
top-hat rail or on special bus bars directly below the controller.
• B&R recommends always using a grounding terminal via the top-hat rail to connect the X2X Link cable
shield directly with the conductive and grounded backplane. This will generally exceed the specified EMC
minimal requirements.
• The shielded cables from other modules can be grouped and clamped together. This may also be necessary
due to space limitations. A different number of cables can be grounded together with a single terminal
depending on the grounding terminals being used.
To reduce the EMC emissions most effectively, the cable shield must be as long as possible after the cable tie
(see ① in the diagram above).

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 Mechanical and electrical configuration

3.7 Wiring guidelines for X20 modules with an Ethernet cable

A number of X20 modules are based on Ethernet technology. POWERLINK cables offered by B&R can be used
for the necessary wiring.
Model number Connection type
X20CA0E61.xxxx Connection cable - RJ45 to RJ45
X67CA0E41.xxxx Attachment cable - RJ45 to M12

Table 6: POWERLINK cable with RJ45 connector

The following wiring guidelines must be observed:

• Use CAT5 SFTP cables.
• Observe minimum cable flex radius (see data sheet for the cable)
• Secure the cable underneath the bus controller. The cable must be secured vertically under the female
RJ45 connector on the bus controller.

Information:
Using POWERLINK cables offered by B&R (X20CA0E61.xxxx and X67CA0E41.xxxx) satisfies the EN
61131-2 product standard.
For any further requirements, the customer must take additional measures.

Wiring diagram

r ≥ rmin

r ≥ rmin

Figure 30: Wiring diagram for X20 modules with an Ethernet cable

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Mechanical and electrical configuration

3.8 The supply concept

Danger!
In order to guarantee a specific supply voltage, a SELV power supply that conforms to IEC 60204 must
be used to supply the bus and I/O.

3.8.1 Bus module rack replacement

Bus supply contacts

Bus data contacts

I/O supply contacts

X20BM11 X20BM01

Figure 31: The bus module replaces the rack in the X20 system
The bus module is the backbone of the X20 system regarding the bus supply and bus data as well as the I/O supply
for the electronics modules. Each bus module is an active bus station, even without an electronics module. There
are two variations of the bus module:
• Interconnected I/O supply
• I/O supply isolated to the left (for power supply modules)

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 Mechanical and electrical configuration

3.9 X20 system infrastructure

Potential group "In" Potential group "Out 1" Potential group "Out 2"

Figure 32: Simple implementation of different potential groups

Different potential groups can be implemented with the appropriate arrangement of supply bus modules, (e.g. for
input groups or different E-stop circuits on the outputs). The I/O supply is fed by power supply modules.

3.10 Bus supply

Because the remote X2X Link backplane and I/O electronics are completely electrically isolated, the X2X Link
supply needs to be fed in at certain intervals. This is initially handled by the bus receiver. A supply module for
X2X Link must be added to refresh the supply after approximately 30 modules (for an example calculation, see
3.23 "Calculating the power requirements"). On the same module, a separate feed for the I/O supply can also be
connected.

3.11 Potential groups

The I/O supply is connected via the bus modules, and the supply is fed in using corresponding power supply
modules. This makes it possible to implement simple potential groups (e.g. for input groups or different output
groups). For isolation, the corresponding bus module is also necessary, which provides isolation of the internal
I/O supply.

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Mechanical and electrical configuration

3.12 Output modules with supply

Generally, a power supply module is also necessary for current output modules with many channels, such as the 8
channel output module with 2 amp outputs. This is not the case with the X20 system. With this module, the supply
is provided directly on the module, thereby saving power supply modules and construction width.

3.13 Bus receiver with supply

The X20BR9300 bus receiver for the X20 system is equipped with a supply for X2X Link as well as for the internal
I/O supply. This eliminates the need for an additional power supply module.

3.14 Supply module for internal I/O supply

The first I/O modules in an X20 system are supplied by the bus receiver. The internal I/O supply is refreshed via
the X20PS2100 power supply module.

3.15 Power supply module for internal I/O supply and bus supply
The X2X Link is fed by the X20BR9300 bus receiver. After approx. 30 modules (see section 3.23 "Calculating the
power requirements" for a calculation example), the supply must be "refreshed". The X20PS3300 power supply
module is used for this. This module is equipped with a feed for X2X Link as well as for the internal I/O supply.

3.16 Bus transmitter with supply

The X20BT9100 bus transmitter has an integrated I/O supply feed. This saves a power supply module for the last
potential group.

3.17 Internal I/O supply failure (ModuleOk)

The ModuleOk status for monitoring the X20 modules is made up of different module parameters. A loss of voltage
in modules that are supplied via the internal I/O supply causes the ModuleOk data point to return the value 0 (false).
This affects all modules that require 0.01 W on X2X Link.

3.18 X20 system power supply

The X20 system is powered by a B&R 24 VDC power supply. B&R power supplies ensure that control systems
are reliably supplied even when operated at the minimum mains input voltage or when maximum power is output
even if there are temporary power failures (≤10 ms).

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3.19 X20 system protection

The protection for the X20 system depends on the supply concept.

3.19.1 Potential groups

Using the X20BM01 bus module and organizing the power supply bus modules accordingly allows various potential
groups to be implemented (e.g. for input groups or various power circuits for the outputs).

BR9300 + BM01

PS2100 + BM01

PS2100 + BM01
X2X
I/O I/O I/O
Link

1 A slow-blow 1)

10 A slow-blow 10 A slow-blow 10 A slow-blow

U1/24 VDC

U2/24 VDC

Figure 33: Protecting various potential groups

1) Recommended for line protection.

3.19.2 Supply via bus transmitter

The bus transmitter has an integrated internal I/O supply feed. This saves a power supply module for the last
potential group.
Keep in mind: this potential group is separated from the rest of the potential groups by an I/O module with the
bus module.
I/O module + BM01
BR9300 + BM01

PS2100 + BM01

BT9x00 + BM11

X2X
I/O I/O I/O
Link

1 A slow-blow 1) 10 A slow-blow 10 A slow-blow 10 A slow-blow

U1/24 VDC

U2/24 VDC

Figure 34: Protection when supplied via bus transmitter

1) Recommended for line protection.

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Mechanical and electrical configuration

3.20 X2X Link supply

3.20.1 Extended and redundant X2X Link supply

The X2X Link remote backplane is supplied separately from the I/O points. This ensures that the remote backplane
doesn't fail if there is a power failure on the I/O side, for example with an emergency stop. After approx. 30 modules,
it is necessary to "refresh" with a power supply module for X2X Link.
To achieve increased supply security, it is possible to set up a redundant X2X Link supply. To do so, the necessary
X2X Link power must be determined and then covered by the corresponding quantity plus at least one additional
X2X Link power supply module. This guarantees the functionality of the remote backplane even if the X2X Link
supply fails.
Please note the following for the correct calculation:
• To determine the necessary X2X Link power, calculate using 75% of the power supply module's rated
power during parallel operation.

Information:
This must be done for all power supply modules at the same time for a non-redundant X2X Link supply
or when completely turning the X2X supply of an X20 module block on/off.

3.20.2 Example for extended X2X Link supply

It is possible to set up potential groups through the use of different supplies for the power supply modules.
BR9300 + BM01

PS2100 + BM01

PS3300 + BM01

X2X X2X
I/O I/O I/O
Link Link

1 A slow-blow 1) 1 A slow-blow 1)

10 A slow-blow 10 A slow-blow 10 A slow-blow

U1/24 VDC

U2/24 VDC

Figure 35: Example for extended X2X Link supply

1) Recommended for line protection.

The X20PS3300 power supply module supplies both the X2X Link and I/O; the X20PS2100 power supply module
only supplies the I/O.

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 Mechanical and electrical configuration

3.20.3 Example for redundant X2X Link supply

Multiple X20PS3300 power supply modules can be set up in parallel. It is possible to set up potential groups through
the use of different supplies.

BR9300 + BM01

PS3300 + BM01

PS3300 + BM01
2)

X2X X2X X2X

I/O I/O I/O
Link Link Link

1 A slow-blow 1) 1 A slow-blow 1) 1 A slow-blow 1)

10 A slow-blow 10 A slow-blow 10 A slow-blow

U1/24 VDC

U2/24 VDC

Figure 36: Example for redundant X2X Link supply

1) Recommended for line protection.
2) With separate supplies, the two reference potentials (GND_1 and GND_2) are combined via the terminal block on the PS3300.

The X20PS3300 power supply module supplies both X2X Link and the I/O.

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3.21 Safe cutoff

3.21.1 General information

The operating principle "Safe cutoff of a potential group" allows the user to implement safety functions that satisfy
the requirements of ISO 13849 within a B&R system when using an external safety relay.
The safety function is limited to cutting off or interrupting the power to the connected actuators.
Functionality
An external safety relay is connected to the I/O supply for the potential group. When the functional safe state is
requested or a "Failsafe" state occurs, then this safety relay cuts off the I/O supply of the potential group. The
power is then also cut off for all actuators connected to this potential group.

3.21.2 Scope of application / Standards referenced

The operating principle is confined to machine manufacturing applications, and therefore implicitly to the following
standards:
• ISO 13849-1:2007 and ISO 13849-2:2013
Requirements of other standards are not taken into consideration.

3.21.3 Intended use

It is the user's responsibility to clarify guidelines for the use of safety-related B&R components with the respective
authorities and to ensure these guidelines are met.
B&R will not assume warranty or liability for damages that occur due to:
• Improper use
• Non-observance of standards and guidelines
• Unauthorized modifications to devices, connections and settings
• Operation of unauthorized or unsuitable devices or device groups
• Failure to follow the safety notices covered in this manual
• Malfunctions caused by the external safety relay

3.21.4 Qualified personnel

Safety functionality is only permitted to be implemented by personnel with appropriate training in safety technology
and knowledge of applicable regulatory and technical requirements.
Use of safety-related products is restricted to the following persons:
• Qualified personnel who are familiar with relevant safety concepts for automation technology as well as
applicable standards and regulations
• Qualified personnel who plan, develop, install and commission safety equipment in machines and systems
Qualified personnel in the context of this manual's safety guidelines are those who, because of their training,
experience and instruction combined with their knowledge of relevant standards, regulations, accident prevention
guidelines and operating conditions, are qualified to carry out essential tasks and recognize and avoid potentially
dangerous situations.
In this regard, sufficient language skills are also required in order to be able to properly understand this manual.

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 Mechanical and electrical configuration

3.21.5 Application in the X20 system

The operating principle applies to a potential group in the X20 system. For information about how to create a
potential group in the X20 system, see section 3.11 "Potential groups".
When implementing the operating principle, each X20 potential group must be supplied by a single power supply
module. Only X20BM01, X20BM23 and X20BM26 modules that guarantee the interruption of the internal I/O supply
to the left are permitted for use as bus modules for the power supply module. This ensures that each potential
group in the X20 system will receive power from exactly one power supply module and prevents the possibility
of multiple power sources.

3.21.5.1 Suitable modules

The operating principle is supported by the following X20 modules:

Module group Module Starting with
revision
Bus modules X20BM01 X20 power supply bus module, 24 VDC keyed, internal I/O supply interrupted to the left D0
X20BM11 X20 bus module, 24 VDC keyed, internal I/O supply continuous D0
X20BM23 X20 power supply bus module, for X20 SafeIO power supply modules, internal I/O supply inter- B0
rupted to the left
X20BM26 X20 power supply bus module, for X20 SafeIO power supply modules, with node number switch, B0
internal I/O supply interrupted to the left
Power supply mod- X20PS2100 X20 power supply module, for internal I/O supply F0
ules X20PS2110 X20 power supply module for internal I/O supply, integrated microfuse C0
Digital outputs X20DO2322 X20 digital output module, 2 outputs, 24 VDC, 0.5 A, source, 3-wire connections F0
X20DO4322 X20 digital output module, 4 outputs, 24 VDC, 0.5 A, source, 3-wire connections F0
X20DO4332 X20 digital output module, 4 outputs, 24 VDC, 2 A, source, 3-wire connections F0
X20DO6321 X20 digital output module, 6 outputs, 24 VDC, 0.5 A, sink, 2-wire connections F0
X20DO6322 X20 digital output module, 6 outputs, 24 VDC, 0.5 A, source, 2-wire connections F0
X20DO8232 X20 digital output module, 8 outputs, 12 VDC, 2 A, source, feed directly on module, 1-wire con- E0
nections
X20DO8322 X20 digital output module, 8 outputs, 24 VDC, 0.5 A, source, 1-wire connections E0
X20DO8332 X20 digital output module, 8 outputs, 24 VDC, 2 A, source, feed directly on module, 1-wire con- G0
nections
X20DO9321 X20 digital output module, 12 outputs, 24 VDC, 0.5 A, sink, 1-wire connections E0
X20DO9322 X20 digital output module, 12 outputs, 24 VDC, 0.5 A, source, 1-wire connections H0
Digital signal process- X20DS1119 X20 multifunctional digital signal processor, 3 digital channels 5 V (symmetric) configurable as F0
ing and preparation inputs or outputs, 2 digital input channels 24 V (asymmetric), max. 2 event counters, 1 univer-
sal counter pair configurable as A/B or up/down counter, linear movement generator (A/B, direc-
tion/frequency) with 1 reference pulse, 1 SSI absolute encoder, NetTime module
X20DS1319 X20 multifunctional digital signal processor, 4 digital input channels, 4 digital channels config- D0
urable as inputs or outputs, 2 event counters, 1 universal counter pair configurable as A/B or
up/down counter, linear movement generator (A/B, direction/frequency) with max. 2 reference
pulses, SSI absolute encoder, NetTime module
X20DS4389 X20 digital signal module, 4 digital inputs, 24 VDC, 4 digital outputs, 24 VDC, 0.1 A, oversampling B0
I/O functions, time-triggered I/O functions, NetTime module
Analog outputs X20AO2622 X20 analog output module, 2 outputs, ±10 V or 0 to 20 mA / 4 to 20 mA, 13-bit converter resolution H0
X20AO2632 X20 analog output module, 2 outputs, ±10 V or 0 to 20 mA, 16-bit converter resolution F0
X20AO4622 X20 analog output module, 4 outputs, ±10 V or 0 to 20 mA / 4 to 20 mA, 13-bit converter resolution H0
X20AO4632 X20 analog output module, 4 outputs, ±10 V or 0 to 20 mA, 16-bit converter resolution I0
Counter functions X20DC2395 X20 digital counter module, 1 SSI absolute encoder, 24 V, 1 ABR incremental encoder, 24 V, 2 F0
AB incremental encoders, 24 V, 4 event counters or 2 PWM, local time measurement function
X20DC4395 X20 digital counter module, 2 SSI absolute encoder, 24 V, 2 ABR incremental encoder, 24 V, 4 G0
AB incremental encoders, 24 V, 8 event counters or 4 PWM, local time measurement function
Additional functions X20CM8323 X20 PWM module, 8 digital outputs for switching electromechanical loads, 0.6 A continuous cur- F0
rent, 2 A peak current, current monitoring, switching time detection
Motor controllers X20MM2436 X20 PWM motor module, 24 to 39 VDC ±25%, 2 PWM motor bridges, 3 A continuous current, D0
3.5 A peak current, 4 digital inputs 24 VDC, sink, configurable as incremental encoder
X20SM1426 X20 stepper motor module, 1 motor connection, 1 A continuous current, 1.2 A peak current, 4 C0
digital inputs 24 VDC, sink, can be configured as incremental encoder
X20SM1436 X20 stepper motor module, module supply 24-39 VDC ±25%, 1 motor connection, 3 A continuous D0
current, 3.5 A peak current, 4 digital inputs 24 VDC, sink, can be configured as incremental
encoder

Table 7: List of X20 modules

The operating principle of the X20 system has been tested by TÜV Süd, with the results documented under report
number BE85906T.

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3.21.6 General notices

3.21.6.1 Installation notes

Modules must be protected against impermissible dirt and contaminants. The maximum permissible level of dirt and
contaminants is Pollution Level II as specified in the IEC 60664 standard. This can be achieved through installation
in a control cabinet that provides IP54 protection.
When using the operating principle, uncoated X20 modules must not be operated in condensing relative humidity
or with ambient temperatures below 0°C.

3.21.6.2 Timing

3.21.6.2.1 Worst case scenario

A maximum cutoff time of 500 ms must be assumed for the potential group for worst case scenarios. This time is
needed to guarantee that energy stored within the module is discharged and the actuators are cut off in worst case
scenarios. The cutoff times needed for the upstream external safety relay and actuator must also be added.
Worst case conditions for "Output = Off"
• Digital output: <5 V
• Analog output: <100 mV

3.21.6.2.2 Load-dependent cutoff time

The actual duration of cutoff can be calculated with the following formula.

tspec Actual cutoff time

Ctot Total capacity of all modules in the potential group. (e.g. 10 modules 47 µF + 3 modules with 150 µF → Ctot = 920 µF)
Uin Supply voltage
Uoff Voltage, if Output = Off
Iload External load

Table 8: Parameter descriptions

Module Module's internal capacity
X20MM2436 150 µF
X20SM1426
X20SM1436
Other modules 1) 47 µF

1) Only modules from section 3.21.5.1 "Suitable modules".

If the result is tspec = >500 ms, then the worst-case assumption from section 3.21.6.2.1 "Worst case scenario" applies.

Information:
• The calculated load-dependent cutoff time must be verified by a test measurement!
• At the time a safety function is requested, there is no guarantee that the outputs used to cal-
culate the load-dependent cutoff time are enabled. For example, if an output is disabled at the
time of a request, then the respective internal capacities in the module will not be discharged
in the calculated time (tspec). The worst-case time of 500 ms should be taken into account in this
situation. If the output is enabled from the functional application (shown in the sketch as the
interval tapplication) during the worst-case time (<500 ms), then the output subsequently remains
enabled for the calculated time.

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Safety function request

U

Uin

Worst-case cutoff
Load-dependent cutoff

Uoff

Time
t application t spec

Worst-case time = 500 ms

Figure 37: Output behavior following safety request

3.21.6.3 Potential group structure

The potential group can be made up only of modules in accordance with the table in section 3.21.5.1 "Suitable
modules". Modules not listed in this table would compromise the "absence of feedback" of the external cutoff and
therefore put the safety function at risk.
To ensure clarity and that the external cutoff is triggered when a fault occurs, installing multiple power supply
sources in a potential group is not permitted.
SELV/PELV power supplies must be used for both the bus supply (X2X) and the module supply; otherwise, safe-
ty-related malfunctions can occur due to overvoltages.
For modules with isolated I/O potential for sensors and actuators, the upstream safety relay must shut off the supply
for both the sensors and actuators; otherwise, energy regeneration cannot be excluded.

3.21.6.4 Circuit examples

1. One-channel without feedback

The following example shows a load being cutoff using the E-stop safety function. Only error-free actuators such
as a motor or the "Enable" input of an ACOPOS / ACOPOSmulti drive may be used as the load in this case.
This type of circuit is not permitted for defective actuators such as relays since here the lack of feedback makes
it impossible to detect contact sticking.

Power supply
X20 module
for +24 VDC potential group
23 24 (inputs and outputs)

Reference potential for

+24 VDC Safety GND potential group, 0 VDC Outputs Load
13 relay 14 (inputs and outputs)

E-stop

Figure 38: Circuit example 1: "One-channel without feedback"

Provided that the external components used (E-stop button, safety relay, load) satisfy the respective requirements,
this example can achieve PL e (performance level as specified in ISO 13849).

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2. Two-channel with feedback

The following example shows a load being cutoff using the E-stop safety function. Thanks to the feedback, errors
in the actuator are detected, and with the full two-channel circuit, the cutoff is ensured even in the event of an
error. Whether or not two fully isolated potential groups – as shown in the example – are necessary depends on
the application and how the safety solution is designed.

Power supply +24 VDC

X20 module
for +24 VDC potential group
X1
(inputs and outputs)
23 24
Reference potential for
+24 VDC GND potential group, 0 VDC Outputs
13 14 (inputs and outputs)
Safety
relay

Power supply
X20 module
for +24 VDC potential group
(inputs and outputs)
X2
E-stop Reference potential for
GND potential group, 0 VDC Outputs
(inputs and outputs)

Load

Figure 39: Circuit example 2: "Two-channel with feedback"

Provided that the external components used (E-stop button, safety relay, load) satisfy the respective requirements,
this example can achieve PL e.
3. Example with X20SP1130 power supply module
The following example shows a load being cutoff using an X20SP1130 safe power supply module and an
X20SI4100 safe input module together with the "E-stop" safety function.

X20DO2322

X20SI4100 X20SP1130

Load

E-stop

+
+24 VDC

Figure 40: Circuit example 3: With X20SP1130 power supply module

X20DO8332

X20SI4100 X20SP1130

Load

E-stop

+
+24 VDC

Figure 41: Circuit example 3: With X20SP1130 power supply module and X20DO8332
Provided that the external components used (E-stop button, load) satisfy the respective requirements, this example
can achieve PL e.

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3.21.6.5 Wiring notices

The operating principle "Safe cutoff of a potential group" only applies to the B&R modules used. All other parts
of the safety chain, such as the application, upstream sensors or downstream actuators are NOT included in this
principle.
For this reason, it is important to take the following points into consideration:
• Ensure proper wiring of the safety relay with the I/O supply. A short circuit between the output of the safety
relay and an external 24 V voltage source can cause an unintended supply of 24 V to the internal supply
voltage of the potential group. As a result, the safety function can no longer be guaranteed, which means
that ALL of the channels in the potential group can no longer be cut off by the upstream safety switching
device.
• Make sure that ALL of the potential group's input and output channels and the connected sensors and
actuators are wired properly. A short circuit between an input or output of the potential group and an external
24 V voltage source can cause the unintended feedback of 24 V to the internal supply voltage of the
potential group. As a result, the safety function can no longer be guaranteed, which means that ALL of the
output channels in the potential group can no longer be cut off by the upstream safety relay.
• In accordance with EN ISO 13849-2:2013, Appendix D.2, Table D.4, a short circuit between any two con-
ductors can be excluded, provided that:
° they are permanently connected and protected against external damage (e.g. using a cable duct
or armored conduit)
° OR they are in separate plastic-sheathed cables
° OR they are installed within an electrical enclosure (provided that both the conductors and the
enclosure meet the appropriate requirements [see EN 60204-1 (IEC 60204-1)])
° OR they are individually shielded with a ground connection

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3.21.7 Safety guidelines

This section provides a summary of safety notices for the user.

Danger!
Please observe the following safety notices. Failure to observe one of the following notices can lead
to loss of safety functionality and may result in serious injury.
• The safety relay determines which category (according to ISO 13849) is achieved.
• When using the operating principle, it is the user's responsibility to adhere to the relevant
standards and safety directives. The notices provided in sections 3.21.1 "General information"
through 3.21.4 "Qualified personnel" regarding functionality, applicable standards, proper use
and qualified personnel are also to be observed.
• The safety function is limited to cutting off or interrupting the power to connected devices.
Safety functions that require actively powering on an actuator in a safe state cannot be imple-
mented with this function.
• For all potentials supplying the modules, SELV/PELV power supplies must be used.
• The potential groups for which the operating principle is applied must only contain modules
listed in the table in section 3.21.5.1 "Suitable modules".
• When using the operating principle with uncoated X20 modules, the modules must not be op-
erated in condensing relative humidity or with ambient temperatures below 0°C.
• It is not permitted to mix modules from different systems (X20, X67) within a potential group.
• It is not permitted to install multiple power supply modules in a potential group (particularly
with regard to power supply modules that also supply the bus supply).
• Ensure that the upstream safety relay is wired properly.
• Ensure that ALL sensors and actuators connected to the potential group are wired properly.
• Be aware of the maximum safety-related response time of 500 ms when shutting down the
potential group. The cutoff times needed for the upstream external safety relay and actuator
must also be added. Using the formulas defined in section 3.21.6.2.2 "Load-dependent cutoff
time", it is possible to achieve cutoff times under 500 ms.
• The calculated load-dependent cutoff time must be verified by a test measurement!
• For modules with isolated I/O potential for sensors and actuators, the upstream safety relay
must shut off the supply for both the sensors and actuators.
• The ground connections should be used as functional ground and not as protective ground
and must not be connected to the 24 V supply voltage (GND is permitted). There must not be
any protective components between the ground and the 24 V supply voltage.

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3.22 Combining X2X Link systems

3.22.1 General information

The X2X Link provides a complete remote backplane, which is used for communicating between bus modules and
over the X2X Link cable. Systems based on X2X Link can be combined with one another as needed.

3.22.2 Connection overviews

The following connection overviews illustrate combinations of different systems that are based on X2X Link. The
model numbers indicate which standard cables available from B&R can be used to connect with one another.

3.22.2.1 Combining X20, X67 and compact I/O system

X2X Link X2X Link X2X Link X2X Link X2X Link X2X Link
Attachment cable Connection cables Open cables Attachment cable Open cables Attachment cable
X67CA0X21.xxxx X67CA0X01.xxxx X67CA0X41.xxxx X67CA0X21.xxxx X67CA0X41.xxxx X67CA0X21.xxxx
X67CA0X31.xxxx X67CA0X11.xxxx X67CA0X51.xxxx X67CA0X31.xxxx X67CA0X51.xxxx X67CA0X31.xxxx

X67PS1300 X67 I/O X67 I/O X20 system X67PS1300 X67 I/O X67 I/O

I/O supply I/O supply 24 V Compact

24 V
Attachment cable Connection cables 24 V I/O system
X67CA0P20.xxxx X67CA0P00.xxxx
X67CA0P30.xxxx X67CA0P10.xxxx
24 V

Figure 42: Connection overview - Combining X20, X67 and compact I/O system

3.22.2.2 Combining X20, X67 and valve terminal connections

X2X Link X2X Link X2X Link X2X Link X2X Link
Attachment cable Connection cables Open cables Attachment cable Open cables
X67CA0X21.xxxx X67CA0X01.xxxx X67CA0X41.xxxx X67CA0X21.xxxx X67CA0X41.xxxx
X67CA0X31.xxxx X67CA0X11.xxxx X67CA0X51.xxxx X67CA0X31.xxxx X67CA0X51.xxxx

IP67 XV IP20 XV
X67PS1300 X67 I/O X20 system X67PS1300 X67 I/O

I/O supply I/O supply 24 V I/O supply

24 V
Attachment cable Connection cables Open cables
X67CA0P20.xxxx X67CA0P00.xxxx X67CA0P40.xxxx
X67CA0P30.xxxx X67CA0P10.xxxx X67CA0P50.xxxx
24 V With 7XVxxx.xx-21

Figure 43: Connection overview - Combining X20, X67 and valve terminal connections

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3.22.3 Connection examples

3.22.3.1 X20 system

Connection examples are listed in the module description:

• X20BR9300 bus receiver: 604
• X20BT9100 bus transmitter: 609

3.22.3.2 Compact I/O system

1)
X2X+ (optional)

1
1)
X2X+ (optional)

2
In: X2X White

3
In: X2X⊥ Black

4
In: X2X\ Blue

5
Shield

6
Out: X2X White

7
Out: X2X⊥ Black

8
Out: X2X\ Blue

9 10 11 12
+ Shield
+24 VDC supply
Supply ⊥
-

1) Used to forward the X2X Link supply when using IP67 modules.
Signal Cable type Model number
X2X Link In Open cables1) X67CA0X41.xxxx
X67CA0X51.xxxx
X2X Link Out Attachment cable1) X67CA0X21.xxxx
X67CA0X31.xxxx
X2X Link in/out Cable for custom assembly, 100 m X67CA0X99.1000

Table 9: Compact I/O system - Connection example

1) Bridge for X2X+ in connection with X67 modules.

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3.22.3.3 Valve connection

Connection example with 7XVxxx.xx-11/-12

Bend red wire end back and insulate
(e.g. with heat shrink tubing)

In: X2X White

1
In: X2X⊥ Black

2
In: X2X\ Blue

3
Shield

4
Out: X2X White

5
Out: X2X⊥ Black

6
Out: X2X\ Blue

7
Shield

8
+24 VDC for X2X Link

9 10 11
+ Supply ⊥
+24 VDC for I/O
X2X Link and -
-
I/O supply

Signal Cable type Model number

X2X Link In Open cables1) X67CA0X41.xxxx
X67CA0X51.xxxx
X2X Link Out Attachment cable1) X67CA0X21.xxxx
X67CA0X31.xxxx
X2X Link in/out Cable for custom assembly, 100 m X67CA0X99.1000

Table 10: Connection example for valve connection (7XVxxx.xx-11/-12)

1) In connection with X67 modules.

Connection example with 7XVxxx.xx-21

In: X2X White

1

In: X2X⊥ Black

2

In: X2X\ Blue

3

Shield
4

Out: X2X White

5

Out: X2X⊥ Black

6

Out: X2X\ Blue

7

Shield
8

X2X+ Red
9 10 11

I/O supply Supply ⊥ Blue and black

+24 VDC supply Brown and white

Signal Cable type Model number

X2X Link In Open cables1) X67CA0X41.xxxx
X67CA0X51.xxxx
X2X Link Out Attachment cable1) X67CA0X21.xxxx
X67CA0X31.xxxx
X2X Link in/out Cable for custom assembly, 100 m X67CA0X99.1000
I/O supply Open cables1) X67CA0P40.xxxx
X67CA0P50.xxxx

Table 11: Connection example for valve connection (7XVxxx.xx-21)

1) In connection with X67 modules.

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Connection example with 7XVxxx.xx-51/-62

X2X Link X2X Link

STATUS 2 STATUS 1

Module supply Module supply

Supply Routing

Signal Cable type Model number

X2X Link Connection cables1) X67CA0X01.xxxx
X67CA0X11.xxxx
I/O supply Connection cables1) X67CA0P00.xxxx
X67CA0P10.xxxx

Table 12: Connection example for valve connection (7XVxxx.xx-51/-62)

1) In connection with X67 modules.

3.23 Calculating the power requirements

Overview of I/O supply
The power necessary for operation is provided by the power supply modules, the X20 CPU, the bus receivers and
the bus transmitters.
Module I/O internal power Bus power
X20CP148x, X20CP158x, X20CP358x +240 W +7 W
X20BR9300 +240 W +7 W
X20PS2100 +240 W -0.2 W
X20PS2110 +144 W -0.2 W
X20PS3300 +240 W +7 W
X20PS3310 +144 W +7 W
X20PS9xxx +240 W +7 W

Bus transmitter
When calculating the power requirements for bus transmitters, it is important to know whether they are only being
used as such or are also being used as an I/O power supply module.
Model number I/O internal power Bus power
When operated as When operated as a
a bus transmitter bus transmitter and I/
O power supply module
X20BT9100 -0.1 W +240 W -0.5 W
X20BT9400 -0.1 W +240 W -0.5 W

Table 13: Overview of bus transmitter power

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 Mechanical and electrical configuration

Information about power consumption

The power consumption of individual modules can be found on the respective technical data sheet. Information
about power consumption can be found in the technical data under "General information - Power consumption".
• The value in the "Internal l/O" row refers to the internal power requirements of the I/O module covered by
the 24 VDC I/O supply.
• The value specified in the "Bus" row refers to the X2X Link power balance.
These rows can be used to quickly and easily create a power balance for a certain hardware configuration. The
power consumption values of individual modules should then be subtracted from the power provided by the power
supply module. The sum is not permitted to be less than zero.

Information:
For a calculation example, see 3.23.1 "Example 1" and 3.23.2 "Example 2".
Embedded parameter chip
On modules with 0.01 W power requirements, it is only possible to read the embedded parameter chip if the I/
O supply is also active. Information about the embedded parameter chip can be found in the 2.12 "Embedded
parameter chip" section.

3.23.1 Example 1

Calculating the power requirements for the bus and 24 VDC I/O supply with the following hardware configuration:
Module Bus power [W] I/O-internal power [W] I/O-external power [W] Sensor/Actuator supply [W]1)
X20DI4371 0.14 0.59 - 12.00
X20DI2371 0.12 0.29 - 12.00
X20DO4322 0.16 0.49 48.002) 12.00
X20DO4322 0.16 0.49 48.002) 12.00
X20BT9100 0.50 0.10 - -
Subtotal 1.96 96.00 48.00
Total 1.08 145.96
(=1.96 + 96.00 + 48.00)

1) Rated power at 24 VDC and 0.5 A.

2) Rated power at 24 VDC and 100% simultaneity.

The total power to be supplied by the 24 VDC I/O power supply is 145.86 W. One power supply module is already
integrated in the X20BR9300 bus receiver. The power comparison indicates that the power provided by the power
supply module is sufficient.
Bus power [W] Power 24 VDC I/O supply [W]
X20BR9300 +7.00 +240.001)
Power requirements of I/O modules -1.08 -145.96
Power requirements of all bus modules -0.78 -
Remaining power +5.14 +94.04

1) Rated power at 24 VDC and 10 A.

3.23.2 Example 2

The I/O modules are divided into 3 potential groups in this example:
Potential group 1 Potential group 2 Potential group 3
Digital input modules Digital output modules Analog input modules and temperature modules

Calculating the power requirements for the bus and 24 VDC I/O supply per potential group with the following
hardware configuration:
Potential group 1
Module Bus power [W] I/O-internal power [W] I/O-external power [W] Sensor/Actuator supply [W]1)
X20DI6371 0.15 0.88 - -
X20DI6371 0.15 0.88 - -
X20DI2377 0.15 0.82 - 12.00
Subtotal 2.58 - 12.00
Total 0.45 14.58
(= 2.58 + 12.00)

1) Rated power at 24 VDC and 0.5 A.

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Potential group 2
Module Bus power [W] I/O-internal power [W] I/O-external power [W]1) Sensor/Actuator supply [W]2)
X20DO2322 0.13 0.33 24.00 12.00
X20DO6322 0.18 0.71 72.00 -
X20DO8332 0.22 - -3) -
Subtotal 1.04 96.00 12.00
Total 0.53 109.04
(=1.04 + 96.00 + 12.00)

1) Rated power at 24 VDC and 100% simultaneity.

2) Rated power at 24 VDC and 0.5 A.
3) The power supply is integrated in the module.

Potential group 3
Module Bus power [W] I/O-internal power [W] I/O-external power [W] Sensor/Actuator supply [W]
X20AI4622 0.01 1.10 - -
X20AI4622 0.01 1.10 - -
X20AT4222 0.01 1.10 - -
X20AT2402 0.01 0.72 - -
X20BT9100 0.50 0.10 - -
Subtotal 4.12 - -
Total 0.54 4.12

It is then necessary to perform a power comparison between the power needed by the I/O modules and the power
supplied by the power supply modules.

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 Mechanical and electrical configuration

Potential group 1 is supplied by the supply module integrated in the X20BR9300 bus receiver. The total power
supplied by the bus, including all bus modules, is 3.04 W (= 1.22 W +1.82 W). The total amount of power that must
be provided for the potential group 1 via the 24 VDC I/O supply is 14.58 W.
The power comparison indicates that the power provided by the power supply module integrated in the X20BR9300
is sufficient.
Potential group 1 Bus power [W] Power 24 VDC I/O supply [W]
X20BR9300 +7.00 +240.001)
Power requirements of I/O modules -1.222) -14.583)
Power requirements of all bus modules -1.82 -
Remaining power +3.96 +225.42

1) Rated power at 24 VDC and 10 A.

2) Bus power to be supplied for all I/O modules (i.e. sum of the bus power of all potential groups).
3) 24 VDC I/O supply to be provided for potential group 1.

In potential groups 2 and 3, the 24 VDC I/O supply is fed via the X20PS2100 power supply module. One power
supply module is needed for each potential group.
The power comparison indicates that the power provided by the X20PS2100 is sufficient.
Potential group 2 Power 24 VDC I/O supply [W]
X20PS2100 +240.001)
Power requirements of I/O modules -109.04
Remaining power +130.96

1) Rated power at 24 VDC and 10 A.

Potential group 3 Power 24 VDC I/O supply [W]

X20PS2100 +240.001)
Power requirements of I/O modules -4.12
Remaining power +235.88

1) Rated power at 24 VDC and 10 A.

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Mechanical and electrical configuration

3.24 Power supply module power loss

3.24.1 General information

Power supply modules are used to provide power to an X20 system. The power supply modules are either a
separate module or part of a CPU or a bus controller.
The power consumed by the power supply modules is passed on to the X20 system, taking into consideration
its own power requirements and the effectiveness of the power supplies. The data sheets for the power supply
modules list their own power requirements and power loss (as maximum power consumption). With the formulas
in the following sections, the exact power consumption can also be calculated. This calculation is explained using
an example.
The following image shows where the power supply module uses power for its own requirements. It also shows
where the power supply module uses power to supply the system and where power loss occurs.

Power consumption - Bus

Power consumption - X2X Link Power consumption - I/O

Figure 44: Power supply modules draw power at up to three supply points

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 Mechanical and electrical configuration

3.24.2 Power supply modules without X2X Link supply

Module Power consumption - Bus [W] Power consumption - I/O-internal [W] Power consumption -
X67 X2X Link-internal [W]
X20PS2100 0.2 0.1 + IIO2 × 0.005 -
X20PS2110 0.2 0.1 + IIO2 × 0.02 -
X20BT9100 0.5 0.1 + IIO2 × 0.005 -
X20BT9400 0.5 0.1 + IIO2 × 0.005 0.5 + 0.11 × ΣX67

Table 14: Power consumption of power supply modules without X2X Link supply
II/O ... I/O summation current of all I/O modules supplied by this power supply module
ΣX67 ... Sum of X67 modules (max. = 8)

3.24.3 Power supply module with X2X Link supply

Module Power consumption - Bus [W] Power consumption - I/O-internal [W] Power consumption -
X2X Link-internal [W]
X20PS3300, X20PS9400,
X20PS9500,
0.2 0.1 + IIO2 × 0.005
X20CP1483, X20CP1483-1,
X20CP158x, X20CP358x
X20PS3310
0.2 0.1 + IIO2 × 0.02

X20BR9300
0.4 0.1 + IIO2 × 0.005

X20PS9402, X20PS9502 0.2 0.1 + IIO2 × 0.005 0.6 + 0.12 × ΣPX2X

Table 15: Power consumption of power supply modules with X2X Link supply
ΣPX2X ... Sum of the bus power consumption of all modules in the X20 system (compact CPU, fieldbus CPU, BC, BR, I/O, BM, BT)
n ... Number of all power supply modules in the X20 system with X2X Link supply, including X20BR9300
II/O ... I/O summation current of all I/O modules supplied by this power supply module

3.24.4 Power supply module for X20 standalone devices

Module Power consumption [W]
X20PS8002 0.5 + 0.12 × POut

Table 16: Power consumption of power supply module for X20 standalone devices
POut ... Sum of power consumption values of all modules (HB) supplied by the power supply module

3.24.5 Potential distribution modules

Module Power consumption - Bus [W] Power consumption - I/O [W]
X20PD0011, X20PD0012 0.12 0.15 + IIO2× 0.02
X20PD0016, X20PD2113 0.12 0.28 + IIO2× 0.02

Table 17: Power consumption of potential distributor modules

II/O ... PD0011, PD0012, PD0016, PD2113 with internal supply
II/O corresponds to the sum of all load currents.

PD2113 with external supply (power supply module)

If the X20PD2113 module is being used as a power supply module, then II/O corresponds to the summation current of all I/O modules supplied
by the X20PD2113.

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Mechanical and electrical configuration

3.24.6 Example

Calculating the total internal power consumption of a BR9300 bus receiver with the following hardware configura-
tion:
Module Bus power [W] I/O-internal power [W]
X20DI4371 0.14 0.59
X20DI2371 0.12 0.29
X20DO4322 0.16 0.49
X20DO4322 0.16 0.49
X20BT9100 0.50 0.10
Total 1.08 1.96

Two power values have to be calculated in order to determine the entire internal power consumption of the bus
receiver.
• Internal X2X Link power consumption of the X20BR9300
• Internal I/O power consumption of the X20BR9300

3.24.6.1 Calculating the internal X2X Link power consumption of the X20BR9300

Bus power consumption of all modules in the X20 system

The sum of the bus power consumption from all of the modules in the X20 system is necessary in order to calculate
the internal X2X Link power consumption of the X20BR9300.
The sum for the example configuration is calculated using the following formula: The bus module of the X20BR9300
does not have to be taken into account in the calculation. The power consumption of the bus module is already
included with a factor of 0.8 (see formula below).
A power consumption of 0.13 W for each bus module must be included in the calculation for the 4 I/O modules
and the bus transmitter.

Internal X2X Link power consumption of the X20BR9300

The internal X2X Link power consumption of the X20BR9300 is calculated using the following formula. Since X2X
Link is only supplied by the X20BR9300 bus receiver, the factor is n = 1:

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 Mechanical and electrical configuration

3.24.6.2 Calculating the internal I/O power consumption of the X20BR9300

The I/O summation current of all I/O modules supplied by the X20BR9300 is needed to calculate the internal I/O
power consumption. The I/O summation current is composed of three parts:
• Internal power consumption of the I/O modules
• Sum of the output currents
• Sum of the actuator currents

Internal power consumption of the I/O modules

The current that results from the internal consumption of the I/O modules is calculated according to the following
formula:

Sum of output and actuator currents

Two X20DO4322 modules are included in the example configuration. The following images show which outputs
are wired and how high the output current and actuator current are per channel.
Connections and currents of the first X20DO4322:

DO

0.35 A 0.4 A
Actuator 1

Actuator 2
0.1 A 0.08 A

0.5 A 0.3 A
Actuator 4
Actuator 3

0.15 A 0.09 A

+24 VDC +24 VDC

GND GND

Figure 45: Connections and currents of the first X20DO4322

X20 system User's Manual 3.10 113

Mechanical and electrical configuration

Connections and currents of the second X20DO4322:

DO

0.45 A 0.5 A

Actuator 1

Actuator 2
0.07 A 0.1 A

0.35 A
Actuator 3

0.09 A

+24 VDC +24 VDC

GND GND

Figure 46: Connections and currents of the second X20DO4322

Calculating the sum of the output currents:

Calculating the sum of the actuator currents:

Calculating the I/O summation current

The I/O summation current is calculated from the sum of all three partial currents.

Calculating the internal I/O power consumption of the X20BR9300

The internal I/O power consumption is calculated using the following formula:

114 X20 system User's Manual 3.10

 Mechanical and electrical configuration

3.24.6.3 Total internal power consumption of the X20BR9300

The following 3 power values must be added together to calculate the total internal power of the X20BR9300:
• Power consumption - Bus
• Power consumption - I/O-internal
• Power consumption - X2X Link-internal

Connections and currents of the second X20DO4322:

DO

0.45 A 0.5 A
Actuator 1

Actuator 2
0.07 A 0.1 A

0.35 A
Actuator 3

0.09 A

+24 VDC +24 VDC

GND GND

Figure 47: Connections and currents of the second X20DO4322

Calculating the sum of the output currents:

Calculating the sum of the actuator currents:

Calculating the I/O summation current

The I/O summation current is calculated from the sum of all three partial currents.

Calculating the internal I/O power consumption of the X20BR9300

The internal I/O power consumption is calculated using the following formula:

X20 system User's Manual 3.10 115

X20 system modules • Module overview: Alphabetically

4 X20 system modules

4.1 Module overview: Alphabetically

Product ID Short description on page
0ACS100A.00-1 Acceleration sensor, nominal sensitivity 100 mV/g, top exit 2204
0ACS100A.90-1 Acceleration sensor, nominal sensitivity 100 mV/g, side exit 2206
X20AI1744 X20 analog input module, 1 full-bridge strain gauge input, 24-bit converter resolution, 5 kHz input filter 129
X20AI1744-3 X20 analog input module, 1 full-bridge strain gauge input, 24-bit converter resolution, 5 Hz input filter 129
X20AI2222 X20 analog input module, 2 inputs, ±10 V, 13-bit resolution, configurable input filter 144
X20AI2237 X20 analog input module, 2 inputs, ±10 V, 16-bit resolution, each channel electrically isolated and with own 152
sensor supply
X20AI2322 X20 analog input module, 2 inputs, 0-20 mA / 4-20 mA, 12-bit converter resolution, configurable input filter 167
X20AI2437 X20 analog input module, 2 inputs, 4 to 20 mA, 16-bit resolution, each channel electrically isolated and with 176
own sensor supply
X20AI2438 X20 analog input module, 2 inputs, 4 to 20 mA, 16-bit resolution, each channel electrically isolated and with 193
own sensor supply, HART protocol supported
X20AI2622 X20 analog input module, 2 inputs, ±10 V or 0 to 20 mA / 4 to 20 mA, 13-bit resolution, configurable input filter 249
X20AI4222 X20 analog input module, 4 inputs, ±10 V, 13-bit resolution, configurable input filter 259
X20AI4322 X20 analog input module, 4 inputs, 0-20 mA / 4-20 mA, 12-bit converter resolution, configurable input filter 267
X20AI4622 X20 analog input module, 4 inputs, ±10 V or 0 to 20 mA / 4 to 20 mA, 13-bit resolution, configurable input filter 276
X20AI8221 X20 analog input module, 8 inputs, ±10 V, 13-bit converter resolution 286
X20AI8321 X20 analog input module, 8 inputs, 0-20 mA, 12-bit resolution 294
X20AO2437 X20 analog output module, 2 outputs, 4 to 20 mA / 0 to 20 mA or 0 to 24 mA 16-bit resolution, single channel 390
electrically isolated
X20AO2438 X20 analog output module, 2 outputs, 4 to 20 mA / 0 to 20 mA or 0 to 24 mA 16-bit resolution single channel 401
electrically isolated, supports the HART protocol
X20AO2622 X20 analog output module, 2 outputs, ±10 V / 0 to 20 mA / 4 to 20 mA, 13-bit resolution 454
X20AO2632 X20 analog output module, 2 outputs, ±10 V / 0 to 20 mA, 16-bit resolution 460
X20AO2632-1 X20 analog output module, 2 outputs, ±11 V / 0 to 22 mA, 16-bit resolution 467
X20AO4622 X20 analog output module, 4 outputs, ±10 V / 0 to 20 mA / 4 to 20 mA, 13-bit resolution 474
X20AO4632 X20 analog output module, 4 outputs, ±10 V / 0 to 20 mA, 16-bit resolution 481
X20AO4632-1 X20 analog output module, 4 outputs, ±11 V / 0 to 22 mA, 16-bit resolution 489
X20AO4635 X20 analog output module, 4 outputs, ±10 V / 0 to 20 mA, 16-bit resolution low temperature drift 498
X20AP3111 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 20 mA AC, calculates 304
effective, reactive and apparent power/energy, calculates root mean square values, 240 V keyed
X20AP3121 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 1 A AC, calculates 304
effective, reactive and apparent power/energy, calculates root mean square values, 240 V keyed
X20AP3131 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 5 A AC, calculates 304
effective, reactive and apparent power/energy, calculates root mean square values, 240 V keyed
X20AP3161 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 333 mV AC, calculates 304
effective, reactive and apparent power/energy, calculates root mean square values, 240 V keyed
X20AT2222 X20 temperature input module, 2 inputs for resistance measurement, PT100, PT1000, resolution 0.1°C, 3-wire 2391
connections
X20AT4222 X20 temperature input module, 4 inputs for resistance measurement, PT100, PT1000, resolution 0.1°C, 3-wire 2400
connections
X20ATA312 X20 temperature input module, 2 inputs for resistance measurement, PT100, resolution 0.01 K, 4-wire connec- 2409
tion
X20ATA492 X20 temperature input module, 2 thermocouple inputs, type J, K, N, S, B, R, E, C, T, each channel electrically 2420
isolated, 2x PT1000 input for terminal temperature compensation with terminal block X20TB1E, order terminal
block separately.
X20ATB312 X20 temperature input module, 4 inputs for resistance measurement, PT100, resolution 0.01°C, 4-wire connec- 2442
tions
X20ATC402 X20 temperature input module, 6 thermocouple inputs, type J, K, N, S, B, R, E, C, T, 2x PT1000 integrated for 2453
terminal temperature compensation, with 1x X20TB1E terminal block, order terminal block separately.
X20BB22 X20 Compact CPU base, for Compact CPU and Compact CPU power supply module, base for integrated RS232 630
interface, X20 connection, X20AC0SL1/X20AC0SR1 X20 end plates left and right included
X20BB27 X20 Compact CPU base, for Compact CPU and Compact CPU power supply module, base for integrated RS232 632
and CAN interface, X20 connection, X20AC0SL1/X20AC0SR1 X20 end plates left and right included
X20BB32 X20 Fieldbus CPU base, for Fieldbus CPU and Compact CPU power supply module, base for integrated RS232 1756
interface, slot for X20 interface module, X20 connection, X20AC0SL1/X20AC0SR1 X20 end plates left and right
included
X20BB37 X20 Fieldbus CPU base, for Fieldbus CPU and Compact CPU power supply module, base for integrated RS232 1758
and CAN interface, slot for X20 interface module, X20 connection, X20AC0SL1/X20AC0SR1 X20 end plates
left and right included
X20BB42 X20 Fieldbus CPU base, for Fieldbus CPU and Compact CPU power supply module, base for integrated RS232 1760
interface, 2 slots for X20 interface modules, X20 connection, X20AC0SL1/X20AC0SR1 X20 end plates left and
right included
X20BB47 X20 Fieldbus CPU base, for Fieldbus CPU and Compact CPU power supply module, base for integrated RS232 1762
and CAN interface, 2 slots for X20 interface modules, X20 connection, X20AC0SL1/X20AC0SR1 X20 end plates
left and right included
X20BB80 X20 bus base for X20 base module (BC, HB, ...) and X20 supply module, X20AC0SL1/X20AC0SR1 X20 end 570
plates left and right included

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 X20 system modules • Module overview: Alphabetically
Product ID Short description on page
X20BB81 X20 bus base with 1 expansion slot for X20 base module (BC, HB, ...) and an X20 auxiliary module (IF, HB, ...) 1738
and X20 power supply module, X20AC0SL1/X20AC0SR1 X20 end plates left and right included
X20BB82 X20 bus base with 2 expansion slots for X20 base module (BC, HB, ...) and two X20 auxiliary modules (IF, 1740
HB, ...) and X20 power supply module, X20AC0SL1/X20AC0SR1 X20 end plates left and right included
X20BC0043 X20 bus controller, CANopen interface, order 1x TB2105 terminal block separately. Order bus base, power 507
supply module and terminal block separately.
X20BC0043-10 X20 bus controller, CANopen interface, configuration supported by the B&R FieldbusDESIGNER, order 1x 514
TB2105 terminal block separately. Order bus base, power supply module and terminal block separately.
X20BC0053 X20 bus controller, DeviceNet interface, order 1x TB2105 terminal block separately. Order bus base, power 521
supply module and terminal block separately.
X20BC0063 X20 bus controller, PROFIBUS DP interface, 9-pin DSUB connection, order bus base, power supply module 527
and terminal block separately.
X20BC0073 X20 bus controller, CAN I/O interface, order 1x TB2105 terminal block separately. Order bus base, power supply 532
module and terminal block separately.
X20BC0083 X20 bus controller, POWERLINK interface, integrated 2x hub, 2x RJ45 connection, order bus base, power 537
supply module and terminal block separately.
X20BC0087 X20 bus controller, Modbus/TCP or Modbus/UDP interface, integrated 2x switch, 2x RJ45 connection, order 542
bus base, power supply module and terminal block separately.
X20BC0088 X20 bus controller, EtherNet/IP interface, integrated switch, web interface 2x RJ45 connection, order bus base, 547
power supply module and terminal block separately.
X20BC00E3 X20 bus controller, PROFINET interface, integrated 2x switch, 2x RJ45 connection, order bus base, power 552
supply module and terminal block separately.
X20BC00G3 X20 bus controller, EtherCAT interface, 2x RJ45 connection, order bus base, power supply module and terminal 558
block separately.
X20BC0143-10 X20 bus controller, CANopen interface, 9-pin DSUB, configuration supported by the B&R FieldbusDESIGNER, 562
order 1x 7AC911.9 connector separately. Order bus base, power supply module and terminal block separately.
X20BC1083 X20 bus controller, 1 POWERLINK interface, integrated 2-port hub, supports X20 interface module expansions, 1708
2 RJ45, order bus base, power supply module and terminal block separately.
X20BC8083 X20 bus controller, POWERLINK interface, integrated 2x hub, supports X20 hub module expansions, 2x RJ45 1713
connection, order bus base, power supply module and terminal block separately.
X20BC8084 X20 bus controller, POWERLINK interface, integrated compact link selector supports active X20 hub module 1718
expansions, 2x RJ45 connection, order bus base, power supply module and terminal block separately.
X20BC80G3 X20 bus controller, EtherCAT interface, supports expansion with X20 EtherCAT junction modules, 2x RJ45 1733
connection, order bus base, supply module and terminal separately!
X20BM01 X20 supply bus module, internal I/O supply interrupted to the left 584
X20BM05 X20 supply bus module with node number switch, internal I/O supply is isolated to the left 586
X20BM11 X20 bus module, 24 V coded, internal I/O supply is interconnected 588
X20BM12 X20 bus module, 240 V coded, internal I/O supply is interconnected 590
X20BM15 X20 bus module with node number switches, internal I/O supply is interconnected 592
X20BM21 X20 bus module for double-width modules, internal I/O supply is isolated to the left 594
X20BM31 X20 bus module for double-width modules, internal I/O supply is interconnected 596
X20BM32 X20 bus module, 240 V coded, for double wide modules, internal I/O supply is interconnected 598
X20BR9300 X20 bus receiver, X2X Link, supply for X2X Link and internal I/O supply, X20 locking plates (left and right) 601
X20AC0SL1/X20AC0SR1 included
X20BT9100 X20 bus transmitter, X2X Link, supply for internal I/O supply 607
X20BT9400 X20 bus transmitter X2X Link, feed for internal I/O supply, X2X Link supply for X67 modules, reverse polari- 613
ty protection, short circuit protection, overload protection, parallel connection possible, redundancy operation
possible
X20CM1201 X20 combination module, 1 AB incremental encoder, 24 V, 4 digital inputs 24 V, 4 channels 24 V configurable 1312
as inputs or outputs, flexible digital controller logic
X20CM1941 X20 resolver module, 14-bit resolver input, converter up to 12-bit ABR output 646
X20CM4810 X20 analog input module for vibration measurement and analyse of condition monitoring exercises. 4 IEPE 2067
analog input 51,5625 kHz sampling frequency 24 bit converter resolution
X20CM8281 X20 universal mixed module, 4 digital inputs, 24 VDC, sink, 1-wire connections, 2 digital outputs, 0.5 A, source, 2210
1-wire connections, 1 analog input, ±10 V or 0 to 20 mA / 4 to 20 mA, 12-bit resolution, 1 analog output, ±10 V /
0 to 20 mA, 12-bit resolution, 2 counters as event counters or gate measurement
X20CM8323 X20 PWM module, 8 digital outputs for switching electromechanical loads, 0.6 A continuous current, 2 A peak 2227
current, current monitoring, switching time detection
X20CP0201 X20 CPU, compact CPU µP 16, 100 kB SRAM, 1 MB FlashPROM, support of RS232 and CAN according to 623
compact CPU base, order bus base, power supply module and terminal block separately
X20CP0291 X20 CPU, compact CPU µP 16, 100 kB SRAM, 1 MB FlashPROM, support of RS232 and CAN according to 623
compact CPU base, 1 Ethernet interface 100 Base-T, order bus base, power supply module and terminal block
separately
X20CP0292 X20 CPU, compact CPU µP 25, 100 kB SRAM, 1 MB FlashPROM, support of RS232 and CAN according to 623
compact CPU base, 3 Ethernet interface 750 Base-T, order bus base, power supply module and terminal block
separately
X20CP1483 X20 CPU, x86 100 MHz Intel compatible, 32 MB DRAM, 128 kB SRAM, removable application memory: Com- 896
pactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20
locking plate (right) X20AC0SR1 included, order application memory separately.
X20CP1483-1 X20 CPU, x86 100 MHz Intel compatible, 64 MB DRAM, 128 kB SRAM, removable application memory: Com- 896
pactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20
locking plate (right) X20AC0SR1 included, order application memory separately.
X20CP1583 X20 CPU, ATOM 333 MHz compatible, 128 MB DDR2 RAM, 1 MB SRAM, removable application memory: 913
CompactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and
X20 locking plate (right) X20AC0SR1 included, order application memory separately.

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X20 system modules • Module overview: Alphabetically
Product ID Short description on page
X20CP1584 X20 CPU, ATOM 0.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: CompactFlash, 913
1 insert slot for X20 interface modules, 2 USB ports, 1 RS232 interface, 1 Ethernet interface 10/100/1000 Base-
T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20 locking plate
(right) X20AC0SR1 included, order application memory separately.
X20CP1585 X20 CPU, ATOM 1.0 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: CompactFlash, 913
1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface 10/100/1000
Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20 locking
plate (right) X20AC0SR1 included, order application memory separately.
X20CP1586 X20 CPU, ATOM 1.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: CompactFlash, 913
1 insert slot for X20 interface modules, 2 USB ports, 1 RS232 interface, 1 Ethernet interface 10/100/1000 Base-
T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20 locking plate
(right) X20AC0SR1 included, order application memory separately.
X20CP3583 X20 CPU, ATOM 333 MHz compatible, 128 MB DDR2 RAM, 1 MB SRAM, removable application memory: 917
CompactFlash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet inter-
face 10/100/1000 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot covers
and X20 locking plate (right) X20AC0SR1 included, order application memory separately.
X20CP3584 X20 CPU, ATOM 0.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: Compact- 917
Flash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000BASE-T, 1 POWERLINK interface, incl. supply module, 1 terminal block, slot cover and X20 locking
plate (right) included, order application memory separately.
X20CP3585 X20 CPU, ATOM 1.0 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: Compact- 917
Flash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000BASE-T, 1 POWERLINK interface, incl. supply module, 1 terminal block, slot cover and X20 locking
plate (right) included, order application memory separately.
X20CP3586 X20 CPU, ATOM 1.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: Compact- 917
Flash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000BASE-T, 1 POWERLINK interface, incl. supply module, 1 terminal block, slot cover and X20 locking
plate (right) included, order application memory separately.
X20CS1011 X20 interface module, 1 Moeller SmartWire interface 1461
X20CS1012 X20 interface module, 1x M-Bus master, integrated slave supply 1476
X20CS1013 X20 interface module, 1x DALI master 1524
X20CS1020 X20 interface module, 1 RS232 interface, max. 115.2 kbit/s 1533
X20CS1030 X20 interface module, 1 RS422/485 interface, max. 115.2 Mbit/s 1575
X20CS1070 X20 interface module, 1x CAN, max. 1 Mbit/s, object buffer in transmit and receive direction 1617
X20CS2770 X20 interface module, 2x CAN, max. 1 Mbit/s, object buffer in transmit and receive direction 1662
X20DC1073 X20 digital counter module, 1x SinCos, 1 Vss, 400 kHz input frequency, encoder monitoring, NetTime module 1332
X20DC1176 X20 digital counter module, 1 ABR incremental encoder, 5 V 600 kHz input frequency, 4x evaluation, encoder 653
monitoring, NetTime module
X20DC1178 X20 digital counter module, 1 SSI absolute encoders, 5 V, 1 MBit/s, 32-bit, encoder monitoring, NetTime module 669
X20DC1196 X20 digital counter module, 1 ABR incremental encoders, 5 V, 600 kHz input frequency, 4x evaluation 684
X20DC1198 X20 digital counter module, 1 SSI absolute encoder, 5 V, 1 MBit/s, 32-bit 694
X20DC11A6 X20 digital counter module, 1 ABR incremental encoders, 5 V, 5 MHz input frequency, 4x evaluation 701
X20DC1376 X20 digital counter module, 1 ABR incremental encoder, 24 V 100 kHz input frequency, 4x evaluation, encoder 717
monitoring, NetTime module
X20DC137A X20 digital counter module, 1x ABR incremental encoder, 24 V (differential), 300 kHz input frequency, 4x eval- 732
uation, encoder monitoring, NetTime module
X20DC1396 X20 digital counter module, 1 ABR incremental encoders, 24 V, 100 kHz input frequency, 4x evaluation 747
X20DC1398 X20 digital counter module, 1 SSI absolute encoder, 24 V, 125 kbit/s, 32-bit 757
X20DC1976 X20 digital counter module, 1x ABR incremental encoder, 5 V (single ended), 250 kHz input frequency, 4x 764
evaluation, encoder monitoring, NetTime module
X20DC2190 X20 digital counter module, ultrasonic transducer module, interfaces: EP start/stop, DPI/IP, 2 transducer rods, 780
4 path evaluation
X20DC2395 X20 digital counter module, 1 SSI absolute encoder, 24 V, 1 ABR incremental encoder, 24 V, 2 AB incremental 793
encoders, 24 V, 4 event counters or 2 PWM, local time measurement function
X20DC2396 X20 digital counter module, 2 ABR incremental encoders, 24 V, 100 kHz input frequency, 4x evaluation 833
X20DC2398 X20 digital counter module, 2 SSI absolute encoder, 24 V, 125 kbit/s, 32-bit 843
X20DC4395 X20 digital counter module, 2 SSI absolute encoder, 24 V, 2 ABR incremental encoder, 24 V, 4 AB incremental 850
encoders, 24 V, 8 event counters or 4 PWM, local time measurement function
X20DI2371 X20 digital input module, 2 inputs, 24 VDC, sink, configurable input filter, 3-wire connections 936
X20DI2372 X20 digital input module, 2 inputs, 24 VDC, source, configurable input filter, 3-wire connections 942
X20DI2377 X20 digital input module, 2 inputs, 24 VDC, sink, configurable input filter, 2 event counters 50 kHz, 3-wire 948
connections
X20DI2653 X20 digital input module, 2 inputs, 100 to 240 VAC, 240 V keyed, 3-wire connections 956
X20DI4371 X20 digital input module, 4 inputs, 24 VDC, sink, configurable input filter, 3-wire connections 962
X20DI4372 X20 digital input module, 4 inputs, 24 VDC, source, configurable input filter, 3-wire connections 969
X20DI4375 X20 digital input module, 4 inputs, 24 VDC, sink, configurable input filter, open line and short circuit detection, 975
3-wire connections
X20DI4653 X20 digital input module, 4 inputs, 100 to 240 VAC, 240 V keyed, 2-wire connections 986
X20DI4760 X20 digital input module, 4 NAMUR inputs, 8.05 V 992
X20DI6371 X20 digital input module, 6 inputs, 24 VDC, sink, configurable input filter, 2-wire connections 1001
X20DI6372 X20 digital input module, 6 inputs, 24 VDC, source, configurable input filter, 2-wire connections 1007
X20DI6373 X20 digital input module, 6 inputs, 24 VDC, sink/source, all inputs floating, configurable input filter, 2-wire con- 1013
nections
X20DI6553 X20 digital input module, 6 inputs, 100 to 120 VAC, 240 V keyed, 1-wire connections 1019
X20DI8371 X20 digital input module, 8 inputs, 24 VDC, sink, configurable input filter, 1-wire connections 1025
X20DI9371 X20 digital input module, 12 inputs, 24 VDC, sink, configurable input filter, 1-wire connections 1031
X20DI9372 X20 digital input module, 12 inputs, 24 VDC, source, configurable input filter, 1-wire connections 1037
X20DID371 X20 digital input module, 8 inputs, 24 VDC, sink, configurable input filter, 2-wire connections 1043
X20DIF371 X20 digital input module, 16 inputs, 24 VDC, sink, configurable input filter, 1-wire connections 1049

118 X20 system User's Manual 3.10

 X20 system modules • Module overview: Alphabetically
Product ID Short description on page
X20DM9324 X20 digital mixed module, 8 inputs, 24 VDC, sink, configurable input filter, 4 outputs, 24 VDC, 0.5 A, source, 1056
1-wire connections
X20DO2321 X20 digital output module, 2 outputs, 24 VDC, 0.5 A, sink, 3-wire connections 1066
X20DO2322 X20 digital output module, 2 outputs, 24 VDC, 0.5 A, source, 3-wire connections 1074
X20DO2623 X20 digital output module, 2 outputs, 100-240 VAC, 1 A, source, 240 V keyed, 3-wire connections 1082
X20DO2633 X20 digital output module, 2 triac outputs, 12 to 240 VAC, 2 A, L switching, phase angle control, 240 V keyed 1091
X20DO2649 X20 digital output module, 2 relays, changeover contacts, 230 VAC / 5 A, 24 VDC / 5 A 1106
X20DO4321 X20 digital output module, 4 outputs, 24 VDC, 0.5 A, sink, 3-wire connections 1112
X20DO4322 X20 digital output module, 4 outputs, 24 VDC, 0.5 A, source, 3-wire connections 1120
X20DO4331 X20 digital output module, 4 outputs, 24 VDC, 2 A, sink, 3-wire connections 1128
X20DO4332 X20 digital output module, 4 outputs, 24 VDC, 2 A, source, 3-wire connections 1138
X20DO4529 X20 digital output module, 4 relays, changeover contacts, 115 VAC / 0.5 A, 24 VDC / 1 A 1148
X20DO4613 X20 digital output module, 4 triac coupler outputs, 12 to 240 VAC, 50 mA, zero-crossing detection, 240 V keyed,... 1154
X20DO4623 X20 digital output module, 4 outputs, 100-240 VAC, 0.5 A, source, 240 V keyed, 2-wire connections 1167
X20DO4633 X20 digital output module, 4 triac outputs, 12 to 240 VAC, 1 A, L switching, phase angle control, 240 V keyed 1175
X20DO4649 X20 digital output module, 4 relays, N.O. contacts, 240 VAC / 5 A 1190
X20DO6321 X20 digital output module, 6 outputs, 24 VDC, 0.5 A, sink, 2-wire connections 1196
X20DO6322 X20 digital output module, 6 outputs, 24 VDC, 0.5 A, source, 2-wire connections 1202
X20DO6325 X20 digital output module, 6 outputs, 24 VDC, 0.5 A, source, open line and overload detection, 2-wire connec- 1210
tions
X20DO6529 X20 digital output module, 6 relays, normally open contacts, 115 VAC / 0.5 A, 30 VDC / 1 A 1222
X20DO6639 X20 digital output module, 6 relays, normally open contacts, 240 VAC / 2 A, 30 VDC / 2 A 1228
X20DO8232 X20 digital output module, 8 outputs, 12 VDC, 2.0 A, source, supply directly on module, 1 wire technology 1234
X20DO8322 X20 digital output module, 8 outputs, 24 VDC, 0.5 A, source, 1-wire connections 1245
X20DO8323 X20 digital output module, 8 outputs, 12 to 24 V, 0.5 A, sink/source, 1-wire connections, full bridge, half bridge, 1252
thermal overload protection
X20DO8331 X20 digital output module, 8 outputs, 24 VDC, 2 A, sink, supply directly on module, 1-wire connections 1260
X20DO8332 X20 digital output module, 8 outputs, 24 VDC, 2 A, source, supply directly on module, 1-wire connections 1271
X20DO9321 X20 digital output module, 12 outputs, 24 VDC, 0.5 A, sink, 1-wire connections 1282
X20DO9322 X20 digital output module, 12 outputs, 24 VDC, 0.5 A, source, 1-wire connections 1289
X20DOD322 X20 digital output module, 8 outputs, 24 VDC, 0.5 A, source, 2-wire connections 1297
X20DOF322 X20 digital output module, 16 outputs, 24 VDC, 0.5 A, source, 1-wire connections 1303
X20DS1828 X20 digital signal module, 1x HIPERFACE, NetTime module 1337
X20DS1928 X20 digital signal module, 1x EnDat 2.1/2.2, NetTime module 1399
X20DS438A X20 digital signal module, 4x I/O Link master V1.1, can also be configured as 4x digital input or output channels, 2244
3-wire connections
X20ET8819 X20 Ethernet analysis tool, can be expanded with active hub modules, 2x RJ45 1884
X20HB1881 X20 hub expansion module, integrated 1x hub, 1 fiber optic connection 2367
X20HB2880 X20 hub expansion module, 2x RJ45 2370
X20HB2881 X20 hub expansion module, integrated 2x hub, for fiber optic connection 2373
X20HB2885 X20 hub expansion module, integrated active 2x hub, 2x RJ45 2383
X20HB2886 X20 hub expansion module, integrated active 2x hub, 2 fiber optic connections 2386
X20HB28G0 X20 EtherCAT junction module, 2x EtherCAT junction, 2x RJ45 connection 2376
X20HB8815 X20 POWERLINK - TCP/IP gateway, can be expanded with active hub modules, 2x RJ45 1897
X20HB8880 X20 hub base module, integrated 2x hub, 2x RJ45 1904
X20HB8884 X20 compact link selector, 2x RJ45 connection, order bus base, power supply module and terminal block sep- 2353
arately.
X20HB88G0 X20 EtherCAT junction base module integr. 2x EtherCAT junction, 2x RJ45 connection 1908
X20IF0000 X20 dummy interface module (non-functional) 1453
X20IF1020 X20 interface module, 1 RS232, max. 115.2 kbit/s, electrically isolated 1769
X20IF1030 X20 interface module, 1 RS422/RS485, max. 115.2 kbit/s, electrically isolated 1772
X20IF1041-1 X20 interface module, for DTM configuration, 1 CANopen master interface, electrically isolated, order 1x TB2105 1775
terminal block separately.
X20IF1043-1 X20 interface module, for DTM configuration, 1 CANopen slave interface, electrically isolated, order 1x TB2105 1779
terminal block separately.
X20IF1051-1 X20 interface module, for DTM configuration, 1 DeviceNet scanner (master) interface, electrically isolated, order 1783
1x TB2105 terminal block separately.
X20IF1053-1 X20 interface module, for DTM configuration, 1 DeviceNet adapter (slave) interface, electrically isolated, order 1787
1x TB2105 terminal block separately.
X20IF1061 X20 interface module, 1 PROFIBUS DP V1 master interface, max. 12 Mbit/s, max. 3.5 kB input data and max. 1791
3.5 kB output data, electrically isolated
X20IF1061-1 X20 interface module for DTM configuration, 1 PROFIBUS DP V0/V1 master interface, electrically isolated 1794
X20IF1063 X20 interface module, 1 PROFIBUS DP V0 slave interface, max. 12 Mbit/s, electrically isolated 1798
X20IF1063-1 X20 interface module, for DTM configuration, 1 PROFIBUS DP V1 slave interface, electrically isolated 1801
X20IF1065 X20 interface module, 1 PROFIBUS DP V1 slave interface, max. 12 Mbit/s, electrically isolated 1805
X20IF1072 X20 interface module, 1 CAN interface, max. 1 Mbit/s, electrically isolated, order 1x TB2105 terminal block 1808
separately.
X20IF1074 X20 interface module for SGC, 1 CAN interface, max. 1 Mbit/s, electrically isolated, order 1x TB2105 terminal 1764
block separately
X20IF1082 X20 interface module, 1 POWERLINK interface, managing or controlled node, integrated 2x hub, ring redun- 1812
dancy function
X20IF1082-2 X20 interface module, 1 POWERLINK interface, managing or controlled node, integrated 2x hub, ring redun- 1818
dancy function, PRC function
X20IF1086-2 X20 interface module, 1 POWERLINK interface, managing or controlled node, PRC function, 1x fiber optic 1824
connection
X20IF1091 X20 interface module, 1 X2X Link master interface, electrically isolated, order 1x TB704 terminal block sepa- 1830
rately.

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X20 system modules • Module overview: Alphabetically
Product ID Short description on page
X20IF1091-1 X20 interface module for expandable bus controller, 1 X2X Link master interface, electrically isolated, order 1x 1742
TB704 terminal block separately.
X20IF10A1-1 X20 interface module, for DTM configuration, 1 ASi master interface, electrically isolated, order 1x TB704 ter- 1833
minal block separately.
X20IF10D1-1 X20 interface module, for DTM configuration, 1 EtherNet/IP scanner (master) interface, electrically isolated 1837
X20IF10D3-1 X20 interface module, for DTM configuration, 1 EtherNet/IP adapter (slave) interface, electrically isolated 1841
X20IF10E1-1 X20 interface module for DTM configuration, 1 PROFINET RT controller (master) interface, electrically isolated 1845
X20IF10E3-1 X20 interface module, for DTM configuration, 1 PROFINET RT device (slave) interface, electrically isolated 1849
X20IF10G3-1 X20 interface module for DTM configuration, 1 EtherCAT slave interface, electrically isolated 1853
X20IF10X0 X20 interface module, 1 redundancy link interface 1000BASE-SX, CPU-CPU data synchronization module for 1857
controller redundancy
X20IF2181-2 X20 interface module, 1x link selector for POWERLINK cable redundancy, POWERLINK functions: - Managing 1860
node - Controlled node for iCN operation - Redundant managing node for CPU redundancy - Ring redundancy
- 2x hub - Multi ASend - PRC function 2x RJ45 connection
X20IF2772 X20 interface module, 2 CAN interfaces, max. 1 Mbit/s, electrically isolated, order 2x TB2105 terminal block 1874
separately.
X20IF2792 X20 interface module, 1 CAN interface, max. 1 Mbit/s, electrically isolated, 1 X2X Link master interface, elec- 1878
trically isolated, order 1x TB2105 and 1x TB704 terminal block separately.
X20MM2436 X20 PWM motor module, 24 to 39 VDC ±25%, 2 PWM motor bridges, 3 A continuous current, 3.5 A peak current, 1913
4 digital inputs 24 VDC, sink, configurable as incremental encoder
X20MM3332 X20 digital motor module, 24 VDC, 3 digital outputs, full bridge (H bridge), 3 A continuous current, 5 A peak 1930
current
X20MM4331 X20 digital motor module, 24 VDC, 4 digital outputs, half bridge, 3 A continuous current, 5 A peak current 1944
X20MM4456 X20 PWM motor module, 24 to 48 VDC ±25%, 4 PWM motor bridges, 6 A continuous current, 10 A peak current, 1956
4x 4 digital inputs 24 VDC, sink, configurable as incremental encoder
X20PD0011 X20 potential distributor module, 12x GND, integrated microfuse 2308
X20PD0012 X20 potential distributor module, 12x 24 VDC, integrated microfuse 2312
X20PD0016 X20 potential distributor module, 5x GND, 5x 24 VDC, floating feed, integrated microfuse 2316
X20PD2113 X20 potential distributor module, 6x GND, 6x 24 VDC, with feed option, integrated microfuse 2320
X20PS2100 X20 supply module for internal I/O supply 2331
X20PS2110 X20 supply module for internal I/O supply, integrated microfuse 2335
X20PS3300 X20 supply module for X2X Link and internal I/O supply 2340
X20PS3310 X20 supply module for X2X Link and internal I/O supply, integrated microfuse 2346
X20PS4951 X20 power supply module for potentiometers, 4x ±10 V for potentiometer supply 2325
X20PS8002 X20 supply module for standalone hub and compact link selector 2379
X20PS9400 X20 supply module for bus controller and internal I/O supply, X2X Link supply 572
X20PS9402 X20 supply module, for bus controller and internal I/O supply, X2X Link supply, supply not electrically isolated 578
X20PS9500 X20 supply module for compact and fieldbus CPUs and internal I/O supply, X2X Link supply 634
X20PS9502 X20 power supply module for compact and fieldbus and internal I/O supply, X2X Link bus supply, supply not 639
electrically isolated
X20SM1426 X20 stepper motor module, 1 motor connection, 1 A continuous current, 1.2 A peak current, 4 digital inputs 24 1976
VDC, sink, can be configured as incremental encoder
X20SM1436 X20 stepper motor module, module supply 24-39 VDC ±25%, 1 motor connection, 3 A continuous current, 3.5 2020
A peak current, 4 digital inputs 24 VDC, sink, can be configured as incremental encoder
X20TB06 X20 terminal block, 6-pin, 24 V coded 2475
X20TB12 X20 terminal block, 12-pin, 24 V keyed 2475
X20TB1E X20 terminal block, 12-pin, 24 VDC keyed, 2x PT1000 integrated for terminal temperature compensation 2477
X20TB1F X20 terminal block, 16-pin, 24 VDC keyed 2479
X20TB32 X20 terminal block, 12-pin, 240 VAC keyed 2481
X20XC0201 X20 CPU, fieldbus CPU µP 16, 100 kB SRAM, 1 MB FlashPROM, support of RS232, CAN and interface module, 1748
according to fieldbus CPU base, order power supply module, bus base and terminal block separately
X20XC0202 X20 CPU, fieldbus CPU µP 25, 750 kB SRAM, 3 MB FlashPROM, support of RS232, CAN and interface module, 1748
according to fieldbus CPU base, order power supply module, bus base and terminal block separately
X20XC0292 X20 CPU, fieldbus CPU µP 25, 750 kB SRAM, 3 MB FlashPROM, support of RS232, CAN and interface module, 1748
according to fieldbus CPU base, 1 Ethernet interface 100 Base-T, order bus base, power supply module and
terminal block separately
X20ZF0000 Dummy X20 module (non-functional) 1455
X20ZF000F Dummy X20 module (non-functional) 1458

120 X20 system User's Manual 3.10

 X20 system modules • Module overview: Grouped

4.2 Module overview: Grouped

CPU modules
Product ID Short description on page
X20CP1483 X20 CPU, x86 100 MHz Intel compatible, 32 MB DRAM, 128 kB SRAM, removable application memory: Com- 896
pactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20
locking plate (right) X20AC0SR1 included, order application memory separately.
X20CP1483-1 X20 CPU, x86 100 MHz Intel compatible, 64 MB DRAM, 128 kB SRAM, removable application memory: Com- 896
pactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20
locking plate (right) X20AC0SR1 included, order application memory separately.
X20CP1583 X20 CPU, ATOM 333 MHz compatible, 128 MB DDR2 RAM, 1 MB SRAM, removable application memory: 913
CompactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and
X20 locking plate (right) X20AC0SR1 included, order application memory separately.
X20CP1584 X20 CPU, ATOM 0.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: CompactFlash, 913
1 insert slot for X20 interface modules, 2 USB ports, 1 RS232 interface, 1 Ethernet interface 10/100/1000 Base-
T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20 locking plate
(right) X20AC0SR1 included, order application memory separately.
X20CP1585 X20 CPU, ATOM 1.0 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: CompactFlash, 913
1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface 10/100/1000
Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20 locking
plate (right) X20AC0SR1 included, order application memory separately.
X20CP1586 X20 CPU, ATOM 1.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: CompactFlash, 913
1 insert slot for X20 interface modules, 2 USB ports, 1 RS232 interface, 1 Ethernet interface 10/100/1000 Base-
T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20 locking plate
(right) X20AC0SR1 included, order application memory separately.
X20CP3583 X20 CPU, ATOM 333 MHz compatible, 128 MB DDR2 RAM, 1 MB SRAM, removable application memory: 917
CompactFlash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet inter-
face 10/100/1000 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot covers
and X20 locking plate (right) X20AC0SR1 included, order application memory separately.
X20CP3584 X20 CPU, ATOM 0.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: Compact- 917
Flash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000BASE-T, 1 POWERLINK interface, incl. supply module, 1 terminal block, slot cover and X20 locking
plate (right) included, order application memory separately.
X20CP3585 X20 CPU, ATOM 1.0 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: Compact- 917
Flash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000BASE-T, 1 POWERLINK interface, incl. supply module, 1 terminal block, slot cover and X20 locking
plate (right) included, order application memory separately.
X20CP3586 X20 CPU, ATOM 1.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: Compact- 917
Flash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000BASE-T, 1 POWERLINK interface, incl. supply module, 1 terminal block, slot cover and X20 locking
plate (right) included, order application memory separately.

Product ID Short description on page

X20CP0201 X20 CPU, compact CPU µP 16, 100 kB SRAM, 1 MB FlashPROM, support of RS232 and CAN according to 623
compact CPU base, order bus base, power supply module and terminal block separately
X20CP0291 X20 CPU, compact CPU µP 16, 100 kB SRAM, 1 MB FlashPROM, support of RS232 and CAN according to 623
compact CPU base, 1 Ethernet interface 100 Base-T, order bus base, power supply module and terminal block
separately
X20CP0292 X20 CPU, compact CPU µP 25, 100 kB SRAM, 1 MB FlashPROM, support of RS232 and CAN according to 623
compact CPU base, 3 Ethernet interface 750 Base-T, order bus base, power supply module and terminal block
separately

Product ID Short description on page

X20XC0201 X20 CPU, fieldbus CPU µP 16, 100 kB SRAM, 1 MB FlashPROM, support of RS232, CAN and interface module, 1748
according to fieldbus CPU base, order power supply module, bus base and terminal block separately
X20XC0202 X20 CPU, fieldbus CPU µP 25, 750 kB SRAM, 3 MB FlashPROM, support of RS232, CAN and interface module, 1748
according to fieldbus CPU base, order power supply module, bus base and terminal block separately
X20XC0292 X20 CPU, fieldbus CPU µP 25, 750 kB SRAM, 3 MB FlashPROM, support of RS232, CAN and interface module, 1748
according to fieldbus CPU base, 1 Ethernet interface 100 Base-T, order bus base, power supply module and
terminal block separately

X20 system User's Manual 3.10 121

X20 system modules • Module overview: Grouped

All modules
Product ID Short description on page
X20DO6325 X20 digital output module, 6 outputs, 24 VDC, 0.5 A, source, open line and overload detection, 2-wire connec- 1210
tions
Analog input modules
X20AI1744 X20 analog input module, 1 full-bridge strain gauge input, 24-bit converter resolution, 5 kHz input filter 129
X20AI1744-3 X20 analog input module, 1 full-bridge strain gauge input, 24-bit converter resolution, 5 Hz input filter 129
X20AI2222 X20 analog input module, 2 inputs, ±10 V, 13-bit resolution, configurable input filter 144
X20AI2237 X20 analog input module, 2 inputs, ±10 V, 16-bit resolution, each channel electrically isolated and with own 152
sensor supply
X20AI2322 X20 analog input module, 2 inputs, 0-20 mA / 4-20 mA, 12-bit converter resolution, configurable input filter 167
X20AI2437 X20 analog input module, 2 inputs, 4 to 20 mA, 16-bit resolution, each channel electrically isolated and with 176
own sensor supply
X20AI2438 X20 analog input module, 2 inputs, 4 to 20 mA, 16-bit resolution, each channel electrically isolated and with 193
own sensor supply, HART protocol supported
X20AI2622 X20 analog input module, 2 inputs, ±10 V or 0 to 20 mA / 4 to 20 mA, 13-bit resolution, configurable input filter 249
X20AI4222 X20 analog input module, 4 inputs, ±10 V, 13-bit resolution, configurable input filter 259
X20AI4322 X20 analog input module, 4 inputs, 0-20 mA / 4-20 mA, 12-bit converter resolution, configurable input filter 267
X20AI4622 X20 analog input module, 4 inputs, ±10 V or 0 to 20 mA / 4 to 20 mA, 13-bit resolution, configurable input filter 276
X20AI8221 X20 analog input module, 8 inputs, ±10 V, 13-bit converter resolution 286
X20AI8321 X20 analog input module, 8 inputs, 0-20 mA, 12-bit resolution 294
X20AP3111 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 20 mA AC, calculates 304
effective, reactive and apparent power/energy, calculates root mean square values, 240 V keyed
X20AP3121 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 1 A AC, calculates 304
effective, reactive and apparent power/energy, calculates root mean square values, 240 V keyed
X20AP3131 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 5 A AC, calculates 304
effective, reactive and apparent power/energy, calculates root mean square values, 240 V keyed
X20AP3161 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 333 mV AC, calculates 304
effective, reactive and apparent power/energy, calculates root mean square values, 240 V keyed
Analog output modules
X20AO2437 X20 analog output module, 2 outputs, 4 to 20 mA / 0 to 20 mA or 0 to 24 mA 16-bit resolution, single channel 390
electrically isolated
X20AO2438 X20 analog output module, 2 outputs, 4 to 20 mA / 0 to 20 mA or 0 to 24 mA 16-bit resolution single channel 401
electrically isolated, supports the HART protocol
X20AO2622 X20 analog output module, 2 outputs, ±10 V / 0 to 20 mA / 4 to 20 mA, 13-bit resolution 454
X20AO2632 X20 analog output module, 2 outputs, ±10 V / 0 to 20 mA, 16-bit resolution 460
X20AO2632-1 X20 analog output module, 2 outputs, ±11 V / 0 to 22 mA, 16-bit resolution 467
X20AO4622 X20 analog output module, 4 outputs, ±10 V / 0 to 20 mA / 4 to 20 mA, 13-bit resolution 474
X20AO4632 X20 analog output module, 4 outputs, ±10 V / 0 to 20 mA, 16-bit resolution 481
X20AO4632-1 X20 analog output module, 4 outputs, ±11 V / 0 to 22 mA, 16-bit resolution 489
X20AO4635 X20 analog output module, 4 outputs, ±10 V / 0 to 20 mA, 16-bit resolution low temperature drift 498
Bus controllers
X20BC0043 X20 bus controller, CANopen interface, order 1x TB2105 terminal block separately. Order bus base, power 507
supply module and terminal block separately.
X20BC0043-10 X20 bus controller, CANopen interface, configuration supported by the B&R FieldbusDESIGNER, order 1x 514
TB2105 terminal block separately. Order bus base, power supply module and terminal block separately.
X20BC0053 X20 bus controller, DeviceNet interface, order 1x TB2105 terminal block separately. Order bus base, power 521
supply module and terminal block separately.
X20BC0063 X20 bus controller, PROFIBUS DP interface, 9-pin DSUB connection, order bus base, power supply module 527
and terminal block separately.
X20BC0073 X20 bus controller, CAN I/O interface, order 1x TB2105 terminal block separately. Order bus base, power supply 532
module and terminal block separately.
X20BC0083 X20 bus controller, POWERLINK interface, integrated 2x hub, 2x RJ45 connection, order bus base, power 537
supply module and terminal block separately.
X20BC0087 X20 bus controller, Modbus/TCP or Modbus/UDP interface, integrated 2x switch, 2x RJ45 connection, order 542
bus base, power supply module and terminal block separately.
X20BC0088 X20 bus controller, EtherNet/IP interface, integrated switch, web interface 2x RJ45 connection, order bus base, 547
power supply module and terminal block separately.
X20BC00E3 X20 bus controller, PROFINET interface, integrated 2x switch, 2x RJ45 connection, order bus base, power 552
supply module and terminal block separately.
X20BC00G3 X20 bus controller, EtherCAT interface, 2x RJ45 connection, order bus base, power supply module and terminal 558
block separately.
X20BC0143-10 X20 bus controller, CANopen interface, 9-pin DSUB, configuration supported by the B&R FieldbusDESIGNER, 562
order 1x 7AC911.9 connector separately. Order bus base, power supply module and terminal block separately.
Bus modules
X20BM01 X20 supply bus module, internal I/O supply interrupted to the left 584
X20BM05 X20 supply bus module with node number switch, internal I/O supply is isolated to the left 586
X20BM11 X20 bus module, 24 V coded, internal I/O supply is interconnected 588
X20BM12 X20 bus module, 240 V coded, internal I/O supply is interconnected 590
X20BM15 X20 bus module with node number switches, internal I/O supply is interconnected 592
X20BM21 X20 bus module for double-width modules, internal I/O supply is isolated to the left 594
X20BM31 X20 bus module for double-width modules, internal I/O supply is interconnected 596
X20BM32 X20 bus module, 240 V coded, for double wide modules, internal I/O supply is interconnected 598
Bus receivers and transmitters
X20BR9300 X20 bus receiver, X2X Link, supply for X2X Link and internal I/O supply, X20 locking plates (left and right) 601
X20AC0SL1/X20AC0SR1 included
X20BT9100 X20 bus transmitter, X2X Link, supply for internal I/O supply 607

122 X20 system User's Manual 3.10

 X20 system modules • Module overview: Grouped
Product ID Short description on page
X20BT9400 X20 bus transmitter X2X Link, feed for internal I/O supply, X2X Link supply for X67 modules, reverse polari- 613
ty protection, short circuit protection, overload protection, parallel connection possible, redundancy operation
possible
Compact CPUs
X20CP0201 X20 CPU, compact CPU µP 16, 100 kB SRAM, 1 MB FlashPROM, support of RS232 and CAN according to 623
compact CPU base, order bus base, power supply module and terminal block separately
X20CP0291 X20 CPU, compact CPU µP 16, 100 kB SRAM, 1 MB FlashPROM, support of RS232 and CAN according to 623
compact CPU base, 1 Ethernet interface 100 Base-T, order bus base, power supply module and terminal block
separately
X20CP0292 X20 CPU, compact CPU µP 25, 100 kB SRAM, 1 MB FlashPROM, support of RS232 and CAN according to 623
compact CPU base, 3 Ethernet interface 750 Base-T, order bus base, power supply module and terminal block
separately
Counter functions
X20CM1941 X20 resolver module, 14-bit resolver input, converter up to 12-bit ABR output 646
X20DC1176 X20 digital counter module, 1 ABR incremental encoder, 5 V 600 kHz input frequency, 4x evaluation, encoder 653
monitoring, NetTime module
X20DC1178 X20 digital counter module, 1 SSI absolute encoders, 5 V, 1 MBit/s, 32-bit, encoder monitoring, NetTime module 669
X20DC1196 X20 digital counter module, 1 ABR incremental encoders, 5 V, 600 kHz input frequency, 4x evaluation 684
X20DC1198 X20 digital counter module, 1 SSI absolute encoder, 5 V, 1 MBit/s, 32-bit 694
X20DC11A6 X20 digital counter module, 1 ABR incremental encoders, 5 V, 5 MHz input frequency, 4x evaluation 701
X20DC1376 X20 digital counter module, 1 ABR incremental encoder, 24 V 100 kHz input frequency, 4x evaluation, encoder 717
monitoring, NetTime module
X20DC137A X20 digital counter module, 1x ABR incremental encoder, 24 V (differential), 300 kHz input frequency, 4x eval- 732
uation, encoder monitoring, NetTime module
X20DC1396 X20 digital counter module, 1 ABR incremental encoders, 24 V, 100 kHz input frequency, 4x evaluation 747
X20DC1398 X20 digital counter module, 1 SSI absolute encoder, 24 V, 125 kbit/s, 32-bit 757
X20DC1976 X20 digital counter module, 1x ABR incremental encoder, 5 V (single ended), 250 kHz input frequency, 4x 764
evaluation, encoder monitoring, NetTime module
X20DC2190 X20 digital counter module, ultrasonic transducer module, interfaces: EP start/stop, DPI/IP, 2 transducer rods, 780
4 path evaluation
X20DC2395 X20 digital counter module, 1 SSI absolute encoder, 24 V, 1 ABR incremental encoder, 24 V, 2 AB incremental 793
encoders, 24 V, 4 event counters or 2 PWM, local time measurement function
X20DC2396 X20 digital counter module, 2 ABR incremental encoders, 24 V, 100 kHz input frequency, 4x evaluation 833
X20DC2398 X20 digital counter module, 2 SSI absolute encoder, 24 V, 125 kbit/s, 32-bit 843
X20DC4395 X20 digital counter module, 2 SSI absolute encoder, 24 V, 2 ABR incremental encoder, 24 V, 4 AB incremental 850
encoders, 24 V, 8 event counters or 4 PWM, local time measurement function
Digital input modules
X20DI2371 X20 digital input module, 2 inputs, 24 VDC, sink, configurable input filter, 3-wire connections 936
X20DI2372 X20 digital input module, 2 inputs, 24 VDC, source, configurable input filter, 3-wire connections 942
X20DI2377 X20 digital input module, 2 inputs, 24 VDC, sink, configurable input filter, 2 event counters 50 kHz, 3-wire 948
connections
X20DI2653 X20 digital input module, 2 inputs, 100 to 240 VAC, 240 V keyed, 3-wire connections 956
X20DI4371 X20 digital input module, 4 inputs, 24 VDC, sink, configurable input filter, 3-wire connections 962
X20DI4372 X20 digital input module, 4 inputs, 24 VDC, source, configurable input filter, 3-wire connections 969
X20DI4375 X20 digital input module, 4 inputs, 24 VDC, sink, configurable input filter, open line and short circuit detection, 975
3-wire connections
X20DI4653 X20 digital input module, 4 inputs, 100 to 240 VAC, 240 V keyed, 2-wire connections 986
X20DI4760 X20 digital input module, 4 NAMUR inputs, 8.05 V 992
X20DI6371 X20 digital input module, 6 inputs, 24 VDC, sink, configurable input filter, 2-wire connections 1001
X20DI6372 X20 digital input module, 6 inputs, 24 VDC, source, configurable input filter, 2-wire connections 1007
X20DI6373 X20 digital input module, 6 inputs, 24 VDC, sink/source, all inputs floating, configurable input filter, 2-wire con- 1013
nections
X20DI6553 X20 digital input module, 6 inputs, 100 to 120 VAC, 240 V keyed, 1-wire connections 1019
X20DI8371 X20 digital input module, 8 inputs, 24 VDC, sink, configurable input filter, 1-wire connections 1025
X20DI9371 X20 digital input module, 12 inputs, 24 VDC, sink, configurable input filter, 1-wire connections 1031
X20DI9372 X20 digital input module, 12 inputs, 24 VDC, source, configurable input filter, 1-wire connections 1037
X20DID371 X20 digital input module, 8 inputs, 24 VDC, sink, configurable input filter, 2-wire connections 1043
X20DIF371 X20 digital input module, 16 inputs, 24 VDC, sink, configurable input filter, 1-wire connections 1049
Digital input/output modules
X20DM9324 X20 digital mixed module, 8 inputs, 24 VDC, sink, configurable input filter, 4 outputs, 24 VDC, 0.5 A, source, 1056
1-wire connections
Digital output modules
X20DO2321 X20 digital output module, 2 outputs, 24 VDC, 0.5 A, sink, 3-wire connections 1066
X20DO2322 X20 digital output module, 2 outputs, 24 VDC, 0.5 A, source, 3-wire connections 1074
X20DO2623 X20 digital output module, 2 outputs, 100-240 VAC, 1 A, source, 240 V keyed, 3-wire connections 1082
X20DO2633 X20 digital output module, 2 triac outputs, 12 to 240 VAC, 2 A, L switching, phase angle control, 240 V keyed 1091
X20DO2649 X20 digital output module, 2 relays, changeover contacts, 230 VAC / 5 A, 24 VDC / 5 A 1106
X20DO4321 X20 digital output module, 4 outputs, 24 VDC, 0.5 A, sink, 3-wire connections 1112
X20DO4322 X20 digital output module, 4 outputs, 24 VDC, 0.5 A, source, 3-wire connections 1120
X20DO4331 X20 digital output module, 4 outputs, 24 VDC, 2 A, sink, 3-wire connections 1128
X20DO4332 X20 digital output module, 4 outputs, 24 VDC, 2 A, source, 3-wire connections 1138
X20DO4529 X20 digital output module, 4 relays, changeover contacts, 115 VAC / 0.5 A, 24 VDC / 1 A 1148
X20DO4613 X20 digital output module, 4 triac coupler outputs, 12 to 240 VAC, 50 mA, zero-crossing detection, 240 V keyed,... 1154
X20DO4623 X20 digital output module, 4 outputs, 100-240 VAC, 0.5 A, source, 240 V keyed, 2-wire connections 1167
X20DO4633 X20 digital output module, 4 triac outputs, 12 to 240 VAC, 1 A, L switching, phase angle control, 240 V keyed 1175
X20DO4649 X20 digital output module, 4 relays, N.O. contacts, 240 VAC / 5 A 1190
X20DO6321 X20 digital output module, 6 outputs, 24 VDC, 0.5 A, sink, 2-wire connections 1196

X20 system User's Manual 3.10 123

X20 system modules • Module overview: Grouped
Product ID Short description on page
X20DO6322 X20 digital output module, 6 outputs, 24 VDC, 0.5 A, source, 2-wire connections 1202
X20DO6529 X20 digital output module, 6 relays, normally open contacts, 115 VAC / 0.5 A, 30 VDC / 1 A 1222
X20DO6639 X20 digital output module, 6 relays, normally open contacts, 240 VAC / 2 A, 30 VDC / 2 A 1228
X20DO8232 X20 digital output module, 8 outputs, 12 VDC, 2.0 A, source, supply directly on module, 1 wire technology 1234
X20DO8322 X20 digital output module, 8 outputs, 24 VDC, 0.5 A, source, 1-wire connections 1245
X20DO8323 X20 digital output module, 8 outputs, 12 to 24 V, 0.5 A, sink/source, 1-wire connections, full bridge, half bridge, 1252
thermal overload protection
X20DO8331 X20 digital output module, 8 outputs, 24 VDC, 2 A, sink, supply directly on module, 1-wire connections 1260
X20DO8332 X20 digital output module, 8 outputs, 24 VDC, 2 A, source, supply directly on module, 1-wire connections 1271
X20DO9321 X20 digital output module, 12 outputs, 24 VDC, 0.5 A, sink, 1-wire connections 1282
X20DO9322 X20 digital output module, 12 outputs, 24 VDC, 0.5 A, source, 1-wire connections 1289
X20DOD322 X20 digital output module, 8 outputs, 24 VDC, 0.5 A, source, 2-wire connections 1297
X20DOF322 X20 digital output module, 16 outputs, 24 VDC, 0.5 A, source, 1-wire connections 1303
Digital signal processing and preparation
X20CM1201 X20 combination module, 1 AB incremental encoder, 24 V, 4 digital inputs 24 V, 4 channels 24 V configurable 1312
as inputs or outputs, flexible digital controller logic
X20DC1073 X20 digital counter module, 1x SinCos, 1 Vss, 400 kHz input frequency, encoder monitoring, NetTime module 1332
X20DS1828 X20 digital signal module, 1x HIPERFACE, NetTime module 1337
X20DS1928 X20 digital signal module, 1x EnDat 2.1/2.2, NetTime module 1399
X20DS438A X20 digital signal module, 4x I/O Link master V1.1, can also be configured as 4x digital input or output channels, 2244
3-wire connections
Dummy modules
X20IF0000 X20 dummy interface module (non-functional) 1453
X20ZF0000 Dummy X20 module (non-functional) 1455
X20ZF000F Dummy X20 module (non-functional) 1458
Expandable bus controllers
X20BC1083 X20 bus controller, 1 POWERLINK interface, integrated 2-port hub, supports X20 interface module expansions, 1708
2 RJ45, order bus base, power supply module and terminal block separately.
X20BC8083 X20 bus controller, POWERLINK interface, integrated 2x hub, supports X20 hub module expansions, 2x RJ45 1713
connection, order bus base, power supply module and terminal block separately.
X20BC8084 X20 bus controller, POWERLINK interface, integrated compact link selector supports active X20 hub module 1718
expansions, 2x RJ45 connection, order bus base, power supply module and terminal block separately.
X20BC80G3 X20 bus controller, EtherCAT interface, supports expansion with X20 EtherCAT junction modules, 2x RJ45 1733
connection, order bus base, supply module and terminal separately!
Fieldbus CPUs
X20XC0201 X20 CPU, fieldbus CPU µP 16, 100 kB SRAM, 1 MB FlashPROM, support of RS232, CAN and interface module, 1748
according to fieldbus CPU base, order power supply module, bus base and terminal block separately
X20XC0202 X20 CPU, fieldbus CPU µP 25, 750 kB SRAM, 3 MB FlashPROM, support of RS232, CAN and interface module, 1748
according to fieldbus CPU base, order power supply module, bus base and terminal block separately
X20XC0292 X20 CPU, fieldbus CPU µP 25, 750 kB SRAM, 3 MB FlashPROM, support of RS232, CAN and interface module, 1748
according to fieldbus CPU base, 1 Ethernet interface 100 Base-T, order bus base, power supply module and
terminal block separately
Motor controllers
X20MM2436 X20 PWM motor module, 24 to 39 VDC ±25%, 2 PWM motor bridges, 3 A continuous current, 3.5 A peak current, 1913
4 digital inputs 24 VDC, sink, configurable as incremental encoder
X20MM3332 X20 digital motor module, 24 VDC, 3 digital outputs, full bridge (H bridge), 3 A continuous current, 5 A peak 1930
current
X20MM4331 X20 digital motor module, 24 VDC, 4 digital outputs, half bridge, 3 A continuous current, 5 A peak current 1944
X20MM4456 X20 PWM motor module, 24 to 48 VDC ±25%, 4 PWM motor bridges, 6 A continuous current, 10 A peak current, 1956
4x 4 digital inputs 24 VDC, sink, configurable as incremental encoder
X20SM1426 X20 stepper motor module, 1 motor connection, 1 A continuous current, 1.2 A peak current, 4 digital inputs 24 1976
VDC, sink, can be configured as incremental encoder
X20SM1436 X20 stepper motor module, module supply 24-39 VDC ±25%, 1 motor connection, 3 A continuous current, 3.5 2020
A peak current, 4 digital inputs 24 VDC, sink, can be configured as incremental encoder
Other functions
X20CM4810 X20 analog input module for vibration measurement and analyse of condition monitoring exercises. 4 IEPE 2067
analog input 51,5625 kHz sampling frequency 24 bit converter resolution
X20CM8281 X20 universal mixed module, 4 digital inputs, 24 VDC, sink, 1-wire connections, 2 digital outputs, 0.5 A, source, 2210
1-wire connections, 1 analog input, ±10 V or 0 to 20 mA / 4 to 20 mA, 12-bit resolution, 1 analog output, ±10 V /
0 to 20 mA, 12-bit resolution, 2 counters as event counters or gate measurement
X20CM8323 X20 PWM module, 8 digital outputs for switching electromechanical loads, 0.6 A continuous current, 2 A peak 2227
current, current monitoring, switching time detection
X20PD0011 X20 potential distributor module, 12x GND, integrated microfuse 2308
X20PD0012 X20 potential distributor module, 12x 24 VDC, integrated microfuse 2312
X20PD0016 X20 potential distributor module, 5x GND, 5x 24 VDC, floating feed, integrated microfuse 2316
X20PD2113 X20 potential distributor module, 6x GND, 6x 24 VDC, with feed option, integrated microfuse 2320
X20PS4951 X20 power supply module for potentiometers, 4x ±10 V for potentiometer supply 2325
Power supplies
X20PS2100 X20 supply module for internal I/O supply 2331
X20PS2110 X20 supply module for internal I/O supply, integrated microfuse 2335
X20PS3300 X20 supply module for X2X Link and internal I/O supply 2340
X20PS3310 X20 supply module for X2X Link and internal I/O supply, integrated microfuse 2346
Sensors
0ACS100A.00-1 Acceleration sensor, nominal sensitivity 100 mV/g, top exit 2204
0ACS100A.90-1 Acceleration sensor, nominal sensitivity 100 mV/g, side exit 2206
System modules for X20 redundancy systems
X20HB2885 X20 hub expansion module, integrated active 2x hub, 2x RJ45 2383

124 X20 system User's Manual 3.10

 X20 system modules • Module overview: Grouped
Product ID Short description on page
X20HB2886 X20 hub expansion module, integrated active 2x hub, 2 fiber optic connections 2386
System modules for bus controllers
X20BB80 X20 bus base for X20 base module (BC, HB, ...) and X20 supply module, X20AC0SL1/X20AC0SR1 X20 end 570
plates left and right included
X20PS9400 X20 supply module for bus controller and internal I/O supply, X2X Link supply 572
X20PS9402 X20 supply module, for bus controller and internal I/O supply, X2X Link supply, supply not electrically isolated 578
System modules for compact CPUs
X20BB22 X20 Compact CPU base, for Compact CPU and Compact CPU power supply module, base for integrated RS232 630
interface, X20 connection, X20AC0SL1/X20AC0SR1 X20 end plates left and right included
X20BB27 X20 Compact CPU base, for Compact CPU and Compact CPU power supply module, base for integrated RS232 632
and CAN interface, X20 connection, X20AC0SL1/X20AC0SR1 X20 end plates left and right included
X20PS9500 X20 supply module for compact and fieldbus CPUs and internal I/O supply, X2X Link supply 634
X20PS9502 X20 power supply module for compact and fieldbus and internal I/O supply, X2X Link bus supply, supply not 639
electrically isolated
System modules for expandable bus controllers
X20BB81 X20 bus base with 1 expansion slot for X20 base module (BC, HB, ...) and an X20 auxiliary module (IF, HB, ...) 1738
and X20 power supply module, X20AC0SL1/X20AC0SR1 X20 end plates left and right included
X20BB82 X20 bus base with 2 expansion slots for X20 base module (BC, HB, ...) and two X20 auxiliary modules (IF, 1740
HB, ...) and X20 power supply module, X20AC0SL1/X20AC0SR1 X20 end plates left and right included
X20IF1091-1 X20 interface module for expandable bus controller, 1 X2X Link master interface, electrically isolated, order 1x 1742
TB704 terminal block separately.
System modules for fieldbus CPUs
X20BB32 X20 Fieldbus CPU base, for Fieldbus CPU and Compact CPU power supply module, base for integrated RS232 1756
interface, slot for X20 interface module, X20 connection, X20AC0SL1/X20AC0SR1 X20 end plates left and right
included
X20BB37 X20 Fieldbus CPU base, for Fieldbus CPU and Compact CPU power supply module, base for integrated RS232 1758
and CAN interface, slot for X20 interface module, X20 connection, X20AC0SL1/X20AC0SR1 X20 end plates
left and right included
X20BB42 X20 Fieldbus CPU base, for Fieldbus CPU and Compact CPU power supply module, base for integrated RS232 1760
interface, 2 slots for X20 interface modules, X20 connection, X20AC0SL1/X20AC0SR1 X20 end plates left and
right included
X20BB47 X20 Fieldbus CPU base, for Fieldbus CPU and Compact CPU power supply module, base for integrated RS232 1762
and CAN interface, 2 slots for X20 interface modules, X20 connection, X20AC0SL1/X20AC0SR1 X20 end plates
left and right included
X20IF1074 X20 interface module for SGC, 1 CAN interface, max. 1 Mbit/s, electrically isolated, order 1x TB2105 terminal 1764
block separately
System modules for the X20 hub system
X20HB1881 X20 hub expansion module, integrated 1x hub, 1 fiber optic connection 2367
X20HB2880 X20 hub expansion module, 2x RJ45 2370
X20HB2881 X20 hub expansion module, integrated 2x hub, for fiber optic connection 2373
X20HB28G0 X20 EtherCAT junction module, 2x EtherCAT junction, 2x RJ45 connection 2376
X20PS8002 X20 supply module for standalone hub and compact link selector 2379
Temperature measurement
X20AT2222 X20 temperature input module, 2 inputs for resistance measurement, PT100, PT1000, resolution 0.1°C, 3-wire 2391
connections
X20AT4222 X20 temperature input module, 4 inputs for resistance measurement, PT100, PT1000, resolution 0.1°C, 3-wire 2400
connections
X20ATA312 X20 temperature input module, 2 inputs for resistance measurement, PT100, resolution 0.01 K, 4-wire connec- 2409
tion
X20ATA492 X20 temperature input module, 2 thermocouple inputs, type J, K, N, S, B, R, E, C, T, each channel electrically 2420
isolated, 2x PT1000 input for terminal temperature compensation with terminal block X20TB1E, order terminal
block separately.
X20ATB312 X20 temperature input module, 4 inputs for resistance measurement, PT100, resolution 0.01°C, 4-wire connec- 2442
tions
X20ATC402 X20 temperature input module, 6 thermocouple inputs, type J, K, N, S, B, R, E, C, T, 2x PT1000 integrated for 2453
terminal temperature compensation, with 1x X20TB1E terminal block, order terminal block separately.
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 V coded 2475
X20TB12 X20 terminal block, 12-pin, 24 V keyed 2475
X20TB1E X20 terminal block, 12-pin, 24 VDC keyed, 2x PT1000 integrated for terminal temperature compensation 2477
X20TB1F X20 terminal block, 16-pin, 24 VDC keyed 2479
X20TB32 X20 terminal block, 12-pin, 240 VAC keyed 2481
X20 CPUs
X20CP1483 X20 CPU, x86 100 MHz Intel compatible, 32 MB DRAM, 128 kB SRAM, removable application memory: Com- 896
pactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20
locking plate (right) X20AC0SR1 included, order application memory separately.
X20CP1483-1 X20 CPU, x86 100 MHz Intel compatible, 64 MB DRAM, 128 kB SRAM, removable application memory: Com- 896
pactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20
locking plate (right) X20AC0SR1 included, order application memory separately.
X20CP1583 X20 CPU, ATOM 333 MHz compatible, 128 MB DDR2 RAM, 1 MB SRAM, removable application memory: 913
CompactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and
X20 locking plate (right) X20AC0SR1 included, order application memory separately.
X20CP1584 X20 CPU, ATOM 0.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: CompactFlash, 913
1 insert slot for X20 interface modules, 2 USB ports, 1 RS232 interface, 1 Ethernet interface 10/100/1000 Base-
T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20 locking plate
(right) X20AC0SR1 included, order application memory separately.

X20 system User's Manual 3.10 125

X20 system modules • Module overview: Grouped
Product ID Short description on page
X20CP1585 X20 CPU, ATOM 1.0 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: CompactFlash, 913
1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface 10/100/1000
Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20 locking
plate (right) X20AC0SR1 included, order application memory separately.
X20CP1586 X20 CPU, ATOM 1.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: CompactFlash, 913
1 insert slot for X20 interface modules, 2 USB ports, 1 RS232 interface, 1 Ethernet interface 10/100/1000 Base-
T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20 locking plate
(right) X20AC0SR1 included, order application memory separately.
X20CP3583 X20 CPU, ATOM 333 MHz compatible, 128 MB DDR2 RAM, 1 MB SRAM, removable application memory: 917
CompactFlash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet inter-
face 10/100/1000 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot covers
and X20 locking plate (right) X20AC0SR1 included, order application memory separately.
X20CP3584 X20 CPU, ATOM 0.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: Compact- 917
Flash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000BASE-T, 1 POWERLINK interface, incl. supply module, 1 terminal block, slot cover and X20 locking
plate (right) included, order application memory separately.
X20CP3585 X20 CPU, ATOM 1.0 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: Compact- 917
Flash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000BASE-T, 1 POWERLINK interface, incl. supply module, 1 terminal block, slot cover and X20 locking
plate (right) included, order application memory separately.
X20CP3586 X20 CPU, ATOM 1.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: Compact- 917
Flash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000BASE-T, 1 POWERLINK interface, incl. supply module, 1 terminal block, slot cover and X20 locking
plate (right) included, order application memory separately.
X20 electronics module communication
X20CS1011 X20 interface module, 1 Moeller SmartWire interface 1461
X20CS1012 X20 interface module, 1x M-Bus master, integrated slave supply 1476
X20CS1013 X20 interface module, 1x DALI master 1524
X20CS1020 X20 interface module, 1 RS232 interface, max. 115.2 kbit/s 1533
X20CS1030 X20 interface module, 1 RS422/485 interface, max. 115.2 Mbit/s 1575
X20CS1070 X20 interface module, 1x CAN, max. 1 Mbit/s, object buffer in transmit and receive direction 1617
X20CS2770 X20 interface module, 2x CAN, max. 1 Mbit/s, object buffer in transmit and receive direction 1662
X20 hub system
X20ET8819 X20 Ethernet analysis tool, can be expanded with active hub modules, 2x RJ45 1884
X20HB8815 X20 POWERLINK - TCP/IP gateway, can be expanded with active hub modules, 2x RJ45 1897
X20HB8880 X20 hub base module, integrated 2x hub, 2x RJ45 1904
X20HB88G0 X20 EtherCAT junction base module integr. 2x EtherCAT junction, 2x RJ45 connection 1908
X20 interface module communication
X20IF1020 X20 interface module, 1 RS232, max. 115.2 kbit/s, electrically isolated 1769
X20IF1030 X20 interface module, 1 RS422/RS485, max. 115.2 kbit/s, electrically isolated 1772
X20IF1041-1 X20 interface module, for DTM configuration, 1 CANopen master interface, electrically isolated, order 1x TB2105 1775
terminal block separately.
X20IF1043-1 X20 interface module, for DTM configuration, 1 CANopen slave interface, electrically isolated, order 1x TB2105 1779
terminal block separately.
X20IF1051-1 X20 interface module, for DTM configuration, 1 DeviceNet scanner (master) interface, electrically isolated, order 1783
1x TB2105 terminal block separately.
X20IF1053-1 X20 interface module, for DTM configuration, 1 DeviceNet adapter (slave) interface, electrically isolated, order 1787
1x TB2105 terminal block separately.
X20IF1061 X20 interface module, 1 PROFIBUS DP V1 master interface, max. 12 Mbit/s, max. 3.5 kB input data and max. 1791
3.5 kB output data, electrically isolated
X20IF1061-1 X20 interface module for DTM configuration, 1 PROFIBUS DP V0/V1 master interface, electrically isolated 1794
X20IF1063 X20 interface module, 1 PROFIBUS DP V0 slave interface, max. 12 Mbit/s, electrically isolated 1798
X20IF1063-1 X20 interface module, for DTM configuration, 1 PROFIBUS DP V1 slave interface, electrically isolated 1801
X20IF1065 X20 interface module, 1 PROFIBUS DP V1 slave interface, max. 12 Mbit/s, electrically isolated 1805
X20IF1072 X20 interface module, 1 CAN interface, max. 1 Mbit/s, electrically isolated, order 1x TB2105 terminal block 1808
separately.
X20IF1082 X20 interface module, 1 POWERLINK interface, managing or controlled node, integrated 2x hub, ring redun- 1812
dancy function
X20IF1082-2 X20 interface module, 1 POWERLINK interface, managing or controlled node, integrated 2x hub, ring redun- 1818
dancy function, PRC function
X20IF1086-2 X20 interface module, 1 POWERLINK interface, managing or controlled node, PRC function, 1x fiber optic 1824
connection
X20IF1091 X20 interface module, 1 X2X Link master interface, electrically isolated, order 1x TB704 terminal block sepa- 1830
rately.
X20IF10A1-1 X20 interface module, for DTM configuration, 1 ASi master interface, electrically isolated, order 1x TB704 ter- 1833
minal block separately.
X20IF10D1-1 X20 interface module, for DTM configuration, 1 EtherNet/IP scanner (master) interface, electrically isolated 1837
X20IF10D3-1 X20 interface module, for DTM configuration, 1 EtherNet/IP adapter (slave) interface, electrically isolated 1841
X20IF10E1-1 X20 interface module for DTM configuration, 1 PROFINET RT controller (master) interface, electrically isolated 1845
X20IF10E3-1 X20 interface module, for DTM configuration, 1 PROFINET RT device (slave) interface, electrically isolated 1849
X20IF10G3-1 X20 interface module for DTM configuration, 1 EtherCAT slave interface, electrically isolated 1853
X20IF10X0 X20 interface module, 1 redundancy link interface 1000BASE-SX, CPU-CPU data synchronization module for 1857
controller redundancy
X20IF2181-2 X20 interface module, 1x link selector for POWERLINK cable redundancy, POWERLINK functions: - Managing 1860
node - Controlled node for iCN operation - Redundant managing node for CPU redundancy - Ring redundancy
- 2x hub - Multi ASend - PRC function 2x RJ45 connection
X20IF2772 X20 interface module, 2 CAN interfaces, max. 1 Mbit/s, electrically isolated, order 2x TB2105 terminal block 1874
separately.
X20IF2792 X20 interface module, 1 CAN interface, max. 1 Mbit/s, electrically isolated, 1 X2X Link master interface, elec- 1878
trically isolated, order 1x TB2105 and 1x TB704 terminal block separately.

126 X20 system User's Manual 3.10

 X20 system modules • Module overview: Grouped
Product ID Short description on page
X20 redundancy systems
X20HB8884 X20 compact link selector, 2x RJ45 connection, order bus base, power supply module and terminal block sep- 2353
arately.

X20 system User's Manual 3.10 127

X20 system modules • Analog input modules • Brief information

4.3 Analog input modules

Analog input modules convert measured values (voltages, currents) into numerical values, which can be processed
by the PLC.
In the PLC, analog data is always in 16-bit 2s complement regardless of the resolution. Therefore, the resolution
of the module used does not have to be taken into consideration when creating an application program.
Every channel on an analog input module has a status LED.

4.3.1 Brief information

Product ID Short description on page
X20AI1744 X20 analog input module, 1 full-bridge strain gauge input, 24-bit converter resolution, 5 kHz input filter 129
X20AI1744-3 X20 analog input module, 1 full-bridge strain gauge input, 24-bit converter resolution, 5 Hz input filter 129
X20AI2222 X20 analog input module, 2 inputs, ±10 V, 13-bit resolution, configurable input filter 144
X20AI2237 X20 analog input module, 2 inputs, ±10 V, 16-bit resolution, each channel electrically isolated and with own 152
sensor supply
X20AI2322 X20 analog input module, 2 inputs, 0-20 mA / 4-20 mA, 12-bit converter resolution, configurable input filter 167
X20AI2437 X20 analog input module, 2 inputs, 4 to 20 mA, 16-bit resolution, each channel electrically isolated and with 176
own sensor supply
X20AI2438 X20 analog input module, 2 inputs, 4 to 20 mA, 16-bit resolution, each channel electrically isolated and with 193
own sensor supply, HART protocol supported
X20AI2622 X20 analog input module, 2 inputs, ±10 V or 0 to 20 mA / 4 to 20 mA, 13-bit resolution, configurable input filter 249
X20AI4222 X20 analog input module, 4 inputs, ±10 V, 13-bit resolution, configurable input filter 259
X20AI4322 X20 analog input module, 4 inputs, 0-20 mA / 4-20 mA, 12-bit converter resolution, configurable input filter 267
X20AI4622 X20 analog input module, 4 inputs, ±10 V or 0 to 20 mA / 4 to 20 mA, 13-bit resolution, configurable input filter 276
X20AI8221 X20 analog input module, 8 inputs, ±10 V, 13-bit converter resolution 286
X20AI8321 X20 analog input module, 8 inputs, 0-20 mA, 12-bit resolution 294
X20AP3111 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 20 mA AC, calculates 304
effective, reactive and apparent power/energy, calculates root mean square values, 240 V keyed
X20AP3121 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 1 A AC, calculates 304
effective, reactive and apparent power/energy, calculates root mean square values, 240 V keyed
X20AP3131 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 5 A AC, calculates 304
effective, reactive and apparent power/energy, calculates root mean square values, 240 V keyed
X20AP3161 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 333 mV AC, calculates 304
effective, reactive and apparent power/energy, calculates root mean square values, 240 V keyed

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4.3.2 X20AI1744, X20AI1744-3

4.3.2.1 General Information

The X20AI1744 and X20AI1744-3 modules work with both 4-line and 6-line strain gauge cells. If a 6-line strain
gauge cell is connected, the line compensation no longer functions. This module concept requires compensation
in the measurement system. This compensation eliminates the absolute uncertainty in the measurement circuit,
suchas component tolerances, effective bridge voltage, or zero offset. The measurement precision refers to the
absolute (compensated) value, which will only change as a result of changes in the operating temperature.
The AI1744 analog input module is available in two versions:
Model number Description
X20AI1744 The module is equipped with a 5kHz input filter for fast signal sequences. It therefore also allows high frequency signals and
disturbances to pass through.
X20AI1744-3 This version is equipped with a slow 5Hz input filter. It is therefore suitable for slow signal sequences and provides good suppres-
sion of high frequency disturbance signals.

• 1 full-bridge strain gauge input

• Data output rate can be set from 2.5 Hz to 7.5 kHz
• Special operating modes (synchronous mode and multiple sampling)

4.3.2.2 Order data

Model number Short description Figure

Analog input modules
X20AI1744 X20 analog input module, 1 full-bridge strain gauge input, 24-bit
converter resolution, 5 kHz input filter
X20AI1744-3 X20 analog input module, 1 full-bridge strain gauge input, 24-bit
converter resolution, 5 Hz input filter
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 18: X20AI1744, X20AI1744-3 - Order data

4.3.2.3 Technical data

Product ID X20AI1744 X20AI1744-3

Short description
I/O module 1 full-bridge strain gauge input
General information
B&R ID code 0x1CDE 0xA4EF
Status indicators Channel status, operating status, module status
Diagnostics
Module run/error Yes, using status LED and software
Open line Yes, using status LED and software
Input Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.25 W
Additional power dissipation caused by the actua- Max. 0.36 W 1)
tors (resistive) [W]
Electrical isolation
Bus - Analog input Yes
Bus - Bridge supply voltage Yes
Channel - I/O supply No
Certification
CE Yes
cULus Yes
KC Yes
GOST-R Yes
Full-bridge strain gauge
Strain gauge factor ±2 to ±256 mV/V, configurable using software

Table 19: X20AI1744, X20AI1744-3 - Technical data

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Product ID X20AI1744 X20AI1744-3
Connection 4- or 6-wire connections 2)
Input type Differential, used to evaluate a full-bridge strain gauge
Digital converter resolution 24-bit
Conversion time Depends on the configured data output rate
Data output rate 2.5 - 7500 samples per second, configurable using software (fDATA)
Input filter
Cutoff frequency 5 kHz 5 Hz
Orderliness 3
Slope 60 dB
ADC filter characteristics Sigma-Delta, see section "Filter characteristics of the Sigma-Delta ADC"
Operating range / Measurement sensor 85 to 5000 Ω
Influence of cable length The shielded, twisted pair cable should be as short as possible and run sepa-
rately to the sensor (isolated from load circuit) without intermediate terminals
Input protection RC protection
Input current 690 nA
Common-mode range 0 to 3 VDC
Permissible input voltage range (with regard to the poten-
tial strain gauge GND) on the inputs "Input +" and "Input -"
Isolation voltage between input and bus 500 Veff
Conversion procedure Sigma-Delta
Output of the digital value
Broken bridge supply line Value approaches 0
Broken sensor line Value approaches ±end value (Status bit "open circuit" in register Module status is set)
Valid value range 0x007FFFFF to 0xFF800001
Strain gauge supply
Voltage 5.5 VDC / max. 65 mA 3)
Short circuit protection, overload protection Yes
Voltage drop for short circuit protection Max. 0.2 VDC at 65 mA
Quantization
LSB value (16-bit)
2 mV/V 336 nV
4 mV/V 671 nV
8 mV/V 1.343 µV
16 mV/V 2.686 µV
32 mV/V 5.371 μV
64 mV/V 10.74 μV
128 mV/V 21.48 μV
256 mV/V 42.97 μV
LSB value (24-bit)
2 mV/V 1.31 nV
4 mV/V 2.62 nV
8 mV/V 5.25 nV
16 mV/V 10.49 nV
32 mV/V 20.98 nV
64 mV/V 41.96 nV
128 mV/V 83.92 nV
256 mV/V 167.85 nV
Temperature coefficient
Rev. ≤D1 30 ppm/°C
Rev. ≥E0 10 ppm/°C
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation 0 to 55°C
Vertical installation 0 to 50°C
Derating -
Storage -25 to 70°C
Transport -25 to 70°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing

Table 19: X20AI1744, X20AI1744-3 - Technical data

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Product ID X20AI1744 X20AI1744-3
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 19: X20AI1744, X20AI1744-3 - Technical data

1) Depends on the full-bridge strain gauge used
2) With 6-wire connections, line compensation does not function. (See section "Connection examples")
3) The maximum current of 90 mA is permitted up to an operating temperature of 45°C.

4.3.2.4 Status LEDs

The status LEDs are identical on the X20AI1744 and X20AI1744- 3 modules.
Image LED Color Status Description
r Green Off No power to module
Single flash Reset mode
Double flash Boot mode (during firmware update)
Blinking Preoperational mode
On RUN mode
e Red Off Module supply not connected or everything OK
On Error or reset status
1 Green Off Possible causes:
• Open line
• Sensor is unplugged
• Converter is busy
On Analog/digital converter running, value OK

Table 20: Status LEDs

4.3.2.5 Pinout

The pinouts are identical on the X20AI1744 and X20AI1744- 3 modules.

r e
X20 AI 1744

Strain gauge VCC Strain gauge VCC

Strain gauge VCC Strain gauge VCC

Input + Input +

Input - Input -

Strain gauge GND Strain gauge GND

Strain gauge GND Strain gauge GND

Figure 48: Pinout

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4.3.2.6 Connection examples

Full-bridge strain gauge with 4-line connection

AI

Full-bridge strain gauge

+U

- +

+24 VDC +24 VDC

GND GND

Figure 49: Connection example - Full-bridge strain gauge with 4-line connection

Full-bridge strain gauge with 6-line connection

Precision can be improved by using strain gauge cells with feedback of the bridge voltage. The additional sensor
lines with the strain gauge bridge supply compensate for the thermal resistance change of the feed lines. If a 6-
line strain gauge cell is connected to the module, the sense lines are bypassed by the 4 internally linked strain
gauge VCC connections (i.e. strain gauge GND). For this reason, the line compensation no longer functions.
The measurement precision is therefore affected by changes in operating temperature. Longer cable lengths and
smaller cable cross-sections also increase the potential for errors in the measurement system.
In order to reduce cable resistance, the sense lines should be connected in parallel with the strain gauge bridge
supply lines. Optimal signal quality can be obtained by using a shielded twisted pair cable. The connections for the
strain gauge supply lines, the sensor lines, and the bridge differential voltage lines should each use one twisted
pair cable.

AI

Full-bridge strain gauge

+U +U Sense

- +

⊥ ⊥ Sense

+24 VDC +24 VDC

GND GND

Figure 50: Connection example - Full-bridge strain gauge with 6-line connection

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Parallel connection of 2 full-bridge strain gauges with 4-line connections

For parallel connection of full-bridge strain gauges, please refer to the manufacturer's guidelines.

AI

Full-bridge strain gauge 1 Full-bridge strain gauge 2

+U +U

- + + -

⊥ ⊥

+24 VDC +24 VDC

GND GND

Figure 51: Connection example - Parallel connection of 2 full-bridge strain gauges

When connecting 3 or more full-bridge strain gauges in parallel, two lines must be connected together in an X20
terminal block.

4.3.2.7 Input circuit diagram

Strain gauge VCC Reference

Strain gauge VCC Reference

local
Processor port
Input +
+

Input -
Filters
60 db / dec. -
Strain gauge GND

AD converter
Strain gauge GND

Figure 52: Input circuit diagram

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4.3.2.8 Filter characteristics of the Sigma-Delta ADC

Gain

0 4x 8x 12 x 16 x 20 x 24 x

1xf
DATA Frequency

4.3.2.9 Effective resolution of the AD converter

The AD converter on the AI1744 provides a 24 bit measurement value. However, the actual attainable noise-free
resolution is always less than 24 bit. This "effective resolution" depends on the data rate and measurement range.
Example:
Because of the conversion methods, a data rate of 2.5 Hz and a specified measurement area of 2 mV/V result in
an effective resolution of 18.7 bits:
24-bit

23 21 20 16 15 12 11 8 7 4 3 0

18.7-bit

Figure 53: Example for the effective resolution of the AD converter

The low-order bits (grayed out) contain only noise instead of valid values and must therefore not be evaluated.
With the multiple sampling function model, only the highest 16 bits are made available.

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4.3.2.10 Calculation example / Quantization

In a weighing application, the corresponding weight located on the connected load cell should be determined from
the value derived from the X20AI1744.
The characteristics of the strain gauge load cell are as follows:
• Rated load: 1000 kg
• Bridge factor: 4 mV/V
The value for the positive full-scale deflection at a specified rated load of 1000kg is derived from the bridge factor
of the strain gauge load cell (multiplication with the bridge supply voltage from the AI1744 module):
4 mV/V × 5.5 V = 22 mV
With a simple Rule of Three calculation, the corresponding value can be calculated (as seen in the table) from
weight to the converter value and vice versa. This simplified theoretical approach is only valid for an ideal mea-
surement system. Calibration of the entire measurement system is recommended because not only the X20AI1744
module, but particularly the strain gauge bridges feature tolerances (offset, gain). When taring, the gradient offset
is recalculated and the gain of the linear equation is determined when standardized. In addition to the calculation
displayed in the table, these calculations must also be carried out in the application.
24 bit value from the X20AI1744 Quantization Corresponding weight
0x007F FFFF 8,388,607 22.0 mV 1000 kg
0x0000 0001 1 2.62 nV 0.119 g
0x0000 20C3 8,387 22.0 μV 1 kg
0x0001 0000 65,536 171.9 μV 7.81 kg

Table 21: X20AI1744 - Calculation example / Quantization

The values for each LSB can be found in the technical data of the X20AI1744, under "Quantization" (1 LSB in
reference to 16 bit and 1 LSB in reference to 24 bit).

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4.3.2.11 Register description

4.3.2.11.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 StatusInput01 USINT ●
4 AnalogInput01 DINT ●
16 ConfigOutput01 USINT ●
18 ConfigCycletime01 UINT ●
32 AdcClkFreqShift011) USINT ●

1) X20AI744: from firmware version 8 / upgrade 1.3.0.0; X20AI744-3: from firmware version 8 / upgrade 1.2.0.0

4.3.2.11.2 Function model 1 - Multiple sampling

In this function model, the AD converter is operated in synchronization with X2X Link using a fixed ADC cycle time
(configurable as 50 or 100 µs).
The module returns between 3 and 10 measured values per X2X cycle depending on the configuration. With an
X2X cycle time of 400 µs and ADC cycle time of 50 µs, exactly 8 measurements are performed and the module
can return 8 values (strain gauge value 01 to strain gauge value 08).
If a longer cycle time is used, the values returned correspond to the last measurements. If using an X2X cycle time
that is not a whole number multiple of the ADC cycle time, then the conversion cannot be synchronized with X2X
Link. In this case, the module outputs the invalid value 0x8000.
Example 1
With an X2X cycle time of 800 µs, 16 measurements are performed per X2X cycle. The first 6 measured values
are discarded; the last 10 measured values are provided by the module.
With a shorter X2X cycle time, the number of measured values should not exceed the number of measurements
that can actually be made. All other measured values are invalid (0x8000). To minimize the load on X2X Link, it is
possible to disable unneeded registers (see "Number of measurement values").
Example 2
If using an X2X cycle time of 300 μs, it is possible to perform 6 measurements per X2X cycle if the ADC cycle
time equals 50 µs. For this reason, only the first 6 registers are valid. The registers for the 7th through 10th mea-
sured value (AnalogInput07 to AnalogInput08) should be disabled by setting "Number of measured values" to "6
measured values" in the I/O configuration.
Register Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
2 StatusInput01 USINT ●
1534 + N * 4 AnalogInput0N (N = 1 to 10) INT ●
1600 ConfigOutput01 (X20AI1744) USINT ●
ConfigGain01_MultiSample (X20AI1744-3)
1603 ConfigCycletime01_MultiSample USINT ●

4.3.2.11.3 Function model 254 - Bus Controller

In the bus controller function model, the module behaves as it does in the standard function model, with the ex-
ception that it is not synchronized to the X2X Link even if Synchronous mode is activated in the ADC configuration
register. Instead, the module behaves as if the set ADC cycle time is not a factor or multiple of the X2X cycle time
and attempts to maintain the set ADC cycle time as precisely as possible.
Register Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
2 StatusInput01 USINT ●
4 AnalogInput01 DINT ●
16 ConfigOutput01 USINT ●
18 ConfigCycletime01 UINT ●
32 AdcClkFreqShift011) USINT ●

1) X20AI744: from firmware version 8 / upgrade 1.3.0.0; X20AI744-3: from firmware version 8 / upgrade 1.2.0.0

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4.3.2.11.4 Register for "Standard" and "Bus Controller" function model

4.3.2.11.4.1 Module status

Name:
StatusInput01
The current state of the module is indicated in this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 AD converter values 0 ADC value is valid
1 ADC value is invalid
1 Line monitoring 0 OK
1 Open line
2 Only valid in synchronous mode 0 ADC runs synchronous to the X2X Link
1 ADC does not run synchronous to the X2X Link
3-7 Reserved -

4.3.2.11.4.2 Strain gauge value

Name:
AnalogInput01
This register contains the ADC's raw value for the full-bridge strain gauge with 24-bit resolution.
Data type Value Information
DINT 0x007FFFFF to 0xFF800001 Valid value range
0x007FFFFF Overrun
0xFF800001 Underflow
0xFF800000 Invalid value

Effective resolution
In principle, the effective resolution of the AD converter is dependent on the data rate and the measurement range
(see "Effective resolution of the AD converter").
The following table shows how the effective resolution (in bits), or the effective value range of the strain gauge
value depend on the module configuration (data rate, measurement area).
Measurement range
Data rate ±16mV/V ±8mV/V ±4mV/V ±2mV/V
fDATA [Hz] Bits Scope Bits Scope Bits Scope Bits Scope
2.5 21.3 ±1,290,000 20.8 ±912,000 19.7 ±425,000 18.7 ±212,000
5 20.7 ±851,000 20.3 ±645,000 19.3 ±322,000 18.3 ±161,000
10 20.4 ±691,000 19.9 ±490,000 18.9 ±244,000 17.9 ±122,000
15 20.1 ±562,000 19.3 ±320,000 18.7 ±212,000 17.7 ±106,000
25 19.7 ±425,000 19.2 ±301,000 18.5 ±185,000 17.5 ±92,000
30 19.6 ±397,000 19.0 ±262,000 18.1 ±140,000 17.1 ±72,000
50 19.4 ±346,000 18.8 ±230,000 17.9 ±122,000 16.9 ±61,000
60 19.3 ±320,000 18.8 ±230,000 17.8 ±114,000 16.8 ±57,000
100 19.1 ±280,000 18.5 ±185,000 17.4 ±86,000 16.4 ±43,000
500 18.0 ±130,000 17.3 ±80,000 16.3 ±40,000 15.3 ±20,000
1000 17.2 ±75,000 16.5 ±46,000 15.6 ±25,000 14.6 ±12.00
2000 16.6 ±49,600 16.1 ±35,000 15.3 ±20,000 14.3 ±10,000
3750 16.2 ±37,600 15.7 ±26,600 14.7 ±13,000 13.7 ±6,600
7500 15.8 ±28,500 15.3 ±20,200 14.4 ±10,800 13.4 ±5,400

Table 22: Effective resolution of the strain gauge value in bits for the measurement range 2 to 16 mV/V

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Measurement range
Data rate ±256mV/V ±128mV/V ±64mV/V ±32mV/V
fDATA [Hz] Bits Scope Bits Scope Bits Scope Bits Scope
2.5 23 ±4,194,000 22.6 ±3,179,000 22.1 ±2,248,000 21.7 ±1,703,000
5 22.3 ±2,582,000 22.4 ±2,767,000 21.9 ±1,957,000 21.3 ±1,291,000
10 22.3 ±2,582,000 22 ±2,097,000 21.6 ±1,589,000 21 ±1,049,000
15 22 ±2,097,000 21.7 ±1,703,000 21.3 ±1,291,000 20.7 ±852,000
25 21.7 ±1,703,000 21.4 ±1,384,000 21.1 ±1,124,000 20.5 ±741,000
30 21.8 ±1,826,000 21.3 ±1,291,000 20.8 ±913,000 20.4 ±692,000
50 21.3 ±1,291,000 21.1 ±1,124,000 20.4 ±692,000 19.9 ±489,000
60 21.3 ±1,291,000 20.9 ±978,000 20.5 ±741,000 19.8 ±456,000
100 20.9 ±978,000 20.7 ±852,000 20.2 ±602,000 19.6 ±397,000
500 20.1 ±562,000 19.6 ±397,000 19.1 ±281,000 18.6 ±199,000
1000 19 ±262,000 18.6 ±199,000 18.1 ±140,000 17.5 ±93,000
2000 18.5 ±185,000 18.1 ±140,000 17.8 ±114,000 17 ±66,000
3750 18.1 ±140,000 17.8 ±114,000 17.3 ±81,000 16.6 ±50,000
7500 17.7 ±106,000 17.3 ±81,000 16.9 ±61,000 16.2 ±38,000

Table 23: Effective resolution of the strain gauge value in bits for the measurement range 32 to 256 mV/V

4.3.2.11.4.3 ADC configuration

Name:
ConfigOutput01
The sampling rate and measurement range for the AD converter can be configured in this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-3 Data rate fDATA (samples per second): 0000 2.5
0001 5
0010 10
0011 15
0100 25
0101 30
0110 50
0111 60
1000 100
1001 500
1010 1000
1011 2000
1100 3750
1101 7500
1110 Synchronous mode1)
1111 Reserved
4-5 Standard measurement range (bit 6 = 0) 00 16 mV/V
01 8 mV/V
10 4 mV/V
11 2 mV/V
Extended measurement range (bit 6 = 1)2) 00 256 mV/V
01 128 mV/V
10 64 mV/V
11 32 mV/V
6 0 Standard measurement range (2 to 16 mV/V)
1 Extended measurement range (32 to 256 mV/V)2)
7 Reserved 0 (must be 0)

1) ADC is operated synchronously with the X2X Link, if possible; beginning with firmware 2
2) Starting with Firmware Version 4

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Synchronous mode

Beginning with firmware version 2, the analog/digital converter (ADC) on the X20AI1744 module can be operated
and read synchronously with the X2X Link. Synchronous mode is activated by selecting the respective operating
mode in the ADC configuration register. A time between 200 and 2,000 µs must also be set in the ADC cycle time
register. If this time is a whole number factor or multiple of the configured cycle time of the X2X Link, then the ADC
is synchronously read with the X2X Link.

Information:
The ADC cycle time must be ≥1/4 of the X2X cycle time.
The bit 2 in Module Status is set (i.e. ADC does not run synchronously), ...
• ... if the configured ADC cycle time cannot be synchronized with the X2X Link.
• ... if the module is still in the settling phase.
Jitter, dead time and settling time:
Jitter
ADC cycle times <1500 μs Max. ±1 μs
ADC cycle times >1500 μs Max. ±4 μs
Dead time on the X2X Link X2X cycle time
50 μs +
128
Settling time
Firmware Version ≤ Max. 150 x ADC cycle time
Firmware Version ≥5 150 x X2X cycle time

Table 24: Jitter, dead time and settling time

The settling time corresponds to the time needed until the AD converter can be operated after activating the syn-
chronous mode or following conversion of the ADC cycle time.

4.3.2.11.4.4 ADC cycle time

Name:
ConfigCycletime01
This register is only used in "Synchronous mode". If synchronous mode is enabled in the ADC configuration, then
the module attempts to operate the ADC synchronously to the X2X Link (based on the ADC cycle time specified
in this register). It is necessary for the X2X Link cycle time and the ADC cycle time to have a certain relationship.
The following conditions must be adhered to:
1 ADC cycle time ≥ 1/4 X2X cycle time
2 ADC cycle time corresponds to a whole number factor or multiple of the X2X cycle time
3 ADC cycle time must be in the range from 50 to 2000 µs
Data type Value
UINT 50 to 2000

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4.3.2.11.4.5 ADC clock frequency shift

Name:
AdcClkFreqShift01
In rare cases, X20AI1744 connected to neighboring slots can influence one another. This can result in tempo-
rary, minimal deviations in measurement values. This can only occur if the SigmaDelta ADCs on the neighboring
X20AI1744 modules are operated at exactly the same clock frequency.
In most cases, these clock frequencies vary slightly due to part variances. When they are the same however, this
register on the X20AI1744 provides a safe way for an application to prevent this type of mutual influence.
Data type Value
SINT -128 to 127

This register can be used to vary the clock frequency in increments of 200 ppm. Setting values from -50 to 50 cover
a range of -10000 ppm to 10000 ppm. This corresponds with -1% to 1%.
Values beyond this range will cause activation of a default mode. The frequency shift is derived from the from the
last 2 digits of the serial number by the X20AI1744 firmware. This saves time that would otherwise be needed for
programming, provided that the last two digits of the serial numbers on the neighboring modules are not the same
Register value Frequency shift in ppm Example of a sampling rate1)
127 ((SerialNo. modulo 100) - 50) * (-200) ppm Based on the serial number
... ... ...
51 ((SerialNo. modulo 100) - 50) * (-200) ppm Based on the serial number
50 10000 505
49 9800 504.9
... ... ...
2 400 500.2
1 200 500.1
0 0 500
-1 -200 499.9
-2 -400 499.8
... ... ...
-50 -10000 495
-51 ((SerialNo. modulo 100) - 50) * (-200) ppm Based on the serial number
... ... ...
-128 ((SerialNo. modulo 100) - 50) * (-200) ppm Based on the serial number

Table 25: Frequency shift of the ADC clock

1) Nominal sampling rate of 500 samples per second

IMPORTANT:
As shown in the table above, shifting the ADC clock frequency will equally shift the ADC sampling rate. Shifting the
ADC clock frequency too much can cause problems with disturbance suppression particularly when a very specific
sampling rate has been defined to suppress existing disturbances (e.g: 50 Hz to suppress the 50 Hz hum). Also
see "Filter characteristics of the Sigma-Delta ADC".
It's situations like this where the option to manually shift the frequency in the I/O configuration or ASIOACC library
should be utilized rather than relying on the default frequency shift that is based on the serial number.
A frequency shift like the one shown below would be sufficient to prevent modules from influencing one another
and would not cause any noticeable difference to the filter characteristics.
Slot 1 2 3 4 5 6 ...
ADC clock frequency shift 0 2 -1 1 -2 0 ...

Information:
• This register has no effect in synchronous mode because the firmware regulates the ADC clock
frequency in such a way that the ADC conversion cycle is synchronous with the X2X cycle.
• When writing to this register using the ASIOACC library, only the lowest value byte of the written
value is accepted. For example, the value 256 (=0x100) is identical to the value 0 (=0x00).

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4.3.2.11.5 Register for "Multiple Sampling" function model

4.3.2.11.5.1 Module status

Name:
StatusInput01
The current state of the module is indicated in this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 AD converter values 0 ADC value is valid
1 ADC value is invalid
1 Line monitoring 0 OK
1 Open line
An open line was found during at least one measurement in this
X2X cycle. This bit is reset if all measurements are OK after
correcting this error, i.e. it does not have to be acknowledged.
2 Synchronous mode 0 ADC runs synchronous to the X2X Link
1 ADC does not run synchronous to the X2X Link
3-7 Reserved -

4.3.2.11.5.2 Strain gauge value - Multiple

Name:
AnalogInput01 to AnalogInput10
This register contains the raw value determined by the ADC for the full-bridge strain gauge with 16-bit resolution.
The module returns between 3 and 10 measured values per X2X cycle depending on the configuration.
Effective resolution
In principle, the effective resolution of the AD converter is dependent on the data rate and the measurement range
(see "Effective resolution of the AD converter").
The following table shows how the effective resolution (in bits), or the effective value range of the strain gauge
value depend on the module configuration (data rate, measurement area).
Measurement range
±16mV/V ±8mV/V ±4mV/V ±2mV/V
Bits Scope Bits Scope Bits Scope Bits Scope
15.4 22,000 14.6 12,000 13.8 7,000 12.8 4,000

Table 26: Effective resolution of the strain gauge value in bits for the measurement range 2 to 16 mV/V
Measurement range
±256mV/V ±128mV/V ±64mV/V ±32mV/V
Bits Scope Bits Scope Bits Scope Bits Scope
17.1 70,000 16.7 53,000 16.4 43,000 15.9 31,000

Table 27: Effective resolution of the strain gauge value in bits for the measurement range 32 to 256 mV/V

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4.3.2.11.5.3 ADC configuration

Name:
ConfigOutput01 (X20AI1744)
ConfigGain01_MultiSample (X20AI1744-3)
The measurement range for the AD converter can be configured in this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Standard measurement range (bit 2 = 0) 00 16 mV/V
01 8 mV/V
10 4 mV/V
11 2 mV/V
Extended measurement range (bit 2 = 1)1) 00 256 mV/V
01 128 mV/V
10 64 mV/V
11 32 mV/V
2 0 Standard measurement range (2 to 16 mV/V)
1 Extended measurement range (32 to 256 mV/V)1)
3-7 Reserved 0 (must be 0)

1) Starting with Firmware Version 4. In the standard measurement range (2 to 16 mV/V), open-circuit detection works reliably at all adjustable data rates. In
the extended measurement range (32 to 256 mV/V), open-circuit detection does not work reliably (because of the variable input impedance of the amplifier
in relation to the set data rate).

4.3.2.11.5.4 ADC cycle time

Name:
ConfigCycletime1_MultiSample
This register can be used to configured the ADC cycle time.
In order for multisampling to work, the X2X cycle time must be divisible by the ADC cycle time (i.e. results in a
whole number).
Data type Value Information
USINT 0 50 μs (default)
1 100 μs
2 - 255 Reserved

4.3.2.11.5.5 Number of measurement values

If the X2X cycle time is too short, then bot all 10 measurements can be performed. To reduce the load on X2X Link,
it makes sense to only transfer as many values as measurements that can be made. This is why it is possible to
configure the number of measured values to be transferred (see "Function model 1 - Multiple sampling").
Example: ADC cycle time 50 μs
X2X cycle time Number of measurement values to be transferred
250 μs 5
300 μs 6
350 μs 7
400 μs 8
450 μs 9
≥500 μs 10

Example: ADC cycle time 100 μs

X2X cycle time Number of measured values to be transferred
300 μs 3
400 μs 4
500 μs 5
600 μs 6
700 μs 7
800 μs 8
900 μs 9
≥1 ms 10

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4.3.2.11.6 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
250 μs

4.3.2.11.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
There is no limitation and no simple dependency on the bus cycle time. In the "Standard" function model, the I/O
update time is defined by the register "ADC configuration" and "ADC cycle time".
In the "Multiple Sampling" function model, the update time is 50 µs.

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4.3.3 X20AI2222

4.3.3.1 General information

The module is equipped with 2 inputs with 13-bit (including sign) digital converter resolution. It can be used to
capture voltage signals in the range from ±10 V.
This module is designed for X20 6-pin terminal blocks. If needed (e.g. for logistical reasons), the 12-pin terminal
block can also be used.
• 2 analog inputs ±10 V
• 13-bit digital converter resolution

4.3.3.2 Order data

Model number Short description Figure

Analog input modules
X20AI2222 X20 analog input module, 2 inputs, ±10 V, 13-bit resolution, con-
figurable input filter
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 28: X20AI2222 - Order data

4.3.3.3 Technical data

Product ID X20AI2222
Short description
I/O module 2 analog inputs ±10 V
General information
B&R ID code 0xCAB0
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Inputs Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 0.8 W 1)
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
GL Yes
GOST-R Yes
Analog inputs
Input ±10 V
Input type Differential input
Digital converter resolution ±12-bit
Conversion time 300 µs for all inputs
Output format
Data type INT
Voltage 0x8001 - 0x7FFF / 1 LSB = 0x0008 = 2.441 mV
Input impedance in signal range 20 MΩ
Input protection Protection against wiring with supply voltage
Permitted input signal Max. ±30 V

Table 29: X20AI2222 - Technical data

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Product ID X20AI2222
Output of the digital value during overload
Below lower limit 0x8001
Above upper limit 0x7FFF
Conversion procedure SAR
Input filter 3rd-order low pass / cutoff frequency 1 kHz
Max. error at 25°C
Gain 0.08% 2)
Offset 0.015% 3)
Max. gain drift 0.006 %/°C 2)
Max. offset drift 0.002 %/°C 3)
Common-mode rejection
DC 70 dB
50 Hz 70 dB
Common-mode range ±12 V
Crosstalk between channels -70 dB
Non-linearity <0.025% 3)
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 29: X20AI2222 - Technical data

1) To reduce power dissipation, B&R recommends bridging unused inputs on the terminals.
2) Based on the current measured value.
3) Based on the 20 V measurement range.

4.3.3.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
e+r Red on / Green single flash Invalid firmware
1-2 Green Off Open line or sensor is disconnected
Blinking Input signal overflow or underflow
On Analog/digital converter running, value OK

Table 30: LED status indicators

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4.3.3.5 Pinout

r e

X20 AI 2222
1 2

AI + 1 U AI + 2 U

AI - 1 U AI - 2 U

Figure 54: Pinout

4.3.3.6 Connection example

AI

+ +

+24 VDC +24 VDC

GND GND

4.3.3.7 Input circuit diagram

AI + x U

A/D Input value

Converter
I/O status
AI - x U

LED (green)

Figure 55: Input circuit diagram

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4.3.3.8 Register description

4.3.3.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
16 Configuring the input filter USINT ●
20 Lower limit value INT ●
22 Upper limit value INT ●
Analog signal - Communication
0 AnalogInput01 INT ●
2 AnalogInput02 INT ●
30 Input status USINT ●

4.3.3.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
16 - Configuring the input filter USINT ●
20 - Lower limit value INT ●
22 - Upper limit value INT ●
Analog signal - Communication
0 0 AnalogInput01 INT ●
2 2 AnalogInput02 INT ●
●
30 - Input status USINT

1) The offset specifies the position of the register within the CAN object.

4.3.3.8.3 Analog inputs

The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.

4.3.3.8.4 Analog input values

Name:
AnalogInput01 to AnalogInput02
The analog input values are mapped to this register.
Data type Value Input signal:
INT -32,768 to 32,767 Voltage signal -10 to 10 VDC

4.3.3.8.5 Input filter

This module is equipped with a configurable input filter. The minimum cycle time must be >500 μs. Filtering is
disabled for shorter cycle times.
If the input filter is active, then the scan rate for the channels is measured in ms. The time offset between the
channels is 200 μs. The conversion takes place asynchronously to the network cycle.

4.3.3.8.5.1 Input ramp limitation

Input ramp limitation can only take place when a filter is used; the input ramp is limited before filtering takes place.
The amount the input value changes is checked to make sure that specified limits are not exceeded. If the values
are exceeded, the adjusted input value is equal to the old value ± the limit value.
Configurable limit values:
Value Limit value
0 The input value is used without limitation.
1 0x3FFF = 16383
2 0x1FFF = 8191
3 0x0FFF = 4095
4 0x07FF = 2047
5 0x03FF = 1023
6 0x01FF = 511
7 0x00FF = 255

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Input ramp limitation is well suited for suppressing disturbances (spikes). The following examples show the function
of the input ramp limitation based on an input jump and a disturbance.
Example 1
The input value jumps from 8,000 to 17,000. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

17000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 56: Adjusted input value for input jump

Example 2
A disturbance interferes with the input value. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 57: Adjusted input value for disturbance

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4.3.3.8.5.2 Filter level

A filter can be defined to prevent large input jumps. This filter is used to bring the input value closer to the actual
analog value over a period of several bus cycles.
Filtering takes place after input ramp limitation.
Formula for calculating the input value:
Value Old Input value
Value New = Value Old - +
Filter level Filter level
Adjustable filter levels:
Value Filter level
0 Filter switched off
1 Filter level 2
2 Filter level 4
3 Filter level 8
4 Filter level 16
5 Filter level 32
6 Filter level 64
7 Filter level 128

The following examples show how filtering works in the event of an input jump or disturbance.
Example 1
The input value jumps from 8,000 to 16,000. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 58: Calculated value during input jump

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Example 2
A disturbance interferes with the input value. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 59: Calculated value during disturbance

4.3.3.8.6 Configuring the input filter

Name:
ConfigOutput01
This register is used to define the filter level and input ramp limitation of the input filter.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-2 Defines the filter level 000 Filter switched off
001 Filter level 2
010 Filter level 4
011 Filter level 8
100 Filter level 16
101 Filter level 32
110 Filter level 64
111 Filter level 128
3 Reserved 0
4-6 Defines the input ramp limitation 000 The input value is used without limitation
001 Limit value = 0x3FFF (16383)
010 Limit value = 0x1FFF (8191)
011 Limit value = 0x0FFF (4095)
100 Limit value = 0x07FF (2047)
101 Limit value = 0x03FF (1023)
110 Limit value = 0x01FF (511)
111 Limit value = 0x00FF (255)
7 Reserved 0

4.3.3.8.7 Lower limit value

Name:
ConfigOutput03
This register can be used to configure the lower limit for analog values. If the analog value goes below the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
The default value of -32768 corresponds to the minimum default value of -10 VDC.
Keep in mind that this setting applies to all channels!

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4.3.3.8.8 Upper limit value

Name:
ConfigOutput04
This register can be used to configure the upper limit for analog values. If the analog value goes above the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
The default value of 32767 corresponds to the maximum default value at +10 VDC.
Keep in mind that this setting applies to all channels!

4.3.3.8.9 Input status

Name:
StatusInput01
This register is used to monitor the module inputs. A change in the monitoring status generates an error message.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Channel 1 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded
11 Open line
2-3 Channel 2 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded
11 Open line
4-7 Reserved 0

Limiting the analog value

In addition to the status information, the analog value is set to the values listed below by default when an error
occurs. The analog value is limited to the new values if the limit values were changed.
Error status Digital value for error (default values)
Open line +32767 (0x7FFF)
Upper limit value exceeded +32767 (0x7FFF)
Lower limit value exceeded -32767 (0x8001)
Invalid value -32768 (0x8000)

4.3.3.8.10 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Inputs without filtering 100 µs
Inputs with filtering 500 µs

4.3.3.8.11 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Inputs without filtering 300 µs for all inputs
Inputs with filtering 1 ms

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4.3.4 X20AI2237

4.3.4.1 General information

The X20AI2237 module is equipped with two voltage inputs with 16-bit digital converter resolution.
Each voltage input has its own sensor supply. The two channels with their respective sensor supplies are electrically
isolated from each other.
• 2 analog voltage inputs
• Electrically isolated analog channels
• Electrically isolated sensor supplies
• 16-bit digital converter resolution
• Very high sampling rate

4.3.4.2 Order data

Model number Short description Figure

Analog input modules
X20AI2237 X20 analog input module, 2 inputs, ±10 V, 16-bit resolution, each
channel electrically isolated and with own sensor supply
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 31: X20AI2237 - Order data

4.3.4.3 Technical data

Product ID X20AI2237
Short description
I/O module 2 analog inputs ±10 V
General information
B&R ID code 0xC9C4
Status indicators I/O function per channel, operating state, module status, sensor supply per channel
Diagnostics
Module run/error Yes, using status LED and software status
Inputs Yes, using status LED and software status
Sensor supply Yes, using status LED and software status
Power consumption
Bus 0.05 W
I/O internal 2.65 W
I/O external 1.5 W 1)
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel Yes
Certification
CE Yes
c-UL-us In preparation
GOST-R Yes
Analog inputs
Input ±10 V
Input type Differential input
Digital converter resolution ±15-bit
Data output rate 10,000 samples per second
Output format
Data type INT
Voltage INT 0x8001 - 0x7FFF / 1 LSB = 0x0001 = 305.176 µV
Input impedance in signal range 20 MΩ

Table 32: X20AI2237 - Technical data

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Product ID X20AI2237
Input protection Up to 30 VDC, reverse polarity protection
Open line detection Yes, via software
Permitted input signal Max. ±30 V
Output of the digital value during overload Configurable
Conversion procedure SAR
Input filter 4th-order low pass / cut-off frequency 10 kHz
Max. error at 25°C
Gain 0.0130% 2)
Offset 0.0035% 3)
Max. gain drift <0.0008 %/°C 2)
Max. offset drift <0.0025 %/°C 3)
Common-mode rejection
DC 84 dB
Up to 60 Hz 84 dB
Up to 10 kHz 82 dB
Common-mode range ±14 V
Non-linearity <0.003% 3)
Test voltage between
Channel and channel 1000 VAC
Channel and bus 1000 VAC
Channel and ground 1000 VAC
Bus and ground 800 VAC
Sensor supply
Nominal voltage 25 V ±2 %
Nominal output current 30 mA
Short circuit protection Yes, continuous
Electrical isolation
Sensor supply - Channel No
Sensor supply - Sensor supply Yes
Maximum voltage ripple
Up to 100 kHz 2.2 mV
Up to 1 MHz 22 mV
higher 100 mV
Short circuit current
Typical 50 mA
Maximum 60 mA
Behavior in the event of a short circuit Current limitation
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
> 2000 m Reduction of ambient temperature by 0,5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 32: X20AI2237 - Technical data

1) Sensor supply
2) Based on the current measurement value
3) Based on the 20 V measurement range.

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4.3.4.4 Status LEDs

Image LED Color Status Description

Operating status
r Green Off Module supply not connected
Single flash Unlink mode
Blinking quickly Sync mode
Blinking slowly PREOPERATIONAL mode
On RUN mode
Module status
e Red Off Module supply not connected or everything is OK
On Error or reset status
Sensor supply
V Yellow Off Module supply not connected or overload
On Sensor supply in its normal operating range
Analog input
1-2 Green Off Indicates one of the following cases:
• Module supply not connected
• Channel disabled
• Open line
Single flash Input signal overflow or underflow
On Analog/digital converter running, value OK

Table 33: X20AI2237 - Status LEDs

4.3.4.5 Pinout

Shielded twisted pair cables should be used to minimize coupling disturbances. Use either one cable for each
channel or a multiple twisted pair cable for both channels.

r e
X20 AI 2237

V V
1 2

Sensor supply 1+ Channel 1 +

Sensor supply 1 − Channel 1 −

Sensor supply 2 + Channel 2 +

Sensor supply 2 − Channel 2 −

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4.3.4.6 Connection examples

4.3.4.6.1 2-wire connection

A 2-wire connection can be implemented as follows:

• 2-wire transducer
• Active voltage source

AI

2-wire
Transducer
(passive)

Voltage source
+24 VDC +24 VDC
GND GND

4.3.4.6.2 4-wire connection

A 4-wire connection can be implemented as follows:

• 4-wire transducer with external supply
• 4-wire transducer supplied by the module

With external
AI power supply

4-wire
transducer
(active)

4-wire
transducer
(active)

With internal
power supply 1)

+24 VDC +24 VDC

GND GND

1)
The internal power supply can handle a load of max. 30 mA.

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4.3.4.7 Input circuit diagram

Electrical
Isolation
Sensor supply x + I/O
DC/DC
Supply
DC/DC 28 V
Input 18 - 30 V
Converter
protection GND x GND I/O
25 V DC/DC
5V
Sensor supply x - DC/DC
3.3 V
GND x

Channel x +

Input Input A/D

Processor
protection filter Converter

Channel x -

4.3.4.8 Behavior in the event of a short circuit

In the event of a short circuit, the output current for the sensor supply is limited according to the following diagram.
25

20
Voltage [V]

15

10

0
0 10 20 30 40 50

Current [mA]

Figure 60: Typical behavior of the sensor supply output current in the event of a short circuit

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4.3.4.9 Register description

4.3.4.9.1 Register overview - Standard

Registers Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Analog input - Configuration
390 AnalogFilter01
UINT ●
434 AnalogFilter02
386 AnalogMode01
UINT ●
430 AnalogMode02
402 UpperLimit01
INT ●
446 UpperLimit02
398 LowerLimit01
INT ●
442 LowerLimit02
406 Hysteres01
INT ●
450 Hysteres02
414 ReplacementUpper01
INT ●
458 ReplacementUpper02
410 ReplacementLower01
INT ●
454 ReplacementLower02
426 PreparationInterval01
UINT ●
470 PreparationInterval02
418 ErrorDelay01
UINT ●
462 ErrorDelay02
422 SumErrorDelay01
UINT ●
466 SumErrorDelay02
Analog input - Communication
258 AnalogInput01 (Measurand)
INT ●
262 AnalogInput02 (Measurand)
0 AnalogInput01 (Evaluated)
INT ●
2 AnalogInput02 (Evaluated)
284 Sampletime01 (32-bit)
DINT ●
292 Sampletime02 (32-bit)
282 Sampletime01 (16-bit)
INT ●
290 Sampletime02 (16-bit)
273 AnalogStatus01 ●
USINT
275 AnalogStatus02
UnderflowAnalogInput Bit 0
OverflowAnalogInput Bit 1
OpenLineAnalogInput Bit 2
SumErrorAnalogInput Bit 4
SensorErrorAnalogInput Bit 6
IoSuppErrorAnalogInput Bit 7

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4.3.4.9.2 Register overview - Bus controller

Registers Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Analog input - Configuration
390 AnalogFilter01
UINT ●
434 AnalogFilter02
386 AnalogMode01
UINT ●
430 AnalogMode02
402 UpperLimit01
INT ●
446 UpperLimit02
398 LowerLimit01
INT ●
442 LowerLimit02
406 Hysteres01
INT ●
450 Hysteres02
414 ReplacementUpper01
INT ●
458 ReplacementUpper02
410 ReplacementLower01
INT ●
454 ReplacementLower02
426 PreparationInterval01
UINT ●
470 PreparationInterval02
418 ErrorDelay01
UINT ●
462 ErrorDelay02
422 SumErrorDelay01
UINT ●
466 SumErrorDelay02
Analog input - Communication
258 AnalogInput01 (Measurand)
INT ●
262 AnalogInput02 (Measurand)
0 AnalogInput01 (Evaluated)
INT ●
2 AnalogInput02 (Evaluated)
284 Sampletime01 (32-bit)
DINT ●
292 Sampletime02 (32-bit)
282 Sampletime01 (16-bit)
INT ●
290 Sampletime02 (16-bit)
273 AnalogStatus01 ●
USINT
275 AnalogStatus02

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4.3.4.9.3 General information

The X20AI2237 provides two electrically isolated channels. Each channel can read an electrical voltage signal in
the ±10 V range, and the supply the signal encoder with 24 VDC.

4.3.4.9.4 Analog input - Configuration

Each channel is configured and enabled separately First, the user must set the scaling of the input value and select
a replacement value strategy. Depending on the requirements of the application, the user can also set user-defined
limit values to limit the slew rate of the input value.
Scaling
The module's ADC works at a resolution of 16 bits (±15 bits). This allows the input value of ±10 V to be mapped
using ±32767 steps. To simplify implementation, the user can configure scaling to ±10000 steps. The conversion
value corresponds to the voltage in mV, and with a resolution of more than 14 bits (±13 bits) is still precise enough
for the many different application that use this technology.
Replacement value strategy
The detected voltage is evaluated in order to ensure the quality of the read value. For example, if a logically
impermissible voltage value or an open line is detected, the limit monitor triggers an appropriate response.
The response is determined by the replacement value strategy selected by the user. With the option "Replace with
static value", the user defines two values that replace the converted value when the upper and lower limits are
exceeded. The alternative "Retain last valid value" keeps the last validated value. However, the evaluation for this
option takes more time. Depending on the defined preparation interval, the currently read value may be delayed.
User limit check
In addition to the qualitative evaluation of the input, the module also provides the option of adapting the range
of permitted values to the requirements of the application. The "UpperLimit" and "LowerLimit" registers can be
used to place additional restrictions on the permitted upper and lower limit. When this feature is used, the selected
replacement value strategy is implemented according to the new limits.
Slew rate of the input value
Analog input signals can experience brief disturbances caused by external factors (EMC). The ADC's high sampling
rate allows you to filter out these types of signal peaks without hindering the application processes.
Two configuration points are available for interpolating the input signal:
• "Level of input filter" and
• "Input limitation"

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The "Level of input filter" limits the permissible changes to the input value. The calculation is recursive, which
means the current value depends on the previously filtered input value. The curve of the filtered input value is
similar to a first order low pass filter.

Formula: Raw value New - Value Old

∆ Value = Value New - Value Old =
Filter level

Raw value New - Value Old

Value New = Value Old +
Filter level

Example 1: The diagram shows how the evaluated input value behaves during normal operation.
Configured filter level: 2 or 4
Jump in incoming raw value: From 8000 to 16000

16000

8000

Raw value jump

Evaluated value: Filter level 2
Evaluated value: Filter level 4

0
0 1 2 3 4 5 6 7 8 t

Figure 61: Step response of input value with respect to configured filter level

Example 2: The diagram shows how the evaluated input value behaves when a disturbance occurs.
Configured filter level: 2 or 4
Spike in incoming raw value: From 8000 to 16000

16000
Disturbance (spike)

8000

Raw value
Evaluated value: Filter level 2
Evaluated value: Filter level 4

0
0 1 2 3 4 5 6 7 8 t

Figure 62: Pulse response of input value with respect to configured filter level

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The higher the filter level is set, the lower the absolute amplitude of the evaluated input value. Due to the recursive
calculation, however, the spike has a considerable after-effect. It is therefore recommended to define an additional
input limit when using high filter levels. This provides an absolute limit to variation in the evaluated input value
in advance.
Example 1: The diagram shows how the evaluated input value behaves during normal operation.
Input limitation: 2047
Configured filter level: 2
Jump in incoming raw value: From 8000 to 17000

17000

8000

Input Filter level

Limitation Raw value jump
Evaluated value

0
0 1 2 3 4 5 6 7 8 t

Figure 63: Step response of input value with configured filter level and input ramp limit

Example 2: The diagram shows how the evaluated input value behaves when a disturbance occurs.
Input limitation: 2047
Configured filter level: 2 or 4
Spike in incoming raw value: From 8000 to 16000

16000
Disturbance (spike)

8000

Raw value
Evaluated value

0
0 1 2 3 4 5 6 7 8 t

Figure 64: Pulse response of input value with configured filter level and input ramp limit

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4.3.4.9.4.1 AnalogFilter

Name:
AnalogFilter01
AnalogFilter02
If required by the application, the "AnalogFilter" register can be used to limit the slew rate of the input value.
Data type Values
UINT See bit structure

Bit structure:
Bit Name Value Note
0-2 Level of input filter 000 Off (input limitation not processed)
001 2
010 4
011 8
100 16
101 32
110 64
111 128
3 Reserved 0
4-6 Input limitation 000 No additional limitation
001 16383
010 8191
011 4095
100 2047
101 1023
110 511
111 255
7 Reserved 0

4.3.4.9.4.2 AnalogMode

Name:
AnalogMode01
AnalogMode02
These registers are used to predefine the operating parameters that the module will be using for the respective
channel. Each channel must be enabled individually and can be configured and operated independently.
It is extremely important to not that different limit values need to be configured for any display normalizing that
needs to take place.
Data type Values
UINT See bit structure

Bit structure:
Bit Name Value Note
0 Channel (on/off) 0 Disabled
1 Enabled
1 Limit exceeded 0 Disabled
1 Enabled
2 Lower limit violation 0 Disabled
1 Enabled
3 Reserved 0
4 Replacement value strategy 0 Replace with static value
1 Retain last valid value
5 Measurement value scaling 0 ±32767 (resolution: 16-bit)
1 ±10000 (resolution: >14-bit)
6-15 Reserved 0

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4.3.4.9.4.3 UpperLimit, LowerLimit

Name:
UpperLimit01
UpperLimit02
LowerLimit01
LowerLimit02
If the value range needs to be restricted further, the "UpperLimit" and "LowerLimit registers can be used to enter
new user-specific limit values.
Data type Values
INT -32767…32767
-10000…10000

Information:
The defined limit values must take the scaling into consideration.

4.3.4.9.4.4 Hysteresis

Name:
Hysteres01
Hysteres02
If the user-specific limit values are being used, then a hysteresis range should also be defined. The "Hysteresis"
registers configure how far a limit value can be exceeded before a response is triggered.
The error status is cleared when the scaled input value once again passes the limit by at least the hysteresis value
in the permitted direction.
Data type Values
INT -32767…32767
-10000…10000

Information:
The hysteresis value must take the scaling into consideration.

4.3.4.9.4.5 ReplacementUpper, ReplacementLower

Name:
ReplacementUpper01
ReplacementUpper02
ReplacementLower01
ReplacementLower02
The "Replace" register is used to define the static values to be displayed instead of the current measurement value
when the limit is violated.
Data type Values
INT -32767…32767

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4.3.4.9.4.6 PreparationInterval

Name:
PreparationInterval01
PreparationInterval02
If the last valid measurement value should be kept when violating the limit value, then PreparationInterval must be
defined. The measurement values continue to be acquired and converted according to the configured I/O update
time. They are then checked and discarded if they do not meet the specifications. When an error does not occur,
therefore, the measurement value acquired two preparation intervals ago is constantly output.
Data type Values [0.1 ms]
UINT 0…65535

"Application"
How it works: for the value being measured (analog)
Measured values are converted at the configured conversion rate and saved to measurement value memory. Condition:
The current contents of the measurement value memory are checked within the configured interval. If a permis- ↓
- Conversion interval (ADC) elapsed
sible value is present, then the contents of the buffer memory are passed to output memory and the contents of "Measurement value memory"
the measurement value memory are passed to the buffer. Measurement value (digital)
If the check turns up an impermissible value, then the contents of the measurement value memory are discard-
Condition:
ed. The copy direction between the output and buffer memory reverses and the last valid value continues to be
↓ - PreparationInterval elapsed
output.
- Measurement value permissible
"Buffer"
Information: Last valid value
Condition:
If configured to keep the last valid value, the delay time from measuring to outputting the value ↓ - PreparationInterval elapsed
will be at least twice the preparation interval. In the worst case scenario, this can also take twice - Measurement value permissible
the interval time plus the configured ADC conversion rate. "Output memory"
Next-to-last valid/
displayed value

4.3.4.9.4.7 ErrorDelay

Name:
ErrorDelay01
ErrorDelay02
This register specifies the number of consecutive conversion procedures where an error is pending until the cor-
responding individual error status bit is set. The delay applies to underflow, overflow and open circuit errors. This
delay can be used to hide temporary measurement value deviations, for example.
Data type Values
UINT 0…65535

4.3.4.9.4.8 SumErrorDelay

Name:
SumErrorDelay01
SumErrorDelay02
A "SumErrorDelay" register can be used to set the time that an error must remain pending before the composite
error bit is set.
Data type Values
UINT 0…65535

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4.3.4.9.5 Analog input - Communication

The measured voltage data can be obtained via two different registers: The unevaluated measurement value
("measurand") contains the scaled converter value. The evaluated measurement value ("Evaluated“) also takes
the limit values and the configured replacement value strategy into consideration.

4.3.4.9.5.1 AnalogInput (Measurand, Evaluated)

Name:
AnalogInput01
AnalogInput02
The "Measurand" registers represent the actual input values after standardization. The settings for limit value
monitoring and replacement value strategy only affect the "Evaluated" registers.
Data type Values
INT -32767…32767
-10000…10000

4.3.4.9.5.2 Sampletime (32-bit, 16-bit)

Name:
Sampletime01
Sampletime02
The registers return the timestamp for when the module reads the current channel mapping. The values are pro-
vided as signed 2-byte or 4-byte values.
Data type Values [µs]
INT -32768...32767: Nettime timestamp of the current input value
DINT -2,147,483,648...2,147,483,647: Nettime timestamp of the current input value

4.3.4.9.5.3 AnalogStatus

Name:
AnalogStatus01
AnalogStatus02
The current error status of the module channels is displayed in this register, regardless of the configured replace-
ment value strategy. Some error information may be delayed according to the previously configured condition.
Data type Values
USINT See bit structure

Bit structure:
Bit Name Value Note
0 UnderflowAnalogInput 0 Value equals lower limit
1 Lower limit value exceeded
1 OverflowAnalogInput 0 Value equals upper limit
1 Upper limit value exceeded
2 OpenLineAnalogInput 0 No open line detected
1 Open line detected
3 Reserved 0
4 SumErrorAnalogInput 0 No error detected
1 Composite error detected
5 Reserved 0
6 SensorErrorAnalogInput 0 Sensor voltage OK
1 Sensor load too high
7 IoSuppErrorAnalogInput 0 Module voltage OK
1 Energy supply not permitted

UnderflowAnalogInput:
The signal underflow error status is indicated here according to the configuration. This error information is activated
as a multiple of the conversion cycles only after the configurable delay time has passed ("ErrorDelay" registers).
OverflowAnalogInput:
The signal overflow error status is indicated here according to the configuration. This error information is activated
as a multiple of the conversion cycles only after the configurable delay time has passed ("ErrorDelay" registers).
SumErrorAnalogInput:
This error information derives from the status of individual errors and is only activated after the configurable delay
time has passed ([ms], "SumErrorDelay" registers). Linking this error information to an application makes it possible
to hide temporary temperature value overflows and underflows, for example.

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SensorErrorAnalogInput:
In addition to the analog input, the module also provides the option of supplying the connected encoder with 24 VDC.
If the input impedance for the sensor is too high, however, the integrated supply voltage will fail.
IoSuppErrorAnalogInput:
This error is activated immediately as soon as the module detects that the necessary supply voltage is no longer
being provided (<20 VDC).

4.3.4.9.6 Function models

A function model specifies the registers on the module (storage model) that are available for the application. Only
these registers are processed on the module during each cycle and transferred cyclically via the bus. In this way,
it is possible to minimize the cycle time by selecting the correct function model.
Function model Number Automation Studio CANopen DeviceNet Modbus/TCP CAN I/O
Default 0 ●
Bus controllers 254 ● ● ● ●

Table 34: Overview of possible function models

4.3.4.9.7 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without causing a communication error
or impaired functionality. It should be noted that very fast cycles decrease the idle time available for handling
monitoring, diagnostics and acyclic commands.
Minimum cycle time
200 µs

4.3.4.9.8 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
1 ms

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4.3.5 X20AI2322

4.3.5.1 General information

The module is equipped with 2 inputs with 12-bit digital converter resolution. It is possible to select between the
two current ranges 0 to 20 mA and 4 to 20 mA.
This module is designed for X20 6-pin terminal blocks. If needed (e.g. for logistical reasons), the 12-pin terminal
block can also be used.
• 2 analog inputs, 0 to 20 mA or 4 to 20 mA
• 12-bit digital converter resolution

4.3.5.2 Order data

Model number Short description Figure

Analog input modules
X20AI2322 X20 analog input module, 2 inputs, 0-20 mA / 4-20 mA, 12-bit
converter resolution, configurable input filter
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 35: X20AI2322 - Order data

4.3.5.3 Technical data

Product ID X20AI2322
Short description
I/O module 2 analog inputs 0 to 20 mA / 4 to 20 mA
General information
B&R ID code 0xCAB2
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Inputs Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 0.8 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
GL Yes
GOST-R Yes
Analog inputs
Input 0 to 20 mA/4 to 20 mA
Input type Differential input
Digital converter resolution 12-bit
Conversion time 300 µs for all inputs
Output format
Data type INT
Current 0x0000 - 0x7FFF / 1 LSB = 0x0008 = 4.883 µA
Load <400 Ω
Input protection Protection against wiring with supply voltage
Permitted input signal Max. ±50 mA

Table 36: X20AI2322 - Technical data

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Product ID X20AI2322
Output of the digital value during overload
Below lower limit 0x0000
Above upper limit 0x7FFF
Conversion procedure SAR
Input filter 3rd-order low pass / cutoff frequency 1 kHz
Max. error at 25°C
Gain
0 to 20 mA 0.08% 1)
4 to 20 mA 0.1% 1)
Offset
0 to 20 mA 0.03% 2)
4 to 20 mA 0.16% 2)
Max. gain drift
0 to 20 mA 0.009 %/°C 1)
4 to 20 mA 0.0113 %/°C 1)
Max. offset drift
0 to 20 mA 0.004 %/°C 2)
4 to 20 mA 0.005 %/°C 2)
Common-mode rejection
DC 70 dB
50 Hz 70 dB
Common-mode range ±12 V
Crosstalk between channels -70 dB
Non-linearity <0.05% 2)
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 36: X20AI2322 - Technical data

1) Based on the current measured value.
2) Based on the 20 mA measurement range.

4.3.5.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
e+r Red on / Green single flash Invalid firmware
1-2 Green Blinking Input signal overflow or underflow
On Analog/digital converter running, value OK

Table 37: LED status indicators

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4.3.5.5 Pinout

r e

X20 AI 2322
1 2

AI +1 I AI +2 I

AI -1 I AI -2 I

Figure 65: Pinout

4.3.5.6 Connection example

AI

+ +

+24 VDC +24 VDC

GND GND

4.3.5.7 Input circuit diagram

PTC
AI + x I

A/D Input value

Shunt
Converter
I/O status
AI - x I

LED (green)

Figure 66: Input circuit diagram

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4.3.5.8 Register description

4.3.5.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
16 Configuring the input filter USINT ●
18 Channel type USINT ●
20 Lower limit value INT ●
22 Upper limit value INT ●
Analog signal - Communication
0 AnalogInput01 INT ●
2 AnalogInput02 INT ●
30 Input status USINT ●

4.3.5.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
16 - Configuring the input filter USINT ●
18 - Channel type USINT ●
20 - Lower limit value INT ●
22 - Upper limit value INT ●
Analog signal - Communication
0 0 AnalogInput01 INT ●
2 2 AnalogInput02 INT ●
30 - Input status USINT ●

1) The offset specifies the position of the register within the CAN object.

4.3.5.8.3 Analog inputs

The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.

4.3.5.8.4 Analog input values

Name:
AnalogInput01 to AnalogInput02
The analog input values are mapped to this register.
Data type Value Input signal:
INT 0 to 32767 Current signal 0 to 20 mA or 4 to 20 mA

4.3.5.8.5 Input filter

This module is equipped with a configurable input filter. The minimum cycle time must be >500 μs. Filtering is
disabled for shorter cycle times.
If the input filter is active, then the scan rate for the channels is measured in ms. The time offset between the
channels is 200 μs. The conversion takes place asynchronously to the network cycle.

4.3.5.8.5.1 Input ramp limitation

Input ramp limitation can only take place when a filter is used; the input ramp is limited before filtering takes place.
The amount the input value changes is checked to make sure that specified limits are not exceeded. If the values
are exceeded, the adjusted input value is equal to the old value ± the limit value.
Configurable limit values:
Value Limit value
0 The input value is used without limitation.
1 0x3FFF = 16383
2 0x1FFF = 8191
3 0x0FFF = 4095
4 0x07FF = 2047
5 0x03FF = 1023
6 0x01FF = 511
7 0x00FF = 255

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Input ramp limitation is well suited for suppressing disturbances (spikes). The following examples show the function
of the input ramp limitation based on an input jump and a disturbance.
Example 1
The input value jumps from 8,000 to 17,000. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

17000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 67: Adjusted input value for input jump

Example 2
A disturbance interferes with the input value. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 68: Adjusted input value for disturbance

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4.3.5.8.5.2 Filter level

A filter can be defined to prevent large input jumps. This filter is used to bring the input value closer to the actual
analog value over a period of several bus cycles.
Filtering takes place after input ramp limitation.
Formula for calculating the input value:
Value Old Input value
Value New = Value Old - +
Filter level Filter level
Adjustable filter levels:
Value Filter level
0 Filter switched off
1 Filter level 2
2 Filter level 4
3 Filter level 8
4 Filter level 16
5 Filter level 32
6 Filter level 64
7 Filter level 128

The following examples show how filtering works in the event of an input jump or disturbance.
Example 1
The input value jumps from 8,000 to 16,000. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 69: Calculated value during input jump

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Example 2
A disturbance interferes with the input value. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 70: Calculated value during disturbance

4.3.5.8.6 Configuring the input filter

Name:
ConfigOutput01
This register is used to define the filter level and input ramp limitation of the input filter.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-2 Defines the filter level 000 Filter switched off
001 Filter level 2
010 Filter level 4
011 Filter level 8
100 Filter level 16
101 Filter level 32
110 Filter level 64
111 Filter level 128
3 Reserved 0
4-6 Defines the input ramp limitation 000 The input value is used without limitation
001 Limit value = 0x3FFF (16383)
010 Limit value = 0x1FFF (8191)
011 Limit value = 0x0FFF (4095)
100 Limit value = 0x07FF (2047)
101 Limit value = 0x03FF (1023)
110 Limit value = 0x01FF (511)
111 Limit value = 0x00FF (255)
7 Reserved 0

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4.3.5.8.7 Channel type

Name:
ConfigOutput02
This register can be used to set the range of the current signal. This is determined by how they are configured.
The following input signals can be set:
• 0 to 20 mA current signal
• 4 to 20 mA current signal
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Reserved 1
2-3 Reserved 0
4 Channel 1: Current measurement range 0 0 to 20 mA current signal
1 4 to 20 mA current signal
5 Channel 2: Current measurement range 0 0 to 20 mA current signal
1 4 to 20 mA current signal
6-7 Reserved 0

4.3.5.8.8 Lower limit value

Name:
ConfigOutput03
This register can be used to configure the lower limit for analog values. If the analog value goes below the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
• When configured as 0 to 20 mA, this value should be set to 0.
• When configured as 4 to 20 mA, this value can be set to -8192 (corresponds to 0 mA) in order
to display values <4 mA.
Keep in mind that this setting applies to all channels!

4.3.5.8.9 Upper limit value

Name:
ConfigOutput04
This register can be used to configure the upper limit for analog values. If the analog value goes above the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
The default value of 32767 corresponds to the maximum default value at 20 mA.
Keep in mind that this setting applies to all channels!

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4.3.5.8.10 Input status

Name:
StatusInput01
This register is used to monitor the module inputs. A change in the monitoring status generates an error message.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Channel 1 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded
2-3 Channel 2 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded
4-7 Reserved 0

Limiting the analog value

In addition to the status information, the analog value is set to the values listed below by default when an error
occurs. The analog value is limited to the new values if the limit values were changed.
Error status Digital value for error (default values)
0 to 20 mA 4 to 20 mA
Upper limit value exceeded +32767 (0x7FFF)
Lower limit value exceeded 0 -8191 (0xE001)

4.3.5.8.11 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Inputs without filtering 100 µs
Inputs with filtering 500 µs

4.3.5.8.12 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Inputs without filtering 300 µs for all inputs
Inputs with filtering 1 ms

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4.3.6 X20AI2437

4.3.6.1 General information

The X20AI2437 module is equipped with two inputs that have 16-bit digital converter resolution.
Each current measurement input has its own sensor supply. The two channels with their respective sensor supplies
are electrically isolated from each other. The user can select between the two measurement ranges 4 to 20 mA
and 0 to 25 mA.
• 2 analog current measurement inputs
• Electrically isolated analog channels
• Electrically isolated sensor supplies
• 16-bit digital converter resolution

4.3.6.2 Order data

Model number Short description Figure

Analog input modules
X20AI2437 X20 analog input module, 2 inputs, 4 to 20 mA, 16-bit resolution,
each channel electrically isolated and with own sensor supply
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 38: X20AI2437 - Order data

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4.3.6.3 Technical data

Product ID X20AI2437
Short description
I/O module 2 analog inputs, 4 to 20 mA or 0 to 25 mA
General information
B&R ID code 0xB784
Status indicators I/O function per channel, operating state, module status, sensor supply per channel
Diagnostics
Module run/error Yes, using status LED and software status
Inputs Yes, using status LED and software status
Sensor supply Yes, using status LED and software status
Power consumption
Bus 0.05 W
I/O internal 1.15 W 1)
I/O external 1.5 W 2)
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel Yes
Certification
CE Yes
GOST-R Yes
UL/CSA Yes
Analog inputs
Input 4 to 20 mA or 0 to 25 mA (can be configured via software)
Input type Differential input
Digital converter resolution 15-bit
Data output rate 4.7 to 960 scans per second, can be set using software
Output format INT
Output format
4 to 20 mA INT $0000 - $7FFF / 1 LSB = $0001 = 488.281 nA
0 to 25 mA INT $0000 - $7FFF / 1 LSB = $0001 = 762.939 nA
0 to 25000 µA INT $0000 - $61A8 / 1 LSB = $0001 = 1000 nA
Load <300 Ω
Input protection Up to 30 VDC, reverse polarity protection (max. 0.1 A)
Open line detection Yes, via software
Permitted input signal 0 to 25 mA
Output of the digital value during overload Configurable
Conversion procedure Sigma Delta
Max. error at 25°C
Gain
0 to 25 mA <0.046% 3)
4 to 20 mA <0.046% 3)
Offset
0 to 25 mA <0.004% 4)
4 to 20 mA <0.013% 4)
Common-mode rejection
DC 80 dB
50 Hz Depends on the sampling rate: e.g. >130 dB for 50 scans per second
Common-mode range 0 to 7 V
Non-linearity <0.003% 4)
Input filter
Hardware 1st-order low pass / cut-off frequency 2.5 kHz
Software Sinc4 filter
Maximum gain drift
0 to 25 mA 0.003 %/°C 3)
4 to 20 mA 0.003 %/°C 3)
Maximum offset drift
0 to 25 mA 0.0002 %/°C 4)
4 to 20 mA 0.0007 %/°C 4)
Test voltage between
Channel and channel 1500 VAC
Channel and bus 1500 VAC
To ground 1500 VAC
Sensor supply
Nominal voltage 25 V ±2 %
Nominal output current Max. 30 mA
Short circuit protection Yes, continuous
Electrical isolation
Sensor supply - Channel No
Sensor supply - Sensor supply Yes

Table 39: X20AI2437 - Technical data

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Product ID X20AI2437
Maximum voltage ripple
Up to 100 kHz ≤2.2 mV
Up to 1 MHz ≤22 mV
higher ≤100 mV
Short circuit current
Typical <50 mA
Maximum 60 mA
Behavior in the event of a short circuit Current limitation
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
> 2000 m Reduction of ambient temperature by 0,5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 39: X20AI2437 - Technical data

1) To reduce power dissipation, B&R recommends leaving unused inputs open.
2) Sensor supply
3) Based on the current measurement value
4) Based on the 25 mA measurement range.

4.3.6.4 Status LEDs

Image LED Color Status Description

Operating state
r Green Off Module supply not connected
Single flash Unlink mode
Blinking quickly Sync mode
Blinking slowly PREOPERATIONAL mode
On RUN mode
Module status
e Red Off Module supply not connected or everything is OK
Single flash A conversion error has occurred. When an error occurs, the LED of the faulty
analog input channel begins to double flash and this status is output.
On Error or reset state
Sensor supply
V Yellow Off Overload
On Sensor supply in normal operating range
Analog input
1-2 Green Off Indicates one of the following conditions:
• Module supply not connected
• Channel disabled
• Open circuit
Single flash Overflow or underflow of the input signal
Double flash A conversion error has occurred. A single flash is output on the red "e" module
status LED.
On Analog/digital converter running, value OK

Table 40: X20AI2437 - Status LEDs

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4.3.6.5 Pin assignments

Shielded twisted pair cables are generally used to minimize disturbance. Use either one cable for each channel
or a multiple twisted pair cable for both channels.

r e

X20 AI 2437
V V
1 2

Sensor supply 1 + Channel 1 +

Sensor supply 1 − Channel 1 −

Sensor supply 2 + Channel 2 +

Sensor supply 2 − Channel 2 −

4.3.6.6 Connection examples

4.3.6.7 Input circuit diagram

Electrical
Isolation
Sensor supply x + I/O
DC/DC
Supply
DC/DC 28 V
Output 18 - 30 V
Converter
protection GND x GND I/O
25 V DC/DC
3.3 V
Sensor supply x -
GND x

Channel x +

Input
protection Protection
Shunt

A/D
and Processor
Converter
Channel x - Filter

GND x

4.3.6.8 Behavior in the event of a short circuit

In the event of a short circuit, the output current for the sensor supply is limited according to the following diagram.
25

20
Voltage [V]

15

10

0
0 10 20 30 40 50

Current [mA]

Figure 71: Typical behavior of the sensor supply output current in the event of a short circuit

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4.3.6.9 Register description

4.3.6.9.1 Register overview - Function model 0 (standard)

Heading Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Channel 1 (electrically isolated)
Analog signal - Communication
0 AnalogInputEvaluated01 INT ● ●
UINT
258 AnalogInput01 INT ● ●
UINT
282 AnalogSampletime01_16Bit INT ● ●
284 AnalogSampletime01_32Bit DINT
30 AnalogStatus01 USINT ● ●
Analog signal - Configuration
386 AnMode_1 UINT ●
390 Samplerate_1 UINT ●
394 OpenLoopLimit_1 INT ●
UINT
466 PreparationInterval_1 UINT ●
414 ReplacementUpper_1 INT ●
UINT
410 ReplacementLower_1 INT ●
UINT
402 UpperLimit_1 INT ●
UINT
398 LowerLimit_1 INT ●
UINT
406 Hysteres_1 INT ●
UINT
418 ErrorDelay_1 UINT ●
422 SumErrorDelay_1 UINT ●
Channel 2 (electrically isolated)
Analog signal - Communication
2 AnalogInputEvaluated02 INT ● ●
UINT
262 AnalogInput02 INT ● ●
UINT
290 AnalogSampletime02_16Bit INT ● ●
292 AnalogSampletime02_32Bit DINT
31 AnalogStatus02 USINT ● ●
Analog signal - Configuration
426 AnMode_2 UINT ●
430 Samplerate_2 UINT ●
434 OpenLoopLimit_2 INT ●
UINT
482 PreparationInterval_2 UINT ●
454 ReplacementUpper_2 INT ●
UINT
450 ReplacementLower_2 INT ●
UINT
442 UpperLimit_2 INT ●
UINT
438 LowerLimit_2 INT ●
UINT
446 Hysteres_2 INT ●
UINT
458 ErrorDelay_2 UINT ●
462 SumErrorDelay_2 UINT ●

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4.3.6.9.2 Variable assignment in Automation Studio (X2X master)

Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Channel 1 (electrically isolated)
Analog signal - Communication
AnalogStatus01 USINT ●
UnderflowAnalogInput01 BOOL ●
OverflowAnalogInput01 BOOL ●
OpenLineAnalogInput01 BOOL ●
ConversionErrorAnalogInput01 BOOL ●
SumErrorAnalogInput01 BOOL ●
SensorErrorAnalogInput01 BOOL ●
IoSuppErrorAnalogInput01 BOOL ●
AnalogInput01 INT ●
UINT
AnalogSampletime01 INT ●
UINT
Channel 2 (electrically isolated)
Analog signal - Communication
AnalogStatus02 USINT ●
UnderflowAnalogInput02 BOOL ●
OverflowAnalogInput02 BOOL ●
OpenLineAnalogInput02 BOOL ●
ConversionErrorAnalogInput02 BOOL ●
SumErrorAnalogInput02 BOOL ●
SensorErrorAnalogInput02 BOOL ●
IoSuppErrorAnalogInput02 BOOL ●
AnalogInput02 INT ●
UINT
AnalogSampletime02 INT ●
UINT

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4.3.6.9.3 Register overview - Bus controller function model 254

Heading Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Channel 1 (electrically isolated)
Analog signal - Communication
0 AnalogInputEvaluated01 INT ●
UINT
30 AnalogStatus01 USINT ●
Analog signal - Configuration
386 AnMode_1 UINT ●
390 Samplerate_1 UINT ●
394 OpenLoopLimit_1 INT ●
UINT
466 PreparationInterval_1 UINT ●
414 ReplacementUpper_1 INT ●
UINT
410 ReplacementLower_1 INT ●
UINT
402 UpperLimit_1 INT ●
UINT
398 LowerLimit_1 INT ●
UINT
406 Hysteres_1 INT ●
UINT
418 ErrorDelay_1 UINT ●
422 SumErrorDelay_1 UINT ●
Channel 2 (electrically isolated)
Analog signal - Communication
2 AnalogInputEvaluated02 INT ●
UINT
31 AnalogStatus02 USINT ●
Analog signal - Configuration
426 AnMode_2 UINT ●
430 Samplerate_2 UINT ●
434 OpenLoopLimit_2 INT ●
UINT
482 PreparationInterval_2 UINT ●
454 ReplacementUpper_2 INT ●
UINT
450 ReplacementLower_2 INT ●
UINT
442 UpperLimit_2 INT ●
UINT
438 LowerLimit_2 INT ●
UINT
446 Hysteres_2 INT ●
UINT
458 ErrorDelay_2 UINT ●
462 SumErrorDelay_2 UINT ●

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4.3.6.9.4 Variable assignment in Automation Studio (CANIO)

Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Channel 1 (electrically isolated)
Analog signal - Communication
AnalogStatus01 USINT ●
UnderflowAnalogInput01 BOOL ●
OverflowAnalogInput01 BOOL ●
OpenLineAnalogInput01 BOOL ●
ConversionErrorAnalogInput01 BOOL ●
SumErrorAnalogInput01 BOOL ●
SensorErrorAnalogInput01 BOOL ●
IoSuppErrorAnalogInput01 BOOL ●
AnalogInput01 INT ●
UINT
Channel 2 (electrically isolated)
Analog signal - Communication
AnalogStatus02 USINT ●
UnderflowAnalogInput02 BOOL ●
OverflowAnalogInput02 BOOL ●
OpenLineAnalogInput02 BOOL ●
ConversionErrorAnalogInput02 BOOL ●
SumErrorAnalogInput02 BOOL ●
SensorErrorAnalogInput02 BOOL ●
IoSuppErrorAnalogInput02 BOOL ●
AnalogInput02 INT ●
UINT

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4.3.6.9.5 Analog signal - Communication

The X20AI2437 module has two independent electrically isolated channels. Both channels can be used to read in an
analog signal. Two registers need to be configured for one analog signal. The two channels operate independently,
so two registers must be configured per channel to be used.
The current input signals (0 to 25 mA) can be displayed in different formats.
Specific features:
• Electrical isolation by channel
• Internal supply with short circuit protection <30 mA per channel
• Configurable filter (default 50 Hz)
• Selective line monitoring can be enabled for: open line (<2 mA), underflow (<3.6 mA) or overflow (>21 mA)
of a configurable threshold
• Selectable error strategy: Replacement value for each threshold (default) or last valid value

4.3.6.9.5.1 AnalogInputEvaluated

Names (pChannelName):
AnalogInputEvaluated01
AnalogInputEvaluated02
These registers take the values from the "AnalogInput" registers and use them to generate the evaluated input
values. The configured auxiliary functions are applied to form these values.
Data type Values
INT 0…25000: Normalizing option 0 to 25 mA
0…32767: Normalizing option 0 to 25 mA
0…32767: Normalizing option 4 to 20 mA
UINT 0…65535: Normalizing option 0 to 25 mA

Predefining values and timing

The value 0 (null) is output to the "AnalogInput" registers until a signal short circuit or converter error causes the
value to be changed.
The timing for acquiring measurement values is determined by the converter hardware and the set sampling rate.
The two channels are converted independently of each other and are not synchronized with the X2X bus.
Conversion time
Channel 0x sampling rate

4.3.6.9.5.2 AnalogInput

Names (pChannelName):
AnalogInput01
AnalogInput02
The normalized input values are transferred to these registers. Depending on the scaling selected, the value range
and the data type can be adapted to the requirements of the application. Generated limit values or value changes
from the configured limit value strategy have no effect on these registers.
Data type Values
INT 0…25000: Normalizing option 0 to 25 mA
0…32767: Normalizing option 0 to 25 mA
0…32767: Normalizing option 4 to 20 mA
UINT 0…65535: Normalizing option 0 to 25 mA

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4.3.6.9.5.3 AnalogSampletime

Names (pChannelName):
AnalogSampletime01
AnalogSampletime01_16Bit
AnalogSampletime01_32Bit
AnalogSampletime02
AnalogSampletime02_16Bit
AnalogSampletime02_32Bit
The registers return the timestamp for when the module reads the current channel mapping. The values are pro-
vided as signed 2-byte or 4-byte values.
Data type Values [µs]
INT -32768...32767: Nettime timestamp of the current input value
DINT -2,147,483,648...2,147,483,647: Nettime timestamp of the current input value

4.3.6.9.5.4 AnalogStatus

Names (pChannelName):
AnalogStatus01
AnalogStatus02
The current error status of the module channels is displayed in this register, regardless of the configured replace-
ment value strategy. Some error information may be delayed according to the previously configured condition.
Data type Values
USINT See bit structure

Bit structure:
Bit Name Information
0 Underflow 0 No error
1 Underflow on Channel 0x
1 Overflow 0 No error
1 Overflow on Channel 0x
2 Open line 0 No error
1 Open line on Channel 0x
3 Conversion error 0 No error
1 Conversion error on Channel 0x
4 Composite error 0 No error
1 Composite error on Channel 0x
5 Reserved -
6 Sensor error 0 No error
1 Sensor error on Channel 0x
7 I/O supply error 0 No error
1 I/O supply error on Channel 0x

Data points from AnalogStatus:

Designation (pChannelName) Information
UnderflowAnalogInput01 0 No error
UnderflowAnalogInput02 1 Underflow on Channel 0x
OverflowAnalogInput01 0 No error
OverflowAnalogInput02 1 Overflow on Channel 0x
OpenLineAnalogInput01 0 No error
OpenLineAnalogInput02 1 Open line on Channel 0x
ConversionErrorAnalogInput01 0 No error
ConversionErrorAnalogInput02 1 Conversion error on Channel 0x
SumErrorAnalogInput01 0 No error
SumErrorAnalogInput02 1 Composite error on Channel 0x
SensorErrorAnalogInput01 0 No error
SensorErrorAnalogInput02 1 Sensor error on Channel 0x
IoSuppErrorAnalogInput01 0 No error
IoSuppErrorAnalogInput02 1 I/O supply error on Channel 0x

Underflow:
The signal underflow error status is indicated here according to the configuration. This error information is activated
as a multiple of the conversion cycles only after the configurable delay time has passed ("ErrorDelay" registers).
Overflow:
The signal overflow error status is indicated here according to the configuration. This error information is activated
as a multiple of the conversion cycles only after the configurable delay time has passed ("ErrorDelay" registers).

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Open line:
According to the configuration, measurement information is checked for values <2 mA ("OpenLoopLimit" register)
to detect a failure signal. Open line detection takes place using a configurable hysteresis value (default: 100 µA,
"Hysteresis" registers). It is possible to disable open line detection ("AnalogMode" registers) to suppress alarms
when hardware is not present. This error information is activated as a multiple of the conversion cycles only after
the configurable delay time has passed ("ErrorDelay" registers).
Conversion error:
This error status is triggered when the hardware exceeds the conversion time.
Composite error:
This error information derives from the status of individual errors and is only activated after the configurable delay
time has passed ([msec], "SumErrorDelay" registers). Linking this error information to an application makes it
possible to hide temporary temperature value overflows and underflows, for example.
Sensor error:
This error is activated immediately after a fault is detected in the internal sensor supply.
I/O supply error:
This error is activated immediately as soon as the module detects that the necessary supply voltage is no longer
being provided (<20 VDC).

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4.3.6.9.6 Analog signal - Configuration

How the analog signal is displayed can be adapted to the requirements of the application. Separate configuration
registers per channel are available to aid in this.

4.3.6.9.6.1 Analog mode

Designations (pChannelName):
AnMode_1
AnMode_2
These registers are used to predefine the operating parameters that the module will be using for the respective
channel. Each channel must be enabled individually and can be configured and operated independently.
It is extremely important to not that different limit values need to be configured for any display normalizing that
needs to take place.
Data type Values
UINT See bit structure

Bit structure:
Bit Description Note
0 Channel 0 Channel 0x turned off
1 Channel 0x enabled (bus controller default setting)
1 Open circuit detection 0 Open circuit monitoring turned off
1 Channel 0x monitoring enabled (bus controller default setting)
2 Underflow detection 0 Underflow detection turned off
1 Underflow detection enabled (bus controller default setting)
3 Replacement value strategy 0 Use replacement values when an error occurs (bus controller
default setting)
1 Keep the last valid converted value
4-5 Normalization 00 Displays 0...25 mA as 0...32767
01 Displays 0...25 mA as 0...25000 [µA] (bus controller default set-
ting)
10 Displays 4...20 mA as 0...32767
11 Displays 0...25 mA as 0...65535
6-15 Reserved -

4.3.6.9.6.2 Sample rate

Names (pChannelName):
Samplerate_1
Samplerate_2
A sample rate can be configured for both analog inputs independently of one another. The following formula for
this parameter is put together using the desired sampling frequency:
Sample rate for ADC = (4920000/1024)/sampling frequency
Data type Values
UINT 4 - 1023: Sample rate
960 ... 200 ms ... 5 Hz
480 ... 100 ms ... 10 Hz
320 ... 66.7 ms ... 15 Hz
192 ... 40 ms ... 25 Hz
160 ... 33.3 ms ... 30 Hz
96 ... 20 ms ... 50 Hz (bus controller default setting)
80 ... 16.7 ms ... 60 Hz
48 ... 10 ms ... 100 Hz
9 ... 2 ms ... 500 Hz
4 ... 1 ms ... 1000 Hz

Setting to 1000 Hz will result in jitter when acquiring measurement values. Jitter-free operation is possible up to
960 Hz (sample rate setting = 5).

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4.3.6.9.6.3 OpenLoopLimit

Names (pChannelName):
OpenLoopLimit_1
OpenLoopLimit_2
The limit value for the respective analog input must be set when open circuit monitoring is enabled and if required
by the configured normalization. If limit value monitoring is active, the corresponding error status is output after a
configured delay when falling below this value. Using a default value of 2000 µA, the following values and formulas
apply to this parameter:
• Displaying 0..25 mA as 0..25000 : 2000
• Displaying 0..25 mA as 0..32767 : 2621, limit value = ([µA]*32767)/25000
• Displaying 4..20 mA as 0..32767 : -4096, limit value = (([µA]*1.31068) - 5242.72)*1.5625
• Displaying 0..25 mA as 0..65535 : 5243, limit value = ([µA]*65535)/25000
Data type Values
INT -32767...32767: Open circuit limit value
UINT 0...65535: Open circuit limit value

4.3.6.9.6.4 PreparationInterval

Names (pChannelName):
PreparationInterval_1
PreparationInterval_2
If the last valid measurement value should be kept when violating the limit value, then PreparationInterval must be
defined. The measurement values continue to be acquired and converted according to the configured I/O update
time. They are then checked and discarded if they do not meet the specifications. When an error does not occur,
therefore, the measurement value acquired two preparation intervals ago is constantly output.
Data type Values [0.1 ms]
UINT 0…65535

"Application"
How it works: for the value being measured (analog)
Measured values are converted at the configured conversion rate and saved to measurement value memory. Condition:
The current contents of the measurement value memory are checked within the configured interval. If a permis- ↓
- Conversion interval (ADC) elapsed
sible value is present, then the contents of the buffer memory are passed to output memory and the contents of "Measurement value memory"
the measurement value memory are passed to the buffer. Measurement value (digital)
If the check turns up an impermissible value, then the contents of the measurement value memory are discard-
Condition:
ed. The copy direction between the output and buffer memory reverses and the last valid value continues to be
↓ - PreparationInterval elapsed
output.
- Measurement value permissible
"Buffer"
Information: Last valid value
Condition:
If configured to keep the last valid value, the delay time from measuring to outputting the value ↓ - PreparationInterval elapsed
will be at least twice the preparation interval. In the worst case scenario, this can also take twice - Measurement value permissible
the interval time plus the configured ADC conversion rate. "Output memory"
Next-to-last valid/
displayed value

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4.3.6.9.6.5 ReplacementUpper, ReplacementLower

Names (pChannelName):
ReplacementUpper_1
ReplacementUpper_2
ReplacementLower_1
ReplacementLower_2
The "Replace" registers are used to predefine the static values that will be displayed instead of the current mea-
surement value when a limit value is violated.
Data type Values
INT -32767...32767
UINT 0...65535

If the replacement strategy "Use replacement values when an error occurs" is activated, the replacement value must
be set for the respective analog input taking the configured normalization into account as well. When an overflow
or underflow error status occurs, the "AnalogInputEvaluated0x" channel is replaced with the corresponding value.
Using a default value of 21000 µA and 3600 µA, the following values and formulas apply to this parameter:
Overflow:
• Displaying 0..25 mA as 0..25000 : 21000
• Displaying 0..25 mA as 0..32767 : 27524, limit value = ([µA]*32767)/25000
• Displaying 4..20 mA as 0..32767 : 32767, limit value = (([µA]*1.31068) - 5242.72)*1.5625
• Displaying 0..25 mA as 0..65535 : 55049, limit value = ([µA]*65535)/25000
Underflow:
• Displaying 0..25 mA as 0..25000 : 3600
• Displaying 0..25 mA as 0..32767 : 4718, limit value = ([µA]*32767)/25000
• Displaying 4..20 mA as 0..32767 : -819, limit value = (([µA]*1.31068) - 5242.72)*1.5625
• Displaying 0..25 mA as 0..65535 : 9437, limit value = ([µA]*65535)/25000

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4.3.6.9.6.6 UpperLimit, LowerLimit

Names (pChannelName):
UpperLimit_1
UpperLimit_2
LowerLimit_1
LowerLimit_2
If the value range needs to be restricted further, the "UpperLimit" and "LowerLimit registers can be used to enter
new user-specific limit values.
Data type Values
INT -32767…32767
UINT 0...65535

The limit value must be set for the respective analog input depending on the configured normalization. After the
configured delay time has passed, the corresponding error status is given if the respective value is overrun or
underrun. When this error status occurs, the "AnalogInputEvaluated0x" channel is evaluated according to the
replacement value strategy. Using a default value of 21000 µA and 3600 µA, the following values and formulas
apply to this parameter:
UpperLimit
• Displaying 0..25 mA as 0..25000 : 21000
• Displaying 0..25 mA as 0..32767 : 27524, limit value = ([µA]*32767)/25000
• Displaying 4..20 mA as 0..32767 : 32767, limit value = (([µA]*1.31068) - 5242.72)*1.5625
• Displaying 0..25 mA as 0..65535 : 55049, limit value = ([µA]*65535)/25000
LowerLimit
• Displaying 0..25 mA as 0..25000 : 3600
• Displaying 0..25 mA as 0..32767 : 4718, limit value = ([µA]*32767)/25000
• Displaying 4..20 mA as 0..32767 : -819, limit value = (([µA]*1.31068) - 5242.72)*1.5625
• Displaying 0..25 mA as 0..65535 : 9437, limit value = ([µA]*65535)/25000

4.3.6.9.6.7 Hysteresis

Names (pChannelName):
Hysteres_1
Hysteres_2
If the user-specific limit values are being used, then a hysteresis range should also be defined. The "Hysteresis"
registers configure how far a limit value can be exceeded before a response is triggered.
Data type Values
INT -32767…32767
UINT 0...65535

Te hysteresis value must be set for the respective analog input dpending on the configured normalization. The
error status is cleared if the actual analog value changes by at least this hysteresis value from the limit value in the
allowed direction. Using a default value of 100 µA, the following values and formulas result for this parameter:
• Displaying 0..25 mA as 0..25000 : 100
• Displaying 0..25 mA as 0..32767 : 131, limit value = ([µA]*32767)/25000
• Displaying 4..20 mA as 0..32767 : 156, limit value = [µA]*1.5625
• Displaying 0..25 mA as 0..65535 : 262, limit value = ([µA]*65535)/25000

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4.3.6.9.6.8 ErrorDelay

Names (pChannelName):
ErrorDelay_1
ErrorDelay_2
This register specifies the number of consecutive conversion procedures where an error is pending until the cor-
responding individual error status bit is set. The delay applies to underflow, overflow and open circuit errors. This
delay can be used to hide temporary measurement value deviations, for example.
Data type Values
UINT 0...10: Error formation delay [conversion cycles]
2 conversion cycles [default]

4.3.6.9.6.9 SumErrorDelay

Names (pChannelName):
SumErrorDelay_1
SumErrorDelay_2
This register specifies the time in milliseconds that one of the individual error bits must be pending until the com-
posite error status bit is set.
Data type Values
UINT 0...65535: Composite error bit delay [msec]
4000 msec [default]

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4.3.6.9.7 Function models

Name Number Automation CANopen DeviceNet Modbus/TCP CANIO

Studio
Standard function model 0 ●
Bus controller function model 254 ● ● ● ●

A function model specifies the registers on the module (storage model) that are available for the application. Only
these registers are processed on the module during each cycle and transferred cyclically via the bus. In this way,
it is possible to minimize the cycle time by selecting the correct function model.

4.3.6.9.8 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without causing a communication error
or impaired functionality. It should be noted that very fast cycles decrease the idle time available for handling
monitoring, diagnostics and acyclic commands.
Minimum cycle time
200 μs

4.3.6.9.9 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Analog inputs 1 ms

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4.3.7 X20AI2438

4.3.7.1 General information

The X20AI2438 module is equipped with two inputs with 16-bit digital converter resolution. It supports the HART
communication standard for data transfer, parameter configuration and diagnostics.
Each current measurement input has its own sensor supply. The two channels with their respective sensor supplies
are electrically isolated from each other. The user can select between the two measurement ranges 4 to 20 mA
and 0 to 25 mA.
• 2 analog current measurement inputs
• HART protocol integration
• Support for HART variables
• Electrically isolated analog channels
• Electrically isolated sensor supplies
• 16-bit digital converter resolution

4.3.7.2 Order data

Model number Short description Figure

Analog input modules
X20AI2438 X20 analog input module, 2 inputs, 4 to 20 mA, 16-bit resolution,
each channel electrically isolated and with own sensor supply,
HART protocol supported
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 41: X20AI2438 - Order data

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4.3.7.3 Technical data

Product ID X20AI2438
Short description
I/O module 2 analog inputs, 4 to 20 mA or 0 to 25 mA
General information
B&R ID code 0xB3A9
Status indicators I/O function per channel, operating state, module status, sensor supply per channel, HART
Diagnostics
Module run/error Yes, using status LED and software status
Inputs Yes, using status LED and software status
Sensor supply Yes, using status LED and software status
HART link Yes, using status LED and software status
HART error Yes, using status LED and software status
Power consumption
Bus 0.05 W
Internal I/O 1.15 W 1)
External I/O 1.5 W 2)
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel Yes
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Analog inputs
Input 4 to 20 mA or 0 to 25 mA (can be configured via software)
Input type Differential input
Digital converter resolution 15-bit
Data output rate
With HART 4.7 to 10 scans per second, can be set using software
Analog 4.7 to 100 scans per second, can be set using software
Output format INT
Output format
4 to 20 mA INT 0x0000 - 0x7FFF / 1 LSB = 0x0001 = 488.281 nA
0 to 25 mA INT 0x0000 - 0x7FFF / 1 LSB = 0x0001 = 762.939 nA
0 to 25000 µA INT 0x0000 - 0x61A8 / 1 LSB = 0x0001 = 1000 nA
Load <300 Ω
Input protection Up to 30 VDC, reverse polarity protection (max. 0.1 A)
Open line detection Yes, via software
Permitted input signal 0 to 25 mA
Output of the digital value during overload Configurable
Conversion procedure Sigma Delta
Max. error at 25°C
Gain
0 to 25 mA <0.046% 3)
4 to 20 mA <0.046% 3)
Offset
0 to 25 mA <0.004% 4)
4 to 20 mA <0.013% 4)
Common-mode rejection
DC 80 dB
50 Hz Depends on the sampling rate: e.g. >130 dB for 50 scans per second
Common-mode range 0 to 7 V
Non-linearity <0.003% 4)
Input filter
Hardware 1st-order low pass / cut-off frequency 100 Hz
Software Sinc4 filter
Maximum gain drift
0 to 25 mA 0.003 %/°C 3)
4 to 20 mA 0.003 %/°C 3)
Maximum offset drift
0 to 25 mA 0.0002 %/°C 4)
4 to 20 mA 0.0007 %/°C 4)
Test voltage between
Channel and channel 1500 VAC
Channel and bus 1500 VAC
To ground 1500 VAC
Sensor supply
Nominal voltage 25 V ±2 %
Nominal output current Max. 30 mA

Table 42: X20AI2438 - Technical data

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Product ID X20AI2438
Short circuit protection Yes, continuous
Electrical isolation
Sensor supply - Channel No
Sensor supply - Sensor supply Yes
Maximum voltage ripple
Up to 100 kHz ≤2.2 mV
Up to 1 MHz ≤22 mV
Higher ≤100 mV
Short circuit current
Typical <50 mA
Maximum 60 mA
Behavior in the event of short circuit Current limitation
HART
Transfer rate 1200 bit/s
Operating frequencies 1200 Hz / 2200 Hz
Multi-drop operation
Possible Yes
Participants 5
Burst operation possible Yes
Transmission amplitude
Minimum 400 mVpp
Typical 500 mVpp
Maximum 600 mVpp
Receiving amplitude
Minimum 120 mVpp
Maximum 800 mVpp
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0,5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 42: X20AI2438 - Technical data

1) To reduce power dissipation, B&R recommends leaving unused inputs open.
2) Sensor supply
3) Based on the current measurement value
4) Based on the 25 mA measurement range.

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4.3.7.4 Status LEDs

Image LED Color Status Description

Operating mode
r Green Off Module supply not connected
Single flash Unlink mode
Blinking quickly Sync mode
Blinking slowly PREOPERATIONAL mode
On RUN mode
Module status
e Red Off Module supply not connected or everything is OK
Single flash A conversion error has occurred. This status is output along with a double flash
on the channel LED of the analog input where the error occurs.
On Error or reset status
Sensor supply
V Yellow Off Module supply not connected or overload
On Sensor supply in its normal operating range
Analog input
1-2 Green Off Indicates one of the following cases:
• Module supply not connected
• Channel disabled
• Open line
Single flash Input signal overflow or underflow
Double flash A conversion error has occurred. A single flash is output on the red "e" module
status LED.
On Analog/digital converter running, value OK
HART link
L Green Off Indicates one of the following cases:
• Module supply not connected
• HART disabled for the respective channel
Flickering Carrier signal active (DCD or RTS)
HART error
e Red Off Indicates one of the following cases:
• Communication taking place without errors
• Module supply not connected
• HART disabled for the respective channel
On Communication error

Table 43: X20AI2438 - Status LEDs

4.3.7.5 Pin assignments

Shielded twisted pair cables should be used to minimize coupling disturbances. Use either one cable for each
channel or a multiple twisted pair cable for both channels.

r e
X20 AI 2438

V V
1 2
L L
e e

Sensor supply 1 + Channel 1 +

Sensor supply 1 − Channel 1 −

Sensor supply 2 + Channel 2 +

Sensor supply 2 − Channel 2 −

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4.3.7.6 Connection examples

4.3.7.7 Input circuit diagram

Electrical
Isolation
Sensor supply x + I/O
DC/DC
Supply
DC/DC 28 V
Output 18 - 30 V
Converter
protection GND x GND I/O
25 V DC/DC
3.3 V
Sensor supply x -
GND x
RTS (Request to Send)

Channel x + HART
Modem

Input Processor
protection Protection

Shunt
A/D
and
Converter
Channel x - Filter

GND x

4.3.7.8 Behavior in the event of a short circuit

In the event of a short circuit, the output current for the sensor supply is limited according to the following diagram.
25

20
Voltage [V]

15

10

0
0 10 20 30 40 50

Current [mA]

Figure 72: Typical behavior of the sensor supply output current in the event of a short circuit

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4.3.7.9 Register description

4.3.7.9.1 Register overview - Function model 0 (standard)

Heading Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Analog signal - Communication channel 01
INT
0 AnalogInputEvaluated01 ● ●
UINT
30 AnalogStatus01 USINT ● ●
INT
258 AnalogInput01 ● ●
UINT
282 AnalogSampletime01_16bit INT
● ●
284 AnalogSampletime01_32bit DINT
Analog signal - Communication channel 02
INT
8 AnalogInputEvaluated02 ● ●
UINT
31 AnalogStatus02 USINT ● ●
INT
262 AnalogInput02 ● ●
UINT
290 AnalogSampletime02_16bit INT
● ●
292 AnalogSampletime02_32bit DINT
Analog signal - Configuration channel 01
386 AnMode_1 UINT ●
390 Samplerate_1 UINT ●
INT
394 OpenLoopLimit_1 ●
UINT
466 PreparationInterval_1 UINT ●
INT
414 ReplacementUpper_1 ●
UINT
INT
410 ReplacementLower_1 ●
UINT
INT
402 UpperLimit_1 ●
UINT
INT
398 LowerLimit_1 ●
UINT
INT
406 Hysteres_1 ●
UINT
418 ErrorDelay_1 UINT ●
422 SumErrorDelay_1 UINT ●
Analog signal - Configuration channel 02
426 AnMode_2 UINT ●
430 Samplerate_2 UINT ●
INT
434 OpenLoopLimit_2 ●
UINT
482 PreparationInterval_2 UINT ●
INT
454 ReplacementUpper_2 ●
UINT
INT
450 ReplacementLower_2 ●
UINT
INT
442 UpperLimit_2 ●
UINT
INT
438 LowerLimit_2 ●
UINT
INT
446 Hysteres_2 ●
UINT
458 ErrorDelay_2 UINT ●
462 SumErrorDelay_2 UINT ●
HART - Configuration channel 01
1537 HartNodeCnt_1 USINT ●
1539 HartMode_1 USINT ●
1541 HartBurstNode_1 USINT ●
HART - Configuration channel 02
1665 HartNodeCnt_2 USINT ●
1667 HartMode_2 USINT ●
1669 HartBurstNode_2 USINT ●
HART - Communication channel 01
562 + PvNodeComStatus01_01
UINT ●
Index*4 PvNodeComStatus01_[02…15]
602 + PvSampleTime01_01_16bit
INT
Index*24 PvSampleTime01_[02…15]_16bit
● ●
604 + PvSampleTime01_01_32bit
DINT
Index*24 PvSampleTime01_[02…15]_32bit
4 PvInput01_01
612 + REAL ● ●
PvInput01_[02…15]
Index*24
617 + PvUnit01_01
USINT ● ●
Index*24 PvUnit01_[02…15]

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Heading Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
HART - Communication channel 02
1074 + PvNodeComStatus02_01
UINT ●
Index*4 PvNodeComStatus02_[02…15]
1114 + PvSampleTime02_01_16bit
INT
Index*24 PvSampleTime02_[02…15]_16bit
● ●
1116 + PvSampleTime02_01_32bit
DINT
Index*24 PvSampleTime02_[02…15]_32bit
12 PvInput02_01
1124 + REAL ● ●
PvInput02_[02…15]
Index*24
1129 + PvUnit02_01
USINT ● ●
Index*24 PvUnit02_[02…15]
HART - Extension register channel 01
522 PvCountHartRequest01 UINT ● ●
530 PvCountHartTimeout01 UINT ● ●
538 PvCountHartRxError01 UINT ● ●
546 PvCountHartFrameError01 UINT ● ●
554 PvNodeFound01 UINT ● ●
558 PvNodeError01 UINT ● ●
1546 HartProtTimeOut_1 UINT ●
1550 HartProtRetry_1 UINT ●
1554 HartPreamble_1 UINT ●
1558 HartNodeDisable_1 UINT ●
HART - Extension register channel 02
1034 PvCountHartRequest02 UINT ● ●
1042 PvCountHartTimeout02 UINT ● ●
1050 PvCountHartRxError02 UINT ● ●
1058 PvCountHartFrameError02 UINT ● ●
1066 PvNodeFound02 UINT ● ●
1070 PvNodeError02 UINT ● ●
1674 HartProtTimeOut_2 UINT ●
1678 HartProtRetry_2 UINT ●
1682 HartPreamble_2 UINT ●
1686 HartNodeDisable_2 UINT ●
FlatStream
1793 OutputMTU USINT ●
1795 InputMTU USINT ●
1797 FlatstreamMode USINT ●
1799 Forward USINT ●
1801 ForwardDelay USINT ●
1857 InputSequence USINT ● ●
1857 + RxByte1
USINT ● ●
Index*2 RxByte[2…15]
1889 OutputSequence USINT ● ●
1889 + TxByte1
USINT ● ●
Index*2 TxByte[2…15]

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4.3.7.9.2 Variable assignment in Automation Studio (X2X master)

Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Analog signal - Communication channel 01
AnalogStatus01 USINT ●
UnderflowAnalogInput01 BOOL ●
OverflowAnalogInput01 BOOL ●
OpenLineAnalogInput01 BOOL ●
ConversionErrorAnalogInput01 BOOL ●
SumErrorAnalogInput01 BOOL ●
SensorErrorAnalogInput01 BOOL ●
IoSuppErrorAnalogInput01 BOOL ●
INT
AnalogInput01 ●
UINT
INT
AnalogSampletime01 ●
UINT
Analog signal - Communication channel 02
AnalogStatus02 USINT ●
UnderflowAnalogInput02 BOOL ●
OverflowAnalogInput02 BOOL ●
OpenLineAnalogInput02 BOOL ●
ConversionErrorAnalogInput02 BOOL ●
SumErrorAnalogInput02 BOOL ●
SensorErrorAnalogInput02 BOOL ●
IoSuppErrorAnalogInput02 BOOL ●
INT
AnalogInput02 ●
UINT
INT
AnalogSampletime02 ●
UINT
HART - Communication channel 01
INT
PvSampleTime01_[01…15] ●
UINT
PvInput01_[01…15] REAL ●
PvUnit01_[01…15] USINT ●
HART - Communication channel 02
INT
PvSampleTime02_[01…15] ●
UINT
PvInput02_[01…15] REAL ●
PvUnit02_[01…15] USINT ●
HART - Extension register channel 01
PvCountHartRequest01 UINT ●
PvCountHartTimeout01 UINT ●
PvCountHartRxError01 UINT ●
PvCountHartFrameError01 UINT ●
PvNodeFound01 UINT ●
PvNodeError01 UINT ●
HART - Extension register channel 02
PvCountHartRequest02 UINT ●
PvCountHartTimeout02 UINT ●
PvCountHartRxError02 UINT ●
PvCountHartFrameError02 UINT ●
PvNodeFound02 UINT ●
PvNodeError02 UINT ●
FlatStream
InputSequence USINT ●
RxByte[1…15] USINT ●
OutputSequence USINT ●
TxByte[1…15] USINT ●

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4.3.7.9.3 Register overview - Function model 254 (bus controller)

Heading Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Analog signal - Communication channel 01
INT
0 AnalogInputEvaluated01 ●
UINT
30 AnalogStatus01 USINT ●
Analog signal - Communication channel 02
INT
8 AnalogInputEvaluated02 ●
UINT
31 AnalogStatus02 USINT ●
Analog signal - Configuration channel 01
386 AnMode_1 UINT ●
390 Samplerate_1 UINT ●
INT
394 OpenLoopLimit_1 ●
UINT
466 PreparationInterval_1 UINT ●
INT
414 ReplacementUpper_1 ●
UINT
INT
410 ReplacementLower_1 ●
UINT
INT
402 UpperLimit_1 ●
UINT
INT
398 LowerLimit_1 ●
UINT
INT
406 Hysteres_1 ●
UINT
418 ErrorDelay_1 UINT ●
422 SumErrorDelay_1 UINT ●
Analog signal - Configuration channel 02
426 AnMode_2 UINT ●
430 Samplerate_2 UINT ●
INT
434 OpenLoopLimit_2 ●
UINT
482 PreparationInterval_2 UINT ●
INT
454 ReplacementUpper_2 ●
UINT
INT
450 ReplacementLower_2 ●
UINT
INT
442 UpperLimit_2 ●
UINT
INT
438 LowerLimit_2 ●
UINT
INT
446 Hysteres_2 ●
UINT
458 ErrorDelay_2 UINT ●
462 SumErrorDelay_2 UINT ●
HART - Configuration channel 01
1537 HartNodeCnt_1 USINT ●
1539 HartMode_1 USINT ●
1541 HartBurstNode_1 USINT ●
HART - Configuration channel 02
1665 HartNodeCnt_2 USINT ●
1667 HartMode_2 USINT ●
1669 HartBurstNode_2 USINT ●
HART - Communication channel 01
4 PvInput01_01 REAL ●
612 +
PvInput01_[02…15] REAL ●
Index*24
2 PvUnit01_01 USINT ●
617 +
PvUnit01_[02…15] USINT ●
Index*24
562 + PvNodeComStatus01_01
UINT ●
Index*4 PvNodeComStatus01_[02…15]
HART - Communication channel 02
12 PvInput02_01 REAL ●
1124 +
PvInput02_[02…15] REAL ●
Index*24
10 PvUnit02_01 USINT ●
1129 +
PvUnit02_[02…15] USINT ●
Index*24
1074 + PvNodeComStatus02_01
UINT ●
Index*4 PvNodeComStatus02_[02…15]
HART - Extension register channel 01
522 PvCountHartRequest01 UINT ●
530 PvCountHartTimeout01 UINT ●
538 PvCountHartRxError01 UINT ●

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Heading Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
546 PvCountHartFrameError01 UINT ●
554 PvNodeFound01 UINT ●
558 PvNodeError01 UINT ●
1546 HartProtTimeOut_1 UINT ●
1550 HartProtRetry_1 UINT ●
1554 HartPreamble_1 UINT ●
1558 HartNodeDisable_1 UINT ●
HART - Extension register channel 02
1034 PvCountHartRequest02 UINT ●
1042 PvCountHartTimeout02 UINT ●
1050 PvCountHartRxError02 UINT ●
1058 PvCountHartFrameError02 UINT ●
1066 PvNodeFound02 UINT ●
1070 PvNodeError02 UINT ●
1674 HartProtTimeOut_2 UINT ●
1678 HartProtRetry_2 UINT ●
1682 HartPreamble_2 UINT ●
1686 HartNodeDisable_2 UINT ●

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4.3.7.9.4 Variable assignment in Automation Studio (CANIO)

Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Analog signal - Communication channel 01
AnalogStatus01 USINT ●
UnderflowAnalogInput01 BOOL ●
OverflowAnalogInput01 BOOL ●
OpenLineAnalogInput01 BOOL ●
ConversionErrorAnalogInput01 BOOL ●
SumErrorAnalogInput01 BOOL ●
SensorErrorAnalogInput01 BOOL ●
IoSuppErrorAnalogInput01 BOOL ●
INT
AnalogInput01 ●
UINT
Analog signal - Communication channel 02
AnalogStatus02 USINT ●
UnderflowAnalogInput02 BOOL ●
OverflowAnalogInput02 BOOL ●
OpenLineAnalogInput02 BOOL ●
ConversionErrorAnalogInput02 BOOL ●
SumErrorAnalogInput02 BOOL ●
SensorErrorAnalogInput02 BOOL ●
IoSuppErrorAnalogInput02 BOOL ●
INT
AnalogInput02 ●
UINT
HART - Communication channel 01
REAL
PvInput01_01 ●
(UDINT)1)
PvInput01_[02…15] REAL ●
PvUnit01_[01…15] USINT ●
HART - Communication channel 02
REAL
PvInput02_01 ●
(UDINT)1)
PvInput02_[02…15] REAL ●
PvUnit02_[01…15] USINT ●
HART - Extension register channel 01
PvCountHartRequest01 UINT ●
PvCountHartTimeout01 UINT ●
PvCountHartRxError01 UINT ●
PvCountHartFrameError01 UINT ●
PvNodeFound01 UINT ●
PvNodeError01 UINT ●
HART - Extension register channel 02
PvCountHartRequest02 UINT ●
PvCountHartTimeout02 UINT ●
PvCountHartRxError02 UINT ●
PvCountHartFrameError02 UINT ●
PvNodeFound02 UINT ●
PvNodeError02 UINT ●

1) REAL data types are not supported by the B&R CANIO Manager on SG3 CPUs. Therefore they can be accessed as UDINT data types in the corresponding
hardware description files.

The UDINT variable data content corresponds to REAL format (IEEE), so it is important to note that using a "Casting" command is not permitted!

Example for C syntax: memcpy(HartREAL_PV,HartUDINT_PV,4)

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4.3.7.9.5 General information

The X20AI2438 module has two independent electrically isolated channels with integrated HART modems. Both
channels can be used to read in an analog signal and handle HART communication. Two registers need to be
configured for one analog signal. The two channels operate independently, so two registers must be configured
per channel to be used.
The current input signals (0 to 25 mA) can be displayed in various formats and used as conventional analog inputs.
The integrated HART modems retrieve digital information from the memory on the HART slave using the same
physical lines that modulate the HART signals.
When using the 0 to 25 mA current input variant, the module is conceived as a HART master for 2 channels (loops),
with FSK modulation of the HART protocol and sensor supply for max. 4 slaves per channel.
Each channel can use one of the following connection variants:
• Connection of one HART node (point-to-point) with evaluation of the analog signal and output of 4 HART
process variables OR
• Connection of up to 15 HART nodes in multidrop mode with output of the primary HART variable from
activated nodes
Specific features:
• Electrical isolation by channel
• Up to 4 or 15 HART input variables per channel
• Configurable sampling rate (input filter) to transfer HART and analog signal without interference (default:
50 Hz or 20 ms)
• Internal supply with short circuit protection <30 mA per channel
• Selective line monitoring can be enabled for: open line (<2 mA), underflow (<3.6 mA) or overflow (>21 mA)
of a configurable threshold
• Selectable error strategy (static replacement value or retention of the last permitted value)
• Cyclic "HART status" polling (HART command 0), the status information received is made available for
channel diagnostics
• Compatible with an additional secondary master in the HART network (module acts as the primary master)
• "HART communication error bit" (shows loss of HART connection if a connection had already been estab-
lished successfully)
• Optional: Burst mode for one node per channel
• Optional: Cyclic polling of "HART variables" (HART command 3 or 9)
• Optional: Sensor supply for max. 4 nodes per channel in the multidrop variant
• Optional: FlatStream functionality (module acts as bridge for HART packets)

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4.3.7.9.6 Analog signal - Communication

4.3.7.9.6.1 AnalogInputEvaluated

Names (pChannelName):
AnalogInputEvaluated01
AnalogInputEvaluated02
These registers take the values from the "AnalogInput" registers and use them to generate the evaluated input
values. The configured auxiliary functions are applied to form these values.
Data type Values
INT 0…25000: Normalizing option 0 to 25 mA
0…32767: Normalizing option 0 to 25 mA
0…32767: Normalizing option 4 to 20 mA
UINT 0…65535: Normalizing option 0 to 25 mA

Predefining values and timing

The value 0 (null) is output to the "AnalogInput" registers until a signal short circuit or converter error causes the
value to be changed.
The timing for acquiring measurement values is determined by the converter hardware and the set sampling rate.
The two channels are converted independently of each other and are not synchronized with the X2X bus.
Conversion time
Channel 0x sampling rate

4.3.7.9.6.2 AnalogInput

Names (pChannelName):
AnalogInput01
AnalogInput02
The normalized input values are transferred to these registers. Depending on the scaling selected, the value range
and the data type can be adapted to the requirements of the application. Generated limit values or value changes
from the configured limit value strategy have no effect on these registers.
Data type Values
INT 0…25000: Normalizing option 0 to 25 mA
0…32767: Normalizing option 0 to 25 mA
0…32767: Normalizing option 4 to 20 mA
UINT 0…65535: Normalizing option 0 to 25 mA

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4.3.7.9.6.3 AnalogStatus

Names (pChannelName):
AnalogStatus01
AnalogStatus02
The current error status of the module channels is displayed in this register, regardless of the configured replace-
ment value strategy. Some error information may be delayed according to the previously configured condition.
Data type Values
USINT See bit structure

Bit structure:
Bit Name Information
0 Underflow 0 No error
1 Underflow on Channel 0x
1 Overflow 0 No error
1 Overflow on Channel 0x
2 Open line 0 No error
1 Open line on Channel 0x
3 Conversion error 0 No error
1 Conversion error on Channel 0x
4 Composite error 0 No error
1 Composite error on Channel 0x
5 Reserved -
6 Sensor error 0 No error
1 Sensor error on Channel 0x
7 I/O supply error 0 No error
1 I/O supply error on Channel 0x

Data points from AnalogStatus:

Designation (pChannelName) Information
UnderflowAnalogInput01 0 No error
UnderflowAnalogInput02 1 Underflow on Channel 0x
OverflowAnalogInput01 0 No error
OverflowAnalogInput02 1 Overflow on Channel 0x
OpenLineAnalogInput01 0 No error
OpenLineAnalogInput02 1 Open line on Channel 0x
ConversionErrorAnalogInput01 0 No error
ConversionErrorAnalogInput02 1 Conversion error on Channel 0x
SumErrorAnalogInput01 0 No error
SumErrorAnalogInput02 1 Composite error on Channel 0x
SensorErrorAnalogInput01 0 No error
SensorErrorAnalogInput02 1 Sensor error on Channel 0x
IoSuppErrorAnalogInput01 0 No error
IoSuppErrorAnalogInput02 1 I/O supply error on Channel 0x

Underflow:
The signal underflow error status is indicated here according to the configuration. This error information is activated
as a multiple of the conversion cycles only after the configurable delay time has passed ("ErrorDelay" registers).
Overflow:
The signal overflow error status is indicated here according to the configuration. This error information is activated
as a multiple of the conversion cycles only after the configurable delay time has passed ("ErrorDelay" registers).
Open line:
According to the configuration, measurement information is checked for values <2 mA ("OpenLoopLimit" register)
to detect a failure signal. Open line detection takes place using a configurable hysteresis value (default: 100 µA,
"Hysteresis" registers). It is possible to disable open line detection ("AnalogMode" registers) to suppress alarms
when hardware is not present. This error information is activated as a multiple of the conversion cycles only after
the configurable delay time has passed ("ErrorDelay" registers).
Conversion error:
This error status is triggered when the hardware exceeds the conversion time.
Composite error:
This error information derives from the status of individual errors and is only activated after the configurable delay
time has passed ([msec], "SumErrorDelay" registers). Linking this error information to an application makes it
possible to hide temporary temperature value overflows and underflows, for example.
Sensor error:
This error is activated immediately after a fault is detected in the internal sensor supply.

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I/O supply error:

This error is activated immediately as soon as the module detects that the necessary supply voltage is no longer
being provided (<20 VDC).

4.3.7.9.6.4 AnalogSampletime

Names (pChannelName):
AnalogSampletime01
AnalogSampletime01_16bit
AnalogSampletime01_32bit
AnalogSampletime02
AnalogSampletime02_16bit
AnalogSampletime02_32bit
The registers return the timestamp for when the module reads the current channel mapping. The values are pro-
vided as signed 2-byte or 4-byte values.
Data type Values [µs]
INT -32768 to 32767: Nettime timestamp of the current input value
DINT -2,147,483,648 to 2,147,483,647: Nettime timestamp of the current input value

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4.3.7.9.7 Analog signal - Configuration

How the analog signal is displayed can be adapted to the requirements of the application. Separate configuration
registers per channel are available to aid in this.

4.3.7.9.7.1 Analog mode

Names (pChannelName):
AnMode_1
AnMode_2
These registers are used to predefine the operating parameters that the module will be using for the respective
channel. Each channel must be enabled individually and can be configured and operated independently.
It is extremely important to not that different limit values need to be configured for any display normalizing that
needs to take place.
Data type Values
UINT See bit structure

Bit structure:
Bit Name Information
0 Channel 0 Channel 0x turned off
1 Channel 0x enabled (bus controller default setting)
1 Open line detection 0 Open line monitoring turned off
1 Open line monitoring enabled (bus controller default setting)
2 Underflow detection 0 Underflow detection turned off
1 Underflow detection enabled (bus controller default setting)
3 Replacement value strategy 0 Use replacement values when an error occurs (bus controller
default setting)
1 Keep the last valid converted value
4-5 Normalization 00 Displays 0...25 mA as 0...32767
01 Displays 0...25 mA as 0...25000 [µA] (bus controller default set-
ting)
10 Displays 4...20 mA as 0...32767
11 Displays 0...25 mA as 0...65535
6-15 Reserved

4.3.7.9.7.2 Sample rate

Names (pChannelName):
Samplerate_1
Samplerate_2
A sample rate can be configured for both analog inputs independently of one another. The following formula for
this parameter is derived using the desired sampling frequency:
Sample rate for ADC = (4920000/1024)/sampling frequency
Data type Values
UINT 48 - 1023: Sample rate
960 ... 200 ms ... 5 Hz
480 ... 100 ms ... 10 Hz
320 ... 66.7 ms ... 15 Hz
192 ... 40 ms ... 25 Hz
160 ... 33.3 ms ... 30 Hz
96 ... 20 ms ... 50 Hz (bus controller default setting)
80 ... 16.7 ms ... 60 Hz
48 ... 10 ms ... 100 Hz

The fastest sample rate of 10 ms for the analog inputs is predefined by the cut-off frequency of the hardware filter.
When using HART communication, however, a sample rate not faster than 100 ms is recommended.

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4.3.7.9.7.3 OpenLoopLimit

Names (pChannelName):
OpenLoopLimit_1
OpenLoopLimit_2
The limit value for the respective analog input must be set when open circuit monitoring is enabled and if required
by the configured normalization. If limit value monitoring is active, the corresponding error status is output after a
configured delay when falling below this value. Using a default value of 2000 µA, the following values and formulas
apply to this parameter:
• Displaying 0..25 mA as 0..25000 : 2000
• Displaying 0..25 mA as 0..32767 : 2621, limit value = ([µA]*32767)/25000
• Displaying 4..20 mA as 0..32767 : -4096, limit value = (([µA]*1.31068) - 5242.72)*1.5625
• Displaying 0..25 mA as 0..65535 : 5243, limit value = ([µA]*65535)/25000
Data type Values
INT -32767...32767: Open circuit limit value
UINT 0...65535: Open circuit limit value

4.3.7.9.7.4 PreparationInterval

Names (pChannelName):
PreparationInterval_1
PreparationInterval_2
If the last valid measurement value should be kept when violating the limit value, then PreparationInterval must be
defined. The measurement values continue to be acquired and converted according to the configured I/O update
time. They are then checked and discarded if they do not meet the specifications. When an error does not occur,
therefore, the measurement value acquired two preparation intervals ago is constantly output.
Data type Values [0.1 ms]
UINT 0…65535

"Application"
How it works: for the value being measured (analog)
Measured values are converted at the configured conversion rate and saved to measurement value memory. Condition:
The current contents of the measurement value memory are checked within the configured interval. If a permis- ↓
- Conversion interval (ADC) elapsed
sible value is present, then the contents of the buffer memory are passed to output memory and the contents of "Measurement value memory"
the measurement value memory are passed to the buffer. Measurement value (digital)
If the check turns up an impermissible value, then the contents of the measurement value memory are discard-
Condition:
ed. The copy direction between the output and buffer memory reverses and the last valid value continues to be
↓ - PreparationInterval elapsed
output.
- Measurement value permissible
"Buffer"
Information: Last valid value
Condition:
If configured to keep the last valid value, the delay time from measuring to outputting the value ↓ - PreparationInterval elapsed
will be at least twice the preparation interval. In the worst case scenario, this can also take twice - Measurement value permissible
the interval time plus the configured ADC conversion rate. "Output memory"
Next-to-last valid/
displayed value

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4.3.7.9.7.5 ReplacementUpper, ReplacementLower

Names (pChannelName):
ReplacementUpper_1
ReplacementUpper_2
ReplacementLower_1
ReplacementLower_2
The "Replace" registers are used to predefine the static values that will be displayed instead of the current mea-
surement value when a limit value is violated.
Data type Values
INT -32767...32767
UINT 0...65535

If the replacement strategy "Use replacement values when an error occurs" is activated, the replacement value must
be set for the respective analog input taking the configured normalization into account as well. When an overflow
or underflow error status occurs, the "AnalogInputEvaluated0x" channel is replaced with the corresponding value.
Using a default value of 21000 µA and 3600 µA, the following values and formulas apply to this parameter:
Overflow:
• Displaying 0..25 mA as 0..25000 : 21000
• Displaying 0..25 mA as 0..32767 : 27524, limit value = ([µA]*32767)/25000
• Displaying 4..20 mA as 0..32767 : 32767, limit value = (([µA]*1.31068) - 5242.72)*1.5625
• Displaying 0..25 mA as 0..65535 : 55049, limit value = ([µA]*65535)/25000
Underflow:
• Displaying 0..25 mA as 0..25000 : 3600
• Displaying 0..25 mA as 0..32767 : 4718, limit value = ([µA]*32767)/25000
• Displaying 4..20 mA as 0..32767 : -819, limit value = (([µA]*1.31068) - 5242.72)*1.5625
• Displaying 0..25 mA as 0..65535 : 9437, limit value = ([µA]*65535)/25000

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4.3.7.9.7.6 UpperLimit, LowerLimit

Names (pChannelName):
UpperLimit_1
UpperLimit_2
LowerLimit_1
LowerLimit_2
If the value range needs to be restricted further, the "UpperLimit" and "LowerLimit registers can be used to enter
new user-specific limit values.
Data type Values
INT -32767…32767
UINT 0...65535

The limit value must be set for the respective analog input depending on the configured normalization. After the
configured delay time has passed, the corresponding error status is given if the respective value is overrun or
underrun. When this error status occurs, the "AnalogInputEvaluated0x" channel is evaluated according to the
replacement value strategy. Using a default value of 21000 µA and 3600 µA, the following values and formulas
apply to this parameter:
UpperLimit
• Displaying 0..25 mA as 0..25000 : 21000
• Displaying 0..25 mA as 0..32767 : 27524, limit value = ([µA]*32767)/25000
• Displaying 4..20 mA as 0..32767 : 32767, limit value = (([µA]*1.31068) - 5242.72)*1.5625
• Displaying 0..25 mA as 0..65535 : 55049, limit value = ([µA]*65535)/25000
LowerLimit
• Displaying 0..25 mA as 0..25000 : 3600
• Displaying 0..25 mA as 0..32767 : 4718, limit value = ([µA]*32767)/25000
• Displaying 4..20 mA as 0..32767 : -819, limit value = (([µA]*1.31068) - 5242.72)*1.5625
• Displaying 0..25 mA as 0..65535 : 9437, limit value = ([µA]*65535)/25000

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4.3.7.9.7.7 Hysteresis

Names (pChannelName):
Hysteres_1
Hysteres_2
If the user-specific limit values are being used, then a hysteresis range should also be defined. The "Hysteresis"
registers configure how far a limit value can be exceeded before a response is triggered.
Data type Values
INT -32767…32767
UINT 0...65535

Te hysteresis value must be set for the respective analog input dpending on the configured normalization. The
error status is cleared if the actual analog value changes by at least this hysteresis value from the limit value in the
allowed direction. Using a default value of 100 µA, the following values and formulas result for this parameter:
• Displaying 0..25 mA as 0..25000 : 100
• Displaying 0..25 mA as 0..32767 : 131, limit value = ([µA]*32767)/25000
• Displaying 4..20 mA as 0..32767 : 156, limit value = [µA]*1.5625
• Displaying 0..25 mA as 0..65535 : 262, limit value = ([µA]*65535)/25000

4.3.7.9.7.8 ErrorDelay

Names (pChannelName):
ErrorDelay_1
ErrorDelay_2
This register specifies the number of consecutive conversion procedures where an error is pending until the cor-
responding individual error status bit is set. The delay applies to underflow, overflow and open circuit errors. This
delay can be used to hide temporary measurement value deviations, for example.
Data type Values
UINT 0...10: Error formation delay [conversion cycles]
2 conversion cycles [default]

4.3.7.9.7.9 SumErrorDelay

Names (pChannelName):
SumErrorDelay_1
SumErrorDelay_2
This register specifies the time in milliseconds that one of the individual error bits must be pending until the com-
posite error status bit is set.
Data type Values
UINT 0...65535: Composite error bit delay [msec]
4000 msec [default]

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4.3.7.9.8 HART

HART (Highway Addressable Remote Transducer) is a protocol for communicating with intelligent field devices. It
was developed in order to more efficiently use the infrastructure for transferring analog signals. The digital HART
notifications are modulated to the analog signal using Frequency Shift Keying (FSK). HART can thus use the same
physical line as the analog signal without influencing the original function.
HART slaves are able to determine different process data independently and prepare HART concordantly. This
protocol supports polling of the value of a process variable as well as its unit and status. Field devices usually supply
their information after the master requests it. In newer revisions, it is also possible to transfer configuration data.
There are two different types of HART networks. In a point-to-point network, only one slave is connected to a HART
master. Here, the analog signal and the HART signal can be transferred over the same line. Managing several
slaves with HART requires what is known as a multidrop network. Here, each HART slave is assigned and identified
by a unique address. Classic analog signals cannot be clearly traced in bus systems. As a result, the HART protocol
does not support analog information transfers in multidrop networks up to and including HART Revision 5.

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4.3.7.9.8.1 HART - Register names (pChannelName)

• HART configuration:
HartNodeCnt_1
HartNodeCnt_2
HartBurstNode_1
HartBurstNode_2
HartMode_1
HartMode_2
• HART communication:
PvInput01_[01...15]
PvInput02_[01...15]
PvUnit01_[01...15]
PvUnit02_[01...15]
PvSampleTime01_[01...15]
PvSampleTime01_[01...15]_16bit
PvSampleTime01_[01...15]_32bit
PvSampleTime02_[01...15]
PvSampleTime02_[01...15]_16bit
PvSampleTime02_[01...15]_32bit
PvNodeComStatus01_[01...15]
PvNodeComStatus02_[01...15]
PvCountHartRequest01
PvCountHartRequest02
PvCountHartTimeout01
PvCountHartTimeout02
PvCountHartRxError01
PvCountHartRxError02
PvCountHartFrameError01
PvCountHartFrameError02
PvNodeFound01
PvNodeFound02
PvNodeError01
PvNodeError02
• HART - Extended configuration:
HartNodeDisable_1
HartNodeDisable_2
HartProtTimeOut_1
HartProtTimeOut_2
HartProtRetry_1
HartProtRetry_2
HartPreamble_1
HartPreamble_2

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4.3.7.9.8.2 HART - Configuration

HART modules are analog modules equipped with a HART modem. For each channel, a separate HART network
can be managed by the module, which acts as a primary master. Once configured successfully, the HART infor-
mation is stored in the module where it can then be used by the PLC.
The number of HART slaves must be specified in the configuration.
If only one slave is connected to the HART channel, then it is part of a point-to-point network. The module can then
prepare up to four process variables from the connected slave.
Multidrop mode allows up to 15 HART slaves to be connected. The primary process variable from each slave is
then retrieved.

HartNodeCnt

The "HartNodeCnt" registers tell the module how many HART slaves are connected to a channel.

Information:
If a slave is not connected to one of the HART channels, the value "0" should be defined in this register.
This shortens the I/O update time and avoids superfluous error messages.
Data type Values
USINT 0 HART communication disabled for this channel
1 Point-to-point Standard HART communication (bus controller default)
2 to 15 Multidrop Number of HART slave nodes

HartBurstNode

In addition to the type of network, the user can also choose from two different types of communication behavior.
Conventional HART communication relies on polling. The module requests the data from the individual HART
slaves and receives the corresponding information from each slave as a response. If a HART node should be
queried in short time intervals, the user can configure burst mode for channels on one node. In this case, the slave
transmits the node's information cyclically without constant prompting from the master.
The "HartBurstNode" registers are therefore used to enter the node numbers (short address) for the channels
whose information should be retrieved using burst mode. Burst mode itself is enabled with the "HartMode" register.
Data type Values
USINT 0 to 15
Point-to-point → 0 (bus controller default)

HartMode

The user can use the "HartMode" registers to configure the communication behavior of each of the HART channels.
Generally, the HART nodes are polled individually. This register can still be used to start or stop burst mode when
needed.
In burst mode, a node transmits its information cyclically instead of continuously. As a result, the HART standard
allows the simultaneous usage of both burst mode and polling.

Information:
To retrieve information with burst mode, the "HartBurstNode" register must be configured correctly.
Data type Values
USINT See bit structure

Bit structure:
Bit Name Information
0 Slave polling mode 0 Polling mode enabled (bus controller default)
1 Polling mode disabled
1 Start slave burst mode 0 No response to burst (bus controller default)
1 Enables burst mode in the "HartBurstNode" node
2 Stop slave burst mode 0 No response to burst (bus controller default)
1 Disables burst mode if enabled
3-7 Reserved -

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4.3.7.9.8.3 HART - Communication

Once the configuration has been completed, the information is retrieved automatically and transferred to the
module's registers. A separate register in the module is implemented for each piece of information. HART modules
are designed to retrieve up to 15 pieces of information per channel. The module reads in the data, stores it in tem-
porary memory and prepares it for retrieval. When the X2X master accesses the module registers, it is irrelevant
whether the HART data originates from a point-to-point network or a multidrop network.

Overview of internal module mapping

Point-to-point network (1 HART slave) Multidrop network (2 to 15 HART slaves)
(Pv)Input_01 Primary piece of information from HART node 1 Primary piece of information from HART node 1
(Pv)Input_02 Secondary piece of information from HART node 1 Primary piece of information from HART node 2
… … …
(Pv)Input_04 Quaternary piece of information from HART node 1 Primary piece of information from HART node 4
(Pv)Input_05 Reserved Primary piece of information from HART node 5
… … …
(Pv)Input_15 Reserved Primary piece of information from HART node 15

The HART specifications stipulates that information from a HART node be split into various pieces. The value of a
process variable is stored to the respective "PvInput" register and has a size of 4 bytes (REAL) in accordance with
the HART specification. Due to the length limitation of 30 bytes on the X2X bus, there are restrictions to the number
of cyclic variables possible. It is recommended to only transfer a maximum of two "PvInput" registers cyclically to
the X2X master. All other information should be transferred in a different way. To access HART information, the
user can choose from among the following methods:
• Data points that are configured to be transferred cyclically are read once per bus cycle. This method allows
information to be exchanged between the module and the X2X master in real time. Nevertheless, the length
limitation may prevent all data from being retrieved within one cycle.
• If the AsIOAcc library is used, information is retrieved acyclically only when it is needed, i.e. communication
can be adapted to the application running on the X2X master. In this way, all of the necessary module
registers on the X2X bus can be polled despite the length limitation.
This method of information exchange is not real-time capable.
• HART modules are equipped with a FlatStream interface. When using FlatStream communication, the
module acts a bridge between the X2X master and the HART slave, i.e. the X2X master communicates
directly with the HART slave (see section "FlatStream communication").
FlatStream communication is also not real-time capable. It allows unrestricted access to the HART slave.
The user must have sufficient knowledge of the HART protocol command set as well as the capabilities
of the HART slave device.

PvInput

The "Input" registers return the current value of the process variable that has been read.

Information:
These registers are of data type REAL, which means that the available bytes on the X2X bus are filled
more quickly when operated cyclically. If information from several slave nodes is needed, it must be
retrieved acyclically or using FlatStream.
Data type Values
REAL IEEE745 SPF: 32-bit data type with valid value
0x7FA00000: Not a number (NaN) with invalid value

PvUnit

The "PvUnit" registers return a HART-specific code that specifies the unit for the measured value. The coding for
this is established in the HART specification.
Data type Values
USINT See description of the HART slave
See HART specification

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PvSampleTime

The registers return the timestamp for when the module reads the current channel mapping. The values are pro-
vided as signed 2-byte or 4-byte values.
Data type Values [µs]
INT -32768 to 32767: Nettime timestamp of the current input value
DINT -2,147,483,648 to 2,147,483,647: Nettime timestamp of the current input value

This refers to the point in time when the HART master receives the slave's response. This is a way to check whether
new HART information has been read since the last X2X cycle.

Information:
The cycle times of a HART network are relatively long so that it is not possible to reliably determine
when exactly the measured value is retrieved with just this information.

PvNodeComStatus

The "PvNodeComStatus" registers return information about whether a value that has been read is valid. According
to the HART specification, this type of status register consists of two parts. The high byte stores the "response
code" and the low byte the "field device status". This makes it possible to check the current status of a read process
variable.
The "PvNodeComStatus" register can be checked before further processing information in temporary storage. If
the current value is 0x0000, an error was not detected during the HART transfer and the information from the
checked node can be used. If a different value is present, the situation in the HART network should be checked.
This can be done using an extension register, for example.
Data type Values
UINT See bit structure

Bit structure:
Bit Name Information
0 Quality - Node information 2…n 0 Digital measured value okay
1 Measured value outside the permitted range
1 Quality - Node information 1 0 Digital measured value okay
1 Measured value outside the permitted range
2 Limit violation 0 Parameter okay
1 Invalid measured value(s) or encoder supply value
3 Static analog signal 0 Normal value change/fluctuation
1 Constant analog value of Node 1 slave
4 Additional status information 0 Not available
(only supported by a few slaves) 1 Available (only using FlatStream command #48)
5 Reboot 0 Normal operation
1 Field device restarts
6 Device ID 0 Unchanged
1 Changed
7 Device error 0 Measured value okay
1 Questionable measured value information
8-14 Response code, if relevant See coding (HART-specific)
15 Error - Communication 0 Error-free communication (response code irrelevant)
1 Faulty communication (response code relevant)

HART-specific response code (excerpt):

0x82 … Receive buffer overflow If a HART communication error occurs, the response code is written. Bit 15 is
0x88 … Incorrect checksum always set.
0x90 … Faulty protocol structure
0xA0 … Overrun
0xC0 … Parity not allowed
0xFF … Timeout

Retrieving information that has been read

After the node data has been transferred to the module registers, the information can be retrieved from the module.
A separate register in the module is implemented for each piece of information.

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PvCountHartRequest

The "PvCountHartRequest" registers are increased once the module is ready to transmit a message to the corre-
sponding channel.
Data type Values
UINT 0 to 65535

PvCountHartTimeout

The "PvCountHartTimeout" registers are increased if the slave exceeds the maximum permitted time before re-
sponding to the module's request.
Data type Values
UINT 0 to 65535

PvCountHartRxError

The "PvCountHartRxError" registers are increased if communication errors occur on Layer 1 of the OSI model (e.g.
transmission error as per parity bit).
Data type Values
UINT 0 to 65535

PvCountHartFrameError

The "PvCountHartFrameError" registers are increased if communication errors occur on Layer 2 of the OSI model
(e.g. faulty telegram structure).
Data type Values
UINT 0 to 65535

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PvNodeFound

The "PvNodeFound" registers provide information about which nodes were detected on which channel (slave
identified successfully).
Data type Values
UINT See bit structure

Bit structure:
Bit Name Information
0 Node 0 (default mode) 0 Not detected as valid
Node 1 (multidrop mode) 1 Detected as valid
1 Node 2 (multidrop mode) 0 Not detected as valid
1 Detected as valid
...
13 Node 14 (multidrop mode) 0 Not detected as valid
1 Detected as valid
14 Node 15 (multidrop mode) 0 Not detected as valid
1 Detected as valid
15 Reserved -

PvNodeError

The "PvNodeError" registers contain the HART communication error bits. These bits are set if the connection to
a node was established successfully but the node at some point no longer responds as it should (e.g. the HART
slave exceeds the configured timeout / number of retries).
Data type Values
UINT See bit structure

Bit structure:
Bit Name Information
0 Node 0 (default mode) 0 Detected as having no errors
Node 1 (multidrop mode) 1 Error
1 Node 2 (multidrop mode) 0 Detected as having no errors
1 Error
...
13 Node 14 (multidrop mode) 0 Detected as having no errors
1 Error
14 Node 15 (multidrop mode) 0 Detected as having no errors
1 Error
15 Reserved -

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4.3.7.9.8.4 Extended configuration

The additional configuration registers are specified values when the module is started. In most systems, the user
does not need to make any adjustments here. Register values should only be changed if HART network commu-
nication is not taking place satisfactorily.

HartNodeDisable

The "HartNodeDisable" registers are intended for things like maintenance. They make it possible to cut off config-
ured HART nodes to suppress error messages for a certain period of time. During normal operation, the configured
nodes must be switched active to guarantee that the procedure runs smoothly.
Data type Values
UINT See bit structure

Bit structure:
Bit Name Information
0 Node 0 (default mode) 0 Enabled (bus controller default)
Node 1 (multidrop mode) 1 Disabled
1 Node 2 (multidrop mode) 0 Enabled
1 Disabled (bus controller default)
...
13 Node 14 (multidrop mode) 0 Enabled
1 Disabled (bus controller default)
14 Node 15 (multidrop mode) 0 Enabled
1 Disabled (bus controller default)
15 Reserved -

HartProtTimeOut

The "HartProtTimeOut" registers specify the time span within which the slave must respond for the response to
be valid.
Data type Values [ms]
UINT 0 to 65535
Bus controller default: 256 [ms]

HartProtRetry

The "HartProtRetry" registers how many times the master retries a request if it receives an invalid response or
no response at all.
Data type Values
UINT 0 to 65535
Bus controller default: 3 attempts

HartPreamble

The length of the preamble can be set in the "HartPreamble" registers. The preamble is used to synchronize the
receiver to the transmitter. The longer the declared preamble, the less chance that a communication error will
occur. Nevertheless, a useful signal is not transmitted during synchronization so the preamble should be kept as
short as possible.
Data type Values
UINT 5 to 20
Bus controller default: 20

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4.3.7.9.9 FlatStream communication

4.3.7.9.9.1 Introduction

B&R offers an additional communication method for some modules. "FlatStream" was designed for X2X and
POWERLINK networks and allows data transmission to be adapted to individual demands. Although this method
is not 100% real-time capable, it still allows data transmission to be handled more efficiently than with standard
cyclic polling.
Field device
X2X language

Cyclic call
via I/O mapping

B&R CPU
Cyclic call B&R module Cyclic
PLC or B&R field device
of cached values cached value communication
bus controller

Acyclic call
via
library functions
B&R CPU
Acyclic call B&R module Cyclic
PLC or B&R field device
of cached values cached value communication
bus controller

FlatStream

B&R CPU X2X-compatible B&R module

PLC or Device command B&R field device
device command as a bridge
bus controller

Figure 73: Three types of communication

FlatStream extends cyclic and acyclic data queries. With FlatStream communication, the module acts as a bridge.
It is used to pass CPU queries directly on to the field device.

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4.3.7.9.9.2 Message, segment, sequence, MTU

The physical properties of the bus system limit the amount of data that can be transmitted during one bus cycle.
With FlatStream communication, all messages are viewed as part of a continuous data stream. Long data streams
must be broken down into several fragments that are sent one after the other. To understand how the receiver puts
these fragments back together to get the original information, it is important to understand the difference between
a message, a segment, a sequence and an MTU.
Message:
A message refers to information exchanged between two partner stations. The length of a message is not restricted
by the FlatStream communication method. Nevertheless, module-specific limitations must be considered.
Segment (logical division of a message):
A segment has a finite size and can be understood as a section of a message. The number of segments per
message is arbitrary. So that the recipient can correctly reassemble the transmitted segments, each segment
is preceded by a byte with additional information. This control byte contains information such as the length of a
segment and whether the approaching segment completes the message. This makes it possible for the receiving
station to interpret the incoming data stream correctly.
Sequence (how a segment needs to be arranged physically):
The maximum size of a sequence corresponds to the number of enabled Rx or Tx bytes (later: "MTU"). The
transmitting station splits the transmit array into valid sequences. These sequences are then written successively
to the MTU and transmitted to the receiving station where they are put back together again. The receiver stores
the incoming sequences in a receive array, obtaining an image of the data stream in the process.
With FlatStream communication, the number of sequences sent are counted. Successfully transmitted sequences
must be acknowledged by the receiving station to ensure the integrity of the transmission.
MTU (Maximum Transmission Unit) – Physical transport:
MTU refers to the enabled USINT registers used with FlatStream. These registers can accept at least one se-
quence and pass it on to the receiving station. A separate MTU is defined for each direction of communication.
The OutputMTU defines the number of FlatStream Tx bytes, and the InputMTU specifies the number of FlatStream
Rx bytes. The MTUs are transported cyclically via the X2X Link, increasing the load with each additional enabled
USINT register.
Properties:
FlatStream messages are not transmitted cyclically or in 100% real time. Many bus cycles may be needed to trans-
mit a particular message. Although the Rx and Tx registers are exchanged between the transmitter and the receiv-
er cyclically, they are only processed further if explicitly accepted by the "InputSequence" or "OutputSequence"
register.
Behavior in the event of an error (brief summary):
The protocol for X2X and POWERLINK networks specifies that the last valid values should be retained when
disturbances occur. With conventional communication (cyclic/acyclic data queries), this type of error can generally
be ignored.
In order for communication to also take place without errors using FlatStream, all of the sequences issued by the
receiver must be acknowledged. If Forward functionality is not used, then subsequent communication is delayed
for the length of the disturbance.
If Forward functionality is being used, the receiving station receives a transmission counter that is incremented
twice. The receiver stops, i.e. it no longer returns any acknowledgments. The transmitting station uses the Se-
quenceAck to determine that the transmission was faulty and that all affected sequences will have to be repeated.

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4.3.7.9.9.3 The FlatStream principle

Requirements:
Before FlatStream can be used, the respective communication direction must be synchronized, i.e. both commu-
nication partners cyclically query the sequence counter on the opposite station. This checks to see if there is new
data that should be accepted.
Communication:
If a communication partner wants to transmit a message to its opposite station, it should first create a transmit
array that corresponds to FlatStream conventions. This allows the FlatStream data to be organized very efficiently
without having to block other important resources.
PLC / Bus controller Module
Module-internal Module-internal
Transmit array OutputMTU Receive buffer Receive array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 TxBytes Cyc. *RxBytes _data_01

_data_02 _data_02
If OutputMTU The transmit buffer If the OutputSequence-
_data_03 is enabled: on the module is counter is incremented: _data_03
adapted cyclically to
_data_04 CPU fills OutputMTU via X2X Module adds the transmit buffer _data_04
OutputMTU . to the internal array
_data_05 with the next
_data_05
... sequence from the If successful: ...
Transmit array InputSequenceAck is
_data_xx adapted to the _data_xx
transmit array.

Module-internal Module-internal
Receive array InputMTU Send buffer Transmit array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 RxBytes Cyc. *TxBytes _data_01

_data_02 _data_02
If the InputMTU is If permitted:
_data_03 InputSequence- adapted cyclically to Module fills the internal _data_03
counter is incremented: adapted to the transmit buffer with the
_data_04 receive buffer. next sequence _data_04
_data_05 InputMTU must of the transmit array _data_05
be added to the
... end of the receive array Module increments the ...
(Increase InputSequenceAck InputSequence counter
_data_xx to finish correctly) _data_xx

Figure 74: FlatStream communication

Procedure:
The first thing that happens is that the message is broken into valid segments of up to 63 bytes, and the corre-
sponding control bytes are created. The data is formed into a data stream made up of one control bytes per asso-
ciated segment. This data stream can be written to the transmit array. The maximum size of each array element
matches that of the enabled MTU so that one element corresponds to one sequence.
When the array has been completely created, the transmitter checks whether the MTU is allowed to be refilled.
Then it copies the first element of the array or the first sequence to the Tx byte registers. The MTU is transported to
the receiver station via X2X Link and stored in the corresponding Rx byte registers. To signal that the data should
be accepted by the receiver, the transmitter increases its SequenceCounter.
If the communication direction is synchronized, the opposite station detects the incremented SequenceCounter.
The current sequence is appended to the receive array and acknowledged by SequenceAck. This acknowledgment
signals to the transmitter that the MTU can now be refilled.
If the transmission is successful, the data in the receive array will correspond 100% to the data in the transmit array.
During the transmission, the receiving station must detect and evaluate the incoming control bytes. A separate
receive array should be created for each message. This allows the receiver to immediately begin further processing
of messages once they have been completely transmitted.

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4.3.7.9.9.4 Registers for FlatStream mode

Five registers are available for configuring FlatStream. The default configuration can be used to transmit small
amounts of data relatively easily.

Information:
The CPU communicates directly with the field device via the OutputSequence/InputSequence registers
and the enabled Tx / Rx bytes. For this reason, the user needs to have sufficient knowledge of the
communication protocol being used on the field device.

FlatStream configuration

To use FlatStream, the program sequence must first be expanded. The cycle time of the FlatStream routines must
be set to a multiple of the bus cycle. Other program routines should be implemented in Cyclic #1 to ensure data
consistency.
At the absolute minimum, the "InputMTU" and "OutputMTU" registers need to be configured. All other registers are
filled in with default values at the beginning and can be used immediately. These registers are used for additional
options, e.g. to transmit data in a more compact way or to increase the efficiency of the general procedure.
The Forward registers extend the functionality of the FlatStream protocol. This functionality is useful for substan-
tially increasing the FlatStream data rate, but it also requires quite a bit of extra work when creating the program
sequence.

OutputMTU, InputMTU
These registers define the number of enabled Tx or Rx bytes, i.e. the maximum size of a sequence. The user must
consider that the more bytes made available also means a higher load on the bus system.

Information:
In the rest of this documentation, the names "OutputMTU" and "InputMTU" do not refer to the registers
explained here. Instead, they are used as synonyms for the currently enabled Tx or Rx bytes.
Data type Value
USINT See the module-specific register overview (theoretically: 3 - 27)

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FlatStream operation

When using FlatStream, the communication direction is enormously important. For sending data to a module ("out-
put" direction), the Tx bytes are used. For receiving data from a module ("input" direction), the Rx bytes are used.
The "OutputSequence" and "InputSequence" registers are used to control and ensure that communication is taking
place properly, i.e. the transmitter issues the directive that the data should be accepted and the receiver acknowl-
edges that a sequence has been transmitted successfully.
Tx and Rx bytes:
The Tx and Rx bytes are cyclic registers used to transport the payload data and the necessary control bytes.
The number of active Tx/Rx bytes is taken from the configuration of the "OutputMTU" and "InputMTU" registers,
respectively.
In the user program, only the Tx/Rx bytes from the CPU can be used. The corresponding counterparts are located
in the module and are not accessible to the user. For this reason, names were chosen from the CPU point of view.
• "T" - "Transmit" → CPU transmits data to the module.
• "R" - "Receive" → CPU receives data from the module.
Data type Value
USINT 0...65535

Control bytes:
In addition to the payload data, the Tx and Rx bytes also transmit the necessary control bytes. These control bytes
contain additional information about the data stream so that the receiver can reconstruct the original message from
the transmitted segments.
Bit structure of a control byte:
Bit Name Information
0-5 SegmentLength 0-63 Size of the subsequent segment in bytes (default: Max. MTU size - 1)
6 nextCBPos 0 Next control byte at the beginning of the next MTU
1 Next control byte directly after the end of the current segment
7 MessageEndBit 0 Message continues after the subsequent segment
1 Message ended by the subsequent segment

SegmentLength:
The segment length lets the receiver know the length of the coming segment. If the configured segment length
is insufficient for a message, then the information must be distributed over several segments. In these cases, the
actual end of the message is detected using bit 7 of the control byte.

Information:
The control byte is not included in the calculation to determine the segment length. The segment length
is only derived from the bytes of payload data.
nextCBPos:
This bit indicates the position where the next control byte is to be expected. This information is especially important
when using the "MultiSegmentMTU" option.
When using FlatStream communication with multi-segment MTUs, the next control byte is no longer expected in
the first Rx byte of the subsequent MTU, but directly after the current segment.
MessageEndBit:
The "MessageEndBit" is set if the subsequent segment completes a message. The message has then been com-
pletely transmitted and is ready for further processing.

Information:
In the output direction, this bit must also be set if one individual segment is enough to hold the entire
message. The module will only process a message internally if this identifier is detected.
The size of the message being transmitted can be calculated by adding all of the message's segment
lengths together.
FlatStream formula for calculating message length:
Message [bytes] = SegmentLengths (all CBs without ME) + SegmentLength (of the first CB with CB Control byte
ME) ME MessageEndBit

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OutputSequence
The "OutputSequence" register contains information about the communication status of the CPU. It is written by
the CPU and read by the module.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Information
0-2 OutputSequenceCounter 0-7 Counter for the sequences issued in the output direction
3 OutputSyncBit 0 Output direction disabled
1 Output direction enabled
4-6 InputSequenceAck 0-7 Mirrors the InputSequenceCounter value
7 InputSyncAck 0 Input direction not ready (disabled)
1 Input direction ready (enabled)

OutputSequenceCounter:
The OutputSequenceCounter is a continuous counter of sequences that have been issued by the CPU. The CPU
uses the OutputSequenceCounter to direct the module to accept a sequence (the output direction must be syn-
chronized when this happens).
OutputSyncBit:
The CPU uses the OutputSyncBit to attempt to synchronize the output channel.
InputSequenceAck:
InputSequenceAck is used for acknowledgment. The value of the InputSequenceCounter is mirrored if the CPU
has received a sequence successfully.
InputSyncAck:
The InputSyncAck bit acknowledges the synchronization of the input channel for the module. This indicates that
the CPU is ready to receive data.

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InputSequence
The "InputSequence" register contains information about the communication status of the module. It is written by
the module and should only be read by the CPU.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Information
0-2 InputSequenceCounter 0-7 Counter for sequences issued in the input direction
3 InputSyncBit 0 Not ready (disabled)
1 Ready (enabled)
4-6 OutputSequenceAck 0-7 Mirrors the OutputSequenceCounter value
7 OutputSyncAck 0 Not ready (disabled)
1 Ready (enabled)

InputSequenceCounter:
The InputSequenceCounter is a continuous counter of sequences that have been issued by the module. The
module uses the InputSequenceCounter to direct the CPU to accept a sequence (the input direction must be
synchronized when this happens).
InputSyncBit:
The module uses the InputSyncBit to attempt to synchronize the input channel.
OutputSequenceAck:
OutputSequenceAck is used for acknowledgment. The value of the OutputSequenceCounter is mirrored if the
module has received a sequence successfully.
OutputSyncAck:
The OutputSyncAck bit acknowledges the synchronization of the output channel for the CPU. This indicates that
the module is ready to receive data.

Relationship between OutputSequence and InputSequence

Output sequence Input sequence

Communication status of CPU Communication status of module

0-2 OutputSequenceCounter 0-2 InputSequenceCounter

3 OutputSyncBit Intersecting 3 InputSyncBit

4-6 InputSequenceAck Handshakes 4-6 OutputSequenceAck

7 InputSyncAck 7 OutputSyncAck

Figure 75: Relationship between OutputSequence and InputSequence

The OutputSequence and InputSequence registers are logically composed of two half-bytes. The low part signals
to the opposite station whether a channel should be opened or if data should be accepted. The high part is to
acknowledge that the requested action was carried out.
SyncBit and SyncAck:
If SyncBit and SyncAck are set in one communication direction, then the channel is considered "synchronized", i.e.
it is possible to send messages in this direction. The status bit of the opposite station must be checked cyclically.
If SyncAck has been reset, then the SyncBit must be adjusted on that station. Before new data can be transmitted,
the channel needs to be resynchronized.
SequenceCounter and SequenceAck:
The communication partners cyclically check whether the low nibble on the opposite station changes. When one
of the communication partners finishes writing a new sequence to the MTU, it increments its SequenceCounter.
The current sequence is then transmitted to the receiver, which acknowledges its receipt with SequenceAck. In
this way, a "handshake" is initiated.

Information:
If communication is interrupted, segments from the unfinished message are discarded. All messages
that were transmitted completely are processed.

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Synchronization

During synchronization, a communication channel is opened. It is important to make sure that a module is present
and that the current value of the SequenceCounter is stored on the station receiving the message.
FlatStream can handle full-duplex communication. This means that both channels / communication directions can
be handled separately. They have to be synchronized independently so that simplex communication can theoret-
ically be carried out as well.

Synchronization in the output direction (CPU as the transmitter):

The corresponding synchronization bits (OutputSyncBit and OutputSyncAck) are reset. Because of this, FlatStream
cannot be used at this point in time to send messages from the CPU to the module.
Algorithm:
1.) The CPU must write 000 to the OutputSequenceCounter and reset the OutputSyncBit.
The CPU must cyclically query the high nibble of the "InputSequence" register (checks for 000 in OutputSequenceAck and 0 in OutputSyncAck).
The module does not accept the current contents of the InputMTU since the channel is not yet synchronized.
The module matches OutputSequenceAck and OutputSyncAck to the values of the OutputSequenceCounter and OutputSyncBit.
2.) If the CPU registers the expected values in OutputSequenceAck and OutputSyncAck, it is allowed to increment the OutputSequenceCounter.
The CPU continues cyclically querying the high nibble of the "OutputSequence" register (checks for 001 in OutputSequenceAck and 0 in InputSyncAck).
The module does not accept the current contents of the InputMTU since the channel is not yet synchronized.
The module matches OutputSequenceAck and OutputSyncAck to the values of the OutputSequenceCounter and OutputSyncBit.
3.) When the CPU registers the expected values in OutputSequenceAck and OutputSyncAck, it is allowed to increment the OutputSequenceCounter.
The CPU continues cyclically querying the high nibble of the "OutputSequence" register (checks for 001 in OutputSequenceAck and 1 in InputSyncAck).
Note:
Theoretically, data can be transmitted from this point forward. However, it is still recommended to wait until the output direction is completely synchronized be-
fore transmitting data.
The module sets OutputSyncAck.
The output direction is synchronized, and the CPU can transmit data to the module.

Synchronization in the input direction (CPU as the receiver):

The corresponding synchronization bits (InputSyncBit and InputSyncAck) are reset. Because of this, FlatStream
cannot be used at this point in time to send messages from the module to the CPU.
Algorithm:
The module writes 000 to the InputSequenceCounter and resets the InputSyncBit.
The module monitors the high nibble of the "OutputSequence" register and expects 000 in InputSequenceAck and 0 in InputSyncAck.
1.) The CPU is not allowed to accept the current contents of the InputMTU since the channel is not yet synchronized.
The CPU has to match InputSequenceAck and InputSyncAck to the values of InputSequenceCounter and InputSyncBit.
If the module registers the expected values in InputSequenceAck and InputSyncAck, it increments the InputSequenceCounter.
The module monitors the high nibble of the "OutputSequence" registers and expects 001 in InputSequenceAck and 0 in InputSyncAck.
2.) The CPU is not allowed to accept the current contents of the InputMTU since the channel is not yet synchronized.
The CPU has to match InputSequenceAck and InputSyncAck to the values of InputSequenceCounter and InputSyncBit.
If the module registers the expected values in InputSequenceAck and InputSyncAck, it sets the InputSyncBit.
The module monitors the high nibble of the "OutputSequence" register and expects 1 in InputSyncAck.
3.) The CPU is allowed to set InputSyncAck.
Note:
Theoretically, data can already be transmitted in this cycle.
If the InputSyncBit is set and InputSequenceCounter has been increased by 1, the values in the enabled Rx bytes have to be accepted and acknowledged (see
also "Communication in the input direction").
The input direction is synchronized, and the module can transmit data to the CPU.

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Transmitting and receiving

If a channel is synchronized, then the opposite station is ready to receive messages from the transmitter. Before
the transmitter can send data, it needs to first create a transmit array in order to meet FlatStream requirements.
The transmitting station must also generate a control byte for each segment created. This control byte contains
information about how the subsequent part of the data being transmitted should be processed. The position of the
next control byte in the data stream can vary. For this reason, it must be clearly defined at all times when a new
control byte is being transmitted. The first control byte is always in the first byte of the first sequence. All subsequent
positions are determined recursively.
FlatStream formula for calculating the position of the next control byte:
Position (of the next control byte) = Current position + 1 + Segment length
Example:
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The rest of the configuration corresponds to the default settings.
Message 1: Transmit/Receive array

With 7 USINT elements according to

the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Default
Message 2:

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cyc. 1

B1 B2

C2 A7 - - - - - Sequence for bus cyc. 2

Message 3:
C3 B1 B2 - - - - Sequence for bus cyc. 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C4 D1 D2 D3 D4 D5 D6 Sequence for bus cyc. 4

No more data to transmit C5 D7 D8 D9 - - - Sequence for bus cyc. 5

- - - ... C0 - - - - - - Sequence for bus cyc. 6

Figure 76: Transmit/Receive array (default)

First, the messages must be split into segments. In the default configuration, it is important to ensure that each
sequence can hold an entire segment, including the associated control byte. The sequence is limited to the size of
the enable MTU. In other words, a segment must be at least 1 byte smaller than the MTU.
MTU = 7 bytes → Max. segment length = 6 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 6 bytes of data

➯ Second segment = Control byte + 1 byte of data
• Message 2 (2 bytes)

➯ First segment = Control byte + 2 bytes of data

• Message 3 (9 bytes)

➯ First segment = Control byte + 6 bytes of data

➯ Second segment = Control byte + 3 data bytes
• No more messages

➯ C0 control byte

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A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C0 (control byte 0) C1 (control byte 1) C2 (control byte 2)
- SegmentLength (0) = 0 - SegmentLength (6) = 6 - SegmentLength (1) = 1
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (0) = 0 - MessageEndBit (0) = 0 - MessageEndBit (1) = 128
Control byte Σ 0 Control byte Σ 6 Control byte Σ 129

Table 44: FlatStream determination of the control bytes for the default configuration example (part 1)
C3 (control byte 3) C4 (control byte 4) C5 (control byte 5)
- SegmentLength (2) = 2 - SegmentLength (6) = 6 - SegmentLength (3) = 3
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (1) = 128 - MessageEndBit (0) = 0 - MessageEndBit (1) = 128
Control byte Σ 130 Control byte Σ 6 Control byte Σ 131

Table 45: FlatStream determination of the control bytes for the default configuration example (part 2)

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Transmitting data to a module (output)

When transmitting data, the transmit array must be generated in the application program. Sequences are then
transmitted one by one using FlatStream and received by the module.

Information:
Although all B&R modules with FlatStream communication always support the most compact trans-
missions in the output direction, it is recommended to use the same design for the transfer arrays in
both communication directions.

PLC / Bus controller Module

Module-internal Module-internal
Transmit array OutputMTU Receive buffer Receive array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 TxBytes Cyc. *RxBytes _data_01

_data_02 _data_02
If OutputMTU The transmit buffer If the OutputSequence-
_data_03 is enabled: on the module is counter is incremented: _data_03
adapted cyclically to
_data_04 CPU fills OutputMTU via X2X Module adds the transmit buffer _data_04
OutputMTU with . to the internal array
_data_05 the next
_data_05
... sequence from the If successful: ...
Transmit array InputSequenceAck is
_data_xx adapted to the _data_xx
transmit array.

Figure 77: FlatStream communication (output)

The length of the message is initially smaller than the OutputMTU. In this case, one sequence would be sufficient
to transmit the entire message and the necessary control byte.
Algorithm:
Cyclic status query:
- The Module monitors the OutputSequenceCounter.
0. Cyclic checks:
- The CPU must check OutputSyncAck.
→ If OutputSyncAck = 0: Reset the OutputSyncBit and resynchronize the channel.
- The CPU must check whether OutputMTU is enabled.
→ If OutputSequenceCounter > InputSequenceAck: MTU is not enabled because the last sequence has not yet been acknowledged.
1. Preparation (create transmit array):
- The CPU must split up the message into valid segments and create the necessary control bytes.
- The CPU must add the segments and control bytes to the transmit array.
2. Transmitting:
- The CPU transfers the current element of the transmit array to the OutputMTU.
→ The OutputMTU is transferred cyclically to the module's transmit buffer but not processed further.
- The CPU must increase the OutputSequenceCounter.
Response:
- The module accepts the bytes from the internal receive buffer and adds them to the internal receive array.
- The module sends acknowledgment and writes the value of the OutputSequenceCounter to OutputSequenceAck.
3. Completion:
- The CPU must monitor OutputSequenceAck.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via OutputSequenceAck. In order to detect potential trans-
mission errors in the last sequence as well, it is important to make sure that the length of the Completion phase is run through long enough.
Note:
To monitor communication times exactly, the task cycles that have passed since the last increase of the OutputSequenceCounter should be counted. In this
way, the number of previous bus cycles necessary for the transmission can be measured. If the monitoring counter exceeds a predefined threshold, then the
sequence can be considered lost.
(The relationship of bus to task cycle can be influenced by the user so that the threshold value needs to be determined individually.)
- Subsequent sequences can only be transmitted in the next bus cycle after the completion check has been carried out successfully.

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Message larger than the OutputMTU:

The transmit array, which needs to be created in the program sequence, consists of several elements. The user
has to arrange the control and data bytes correctly and transfer the array elements one after the other. The transfer
algorithm remains the same and is repeated starting at the point Cyclic checks.
General flow chart:

Start

► diff = (OutputSequenceCounter -
OutputSequenceAck) AND 7
► limit = (OutputSequenceCounter -
LastValidAck) AND 7

(diff <= limit)

No OutputSequenceAck = No LastValidAck = Yes
AND (OutputSyncAck = 1)
AND (OutputSyncBit = 1) ? OutputSequenceCounter? OutputSequenceCounter?

Yes Yes No

No LastValidAck =
diff = 0?
OutputSequenceAck

Yes

LastValidAck = No
OutputSequenceAck = 0?
OutputSequenceAck

Yes

No OutputSequenceCounter = 0
More sequences to be sent? OutputSequenceCounter = 1 OutputSyncBit = 1
LastValidAck = 0

Yes

Copy next sequence to MTU

Increase OutputSequenceCounter

Sequence handling Synchronization

Figure 78: Flow chart for the output direction

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Receiving data from a module (input)

When receiving data, the transmit array is generated by the module, transferred via FlatStream and must then
be reproduced in the receive array. The structure of the incoming data stream can be configured with the mode
register. The algorithm for receiving the data does not change in this regard.
PLC / Bus controller Module
Module-internal Module-internal
Receive array InputMTU Send buffer Transmit array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 RxBytes Cyc. *TxBytes _data_01

_data_02 _data_02
If the InputMTU is If permitted:
_data_03 InputSequence- adapted cyclically Module fills the internal _data_03
counter is incremented: to the receive buffer transmit buffer with the
_data_04 via X2X next sequence _data_04
InputMTU must of the transmit array
_data_05 be added to the
_data_05
... receive array Module increments the ...
(Increase InputSequenceAck InputSequence counter
_data_xx to finish correctly) _data_xx

Figure 79: FlatStream communication (input)

Algorithm:
0. Cyclic status query:
- The CPU must monitor the InputSequenceCounter.
Cyclic checks:
- The module checks InputSyncAck.
- The module checks InputSequenceAck.
Preparation:
- The module forms the segments and control bytes and creates the transmit array.
Action:
- The module transfers the current element of the internal transmit array to the internal transmit buffer.
- The module increases the InputSequenceCounter.
1. Receiving (as soon as InputSequenceCounter is increased):
- The CPU must accept data from the InputMTU and append it to the end of the receive array.
- The CPU must match InputSequenceAck to the InputSequenceCounter of the sequence currently being processed.
Completion:
- The module monitors InputSequenceAck.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via InputSequenceAck .
- Subsequent sequences are only transmitted in the next bus cycle after the completion check has been carried out successfully.

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General flow chart:

Start

► InputSequenceAck = InputSequenceCounter

Synchronization
No
InputSyncBit = 1? ► RemainingSegmentSize = 0
► SegmentFlags = 0
Yes

No No
InputSyncAck = 1? InputSequenceAck > 0?

Yes Yes

MTU_Offset = 0 InputSyncAck = 1

(InputSequenceCounter – No
InputSequenceAck)
AND 0x07 = 1?

Yes
► RemainingSegmentSize =
Yes MTU_Data[MTU_Offset] AND 0b0011 1111
RemainingSegmentSize = 0? ► SegmentFlags =
MTU_Data[MTU_Offset] AND 0b1100 0000
No ► MTU_Offset = MTU_Offset + 1

Yes RemainingSegmentSize > No

(InputMTU_Size – MTU_Offset)?

Segment data handling

► DataSize = InputMTU_Size – MTU_Offset ► DataSize = RemainingSegmentSize

► copy segment data e.g. memcpy(xxx, ADR(MTU_Data[MTU_Offset]), DataSize)

► MTU_Offset = MTU_Offset + DataSize
► RemainingSegmentSize = RemainingSegmentSize - DataSize

RemainingSegmentSize = 0 AND Yes

► Mark frame as complete
(SegmentFlags AND 0x80) = 0?

No

RemainingSegmentSize = 0 AND Yes

(SegmentFlags AND 0x40) = 0?

No

Yes
► InputSequenceAck =
InputMTU_Size = MTU_Offset?
InputSequenceCounter

No

Figure 80: Flow chart for the input direction

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Details

It is recommended to store transmitted messages in separate receive arrays.

After a set MessageEndBit is transmitted, the subsequent segment should be added to the receive array. The
message is then complete and can be passed on internally for further processing. A new/separate array should
be created for the next message.

Information:
When transmitting with MultiSegmentMTUs, it is possible for several small messages to be part of one
sequence. In the program, it's important to make sure that a sufficient number of receive arrays can
be managed. The entire sequence must be accepted before it is possible to change the Acknowledge
register.
If a SequenceCounter is incremented by more than one value, then an error has occurred (this situation is very
unlikely when operating without "Forward" functionality).
In this case, the receiver stops. All additional incoming sequences are ignored until the transmission with the correct
SequenceCounter is retried. This response prevents the transmitter from receiving any more acknowledgments for
transmitted sequences. The transmitter can identify the last successfully transmitted sequence from the opposite
station's SequenceAck and continue the transmission from this point.
Acknowledgments must be checked for validity.
If the receiver has successfully accepted a sequence, it must be acknowledged. The receiver takes on the Se-
quenceCounter value sent along with the transmission and matches the SequenceAck to it. The transmitter reads
the SequenceAck and registers the successful transmission. If the transmitter acknowledges a sequence that has
not yet been dispatched, then the transmission needs to be interrupted and the channel resynchronized. The syn-
chronization bits are reset and the current/incomplete message is discarded. It needs to be sent again once the
channel has been resynchronized.

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FlatStream mode register

In the input direction, the transmit array is generated automatically. This register offers two options to the user
that allow an incoming data stream to have a more compact arrangement. Once enabled, the program code for
evaluation must be adapted accordingly.

Information:
All B&R modules that offer FlatStream mode support the options "Large segments" and "MultiSeg-
mentMTUs" in the output direction. Compact transmission only needs to be explicitly allowed in the
input direction.
Bit structure:
Bit Name Information
0 MultiSegmentMTU 0 Not allowed (default)
1 Allowed
1 Large segments 0 Not allowed (default)
1 Allowed
2-7 Reserved

Default:
By default, both options relating to compact transmission in the input direction are disabled.
1. The module only forms segments that are at least one byte smaller than the enabled MTU. Each sequence
begins with a control byte so that the data stream is clearly structured and relatively easy to evaluate.
2. Since a FlatStream message can be of any length, the last segment of the message frequently doesn't fill up
all of the MTU's space. By default, the remaining bytes during this type of transfer cycle are not used.

Bus cycle 1 Bus cycle 2 Bus cycle 3

C C C
- - -
ME0 ME1 ME1

Segment 1 Segment 2 Segment 3

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 81: Message arrangement in the MTU (default)

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MultiSegmentMTUs allowed:
With this option, the InputMTU is completely filled (if enough data is pending). The previously unfilled Rx bytes
transmit the next control bytes and their segments. This allows the enabled Rx bytes to be used more efficiently.

Bus cycle 1 Bus cycle 2 Bus cycle 3

C C C C
- -
ME0 ME1 ME0 ME1

Segment 1 Segment 2 3 Segment 4

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 82: Arrangement of messages in the MTU (MultiSegmentMTUs)

Large segments allowed:
When transmitting very long messages or when enabling only very few Rx bytes, then a great many segments must
be created by default. The bus system is more stressed than necessary since an additional control byte needs to
be created and transmitted for each segment. With the "Large segments" option, the segment length is limited to
63 bytes independently of the InputMTU. One segment can stretch across several sequences, i.e. it is possible for
"pure" sequences to occur without a control byte.

Information:
It is still possible to split up a message into several segments, however. If this option is used and
messages with more than 63 bytes occur, for example, then messages can still be split up among
several segments.

Bus cycle 1 Bus cycle 2 Bus cycle 3

C C
- - - -
ME1 ME1

Segment 1 Segment 2 Segment 3

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 83: Arrangement of messages in the MTU (large segments)

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Using both options:

It is also possible to use both options at the same time.

Bus cycle 1 Bus cycle 2 Bus cycle 3

C C
- - - -
ME1 ME1

Segment 1 Segment 2 Segment 3

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 84: Arrangement of messages in the MTU (large segments and MultiSegmentMTUs)

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FlatStream adjustment

If the way messages are structured is changed, then the way data in the transmit/receive array is arranged is also
different. The following changes apply to the example given earlier on.
MultiSegmentMTU:
If MultiSegmentMTUs are allowed, then "open positions" in an MTU can be used. These "open positions" occur if
the last segment in a message doesn't fully use the entire MTU. MultiSegmentMTUs allow these bits to be used
to transmit the following control bytes and segments. In the program sequence, the "nextCBPos" bit in the control
byte is set so that the receiver can correctly identify the next control byte.
Example:
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The configuration allows transmission of MultiSegmentMTUs.
Message 1: Transmit/Receive array

With 7 USINT elements according to

the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Message 2: MultiSegmentMTU

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

C2 A7 C3 B1 B2 C4 D1 Sequence for bus cycle 2

Message 3:
C5 D2 D3 D4 D5 D6 D7 Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C6 D8 D9 C0 - - - Sequence for bus cycle 4

No more data to transmit C0 - - - - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 85: Transmit/receive array (MultiSegmentMTU)

First, the messages must be split into segments. As in the default configuration, it's important for each sequence
to begin with a control byte. The free bits in the MTU at the end of a message are filled with data from the following
message, however. With this option, the "nextCBPos" bit is always set if payload data is sent after the control byte.
MTU = 7 bytes → Max. segment length = 6 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 6 data bytes (MTU full)

➯ Second segment = Control byte + 1 data byte (MTU still has 5 open bytes)
• Message 2 (2 bytes)

➯ First segment = Control byte + 2 data bytes (MTU still has 2 open bytes)
• Message 3 (9 bytes)

➯ First segment = Control byte + 1 data byte (MTU full)

➯ Second segment = Control byte + 6 data bytes (MTU full)
➯ Third segment = Control byte + 2 data bytes (MTU still has 4 open bytes)
• No more messages

➯ C0 control byte

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A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C1 (control byte 1) C2 (control byte 2) C3 (control byte 3)
- SegmentLength (6) = 6 - SegmentLength (1) = 1 - SegmentLength (2) = 2
- nextCBPos (1) = 64 - nextCBPos (1) = 64 - nextCBPos (1) = 64
- MessageEndBit (0) = 0 - MessageEndBit (1) = 128 - MessageEndBit (1) = 128
Control byte Σ 70 Control byte Σ 193 Control byte Σ 194

Table 46: FlatStream determination of the control bytes for example with MultiSegmentMTU (part 1)

Warning!
The second sequence must have been completely processed before it can be acknowledged with Se-
quenceAck. In the example, there are three different segments within the second sequence, i.e. the
program must include enough receive arrays to handle this situation.
C4 (control byte 4) C5 (control byte 5) C6 (control byte 6)
- SegmentLength (1) = 1 - SegmentLength (6) = 6 - SegmentLength (2) = 2
- nextCBPos (6) = 6 - nextCBPos (1) = 64 - nextCBPos (1) = 64
- MessageEndBit (0) = 0 - MessageEndBit (1) = 0 - MessageEndBit (1) = 128
Control byte Σ 7 Control byte Σ 70 Control byte Σ 194

Table 47: FlatStream determination of the control bytes for example with MultiSegmentMTU (part 2)

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Large segments:
Segments are limited to a maximum of 63 bytes. This means they can be larger than the active MTU. These large
segments are divided among several sequences when transmitted. It is possible for sequences to be completely
filled with payload data and not have a control byte.

Information:
It is still possible to subdivide a message into several segments so that the size of a data packet doesn't
also have to be limited to 63 bytes.
Example:
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The configuration allows the transmission of large segments.
Message 1: Transmit/Receive array

With 7 USINT elements according to

the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Message 2: Large segments

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

A7 - - - - - - Sequence for bus cycle 2

Message 3:
C2 B1 B2 - - - - Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C3 D1 D2 D3 D4 D5 D6 Sequence for bus cycle 4

No more data to transmit D7 D8 D9 - - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 86: Transmit/receive array (large segments)

First, the messages must be split into segments. The ability to form large segments means that messages are split
up less frequently, which results in fewer generated control bytes.
Large segments allowed → Max. segment length = 63 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 7 data bytes

• Message 2 (2 bytes)

➯ First segment = Control byte + 2 data bytes

• Message 3 (9 bytes)

➯ First segment = Control byte + 9 data bytes

• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C1 (control byte 1) C2 (control byte 2) C3 (control byte 3)
- SegmentLength (7) = 7 - SegmentLength (2) = 2 - SegmentLength (9) = 9
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (1) = 128 - MessageEndBit (1) = 128 - MessageEndBit (1) = 128
Control byte Σ 135 Control byte Σ 130 Control byte Σ 137

Table 48: FlatStream determination of the control bytes for example with large segments.

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Large segments and MultiSegmentMTU:

Example:
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The configuration allows transmission of large segments as well as MultiSegmentMTUs.
Message 1: Transmit/Receive array
With 7 USINT elements according to
the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Message 2: Both options

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

A7 C2 B1 B2 C3 D1 D2 Sequence for bus cycle 2

Message 3:
D3 D4 D5 D6 D7 D8 D9 Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C0 - - - - - - Sequence for bus cycle 4

No more data to transmit C0 - - - - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 87: Transmit/receive array (large segments and MultiSegmentMTUs)

First, the messages must be split into segments. If the last segment of a message doesn't completely fill the MTU,
it can be used for other data in the data stream. The "nextCBPos" bit must always be set if the control byte belongs
to a segment with payload data.
The ability to form large segments means that messages are split up less frequently, which results in fewer gen-
erated control bytes. Control bytes are generated in the same way as with the "Large segments" option.
Large segments allowed → Max. segment length = 63 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 7 data bytes

• Message 2 (2 bytes)

➯ First segment = Control byte + 2 data bytes

• Message 3 (9 bytes)

➯ First segment = Control byte + 9 data bytes

• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C1 (control byte 1) C2 (control byte 2) C3 (control byte 3)
- SegmentLength (7) = 7 - SegmentLength (2) = 2 - SegmentLength (9) = 9
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (1) = 128 - MessageEndBit (1) = 128 - MessageEndBit (1) = 128
Control byte Σ 135 Control byte Σ 130 Control byte Σ 137

Table 49: FlatStream determination of the control bytes for large segments and MultiSegmentMTU example

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4.3.7.9.9.5 Example of Forward functionality on X2X Link

Forward functionality is a method that can be used to substantially increase the FlatStream data rate. The basic
principle is also used in other technical areas such as "pipelining" for microprocessors.

Operating principle

X2X Link communication cycles through five different steps to transmit a FlatStream sequence. At least five bus
cycles are therefore required to successfully transfer the sequence.
Step I Step II Step III Step IV Step V
Actions Transfer sequence from Cyclic matching of MTU and Append sequence to re- Cyclic matching of Check SequenceAck
transmit array, module buffer ceive array MTU and module buffer
increase Sequence- Adjust SequenceAck
Counter
Resource Sender Bus system Recipient Bus system Sender
(task to transmit) (direction 1) (task to receive) (direction 2) (task for Ack checking)

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 ...

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Figure 88: Comparison of transmission without/with Forward

Each of the five steps (tasks) requires different resources. If Forward functionality is not used, the sequences are
executed one after the other. Each resource is then only active if it is needed for the current sub-action.
With Forward, a resource that has executed its task can already be used for the next message. The condition for
enabling the MTU is changed to allow for this. Sequences are then passed to the MTU according to the timing. The
transmitting station no longer waits for an acknowledgment from SequenceAck, which means that the available
bandwidth can be used much more efficiently.
In the most ideal situation, all resources are working during each bus cycle. The receiver still has to acknowledge
every sequence received. Only when SequenceAck has been changed and checked by the transmitter is the
sequence considered as having been transmitted successfully.

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Configuration

The Forward function only has to be enabled for the input direction. Two additional configuration registers are
available for doing so. FlatStream modules have been optimized in such a way that they support this function. In
the output direction, the Forward function can be used as soon as the size of the OutputMTU is specified.
Forward:
With the "Forward" register, the user specifies how many unacknowledged sequences the module is allowed to
transmit.
Recommendation:
X2X Link: Max. 5
POWERLINK: Max. 7
Data type Value
USINT 1...7
Default: 1

ForwardDelay:
The "ForwardDelay" register is used to specify the delay time in µs. This is the amount of time the module has
to wait after sending a sequence until it is allowed to write new data to the MTU in the following bus cycle. The
program routine for receiving sequences from a module can therefore be run in a task class whose cycle time is
slower than the bus cycle.
Data type Values [µs]
UINT 0...65535
Default: 0

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Figure 89: Effect of ForwardDelay when using FlatStream communication with the Forward function
In the program, it is important to make sure that the CPU is processing all of the incoming InputSequences and In-
putMTUs. The ForwardDelay value causes delayed acknowledgment in the output direction and delayed reception
in the input direction. In this way, the CPU has more time to process the incoming InputSequence or InputMTU.

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Transmitting and receiving with Forward

The basic algorithm for transmitting and receiving data remains the same. With the Forward function, up to seven
unacknowledged sequences can be transmitted. Sequences can be transmitted without having to wait for the
previous message to be acknowledged. Since the delay between writing and response is eliminated, a considerable
amount of additional data can be transferred in the same time window.
Algorithm for transmitting:
Cyclic status query:
- The Module monitors the OutputSequenceCounter.
0. Cyclic checks:
- The CPU must check OutputSyncAck.
→ If OutputSyncAck = 0: Reset the OutputSyncBit and resynchronize the channel.
- The CPU must check whether OutputMTU is enabled.
→ If OutputSequenceCounter > OutputSequenceAck + 7, then it is not enabled because the last sequence has not yet been acknowledged.
1. Preparation (create transmit array):
- The CPU must split up the message into valid segments and create the necessary control bytes.
- The CPU must add the segments and control bytes to the transmit array.
2. Transmitting:
- The CPU must transfer the current part of the transmit array to the OutputMTU.
- The CPU must increase the OutputSequenceCounter for the sequence to be accepted by the module.
- The CPU can then transmit in the next bus cycle if the MTU has been enabled.
The module responds since OutputSequenceCounter > OutputSequenceAck:
- The module accepts data from the internal receive buffer and appends it to the end of the internal receive array.
- The module is acknowledged and the currently received value of the OutputSequenceCounter is transferred to OutputSequenceAck.
- The module requests the status cyclically again.
3. Completion (acknowledgment):
- The CPU must check OutputSequenceAck cyclically.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via OutputSequenceAck. In order to detect potential trans-
mission errors in the last sequence as well, it is important to make sure that the algorithm is run through long enough.
Note:
To monitor communication times exactly, the task cycles that have passed since the last increase of the OutputSequenceCounter should be counted. In this
way, the number of previous bus cycles necessary for the transmission can be measured. If the monitoring counter exceeds a predefined threshold, then the
sequence can be considered lost (the relationship of bus to task cycle can be influenced by the user so that the threshold value needs to be determined individ-
ually).

Algorithm for receiving:

0. Cyclic status query:
- The CPU must monitor the InputSequenceCounter.
Cyclic checks:
- The module checks InputSyncAck.
- The module checks if InputMTU is enabled.
→ Enabling criteria: InputSequenceCounter > InputSequenceAck + Forward
Preparation:
- The module forms the control bytes / segments and creates the transmit array.
Action:
- The module transmits the current part of the transmit array to the receive buffer.
- The module increases the InputSequenceCounter.
- The module waits for a new bus cycle after the ForwardDelay time has expired.
- The module repeats the action if the InputMTU is enabled.
1. Receiving (InputSequenceCounter > InputSequenceAck):
- The CPU must accept data from the InputMTU and append it to the end of the receive array.
- The CPU must match InputSequenceAck to the InputSequenceCounter of the sequence currently being processed.
Completion:
- The module monitors InputSequenceAck.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via InputSequenceAck .

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Details/Background:
1. Illegal SequenceCounter size (counter offset)
Error situation: MTU not enabled
If the difference between SequenceCounter and SequenceAck is larger than allowed during transmission,
then a transmission error has occurred. In this case, all unacknowledged sequences must be repeated with
the old SequenceCounter value.
2. Checking an acknowledgment
After an acknowledgment has been received, a check must verify whether the acknowledged sequence has
been transmitted and had not yet been unacknowledged. If a sequence has been acknowledged more than
once, then a fatal error has occurred. The channel must be closed and resynchronized (same behavior as
when not using Forward).

Information:
In exceptional cases, the module can increment OutputSequenceAck by more than 1 when using
Forward.
This is not an error. The CPU is permitted to consider all sequences up to the one being acknowl-
edged as having been transmitted successfully.

3. Transmit and receive arrays

The Forward function has no effect on the structure of the transmit and receive arrays. They are created and
must be evaluated in the same way.

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Errors when using Forward

In industrial environments, it is often the case that many different devices from various manufacturers are being
used side by side. The electrical and/or electromagnetic properties of these technical devices can sometimes cause
them to interfere with one another. These kinds of situations can be reproduced and protected against in laboratory
conditions only to a certain point.
Precautions have been taken for X2X Link transmissions if this type of interference occurs. For example, if an
invalid checksum occurs, the I/O system will ignore the data from this bus cycle and the receiver will receive the
last valid data once more. With conventional (cyclic) data points, this error can often be ignored. In the following
cycle, the same data point is again retrieved, adjusted and transmitted.
Using Forward functionality with FlatStream communication makes this situation more complex. The receiver re-
ceives the old data again in this situation as well, i.e. the previous values for SequenceAck/SequenceCounter and
the old MTU.
Loss of acknowledgment (SequenceAck):
If a SequenceAck value is lost, then the MTU was already transmitted properly. For this reason, the receiver is per-
mitted to continue processing with the next sequence. The SequenceAck is aligned with the associated Sequence-
Counter and sent back to the transmitter. Checking the incoming acknowledgments shows that all sequences up
to the last one acknowledged have been transmitted successfully (see sequences 1 and 2 in the image).
Loss of transmission (SequenceCounter, MTU):
If a bus cycle drops out and the SequenceCounter value and/or filled MTU are lost, then no data reaches the
receiver. At this point, the transmission routine is not yet affected by the error. The time-controlled MTU is released
again and can be rewritten to. The receiver receives SequenceCounter values that have been incremented several
times. For the receive array to be put together correctly, the receiver is only allowed to process transmissions
whose SequenceCounter has been increased by one. The incoming sequences must be ignored, i.e. the receiver
stops and no longer transmits back any acknowledgments. If the maximum number of unacknowledged sequences
has been sent and no acknowledgments are returned, the transmitter must repeat the affected SequenceCounter
and associated MTUs (see sequence 3 and 4 in the image).

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Sequence 4 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Sequence 1 Step I Step II Step III

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step I Step II Step III

Sequence 4 Step I Step II Step I Step II

Bus cycle 1 Bus cycle 2 Bus cycle 3 EMC Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Figure 90: Effect of a lost bus cycle

Loss of acknowledgment:
In sequence 1, the acknowledgment is lost due to disturbance. Sequences 1 and 2 are therefore acknowledged
in Step V of sequence 2.
Loss of transmission:
In sequence 3, the entire transmission is lost due to disturbance. The receiver stops and no longer sends back
any acknowledgments.
The sending station continues transmitting until it has issued the maximum permitted number of unacknowledged
transmissions.
Five bus cycles later at the earliest (depending on the configuration), it begins resending the unsuccessfully sent
transmissions.

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4.3.7.9.10 HART with FlatStream

When using FlatStream communication, the module acts as a bridge between the X2X master and an intelligent
field device connected to the module. FlatStream mode can be used for either point-to-point connections as well
as for multidrop systems. Specific algorithms such as timeout and checksum monitoring are usually managed
automatically. During normal operation, the user does not have access to these details.
HART is considered a master-slave network where half-duplex communication takes place asynchronously. Vari-
ous features have been included to ensure that signals are transmitted without errors.
For example, the user can increase the length of the preamble, thus making the transmission more secure. How-
ever, this also has an effect on the percentage of payload data and overhead.
Additional information about HART can be found at http://www.HARTcomm.org.

Operation
The module has two independent channels. When using FlatStream, the channel number must therefore be spec-
ified. The general structure of a FlatStream frame is extended as follows.
Input/Output sequence Tx/Rx bytes
(Unchanged) Control byte Channel number HART frame
(unchanged) (without preamble and checksum)

HART frame with FlatStream

Start ADDR CMD BCNT (STS) (DATA)

Start Start delimiter

ADDR Address within HART network
CMD HART command
BCNT Byte counter (number of remaining bytes)
*STS State of last received command, information about operation mode of HART slave and communication errors
(feedback from HART slave, if supported by HART slave)
*DATA Data (if required according to command)

Examples of HART commands

Command Description
0x00 Read slave ID
0x03 Read current value and up to four variables
0x09 Read up to four variables including status
0x21 Read variables

4.3.7.9.11 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without causing a communication error
or impaired functionality. It should be noted that very fast cycles decrease the idle time available for handling
monitoring, diagnostics and acyclic commands.
Minimum cycle time
200 μs

4.3.7.9.12 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Analog inputs 1 ms

Minimum I/O update time for HART communication

Point-to-point 500 ms
Multidrop Number of stations * 1000 ms

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4.3.8 X20AI2622

4.3.8.1 General information

The module is equipped with 2 inputs with 13-bit (including sign) digital converter resolution. It is possible to select
between the current and voltage signal using different connection terminal points.
This module is designed for X20 6-pin terminal blocks. If needed (e.g. for logistical reasons), the 12-pin terminal
block can also be used.
• 2 analog inputs
• Either current or voltage signal possible
• 13-bit digital converter resolution

4.3.8.2 Order data

Model number Short description Figure

Analog input modules
X20AI2622 X20 analog input module, 2 inputs, ±10 V or 0 to 20 mA / 4 to 20
mA, 13-bit resolution, configurable input filter
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 50: X20AI2622 - Order data

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4.3.8.3 Technical data

Product ID X20AI2622
Short description
I/O module 2 analog inputs ±10 V or 0 to 20 mA / 4 to 20 mA
General information
B&R ID code 0x1B9E
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Inputs Yes, using status LED and software
Channel type Yes, using software
Power consumption
Bus 0.01 W
Internal I/O 0.8 W 1)
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Analog inputs
Input ±10 V or 0 to 20 mA / 4 to 20 mA, via different connection terminal points
Input type Differential input
Digital converter resolution
Voltage ±12-bit
Current 12-bit
Conversion time 300 µs for all inputs
Output format INT
Output format
Voltage INT 0x8001 - 0x7FFF / 1 LSB = 0x0008 = 2.441 mV
Current INT 0x0000 - 0x7FFF / 1 LSB = 0x0008 = 4.883 µA
Input impedance in signal range
Voltage 20 MΩ
Current -
Load
Voltage -
Current <400 Ω
Input protection Protection against wiring with supply voltage
Permitted input signal
Voltage Max. ±30 V
Current Max. ±50 mA
Output of the digital value during overload
Below lower limit
Voltage 0x8001
Current 0x0000
Above upper limit
Voltage 0x7FFF
Current 0x7FFF
Conversion procedure SAR
Input filter 3rd-order low pass / cutoff frequency 1 kHz
Max. error at 25°C
Voltage
Gain 0.08% 2)
Offset 0.015% 3)
Current
Gain 0 to 20 mA = 0.08% / 4 to 20 mA = 0.1% 2)
Offset 0 to 20 mA = 0.03% / 4 to 20 mA = 0.16% 4)
Max. gain drift
Voltage 0.006 %/°C 2)
Current 0 to 20 mA = 0.009 %/°C
4 to 20 mA = 0.0113 %/°C 2)
Max. offset drift
Voltage 0.002 %/°C 3)
Current 0 to 20 mA = 0.004 %/°C
4 to 20 mA = 0.005 %/°C 4)
Common-mode rejection
DC 70 dB
50 Hz 70 dB
Common-mode range ±12 V

Table 51: X20AI2622 - Technical data

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Product ID X20AI2622
Crosstalk between channels <-70 dB
Non-linearity
Voltage <0.025% 3)
Current <0.05% 4)
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 51: X20AI2622 - Technical data

1) To reduce power dissipation, B&R recommends bridging unused inputs on the terminals or configuring them as current signals.
2) Based on the current measured value.
3) Based on the 20 V measurement range.
4) Based on the 20 mA measurement range.

4.3.8.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
e+r Red on / Green single flash Invalid firmware
1-2 Green Off Open line1) or sensor is disconnected
Blinking Input signal overflow or underflow
On Analog/digital converter running, value OK

Table 52: LED status indicators

1) Open line detection only possible when measuring voltage.

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4.3.8.5 Pinout

r e

X20 AI 2622
1 2

AI + 1 I AI + 2 I

AI + 1 U AI + 2 U

AI - 1 U/I AI - 2 U/I

Figure 91: Pinout

4.3.8.6 Connection example

Voltage Current
measurement measurement

+24 VDC +24 VDC

GND GND

4.3.8.7 Input circuit diagram

Current/Voltage switching

PTC
AI + x I

Shunt

AI + x U Input value
A/D
converter
I/O status
AI - x U/I

LED (green)

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4.3.8.8 Register description

4.3.8.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 AnalogInput01 INT ●
2 AnalogInput02 INT ●
16 ConfigOutput01 USINT ●
18 ConfigOutput02 USINT ●
20 ConfigOutput03 INT ●
22 ConfigOutput04 INT ●
30 StatusInput01 USINT ●

4.3.8.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 AnalogInput01 INT ●
2 2 AnalogInput02 INT ●
16 - ConfigOutput01 USINT ●
18 - ConfigOutput02 USINT ●
20 - ConfigOutput03 INT ●
22 - ConfigOutput04 INT ●
30 - StatusInput01 USINT ●

1) The offset specifies the position of the register within the CAN object.

4.3.8.8.3 Analog inputs

The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.

4.3.8.8.4 Analog input values

Name:
AnalogInput01 to AnalogInput02
The analog input value are mapped to this register depending on the configured operating mode.
Data type Value Input signal:
INT -32768 to 32767 Voltage signal -10 to 10 VDC
0 to 32767 Current signal 0 to 20 mA

4.3.8.8.5 Input filter

This module is equipped with a configurable input filter. The minimum cycle time must be >500 μs. Filtering is
disabled for shorter cycle times.
If the input filter is active, then the scan rate for the channels is measured in ms. The time offset between the
channels is 200 μs. The conversion takes place asynchronously to the network cycle.

4.3.8.8.5.1 Input ramp limitation

Input ramp limitation can only take place when a filter is used; the input ramp is limited before filtering takes place.
The amount the input value changes is checked to make sure that specified limits are not exceeded. If the values
are exceeded, the adjusted input value is equal to the old value ± the limit value.
Configurable limit values:
Value Limit value
0 The input value is used without limitation.
1 0x3FFF = 16383
2 0x1FFF = 8191
3 0x0FFF = 4095
4 0x07FF = 2047
5 0x03FF = 1023
6 0x01FF = 511
7 0x00FF = 255

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Input ramp limitation is well suited for suppressing disturbances (spikes). The following examples show the function
of the input ramp limitation based on an input jump and a disturbance.
Example 1
The input value jumps from 8,000 to 17,000. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

17000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 92: Adjusted input value for input jump

Example 2
A disturbance interferes with the input value. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 93: Adjusted input value for disturbance

4.3.8.8.5.2 Filter level

A filter can be defined to prevent large input jumps. This filter is used to bring the input value closer to the actual
analog value over a period of several bus cycles.
Filtering takes place after input ramp limitation.
Formula for calculating the input value:
Value Old Input value
Value New = Value Old - +
Filter level Filter level

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Adjustable filter levels:

Value Filter level
0 Filter switched off
1 Filter level 2
2 Filter level 4
3 Filter level 8
4 Filter level 16
5 Filter level 32
6 Filter level 64
7 Filter level 128

The following examples show how filtering works in the event of an input jump or disturbance.
Example 1
The input value jumps from 8,000 to 16,000. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 94: Calculated value during input jump

Example 2
A disturbance interferes with the input value. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 95: Calculated value during disturbance

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4.3.8.8.6 Configuring the input filter

Name:
ConfigOutput01
This register is used to define the filter level and input ramp limitation of the input filter.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-2 Defines the filter level 000 Filter switched off
001 Filter level 2
010 Filter level 4
011 Filter level 8
100 Filter level 16
101 Filter level 32
110 Filter level 64
111 Filter level 128
3 Reserved 0
4-6 Defines the input ramp limitation 000 The input value is used without limitation
001 Limit value = 0x3FFF (16383)
010 Limit value = 0x1FFF (8191)
011 Limit value = 0x0FFF (4095)
100 Limit value = 0x07FF (2047)
101 Limit value = 0x03FF (1023)
110 Limit value = 0x01FF (511)
111 Limit value = 0x00FF (255)
7 Reserved 0

4.3.8.8.7 Channel type

Name:
ConfigOutput02
This register can be used to define the type and range of signal measurement.
Each channel is capable of handling either current or voltage signals. This differentiation is made using multiple
connection terminal points and an integrated switch in the module. The switch is automatically activated by the
module depending on the specified configuration. The following input signals can be set:
• ±10 V voltage signal (default)
• 0 to 20 mA current signal
• 4 to 20 mA current signal
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Channel 1 0 Voltage signal
1 Current signal, measurement range corresponding to bit 4
1 Channel 2 0 Voltage signal
1 Current signal, measurement range corresponding to bit 5
2-3 0
4 Channel 1: Current measurement range 0 0 to 20 mA current signal
1 4 to 20 mA current signal
5 Channel 2: Current measurement range 0 0 to 20 mA current signal
1 4 to 20 mA current signal
6-7 0

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4.3.8.8.8 Limit values

The input signal is monitored at the upper and lower limit values. These must be defined according to the operating
mode:
Limit value (default) Voltage signal ±10 V Current signal 0 to 20 mA Current signal 4 to 20 mA
Upper maximum limit value +10 V +32767 (0x7FFF) 20 mA +32767 (0x7FFF) 20 mA +32767 (0x7FFF)
Lower minimum limit value -10 V -32767 (0x8001) 0 mA 01) 4 mA 02)

1) The analog value is limited down to 0.

2) The analog value is limited down to 0 at currents <4 mA. The status bit for the lower limit is set.

Other limit values can be defined if necessary. Limit values are valid for all channels and activated automatically
by writing to the limit value registers. From this point on, the analog values will be monitored and limited according
to the new limits. The results of monitoring are displayed in the status register.
Examples of limit value settings
Application case Limit value settings
Current signal: 4 to 20 mA A negative limit value must be configured in order to measure values <4 mA with a current signal of 4 to
20 mA: 0 mA is equal to a value of -8192 (0xE000).
Mixed voltage and current signal The configured limit values are valid for all channels. Mixed operation (voltage and current signal) there-
fore requires a compromise.
The following configuration has proven effective:
Upper limit = +32767, lower limit = -32767
This makes it possible to also measure negative voltage values. A lower limit value of 0 would limit the
voltage value to 0.
Current signal on all channels All channels are configured for measuring current. The limit value setting in Automation Studio is not
adjusted automatically. That means that +32767 is configured as the upper limit value and -32767 as the
lower limit value. The necessary changes must be made by the user, e.g. lower limit value = 0

4.3.8.8.8.1 Lower limit value

Name:
ConfigOutput03
This register can be used to configure the lower limit for analog values. If the analog value goes below the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
• The default value of -32768 corresponds to the minimum default value of -10 VDC.
• When configured as 0 to 20 mA, this value should be set to 0.
• When configured as 4 to 20 mA, this value can be set to -8192 (corresponds to 0 mA) in order
to display values <4 mA.

Information:
Keep in mind that this setting applies to all channels!

4.3.8.8.8.2 Upper limit value

Name:
ConfigOutput04
This register can be used to configure the upper limit for analog values. If the analog value goes above the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
The default value of 32767 corresponds to the maximum default value of 20 mA or +10 VDC.

Information:
Keep in mind that this setting applies to all channels!

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4.3.8.8.9 Input status

Name:
StatusInput01
This register is used to monitor the module inputs. A change in the monitoring status generates an error message.
The following states are monitored depending on the settings:
Value Voltage signal ±10 V Current signal 0 to 20 mA Current signal 4 to 20 mA
0 No error No error No error
1 Lower limit value exceeded Default setting Lower limit value exceeded
The input value has a lower limit of 0x0000. Un-
derflow monitoring is therefore not necessary.
After lower limit value change
The input value is limited to the configured val-
ue. The status bit is set when the lower limit val-
ue is passed.
2 Upper limit value exceeded Upper limit value exceeded Upper limit value exceeded
3 Open line - -

Data type Value

USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Channel 1 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded
11 Open line
2-3 Channel 2 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded
11 Open line
4-7 Reserved 0

Limiting the analog value

In addition to the status information, the analog value is set to the values listed below by default when an error
occurs. The analog value is limited to the new values if the limit values were changed.
Error status Digital value for error (default values)
Open line +32767 (0x7FFF)
Upper limit value exceeded +32767 (0x7FFF)
Lower limit value exceeded -32767 (0x8001)
Invalid value -32768 (0x8000)

4.3.8.8.10 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Inputs without filtering 100 µs
Inputs with filtering 500 µs

4.3.8.8.11 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Inputs without filtering 300 µs for all inputs
Inputs with filtering 1 ms

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4.3.9 X20AI4222

4.3.9.1 General information

The module is equipped with 4 inputs with 13-bit (including sign) digital converter resolution. It can be used to
capture voltage signals in the range from ±10 V.
• 4 analog inputs ±10 V
• 13-bit digital converter resolution

4.3.9.2 Order data

Model number Short description Figure

Analog input modules
X20AI4222 X20 analog input module, 4 inputs, ±10 V, 13-bit resolution, con-
figurable input filter
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 53: X20AI4222 - Order data

4.3.9.3 Technical data

Product ID X20AI4222
Short description
I/O module 4 analog inputs ±10 V
General information
B&R ID code 0xCAB1
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Inputs Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.1 W 1)
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
GL Yes
GOST-R Yes
Analog inputs
Input ±10 V
Input type Differential input
Digital converter resolution ±12-bit
Conversion time 400 µs for all inputs
Output format
Data type INT
Voltage 0x8001 - 0x7FFF / 1 LSB = 0x0008 = 2.441 mV
Input impedance in signal range 20 MΩ
Input protection Protection against wiring with supply voltage
Permitted input signal Max. ±30 V
Output of the digital value during overload
Below lower limit 0x8001
Above upper limit 0x7FFF
Conversion procedure SAR
Input filter 3rd-order low pass / cutoff frequency 1 kHz

Table 54: X20AI4222 - Technical data

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Product ID X20AI4222
Max. error at 25°C
Gain 0.08% 2)
Offset 0.015% 3)
Max. gain drift 0.006 %/°C 2)
Max. offset drift 0.002 %/°C 3)
Common-mode rejection
DC 70 dB
50 Hz 70 dB
Common-mode range ±12 V
Crosstalk between channels -70 dB
Non-linearity <0.025% 3)
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 54: X20AI4222 - Technical data

1) To reduce power dissipation, B&R recommends bridging unused inputs on the terminals.
2) Based on the current measured value.
3) Based on the 20 V measurement range.

4.3.9.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
e+r Red on / Green single flash Invalid firmware
1-4 Green Off Open line or sensor is disconnected
Blinking Input signal overflow or underflow
On Analog/digital converter running, value OK

Table 55: LED status indicators

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4.3.9.5 Pinout

r e
1 2
3 4

AI + 1 U AI + 2 U

AI - 1 U AI - 2 U

AI + 3 U AI + 4 U

AI - 3 U AI - 4 U

Figure 96: Pinout

4.3.9.6 Connection example

AI

+ +

+ +

+24 VDC +24 VDC

GND GND

4.3.9.7 Input circuit diagram

AI + x U

A/D Input value

Converter
I/O status
AI - x U

LED (green)

Figure 97: Input circuit diagram

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4.3.9.8 Register description

4.3.9.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
16 Configuring the input filter USINT ●
20 Lower limit value INT ●
22 Upper limit value INT ●
Analog signal - Communication
Index * 2 - 2 AnalogInput0N (Index N = 1 to 4) INT ●
30 Input status USINT ●

4.3.9.8.2 Function model 254 - Bus controller

Register Offset Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
16 - Configuring the input filter USINT ●
20 - Lower limit value INT ●
22 - Upper limit value INT ●
Analog signal - Communication
Index * 2 - 2 Index * 2 - 2 AnalogInput0N (Index N = 1 to 4) INT ●
30 - Input status USINT ●

1) The offset specifies the position of the register within the CAN object.

4.3.9.8.3 Analog inputs

The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.

4.3.9.8.4 Analog input values

Name:
AnalogInput01 to AnalogInput04
The analog input values are mapped to this register.
Data type Value Input signal:
INT -32,768 to 32,767 Voltage signal -10 to 10 VDC

4.3.9.8.5 Input filter

This module is equipped with a configurable input filter. The minimum cycle time must be >500 μs. Filtering is
disabled for shorter cycle times.
If the input filter is active, then the scan rate for the channels is measured in ms. The time offset between the
channels is 200 μs. The conversion takes place asynchronously to the network cycle.

4.3.9.8.5.1 Input ramp limitation

Input ramp limitation can only take place when a filter is used; the input ramp is limited before filtering takes place.
The amount the input value changes is checked to make sure that specified limits are not exceeded. If the values
are exceeded, the adjusted input value is equal to the old value ± the limit value.
Configurable limit values:
Value Limit value
0 The input value is used without limitation.
1 0x3FFF = 16383
2 0x1FFF = 8191
3 0x0FFF = 4095
4 0x07FF = 2047
5 0x03FF = 1023
6 0x01FF = 511
7 0x00FF = 255

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Input ramp limitation is well suited for suppressing disturbances (spikes). The following examples show the function
of the input ramp limitation based on an input jump and a disturbance.
Example 1
The input value jumps from 8,000 to 17,000. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

17000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 98: Adjusted input value for input jump

Example 2
A disturbance interferes with the input value. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 99: Adjusted input value for disturbance

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4.3.9.8.5.2 Filter level

A filter can be defined to prevent large input jumps. This filter is used to bring the input value closer to the actual
analog value over a period of several bus cycles.
Filtering takes place after input ramp limitation.
Formula for calculating the input value:
Value Old Input value
Value New = Value Old - +
Filter level Filter level
Adjustable filter levels:
Value Filter level
0 Filter switched off
1 Filter level 2
2 Filter level 4
3 Filter level 8
4 Filter level 16
5 Filter level 32
6 Filter level 64
7 Filter level 128

The following examples show how filtering works in the event of an input jump or disturbance.
Example 1
The input value jumps from 8,000 to 16,000. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 100: Calculated value during input jump

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Example 2
A disturbance interferes with the input value. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 101: Calculated value during disturbance

4.3.9.8.6 Configuring the input filter

Name:
ConfigOutput01
This register is used to define the filter level and input ramp limitation of the input filter.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-2 Defines the filter level 000 Filter switched off
001 Filter level 2
010 Filter level 4
011 Filter level 8
100 Filter level 16
101 Filter level 32
110 Filter level 64
111 Filter level 128
3 Reserved 0
4-6 Defines the input ramp limitation 000 The input value is used without limitation
001 Limit value = 0x3FFF (16383)
010 Limit value = 0x1FFF (8191)
011 Limit value = 0x0FFF (4095)
100 Limit value = 0x07FF (2047)
101 Limit value = 0x03FF (1023)
110 Limit value = 0x01FF (511)
111 Limit value = 0x00FF (255)
7 Reserved 0

4.3.9.8.7 Lower limit value

Name:
ConfigOutput03
This register can be used to configure the lower limit for analog values. If the analog value goes below the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
The default value of -32768 corresponds to the minimum default value of -10 VDC.
Keep in mind that this setting applies to all channels!

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4.3.9.8.8 Upper limit value

Name:
ConfigOutput04
This register can be used to configure the upper limit for analog values. If the analog value goes above the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
The default value of 32767 corresponds to the maximum default value at +10 VDC.
Keep in mind that this setting applies to all channels!

4.3.9.8.9 Input status

Name:
StatusInput01
This register is used to monitor the module inputs. A change in the monitoring status generates an error message.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Channel 1 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded
11 Open line
... ...
6-7 Channel 4 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded
11 Open line

Limiting the analog value

In addition to the status information, the analog value is set to the values listed below by default when an error
occurs. The analog value is limited to the new values if the limit values were changed.
Error status Digital value for error (default values)
Open line +32767 (0x7FFF)
Upper limit value exceeded +32767 (0x7FFF)
Lower limit value exceeded -32767 (0x8001)
Invalid value -32768 (0x8000)

4.3.9.8.10 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Inputs without filtering 100 µs
Inputs with filtering 500 µs

4.3.9.8.11 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Inputs without filtering 400 µs for all inputs
Inputs with filtering 1 ms

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4.3.10 X20AI4322

4.3.10.1 General information

The module is equipped with 4 inputs with 12-bit digital converter resolution. It is possible to select between the
two current ranges 0 to 20 mA and 4 to 20 mA.
• 4 analog inputs, 0 to 20 mA or 4 to 20 mA
• 12-bit digital converter resolution

4.3.10.2 Order data

Model number Short description Figure

Analog input modules
X20AI4322 X20 analog input module, 4 inputs, 0-20 mA / 4-20 mA, 12-bit
converter resolution, configurable input filter
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 56: X20AI4322 - Order data

4.3.10.3 Technical data

Product ID X20AI4322
Short description
I/O module 4 analog inputs 0 to 20 mA / 4 to 20 mA
General information
B&R ID code 0xCAB3
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Inputs Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.1 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
GL Yes
GOST-R Yes
Analog inputs
Input 0 to 20 mA/4 to 20 mA
Input type Differential input
Digital converter resolution 12-bit
Conversion time 400 µs for all inputs
Output format
Data type INT
Current 0x0000 - 0x7FFF / 1 LSB = 0x0008 = 4.883 µA
Load <400 Ω
Input protection Protection against wiring with supply voltage
Permitted input signal Max. ±50 mA
Output of the digital value during overload
Below lower limit 0x0000
Above upper limit 0x7FFF
Conversion procedure SAR
Input filter 3rd-order low pass / cutoff frequency 1 kHz

Table 57: X20AI4322 - Technical data

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Product ID X20AI4322
Max. error at 25°C
Gain
0 to 20 mA 0.08% 1)
4 to 20 mA 0.1% 1)
Offset
0 to 20 mA 0.03% 2)
4 to 20 mA 0.16% 2)
Max. gain drift
0 to 20 mA 0.009 %/°C 1)
4 to 20 mA 0.0113 %/°C 1)
Max. offset drift
0 to 20 mA 0.004 %/°C 2)
4 to 20 mA 0.005 %/°C 2)
Common-mode rejection
DC 70 dB
50 Hz 70 dB
Common-mode range ±12 V
Crosstalk between channels -70 dB
Non-linearity <0.05% 2)
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 57: X20AI4322 - Technical data

1) Based on the current measured value.
2) Based on the 20 mA measurement range.

4.3.10.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
e+r Red on / Green single flash Invalid firmware
1-4 Green Blinking Input signal overflow or underflow
On Analog/digital converter running, value OK

Table 58: LED status indicators

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4.3.10.5 Pinout

r e
1 2
3 4

AI + 1 I AI + 2 I

AI - 1 I AI - 2 I

AI + 3 I AI + 4 I

AI - 3 I AI - 4 I

Figure 102: Pinout

4.3.10.6 Connection example

AI

+ +

+ +

+24 VDC +24 VDC

GND GND

4.3.10.7 Input circuit diagram

PTC
AI + x I

A/D Input value

Shunt
Converter
I/O status
AI - x I

LED (green)

Figure 103: Input circuit diagram

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4.3.10.8 Register description

4.3.10.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
16 Configuring the input filter USINT ●
18 Channel type USINT ●
20 Lower limit value INT ●
22 Upper limit value INT ●
Analog signal - Communication
Index * 2 - 2 AnalogInput0N (Index N = 1 to 4) INT ●
30 Input status USINT ●

4.3.10.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
16 - Configuring the input filter USINT ●
18 - Channel type USINT ●
20 - Lower limit value INT ●
22 - Upper limit value INT ●
Analog signal - Communication
Index * 2 - 2 Index * 2 - 2 AnalogInput0N (Index N = 1 to 4) INT ●
30 - Input status USINT ●

1) The offset specifies the position of the register within the CAN object.

4.3.10.8.3 Analog inputs

The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.

4.3.10.8.4 Analog input values

Name:
AnalogInput01 to AnalogInput04
The analog input values are mapped to this register.
Data type Value Input signal:
INT 0 to 32767 Current signal 0 to 20 mA or 4 to 20 mA

4.3.10.8.5 Input filter

This module is equipped with a configurable input filter. The minimum cycle time must be >500 μs. Filtering is
disabled for shorter cycle times.
If the input filter is active, then the scan rate for the channels is measured in ms. The time offset between the
channels is 200 μs. The conversion takes place asynchronously to the network cycle.

4.3.10.8.5.1 Input ramp limitation

Input ramp limitation can only take place when a filter is used; the input ramp is limited before filtering takes place.
The amount the input value changes is checked to make sure that specified limits are not exceeded. If the values
are exceeded, the adjusted input value is equal to the old value ± the limit value.
Configurable limit values:
Value Limit value
0 The input value is used without limitation.
1 0x3FFF = 16383
2 0x1FFF = 8191
3 0x0FFF = 4095
4 0x07FF = 2047
5 0x03FF = 1023
6 0x01FF = 511
7 0x00FF = 255

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Input ramp limitation is well suited for suppressing disturbances (spikes). The following examples show the function
of the input ramp limitation based on an input jump and a disturbance.
Example 1
The input value jumps from 8,000 to 17,000. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

17000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 104: Adjusted input value for input jump

Example 2
A disturbance interferes with the input value. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 105: Adjusted input value for disturbance

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4.3.10.8.5.2 Filter level

A filter can be defined to prevent large input jumps. This filter is used to bring the input value closer to the actual
analog value over a period of several bus cycles.
Filtering takes place after input ramp limitation.
Formula for calculating the input value:
Value Old Input value
Value New = Value Old - +
Filter level Filter level
Adjustable filter levels:
Value Filter level
0 Filter switched off
1 Filter level 2
2 Filter level 4
3 Filter level 8
4 Filter level 16
5 Filter level 32
6 Filter level 64
7 Filter level 128

The following examples show how filtering works in the event of an input jump or disturbance.
Example 1
The input value jumps from 8,000 to 16,000. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 106: Calculated value during input jump

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Example 2
A disturbance interferes with the input value. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 107: Calculated value during disturbance

4.3.10.8.6 Configuring the input filter

Name:
ConfigOutput01
This register is used to define the filter level and input ramp limitation of the input filter.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-2 Defines the filter level 000 Filter switched off
001 Filter level 2
010 Filter level 4
011 Filter level 8
100 Filter level 16
101 Filter level 32
110 Filter level 64
111 Filter level 128
3 Reserved 0
4-6 Defines the input ramp limitation 000 The input value is used without limitation
001 Limit value = 0x3FFF (16383)
010 Limit value = 0x1FFF (8191)
011 Limit value = 0x0FFF (4095)
100 Limit value = 0x07FF (2047)
101 Limit value = 0x03FF (1023)
110 Limit value = 0x01FF (511)
111 Limit value = 0x00FF (255)
7 Reserved 0

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4.3.10.8.7 Channel type

Name:
ConfigOutput02
This register can be used to set the range of the current signal. This is determined by how they are configured.
The following input signals can be set:
• 0 to 20 mA current signal
• 4 to 20 mA current signal
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-3 Reserved 1
4 Channel 1: Current measurement range 0 0 to 20 mA current signal
1 4 to 20 mA current signal
... ...
7 Channel 4: Current measurement range 0 0 to 20 mA current signal
1 4 to 20 mA current signal

4.3.10.8.8 Lower limit value

Name:
ConfigOutput03
This register can be used to configure the lower limit for analog values. If the analog value goes below the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
• When configured as 0 to 20 mA, this value should be set to 0.
• When configured as 4 to 20 mA, this value can be set to -8192 (corresponds to 0 mA) in order
to display values <4 mA.
Keep in mind that this setting applies to all channels!

4.3.10.8.9 Upper limit value

Name:
ConfigOutput04
This register can be used to configure the upper limit for analog values. If the analog value goes above the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
The default value of 32767 corresponds to the maximum default value at 20 mA.
Keep in mind that this setting applies to all channels!

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4.3.10.8.10 Input status

Name:
StatusInput01
This register is used to monitor the module inputs. A change in the monitoring status generates an error message.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Channel 1 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded
... ...
6-7 Channel 4 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded

Limiting the analog value

In addition to the status information, the analog value is set to the values listed below by default when an error
occurs. The analog value is limited to the new values if the limit values were changed.
Error status Digital value for error (default values)
0 to 20 mA 4 to 20 mA
Upper limit value exceeded +32767 (0x7FFF)
Lower limit value exceeded 0 -8191 (0xE001)

4.3.10.8.11 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Inputs without filtering 100 µs
Inputs with filtering 500 µs

4.3.10.8.12 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Inputs without filtering 400 µs for all inputs
Inputs with filtering 1 ms

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4.3.11 X20AI4622

4.3.11.1 General information

The module is equipped with 4 inputs with 13-bit (including sign) digital converter resolution. It is possible to select
between the current and voltage signal using different connection terminal points.
• 4 analog inputs
• Either current or voltage signal possible
• 13-bit digital converter resolution

4.3.11.2 Order data

Model number Short description Figure

Analog input modules
X20AI4622 X20 analog input module, 4 inputs, ±10 V or 0 to 20 mA / 4 to 20
mA, 13-bit resolution, configurable input filter
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 59: X20AI4622 - Order data

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4.3.11.3 Technical data

Product ID X20AI4622
Short description
I/O module 4 analog inputs ±10 V or 0 to 20 mA / 4 to 20 mA
General information
B&R ID code 0x1BAA
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Inputs Yes, using status LED and software
Channel type Yes, using software
Power consumption
Bus 0.01 W
Internal I/O 1.1 W 1)
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Analog inputs
Input ±10 V or 0 to 20 mA / 4 to 20 mA, via different connection terminal points
Input type Differential input
Digital converter resolution
Voltage ±12-bit
Current 12-bit
Conversion time 400 µs for all inputs
Output format INT
Output format
Voltage INT 0x8001 - 0x7FFF / 1 LSB = 0x0008 = 2.441 mV
Current INT 0x0000 - 0x7FFF / 1 LSB = 0x0008 = 4.883 µA
Input impedance in signal range
Voltage 20 MΩ
Current -
Load
Voltage -
Current <400 Ω
Input protection Protection against wiring with supply voltage
Permitted input signal
Voltage Max. ±30 V
Current Max. ±50 mA
Output of the digital value during overload
Below lower limit
Voltage 0x8001
Current 0x0000
Above upper limit
Voltage 0x7FFF
Current 0x7FFF
Conversion procedure SAR
Input filter 3rd-order low pass / cutoff frequency 1 kHz
Max. error at 25°C
Voltage
Gain 0.08% 2)
Offset 0.015% 3)
Current
Gain 0 to 20 mA = 0.08% / 4 to 20 mA = 0.1% 2)
Offset 0 to 20 mA = 0.03% / 4 to 20 mA = 0.16% 4)
Max. gain drift
Voltage 0.006 %/°C 2)
Current 0 to 20 mA = 0.009 %/°C
4 to 20 mA = 0.0113 %/°C 2)
Max. offset drift
Voltage 0.002 %/°C 3)
Current 0 to 20 mA = 0.004 %/°C
4 to 20 mA = 0.005 %/°C 4)
Common-mode rejection
DC 70 dB
50 Hz 70 dB
Common-mode range ±12 V

Table 60: X20AI4622 - Technical data

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Product ID X20AI4622
Crosstalk between channels <-70 dB
Non-linearity
Voltage <0.025% 3)
Current <0.05% 4)
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 60: X20AI4622 - Technical data

1) To reduce power dissipation, B&R recommends bridging unused inputs on the terminals or configuring them as current signals.
2) Based on the current measured value.
3) Based on the 20 V measurement range.
4) Based on the 20 mA measurement range.

4.3.11.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
e+r Red on / Green single flash Invalid firmware
1-4 Green Off Open line1) or sensor is disconnected
Blinking Input signal overflow or underflow
On Analog/digital converter running, value OK

Table 61: LED status indicators

1) Open line detection only possible when measuring voltage.

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4.3.11.5 Pinout

r e

X20 AI 4622
1 2
3 4

AI + 1 I AI + 2 I

AI + 1 U AI + 2 U

AI - 1 U/I AI - 2 U/I

AI + 3 I AI + 4 I

AI + 3 U AI + 4 U

AI - 3 U/I AI - 4 U/I

Figure 108: Pinout

4.3.11.6 Connection example

Voltage AI Current
measurement measurement

+24 VDC +24 VDC

GND GND

4.3.11.7 Input circuit diagram

Current/Voltage switching

PTC
AI + x I

Shunt

AI + x U Input value
A/D
converter
I/O status
AI - x U/I

LED (green)

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4.3.11.8 Register description

4.3.11.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 AnalogInput01 INT ●
2 AnalogInput02 INT ●
4 AnalogInput03 INT ●
6 AnalogInput04 INT ●
16 ConfigOutput01 USINT ●
18 ConfigOutput02 USINT ●
20 ConfigOutput03 INT ●
22 ConfigOutput04 INT ●
30 StatusInput01 USINT ●

4.3.11.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 AnalogInput01 INT ●
2 2 AnalogInput02 INT ●
4 4 AnalogInput03 INT ●
6 6 AnalogInput04 INT ●
16 - ConfigOutput01 USINT ●
18 - ConfigOutput02 USINT ●
20 - ConfigOutput03 INT ●
22 - ConfigOutput04 INT ●
30 - StatusInput01 USINT ●

1) The offset specifies the position of the register within the CAN object.

4.3.11.8.3 Analog inputs

The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.

4.3.11.8.4 Analog input values

Name:
AnalogInput01 to AnalogInput04
The analog input value are mapped to this register depending on the configured operating mode.
Data type Value Input signal:
INT -32768 to 32767 Voltage signal -10 to 10 VDC
0 to 32767 Current signal 0 to 20 mA

4.3.11.8.5 Input filter

This module is equipped with a configurable input filter. The minimum cycle time must be >500 μs. Filtering is
disabled for shorter cycle times.
If the input filter is active, then the scan rate for the channels is measured in ms. The time offset between the
channels is 200 μs. The conversion takes place asynchronously to the network cycle.

4.3.11.8.5.1 Input ramp limitation

Input ramp limitation can only take place when a filter is used; the input ramp is limited before filtering takes place.
The amount the input value changes is checked to make sure that specified limits are not exceeded. If the values
are exceeded, the adjusted input value is equal to the old value ± the limit value.
Configurable limit values:
Value Limit value
0 The input value is used without limitation.
1 0x3FFF = 16383
2 0x1FFF = 8191
3 0x0FFF = 4095
4 0x07FF = 2047
5 0x03FF = 1023
6 0x01FF = 511
7 0x00FF = 255

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Input ramp limitation is well suited for suppressing disturbances (spikes). The following examples show the function
of the input ramp limitation based on an input jump and a disturbance.
Example 1
The input value jumps from 8,000 to 17,000. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

17000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 109: Adjusted input value for input jump

Example 2
A disturbance interferes with the input value. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 110: Adjusted input value for disturbance

4.3.11.8.5.2 Filter level

A filter can be defined to prevent large input jumps. This filter is used to bring the input value closer to the actual
analog value over a period of several bus cycles.
Filtering takes place after input ramp limitation.
Formula for calculating the input value:
Value Old Input value
Value New = Value Old - +
Filter level Filter level

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Adjustable filter levels:

Value Filter level
0 Filter switched off
1 Filter level 2
2 Filter level 4
3 Filter level 8
4 Filter level 16
5 Filter level 32
6 Filter level 64
7 Filter level 128

The following examples show how filtering works in the event of an input jump or disturbance.
Example 1
The input value jumps from 8,000 to 16,000. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 111: Calculated value during input jump

Example 2
A disturbance interferes with the input value. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 112: Calculated value during disturbance

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4.3.11.8.6 Configuring the input filter

Name:
ConfigOutput01
This register is used to define the filter level and input ramp limitation of the input filter.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-2 Defines the filter level 000 Filter switched off
001 Filter level 2
010 Filter level 4
011 Filter level 8
100 Filter level 16
101 Filter level 32
110 Filter level 64
111 Filter level 128
3 Reserved 0
4-6 Defines the input ramp limitation 000 The input value is used without limitation
001 Limit value = 0x3FFF (16383)
010 Limit value = 0x1FFF (8191)
011 Limit value = 0x0FFF (4095)
100 Limit value = 0x07FF (2047)
101 Limit value = 0x03FF (1023)
110 Limit value = 0x01FF (511)
111 Limit value = 0x00FF (255)
7 Reserved 0

4.3.11.8.7 Channel type

Name:
ConfigOutput02
This register can be used to define the type and range of signal measurement.
Each channel is capable of handling either current or voltage signals. This differentiation is made using multiple
connection terminal points and an integrated switch in the module. The switch is automatically activated by the
module depending on the specified configuration. The following input signals can be set:
• ±10 V voltage signal (default)
• 0 to 20 mA current signal
• 4 to 20 mA current signal
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Channel 1 0 Voltage signal
1 Current signal, measurement range corresponding to bit 4
... ...
3 Channel 4 0 Voltage signal
1 Current signal, measurement range corresponding to bit 7
4 Channel 1: Current measurement range 0 0 to 20 mA current signal
1 4 to 20 mA current signal
... ...
7 Channel 4: Current measurement range 0 0 to 20 mA current signal
1 4 to 20 mA current signal

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4.3.11.8.8 Limit values

The input signal is monitored at the upper and lower limit values. These must be defined according to the operating
mode:
Limit value (default) Voltage signal ±10 V Current signal 0 to 20 mA Current signal 4 to 20 mA
Upper maximum limit value +10 V +32767 (0x7FFF) 20 mA +32767 (0x7FFF) 20 mA +32767 (0x7FFF)
Lower minimum limit value -10 V -32767 (0x8001) 0 mA 01) 4 mA 02)

1) The analog value is limited down to 0.

2) The analog value is limited down to 0 at currents <4 mA. The status bit for the lower limit is set.

Other limit values can be defined if necessary. Limit values are valid for all channels and activated automatically
by writing to the limit value registers. From this point on, the analog values will be monitored and limited according
to the new limits. The results of monitoring are displayed in the status register.
Examples of limit value settings
Application case Limit value settings
Current signal: 4 to 20 mA A negative limit value must be configured in order to measure values <4 mA with a current signal of 4 to
20 mA: 0 mA is equal to a value of -8192 (0xE000).
Mixed voltage and current signal The configured limit values are valid for all channels. Mixed operation (voltage and current signal) there-
fore requires a compromise.
The following configuration has proven effective:
Upper limit = +32767, lower limit = -32767
This makes it possible to also measure negative voltage values. A lower limit value of 0 would limit the
voltage value to 0.
Current signal on all channels All channels are configured for measuring current. The limit value setting in Automation Studio is not
adjusted automatically. That means that +32767 is configured as the upper limit value and -32767 as the
lower limit value. The necessary changes must be made by the user, e.g. lower limit value = 0

4.3.11.8.8.1 Lower limit value

Name:
ConfigOutput03
This register can be used to configure the lower limit for analog values. If the analog value goes below the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
• The default value of -32768 corresponds to the minimum default value of -10 VDC.
• When configured as 0 to 20 mA, this value should be set to 0.
• When configured as 4 to 20 mA, this value can be set to -8192 (corresponds to 0 mA) in order
to display values <4 mA.

Information:
Keep in mind that this setting applies to all channels!

4.3.11.8.8.2 Upper limit value

Name:
ConfigOutput04
This register can be used to configure the upper limit for analog values. If the analog value goes above the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
The default value of 32767 corresponds to the maximum default value of 20 mA or +10 VDC.

Information:
Keep in mind that this setting applies to all channels!

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4.3.11.8.9 Input status

Name:
StatusInput01
This register is used to monitor the module inputs. A change in the monitoring status generates an error message.
The following states are monitored depending on the settings:
Value Voltage signal ±10 V Current signal 0 to 20 mA Current signal 4 to 20 mA
0 No error No error No error
1 Lower limit value exceeded Default setting Lower limit value exceeded
The input value has a lower limit of 0x0000. Un-
derflow monitoring is therefore not necessary.
After lower limit value change
The input value is limited to the configured val-
ue. The status bit is set when the lower limit val-
ue is passed.
2 Upper limit value exceeded Upper limit value exceeded Upper limit value exceeded
3 Open line - -

Data type Value

USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Channel 1 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded
11 Open line
... ...
6-7 Channel 4 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded
11 Open line

Limiting the analog value

In addition to the status information, the analog value is set to the values listed below by default when an error
occurs. The analog value is limited to the new values if the limit values were changed.
Error status Digital value for error (default values)
Open line +32767 (0x7FFF)
Upper limit value exceeded +32767 (0x7FFF)
Lower limit value exceeded -32767 (0x8001)
Invalid value -32768 (0x8000)

4.3.11.8.10 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Inputs without filtering 100 µs
Inputs with filtering 500 µs

4.3.11.8.11 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Inputs without filtering 300 µs for all inputs
Inputs with filtering 1 ms

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4.3.12 X20AI8221

4.3.12.1 General information

The module is equipped with 8 inputs with 13-bit (including sign) digital converter resolution. It can be used to
capture voltage signals in the range from ±10 V.
• 8 analog inputs ±10 V
• 13-bit digital converter resolution

4.3.12.2 Order data

Model number Short description Figure

Analog input modules
X20AI8221 X20 analog input module, 8 inputs, ±10 V, 13-bit converter res-
olution
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB1F X20 terminal block, 16-pin, 24 VDC keyed

Table 62: X20AI8221 - Order data

4.3.12.3 Technical data

Product ID X20AI8221
Short description
I/O module 8 analog inputs ±10 V
General information
B&R ID code 0xD82F
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Inputs Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.04 W 1)
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
GL Yes
GOST-R Yes
Analog inputs
Input ±10 V
Input type Differential input
Digital converter resolution ±12-bit
Conversion time 1 ms for all inputs
Output format
Data type INT
Voltage 0x8001 - 0x7FFF / 1 LSB = 0x0008 = 2.441 mV
Input impedance in signal range 20 MΩ
Input protection Protection against wiring with supply voltage
Open line detection Yes, using software
Reverse polarity protection Yes
Permitted input signal Max. ±30 V
Output of the digital value during overload
Below lower limit 0x8001
Above upper limit 0x7FFF

Table 63: X20AI8221 - Technical data

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Product ID X20AI8221
Conversion procedure SAR
Input filter 3rd-order low pass / cutoff frequency 1 kHz
Max. error at 25°C
Gain 0.08% 2)
Offset 0.015% 3)
Max. gain drift 0.006 %/°C 2)
Max. offset drift 0.002 %/°C 3)
Common-mode rejection
DC 70 dB
50 Hz 70 dB
Common-mode range ±12 V
Crosstalk between channels -70 dB
Non-linearity <0.025% 3)
Isolation voltage between channel and bus 500 VDC, 1 min
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB1F terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 63: X20AI8221 - Technical data

1) To reduce power dissipation, B&R recommends bridging unused inputs on the terminals.
2) Based on the current measured value.
3) Based on the 20 V measurement range.

4.3.12.4 LED status indicators

Figure LED Color Status Description

S Green Off No power to module
Single flash UNLINK mode
Double flash BOOT mode (during firmware update)1)
Blinking quickly SYNC mode
Blinking slowly PREOPERATIONAL mode
On RUN mode
Red Off No power to module or everything OK
On Error or reset status
1-8 Green Off Indicates one of the following cases:
• No power to module
• Open line
Single flash Input signal overflow or underflow
On Analog/digital converter running, value OK

Table 64: LED status indicators

1) Depending on the configuration, a firmware update can take up to several minutes.

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4.3.12.5 Pinout

S 1
2
3
4
5
6
7
8

AI + 1 U AI− 1 U
AI + 2 U AI− 2 U
AI + 3 U AI− 3 U
AI + 4 U AI− 4 U
AI + 5 U AI− 5 U
AI + 6 U AI− 6 U
AI + 7 U AI− 7 U
AI + 8 U AI− 8 U

Figure 113: Pinout

4.3.12.6 Connection example

AI

U1

U2

U3

U4

U5

U6

U7

U8

+24 VDC +24 VDC

GND GND

Figure 114: Connection example

4.3.12.7 Input circuit diagram

AI + x U

A/D Input value

Converter
I/O status
AI - x U

LED (green)

Figure 115: Input circuit diagram

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4.3.12.8 Register description

4.3.12.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
16 Configuring the input filter USINT ●
20 Lower limit value INT ●
22 Upper limit value INT ●
Analog signal - Communication
Index * 2 - 2 AnalogInput0N (Index N = 1 to 8) INT ●
30 StatusInput01 USINT ●
31 StatusInput02 USINT ●

4.3.12.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
16 - Configuring the input filter USINT ●
20 - Lower limit value INT ●
22 - Upper limit value INT ●
Analog signal - Communication
Index * 2 - 2 Index * 2 - 2 AnalogInput0N (Index N = 1 to 8) INT ●
30 - StatusInput01 USINT ●
31 - StatusInput02 USINT ●

1) The offset specifies the position of the register within the CAN object.

4.3.12.8.3 Analog inputs

Input signals are converted asynchronously in a 1 ms interval.

4.3.12.8.4 Analog input values

Name:
AnalogInput01 to AnalogInput08
The analog input values are mapped to this register.
Data type Value Input signal:
INT -32,768 to 32,767 Voltage signal -10 to 10 VDC

4.3.12.8.5 Input filter

This module is equipped with a configurable input filter.

4.3.12.8.5.1 Input ramp limitation

Input ramp limitation can only take place when a filter is used; the input ramp is limited before filtering takes place.
The amount the input value changes is checked to make sure that specified limits are not exceeded. If the values
are exceeded, the adjusted input value is equal to the old value ± the limit value.
Configurable limit values:
Value Limit value
0 The input value is used without limitation.
1 0x3FFF = 16383
2 0x1FFF = 8191
3 0x0FFF = 4095
4 0x07FF = 2047
5 0x03FF = 1023
6 0x01FF = 511
7 0x00FF = 255

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Input ramp limitation is well suited for suppressing disturbances (spikes). The following examples show the function
of the input ramp limitation based on an input jump and a disturbance.
Example 1
The input value jumps from 8,000 to 17,000. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

17000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 116: Adjusted input value for input jump

Example 2
A disturbance interferes with the input value. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 117: Adjusted input value for disturbance

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4.3.12.8.5.2 Filter level

A filter can be defined to prevent large input jumps. This filter is used to bring the input value closer to the actual
analog value over a period of several bus cycles.
Filtering takes place after input ramp limitation.
Formula for calculating the input value:
Value Old Input value
Value New = Value Old - +
Filter level Filter level
Adjustable filter levels:
Value Filter level
0 Filter switched off
1 Filter level 2
2 Filter level 4
3 Filter level 8
4 Filter level 16
5 Filter level 32
6 Filter level 64
7 Filter level 128

The following examples show how filtering works in the event of an input jump or disturbance.
Example 1
The input value jumps from 8,000 to 16,000. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 118: Calculated value during input jump

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Example 2
A disturbance interferes with the input value. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 119: Calculated value during disturbance

4.3.12.8.6 Configuring the input filter

Name:
ConfigOutput01
This register is used to define the filter level and input ramp limitation of the input filter.
Data type Value
UINT See bit structure.

Bit structure:
Bit Description Value Information
0-2 Defines the filter level 000 Filter switched off
001 Filter level 2
010 Filter level 4
011 Filter level 8
100 Filter level 16
101 Filter level 32
110 Filter level 64
111 Filter level 128
3 Reserved 0
4-6 Defines the input ramp limitation 000 The input value is used without limitation
001 Limit value = 0x3FFF (16383)
010 Limit value = 0x1FFF (8191)
011 Limit value = 0x0FFF (4095)
100 Limit value = 0x07FF (2047)
101 Limit value = 0x03FF (1023)
110 Limit value = 0x01FF (511)
111 Limit value = 0x00FF (255)
7 - 15 Reserved 0

4.3.12.8.7 Lower limit value

Name:
ConfigOutput03
This register can be used to configure the lower limit for analog values. If the analog value goes below the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
The default value of -32768 corresponds to the minimum default value of -10 VDC.
Keep in mind that this setting applies to all channels!

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4.3.12.8.8 Upper limit value

Name:
ConfigOutput04
This register can be used to configure the upper limit for analog values. If the analog value goes above the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
The default value of 32767 corresponds to the maximum default value at +10 VDC.
Keep in mind that this setting applies to all channels!

4.3.12.8.9 Input status

Name:
StatusInput01 to StatusInput02
This register is used to monitor the module inputs. A change in the monitoring status generates an error message.
Data type Value
USINT See bit structure.

Bit structure:
StatusInput01 monitors Channels 1 to 4
StatusInput02 monitors Channels 5 to 8
Bit Description Value Information
0-1 Channel 1 or 5 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded
11 Open line
... ...
6-7 Channel 4 or 8 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded
11 Open line

Limiting the analog value

In addition to the status information, the analog value is set to the values listed below by default when an error
occurs. The analog value is limited to the new values if the limit values were changed.
Error status Digital value for error (default values)
Open line +32767 (0x7FFF)
Upper limit value exceeded +32767 (0x7FFF)
Lower limit value exceeded -32767 (0x8001)
Invalid value -32768 (0x8000)

4.3.12.8.10 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
150 μs

4.3.12.8.11 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
1 ms

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4.3.13 X20AI8321

4.3.13.1 General information

The module is equipped with 8 inputs with 12-bit digital converter resolution. It is possible to select between the
two current ranges 0 to 20 mA and 4 to 20 mA.
• 8 analog inputs, 0 to 20 mA or 4 to 20 mA
• 12-bit digital converter resolution

4.3.13.2 Order data

Model number Short description Figure

Analog input modules
X20AI8321 X20 analog input module, 8 inputs, 0-20 mA, 12-bit resolution
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB1F X20 terminal block, 16-pin, 24 VDC keyed

Table 65: X20AI8321 - Order data

4.3.13.3 Technical data

Product ID X20AI8321
Short description
I/O module 8 analog inputs 0 to 20 mA / 4 to 20 mA
General information
B&R ID code 0xD831
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Inputs Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.24 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
GL Yes
GOST-R Yes
Analog inputs
Input 0 to 20 mA/4 to 20 mA
Input type Differential input
Digital converter resolution 12-bit
Conversion time 1 ms for all inputs
Output format
Data type INT
Current 0x0000 - 0x7FFF / 1 LSB = 0x0008 = 4.883 µA
Load <300 Ω
Input protection Protection against wiring with supply voltage
Reverse polarity protection Yes
Permitted input signal Max. ±50 mA
Output of the digital value during overload
Below lower limit 0x0000
Above upper limit 0x7FFF
Conversion procedure SAR

Table 66: X20AI8321 - Technical data

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Product ID X20AI8321
Input filter 3rd-order low pass / cutoff frequency 1 kHz
Max. error at 25°C
Gain
0 to 20 mA 0.08% 1)
4 to 20 mA 0.1% 1)
Offset
0 to 20 mA 0.03% 2)
4 to 20 mA 0.16% 2)
Max. gain drift
0 to 20 mA 0.009 %/°C 1)
4 to 20 mA 0.0113 %/°C 1)
Max. offset drift
0 to 20 mA 0.005 %/°C 2)
4 to 20 mA 0.006 %/°C 2)
Common-mode rejection
DC 70 dB
50 Hz 70 dB
Common-mode range ±12 V
Crosstalk between channels -70 dB
Non-linearity <0.05% 2)
Isolation voltage between channel and bus 500 VDC, 1 min
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB1F terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 66: X20AI8321 - Technical data

1) Based on the current measured value.
2) Based on the 20 mA measurement range.

4.3.13.4 LED status indicators

Figure LED Color Status Description

S Green Off No power to module
Single flash UNLINK mode
Double flash BOOT mode (during firmware update)1)
Blinking quickly SYNC mode
Blinking slowly PREOPERATIONAL mode
On RUN mode
Red Off No power to module or everything OK
On Error or reset status
1-8 Green Off No power to module
Single flash Input signal overflow or underflow
On Analog/digital converter running, value OK

Table 67: LED status indicators

1) Depending on the configuration, a firmware update can take up to several minutes.

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4.3.13.5 Pinout

S 1
2
3
4
5
6
7
8

AI + 1 I AI− 1 I
AI + 2 I AI− 2 I
AI + 3 I AI− 3 I
AI + 4 I AI− 4 I
AI + 5 I AI− 5 I
AI + 6 I AI− 6 I
AI + 7 I AI− 7 I
AI + 8 I AI− 8 I

Figure 120: Pinout

4.3.13.6 Connection example

AI

I1 I

I I2

I3 I

I I4

I5 I

I I6

I7 I

I I8

+24 VDC +24 VDC

GND GND

Figure 121: Connection example

4.3.13.7 Input circuit diagram

PTC
AI + x I

A/D Input value

Shunt
Converter
I/O status
AI - x I

LED (green)

Figure 122: Input circuit diagram

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4.3.13.8 Register description

4.3.13.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
16 Configuring the input filter USINT ●
18 Channel type UINT ●
20 Lower limit value INT ●
22 Upper limit value INT ●
Analog signal - Communication
Index * 2 - 2 AnalogInput0N (Index N = 1 to 8) INT ●
30 StatusInput01 USINT ●
31 StatusInput02 USINT ●

4.3.13.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
16 - Configuring the input filter USINT ●
18 - Channel type UINT ●
20 - Lower limit value INT ●
22 - Upper limit value INT ●
Analog signal - Communication
Index * 2 - 2 Index * 2 - 2 AnalogInput0N (Index N = 1 to 8) INT ●
30 - StatusInput01 USINT ●
31 - StatusInput02 USINT ●

1) The offset specifies the position of the register within the CAN object.

4.3.13.8.3 Analog inputs

Input signals are converted asynchronously in a 1 ms interval.

4.3.13.8.4 Analog input values

Name:
AnalogInput01 to AnalogInput08
The analog input values are mapped to this register.
Data type Value Input signal:
INT 0 to 32767 Current signal 0 to 20 mA or 4 to 20 mA

4.3.13.8.5 Input filter

This module is equipped with a configurable input filter.

4.3.13.8.5.1 Input ramp limitation

Input ramp limitation can only take place when a filter is used; the input ramp is limited before filtering takes place.
The amount the input value changes is checked to make sure that specified limits are not exceeded. If the values
are exceeded, the adjusted input value is equal to the old value ± the limit value.
Configurable limit values:
Value Limit value
0 The input value is used without limitation.
1 0x3FFF = 16383
2 0x1FFF = 8191
3 0x0FFF = 4095
4 0x07FF = 2047
5 0x03FF = 1023
6 0x01FF = 511
7 0x00FF = 255

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Input ramp limitation is well suited for suppressing disturbances (spikes). The following examples show the function
of the input ramp limitation based on an input jump and a disturbance.
Example 1
The input value jumps from 8,000 to 17,000. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

17000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 123: Adjusted input value for input jump

Example 2
A disturbance interferes with the input value. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 124: Adjusted input value for disturbance

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4.3.13.8.5.2 Filter level

A filter can be defined to prevent large input jumps. This filter is used to bring the input value closer to the actual
analog value over a period of several bus cycles.
Filtering takes place after input ramp limitation.
Formula for calculating the input value:
Value Old Input value
Value New = Value Old - +
Filter level Filter level
Adjustable filter levels:
Value Filter level
0 Filter switched off
1 Filter level 2
2 Filter level 4
3 Filter level 8
4 Filter level 16
5 Filter level 32
6 Filter level 64
7 Filter level 128

The following examples show how filtering works in the event of an input jump or disturbance.
Example 1
The input value jumps from 8,000 to 16,000. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000

8000

0
1 2 3 4 5 6 7 8 t [ms]

Input jump

Figure 125: Calculated value during input jump

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Example 2
A disturbance interferes with the input value. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4

16000
Disturbance (spike)

8000

0
1 2 3 4 5 6 7 8 t [ms]

Figure 126: Calculated value during disturbance

4.3.13.8.6 Configuring the input filter

Name:
ConfigOutput01
This register is used to define the filter level and input ramp limitation of the input filter.
Data type Value
UINT See bit structure.

Bit structure:
Bit Description Value Information
0-2 Defines the filter level 000 Filter switched off
001 Filter level 2
010 Filter level 4
011 Filter level 8
100 Filter level 16
101 Filter level 32
110 Filter level 64
111 Filter level 128
3 Reserved 0
4-6 Defines the input ramp limitation 000 The input value is used without limitation
001 Limit value = 0x3FFF (16383)
010 Limit value = 0x1FFF (8191)
011 Limit value = 0x0FFF (4095)
100 Limit value = 0x07FF (2047)
101 Limit value = 0x03FF (1023)
110 Limit value = 0x01FF (511)
111 Limit value = 0x00FF (255)
7 - 15 Reserved 0

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4.3.13.8.7 Channel type

Name:
ConfigOutput02
This register can be used to set the range of the current signal. This is determined by how they are configured.
The following input signals can be set:
• 0 to 20 mA current signal
• 4 to 20 mA current signal
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Channel 1: Current measurement range 0 0 to 20 mA current signal
1 4 to 20 mA current signal
... ...
7 Channel 8: Current measurement range 0 0 to 20 mA current signal
1 4 to 20 mA current signal

4.3.13.8.8 Lower limit value

Name:
ConfigOutput03
This register can be used to configure the lower limit for analog values. If the analog value goes below the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
• When configured as 0 to 20 mA, this value should be set to 0.
• When configured as 4 to 20 mA, this value can be set to -8192 (corresponds to 0 mA) in order
to display values <4 mA.
Keep in mind that this setting applies to all channels!

4.3.13.8.9 Upper limit value

Name:
ConfigOutput04
This register can be used to configure the upper limit for analog values. If the analog value goes above the limit
value, it is frozen at this value and the corresponding error status bit is set.
Data type Value
INT -32,768 to 32,767

Information:
The default value of 32767 corresponds to the maximum default value at 20 mA.
Keep in mind that this setting applies to all channels!

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4.3.13.8.10 Input status

Name:
StatusInput01 to StatusInput02
This register is used to monitor the module inputs. A change in the monitoring status generates an error message.
Data type Value
USINT See bit structure.

Bit structure:
StatusInput01 monitors Channels 1 to 4
StatusInput02 monitors Channels 5 to 8
Bit Description Value Information
0-1 Channel 1 or 5 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded
... ...
6-7 Channel 4 or 8 00 No error
01 Lower limit value exceeded
10 Upper limit value exceeded

Limiting the analog value

In addition to the status information, the analog value is set to the values listed below by default when an error
occurs. The analog value is limited to the new values if the limit values were changed.
Error status Digital value for error (default values)
0 to 20 mA 4 to 20 mA
Upper limit value exceeded +32767 (0x7FFF)
Lower limit value exceeded 0 -8191 (0xE001)

4.3.13.8.11 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
150 μs

4.3.13.8.12 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
1 ms

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4.3.14 X20AP31x1

4.3.14.1 General information

Power monitoring
These modules measure active, reactive and apparent power individually for each of the three phases and for
all of them collectively. The power consumption of each phase and the total sum is also recorded. In addition,
the modules provide the RMS values for voltage and current on the three phases. When measuring the current,
the value of the current through the neutral line can also be detected and monitored. Measurement of the mains
frequency and the phase angle of the three phases (current and voltage) complete the power measurement data.

Energy management
The integrated functions on the modules map the immediate power requirements of the machine in detail and also
record its total power consumption. For the user, all relevant data is prepared and made available in the process
image.
The ability to measure currents and voltages up to the 31st harmonic enables higher precision recording of RMS
values. This allows the modules to easily cope with irregular sine curves, and makes them well-suited to renewable
energy applications. In these types of applications, being able to accurately measure the frequency at a resolution
of 0.01 Hz between 45-65 Hz is a great advantage. In general, the modules are suitable for use with 1-phase, 2-
phase or 3-phase power mains.

Features
• Calculate RMS values from currents and voltages
• Calculate active, reactive and apparent power
• Calculate active, reactive and apparent energy
• Phasing detection
• Measure individual phases and calculate cumulative values
• Optionally measure current through the neutral line
• Calculate frequency and harmonics with high precision

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4.3.14.2 Order data

Model number Short description

Analog input modules
X20AP3111 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 20 mA AC,
calculates effective, reactive and apparent power/energy, calculates root mean square values,
240 V keyed
X20AP3121 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 1 A AC,
calculates effective, reactive and apparent power/energy, calculates root mean square values,
240 V keyed
X20AP3131 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 5 A AC,
calculates effective, reactive and apparent power/energy, calculates root mean square values,
240 V keyed
X20AP3161 X20 energy measurement module, 3 analog inputs 480 VAC, 50/60 Hz, 4 analog inputs 333
mV AC, calculates effective, reactive and apparent power/energy, calculates root mean square
values, 240 V keyed
Required accessories
Bus modules
X20BM32 X20 bus module for double-width modules, 240 VAC keyed, internal I/O supply continuous
Terminal blocks
X20TB32 X20 terminal block, 12-pin, 240 VAC keyed

Table 68: X20AP3111, X20AP3121, X20AP3131, X20AP3161 - Order data

4.3.14.3 Technical data

Product ID X20AP3111 X20AP3121 X20AP3131 X20AP3161

Short description
I/O module 3-phase power and energy measurement module
General information
B&R ID code 0xC9DA 0xC9DB 0xC9DC 0xE17B
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Inputs Yes, using status LED and software
Power consumption
Bus 0.85 W
Internal I/O -
Additional module power dissipation 40 mW 1) 2 W 1) - 2)
[W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Isolation voltage
Inputs - Bus / I/O supply 5500 VDC
Inputs - Ground 5500 VDC
Bus / I/O supply - Ground 510 VAC
Certification
CE Yes
cULus Yes -
ATEX Zone 2 Yes -
GOST-R Yes
Voltage inputs
Number of phases 3
Nominal voltage
Between phases Max. 480 VAC
Phase to N Max. 277 VAC
Max. overload voltage 1.5 x UN permanent
2 x UN for 1 min

Table 69: X20AP3111, X20AP3121, X20AP3131, X20AP3161 - Technical data

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Product ID X20AP3111 X20AP3121 X20AP3131 X20AP3161
Max. display value 655 VAC
Resolution 10 mV, with voltage connected directly
Rated frequency 50 and 60 Hz
Current inputs
Quantity 4 AC inputs 4 AC voltage inputs
Nominal current
Secondary 20 mA 1A 5A 333 mV
Primary 65 A directly configurable, larger values through conversion in the application 3)
Max. overload current 20 x IN for 0.5 s 8 x IN for 0.5 s -
Max. measurement current 20 mA 1A 5A 333 mV
Resolution 1 mA, based on the primary current 3)
Load 25 Ω 500 mΩ 20 mΩ -
Measurement precision
URMS and IRMS <0.5%
Effective, reactive and apparent power <0.5% on average
Frequency, power factor and phase <0.5% 4)
angle
Active energy per phase and total
Power factor = 1.0 0.1% 5)
Power factor = 0.5 L 0.1% 6)
Power factor = 0.8 C 0.1% 4)
Reactive energy per phase and total
sin ϕ = 1.0 0.2% 5)
sin ϕ = 0.5 L 0.2% 6)
sin ϕ = 0.8 C 0.2% 4)
Apparent energy
Per phase and arithmetic total 0.2%
Vector sum 0.5%
Active energy of fundamental frequen-
cy per phase and total
Power factor = 1.0 0.2% 5)
Power factor = 0.5 L 0.2% 6)
Power factor = 0.8 C 0.2% 4)
Active energy of harmonics per phase
and total
sin ϕ = 1.0 0.5% 5)
sin ϕ = 0.5 L 0.5% 6)
sin ϕ = 0.8 C 0.5% 4)
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea
level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB32 terminal block separately
Order 1x X20BM32 bus module separately
Spacing 25 +0.2 mm

Table 69: X20AP3111, X20AP3121, X20AP3131, X20AP3161 - Technical data

1) Power dissipation of current measurement shunts.
2) Shunts are external in the current transformer
3) For measuring higher current values, see section "Current transformer - Pinout".
4) From 0.151 VAC to 480 VAC
5) From 0.101 VAC to 480 VAC
6) From 0.126 VAC to 480 VAC

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4.3.14.4 LED status indicators

Figure LED Color Status Description

Operating status
r Green Off No power to module
Single flash UNLINK mode
Double flash BOOT mode (during firmware update)1)
Blinking quickly SYNC mode
Blinking slowly PREOPERATIONAL mode
On RUN mode
Module status
e Red Off No power to module or everything OK
On Error or reset status
Analog input voltage
U1 - U3 Green / yellow Off Display disabled or URMS < "Fail" threshold value
Green Blinking Phase sequence is correct and URMS < "Warning" threshold value
On Phase sequence is correct and URMS > "Warning" threshold value
Yellow Blinking Phase sequence is incorrect and URMS < "Warning" threshold value
On Phase sequence is incorrect and URMS > "Warning" threshold value
Analog input current
I1 - I3 Green / yellow Off Display disabled or IRMS < "Display" threshold value
Green On Active power positive
Yellow On Active power negative
Analog input neutral current
IN Red Off Neutral current monitoring disabled
On Neutral current > threshold value

Table 70: LED status indicators

1) Depending on the configuration, a firmware update can take up to several minutes.

4.3.14.5 Pinout

r e
X20 AP 3111

U1 I1
U2 I2
U3 I3
IN

U L1 I L1a

U L2 I L1b

U L3 I L2a

I Na I L2b

I Nb I L3a

UN I L3b

Figure 127: Pinout

Danger!
Risk of electric shock!
The terminal block must only be allowed to conduct voltage when it is inserted. It must not under any
circumstances be removed or inserted when voltage is applied or have voltage applied to it when it
is removed.

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4.3.14.6 Current transformer

Potential-free measurement of the AC current requires a current transformer. The current transformer is a trans-
ducer that delivers a secondary signal proportional to the primary current. This secondary signal is measured by the
module. The maximum directly configurable primary current is 65 A. Values higher than 65 A can also be measured
by implementing a transformation in the software application (see explanation and example provided below).
The maximum secondary signal depends on the module:
Module Secondary current/voltage
X20AP3111 20 mA
X20AP3121 1A
X20AP3131 5A
X20AP3161 333 mV

The rated transformation ratio is calculated using the following formula:

primary nominal current
X20AP3111 - X20AP3221 - X20AP3131 Rated transformation ratio Kn =
secondary nominal current
X20AP3161 No transformation; the maximum primary current corresponds to the 333 mV

A smaller transformation ratio should be defined for measuring higher primary currents. The values calculated
by the module must be converted in the application according to the real rated transformation ratio that must be
defined.
Example: Currents of up to 100 A are flowing on the primary side. A current transformer with a rated
transformation ratio of 100/1 A is used. A rated transformation ratio of 50/1 A is defined in the
module to match the current transformer. If the primary current calculated by the module is 40 A,
then the actual value will be calculated as follows:

Actual primary current = 40 A * 100 / 50 = 80 A

Actual resolution = 1 mA * 100 / 50 = 2 mA
Note: The same factor must be used for all power ratings and energy values when making the
transformation.

Caution!
To prevent damaging the module, you must ensure the current inputs are electrically isolated. This is
done by connecting one transformer for each current input that is being used.
The current inputs on the module are not electrically isolated, so the secondary circuit between the
transformer and the module must not be grounded. Grounding would distort the measurement and
show current values that are too low!
Any other devices connected to this secondary circuit must also be electrically isolated (also see
Figure 129 "Input circuit diagram of current inputs")!

4.3.14.7 Voltage transformer

Voltage transformers are not provided in the configuration by default (e.g. by setting the transformation ratio).
They can, however, be used to measure higher voltages than the nominal voltages specified in the technical data.
Similar to current value correction (see 4.3.14.6 "Current transformer") the rated transformation ratio between
primary and secondary voltage should be calculated and applied.

Information:
The same factor must be used for all voltage values, power ratings and energy values when making
the transformation.

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4.3.14.8 Input circuit diagram

AC voltage inputs
Protective impedance Anti-aliasing filter

A/D Input value

U Lx
transformer

Filter

UN

Figure 128: Input circuit diagram of voltage inputs

AC current inputs
AP3111, AP3121, AP3131: (Current measurement)
External Measurement shunts Anti-aliasing filter
current transformer I xa
(current output)
A/D Input value
transformer
I xb

UN

Figure 129: Input circuit diagram of current inputs

AP3161: (Voltage measurement)
External Overvoltage protection Anti-aliasing filter
current transformer I xa
(voltage output)
A/D Input value
transformer
I xb

UN

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4.3.14.9 Typical connection examples for different mains configurations

General information
There are many different mains configurations around the world. This section will present a few typical connection
examples.

Connection example 1 - Mains A

This example involves a 3-element, 3-phase, 4-line star measurement with grounded neutral conductor and optional
fault current detection.

U L1

U L2

U L3

UN

I L1a

I L1b

I L2a

I L2b

I L3a

I L3b

I Na
optional
I Nb

L1 L2 L3 N

Figure 130: Supported mains configuration A

Connection example 2 - Mains B

This example involves a 3-element, 3-phase, 3-line star measurement.

U L1

U L2

U L3

UN

I L1a

I L1b

I L2a

I L2b

I L3a

I L3b

I Na

I Nb

L1 L2 L3

Figure 131: Supported mains configuration B

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Connection example 3 - Mains C

This example involves a 3-element, 3-phase, 3-line star measurement with grounded neutral conductor and optional
fault current detection.

U L1

U L2

U L3

UN

I L1a

I L1b

I L2a

I L2b

I L3a

I L3b

I Na
optional
I Nb

L1 L2 L3

Figure 132: Supported mains configuration C

Connection example 4 - Mains D

This example involves a 3-element, 3-phase, 4-line star measurement with optional fault current detection.

U L1

U L2

U L3

UN

I L1a

I L1b

I L2a

I L2b

I L3a

I L3b

I Na
optional
I Nb

L1 L2 L3 N

Figure 133: Supported mains configuration D

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Connection example 5 - Mains E

This example involves a 2-element, 2-phase, 3-line star measurement with grounded neutral line conductor.

U L1

U L2

U L3

UN

I L1a

I L1b

I L2a

I L2b

I L3a

I L3b

I Na
optional
I Nb

L1 L3 N

Figure 134: Supported mains configuration E

Connection example 6 - Mains F

This example involves a 3-element, 3-phase, 3-line delta measurement.

U L1

U L2

U L3

UN

I L1a

I L1b

I L2a

I L2b

I L3a

I L3b

I Na

I Nb

L1 L2 L3

Figure 135: Supported mains configuration F

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Connection example 7 - Mains G

This example involves a 3-element, 3-phase, 4-line delta measurement with grounded neutral.

Information:
The maximum voltage value specified in the data sheet must not be exceeded!

U L1

U L2

U L3

UN

I L1a

I L1b

I L2a

I L2b

I L3a

I L3b

I Na
optional
I Nb

L1 L2 L3 N

Figure 136: Supported mains configuration G

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4.3.14.10 Register description

4.3.14.10.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Standard register
2 PmeanT INT ●
4 QmeanT INT ●
6 SmeanT INT ●
8 AEnergyT DINT ●
12 REnergyT DINT ●
130 StatusInput UINT ●
CntPulseActive Bit 0
CntPulseApparent Bit 1
CntPulseActiveFund Bit 2
CntPulseActiveHarm Bit 3
ZeroCrossA Bit 4
ZeroCrossB Bit 5
ZeroCrossC Bit 6
RBTrigDFT Bit 8
RBUpdateEnergy Bit 9
RBClearEnergy Bit 10
RBForceEnergy Bit 11
194 ControlOutput UINT ●
TrigDFT Bit 0
EnabEnergy Bit 1
ClearEnergy Bit 2
ForceEnergy Bit 3
Analog status registers
266 SysStatus1 UINT ●
270 SysStatus2 UINT ●
274 SysStatus3 UINT ●
278 SysStatus4 UINT ●
265 SystemStatusSel01 USINT ●
SumStatusPhaseLoss Bit 2
SumStatusPhaseWarning Bit 3
ErrOrderPhasecurrent Bit 6
ErrOrderPhaseVoltage Bit 7
271 SystemStatusSel02 USINT ●
SumStatusWarningTHDCurrent Bit 2
SumStatusWarningTHDVoltage Bit 3
ErrIrmsNCalc Bit 6
ErrIrmsNMeas Bit 7
278 PhaseStatus UINT ●
LossPhaseC Bit 0
LossPhaseB Bit 1
LossPhaseA Bit 2
WarningPhaseC Bit 4
WarningPhaseB Bit 5
WarningPhaseA Bit 6
Analog RMS registers
290 IrmsN (measured) UINT ●
294 UrmsA UINT ●
298 UrmsB UINT ●
302 UrmsC UINT ●
306 IrmsNcalc (calculated) UINT ●
310 IrmsA UINT ●
314 IrmsB UINT ●
318 IrmsC UINT ●
Analog THD and angle registers
538 Freq UINT ●
542 PAngleA INT ●
546 PAngleB INT ●
550 PAngleC INT ●
554 Temperature INT ●
558 UAngleA INT ●
562 UAngleB INT ●
564 UAngleC INT ●
Analog power registers
778 PmeanT INT ●
782 PmeanA INT ●
786 PmeanB INT ●
790 PmeanC INT ●
794 QmeanT INT ●

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Register Name Data type Read Write
Cyclic Non-cyclic Cyclic Non-cyclic
798 QmeanA INT ●
802 QmeanB INT ●
806 QmeanC INT ●
810 SmeanT INT ●
814 SmeanA INT ●
818 SmeanB INT ●
822 SmeanC INT ●
826 PFmeanT INT ●
830 PFmeanA INT ●
834 PFmeanB INT ●
838 PFmeanC INT ●
Analog energy registers
4108 APenergyT UDINT ●
4116 APenergyA UDINT ●
4124 APenergyB UDINT ●
4132 APenergyC UDINT ●
4140 ANenergyT UDINT ●
4148 ANenergyA UDINT ●
4156 ANenergyB UDINT ●
4164 ANenergyC UDINT ●
4172 RPenergyT UDINT ●
4180 RPenergyA UDINT ●
4188 RPenergyB UDINT ●
4196 RPenergyC UDINT ●
4204 RNenergyT UDINT ●
4212 RNenergyA UDINT ●
4220 RNenergyB UDINT ●
4228 RNenergyC UDINT ●
4236 SAenergyT UDINT ●
4244 SenergyA UDINT ●
4252 SenergyB UDINT ●
4260 SenergyC UDINT ●
4268 SVenergyT UDINT ●
4404 AEnergyT DINT ●
4412 REnergyT DINT ●
Module configuration
1026 ChanControl UINT ●
1030 IDispTh UINT ●
1034 I_RatioA UINT ●
1038 I_RatioB UINT ●
1042 I_RatioC UINT ●
1046 I_RatioN UINT ●
1050 CfgUpdate UINT ●
1054 Cs0Update UINT ●
1058 Cs1Update UINT ●
1066 Cs3Update UINT ●
1570 Cs1UpdateFB UINT ●
1578 Cs3UpdateFB UINT ●
ADC status configuration
1090 ZXConfig UINT ●
1094 SagTh UINT ●
1098 PhaseLoseTh UINT ●
1102 INWarnTh0 UINT ●
1106 INWarnTh1 UINT ●
1110 THDNUTh UINT ●
1114 THDNITh UINT ●
ADC measurement configuration checksum 0
1154 PLconstH UINT ●
1158 PLconstL UINT ●
1162 MeteringMode UINT ●
ADC power calibration checksum 1
1246 PhiA_W UINT ●
1254 PhiB_W UINT ●
1262 PhiC_W UINT ●
ADC RMS comparison checksum 3
1346 UGainA_W UINT ●
1350 IGainA_W UINT ●
1354 UoffsetA_W INT ●
1358 IoffsetA_W INT ●
1362 UGainB_W UINT ●
1366 IGainB_W UINT ●
1370 UoffsetB_W INT ●
1374 IoffsetB_W INT ●

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Register Name Data type Read Write
Cyclic Non-cyclic Cyclic Non-cyclic
1378 UGainC_W UINT ●
1382 IGainC_W UINT ●
1386 UoffsetC_W INT ●
1390 IoffsetC_W INT ●
1394 IGainN_W UINT ●
1398 IoffsetN_W INT ●
ADC power calibration – read
1758 PhiA_R UINT ●
1766 PhiB_R UINT ●
1774 PhiC_R UINT ●
ADC RMS comparison – read
1858 UGainA_R UINT ●
1862 IGainA_R UINT ●
1866 UoffsetA_R INT ●
1870 IoffsetA_R INT ●
1874 UGainB_R UINT ●
1878 IGainB_R UINT ●
1882 UoffsetB_R INT ●
1886 IoffsetB_R INT ●
1890 UGainC_R UINT ●
1894 IGainC_R UINT ●
1898 UoffsetC_R INT ●
1902 IoffsetC_R INT ●
1906 IGainN_R UINT ●
1910 IoffsetN_R INT ●
FlatStream interface
2049 OutputMTU USINT ●
2051 InputMTU USINT ●
2055 FlatstreamMode USINT ●
2057 Forward USINT ●
2059 ForwardDelay USINT ●
2113 InputSequence USINT ●
2113 + 2*N RxByteN (Index N = 1 to 27) USINT ●
2177 OutputSequence USINT ●
2177 + 2*N TxByteN (Index N = 1 to 15) USINT ●
Force analog energy registers
2316 Frc_APenergyT UDINT ●
2324 Frc_APenergyA UDINT ●
2332 Frc_APenergyB UDINT ●
2340 Frc_APenergyC UDINT ●
2348 Frc_ANenergyT UDINT ●
2356 Frc_ANenergyA UDINT ●
2364 Frc_ANenergyB UDINT ●
2372 Frc_ANenergyC UDINT ●
2380 Frc_RPenergyT UDINT ●
2388 Frc_RPenergyA UDINT ●
2396 Frc_RPenergyB UDINT ●
2404 Frc_RPenergyC UDINT ●
2412 Frc_RNenergyT UDINT ●
2420 Frc_RNenergyA UDINT ●
2428 Frc_RNenergyB UDINT ●
2436 Frc_RNenergyC UDINT ●
2444 Frc_SAenergyT UDINT ●
2452 Frc_SenergyA UDINT ●
2460 Frc_SenergyB UDINT ●
2468 Frc_SenergyC UDINT ●
2476 Frc_SVenergyT UDINT ●
2484 Frc_APenergyTF UDINT ●
2492 Frc_APenergyAF UDINT ●
2500 Frc_APenergyBF UDINT ●
2508 Frc_APenergyCF UDINT ●
2516 Frc_ANenergyTF UDINT ●
2524 Frc_ANenergyAF UDINT ●
2532 Frc_ANenergyBF UDINT ●
2540 Frc_ANenergyCF UDINT ●
2548 Frc_APenergyTH UDINT ●
2556 Frc_APenergyAH UDINT ●
2564 Frc_APenergyBH UDINT ●
2572 Frc_APenergyCH UDINT ●
2580 Frc_ANenergyTH UDINT ●
2588 Frc_ANenergyAH UDINT ●
2596 Frc_ANenergyBH UDINT ●
2604 Frc_ANenergyCH UDINT ●

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Register Name Data type Read Write
Cyclic Non-cyclic Cyclic Non-cyclic
Oversampling buffer
Oversampling array[16]: Oversampling line
6146 + IactN_SampleN (Index N = 1 to 16) INT ●
((16-N)*40)
6150 + IactA_SampleN (Index N = 1 to 16) INT ●
((16-N)*40)
6154 + UactA_SampleN (Index N = 1 to 16) INT ●
((16-N)*40)
6158 + IactB_SampleN (Index N = 1 to 16) INT ●
((16-N)*40)
6162 + UactB_SampleN (Index N = 1 to 16) INT ●
((16-N)*40)
6166 + IactC_SampleN (Index N = 1 to 16) INT ●
((16-N)*40)
6170 + UactC_SampleN (Index N = 1 to 16) INT ●
((16-N)*40)
6773 SampleCountN SINT ●
6774 INT
6778 Timestamp INT ●
6780 DINT

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4.3.14.10.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Standard register
778 2 PmeanT INT ●
794 4 QmeanT INT ●
810 6 SmeanT INT ●
4404 8 AEnergyT DINT ●
4412 12 REnergyT DINT ●
130 0 StatusInput UINT ●
CntPulseActive Bit 0
CntPulseApparent Bit 1
CntPulseActiveFund Bit 2
CntPulseActiveHarm Bit 3
ZeroCrossA Bit 4
ZeroCrossB Bit 5
ZeroCrossC Bit 6
RBTrigDFT Bit 8
RBUpdateEnergy Bit 9
RBClearEnergy Bit 10
RBForceEnergy Bit 11
194 0 ControlOutput UINT ●
TrigDFT Bit 0
EnabEnergy Bit 1
ClearEnergy Bit 2
ForceEnergy Bit 3
Analog status registers
266 - SysStatus1 UINT ●
270 - SysStatus2 UINT ●
274 - SysStatus3 UINT ●
278 - SysStatus4 UINT ●
265 - SystemStatusSel01 USINT ●
SumStatusPhaseLoss Bit 2
SumStatusPhaseWarning Bit 3
ErrOrderPhasecurrent Bit 6
ErrOrderPhaseVoltage Bit 7
271 - SystemStatusSel02 USINT ●
SumStatusWarningTHDCurrent Bit 2
SumStatusWarningTHDVoltage Bit 3
ErrIrmsNCalc Bit 6
ErrIrmsNMeas Bit 7
278 - PhaseStatus UINT ●
LossPhaseC Bit 0
LossPhaseB Bit 1
LossPhaseA Bit 2
WarningPhaseC Bit 4
WarningPhaseB Bit 5
WarningPhaseA Bit 6
Analog RMS registers
290 - IrmsN (measured) UINT ●
294 - UrmsA UINT ●
298 - UrmsB UINT ●
302 - UrmsC UINT ●
306 - IrmsNcalc (calculated) UINT ●
310 - IrmsA UINT ●
314 - IrmsB UINT ●
318 - IrmsC UINT ●
Analog THD and angle registers
538 - Freq UINT ●
542 - PAngleA INT ●
546 - PAngleB INT ●
550 - PAngleC INT ●
554 - Temperature INT ●
558 - UAngleA INT ●
562 - UAngleB INT ●
564 - UAngleC INT ●
Analog power registers
778 - PmeanT INT ●
782 - PmeanA INT ●
786 - PmeanB INT ●
790 - PmeanC INT ●
794 - QmeanT INT ●
798 - QmeanA INT ●
802 - QmeanB INT ●

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Register Offset1) Name Data type Read Write
Cyclic Non-cyclic Cyclic Non-cyclic
806 - QmeanC INT ●
810 - SmeanT INT ●
814 - SmeanA INT ●
818 - SmeanB INT ●
822 - SmeanC INT ●
826 - PFmeanT INT ●
830 - PFmeanA INT ●
834 - PFmeanB INT ●
838 - PFmeanC INT ●
Analog energy registers
4108 - APenergyT UDINT ●
4116 - APenergyA UDINT ●
4124 - APenergyB UDINT ●
4132 - APenergyC UDINT ●
4140 - ANenergyT UDINT ●
4148 - ANenergyA UDINT ●
4156 - ANenergyB UDINT ●
4164 - ANenergyC UDINT ●
4172 - RPenergyT UDINT ●
4180 - RPenergyA UDINT ●
4188 - RPenergyB UDINT ●
4196 - RPenergyC UDINT ●
4204 - RNenergyT UDINT ●
4212 - RNenergyA UDINT ●
4220 - RNenergyB UDINT ●
4228 - RNenergyC UDINT ●
4236 - SAenergyT UDINT ●
4244 - SenergyA UDINT ●
4252 - SenergyB UDINT ●
4260 - SenergyC UDINT ●
4268 - SVenergyT UDINT ●
4404 - AEnergyT DINT ●
4412 - REnergyT DINT ●
Module configuration
1026 - ChanControl UINT ●
1030 - IDispTh UINT ●
1034 - I_RatioA UINT ●
1038 - I_RatioB UINT ●
1042 - I_RatioC UINT ●
1046 - I_RatioN UINT ●
1050 - CfgUpdate UINT ●
1054 - Cs0Update UINT ●
1058 - Cs1Update UINT ●
1066 - Cs3Update UINT ●
1570 - Cs1UpdateFB UINT ●
1578 - Cs3UpdateFB UINT ●
ADC status configuration
1090 - ZXConfig UINT ●
1094 - SagTh UINT ●
1098 - PhaseLoseTh UINT ●
1102 - INWarnTh0 UINT ●
1106 - INWarnTh1 UINT ●
1110 - THDNUTh UINT ●
1114 - THDNITh UINT ●
ADC measurement configuration checksum 0
1154 - PLconstH UINT ●
1158 - PLconstL UINT ●
1162 - MeteringMode UINT ●
ADC power calibration checksum 1
1246 - PhiA_W UINT ●
1254 - PhiB_W UINT ●
1262 - PhiC_W UINT ●
ADC RMS comparison checksum 3
1346 - UGainA_W UINT ●
1350 - IGainA_W UINT ●
1354 - UoffsetA_W INT ●
1358 - IoffsetA_W INT ●
1362 - UGainB_W UINT ●
1366 - IGainB_W UINT ●
1370 - UoffsetB_W INT ●
1374 - IoffsetB_W INT ●
1378 - UGainC_W UINT ●
1382 - IGainC_W UINT ●

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Register Offset1) Name Data type Read Write
Cyclic Non-cyclic Cyclic Non-cyclic
1386 - UoffsetC_W INT ●
1390 - IoffsetC_W INT ●
1394 - IGainN_W UINT ●
1398 - IoffsetN_W INT ●
ADC power calibration – read
1758 - PhiA_R UINT ●
1766 - PhiB_R UINT ●
1774 - PhiC_R UINT ●
ADC RMS comparison – read
1858 - UGainA_R UINT ●
1862 - IGainA_R UINT ●
1866 - UoffsetA_R INT ●
1870 - IoffsetA_R INT ●
1874 - UGainB_R UINT ●
1878 - IGainB_R UINT ●
1882 - UoffsetB_R INT ●
1886 - IoffsetB_R INT ●
1890 - UGainC_R UINT ●
1894 - IGainC_R UINT ●
1898 - UoffsetC_R INT ●
1902 - IoffsetC_R INT ●
1906 - IGainN_R UINT ●
1910 - IoffsetN_R INT ●
FlatStream interface
2049 - OutputMTU USINT ●
2051 - InputMTU USINT ●
2055 - FlatstreamMode USINT ●
2057 - Forward USINT ●
2059 - ForwardDelay USINT ●
2113 16 InputSequence USINT ●
2113 + 2*N 16 + N RxByteN (Index N = 1 to 7) USINT ●
2177 16 OutputSequence USINT ●
2177 + 2*N 16 + N TxByteN (Index N = 1 to 7) USINT ●
Force analog energy registers
2316 - Frc_APenergyT UDINT ●
2324 - Frc_APenergyA UDINT ●
2332 - Frc_APenergyB UDINT ●
2340 - Frc_APenergyC UDINT ●
2348 - Frc_ANenergyT UDINT ●
2356 - Frc_ANenergyA UDINT ●
2364 - Frc_ANenergyB UDINT ●
2372 - Frc_ANenergyC UDINT ●
2380 - Frc_RPenergyT UDINT ●
2388 - Frc_RPenergyA UDINT ●
2396 - Frc_RPenergyB UDINT ●
2404 - Frc_RPenergyC UDINT ●
2412 - Frc_RNenergyT UDINT ●
2420 - Frc_RNenergyA UDINT ●
2428 - Frc_RNenergyB UDINT ●
2436 - Frc_RNenergyC UDINT ●
2444 - Frc_SAenergyT UDINT ●
2452 - Frc_SenergyA UDINT ●
2460 - Frc_SenergyB UDINT ●
2468 - Frc_SenergyC UDINT ●
2476 - Frc_SVenergyT UDINT ●
2484 - Frc_APenergyTF UDINT ●
2492 - Frc_APenergyAF UDINT ●
2500 - Frc_APenergyBF UDINT ●
2508 - Frc_APenergyCF UDINT ●
2516 - Frc_ANenergyTF UDINT ●
2524 - Frc_ANenergyAF UDINT ●
2532 - Frc_ANenergyBF UDINT ●
2540 - Frc_ANenergyCF UDINT ●
2548 - Frc_APenergyTH UDINT ●
2556 - Frc_APenergyAH UDINT ●
2564 - Frc_APenergyBH UDINT ●
2572 - Frc_APenergyCH UDINT ●
2580 - Frc_ANenergyTH UDINT ●
2588 - Frc_ANenergyAH UDINT ●
2596 - Frc_ANenergyBH UDINT ●
2604 - Frc_ANenergyCH UDINT ●

1) The offset specifies the position of the register within the CAN object.

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4.3.14.10.3 General information

The modules are used for power monitoring and for a machine's energy management. Examples of where this
would be used:
• Multi-phase energy measurement for class 0.5S or class 1 for

° 3-phase, 4-line applications with neutral line (with/without grounding)

° 3-phase, 3-line applications (with/without grounding)
° 2-phase mains networks with grounded phase B connection
° ARON connection
• Single-phase measurement by disabling inputs that are not needed
• Mains analysis according to harmonic content
• Signal trace by 8 kHz recording of the 3 voltage channels and 4 current channels with FIFO

4.3.14.10.3.1 Measured value preparation

The modules provide the following possibilities for measured value preparation:
• IEC62052-11, IEC62053-22 and IEC62053-23, ANSI C12.1 and ANSI C12.20: Can be used for class 0.5S
or class 1 multi-phase wattmeter or class 2 multi-phase varmeter
• Precision of ±0.1% for real energy and ±0.02% for reactive energy over a range of 6000:1
• Temperature coefficient of internal reference of 6 ppm/°C
• Each phase can be calibrated for the active power
• Calibration not required for reactive power and apparent power
• Error ≤±0.5% for voltage, current, active-, reactive-, apparent power, frequency active power factor and
phase angle
• Energy registers for active, reactive and apparent energy, separated for forward and backward, fundamen-
tal waves and harmonics
• Threshold register for status signal generation and activation of power and energy measurement
• Determining the THD harmonic component
• Discrete Fourier Transformation (DFT) up to 31st harmonic component per phase for voltage and current
• Status signals for voltage dip, loss of voltage, phase sequence, energy flow, neutral current monitor, har-
monic component monitor

4.3.14.10.3.2 Additional information

Information Description
Measurement range monitoring Due to the majority of registers consisting of 16 bit values (exception: energy registers, which are interpolated
to 32 bit by the FW), the measurement ranges are subject to limitations, e.g. voltage 650.00 Vrms and current
65,000 Arms (after accounting for the transfer factor of the current transformer).
Extended measurement ranges Extended measurement ranges can be achieved with the software application by upscaling the measured values.
Frozen values Sample time register:
A NetTime is assigned to the group of measured values when read from the power meter. This NetTime can be
used to determine if the values have been frozen.
Environment variables The values for duty cycle, boot counter, and minimum / maximum transformer temperature are recorded.

4.3.14.10.3.3 Measurement function

The values measured for RMS, power, active power factor, phase angle and frequency are mean values over
16 full waves, the update rate is ~3 Hz.
The following represents the measurement time over 16 full waves at the corresponding frequency:
50 Hz ... 320 ms
60 Hz ... 267 ms

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Energy measurement

The power measurement (energy measurement) is based on the integration of the measured values with a sampling
rate of 1 MHz.
The collected energy values are made available as energy pulses with an adjustable resolution of 0.1 CF or 0.01 CF
values in the energy registers and with a resolution of 1 CF on the CF status flags.
The conversion can be defined using the PL constant. The default value 0x4A817C80 = 1.250.000.000 is equal
to 360 CF/kWh or 0.1 CF/kWs. Increasing the value causes the CF amount to decrease per energy unit (e.g.
0x53D1AC10 = 1.406.250.000 is equal to 320 CF/kWh). When choosing to display the values as kWh, a resolution
of 0.08789 CF/kWs is set internally and the register values are converted with a factor of 1/4096.
The energy threshold register (e.g. PStartTh) can be used to set the amount of energy needed to start an accu-
mulation or to reset the "no load" signals in the status registers. The length of the CF pulse can vary according
to the resulting output rate.
Automatic reading of the energy meter from the transformer must be enabled because valid values are only avail-
able after the transformer has been configured. It is possible to clear the energy register or to set it with a block
of the register written in the software application.
Tp = 80 ms

CFx

T ≥ 160 ms

Tp = 0.5 T

CFx

10 ms ≤ T < 160 ms

Tp = 5 ms

CFx

if T < 10 ms,
then T is set to 10 ms

Figure 137: The length of the CF pulse can vary according to the resulting output rate

Power measurement

The phase power ratings are calculated by the module and stored in the corresponding registers.
The total power ratings are equal to the sum of the phase power ratings. To prevent the number range from being
exceeded, the value in the registers is equal to a fourth of the actual power. This value must be multiplied by 4
by the application.
The vector-based total apparent power (complex total apparent power) is calculated according to IEEE1459.

Power factor

The phase power factor is calculated by dividing the phase active power by the phase apparent power.
The total power factor is calculated by dividing the total active power by the total apparent power.

Neutral current

The neutral current can be measured or calculated. Both values are available.

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The user can configure which one to use for displaying the status.

Phase angle

The phase angle is calculated based on the zero-crossing detection.

Frequency

Frequency measurement is based on Phase A. If A fails, then Phase C is used. If both A and C fail, then Phase
B is used.

Temperature

The Chip-Junction temperature is measured approximately every 100 ms using the sensor integrated in the trans-
former.

THD+N - Sum of interference power of the harmonic (THD) + interference power of the noise (N)

The THD+N measurement is used to monitor the percentage of harmonics in the network.
If this percentage falls below 10%, then an accuracy of 0.01% can no longer be guaranteed.
This is calculated as follows: (SQR (RMStotal^2 - RMSfundamental wave^2)) / RMSfundamental wave

Fourier analysis

The harmonic component from the 2nd to the 31st harmonic is calculated for voltage and current and the THD
(Total Harmonic Distortion) of each phase.
The DFT period is 0.5 s. This corresponds to a resolution of 2 Hz. The input samples are recorded at a sampling
rate of 8 kHz and can be optionally multiplied with a "Hann window" before being evaluated. This is initiated when
requested by the application.
Mains frequency Sampling frequency

Hanning Analysis of harmonics

window

Frequency Percentage-based
Input Scaling
Digital components for components of
samples Post-
X X Fourier fundamental wave fundamental wave
from the processing
Transformation and and
DSP processor
harmonics harmonics

Interface to the
oversampling
buffer

Interface for automatic

output of values

Figure 138: Diagram of Fourier analysis

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4.3.14.10.3.4 Event generation

Zero-crossing detection

Zero-crossing detection can be configured for each phase for cu or voltage and edge and forms the basis for
frequency and angle measurements and subsequently also for active and reactive power calculations.
U

TZX

ZX
positive zero crossing
TD

ZX
negative zero crossing

ZX
all zero crossings

Figure 139: Time diagram of zero-crossing detection per phase

Icon Description Minimum Typical Maximum Unit
TZX Length of high signal 5 ms
TD Delay time 0.2 0.5 ms

Table 71: Specification of zero-crossing detection

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Detection of voltage dip or power failure

Event Description
Voltage dip The threshold for voltage dips is typically set to 78% of the standard voltage (approx. 170 Vrms). The status flag is set if more
than three 8 kHz samples are below the threshold value within 2 consecutive 11 ms windows.
Power failure The threshold for voltage dips is typically set to 10% of the standard voltage (approx. 22 Vrms). The status flag is set if more than
three 8 kHz samples are below the threshold value within 2 consecutive 11 ms windows.
If a power failure is detected, then zero-crossing detection is disabled for voltage and current for this phase.

Voltage

+Threshold

Time
-Threshold

11 ms window Reason for voltage dip / power

failure found in 2 subsequent windows

IRQ
(if enabled)

Voltage dip / power failure

detected

Figure 140: Time diagram for detecting a voltage dip or power failure

Neutral current monitoring

Neutral current monitoring of the measured and the calculated value is done with separate threshold value registers
and status flags.

Phase sequence monitoring

3 phase and 2 phase applications are handled differently:

Application Description
3 phases Zero cross-overs of voltage and current must follow the sequence Phase A before Phase B before Phase C
2 phases Zero cross-overs of voltage and current must follow the sequence Phase A at least 180° before Phase C

Table 72: Phase sequence monitoring according to the application

4.3.14.10.3.5 Configuration registers

The configuration and calibration registers are each composed of blocks and employ a checksum feature to high-
light undesired changes. In order to apply this register to the transformer, the respective transfer register must be
changed after the data is transferred to the module (incrementing, bit toggling, etc.). The start value of the transfer
register is 0 after startup.

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4.3.14.10.4 Interface for transferring process variable mapping

Due to the amount of potential cyclic input data and the limitation to 30 byte cyclic X2X data, the extended Flat
Stream interface, DPS = Data Point Stream, has been defined as the mechanism for transferring the process
variables. DPS is based on the Flat Streaming Interface (FSI) for serial interface modules. The FSI was expanded
to include the block number as the first byte of the user data frame and implements the termination of a frame
(data image of the channel) with a zero segment.
The data blocks are re-transferred if a read request is triggered after a transfer has been completed. A block number
can be sent via the DPS to set a different block or transfer the entire image (default: block number 0).
It should be possible to adapt the DPS interface to the available buffer size. However, the higher-level fieldbus
must be taken into account when doing so (e.g.: CAN 8 byte object, InputMTU size 7). The block number is added
to the front of the actual payload data as a means to differentiate the blocks.
#define ADC_BLK_ALL 0 // struct ADC_REG
#define ADC_BLK_STATUS 1 // long NetTimeReg + struct ADC_REG_STATUS
#define ADC_BLK_RMS 2 // struct ADC_REG_RMS
#define ADC_BLK_POWER 3 // struct ADC_REG_POWER
#define ADC_BLK_THD_ANGLE 4 // struct THD_ANGLE
#define ADC_BLK_ENERGY 5 // long NetTimeEnergy + struct ADC_REG_ENERGY
#define ADC_BLK_DFT 6 // long NetTimeDft + struct ADC_REG_DFT
#define ADC_BLK_CFGACT 7 // struct ADC_REG_CFGACT
#define ADC_BLK_ENVREG 8 // struct ENV_STATUS

Information:
• Consistency of the data is only provided for the individual variables because the data is trans-
ferred from the AD converter asynchronously to the conversion.
• Make sure that the byte sequence of the register is in accordance with the Little Endian model
(Intel format).

The NetTime timestamps are always updated after the blocks are generated when preparing a new alternating
buffer.

4.3.14.10.4.1 Data block structure

ADC_REG

typedef struct ADC_REG ADC_REG;

struct ADC_REG
{
long NetTimeReg; // Time of Section copy to Buffer
ADC_REG_STATUS Status; // Status registers
ADC_REG_RMS Rms; // RMS Registers
ADC_REG_POWER Power; // Power Registers
ADC_REG_THD_ANGLE ThdAngle; // THD + Angle Registers

// Regular Energy Registers

long NetTimeEnergy; // Time of Section copy to Buffer
ADC_REG_ENERGY Energy; // Energy Registers

long NetTimeDft; // Time of Section copy to Buffer

ADC_REG_DFT Dft; // DFT Registers
// Read Back selected CFG Registers
ADC_REG_CFGACT CfgAct; // Config read back
// Read Back Environment Registers
ENV_STATUS EnvReg;
};

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ADC_REG_STATUS

typedef struct ADC_REG_STATUS ADC_REG_STATUS;

struct ADC_REG_STATUS
{
unsigned short SysStatus0; // System Status 0
unsigned short SysStatus1; // System Status 1
unsigned short EnStatus0; // Metering Status 0
unsigned short EnStatus1; // Metering Status 1
};

ADC_REG_RMS

typedef struct ADC_REG_RMS ADC_REG_RMS;

struct ADC_REG_RMS
{
unsigned short IrmsN1; // N Line Sampled current RMS
unsigned short UrmsA; // phase A voltage RMS
unsigned short UrmsB; // phase B voltage RMS
unsigned short UrmsC; // phase C voltage RMS
unsigned short IrmsN0; // N Line calculated current RMS
unsigned short IrmsA; // phase A voltage RMS
unsigned short IrmsB; // phase B voltage RMS
unsigned short IrmsC; // phase C voltage RMS
};

ADC_REG_POWER

typedef struct ADC_REG_POWER ADC_REG_POWER;

struct ADC_REG_POWER
{
unsigned short SVmeanTLSB; // LSB of (Vector Sum) Total Apparent Power
unsigned short SVmeanT; // (Vector Sum) Total Apparent Power

// Power and Power Factor Register

signed short PmeanT; // Total Active Power
signed short PmeanA; // Phase A Active Power
signed short PmeanB; // Phase B Active Power
signed short PmeanC; // Phase C Active Power
signed short QmeanT; // Total Reactive Power
signed short QmeanA; // Phase A Reactive Power
signed short QmeanB; // Phase B Reactive Power
signed short QmeanC; // Phase C Reactive Power
signed short SAmeanT; // (Arithmetic Sum) Total apparent power
signed short SmeanA; // phase A apparent power
signed short SmeanB; // phase B apparent power
signed short SmeanC; // phase C apparent power
signed short PFmeanT; // Total power factor
signed short PFmeanA; // phase A power factor
signed short PFmeanB; // phase A power factor
signed short PFmeanC; // phase A power factor

// Fundamental/ Harmonic Power and Voltage/ Current RMS Registers

signed short PmeanTF; // Total active fundamental power
signed short PmeanAF; // phase A active fundamental power
signed short PmeanBF; // phase B active fundamental power
signed short PmeanCF; // phase C active fundamental power
signed short PmeanTH; // Total active harmonic power
signed short PmeanAH; // phase A active harmonic power
signed short PmeanBH; // phase B active harmonic power
signed short PmeanCH; // phase C active harmonic power
};

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ADC_REG_THD_ANGLE

typedef struct ADC_REG_THD_ANGLE ADC_REG_THD_ANGLE;

struct ADC_REG_THD_ANGLE
{
// THD+N, Frequency, Angle and Temperature Registers
unsigned short THDNUA; // phase A voltage THD+N
unsigned short THDNUB; // phase B voltage THD+N
unsigned short THDNUC; // phase C voltage THD+N
unsigned short THDNIA; // phase A current THD+N
unsigned short THDNIB; // phase B current THD+N
unsigned short THDNIC; // phase C current THD+N
unsigned short Freq; // Frequency
signed short PAngleA; // phase A mean phase angle
signed short PAngleB; // phase B mean phase angle
signed short PAngleC; // phase C mean phase angle
signed short Temp; // Measured temperature
signed short UangleA; // phase A voltage phase angle
signed short UangleB; // phase B voltage phase angle
signed short UangleC; // phase C voltage phase angle
};

ADC_REG_ENERGY

typedef struct ADC_REG_ENERGY ADC_REG_ENERGY;

struct ADC_REG_ENERGY
{
unsigned long APenergyT; // Total Forward Active Energy
unsigned long APenergyA; // Phase A Forward Active Energy
unsigned long APenergyB; // Phase B Forward Active Energy
unsigned long APenergyC; // Phase C Forward Active Energy
unsigned long ANenergyT; // Total Reverse Active Energy
unsigned long ANenergyA; // Phase A Reverse Active Energy
unsigned long ANenergyB; // Phase B Reverse Active Energy
unsigned long ANenergyC; // Phase C Reverse Active Energy
unsigned long RPenergyT; // Total Forward Reactive Energy
unsigned long RPenergyA; // Phase A Forward Reactive Energy
unsigned long RPenergyB; // Phase B Forward Reactive Energy
unsigned long RPenergyC; // Phase C Forward Reactive Energy
unsigned long RNenergyT; // Total Reverse Reactive Energy
unsigned long RNenergyA; // Phase A Reverse Reactive Energy
unsigned long RNenergyB; // Phase B Reverse Reactive Energy
unsigned long RNenergyC; // Phase C Reverse Reactive Energy
unsigned long SAenergyT; // (Arithmetic Sum) Total Apparent Energy
unsigned long SenergyA; // Phase A Apparent Energy
unsigned long SenergyB; // Phase B Apparent Energy
unsigned long SenergyC; // Phase C Apparent Energy
unsigned long SVenergyT; // (Vector Sum) Total Apparent Energy

// Fundamental / Harmonic Energy Register

unsigned long APenergyTF; // Total Forward Active Fundamental Energy
unsigned long APenergyAF; // Phase A Forward Active Fundamental Energy
unsigned long APenergyBF; // Phase B Forward Active Fundamental Energy
unsigned long APenergyCF; // Phase C Forward Active Fundamental Energy
unsigned long ANenergyTF; // Total Reverse Active Fundamental Energy
unsigned long ANenergyAF; // Phase A Reverse Active Fundamental Energy
unsigned long ANenergyBF; // Phase B Reverse Active Fundamental Energy
unsigned long ANenergyCF; // Phase C Reverse Active Fundamental Energy
unsigned long APenergyTH; // Total Forward Active Harmonic Energy
unsigned long APenergyAH; // Phase A Forward Active Harmonic Energy
unsigned long APenergyBH; // Phase B Forward Active Harmonic Energy
unsigned long APenergyCH; // Phase C Forward Active Harmonic Energy
unsigned long ANenergyTH; // Total Reverse Active Harmonic Energy
unsigned long ANenergyAH; // Phase A Reverse Active Harmonic Energy
unsigned long ANenergyBH; // Phase B Reverse Active Harmonic Energy
unsigned long ANenergyCH; // Phase C Reverse Active Harmonic Energy

signed long AEnergyT; // Total Active Energy

signed long REnergyT; // Total Reactive Energy
};

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ADC_REG_DFT

typedef struct ADC_REG_DFT ADC_REG_DFT;

struct ADC_REG_DFT
{
// Arithmetic ratio, 2 bits integer and 14 bits fractional;
// That is: Harmonic Ratio (%) = Register Value / 163.84
unsigned short DftAI[32]; // phase A, Current, Harmonic Ratio for 2nd to 32nd
// order componentand Total Harmonic Distortion Ratio
unsigned short DftBI[32]; // phase B, Current, Harmonic Ratio for 2nd to 32nd
// order componentand Total Harmonic Distortion Ratio
unsigned short DftCI[32]; // phase C, Current, Harmonic Ratio for 2nd to 32nd
// order componentand Total Harmonic Distortion Ratio
unsigned short DftAV[32]; // phase A, Voltage, Harmonic Ratio for 2nd to 32nd
// order componentand Total Harmonic Distortion Ratio
unsigned short DftBV[32]; // phase B, Voltage, Harmonic Ratio for 2nd to 32nd
// order componentand Total Harmonic Distortion Ratio
unsigned short DftCV[32]; // phase C, Voltage, Harmonic Ratio for 2nd to 32nd
// order componentand Total Harmonic Distortion Ratio

// Format: Need special scaling/conversion.

//The register value * 147.62 = full-scale input signal RMS.
// Current, Fundamental component value = Register Value * 209 * 65.535 / 8388608
// Voltage, Fundamental component value = Register Value * 209 * 655.35 / 8388608

unsigned short DftAI_Fund;

unsigned short DftAV_Fund;
unsigned short DftBI_Fund;
unsigned short DftBV_Fund;
unsigned short DftCI_Fund;
unsigned short DftCV_Fund;
};

// Excerpt of configuration registers used by APROL, readable only by FS-IF

// and with register numbers of registers with the same names.

typedef struct ADC_REG_CFGACT ADC_REG_CFGACT;

struct ADC_REG_CFGACT
{
unsigned short ChanControl;
unsigned short IDispTh;
unsigned short I_RatioA;
unsigned short I_RatioB;
unsigned short I_RatioC;
unsigned short I_RatioN;
unsigned short ZXConfig;
unsigned short SagTh;
unsigned short PhaseLoseTh;
unsigned short INWarnTh0;
unsigned short INWarnTh1;
unsigned short THDNUTh;
unsigned short THDNITh;
unsigned short MeteringMode;
unsigned short PLconstL;
unsigned short PLconstH;
};

// Environment Variables

typedef struct ENV_STATUS ENV_STATUS;

struct ENV_STATUS
{
unsigned long ulUpTime;
unsigned long ulUpCnt;
signed short ssMinTemp;
signed short ssMaxTemp;
unsigned long ulRes[13];
};

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4.3.14.10.5 Standard register

4.3.14.10.5.1 Total active power

Name:
PmeanT
The value in the register equals a fourth of the actual power. The calculation can be performed in either absolute
or arithmetic mode (see register "MeteringMode" <Bit 3>). Each phase can be separately enabled for the power
calculation (see register "MeteringMode" <Bits 0, 1 and 2>).
Data type Value Information
INT -32,767 to 32,767 Resolution 4 W

This value must be multiplied by 4 by the application. Calculation formula for actual power:
Actual total active power = Register value * 4

4.3.14.10.5.2 Total reactive power

Name:
QmeanT
The value in the register equals a fourth of the actual power. The calculation can be performed in either absolute
or arithmetic mode (see register "MeteringMode" <Bit 4>). Each phase can be separately enabled for the power
calculation (see register "MeteringMode" <Bits 0, 1 and 2>).
Data type Value Information
INT -32,767 to 32,767 Resolution 4 var

This value must be multiplied by 4 by the application. Calculation formula for actual power:
Actual total reactive power = Register value * 4

4.3.14.10.5.3 Total apparent power

Name:
SmeanT
The value in the register equals a fourth of the actual power. The power is calculated in arithmetic mode. Each
phase can be separately enabled for the power calculation (see register "MeteringMode" <Bits 0, 1 and 2>).
Data type Value Information
INT 0 to 32767 Resolution 4 VA

This value must be multiplied by 4 by the application. Calculation formula for actual power:
Actual total apparent power = Register value * 4

4.3.14.10.5.4 Total active energy combined

Name:
AEnergyT
Total active energy in forward and backward direction.
Data type Value
DINT -2,147,483,647 to 2,147,483,647 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Internal calculation formula for the total active energy:

AEnergyT = (DINT)(APenergyT - ANenergyT) ... Calculation overflows must be handled in the application

4.3.14.10.5.5 Total reactive energy combined

Name:
REnergyT
Total reactive energy in forward and backward direction.
Data type Value Information
DINT -2,147,483,647 to 2,147,483,647 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Internal calculation formula for the total reactive energy:

REnergyT = (DINT)(RPenergyT - RNenergyT) ... Calculation overflows must be handled in the application

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4.3.14.10.5.6 Status signals and responses

Name:
StatusInput
The signals are recorded in 200 µs intervals.
Data type Value
UINT See bit structure

Bit structure:
Bit Name Value Information
0 CF1 energy pulse 1, total active energy 0 Not yet calculated
1 Calculated
1 CF2 energy pulse 2, total apparent energy, configurable 0 Not yet calculated
Standard: 1 Calculated
Arithmetic sum of apparent energy, can be reconfigured via reg-
ister <MeteringMode>
2 CF3 energy pulse 3, total active energy, fundamental wave 0 Not yet calculated
1 Calculated
3 CF4 energy pulse 4, total active energy, harmonics 0 Not yet calculated
1 Calculated
4 ZX1 zero cross signal – Phase A 0 Zero cross-over not detected
1 Standard:
Pulse at positive edge of the zero cross signal of the voltage
input, can be reconfigured via register "ZXConfig"
5 ZX2 zero cross signal – Phase B 0 Zero cross-over not detected
1 Standard:
Pulse at positive edge of the zero cross signal of the voltage
input, can be reconfigured via register "ZXConfig"
6 ZX3 zero cross signal – Phase C 0 Zero cross-over not detected
1 Standard:
Pulse at positive edge of the zero cross signal of the voltage
input, can be reconfigured via register "ZXConfig"
7 Reserved 0
8 DFT response sent x If the state in the register "ControlOutput" corresponds with the
response, then the action is complete
9 Energy value update response sent 0 No update
1 Update complete
10 Energy value response deleted x If the state in the register "ControlOutput" corresponds with the
response, then the action is complete
11 Energy value response set x If the state in the register "ControlOutput" corresponds with the
response, then the action is complete
12 - 15 Reserved 0

4.3.14.10.5.7 Control signals

Name:
ControlOutput
Control signals are evaluated in a ~5 ms interval.
Data type Value
UINT See bit structure

Bit structure:
Bit Name Value Information
0 DFT analysis 0 Don't start
1 Start1)
1 Automatically read energy values 0 Do not automatically read
1 Automatically read
2 Clear energy values 0 Don't delete
1 Delete1)
3 Set energy values 0 Don't start
1 Start1)
4 - 15 Reserved 0

1) If the state in the register "ControlOutput" corresponds with the response, then the action is complete.

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4.3.14.10.6 Analog status registers

4.3.14.10.6.1 Read timestamp for I/O register (+0x0022 = 16 bit)

Name:
SampleTime01_32bit
Network timestamp for the readout of the status, RMS, power register.
Data type Value Information
DINT -2,147,483,647 to 2,147,483,647 Network time

4.3.14.10.6.2 ADC system status 1

Name:
SysStatus1
The register is read by the converter in a ~5 ms interval.
Data type Value
UINT See bit structure

Bit structure:
Bit Name Value Information
0-1 Reserved 0
2 SumStatusPhaseLoss, voltage of one or more phases < failure 0 Voltage within permitted range
threshold in the register 1 Voltage lower than the failure threshold
3 SumStatusPhaseWarning, voltage of one or more phases < 0 Voltage within permitted range
warning threshold in the register 1 Voltage lower than the warning threshold
4-5 Reserved 0
6 ErrOrderPhasecurrent, error in the order of phase currents 0 No error
1 Error
7 ErrOrderPhaseVoltage, error in the order of phase voltages 0 No error
1 Error
8 CS3Err, checksum error in configuration block 3 0 No error
1 Error
9 Reserved 0
10 CS2Err, checksum error in configuration block 2 0 No error
1 Error
11 Reserved 0
12 CS1Err, checksum error in configuration block 1 0 No error
1 Error
13 Reserved 0
14 CS0Err, checksum error in configuration block 0 0 No error
1 Error
15 Reserved 0

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4.3.14.10.6.3 ADC system status 2

Name:
SysStatus2
Data type Value
UINT See bit structure

Bit structure:
Bit Name Value Information
0 RevPchgC, the direction of the active energy for phase C has 0 No change of direction
changed 1 Direction has changed
1 RevPchgB, the direction of the active energy for phase B has 0 No change of direction
changed 1 Direction has changed
2 RevPchgA, the direction of the active energy for phase A has 0 No change of direction
changed 1 Direction has changed
3 RevPchgT, the direction of the active energy for the total has 0 No change of direction
changed 1 Direction has changed
4 RevQchgC, the direction of the reactive energy for phase C has 0 No change of direction
changed 1 Direction has changed
5 RevQchgB, the direction of the reactive energy for phase B has 0 No change of direction
changed 1 Direction has changed
6 RevQchgA, the direction of the reactive energy for phase A has 0 No change of direction
changed 1 Direction has changed
7 RevQchgT, the direction of the reactive energy for the total has 0 No change of direction
changed 1 Direction has changed
8 Reserved 0
9 DFTDone, DFT analysis complete (temporary bit) 0 DFT analysis not complete
1 DFT analysis complete
10 SumStatusWarningTHDCurrent, the THDIx value of one or more 0 THDIx value within permitted range
phases > warning threshold in the register 1 THDIx value higher than warning threshold
11 SumStatusWarningTHDVoltage, the THDUx value of one or 0 THDUx value within permitted range
more phases > warning threshold in the register 1 THDUx value higher than warning threshold
12 - 13 Reserved 0
14 ErrIrmsNCalc, the calculated value of the neutral line > warning 0 Calculated value within permitted range
threshold in the Register 1 Calculated value higher than warning threshold
15 ErrIrmsNMeas, the measured value of the neutral line > warning 0 Measured value within permitted range
threshold in the Register 1 Measured value higher than warning threshold

4.3.14.10.6.4 ADC system status 3

Name:
SysStatus3
Data type Value
UINT See bit structure

Bit structure:
Bit Name Value Information
0 CF1RevFlag, direction of CF signal 0 Forward1)
1 Back2)
1 CF2RevFlag, direction of CF signal 0 Forward1)
1 Back2)
2 CF3RevFlag, direction of CF signal 0 Forward1)
1 Back2)
3 CF4RevFlag, direction of CF signal 0 Forward1)
1 Back2)
4 - 11 Reserved 0
12 TVSNoload, vector-based total apparent power of all phases in 0 Status with load
"No load" state 1 Status without load
13 TASNoload, total apparent power of all phases in "No load" state 0 Status with load
1 Status without load
14 TPNoload, total active power of all phases in "No load" state 0 Status with load
1 Status without load
15 TQNoload, total reactive power of all phases in "No load" state 0 Status with load
1 Status without load

1) Forward direction of CF pulse (positive sign of corresponding energy register)

2) Reverse direction of CF pulse (negative sign of corresponding energy register)

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4.3.14.10.6.5 ADC system status 4

Name:
SysStatus4
Data type Value
UINT See bit structure

Bit structure:
Bit Name Value Information
0 LossPhaseC, voltage lower than value in the register 0 Voltage is higher
"PhaseLoseTh" 1 Voltage is lower
1 LossPhaseB, voltage lower than value in the register 0 Voltage is higher
"PhaseLoseTh" 1 Voltage is lower
2 LossPhaseA, voltage lower than value in the register 0 Voltage is higher
"PhaseLoseTh" 1 Voltage is lower
3 Reserved 0
4 WarningPhaseC, voltage lower than value in the register 0 Voltage is higher
"SagTh" 1 Voltage is lower
5 WarningPhaseB, voltage lower than value in the register 0 Voltage is higher
"SagTh" 1 Voltage is lower
6 WarningPhaseA, voltage lower than value in the register 0 Voltage is higher
"SagTh" 1 Voltage is lower
7 - 15 Reserved 0

4.3.14.10.6.6 ADC system status 1

Name:
SystemStatusSel01
The most important bits of the "SysStatus1" register are stored in this register.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Value Information
0-1 Reserved 0
2 SumStatusPhaseLoss, voltage of one or more phases < failure 0 Voltage within permitted range
threshold in the register 1 Voltage lower than the failure threshold
3 SumStatusPhaseWarning, voltage of one or more phases < 0 Voltage within permitted range
warning threshold in the register 1 Voltage lower than the warning threshold
4-5 Reserved 0
6 ErrOrderPhasecurrent, error in the order of phase currents 0 No error
1 Error
7 ErrOrderPhaseVoltage, error in the order of phase voltages 0 No error
1 Error

4.3.14.10.6.7 ADC system status 2

Name:
SystemStatusSel02
The most important bits of the "SysStatus2" register are stored in this register.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Value Information
0-1 Reserved 0
2 SumStatusWarningTHDCurrent, the THDIx value of one or more 0 THDIx value within permitted range
phases > warning threshold in the register 1 THDIx value higher than warning threshold
3 SumStatusWarningTHDVoltage, the THDUx value of one or 0 THDUx value within permitted range
more phases > warning threshold in the register 1 THDUx value higher than warning threshold
4-5 Reserved 0
6 ErrIrmsNCalc, the calculated value of the neutral line > warning 0 Calculated value within permitted range
threshold in the Register 1 Calculated value higher than warning threshold
7 ErrIrmsNMeas, the measured value of the neutral line > warning 0 Measured value within permitted range
threshold in the Register 1 Measured value higher than warning threshold

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4.3.14.10.6.8 Phase status

Name:
PhaseStatus
This register corresponds to the SysStatus4 register. It contains the status of phases A, B und C.
Data type Value
UINT See bit structure

Bit structure:
Bit Name Value Information
0 LossPhaseC, voltage lower than value in the register 0 Voltage is higher
"PhaseLoseTh" 1 Voltage is lower
1 LossPhaseB, voltage lower than value in the register 0 Voltage is higher
"PhaseLoseTh" 1 Voltage is lower
2 LossPhaseA, voltage lower than value in the register 0 Voltage is higher
"PhaseLoseTh" 1 Voltage is lower
3 Reserved 0
4 WarningPhaseC, voltage lower than value in the register 0 Voltage is higher
"SagTh" 1 Voltage is lower
5 WarningPhaseB, voltage lower than value in the register 0 Voltage is higher
"SagTh" 1 Voltage is lower
6 WarningPhaseA, voltage lower than value in the register 0 Voltage is higher
"SagTh" 1 Voltage is lower
7 - 15 Reserved 0

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4.3.14.10.7 Analog RMS registers

4.3.14.10.7.1 Current RMS neutral line measured

Name:
IrmsN
Measured value of the neutral current between the P and N connections on the current terminal, multiplied with
the transfer factor of the transformer.
Data type Value Information
UINT 0 to 65,535 Measured value 0.001 Arms

4.3.14.10.7.2 Voltage RMS phase A/B/C

Name:
UrmsA
UrmsB
UrmsC
Measured value for N-terminal or virtual zero point.
Data type Value Information
UINT 0 to 65,535 Measured value 0.01 Vrms

4.3.14.10.7.3 Current RMS neutral line calculated

Name:
IrmsNcalc
Calculated value of neutral current derived from the other 3 phases.
Data type Value Information
UINT 0 to 65,535 Measured value 0.001 Arms

4.3.14.10.7.4 Current RMS phase A/B/C

Name:
IrmsA
IrmsB
IrmsC
Measured value of the phase current between the P and N connections on the current terminal, multiplied with
the transfer factor of the transformer.
Data type Value Information
UINT 0 to 65,535 Measured value 0.001 Arms

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4.3.14.10.8 Analog THD and angle registers

4.3.14.10.8.1 THD+N value voltage phase A/B/C

Name:
THDNUA
THDNUB
THDNUC
Data type Value Information
UINT 0 to 10000 Resolution 0.01%

Harmonic content = (SQR(Rmstotal^2 - Rmsfundamental^2))/Rmsfundamental

4.3.14.10.8.2 THD+N value current phase A/B/C

Name:
THDNIA
THDNIB
THDNIC
Data type Value Information
UINT 0 to 10000 Resolution 0.01%

Harmonic content = (SQR(Rmstotal^2 - Rmsfundamental^2))/Rmsfundamental

4.3.14.10.8.3 Fundamental frequency measured

Name:
Freq
Measured fundamental frequency of phases A, B and C.
Data type Value Information
UINT 0 to 10000 Resolution 0.01 Hz

4.3.14.10.8.4 Phase angle of power on phase A/B/C

Name:
PAngleA
PAngleB
PAngleC
Middle phase angle (power angle) of the current to the voltage based on the zero-crossing detection.
Data type Value Information
INT -1800 to 1800 Resolution 0.1°

4.3.14.10.8.5 Transformer temperature

Name:
Temperature
This register contains the internal temperature of the transformer component. The temperature is recorded in a
100 ms interval.
Data type Value Information
INT -200 to 200 Resolution 1°C

4.3.14.10.8.6 Phase angle of voltage on phase A/B/C

Name:
UAngleA
UAngleB
UAngleC
The value for phase A is always 0. On the other phases, the angle corresponds with the offset to A. This is based
on the zero-crossing detection.
Data type Value Information
INT -1800 to 1800 Resolution 0.1°

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4.3.14.10.9 Analog power register

4.3.14.10.9.1 Vector sum of the total apparent power LSW

Name:
SVmeanTLSB
The value in the register equals a fourth of the actual power.
Data type Value Information
INT -32,767 to 32,767 Resolution of units/LSB equals 4/65536 VA

This value must be multiplied by 4 by the application. Calculation formula for actual power:
Actual vector sum of the total apparent power LSW = register value * 4 (complex sum)

4.3.14.10.9.2 Vector sum of the total apparent power MSW

Name:
SVmeanT
The value in the register equals a fourth of the actual power. The calculation is made in accordance with IEEE 1459.
Data type Value Information
INT 0 to 32767 Resolution 4 VA

This value must be multiplied by 4 by the application. Calculation formula for actual power:
Actual vector sum of the total apparent power MSW = register value * 4 (complex sum)

4.3.14.10.9.3 Total active power

Name:
PmeanT
The value in the register equals a fourth of the actual power. The calculation can be performed in either absolute
or arithmetic mode (see register "MeteringMode" <Bit 3>). Each phase can be separately enabled for the power
calculation (see register "MeteringMode" <Bits 0, 1 and 2>).
Data type Value Information
INT -32,767 to 32,767 Resolution 4 W

This value must be multiplied by 4 by the application. Calculation formula for actual power:
Actual total active power = Register value * 4

4.3.14.10.9.4 Active power on phase A/B/C

Name:
PmeanA
PmeanB
PmeanC
Active power on the phase. Each phase can be separately enabled for the power calculation (see register "Meter-
ingMode" <Bits 0, 1 and 2>).
Data type Value Information
INT -32,767 to 32,767 Resolution 1 W

4.3.14.10.9.5 Total reactive power

Name:
QmeanT
The value in the register equals a fourth of the actual power. The calculation can be performed in either absolute
or arithmetic mode (see register "MeteringMode" <Bit 4>). Each phase can be separately enabled for the power
calculation (see register "MeteringMode" <Bits 0, 1 and 2>).
Data type Value Information
INT -32,767 to 32,767 Resolution 4 var

This value must be multiplied by 4 by the application. Calculation formula for actual power:
Actual total reactive power = Register value * 4

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4.3.14.10.9.6 Reactive power on phase A/B/C

Name:
QmeanA
QmeanB
QmeanC
Reactive power on the phase. Each phase can be separately enabled for the power calculation (see register
"MeteringMode" <Bits 0, 1 and 2>).
Data type Value Information
INT -32,767 to 32,767 Resolution 1 var

4.3.14.10.9.7 Total apparent power

Name:
SmeanT
The value in the register equals a fourth of the actual power. The power is calculated in arithmetic mode. Each
phase can be separately enabled for the power calculation (see register "MeteringMode" <Bits 0, 1 and 2>).
Data type Value Information
INT 0 to 32767 Resolution 4 VA

This value must be multiplied by 4 by the application. Calculation formula for actual power:
Actual total apparent power = Register value * 4

4.3.14.10.9.8 Apparent power on phase A/B/C

Name:
SmeanA
SmeanB
SmeanC
Apparent power on the phase. Each phase can be separately enabled for the power calculation (see register
"MeteringMode" <Bits 0, 1 and 2>).
Data type Value Information
INT 0 to 32767 Resolution 1 VA

4.3.14.10.9.9 Total power factor

Name:
PFmeanT
Data type Value Information
INT -1000 to 1000 Resolution 0.001

4.3.14.10.9.10 Power factor on phase A/B/C

Name:
PFmeanA
PFmeanB
PFmeanC
Data type Value Information
INT -1000 to 1000 Resolution 0.001

4.3.14.10.9.11 Total active power of fundamental wave

Name:
PmeanTF
The value in the register equals a fourth of the actual power.
Data type Value Information
INT -32,767 to 32,767 Resolution 4 W

This value must be multiplied by 4 by the application. Calculation formula for actual power:
Actual total active power of fundamental wave = Register value * 4

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4.3.14.10.9.12 Fundamental wave active power on phase A/B/C

Name:
PmeanAF
PmeanBF
PmeanCF
Active power of fundamental wave on the phase.
Data type Value Information
INT -32,767 to 32,767 Resolution 1 W

4.3.14.10.9.13 Total active power of harmonics

Name:
PmeanTH
The value in the register equals a fourth of the actual power.
Data type Value Information
INT -32,767 to 32,767 Resolution 4 W

This value must be multiplied by 4 by the application. Calculation formula for actual power:
Actual total active power of harmonics = Register value * 4

4.3.14.10.9.14 Harmonics active power on phase A/B/C

Name:
PmeanAH
PmeanBH
PmeanCH
Active power of harmonics on the phase.
Data type Value Information
INT -32,767 to 32,767 Resolution 1 W

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4.3.14.10.10 Analog energy registers

4.3.14.10.10.1 Read timestamp for energy registers (+0x0022 = 16 bit)

Name:
SampleTime02_32bit
Network timestamp for the readout of the energy register.
Data type Value Information
DINT -2,147,483,647 to 2,147,483,647 Network time

4.3.14.10.10.2 Forward total active energy

Name:
APenergyT
Total active energy in forward direction.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

4.3.14.10.10.3 Forward active energy on phase A/B/C

Name:
APenergyA
APenergyB
APenergyC
Active energy in forward direction of the phase.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

4.3.14.10.10.4 Reverse total active energy

Name:
ANenergyT
Total active energy in reverse direction.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

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4.3.14.10.10.5 Reverse active energy on phase A/B/C

Name:
ANenergyA
ANenergyB
ANenergyC
Active energy in reverse direction of the phase.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

4.3.14.10.10.6 Forward total reactive energy

Name:
RPenergyT
Total reactive energy in forward direction.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

4.3.14.10.10.7 Forward reactive energy on phase A/B/C

Name:
RPenergyA
RPenergyB
RPenergyC
Reactive energy in forward direction of the phase.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

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4.3.14.10.10.8 Reverse total reactive energy

Name:
RNenergyT
Total reactive energy in reverse direction.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

4.3.14.10.10.9 Reverse reactive energy on phase A/B/C

Name:
RNenergyA
RNenergyB
RNenergyC
Reactive energy in reverse direction of the phase.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

4.3.14.10.10.10 Arithmetic total apparent energy

Name:
SAenergyT
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

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4.3.14.10.10.11 Apparent energy on phase A/B/C

Name:
SenergyA
SenergyB
SenergyC
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

4.3.14.10.10.12 Vectorized total apparent energy

Name:
SVenergyT
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

4.3.14.10.10.13 Forward fundamental wave total active energy

Name:
APenergyTF
Fundamental wave of total active energy in forward direction.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

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4.3.14.10.10.14 Forward fundamental wave active energy on phase A/B/C

Name:
APenergyAF
APenergyBF
APenergyCF
Fundamental wave of active energy in forward direction of the phase.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

4.3.14.10.10.15 Reverse fundamental wave total active energy

Name:
ANenergyTF
Fundamental wave of total active energy in reverse direction.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

4.3.14.10.10.16 Reverse fundamental wave active energy on phase A/B/C

Name:
ANenergyAF
ANenergyBF
ANenergyCF
Fundamental wave of active energy in reverse direction of the phase.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

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4.3.14.10.10.17 Forward harmonics total active energy

Name:
APenergyTH
Harmonics of total active energy in forward direction.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

4.3.14.10.10.18 Forward harmonics active energy on phase A/B/C

Name:
APenergyAH
APenergyBH
APenergyCH
Harmonics of active energy in forward direction of the phase.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

4.3.14.10.10.19 Reverse harmonics total active energy

Name:
ANenergyTH
Harmonics of total active energy in reverse direction.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

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4.3.14.10.10.20 Reverse harmonics active energy on phase A/B/C

Name:
ANenergyAH
ANenergyBH
ANenergyCH
Harmonics of active energy in reverse direction of the phase.
Data type Value Information
UDINT 0 to 4,294,967,295 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

4.3.14.10.10.21 Total active energy combined

Name:
AEnergyT
Total active energy in forward and backward direction.
Data type Value Information
DINT -2,147,483,647 to 2,147,483,647 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Internal calculation formula for the total active energy:

AEnergyT = (DINT)(APenergyT - ANenergyT) ... Calculation overflows must be handled in the application
Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

4.3.14.10.10.22 Total reactive energy combined

Name:
REnergyT
Total reactive energy in forward and backward direction.
Data type Value Information
DINT -2,147,483,647 to 2,147,483,647 Resolution 0.1 or 0.01 CF, depending on the Power Line factor (e.g. kWs)

Internal calculation formula for the total reactive energy:

REnergyT = (DINT)(RPenergyT - RNenergyT) ... Calculation overflows must be handled in the application
Comments:
• The unit CF is derived from the Power Line factor (default: 3600 Imp/kWh), see register "MeteringMode"
• The resolution can be switched between 0.1 and 0.01, see register "MeteringMode"
• The register is updated automatically after being enabled, see register "ControlOutput" <Bit 1>
• The register is cleared upon request, see register "ControlOutput"
• The register is set upon request, see register "ControlOutput" <Bit 3>

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4.3.14.10.11 Analog DFT registers

4.3.14.10.11.1 Read timestamp for DFT register (+0x0022 = 16 bit)

Name:
SampleTime03_32bit
Network timestamp for the readout of the DFT register.
Data type Value Information
DINT -2,147,483,647 to 2,147,483,647 Network time

4.3.14.10.11.2 Current HRn register for phase A/B/C

Name:
AI_HRN (2..32)
BI_HRN (2..32)
CI_HRN (2..32)
Ratio of harmonics.
Data type Value Information
UINT 0 to 32767 Ratio of frequency component

Conversion from % = register value / 163.84

4.3.14.10.11.3 Current THD register for phase A/B/C

Name:
DFT_AI_THD
DFT_BI_THD
DFT_CI_THD
Ratio of total harmonic distortion.
Data type Value Information
UINT 0 to 32767 Total harmonic distortion on phase A current

Conversion from % = register value / 163.84

4.3.14.10.11.4 Fundamental wave current on phase A/B/C

Name:
DftAI_Fund
DftBI_Fund
DftCI_Fund
Data type Value Information
UINT 0 to 32767 Fundamental wave current

Conversion of fundamental wave current = register value * 209 * 65535 / 8388608

4.3.14.10.11.5 Fundamental wave voltage on phase A/B/C

Name:
DftAV_Fund
DftBV_Fund
DftCV_Fund
Data type Value Information
UINT 0 to 32767 Fundamental value voltage

Conversion of fundamental wave voltage = register value * 209 * 65535 / 8388608

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4.3.14.10.12 Module configuration

4.3.14.10.12.1 Analog mode register

Name:
ChanControl
Data type Value
UINT See bit structure

Bit structure:
Bit Name Value Information
0 Channel status LED for phase A 0 Disabled
1 Enabled1)
1 Channel status LED for phase B 0 Disabled
1 Enabled1)
2 Channel status LED for phase C 0 Disabled
1 Enabled1)
3 Reserved 0
4 Neutral current monitor and status LED 0 Disabled
1 Enabled1)
5 Neutral current status derived from the calculated or measured 0 Derived from the calculated value1)
value 1 Derived from the calculated value
6 Conversion of energy register to kWh (internal register / 4096) 0 Disabled
1 Enabled
7 Display current values despite power failure2) 0 Disabled3), Current values = 0
1 Enabled
8 - 15 Oversampling with prescaler 0 Disabled1), Current values = 0
1 - 255 Enabled, Display current values despite power failure

1) Standard in the bus controller function model

2) When a power failure occurs, all current values are held at 0 by default.
3) According to the power failure status of the individual phases, the following values are held at 0 by default.

• Mains frequency, phase angle, power factor

• Effective voltage and current values
• Active, reactive and apparent power values

4.3.14.10.12.2 Analog minimum current for active current channel LED

Name:
IDispTh
Data type Value Information
UINT 100 to 65000 I RMS indicator threshold

The indicator threshold defines the RMS value of the current at which the status LED for the phase current is
illuminated. The default values vary from module to module and should be adjusted to the maximum primary
current. Suggestion: 1% of maximum value
Module Indicator threshold
X20AP3111 200 mA
X20AP3121 500 mA
X20AP3131 500 mA
X20AP3161 500 mA

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4.3.14.10.12.3 Current transformer rating phase A/B/C/N

Name:
I_RatioA
I_RatioB
I_RatioC
I_RatioN
Data type Value Information
UINT 10 to x Current transformer rating

In the modules AP311, 21 and 31, the rated current is multiplied by the rated transformation ratio. In the module
AP3161, the maximum primary current of the transformer is configured directly.
The permissible values differ from module to module (resolution 0.1):
Module Rating
X20AP3111 Transformer ratio: 10 to 32,500 (default: 25000)
X20AP3121 Transformer ratio: 10 to 650 (default: 500)
X20AP3131 Transformer ratio: 10 to 130 (default: 100)
X20AP3161 Measurement range: 50 to 650 (default: 500)

Information:
The maximum resulting current must not exceed the value of 65000 mA.

4.3.14.10.12.4 Update request ADC Cfg register

Name:
CfgUpdate
The registers in the group CfgReg are only updated after the CfgUpdate register is changed. Setting 0xFFFF only
causes this register to be reset without updating the CfgReg register.
Data type Value Information
UINT 0 to 65,535 Update request

4.3.14.10.12.5 Update request ADC Cs0, Cs1 and Cs3 register

Name:
Cs0Update
Cs1Update
Cs3Update
The registers in the group CsxReg are only updated after the CsxUpdate register is changed. Setting 0xFFFF only
causes this register to be reset without updating the CsxReg register.
Data type Value Information
UINT 0 to 65,535 Update request

Name:
Cs1UpdateFB
Cs3UpdateFB
The ADC configuration registers are only transferred to the feedback buffer after transfer to the ADC is complete.
Data type Value Information
UINT 0 to 65,535

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4.3.14.10.13 ADC status configuration

4.3.14.10.13.1 ADC hardware signal allocation

Name:
ZXConfig
Data type Value
UINT See bit structure

Bit structure:
Bit Name Value Information
0 Zero cross signals 0 Enabled
1 Disabled
1-2 ZX20Con: Trigger zero cross-over 00 Positive zero cross-over1)
01 Negative zero cross-over
10 Both zero cross-overs
11 No zero cross-over
3-4 ZX1Con: Trigger zero cross-over 00 Positive zero cross-over1)
01 Negative zero cross-over
10 Both zero cross-overs
11 No zero cross-over
5-6 ZX2Con: Trigger zero cross-over 00 Positive zero cross-over1)
01 Negative zero cross-over
10 Both zero cross-overs
11 No zero cross-over
7-9 ZX0Src: Signal source for ZX0 hardware signal 000 A voltage1)
001 B voltage
010 C voltage
011 Fix 0
100 Current A
101 Current B
110 Current C
111 Fix 0
10 - 12 ZX1Src: Signal source for ZX1 hardware signal 000 A voltage
001 B voltage1)
010 C voltage
011 Fix 0
100 Current A
101 Current B
110 Current C
111 Fix 0
13 - 15 ZX2Src: Signal source for ZX2 hardware signal 000 A voltage
001 B voltage
010 C voltage1)
011 Fix 0
100 Current A
101 Current B
110 Current C
111 Fix 0

1) Standard in the bus controller function model

4.3.14.10.13.2 Voltage warning threshold

Name:
SagTh
Data type Value Information
UINT 5000 to 50000 Resolution 0.01 V

This register defines an RMS voltage value for monitoring the voltage warning signal.

4.3.14.10.13.3 Power failure threshold

Name:
PhaseLoseTh
Data type Value Information
UINT 1000 to 6000 Resolution 0.01 V

This register defines an RMS voltage value for monitoring the power failure signal.

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4.3.14.10.13.4 Warning threshold for the calculated neutral current

Name:
INWarnTh0
Current value for monitoring the calculated neutral line current.
Data type Value Information
UINT 0 to 65000 Resolution 0.001 A

4.3.14.10.13.5 Warning threshold for the measured neutral current.

Name:
INWarnTh1
Current value for monitoring the measured neutral line current.
Data type Value Information
UINT 0 to 65000 Resolution 0.001 A

4.3.14.10.13.6 Warning threshold for exceeding voltage THD

Name:
THDNUTh
Percentage value defining warning threshold for THD ratio.
Data type Value Information
UINT 0 to 10000 Resolution 0.01%

4.3.14.10.13.7 Warning threshold for exceeding current THD

Name:
THDNITh
Percentage value defining warning threshold for THD ratio.
Data type Value Information
UINT 0 to 10000 Resolution 0.01%

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4.3.14.10.14 ADC measurement configuration checksum 0

4.3.14.10.14.1 High word for power line constants

Name:
PLconstH
Data type Value
UINT 0 to 65,535

Basis value of power line constant = 0x4A817C80 = 1,250,000,000 corresponding to 360 CF pulses per kWh
or 0.1 CF pulse per kWs. The result of setting the resolution in the energy registers to a decimal (see register
"MeteringMode" <Bit 9>) is 1 kWs per digit. Power line constant / 10 results in a 10x resolution.

4.3.14.10.14.2 Low word for power line constants

Name:
PLconstL
Data type Value
UINT 0 to 65,535

Basis value of power line constant = 0x4A817C80 = 1,250,000,000 corresponding to 360 CF pulses per kWh
or 0.1 CF pulse per kWs. The result of setting the resolution in the energy registers to a decimal (see register
"MeteringMode" <Bit 9>) is 1 kWs per digit. Power line constant / 10 results in a 10x resolution.

4.3.14.10.14.3 Analog ADC measurement setting 1

Name:
MeteringMode
Data type Value
UINT See bit structure

Bit structure:
Bit Name Value Information
0 Enables phase C for adding the power and energy values to- 0 Not enabled
gether 1 Approved1)
1 Enables phase B for adding the power and energy values to- 0 Not enabled
gether 1 Approved1)
2 Enables phase A for adding the power and energy values to- 0 Not enabled
gether 1 Approved1)
3 Calculation method for adding active power and active energy 0 Arithmetic sum1)
1 Absolute sum
4 Calculation method for adding reactive power and reactive en- 0 Arithmetic sum1)
ergy 1 Absolute sum
5 Reserved 0
6 Selects apparent energy for CF2 source 0 Arithmetic sum1)
1 Vector sum
7 CF2 source 0 Apparent energy
1 Reactive energy1)
8 Measuring configuration 0 3P4W1)
1 3P3W
9 Resolution of energy register 0 0.1 CF1)
1 0.01 CF
10 Integrator for didt current transformer 0 Disabled
1 Enabled
11 High-pass filter 0 Enabled
1 Disabled
12 Basis frequency 0 50 Hz1)
1 60 Hz
13 Phase assignment 0 I1 to Phase A and I3 to Phase C1)
1 I1 to Phase C and I3 to Phase A
14 - 15 Reserved 0

1) Standard in the bus controller function model

Comments regarding measurement configurations:

Measuring configuration Note
3P4W Monitors the phasing of voltages and currents: Phase A before phase B before phase C
3P3W Measuring configuration: Phase A and phase C, N connection bridges to phase B or open
Measurement: e.g. the 2 phases A and C and the 2 corresponding currents are measured, phase B disabled
Monitors the phasing of voltages and currents: Phase difference between A and C >180°

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4.3.14.10.15 User calibration of current and voltage values

Use the following procedure to properly calculate gain and offset:

• Read out the predefined values:
See section 4.3.14.10.16 "ADC RMS comparison – read"
• Calculate and set new values:
See section 4.3.14.10.17 "ADC RMS comparison checksum 3"
• Update predefined values by setting the register "Cs3Update". The predefined values have been updated
when the value in the register "Cs3UpdateFB" is equal to the value of <Cs3Update>.

4.3.14.10.16 ADC RMS comparison – read

4.3.14.10.16.1 General information

The values in the registers specified below must be read at the beginning of the calibration. This is the only way
to ensure that the gain and offset will be calculated correctly.
The values contained in the registers correspond to the valueold in the calculation formulas for gain and offset (see
4.3.14.10.17 "ADC RMS comparison checksum 3").

4.3.14.10.16.2 Voltage RMS gain phase A/B/C

Name:
UGainA_R
UGainB_R
UGainC_R
Data type Value
UINT 0 to 65,535

4.3.14.10.16.3 Current RMS gain phase A/B/C/N

Name:
IGainA_R
IGainB_R
IGainC_R
IGainN_R
Data type Value
UINT 0 to 65,535

4.3.14.10.16.4 Voltage RMS offset phase A/B/C

Name:
UoffsetA_R
UoffsetB_R
UoffsetC_R
Data type Value
INT -32,767 to 32,767

4.3.14.10.16.5 Current RMS offset phase A/B/C/N

Name:
IoffsetA_R
IoffsetB_R
IoffsetC_R
IoffsetN_R
Data type Value
INT -32,767 to 32,767

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4.3.14.10.17 ADC RMS comparison checksum 3

4.3.14.10.17.1 Voltage RMS gain phase A/B/C

Name:
UGainA_W
UGainB_W
UGainC_W
Data type Value Information
UINT 0 to 65,535 Voltage RMS gain, phase-based

The resulting gain is calculated using the following formula:

Valuenew = Valueold * correction factor, determined when U = Un

4.3.14.10.17.2 Current RMS gain phase A/B/C/N

Name:
IGainA_W
IGainB_W
IGainC_W
IGainN_W
Data type Value Information
UINT 0 to 65,535 Current RMS gain, phase-based

The resulting gain is calculated using the following formula:

Valuenew = Valueold * correction factor, determined when I = In

4.3.14.10.17.3 Voltage RMS offset phase A/B/C

Name:
UoffsetA_W
UoffsetB_W
UoffsetC_W
Corresponds to the negated value of the corresponding RMS register when U = 0.
Data type Value Information
INT -32,767 to 32,767 RMS voltage offset, phase-based

4.3.14.10.17.4 Current RMS offset phase A/B/C/N

Name:
IoffsetA_W
IoffsetB_W
IoffsetC_W
IoffsetN_W
Corresponds to the negated value of the corresponding RMS register when I = 0.
Data type Value Information
INT -32,767 to 32,767 RMS current offset, phase-based

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4.3.14.10.18 User calibration of power values

Use the following procedure to properly calculate the power angle correction:
1 Calculate the values
2 Write the value 0xFFFF to register Cs1Update
3 Read register Cs1UpdateFB until 0xFFFF is returned
4 Write the calculated values to the registers PhiA_W, PhiB_W, PhiC_W
5 Write the value 0x0001 to register Cs1Update
6 Read register Cs1UpdateFB until 0x0001 is returned

Information:
These registers are NOT nonvolatile, and the process needs to be repeated after every PowerOn and
every positive edge of the ModuleOK bit.

4.3.14.10.18.1 ADC power angle correction, Phase A/B/C

Name:
PhiA_R
PhiB_R
PhiC_R
These registers can be used to read out the configured values at runtime, but are not nonvolatile and have the
value 0 after the system is started.
Data type Value
UINT See bit structure.

Bit structure:
Bit Name Value Information
0-9 Delay time for energy phase angle correction x The clock base is 2.048 MHz. Maximum 0.499 mSec.
10 - 14 Reserved 0
15 Delay times 0 Effect on current channel
1 Effect on voltage channel

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4.3.14.10.18.2 ADC power calibration checksum 1

Name:
PhiA_W
PhiB_W
PhiC_W
These registers can be used to correct phase shifts at runtime. This can be necessary if the transformers used
distort the phase shift.
Data type Value
UINT See bit structure.

Bit structure:
Bit Name Value Information
0-9 Delay time for energy phase angle correction 0 to 1023 See descriptions for Bits 0 to 9
10 - 14 Reserved 0
15 Delay times 0 or 1 See description for Bit 15

Description - Bits 0 to 9
The maximum correction 0x3FF = 1023 dec. corresponds to 0.49951 ms.
At 50 Hz mains this corresponds to a change of 8.99 degrees
At 60 Hz mains this corresponds to a change of 10.79 degrees
Schematic representation of inductive load: Voltage ahead of current Schematic representation of capacitive load: Current ahead of voltage
Voltage Voltage
Current Current

90° 180° 270° 360° 90° 180° 270° 360°

Desription - Bit 15
0 Delay affects current channel
Effect with inductive load Reduced angle between I and U, and therefore an increased power factor
Effect with capacitive load Increased angle between U and I, and therefore an reduced power factor
1 Delay affects voltage channel
Effect with inductive load Reduced angle between U and I, and therefore an increased power factor
Effect with capacitive load Increased angle between I and U, and therefore an reduced power factor

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4.3.14.10.19 FlatStream communication

4.3.14.10.19.1 Introduction

B&R offers an additional communication method for some modules. "FlatStream" was designed for X2X and
POWERLINK networks and allows data transmission to be adapted to individual demands. Although this method
is not 100% real-time capable, it still allows data transmission to be handled more efficiently than with standard
cyclic polling.
Field device
X2X language

Cyclic call
via I/O mapping

B&R CPU
Cyclic call B&R module Cyclic
PLC or B&R field device
of cached values cached value communication
Bus controller

Acyclic call
via
library functions
B&R CPU
Acyclic call B&R module Cyclic
PLC or B&R field device
of cached values cached value communication
Bus controller

FlatStream

B&R CPU X2X-compatible B&R module

PLC or Device command B&R field device
device command as a bridge
Bus controller

Figure 141: Three types of communication

FlatStream extends cyclic and acyclic data queries. With FlatStream communication, the module acts as a bridge.
It is used to pass CPU queries directly on to the field device.

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4.3.14.10.19.2 Message, segment, sequence, MTU

The physical properties of the bus system limit the amount of data that can be transmitted during one bus cycle.
With FlatStream communication, all messages are viewed as part of a continuous data stream. Long data streams
must be broken down into several fragments that are sent one after the other. To understand how the receiver puts
these fragments back together to get the original information, it is important to understand the difference between
a message, a segment, a sequence and an MTU.
Message
A message refers to information exchanged between two partner stations. The length of a message is not restricted
by the FlatStream communication method. Nevertheless, module-specific limitations must be considered.
Segment (logical division of a message):
A segment has a finite size and can be understood as a section of a message. The number of segments per
message is arbitrary. So that the recipient can correctly reassemble the transmitted segments, each segment
is preceded by a byte with additional information. This control byte contains information such as the length of a
segment and whether the approaching segment completes the message. This makes it possible for the receiving
station to interpret the incoming data stream correctly.
Sequence (how a segment needs to be arranged physically):
The maximum size of a sequence corresponds to the number of enabled Rx or Tx bytes (later: "MTU"). The
transmitting station splits the transmit array into valid sequences. These sequences are then written successively
to the MTU and transmitted to the receiving station where they are put back together again. The receiver stores
the incoming sequences in a receive array, obtaining an image of the data stream in the process.
With FlatStream communication, the number of sequences sent are counted. Successfully transmitted sequences
must be acknowledged by the receiving station to ensure the integrity of the transmission.
MTU (Maximum Transmission Unit) – Physical transport:
MTU refers to the enabled USINT registers used with FlatStream. These registers can accept at least one se-
quence and pass it on to the receiving station. A separate MTU is defined for each direction of communication.
The OutputMTU defines the number of FlatStream Tx bytes, and the InputMTU specifies the number of FlatStream
Rx bytes. The MTUs are transported cyclically via the X2X Link, increasing the load with each additional enabled
USINT register.
Features
FlatStream messages are not transmitted cyclically or in 100% real time. Many bus cycles may be needed to trans-
mit a particular message. Although the Rx and Tx registers are exchanged between the transmitter and the receiv-
er cyclically, they are only processed further if explicitly accepted by the "InputSequence" or "OutputSequence"
register.
Behavior in the event of an error (brief summary)
The protocol for X2X and POWERLINK networks specifies that the last valid values should be retained when
disturbances occur. With conventional communication (cyclic/acyclic data queries), this type of error can generally
be ignored.
In order for communication to also take place without errors using FlatStream, all of the sequences issued by the
receiver must be acknowledged. If Forward functionality is not used, then subsequent communication is delayed
for the length of the disturbance.
If Forward functionality is being used, the receiving station receives a transmission counter that is incremented
twice. The receiver stops, i.e. it no longer returns any acknowledgments. The transmitting station uses the Se-
quenceAck to determine that the transmission was faulty and that all affected sequences will have to be repeated.

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4.3.14.10.19.3 The FlatStream principle

Prerequisites and requirements

Before FlatStream can be used, the respective communication direction must be synchronized, i.e. both commu-
nication partners cyclically query the sequence counter on the opposite station. This checks to see if there is new
data that should be accepted.
Communication
If a communication partner wants to transmit a message to its opposite station, it should first create a transmit
array that corresponds to FlatStream conventions. This allows the FlatStream data to be organized very efficiently
without having to block other important resources.
PLC / Bus controller Module
Module-internal Module-internal
Transmit array OutputMTU receive buffer receive array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 TxBytes Cyc. *RxBytes _data_01

_data_02 _data_02
When OutputMTU The transmit buffer If the OutputSequence
_data_03 released: of the module is counter is increased: _data_03
adjusted cyclically to
_data_04 CPU fills OutputMTU via X2X Module adds the transmit buffer _data_04
OutputMTU to the internal array
_data_05 with the next
_data_05
... sequence of the If successful: ...
transmit array InputSequenceAck is
_data_xx adjusted to the _data_xx
transmit counter

Module-internal Module-internal
Receive array InputMTU transmit buffer transmit array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 RxBytes Cyc. *TxBytes _data_01

_data_02 _data_02
If the InputMTU is If permitted:
_data_03 InputSequence adjusted cyclically Module fills the internal _data_03
counter is increased: to the receive transmit buffer with the
_data_04 buffer via X2X next sequence of the _data_04
_data_05 InputMTU must be transmit array _data_05
added to the end
... of the receive array Module increases the ...
(increase InputSequenceAck InputSequence counter
_data_xx to end properly) _data_xx

Figure 142: FlatStream communication

Procedure
The first thing that happens is that the message is broken into valid segments of up to 63 bytes, and the corre-
sponding control bytes are created. The data is formed into a data stream made up of one control bytes per asso-
ciated segment. This data stream can be written to the transmit array. The maximum size of each array element
matches that of the enabled MTU so that one element corresponds to one sequence.
When the array has been completely created, the transmitter checks whether the MTU is allowed to be refilled.
Then it copies the first element of the array or the first sequence to the Tx byte registers. The MTU is transported to
the receiver station via X2X Link and stored in the corresponding Rx byte registers. To signal that the data should
be accepted by the receiver, the transmitter increases its SequenceCounter.
If the communication direction is synchronized, the opposite station detects the incremented SequenceCounter.
The current sequence is appended to the receive array and acknowledged by SequenceAck. This acknowledgment
signals to the transmitter that the MTU can now be refilled.
If the transmission is successful, the data in the receive array will correspond 100% to the data in the transmit array.
During the transmission, the receiving station must detect and evaluate the incoming control bytes. A separate
receive array should be created for each message. This allows the receiver to immediately begin further processing
of messages once they have been completely transmitted.

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4.3.14.10.19.4 Registers for FlatStream mode

Five registers are available for configuring FlatStream. The default configuration can be used to transmit small
amounts of data relatively easily.

Information:
The CPU communicates directly with the field device via the "OutputSequence" and "InputSequence"
as well as the enabled Tx and Rx bytes. For this reason, the user needs to have sufficient knowledge
of the communication protocol being used on the field device.

FlatStream configuration

To use FlatStream, the program sequence must first be expanded. The cycle time of the FlatStream routines must
be set to a multiple of the bus cycle. Other program routines should be implemented in Cyclic #1 to ensure data
consistency.
At the absolute minimum, the "InputMTU" and "OutputMTU" registers need to be configured. All other registers are
filled in with default values at the beginning and can be used immediately. These registers are used for additional
options, e.g. to transmit data in a more compact way or to increase the efficiency of the general procedure.
The Forward registers extend the functionality of the FlatStream protocol. This functionality is useful for substan-
tially increasing the FlatStream data rate, but it also requires quite a bit of extra work when creating the program
sequence.

Number of enabled Tx and Rx bytes

Name:
OutputMTU
InputMTU
These registers define the number of enabled Tx or Rx bytes, i.e. the maximum size of a sequence. The user must
consider that the more bytes made available also means a higher load on the bus system.

Information:
In the rest of this documentation, the names "OutputMTU" and "InputMTU" do not refer to the registers
explained here. Instead, they are used as synonyms for the currently enabled Tx or Rx bytes.
Data type Value
USINT See the module-specific register overview (theoretically: 3 to 27)

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FlatStream operation

When using FlatStream, the communication direction is enormously important. For sending data to a module ("out-
put" direction), the Tx bytes are used. For receiving data from a module ("input" direction), the Rx bytes are used.
The "OutputSequence" and "InputSequence" registers are used to control and ensure that communication is taking
place properly, i.e. the transmitter issues the directive that the data should be accepted and the receiver acknowl-
edges that a sequence has been transmitted successfully.

Transporting the payload data and the control bytes

Name:
TxByte1 to TxByteN
RxByte1 to RxByteN
(The value the number N is different depending on the bus controller model used.)
The Tx and Rx bytes are cyclic registers used to transport the payload data and the necessary control bytes. The
number of active Tx and Rx bytes is taken from the configuration of the "OutputMTU" and "InputMTU" registers,
respectively.
In the user program, only the Tx and Rx bytes from the CPU can be used. The corresponding counterparts are
located in the module and are not accessible to the user. For this reason, names were chosen from the CPU point
of view.
• "T" - "Transmit" → CPU transmits data to the module.
• "R" - "Receive" → CPU receives data from the module.
Data type Value
USINT 0 to 65535

Control bytes

In addition to the payload data, the Tx and Rx bytes also transmit the necessary control bytes. These control bytes
contain additional information about the data stream so that the receiver can reconstruct the original message from
the transmitted segments.
Bit structure of a control byte
Bit Name Value Information
0-5 SegmentLength 0 - 63 Size of the subsequent segment in bytes (default: Max. MTU size - 1)
6 nextCBPos 0 Next control byte at the beginning of the next MTU
1 Next control byte directly after the end of the current segment
7 MessageEndBit 0 Message continues after the subsequent segment
1 Message ended by the subsequent segment

SegmentLength
The segment length lets the receiver know the length of the coming segment. If the configured segment length
is insufficient for a message, then the information must be distributed over several segments. In these cases, the
actual end of the message is detected using bit 7 of the control byte.

Information:
The control byte is not included in the calculation to determine the segment length. The segment length
is only derived from the bytes of payload data.
nextCBPos
This bit indicates the position where the next control byte is to be expected. This information is especially important
when using the "MultiSegmentMTU" option.
When using FlatStream communication with multi-segment MTUs, the next control byte is no longer expected in
the first Rx byte of the subsequent MTU, but directly after the current segment.

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MessageEndBit
The "MessageEndBit" is set if the subsequent segment completes a message. The message has then been com-
pletely transmitted and is ready for further processing.

Information:
In the output direction, this bit must also be set if one individual segment is enough to hold the entire
message. The module will only process a message internally if this identifier is detected.
The size of the message being transmitted can be calculated by adding all of the message's segment
lengths together.
FlatStream formula for calculating message length:
Message [bytes] = SegmentLengths (all CBs without ME) + SegmentLength (of the first CB with CB Control byte
ME) ME MessageEndBit

Communication status of the CPU

Name:
OutputSequence
The "OutputSequence" register contains information about the communication status of the CPU. It is written by
the CPU and read by the module.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-2 OutputSequenceCounter 0-7 Counter for the sequences issued in the output direction
3 OutputSyncBit 0 Output direction disabled
1 Output direction enabled
4-6 InputSequenceAck 0-7 Mirrors the InputSequenceCounter value
7 InputSyncAck 0 Input direction not ready (disabled)
1 Input direction ready (enabled)

OutputSequenceCounter
The OutputSequenceCounter is a continuous counter of sequences that have been issued by the CPU. The CPU
uses the OutputSequenceCounter to direct the module to accept a sequence (the output direction must be syn-
chronized when this happens).
OutputSyncBit
The CPU uses the OutputSyncBit to attempt to synchronize the output channel.
InputSequenceAck
InputSequenceAck is used for acknowledgment. The value of the InputSequenceCounter is mirrored if the CPU
has received a sequence successfully.
InputSyncAck
The InputSyncAck bit acknowledges the synchronization of the input channel for the module. This indicates that
the CPU is ready to receive data.

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Communication status of the module

Name:
InputSequence
The "InputSequence" register contains information about the communication status of the module. It is written by
the module and should only be read by the CPU.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-2 InputSequenceCounter 0-7 Counter for sequences issued in the input direction
3 InputSyncBit 0 Not ready (disabled)
1 Ready (enabled)
4-6 OutputSequenceAck 0-7 Mirrors the InputSequenceCounter value
7 OutputSyncAck 0 Not ready (disabled)
1 Ready (enabled)

InputSequenceCounter
The InputSequenceCounter is a continuous counter of sequences that have been issued by the module. The
module uses the InputSequenceCounter to direct the CPU to accept a sequence (the input direction must be
synchronized when this happens).
InputSyncBit
The module uses the InputSyncBit to attempt to synchronize the input channel.
OutputSequenceAck
OutputSequenceAck is used for acknowledgment. The value of the OutputSequenceCounter is mirrored if the
module has received a sequence successfully.
OutputSyncAck
The OutputSyncAck bit acknowledges the synchronization of the output channel for the CPU. This indicates that
the module is ready to receive data.

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Relationship between OutputSequence and InputSequence

Outputsequenz Input sequence

CPU communication status Module communication status

0-2 OutputSequenceCounter 0-2 InputSequenceCounter

3 OutputSyncBit Intersecting 3 InputSyncBit

4-6 InputSequenceAck Handshakes 4-6 OutputSequenceAck

7 InputSyncAck 7 OutputSyncAck

Figure 143: Relationship between OutputSequence and InputSequence

The "OutputSequence" and "InputSequence" registers are logically composed of two half-bytes. The low part sig-
nals to the opposite station whether a channel should be opened or if data should be accepted. The high part is
to acknowledge that the requested action was carried out.
SyncBit and SyncAck
If SyncBit and SyncAck are set in one communication direction, then the channel is considered "synchronized", i.e.
it is possible to send messages in this direction. The status bit of the opposite station must be checked cyclically.
If SyncAck has been reset, then the SyncBit must be adjusted on that station. Before new data can be transmitted,
the channel needs to be resynchronized.
SequenceCounter and SequenceAck
The communication partners cyclically check whether the low nibble on the opposite station changes. When one
of the communication partners finishes writing a new sequence to the MTU, it increments its SequenceCounter.
The current sequence is then transmitted to the receiver, which acknowledges its receipt with SequenceAck. In
this way, a "handshake" is initiated.

Information:
If communication is interrupted, segments from the unfinished message are discarded. All messages
that were transmitted completely are processed.

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Synchronization

During synchronization, a communication channel is opened. It is important to make sure that a module is present
and that the current value of the SequenceCounter is stored on the station receiving the message.
FlatStream can handle full-duplex communication. This means that both channels / communication directions can
be handled separately. They have to be synchronized independently so that simplex communication can theoret-
ically be carried out as well.

Synchronization in the output direction (CPU as the transmitter):

The corresponding synchronization bits (OutputSyncBit and OutputSyncAck) are reset. Because of this, FlatStream
cannot be used at this point in time to send messages from the CPU to the module.
Algorithm
1) The CPU must write 000 to the OutputSequenceCounter and reset the OutputSyncBit.
The CPU must cyclically query the high nibble of the "InputSequence" register (checks for 000 in OutputSequenceAck and 0 in OutputSyncAck).
The module does not accept the current contents of the InputMTU since the channel is not yet synchronized.
The module matches OutputSequenceAck and OutputSyncAck to the values of the OutputSequenceCounter and OutputSyncBit.
2) If the CPU registers the expected values in OutputSequenceAck and OutputSyncAck, it is allowed to increment the OutputSequenceCounter.
The CPU continues cyclically querying the high nibble of the "OutputSequence" register (checks for 001 in OutputSequenceAck and 0 in InputSyncAck).
The module does not accept the current contents of the InputMTU since the channel is not yet synchronized.
The module matches OutputSequenceAck and OutputSyncAck to the values of the OutputSequenceCounter and OutputSyncBit.
3) When the CPU registers the expected values in OutputSequenceAck and OutputSyncAck, it is allowed to increment the OutputSequenceCounter.
The CPU continues cyclically querying the high nibble of the "OutputSequence" register (checks for 001 in OutputSequenceAck and 1 in InputSyncAck).

Note:
Theoretically, data can be transmitted from this point forward. However, it is still recommended to wait until the output direction is completely synchronized be-
fore transmitting data.
The module sets OutputSyncAck.
The output direction is synchronized, and the CPU can transmit data to the module.

Synchronization in the input direction (CPU as the receiver):

The corresponding synchronization bits (InputSyncBit and InputSyncAck) are reset. Because of this, FlatStream
cannot be used at this point in time to send messages from the module to the CPU.
Algorithm
The module writes 000 to the InputSequenceCounter and resets the InputSyncBit.
The module monitors the high nibble of the "OutputSequence" registers and expects 000 in InputSequenceAck and 0 in InputSyncAck.
1) The CPU is not allowed to accept the current contents of the InputMTU since the channel is not yet synchronized.
The CPU has to match InputSequenceAck and InputSyncAck to the values of InputSequenceCounter and InputSyncBit.
If the module registers the expected values in InputSequenceAck and InputSyncAck, it increments the InputSequenceCounter.
The module monitors the high nibble of the "OutputSequence" registers and expects 001 in InputSequenceAck and 0 in InputSyncAck.
2) The CPU is not allowed to accept the current contents of the InputMTU since the channel is not yet synchronized.
The CPU has to match InputSequenceAck and InputSyncAck to the values of InputSequenceCounter and InputSyncBit.
If the module registers the expected values in InputSequenceAck and InputSyncAck, it sets the InputSyncBit.
The module monitors the high nibble of the "OutputSequence" register and expects 1 in InputSyncAck.
3) The CPU is allowed to set InputSyncAck.

Note:
Theoretically, data can already be transmitted in this cycle.
If the InputSyncBit is set and InputSequenceCounter has been increased by 1, the values in the enabled Rx bytes have to be accepted and acknowledged (see
also "Communication in the input direction").
The input direction is synchronized, and the module can transmit data to the CPU.

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Transmitting and receiving

If a channel is synchronized, then the opposite station is ready to receive messages from the transmitter. Before
the transmitter can send data, it needs to first create a transmit array in order to meet FlatStream requirements.
The transmitting station must also generate a control byte for each segment created. This control byte contains
information about how the subsequent part of the data being transmitted should be processed. The position of the
next control byte in the data stream can vary. For this reason, it must be clearly defined at all times when a new
control byte is being transmitted. The first control byte is always in the first byte of the first sequence. All subsequent
positions are determined recursively.
FlatStream formula for calculating the position of the next control byte:
Position (of the next control byte) = Current position + 1 + Segment length
Example
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The rest of the configuration corresponds to the default settings.

Message 1: Transmit/Receive array

With 7 USINT elements according to

the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Default
Message 2:

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

C2 A7 - - - - - Sequence for bus cycle 2

Message 3:
C3 B1 B2 - - - - Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C4 D1 D2 D3 D4 D5 D6 Sequence for bus cycle 4

No more data to transmit C5 D7 D8 D9 - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 144: Transmit/Receive array (default)

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First, the messages must be split into segments. In the default configuration, it is important to ensure that each
sequence can hold an entire segment, including the associated control byte. The sequence is limited to the size of
the enable MTU. In other words, a segment must be at least 1 byte smaller than the MTU.
MTU = 7 bytes → Max. segment length = 6 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 6 bytes of data

➯ Second segment = Control byte + 1 data byte
• Message 2 (2 bytes)

➯ First segment = Control byte + 2 bytes of data

• Message 3 (9 bytes)

➯ First segment = Control byte + 6 bytes of data

➯ Second segment = Control byte + 3 data bytes
• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C0 (control byte 0) C1 (control byte 1) C2 (control byte 2)
- SegmentLength (0) = 0 - SegmentLength (6) = 6 - SegmentLength (1) = 1
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (0) = 0 - MessageEndBit (0) = 0 - MessageEndBit (1) = 128
Control byte Σ 0 Control byte Σ 6 Control byte Σ 129

Table 73: FlatStream determination of the control bytes for the default configuration example (part 1)
C3 (control byte 3) C4 (control byte 4) C5 (control byte 5)
- SegmentLength (2) = 2 - SegmentLength (6) = 6 - SegmentLength (3) = 3
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (1) = 128 - MessageEndBit (0) = 0 - MessageEndBit (1) = 128
Control byte Σ 130 Control byte Σ 6 Control byte Σ 131

Table 74: FlatStream determination of the control bytes for the default configuration example (part 2)

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Transmitting data to a module (output)

When transmitting data, the transmit array must be generated in the application program. Sequences are then
transmitted one by one using FlatStream and received by the module.

Information:
Although all B&R modules with FlatStream communication always support the most compact trans-
missions in the output direction, it is recommended to use the same design for the transfer arrays in
both communication directions.

PLC / Bus controller Module

Module-internal Module-internal
Transmit array OutputMTU receive buffer receive array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 TxBytes Cyc. *RxBytes _data_01

_data_02 _data_02
When OutputMTU The transmit buffer If the OutputSequence
_data_03 released: of the module is counter is increased: _data_03
adjusted cyclically to
_data_04 CPU fills OutputMTU via X2X Module adds the transmit buffer _data_04
OutputMTU with to the internal array
_data_05 the next sequence
_data_05
... of transmit array If successful: ...
InputSequenceAck is
_data_xx adjusted to the _data_xx
transmit counter

Figure 145: FlatStream communication (output)

The length of the message is initially smaller than the OutputMTU. In this case, one sequence would be sufficient
to transmit the entire message and the necessary control byte.
Algorithms
Cyclic status query:
- The Module monitors the OutputSequenceCounter.
0) Cyclic checks:
- The CPU must check OutputSyncAck.
→ If OutputSyncAck = 0: Reset the OutputSyncBit and resynchronize the channel.
- The CPU must check whether OutputMTU is enabled.
→ If OutputSequenceCounter > InputSequenceAck: MTU is not enabled because the last sequence has not yet been acknowledged.
1) Preparation (create transmit array):
- The CPU must split up the message into valid segments and create the necessary control bytes.
- The CPU must add the segments and control bytes to the transmit array.
2) Transmit:
- The CPU transfers the current element of the transmit array to the OutputMTU.
→ The OutputMTU is transferred cyclically to the module's transmit buffer but not processed further.
- The CPU must increase the OutputSequenceCounter.
Response:
- The module accepts the bytes from the internal receive buffer and adds them to the internal receive array.
- The module sends acknowledgment and writes the value of the OutputSequenceCounter to OutputSequenceAck.
3) Completion:
- The CPU must monitor the OutputSequenceAck.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via OutputSequenceAck. In order to detect potential trans-
mission errors in the last sequence as well, it is important to make sure that the length of the Completion phase is run through long enough.

Note:
To monitor communication times exactly, the task cycles that have passed since the last increase of the OutputSequenceCounter should be counted. In this
way, the number of previous bus cycles necessary for the transmission can be measured. If the monitoring counter exceeds a predefined threshold, then the
sequence can be considered lost.
(The relationship of bus to task cycle can be influenced by the user so that the threshold value needs to be determined individually.)
- Subsequent sequences can only be transmitted in the next bus cycle after the completion check has been carried out successfully.

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Message larger than the OutputMTU

The transmit array, which needs to be created in the program sequence, consists of several elements. The user
has to arrange the control and data bytes correctly and transfer the array elements one after the other. The transfer
algorithm remains the same and is repeated starting at the point Cyclic checks.
General flow chart

Start

► diff = (OutputSequenceCounter -
OutputSequenceAck) AND 7
► limit = (OutputSequenceCounter -
LastValidAck) AND 7

(diff ≤ limit)
No OutputSequenceAck = No LastValidAck = Yes
AND (OutputSyncAck = 1)
AND (OutputSyncBit = 1) ? OutputSequenceCounter ? OutputSequenceCounter ?

Yes Yes No

No LastValidAck =
diff = 0 ?
OutputSequenceAck

Yes

LastValidAck = No
OutputSequenceAck = 0 ?
OutputSequenceAck

Yes

No OutputSequenceCounter = 0
More sequences to be sent ? OutputSequenceCounter = 1 OutputSyncBit = 1
LastValidAck = 0

Yes

copy next sequence to MTU

increase OutputSequenceCounter

Sequence handling Synchronisation

Figure 146: Flow chart for the output direction

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Receiving data from a module (input)

When receiving data, the transmit array is generated by the module, transferred via FlatStream and must then
be reproduced in the receive array. The structure of the incoming data stream can be configured with the mode
register. The algorithm for receiving the data does not change in this regard.
PLC / Bus controller Module
Module-internal Module-internal
Receive array InputMTU transmit buffer transmit array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 RxBytes Cyc. *TxBytes _data_01

_data_02 _data_02
If the InputMTU is If permitted:
_data_03 InputSequence adjusted cyclically Module fills the internal _data_03
counter is increased: to the receive transmit buffer with the
_data_04 buffer via X2X next sequence of the _data_04
InputMTU must be transmit array
_data_05 added to the end
_data_05
... of the receive array Module increases the ...
(increase InputSequenceAck InputSequence counter
_data_xx to end properly) _data_xx

Figure 147: FlatStream communication (input)

Algorithms
0) Cyclic status query:
- The CPU must monitor the InputSequenceCounter.
Cyclic checks:
- The module checks InputSyncAck.
- The module checks InputSequenceAck.
Preparation:
- The module forms the segments and control bytes and creates the transmit array.
Action:
- The module transfers the current element of the internal transmit array to the internal transmit buffer.
- The module increases the InputSequenceCounter.
1) Receiving (as soon as InputSequenceCounter is increased):
- The CPU must accept data from the InputMTU and append it to the end of the receive array.
- The CPU must match InputSequenceAck to the InputSequenceCounter of the sequence currently being processed.
Completion:
- The module monitors InputSequenceAck.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via InputSequenceAck .
- Subsequent sequences are only transmitted in the next bus cycle after the completion check has been carried out successfully.

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General flow chart

Start

► InputSequenceAck = InputSequenceCounter

Synchronisation
No
InputSyncBit = 1 ? ► RemainingSegmentSize = 0
► SegmentFlags = 0
Yes

No No
InputSyncAck = 1 ? InputSequenceAck > 0 ?

Yes Yes

MTU_Offset = 0 InputSyncAck = 1

(InputSequenceCounter – No
InputSequenceAck)
AND 0x07 = 1 ?

Yes
► RemainingSegmentSize =
Yes MTU_Data[MTU_Offset] AND 0b0011 1111
RemainingSegmentSize = 0 ? ► SegmentFlags =
MTU_Data[MTU_Offset] AND 0b1100 0000
No ► MTU_Offset = MTU_Offset + 1

Yes RemainingSegmentSize > No

(InputMTU_Size – MTU_Offset) ?

Segment data handling

► DataSize = InputMTU_Size – MTU_Offset ► DataSize = RemainingSegmentSize

► copy segment data e.g. memcpy(xxx, ADR(MTU_Data[MTU_Offset]), DataSize)

► MTU_Offset = MTU_Offset + DataSize
► RemainingSegmentSize = RemainingSegmentSize - DataSize

RemainingSegmentSize = 0 AND Yes

► Mark Frame as complete
(SegmentFlags AND 0x80) = 0 ?

No

RemainingSegmentSize = 0 AND Yes

(SegmentFlags AND 0x40) = 0 ?

No

Yes
► InputSequenceAck =
InputMTU_Size = MTU_Offset ?
InputSequenceCounter

No

Figure 148: Flow chart for the input direction

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Details

It is recommended to store transmitted messages in separate receive arrays.

After a set MessageEndBit is transmitted, the subsequent segment should be added to the receive array. The
message is then complete and can be passed on internally for further processing. A new/separate array should
be created for the next message.

Information:
When transmitting with MultiSegmentMTUs, it is possible for several small messages to be part of one
sequence. In the program, it's important to make sure that a sufficient number of receive arrays can
be managed. The entire sequence must be accepted before it is possible to change the Acknowledge
register.
If a SequenceCounter is incremented by more than one value, then an error has occurred.
Note: This situation is very unlikely when operating without "Forward" functionality.
In this case, the receiver stops. All additional incoming sequences are ignored until the transmission with the correct
SequenceCounter is retried. This response prevents the transmitter from receiving any more acknowledgments for
transmitted sequences. The transmitter can identify the last successfully transmitted sequence from the opposite
station's SequenceAck and continue the transmission from this point.
Acknowledgments must be checked for validity.
If the receiver has successfully accepted a sequence, it must be acknowledged. The receiver takes on the Se-
quenceCounter value sent along with the transmission and matches the SequenceAck to it. The transmitter reads
the SequenceAck and registers the successful transmission. If the transmitter acknowledges a sequence that has
not yet been dispatched, then the transmission needs to be interrupted and the channel resynchronized. The syn-
chronization bits are reset and the current/incomplete message is discarded. It needs to be sent again once the
channel has been resynchronized.

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FlatStream mode

Name:
FlatstreamMode
In the input direction, the transmit array is generated automatically. This register offers two options to the user
that allow an incoming data stream to have a more compact arrangement. Once enabled, the program code for
evaluation must be adapted accordingly.

Information:
All B&R modules that offer FlatStream mode support the options "Large segments" and "MultiSeg-
mentMTUs" in the output direction. Compact transmission only needs to be explicitly allowed in the
input direction.
Bit structure:
Bit Name Value Information
0 MultiSegmentMTU 0 Not allowed (default)
1 Allowed
1 Large segments 0 Not allowed (default)
1 Allowed
2-7 Reserved

Default
By default, both options relating to compact transmission in the input direction are disabled.
1. The module only forms segments that are at least one byte smaller than the enabled MTU. Each sequence
begins with a control byte so that the data stream is clearly structured and relatively easy to evaluate.
2. Since a FlatStream message can be of any length, the last segment of the message frequently doesn't fill up
all of the MTU's space. By default, the remaining bytes during this type of transfer cycle are not used.

Bus cycle 1 Bus cycle 2 Bus cycle 3

C C C
- - -
ME0 ME1 ME1

Segment 1 Segment 2 Segment 3

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 149: Message arrangement in the MTU (default)

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MultiSegmentMTUs allowed
With this option, the InputMTU is completely filled (if enough data is pending). The previously unfilled Rx bytes
transmit the next control bytes and their segments. This allows the enabled Rx bytes to be used more efficiently.
Bus cycle 1 Bus cycle 2 Bus cycle 3

C C C C
- -
ME0 ME1 ME0 ME1

Segment 1 Segment 2 3 Segment 4

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 150: Arrangement of messages in the MTU (MultiSegmentMTUs)

Large segments allowed
When transmitting very long messages or when enabling only very few Rx bytes, then a great many segments must
be created by default. The bus system is more stressed than necessary since an additional control byte needs to
be created and transmitted for each segment. With the "Large segments" option, the segment length is limited to
63 bytes independently of the InputMTU. One segment can stretch across several sequences, i.e. it is possible for
"pure" sequences to occur without a control byte.

Information:
It is still possible to split up a message into several segments, however. If this option is used and
messages with more than 63 bytes occur, for example, then messages can still be split up among
several segments.

Bus cycle 1 Bus cycle 2 Bus cycle 3

C C
- - - -
ME1 ME1

Segment 1 Segment 2 Segment 3

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 151: Arrangement of messages in the MTU (large segments)

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Using both options

It is also possible to use both options at the same time.
Bus cycle 1 Bus cycle 2 Bus cycle 3

C C
- - - -
ME1 ME1

Segment 1 Segment 2 Segment 3

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 152: Arrangement of messages in the MTU (large segments and MultiSegmentMTUs)

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Adjusting the FlatStream

If the way messages are structured is changed, then the way data in the transmit/receive array is arranged is also
different. The following changes apply to the example given earlier.
MultiSegmentMTU
If MultiSegmentMTUs are allowed, then "open positions" in an MTU can be used. These "open positions" occur if
the last segment in a message does not fully use the entire MTU. MultiSegmentMTUs allow these bits to be used to
transmit the subsequent control bytes and segments. In the program sequence, the "nextCBPos" bit in the control
byte is set so that the receiver can correctly identify the next control byte.
Example
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The configuration allows transmission of MultiSegmentMTUs.
Message 1: Transmit/Receive array

With 7 USINT elements according to

the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Message 2: MultiSegmentMTU

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

C2 A7 C3 B1 B2 C4 D1 Sequence for bus cycle 2

Message 3:
C5 D2 D3 D4 D5 D6 D7 Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C6 D8 D9 C0 - - - Sequence for bus cycle 4

No more data to transmit C0 - - - - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 153: Transmit/receive array (MultiSegmentMTUs)

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First, the messages must be split into segments. As in the default configuration, it is important for each sequence
to begin with a control byte. The free bits in the MTU at the end of a message are filled with data from the following
message, however. With this option, the "nextCBPos" bit is always set if payload data is sent after the control byte.
MTU = 7 bytes → Max. segment length = 6 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 6 bytes of data (MTU full)

➯ Second segment = Control byte + 1 byte of data (MTU still has 5 open bytes)
• Message 2 (2 bytes)

➯ First segment = Control byte + 2 bytes of data (MTU still has 2 open bytes)
• Message 3 (9 bytes)

➯ First segment = Control byte + 1 byte of data (MTU full)

➯ Second segment = Control byte + 6 bytes of data (MTU full)
➯ Third segment = Control byte + 2 bytes of data (MTU still has 4 open bytes)
• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C1 (control byte 1) C2 (control byte 2) C3 (control byte 3)
- SegmentLength (6) = 6 - SegmentLength (1) = 1 - SegmentLength (2) = 2
- nextCBPos (1) = 64 - nextCBPos (1) = 64 - nextCBPos (1) = 64
- MessageEndBit (0) = 0 - MessageEndBit (1) = 128 - MessageEndBit (1) = 128
Control byte Σ 70 Control byte Σ 193 Control byte Σ 194

Table 75: FlatStream determination of the control bytes for the MultiSegmentMTU example (part 1)

Warning!
The second sequence must have been completely processed before it can be acknowledged with Se-
quenceAck. In this example, there are three different segments within the second sequence, i.e. the
program must include enough receive arrays to handle this situation.
C4 (control byte 4) C5 (control byte 5) C6 (control byte 6)
- SegmentLength (1) = 1 - SegmentLength (6) = 6 - SegmentLength (2) = 2
- nextCBPos (6) = 6 - nextCBPos (1) = 64 - nextCBPos (1) = 64
- MessageEndBit (0) = 0 - MessageEndBit (1) = 0 - MessageEndBit (1) = 128
Control byte Σ 7 Control byte Σ 70 Control byte Σ 194

Table 76: FlatStream determination of the control bytes for the MultiSegmentMTU example (part 2)

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Large segments
Segments are limited to a maximum of 63 bytes. This means they can be larger than the active MTU. These large
segments are divided among several sequences when transmitted. It is possible for sequences to be completely
filled with payload data and not have a control byte.

Information:
It is still possible to subdivide a message into several segments so that the size of a data packet does
not also have to be limited to 63 bytes.
Example
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The configuration allows the transmission of large segments.

Message 1: Transmit/Receive array

With 7 USINT elements according to

the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Message 2: Large segments

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

A7 - - - - - - Sequence for bus cycle 2

Message 3:
C2 B1 B2 - - - - Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C3 D1 D2 D3 D4 D5 D6 Sequence for bus cycle 4

No more data to transmit D7 D8 D9 - - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 154: Transmit/receive array (large segments)

First, the messages must be split into segments. The ability to form large segments means that messages are split
up less frequently, which results in fewer control bytes generated.
Large segments allowed → Max. segment length = 63 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 7 bytes of data

• Message 2 (2 bytes)

➯ First segment = Control byte + 2 bytes of data

• Message 3 (9 bytes)

➯ First segment = Control byte + 9 bytes of data

• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C1 (control byte 1) C2 (control byte 2) C3 (control byte 3)
- SegmentLength (7) = 7 - SegmentLength (2) = 2 - SegmentLength (9) = 9
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (1) = 128 - MessageEndBit (1) = 128 - MessageEndBit (1) = 128
Control byte Σ 135 Control byte Σ 130 Control byte Σ 137

Table 77: FlatStream determination of the control bytes for the large segment example

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Large segments and MultiSegmentMTU

Example
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The configuration allows transmission of large segments as well as MultiSegmentMTUs.
Message 1: Transmit/Receive array
With 7 USINT elements according to
the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Message 2: Both options

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

A7 C2 B1 B2 C3 D1 D2 Sequence for bus cycle 2

Message 3:
D3 D4 D5 D6 D7 D8 D9 Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C0 - - - - - - Sequence for bus cycle 4

No more data to transmit C0 - - - - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 155: Transmit/receive array (large segments and MultiSegmentMTUs)

First, the messages must be split into segments. If the last segment of a message does not completely fill the
MTU, it can be used for other data in the data stream. The "nextCBPos" bit must always be set if the control byte
belongs to a segment with payload data.
The ability to form large segments means that messages are split up less frequently, which results in fewer control
bytes generated. Control bytes are generated in the same way as with the "Large segments" option.
Large segments allowed → Max. segment length = 63 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 7 bytes of data

• Message 2 (2 bytes)

➯ First segment = Control byte + 2 bytes of data

• Message 3 (9 bytes)

➯ First segment = Control byte + 9 bytes of data

• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C1 (control byte 1) C2 (control byte 2) C3 (control byte 3)
- SegmentLength (7) = 7 - SegmentLength (2) = 2 - SegmentLength (9) = 9
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (1) = 128 - MessageEndBit (1) = 128 - MessageEndBit (1) = 128
Control byte Σ 135 Control byte Σ 130 Control byte Σ 137

Table 78: FlatStream determination of the control bytes for the large segment and MultiSegmentMTU example

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4.3.14.10.19.5 Example of Forward functionality on X2X Link

Forward functionality is a method that can be used to substantially increase the FlatStream data rate. The basic
principle is also used in other technical areas such as "pipelining" for microprocessors.

Operating principle

X2X Link communication cycles through five different steps to transmit a FlatStream sequence. At least five bus
cycles are therefore required to successfully transfer the sequence.
Step I Step II Step III Step IV Step V
Actions Transfer sequence from Cyclic matching of MTU and Append sequence to re- Cyclic matching of Check SequenceAck
transmit array, module buffer ceive array MTU and module buffer
increase Sequence- Adjust SequenceAck
Counter
Resource Transmitter Bus system Recipient Bus system Transmitter
(task to transmit) (direction 1) (task to receive) (direction 2) (task for Ack checking)

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 ...

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Figure 156: Comparison of transmission without/with Forward

Each of the five steps (tasks) requires different resources. If Forward functionality is not used, the sequences are
executed one after the other. Each resource is then only active if it is needed for the current sub-action.
With Forward, a resource that has executed its task can already be used for the next message. The condition for
enabling the MTU is changed to allow for this. Sequences are then passed to the MTU according to the timing. The
transmitting station no longer waits for an acknowledgment from SequenceAck, which means that the available
bandwidth can be used much more efficiently.
In the most ideal situation, all resources are working during each bus cycle. The receiver still has to acknowledge
every sequence received. Only when SequenceAck has been changed and checked by the transmitter is the
sequence considered as having been transmitted successfully.

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Configuration

The Forward function only has to be enabled for the input direction. Two additional configuration registers are
available for doing so. FlatStream modules have been optimized in such a way that they support this function. In
the output direction, the Forward function can be used as soon as the size of the OutputMTU is specified.

Number of unconfirmed sequences

Name:
Forward
With the "Forward" register, the user specifies how many unacknowledged sequences the module is allowed to
transmit.
Recommendation:
X2X Link: Max. 5
POWERLINK: Max. 7
Data type Value
USINT 1 to 7
Default: 1

Delay time

Name:
ForwardDelay
The "ForwardDelay" register is used to specify the delay time in µs. This is the amount of time the module has
to wait after sending a sequence until it is allowed to write new data to the MTU in the following bus cycle. The
program routine for receiving sequences from a module can therefore be run in a task class whose cycle time is
slower than the bus cycle.
Data type Value
UINT 0 to 65,535 [µs]
Default: 0

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Zeit

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Zeit

Figure 157: Effect of ForwardDelay when using FlatStream communication with the Forward function
In the program, it is important to make sure that the CPU is processing all of the incoming InputSequences and In-
putMTUs. The ForwardDelay value causes delayed acknowledgment in the output direction and delayed reception
in the input direction. In this way, the CPU has more time to process the incoming InputSequence or InputMTU.

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Transmitting and receiving with Forward

The basic algorithm for transmitting and receiving data remains the same. With the Forward function, up to seven
unacknowledged sequences can be transmitted. Sequences can be transmitted without having to wait for the
previous message to be acknowledged. Since the delay between writing and response is eliminated, a considerable
amount of additional data can be transferred in the same time window.
Algorithm for transmitting
Cyclic status query:
- The Module monitors the OutputSequenceCounter.
0) Cyclic checks:
- The CPU must check OutputSyncAck.
→ If OutputSyncAck = 0: Reset the OutputSyncBit and resynchronize the channel.
- The CPU must check whether OutputMTU is enabled.
→ If OutputSequenceCounter > OutputSequenceAck + 7, then it is not enabled because the last sequence has not yet been acknowledged.
1) Preparation (create transmit array):
- The CPU must split up the message into valid segments and create the necessary control bytes.
- The CPU must add the segments and control bytes to the transmit array.
2) Transmit:
- The CPU must transfer the current part of the transmit array to the OutputMTU.
- The CPU must increase the OutputSequenceCounter for the sequence to be accepted by the module.
- The CPU can then transmit in the next bus cycle if the MTU has been enabled.
The module responds since OutputSequenceCounter > OutputSequenceAck:
- The module accepts data from the internal receive buffer and appends it to the end of the internal receive array.
- The module is acknowledged and the currently received value of the OutputSequenceCounter is transferred to OutputSequenceAck.
- The module requests the status cyclically again.
3) Completion (acknowledgment):
- The CPU must check OutputSequenceAck cyclically.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via OutputSequenceAck. In order to detect potential trans-
mission errors in the last sequence as well, it is important to make sure that the algorithm is run through long enough.

Note:
To monitor communication times exactly, the task cycles that have passed since the last increase of the OutputSequenceCounter should be counted. In this
way, the number of previous bus cycles necessary for the transmission can be measured. If the monitoring counter exceeds a predefined threshold, then the
sequence can be considered lost (the relationship of bus to task cycle can be influenced by the user so that the threshold value needs to be determined individ-
ually).

Algorithm for receiving

0) Cyclic status query:
- The CPU must monitor the InputSequenceCounter.
Cyclic checks:
- The module checks InputSyncAck.
- The module checks if InputMTU is enabled.
→ Enabling criteria: InputSequenceCounter > InputSequenceAck + Forward
Preparation:
- The module forms the control bytes / segments and creates the transmit array.
Action:
- The module transmits the current part of the transmit array to the receive buffer.
- The module increases the InputSequenceCounter.
- The module waits for a new bus cycle after the ForwardDelay time has expired.
- The module repeats the action if the InputMTU is enabled.
1) Receiving (InputSequenceCounter > InputSequenceAck):
- The CPU must accept data from the InputMTU and append it to the end of the receive array.
- The CPU must match InputSequenceAck to the InputSequenceCounter of the sequence currently being processed.
Completion:
- The module monitors InputSequenceAck.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via InputSequenceAck .

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Details/Background
1. Illegal SequenceCounter size (counter offset)
Error situation: MTU not enabled
If the difference between SequenceCounter and SequenceAck is larger than allowed during transmission,
then a transmission error has occurred. In this case, all unacknowledged sequences must be repeated with
the old SequenceCounter value.
2. Checking an acknowledgment
After an acknowledgment has been received, a check must verify whether the acknowledged sequence has
been transmitted and had not yet been unacknowledged. If a sequence has been acknowledged more than
once, then a fatal error has occurred. The channel must be closed and resynchronized (same behavior as
when not using Forward).

Information:
In exceptional cases, the module can increment OutputSequenceAck by more than 1 when using
Forward.
This is not an error. The CPU is permitted to consider all sequences up to the one being acknowl-
edged as having been transmitted successfully.

3. Transmit and receive arrays

The Forward function has no effect on the structure of the transmit and receive arrays. They are created and
must be evaluated in the same way.

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Errors when using Forward

In industrial environments, it is often the case that many different devices from various manufacturers are being
used side by side. The electrical and/or electromagnetic properties of these technical devices can sometimes cause
them to interfere with one another. These kinds of situations can be reproduced and protected against in laboratory
conditions only to a certain point.
Precautions have been taken for X2X Link transmissions if this type of interference occurs. For example, if an
invalid checksum occurs, the I/O system will ignore the data from this bus cycle and the receiver receives the last
valid data once more. With conventional (cyclic) data points, this error can often be ignored. In the following cycle,
the same data point is again retrieved, adjusted and transmitted.
Using Forward functionality with FlatStream communication makes this situation more complex. The receiver re-
ceives the old data again in this situation as well, i.e. the previous values for SequenceAck/SequenceCounter and
the old MTU.
Loss of acknowledgment (SequenceAck)
If a SequenceAck value is lost, then the MTU was already transmitted properly. For this reason, the receiver is per-
mitted to continue processing with the next sequence. The SequenceAck is aligned with the associated Sequence-
Counter and sent back to the transmitter. Checking the incoming acknowledgments shows that all sequences up
to the last one acknowledged have been transmitted successfully (see sequences 1 and 2 in the image).
Loss of transmission (SequenceCounter, MTU):
If a bus cycle drops out and the SequenceCounter value and/or filled MTU are lost, then no data reaches the
receiver. At this point, the transmission routine is not yet affected by the error. The time-controlled MTU is released
again and can be rewritten to.
The receiver receives SequenceCounter values that have been incremented several times. For the receive array
to be put together correctly, the receiver is only allowed to process transmissions whose SequenceCounter has
been increased by one. The incoming sequences must be ignored, i.e. the receiver stops and no longer transmits
back any acknowledgments.
If the maximum number of unacknowledged sequences has been sent and no acknowledgments are returned, the
transmitter must repeat the affected SequenceCounter and associated MTUs (see sequence 3 and 4 in the image).

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Sequence 4 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Sequence 1 Step I Step II Step III

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step I Step II Step III

Sequence 4 Step I Step II Step I Step II

Bus cycle 1 Bus cycle 2 Bus cycle 3 EMC Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Figure 158: Effect of a lost bus cycle

Loss of acknowledgment
In sequence 1, the acknowledgment is lost due to disturbance. Sequences 1 and 2 are therefore acknowledged
in Step V of sequence 2.
Loss of transmission
In sequence 3, the entire transmission is lost due to disturbance. The receiver stops and no longer sends back
any acknowledgments.
The transmitting station continues transmitting until it has issued the maximum permitted number of unacknowl-
edged transmissions.
Five bus cycles later at the earliest (depending on the configuration), it begins resending the unsuccessfully sent
transmissions.

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4.3.14.10.20 Force analog energy registers

Name:
The registers are described under 4.3.14.10.10 "Analog energy registers". Comparison:
Force registers Read registers
Frc_APenergyT "APenergyT"
Frc_APenergyTF
Frc_APenergyTH
Frc_APenergyA "APenergyA"
Frc_APenergyAF
Frc_APenergyAH
Frc_APenergyB "APenergyB"
Frc_APenergyBF
Frc_APenergyBH
Frc_APenergyC "APenergyC"
Frc_APenergyCF
Frc_APenergyCH
Frc_ANenergyT "ANenergyT"
Frc_ANenergyTF
Frc_ANenergyTH
Frc_ANenergyA "ANenergyA"
Frc_ANenergyAF
Frc_ANenergyAH
Frc_ANenergyB "ANenergyB"
Frc_ANenergyBF
Frc_ANenergyBH
Frc_ANenergyC "ANenergyC"
Frc_ANenergyCF
Frc_ANenergyCH
Frc_RPenergyT "RPenergyT"
Frc_RPenergyA "RPenergyA"
Frc_RPenergyB "RPenergyB"
Frc_RPenergyC "RPenergyC"
Frc_RNenergyT "RNenergyT"
Frc_RNenergyA "RNenergyA"
Frc_RNenergyB "RNenergyB"
Frc_RNenergyC "RNenergyC"
Frc_SAenergyT "SAenergyT"
Frc_SenergyA "SenergyA"
Frc_SenergyB "SenergyB"
Frc_SenergyC "SenergyC"
Frc_SVenergyT "SVenergyT"

These registers can be used to set the energy counter to a specific value after a module has been replaced.
Data type Value
UDINT 0 to 4,294,967,295

4.3.14.10.20.1 Force forward total active energy

Name:
FrcAPenergyT
The registers are described under 4.3.14.10.10 "Analog energy registers".
These registers can be used to set the energy counter to a specific value after a module has been replaced. The
register is updated to the current values when triggered by ControlOutput, Bit 3.
Data type Value
UDINT 0 to 4,294,967,295

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4.3.14.10.21 Oversampling buffer

4.3.14.10.21.1 General information

A Sample Line contains the present values for currents (4 channels) and voltages (3 channels), as well as a
consecutive number and the network time when transferred from the transformer. These values are recorded in
an interval of 125 µs * prescaler.
The user must then scale the values to respective physical values:
Voltage: Vrms = (INT32)Vs * 4 / Sqrt(2)
Current: Irms = (INT32)Is * 4 / Sqrt(2)

4.3.14.10.21.2 Sample - Neutral current

Name:
IactN_Sample1 to IactN_Sample16
Data type Value Information
INT -32,767 to 32,767 Present value of the neutral current, resolution 0,001 A

This value must be converted by the application: See section 4.3.14.10.21.1 "General information"

4.3.14.10.21.3 Sample - Current on phase A

Name:
IactA_Sample1 to IactA_Sample16
Data type Value Information
INT -32,767 to 32,767 Present current value on phase A, resolution 0.001 A

This value must be converted by the application: See section 4.3.14.10.21.1 "General information"

4.3.14.10.21.4 Sample - Voltage on phase A

Name:
UactA_Sample1 to UactA_Sample16
Data type Value Information
INT -32,767 to 32,767 Present voltage value on phase A, resolution 0.01 V

This value must be converted by the application: See section 4.3.14.10.21.1 "General information"

4.3.14.10.21.5 Sample - Current on phase B

Name:
IactB_Sample1 to IactB_Sample16
Data type Value Information
INT -32,767 to 32,767 Present current value on phase B, resolution 0.001 A

This value must be converted by the application: See section 4.3.14.10.21.1 "General information"

4.3.14.10.21.6 Sample - Voltage on phase B

Name:
UactB_Sample1 to UactB_Sample16
Data type Value Information
INT -32,767 to 32,767 Present voltage value on phase B, resolution 0.01 V

This value must be converted by the application: See section 4.3.14.10.21.1 "General information"

4.3.14.10.21.7 Sample - Current on phase C

Name:
IactC_Sample1 to IactC_Sample16
Data type Value Information
INT -32,767 to 32,767 Present current value on phase C, resolution 0.001 A

This value must be converted by the application: See section 4.3.14.10.21.1 "General information"

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4.3.14.10.21.8 Sample - Voltage on phase C

Name:
UactC_Sample1 to UactC_Sample16
Data type Value Information
INT -32,767 to 32,767 Present voltage value on phase C, resolution 0.01 V

This value must be converted by the application: See section 4.3.14.10.21.1 "General information"

4.3.14.10.21.9 Sample number

Name:
SampleCount1 to Samplecount16
Number of new Sample Lines since last readout.
Data type Value Information
SINT -127 to 127 Sample Line number, ascending, cyclic
INT -32,767 to 32,767

4.3.14.10.21.10 Sample time

Name:
Timestamp
Older Sample Lines must each be back-calculated with 125 µs.
Data type Value Information
INT -32,767 to 32,767 Network timestamp of Sample Line 1
DINT -2,147,483,647 to 2,147,483,647

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4.3.14.10.22 Environment variables

4.3.14.10.22.1 Operating time in seconds

Name:
OnTime
The operating time since startup is saved in seconds in this register.
Data type Value
UDINT 0 to 4,294,967,295

4.3.14.10.22.2 Startup counter

Name:
UpCounter
The number of restarts since startup is saved in this register.
Data type Value
UDINT 0 to 4,294,967,295

4.3.14.10.22.3 Minimum operating temperature

Name:
MinTemp
The lowest transformer temperature [°C] since startup is saved in this register.
Data type Value Information
INT -200 to 200 Resolution 1°C

4.3.14.10.22.4 Maximum operating temperature

Name:
MaxTemp
The highest transformer temperature [°C] since startup is saved in this register.
Data type Value Information
INT -200 to 200 Resolution 1°C

4.3.14.10.23 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
200 µs

4.3.14.10.24 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Voltage and current sampling rate for calculation of effective value, power and energy 1 MHz
Derived values: RMS, power, energy, power factor, phase angle, frequency (mean values over 16 full waves) Approx. 3 Hz
FFT on request (SR: 8 kHz) 2 Hz

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4.4 Analog output modules

Analog output modules convert PLC internal numerical values into voltages or currents. The numerical values
which are to be converted must be in 16-bit 2s complement. The conversion takes place independently of the
resolution of the output module used.
Every channel on an analog output module has a status LED.

4.4.1 Brief information

Product ID Short description on page
X20AO2437 X20 analog output module, 2 outputs, 4 to 20 mA / 0 to 20 mA or 0 to 24 mA 16-bit resolution, single channel 390
electrically isolated
X20AO2438 X20 analog output module, 2 outputs, 4 to 20 mA / 0 to 20 mA or 0 to 24 mA 16-bit resolution single channel 401
electrically isolated, supports the HART protocol
X20AO2622 X20 analog output module, 2 outputs, ±10 V / 0 to 20 mA / 4 to 20 mA, 13-bit resolution 454
X20AO2632 X20 analog output module, 2 outputs, ±10 V / 0 to 20 mA, 16-bit resolution 460
X20AO2632-1 X20 analog output module, 2 outputs, ±11 V / 0 to 22 mA, 16-bit resolution 467
X20AO4622 X20 analog output module, 4 outputs, ±10 V / 0 to 20 mA / 4 to 20 mA, 13-bit resolution 474
X20AO4632 X20 analog output module, 4 outputs, ±10 V / 0 to 20 mA, 16-bit resolution 481
X20AO4632-1 X20 analog output module, 4 outputs, ±11 V / 0 to 22 mA, 16-bit resolution 489
X20AO4635 X20 analog output module, 4 outputs, ±10 V / 0 to 20 mA, 16-bit resolution low temperature drift 498

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4.4.2 X20AO2437

4.4.2.1 General information

The X20AO2437 module is equipped with two current outputs with 16-bit digital converter resolution. The two
channels are electrically isolated from each other. The user can select between the three output ranges 4 to 20 mA,
0 to 20 mA and 0 to 24 mA.
• 2 analog current outputs
• Electrically isolated analog channels
• 16-bit digital converter resolution

4.4.2.2 Order data

Model number Short description Figure

Analog output modules
X20AO2437 X20 analog output module, 2 outputs, 4 to 20 mA / 0 to 20 mA or
0 to 24 mA 16-bit resolution, single channel electrically isolated
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 79: X20AO2437 - Order data

4.4.2.3 Technical data

Product ID X20AO2437
Short description
I/O module 2 analog outputs 4 to 20 mA, 0 to 20 mA or 0 to 24 mA
General information
B&R ID code 0xB785
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, using status LED and software
Power consumption
Bus 0.05 W
Internal I/O 1.6 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel Yes
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Analog outputs
Output 4 to 20 mA, 0 to 20 mA or 0 to 24 mA, configurable using software
Digital converter resolution 16-bit
Settling time for output changes over entire range 2 ms to 20 s, configurable using software
Data output rate 1 ms without ramp

Table 80: X20AO2437 - Technical data

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Product ID X20AO2437
Max. error at 25°C
Gain
4 to 20 mA 0.025% 1)
0 to 20 mA 0.022% 1)
0 to 24 mA 0.020% 1)
Offset
4 to 20 mA 0.025% 2)
0 to 20 mA 0.022% 2)
0 to 24 mA 0.020% 2)
Output protection Short circuit protection, overvoltage protection (up to 30 VDC)
Open line detection Yes, using hardware and software
Data format INT
Output format
4 to 20 mA INT 0x0000 to 0x7FFF / 1 LSB = 0x0001 = 762.94 nA
0 to 20 mA INT 0x0000 to 0x7FFF / 1 LSB = 0x0001 = 610.352 nA
UINT 0x0000 to 0xFFFF / 1 LSB = 0x0001 = 305.176 nA
0 to 24 mA INT 0x0000 to 0x5DC0 / 1 LSB = 0x0001 = 1000 nA
Load per channel Max. 600 Ω
Short circuit protection Yes, continuous
Output filter Active 2nd-order low pass / cutoff frequency 4 kHz
Configurable slew rate
Maximum gain drift
4 to 20 mA 0.0055 %/°C 1)
0 to 20 mA 0.005 %/°C 1)
0 to 24 mA 0.005 %/°C 1)
Maximum offset drift
4 to 20 mA 0.0035 %/°C 2)
0 to 20 mA 0.002 %/°C 2)
0 to 24 mA 0.002 %/°C 2)
Error caused by load change 3)
4 to 20 mA 0.14%
0 to 20 mA 0.10%
0 to 24 mA 0.10%
Non-linearity <0.003% 4)
Test voltage between
Channel and channel 1000 VAC
Channel and bus 1000 VAC
To ground 1000 VAC
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 80: X20AO2437 - Technical data

1) Based on the current output value.
2) Based on the respective output range
3) Load change from 1 Ω → 600 Ω, resistive
4) Based on the entire output range.

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4.4.2.4 LED status indicators

Figure LED Color Status Description

Operating status
r Green Off No power to module
Single flash UNLINK mode
Double flash BOOT mode (during firmware update)1)
Blinking quickly SYNC mode
Blinking slowly PREOPERATIONAL mode
On RUN mode
Flickering Module is in OSP mode
(approx. 10 Hz)
Module status
e Red Off No power to module or everything OK
Single flash A conversion error has occurred. When an error occurs, the LED of the faulty
analog output channel begins to double flash and this status is output.
On Error or reset status
Analog output
1-2 Orange Off Indicates one of the following cases:
• No power to module
• Channel disabled
Single flash Open line
Double flash A conversion error has occurred. A single flash is output on the red "e" module
status LED.
On Digital/analog converter running, value OK

Table 81: LED status indicators

1) Depending on the configuration, a firmware update can take up to several minutes.

4.4.2.5 Pinout

r e
X20 AO 2437

1 2

Channel 1 +

Channel 1 −

Channel 2 +

Channel 2 −

Figure 159: Pinout

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4.4.2.6 Connection example

With external
AO Power supply

4-wire
Actuator

4-wire
Actuator

+24 VDC +24 VDC

GND GND

Figure 160: Connection example

4.4.2.7 OSP hardware requirements

In order to best use OSP mode, make sure when creating the application that the output module and CPU have
separate power supplies.

4.4.2.8 Output circuit diagram

I/O status
Processor

Electrical
Isolation
LED (orange)
I/O
Power supplies
GND x Power supply

Channel x +
D/A
Converter GND x GND I/O
Channel x -
GND x

Figure 161: Output circuit diagram

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4.4.2.9 Derating

To ensure proper operation, the derating values listed below must be adhered to:
Horizontal installation
Horizontal installation

600

500

400 60°C / 400 Ω

Load [Ω]

300

Prohibited
200
Range

100
50°C / 0 Ω
0
-20 -10 0 10 20 30 40 50 60

Ambient temperature [°C]

Figure 162: Derating the load with horizontal mounting

Vertical installation
Vertical installation

600

500

400
Prohibited
Range
Load [Ω]

300

200 50°C / 200 Ω

100
45°C / 0 Ω
0
-20 -10 0 10 20 30 40 50 60

Ambient temperature [°C]

Figure 163: Derating the load with vertical mounting

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4.4.2.10 Register description

4.4.2.10.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
386 AnalogMode01 UINT ●
394 AnalogMode02
390 DACSlewrate01 UINT ●
398 DACSlewrate02
Analog signal - Communication
0 AnalogOutput01 (U)INT ●
2 AnalogOutput02
30 AnalogStatus01 USINT ●
31 AnalogStatus02
OpenLineAnalogOutput01 or OpenLineAnalogOutput02 Bit 2
ConversionErrorAnalogOutput01 or Bit 3
ConversionErrorAnalogOutput02
IoSuppErrorAnalogOutput01 or IoSuppErrorAnalogOutput02 Bit 7

4.4.2.10.2 Function model 1 - OSP

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
386 AnalogMode01 UINT ●
394 AnalogMode02
390 DACSlewrate01 UINT ●
398 DACSlewrate02
Analog signal - Communication
0 AnalogOutput01 (U)INT ●
2 AnalogOutput02
30 AnalogStatus01 USINT ●
31 AnalogStatus02
OpenLineAnalogOutput01 or OpenLineAnalogOutput02 Bit 2
ConversionErrorAnalogOutput01 or Bit 3
ConversionErrorAnalogOutput02
IoSuppErrorAnalogOutput01 or IoSuppErrorAnalogOutput02 Bit 7
The OSP function model
32 OSPComByte USINT ●
OSPValid Bit 0
401 CfgOSPMode01 USINT ●
403 CfgOSPMode02
34 CfgOSPValue01 INT ●
36 CfgOSPValue02

4.4.2.10.3 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
386 - AnalogMode01 UINT ●
394 AnalogMode02
390 - DACSlewrate01 UINT ●
398 DACSlewrate02
Analog signal - Communication
0 0 AnalogOutput01 (U)INT ●
2 2 AnalogOutput02
30 - AnalogStatus01 USINT ●
31 AnalogStatus02
OpenLineAnalogOutput01 or Bit 2
OpenLineAnalogOutput02
ConversionErrorAnalogOutput01 or Bit 3
ConversionErrorAnalogOutput02
IoSuppErrorAnalogOutput01 or Bit 7
IoSuppErrorAnalogOutput02

1) The offset specifies the position of the register within the CAN object.

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4.4.2.10.4 Analog signal - Configuration

The module has two electrically isolated channels. All registers have a dual design. Channels can be configured
and operated independently of one another.
Specific features
• Electrical isolation by channel
• Configurable output ramp DAC slew rate (Default: 210 ms full scale)

4.4.2.10.4.1 AnalogMode

Name:
AnalogMode01 to AnalogMode02
These registers are used to predefine the operating parameters that the module will be using for the respective
channel. Each channel must be activated and configured separately.

Information:
When you select the operating mode "Scaling 0 to 20 mA (Resolution 0 to 65535)", then the corre-
sponding "AnalogOutput" registers are interpreted internally as UINT instead of INT.
The entire program must be rebuilt for the data type change to take effect. The data type cannot be
changed during runtime (e.g. using a library).
Data type Value
UINT See bit structure.

Bit structure:
Bit Name Value Information
0 Channel 0 Disabled
1 Enabled (bus controller default)
1 Check - DAC configuration/status 0 Enabled (bus controller default)
1 Disabled
2-3 Reserved -
4 Scaling 0 to 20 mA 0 Disabled
(Resolution 0 to 32767) 1 Enabled
5 Scaling 4 to 20 mA 0 Disabled
(Resolution 0 to 32767) 1 Enabled (bus controller default)
6 Scaling 0 to 24 mA 0 Disabled
(Resolution 0 to 24000) 1 Enabled
7 Scaling 0 to 20 mA 0 Disabled
(Resolution 0 to 65535) 1 Enabled
8 - 15 Reserved -

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4.4.2.10.4.2 DACSlewrate

Name:
DACSlewrate01 to DACSlewrate02
These registers limit the rate at which the analog signal is modified. This makes it possible to define a sort of upper
limit frequency.
The following formula f(Analog) = f(Output rate) * Permitted change / max. ∆(standardized output value)
applies:
Data type Value
UINT See bit structure

Bit structure:
Bit Name Value Information
0-2 Permitted change per rate 000 1-bit
001 2-bit
010 4 bit (bus controller default)
011 8-bit
100 16-bit
101 32-bit
110 64-bit
111 128-bit
3-7 Reserved -
8 - 11 Output rate 0000 257730 Hz
0001 198410 Hz
0010 152440 Hz (bus controller default)
0011 131580 Hz
0100 115740 Hz
0101 69440 Hz
0110 37590 Hz
0111 25770 Hz
1000 20160 Hz
1001 16030 Hz
1010 10290 Hz
1011 8280 Hz
1100 6900 Hz
1101 5530 Hz
1110 4240 Hz
1111 3300 Hz
12 - 14 Reserved -
15 Slewrate enable 0 Disabled (undefined jump behavior)
(ramp functionality) 1 Enabled (defined transitions)

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4.4.2.10.5 Analog signal - Communication

In order to output the required current signal (default: 4 to 20 mA), the module must be provided with the standard-
ized output value (default: 0 to 32767).

4.4.2.10.5.1 AnalogOutput

Name:
AnalogOutput01 to AnalogOutput02
These registers provide the standardized output values. Depending on the scaling selected (see AnalogMode
register), the value range and the data type can be adapted to the requirements of the application. Once a permitted
value is determined, the module outputs the respective current.

Information:
The value "0" disables the channel status LED.
Data type Value Information
INT 0 to 32767 Bus controller default: 0
Optional: UINT 0 to 65535

4.4.2.10.5.2 AnalogStatus

Name:
AnalogStatus01 to AnalogStatus02
The status register gives the user feedback about whether the respective channel is functioning properly.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Value Information
0-1 Reserved -
2 OpenLineAnalogOutput01, 02 0 Line OK
1 Open line
3 ConversionErrorAnalogOutput01, 02 0 Conversion temperature OK
1 Conversion temperature too high
4-6 Reserved -
7 IoSuppErrorAnalogOutput01, 02 0 Module supply OK
1 Module supply error

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4.4.2.10.6 "OSP" function model

In the "OSP" function model (Operator Set Predefined), the user defines an analog value or digital pattern. This
OSP value is output as soon as communication between the module and master is interrupted.
Functionality
The user can choose between two OSP modes:
• Retain last valid value
• Replace with static value
In the first case, the module retains the last value as validly recognized output state.
When selecting the mode, "Replace with static value" a plausible output value must be entered in the corresponding
value register. If an OSP event occurs, this value will be output instead of the value currently requested by the task.

4.4.2.10.6.1 Activating the OSP output in the module

Name:
OSPValid
This data point offers the possibility to start module output and request OSP operation during running operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 OSPValid 0 Request OSP operation (after initial start or module in Standby)
1 Request normal operation
1-7 Reserved 0

There is one OSPValid bit on the module, which is managed by the user task. It must be set when the enabled
channels are started. As long as the OSPValid bit remains set in the module, the module behaves the same as
the "Standard" function model.
If an OSP event occurs (e.g. communication between the module and master CPU interrupted) then the OSPValid
bit will be reset on the module. The module enters OSP mode and the output occurs in the "OSPMode" register
according to the configuration.
The following applies:
The OSP replacement value remains even after the communication channel has recovered. OSP mode
is only exited when a set OSPValid bit is transferred.
When the master CPU is restarted, the OSPValid bit is re-initialized on the master CPU. It must once
more be set by the application and transferred via the bus.
When temporary communication errors occur between the module and master CPU (e.g. due to EMC),
a few bus cycles will pass without refreshing the cyclic registers. The OSPValid bit is reset internally in
the module - the bit in the CPU however remains set. Upon the next successful transfer, the OSPValid
bit in the module is set again and the module returns to normal operation.
The ModulOK bit can be evaluated if the task in the master CPU needs to know which output mode the module
is currently in.

Warning!
If the OSPValid bit is reset to "0" on the module, then the output state no longer depends on the relevant
task in the master CPU. However, an output still occurs depending on the configuration of the OSP
replacement value.

4.4.2.10.6.2 Setting the OSP mode

Name:
CfgOSPMode01 to CfgOSPMode02
This register essentially controls a channel's behavior when OSP is being used.
Data type Value Description
USINT 0 Replace with static value
1 Retain last valid value

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4.4.2.10.6.3 Define the OSP analog output value

Name:
CfgOSPValue01 to CfgOSPValue02
This register contains the analog output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
Corresponds to Corresponds to AnalogOutput0x
AnalogOutput0x

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.4.2.10.7 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
200 µs

4.4.2.10.8 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
200 µs

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4.4.3 X20AO2438

4.4.3.1 General information

The X20AO2438 module is equipped with two current outputs with 16-bit digital converter resolution. It supports
the HART communication standard for data transfer, parameter configuration and diagnostics.
The two channels are electrically isolated from each other. The user can select between the three output ranges
4 to 20 mA, 0 to 20 mA and 0 to 24 mA.
• 2 analog current outputs
• HART protocol integration
• Support for HART variables
• Electrically isolated analog channels
• 16-bit digital converter resolution

4.4.3.2 Order data

Model number Short description Figure

Analog output modules
X20AO2438 X20 analog output module, 2 outputs, 4 to 20 mA / 0 to 20 mA or
0 to 24 mA 16-bit resolution single channel electrically isolated,
supports the HART protocol
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 82: X20AO2438 - Order data

4.4.3.3 Technical data

Product ID X20AO2438
Short description
I/O module 2 analog outputs 4 to 20 mA, 0 to 20 mA or 0 to 24 mA
General information
B&R ID code 0xB3AA
Status indicators I/O function per channel, operating state, module status, HART
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, using status LED and software
HART link Yes, using status LED and software
HART error Yes, using status LED and software
Power consumption
Bus 0.05 W
I/O internal 1.65 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel Yes
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Analog outputs
Output 4 to 20 mA, 0 to 20 mA or 0 to 24 mA, configurable using software
Digital converter resolution 16-bit
Settling time for output changes over entire range 2 ms to 20 s, configurable using software

Table 83: X20AO2438 - Technical data

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Product ID X20AO2438
Data output rate
With Hart 210 ms (default)
Analog 1 ms without ramp
Max. error at 25°C
Gain
4 to 20 mA 0.025% 1)
0 to 20 mA 0.022% 1)
0 to 24 mA 0.020% 1)
Offset
4 to 20 mA 0.025% 2)
0 to 20 mA 0.022% 2)
0 to 24 mA 0.020% 2)
Output protection Short circuit protection, overvoltage protection (up to 30 VDC)
Open line detection Yes, using hardware and software
Data format INT
Output format
4 to 20 mA INT 0x0000 to 0x7FFF / 1 LSB = 0x0001 = 762.94 nA
0 to 20 mA INT 0x0000 to 0x7FFF / 1 LSB = 0x0001 = 610.352 nA
UINT 0x0000 to 0xFFFF / 1 LSB = 0x0001 = 305.176 nA
0 to 24 mA INT 0x0000 to 0x5DC0 / 1 LSB = 0x0001 = 1000 nA
Load per channel Max. 600 Ω
Short circuit proof Yes, continuous
Output filter Active 2nd-order low pass / cutoff frequency 19 Hz
Configurable slew rate
Maximum gain drift
4 to 20 mA 0.0055 %/°C 1)
0 to 20 mA 0.005 %/°C 1)
0 to 24 mA 0.005 %/°C 1)
Maximum offset drift
4 to 20 mA 0.0035 %/°C 2)
0 to 20 mA 0.002 %/°C 2)
0 to 24 mA 0.002 %/°C 2)
Error caused by load change 3)
4 to 20 mA 0.14%
0 to 20 mA 0.10%
0 to 24 mA 0.10%
Non-linearity <0.003% 4)
Test voltage between
Channel and channel 1000 VAC
Channel and bus 1000 VAC
To ground 1000 VAC
HART
Transfer rate 1200 bit/s
Operating frequencies 1200 Hz / 2200 Hz
Burst operation possible Yes
Multi-drop operation
possible Yes
Participants Up to 15
Transmission amplitude
Minimum 400 mVpp
Typical 500 mVpp
Maximum 600 mVpp
Receiving amplitude
Minimum 120 mVpp
Maximum 1500 mVpp
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing

Table 83: X20AO2438 - Technical data

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Product ID X20AO2438
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 83: X20AO2438 - Technical data

1) Based on the current output value.
2) Based on the respective output range
3) Load change from 1 Ω → 600 Ω, resistive
4) Based on the entire output range.

4.4.3.4 LED status indicators

Figure LED Color Status Description

Operating status
r Green Off No power to module
Single flash UNLINK mode
Double flash BOOT mode (during firmware update)1)
Blinking quickly SYNC mode
Blinking slowly PREOPERATIONAL mode
On RUN mode
Flickering Module is in OSP mode
(approx. 10 Hz)
Module status
e Red Off No power to module or everything OK
Single flash A conversion error has occurred. When an error occurs, the LED of the faulty
analog output channel begins to double flash and this status is output.
On Error or reset status
Analog output
1-2 Orange Off Indicates one of the following cases:
• No power to module
• Channel disabled
Single flash Open line
Double flash A conversion error has occurred. A single flash is output on the red "e" module
status LED.
On Digital/analog converter running, value OK
HART link
L Green Off Indicates one of the following cases:
• No power to module
• HART disabled for the respective channel
Flickering Carrier signal active (DCD or RTS)
HART error
e Red Off Indicates one of the following cases:
• Communication taking place without errors
• No power to module
• HART disabled for the respective channel
On Communication error

Table 84: LED status indicators

1) Depending on the configuration, a firmware update can take up to several minutes.

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4.4.3.5 Pinout

r e
1 2
L L
e e

Channel 1 +

Channel 1 −

Channel 2 +

Channel 2 −

Figure 164: Pinout

4.4.3.6 Connection example

With external
AO Power supply

4-wire
Actuator

4-wire
Actuator

+24 VDC +24 VDC

GND GND

Figure 165: Connection example

4.4.3.7 OSP hardware requirements

In order to best use OSP mode, make sure when creating the application that the output module and CPU have
separate power supplies.

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4.4.3.8 Output circuit diagram

I/O status

LED (orange)

GND x

HART link
Processor

LED (green)

GND x

HART error

LED (red)

GND x Electrical
Isolation
Receiving HART Power I/O
Modem sections Power supply

Transfer the file.

Channel x + GND x GND I/O

D/A
converter
Channel x -
GND x

Figure 166: Output circuit diagram

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4.4.3.9 Operation

4.4.3.9.1 Derating

To ensure proper operation, the derating values listed below must be adhered to:

Horizontal installation
Horizontal installation

600

500

400 60°C / 400 Ω

Load [Ω]

300

Prohibited
200
Range

100
50°C / 0 Ω
0
-20 -10 0 10 20 30 40 50 60

Ambient temperature [°C]

Figure 167: Derating the load with horizontal mounting

Vertical installation
Vertical installation

600

500

400
Prohibited
Range
Load [Ω]

300

200 50°C / 200 Ω

100
45°C / 0 Ω
0
-20 -10 0 10 20 30 40 50 60

Ambient temperature [°C]

Figure 168: Derating the load with vertical mounting

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4.4.3.9.2 HART communication standard

This module supports the HART communication standard for data transfer, parameter configuration and diagnos-
tics. The HART standard is used for the current range 4 to 20 mA. Be aware that the load is not permitted to fall
below 230 Ω .
600

500 Prohibited
Range
Specified
400 HART operational range
Load [Ω]

300

200

100

0
0 2 4 6 8 10 12 14 16 18 20 22 24

Current [mA]

Figure 169: Specified HART operational range

Both current ranges 0 to 20 mA and 0 to 24 mA are supported by this module. HART communication can also be
used in these ranges as well. It is important to make sure, however, that the output current lies within the specified
HART operational range.

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4.4.3.10 Register description

4.4.3.10.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
386 AnalogMode01 UINT ●
394 AnalogMode02
390 DACSlewrate01 UINT ●
398 DACSlewrate02
Analog signal - Communication
0 AnalogOutput01 (U)INT ●
2 AnalogOutput02
30 AnalogStatus01 USINT ●
31 AnalogStatus02
OpenLineAnalogOutput01 or OpenLineAnalogOutput02 Bit 2
ConversionErrorAnalogOutput01 or Bit 3
ConversionErrorAnalogOutput02
IoSuppErrorAnalogOutput01 or Bit 7
IoSuppErrorAnalogOutput02
HART - Configuration
1537 HartNodeCnt_1 USINT ●
1665 HartNodeCnt_2
1539 HartMode_1 USINT ●
1667 HartMode_2
1541 HartBurstNode_1 USINT ●
1669 HartBurtNode_2
HART - Extended configuration
1558 HartNodeDisable_1 UINT ●
1668 HartNodeDisable_2
1546 HartProtTimeOut_1 UINT ●
1674 HartProtTimeOut_2
1550 HartProtRetry_1 UINT ●
1678 HartProtRetry_2
1554 HartPreamble_1 UINT ●
1682 HartPreamble_2
HART - Communication (P2P)
612 + Index*24 PvInput01_N (Index N = 01 to 04) REAL ● ●1)
1124 + Index*24 PvInput02_N (Index N = 01 to 04)
617 + Index*24 PvUnit01_N (Index N = 01 to 04) USINT ● ●1)
1129 + Index*24 PvUnit02_N (Index N = 01 to 04)
628 PvSampleTime01 DINT ● ●1)
1140 PvSampleTime02
626 PvSampleTime01 INT ●
1138 PvSampleTime02
566 PvNodeComStatus01 UINT ●
1078 PvNodeComStatus02
HART - Communication (multidrop)
612 + Index*24 PvInput01_N (Index N = 01 to 15) REAL ● ●1)
1124 + Index*24 PvInput02_N (Index N = 01 to 15)
617 + Index*24 PvUnit01_N (Index N = 01 to 15) USINT ● ●1)
1129 + Index*24 PvUnit02_N (Index N = 01 to 15)
604 + Index*24 PvSampleTime01_N (Index N = 01 to 15) DINT ● ●1)
1116 + Index*24 PvSampleTime02_N (Index N = 01 to 15)
602 + Index*24 PvSampleTime01_N (Index N = 01 to 15) INT ●
1114 + Index*24 PvSampleTime02_N (Index N = 01 to 15)
562 + Index*4 PvNodeComStatus01_N (Index N = 01 to 15) UINT ●
1116 + Index*24 PvNodeComStatus02_N (Index N = 01 to 15)
HART - Extended communication
522 PvCountHartRequest01 UINT ●
1034 PvCountHartRequest02
530 PvCountHartTimeout01 UINT ●
1042 PvCountHartTimeout02
538 PvCountHartRxError01 UINT ●
1050 PvCountHartRxError02
546 PvCountHartFrameError01 UINT ●
1058 PvCountHartFrameError02
554 PvNodeFound01 UINT ●
1066 PvNodeFound02
558 PvNodeError01 UINT ●
1070 PvNodeError02
FlatStream interface - Configuration
1793 OutputMTU USINT ●
1795 InputMTU USINT ●
1797 FlatstreamMode USINT ●
1799 Forward USINT ●
1802 ForwardDelay UINT ●
FlatStream interface - Communication

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Register Name Data type Read Write
Cyclic Non-cyclic Cyclic Non-cyclic
1857 InputSequence USINT ●
1857 + Index*2 RxByteN (Index N = 1 to 15) USINT ●
1889 OutputSequence USINT ●
1889 + Index*2 TxByteN (Index N = 1 to 15) USINT ●

1) These HART registers are defined multiple times. Hence, they can be activated acyclically, if they are not registered during the cyclical phase of the X2X
transmission.

4.4.3.10.2 Function model 1 - OSP

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
386 AnalogMode01 UINT ●
394 AnalogMode02
390 DACSlewrate01 UINT ●
398 DACSlewrate02
Analog signal - Communication
0 AnalogOutput01 (U)INT ●
2 AnalogOutput02
30 AnalogStatus01 USINT ●
31 AnalogStatus02
OpenLineAnalogOutput01 or OpenLineAnalogOutput02 Bit 2
ConversionErrorAnalogOutput01 or Bit 3
ConversionErrorAnalogOutput02
IoSuppErrorAnalogOutput01 or Bit 7
IoSuppErrorAnalogOutput02
HART - Configuration
1537 HartNodeCnt_1 USINT ●
1665 HartNodeCnt_2
1539 HartMode_1 USINT ●
1667 HartMode_2
1541 HartBurstNode_1 USINT ●
1669 HartBurtNode_2
HART - Extended configuration
1558 HartNodeDisable_1 UINT ●
1668 HartNodeDisable_2
1546 HartProtTimeOut_1 UINT ●
1674 HartProtTimeOut_2
1550 HartProtRetry_1 UINT ●
1678 HartProtRetry_2
1554 HartPreamble_1 UINT ●
1682 HartPreamble_2
HART - Communication (P2P)
612 + Index*24 PvInput01_N (Index N = 01 to 04) REAL ● ●1)
1124 + Index*24 PvInput02_N (Index N = 01 to 04)
617 + Index*24 PvUnit01_N (Index N = 01 to 04) USINT ● ●1)
1129 + Index*24 PvUnit02_N (Index N = 01 to 04)
628 PvSampleTime01 DINT ● ●1)
1140 PvSampleTime02
626 PvSampleTime01 INT ●
1138 PvSampleTime02
566 PvNodeComStatus01 UINT ●
1078 PvNodeComStatus02
HART - Communication (multidrop)
612 + Index*24 PvInput01_N (Index N = 01 to 15) REAL ● ●1)
1124 + Index*24 PvInput02_N (Index N = 01 to 15)
617 + Index*24 PvUnit01_N (Index N = 01 to 15) USINT ● ●1)
1129 + Index*24 PvUnit02_N (Index N = 01 to 15)
604 + Index*24 PvSampleTime01_N (Index N = 01 to 15) DINT ● ●1)
1116 + Index*24 PvSampleTime02_N (Index N = 01 to 15)
602 + Index*24 PvSampleTime01_N (Index N = 01 to 15) INT ●
1114 + Index*24 PvSampleTime02_N (Index N = 01 to 15)
562 + Index*4 PvNodeComStatus01_N (Index N = 01 to 15) UINT ●
1116 + Index*24 PvNodeComStatus02_N (Index N = 01 to 15)
HART - Extended communication
522 PvCountHartRequest01 UINT ●
1034 PvCountHartRequest02
530 PvCountHartTimeout01 UINT ●
1042 PvCountHartTimeout02
538 PvCountHartRxError01 UINT ●
1050 PvCountHartRxError02
546 PvCountHartFrameError01 UINT ●
1058 PvCountHartFrameError02
554 PvNodeFound01 UINT ●
1066 PvNodeFound02
558 PvNodeError01 UINT ●
1070 PvNodeError02

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Register Name Data type Read Write
Cyclic Non-cyclic Cyclic Non-cyclic
FlatStream interface - Configuration
1793 OutputMTU USINT ●
1795 InputMTU USINT ●
1797 FlatstreamMode USINT ●
1799 Forward USINT ●
1802 ForwardDelay UINT ●
FlatStream interface - Communication
1857 InputSequence USINT ●
1857 + Index*2 RxByteN (Index N = 1 to 15) USINT ●
1889 OutputSequence USINT ●
1889 + Index*2 TxByteN (Index N = 1 to 15) USINT ●
The OSP function model
32 OSPComByte USINT ●
OSPValid Bit 0
401 CfgOSPMode01 USINT ●
403 CfgOSPMode02
34 CfgOSPValue01 INT ●
36 CfgOSPValue02

1) These HART registers are defined multiple times. Hence, they can be activated acyclically, if they are not registered during the cyclical phase of the X2X
transmission.

4.4.3.10.3 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
386 - AnalogMode01 UINT ●
394 - AnalogMode02
390 - DACSlewrate01 UINT ●
398 - DACSlewrate02
Analog signal - Communication
0 0 AnalogOutput01 (U)INT ●
2 8 AnalogOutput02
30 - AnalogStatus01 USINT ●
31 - AnalogStatus02
OpenLineAnalogOutput01 or Bit 2
OpenLineAnalogOutput02
ConversionErrorAnalogOutput01 or Bit 3
ConversionErrorAnalogOutput02
IoSuppErrorAnalogOutput01 or Bit 7
IoSuppErrorAnalogOutput02
HART - Configuration
1537 - HartNodeCnt_1 USINT ●
1665 - HartNodeCnt_2
1539 - HartMode_1 USINT ●
1667 - HartMode_2
1541 - HartBurstNode_1 USINT ●
1669 - HartBurtNode_2
HART - Extended configuration
1558 - HartNodeDisable_1 UINT ●
1668 - HartNodeDisable_2
1546 - HartProtTimeOut_1 UINT ●
1674 - HartProtTimeOut_2
1550 - HartProtRetry_1 UINT ●
1678 - HartProtRetry_2
1554 - HartPreamble_1 UINT ●
1682 - HartPreamble_2
HART - Communication (P2P)
636 4 PvInput01_01 REAL ●
1148 12 PvInput02_01
612 + Index*24 - PvInput01_N (Index N = 02 to 04) REAL ●
1124 + Index*24 - PvInput02_N (Index N = 02 to 04)
641 2 PvUnit01_01 USINT ●
1153 10 PvUnit02_01
617 + Index*24 - PvUnit01_N (Index N = 02 to 04) USINT ●
1129 + Index*24 - PvUnit02_N (Index N = 02 to 04)
566 - PvNodeComStatus01 UINT ●
1078 - PvNodeComStatus02
HART - Communication (multidrop)
636 4 PvInput01_01 REAL ●
1148 12 PvInput02_01
612 + Index*24 - PvInput01_N (Index N = 02 to 15) REAL ●
1124 + Index*24 - PvInput02_N (Index N = 02 to 15)
641 2 PvUnit01_01 USINT ●
1153 10 PvUnit02_01
617 + Index*24 - PvUnit01_N (Index N = 02 to 15) USINT ●
1129 + Index*24 - PvUnit02_N (Index N = 02 to 15)

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Register Offset1) Name Data type Read Write
Cyclic Non-cyclic Cyclic Non-cyclic
562 + Index*4 - PvNodeComStatus01_N (Index N = 01 to UINT ●
1116 + Index*24 - 15)
PvNodeComStatus02_N (Index N = 01 to
15)
HART - Extended communication
522 - PvCountHartRequest01 UINT ●
1034 - PvCountHartRequest02
530 - PvCountHartTimeout01 UINT ●
1042 - PvCountHartTimeout02
538 - PvCountHartRxError01 UINT ●
1050 - PvCountHartRxError02
546 - PvCountHartFrameError01 UINT ●
1058 - PvCountHartFrameError02
554 - PvNodeFound01 UINT ●
1066 - PvNodeFound02
558 - PvNodeError01 UINT ●
1070 - PvNodeError02

1) The offset specifies the position of the register within the CAN object.

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4.4.3.10.4 Analog signal - Configuration

The X20AO2438 module has two independent electrically isolated channels with integrated HART modems. Both
channels can be used to output an analog signal and handle HART communication. Two registers need to be
configured for one analog signal. The two channels operate independently, so two registers must be configured
per channel to be used.
The current outputs (default: 4 to 20 mA) can be used as conventional analog signals. The integrated HART
modems retrieve digital information from the memory on the HART slave using the same physical lines that mod-
ulate the HART signals.
Each channel can use one of the following connection variants:
• Point-to-point (connection of one HART node on the channel):
→ Evaluation of the analog signal
and
→ Recording of up to 4 HART values
• Multidrop (connection of up to 15 HART nodes on the channel):
→ Recording of one HART value per connected node
Specific features
• Electrical isolation by channel
• Up to 4 or 15 HART input variables per channel
• Configurable output rate (DAC slew rate) to transfer HART and analog signal without interference (default:
210 ms full scale)
• Selectable error strategy (static replacement value or retention of the last permitted value)
• Cyclic "HART status" polling (HART command 0), the status information received is made available for
channel diagnostics
• Compatible with an additional secondary master in the HART network (module acts as the primary master)
• "HART communication error bit" (shows loss of HART connection if a connection had already been estab-
lished successfully)
• Optional: BURST mode for one node per channel
• Optional: Cyclic polling of "HART variables" (HART command 3 or 9)
• Optional: FlatStream functionality (module acts as bridge for HART packets)

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4.4.3.10.4.1 AnalogMode

Name:
AnalogMode01 to AnalogMode02
These registers are used to predefine the operating parameters that the module will be using for the respective
channel. Each channel must be activated and configured separately.

Information:
When you select the operating mode "Scaling 0 to 20 mA (Resolution 0 to 65535)", then the corre-
sponding "AnalogOutput" registers are interpreted internally as UINT instead of INT.
The entire program must be rebuilt for the data type change to take effect. The data type cannot be
changed during runtime (e.g. using a library).
Data type Value
UINT See bit structure.

Bit structure:
Bit Name Value Information
0 Channel 0 Disabled
1 Enabled (bus controller default)
1 Check - DAC configuration/status 0 Enabled (bus controller default)
1 Disabled
2-3 Reserved -
4 Scaling 0 to 20 mA 0 Disabled
(Resolution 0 to 32767) 1 Enabled
5 Scaling 4 to 20 mA 0 Disabled
(Resolution 0 to 32767) 1 Enabled (bus controller default)
6 Scaling 0 to 24 mA 0 Disabled
(Resolution 0 to 24000) 1 Enabled
7 Scaling 0 to 20 mA 0 Disabled
(Resolution 0 to 65535) 1 Enabled
8 - 15 Reserved -

Information:
The "AnalogMode" registers provide the option of avoiding the cyclic check of the DAC configuration.
To manage communication reliably, this option should only be used if no HART communication is
taking place on the channel.

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4.4.3.10.4.2 DACSlewrate

Name:
DACSlewrate01 to DACSlewrate02
These registers limit the rate at which the analog signal is modified. This makes it possible to define a sort of upper
limit frequency.
The following formula f(Analog) = f(Output rate) * Permitted change / max. ∆(standardized output value)
applies:
Data type Value
UINT See bit structure

To ensure communication takes place without errors, it's important that the frequency range of the digital HART
signal is not influenced by the analog output. HART communication takes place in the frequency range 950 to
2500 Hz.
Example (default): f(Analog) = 152440 Hz * 4 / (32767 - 0)
Conclusion: f(Analog) = ~20 Hz << 950 Hz = f(HART)
Bit structure:
Bit Name Value Information
0-2 Permitted change per rate 000 1-bit
001 2-bit
010 4 bit (bus controller default)
011 8-bit
100 16-bit
101 32-bit
110 64-bit
111 128-bit
3-7 Reserved -
8 - 11 Output rate 0000 257730 Hz
0001 198410 Hz
0010 152440 Hz (bus controller default)
0011 131580 Hz
0100 115740 Hz
0101 69440 Hz
0110 37590 Hz
0111 25770 Hz
1000 20160 Hz
1001 16030 Hz
1010 10290 Hz
1011 8280 Hz
1100 6900 Hz
1101 5530 Hz
1110 4240 Hz
1111 3300 Hz
12 - 14 Reserved -
15 Slewrate enable 0 Disabled (undefined jump behavior)
(ramp functionality) 1 Enabled (defined transitions)

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4.4.3.10.5 Analog signal - Communication

In order to output the required current signal (default: 4 bis 20 mA), the module must be assigned the default
output value (default: 0 to 32767). In this way, the X20AO2438 can be used as a conventional output module. The
integrated HART modem uses the same physical line. Using signals with a higher frequency allows the module to
communicate with and also retrieve information from the HART slave.

4.4.3.10.5.1 AnalogOutput

Name:
AnalogOutput01 to AnalogOutput02
These registers provide the standardized output values. Depending on the scaling selected (see AnalogMode
register), the value range and the data type can be adapted to the requirements of the application. Once a permitted
value is determined, the module outputs the respective current.

Information:
The value "0" disables the channel status LED.
Data type Value Information
INT 0 to 32767 Bus controller default: 0
Optional: UINT 0 to 65535

4.4.3.10.5.2 AnalogStatus

Name:
AnalogStatus01 to AnalogStatus02
The status register gives the user feedback about whether the respective channel is functioning properly.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Value Information
0-1 Reserved -
2 OpenLineAnalogOutput01, 02 0 Line OK
1 Open line
3 ConversionErrorAnalogOutput01, 02 0 Conversion temperature OK
1 Conversion temperature too high
4-6 Reserved -
7 IoSuppErrorAnalogOutput01, 02 0 Module supply OK
1 Module supply error

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4.4.3.10.6 HART

HART (Highway Addressable Remote Transducer) is a protocol for communicating with intelligent field devices. It
was developed in order to more efficiently use the infrastructure for transferring analog signals. The digital HART
notifications are modulated to the analog signal using Frequency Shift Keying (FSK). HART can thus use the same
physical line as the analog signal without influencing the original function.
HART slaves are able to determine different process data independently and prepare HART concordantly. This
protocol supports polling of the value of a process variable as well as its unit and status. Field devices usually supply
their information after the master requests it. In newer revisions, it is also possible to transfer configuration data.
There are two different types of HART networks. In a point-to-point network, only one slave is connected to a HART
master. Here, the analog signal and the HART signal can be transferred over the same line. Managing several
slaves with HART requires what is known as a multidrop network. Here, each HART slave is assigned and identified
by a unique address. Classic analog signals cannot be clearly traced in bus systems. As a result, the HART protocol
does not support analog information transfers in multidrop networks up to and including HART Revision 5.

Information:
Split range operation with HART AO modules
Beginning with HART revision 6, bus stations that use an analog signal according to the split range
method are written to separately. The HART protocol supports multidrop addressing as well as the use
of analog signals for these applications.
The module was designed based on HART-Revision 5. Only single-channel FSK scheme is available for transmit-
ting the signals.
Since all HART frames are generated and evaluated in the application when using the FlatStream interface, infor-
mation that isn't specified until later revisions can also be read.

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4.4.3.10.6.1 HART - Configuration

HART modules are analog modules equipped with a HART modem. For each channel, a separate HART network
can be managed by the module, which acts as a primary master. Once configured successfully, the HART infor-
mation is stored in the module where it can then be used by the PLC.
The number of HART slaves must be specified in the configuration.
If only one slave is connected to the HART channel, then it is part of a point-to-point network. The module can then
prepare up to four process variables from the connected slave.
Multidrop mode allows up to 15 HART slaves to be connected. The primary process variable from each slave is
then retrieved.

HartNodeCnt

Name:
HartCodeCnt_1 to HartCodeCnt_2
These registers tell the module how many HART slaves are connected to a channel.

Information:
If a slave is not connected to one of the HART channels, the value "0" should be defined in this register.
This shortens the I/O update time and avoids superfluous error messages.
Data type Value Information
USINT 0 HART communication disabled for this channel
1 Point-to-point Standard HART communication (bus controller default)
2 to 15 Multidrop Number of HART slave nodes

HartBurstNode

Name:
HartBurstNode_1 to HartBurstNode_2
In addition to the type of network, the user can also choose from two different types of communication behavior.
Conventional HART communication relies on polling. The module requests the data from the individual HART
slaves and receives the corresponding information from each slave as a response. If a HART node should be
queried in short time intervals, the user can configure burst mode for channels on one node. In this case, the slave
transmits the node's information cyclically without constant prompting from the master.
The "HartBurstNode" registers are therefore used to enter the node numbers (short address) for the chan-
nels whose information should be retrieved using burst mode. Burst mode itself is enabled with the
"HartMode""HartMode" register.
Data type Value Information
USINT 0 to 15 Point-to-point 0 (bus controller default)

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HartMode

Name:
HartMode_1 to HartMode_2
The user can use these registers to configure the communication behavior of each of the HART channels. Gener-
ally, the HART nodes are polled individually. This register can still be used to start or stop burst mode when needed.
In burst mode, a node transmits its information cyclically instead of continuously. As a result, the HART standard
allows the simultaneous usage of both burst mode and polling.

Information:
To retrieve information with burst mode, the "HartBurstNode"HartBurstNode register must be config-
ured correctly.
Data type Value
UINT See bit structure.

Bit structure:
Bit Name Value Information
0 Slave polling mode 0 Polling mode enabled (Bus Controller Default)
1 Polling mode disabled
1 Start slave burst mode 0 No response to burst (bus controller default)
1 Enables burst mode in the "HartBurstNode" nodeHartBurstNode
2 Stop slave burst mode 0 No response to burst (bus controller default)
1 Disables burst mode, if enabled
3-7 Reserved -

4.4.3.10.6.2 HART - Communication

Once the configuration has been completed, the information is retrieved automatically and transferred to the
module's registers. A separate register in the module is implemented for each piece of information. HART modules
are designed to retrieve up to 15 pieces of information per channel. The module reads in the data, stores it in tem-
porary memory and prepares it for retrieval. When the X2X master accesses the module registers, it is irrelevant
whether the HART data originates from a point-to-point network or a multidrop network.
Overview of internal module mapping
Point-to-point network (1 HART slave) Multidrop network (2 to 15 HART slaves)
(Pv)Input_01 Primary piece of information from HART node 1 Primary piece of information from HART node 1
(Pv)Input_02 Secondary piece of information from HART node 1 Primary piece of information from HART node 2
... ... ...
(Pv)Input_04 Quaternary piece of information from HART node 1 Primary piece of information from HART node 4
(Pv)Input_05 Reserved Primary piece of information from HART node 5
... ... ...
(Pv)Input_15 Reserved Primary piece of information from HART node 15

The HART specifications stipulates that information from a HART node be split into various pieces. The value of
a process variable is stored to the respective "PvInput" register and has a size of 4 bytes (REAL) in accordance
with the HART specification. Due to the length limitation of 30 bytes on the X2X link, there are restrictions to
the number of possible cyclic variables. It is recommended to only transfer a maximum of two "PvInput""PvInput"
registers cyclically to the X2X master. All other information should be transferred in a different way. To access
HART information, the user can choose from among the following methods:
• Data points that are configured to be transferred cyclically are read once per bus cycle. This method allows
information to be exchanged between the module and the X2X master in real time. Nevertheless, the length
limitation may prevent all data from being retrieved within one cycle.
• If the AsIOAcc library is used, information is retrieved acyclically only when it is needed, i.e. communication
can be adapted to the application running on the X2X master. In this way, all of the necessary module
registers on the X2X link can be polled despite the length limitation.
This method of information exchange is not real-time capable.
• HART modules are equipped with a FlatStream interface. When using FlatStream communication, the
module acts a bridge between the X2X master and the HART slave, i.e. the X2X master communicates
directly with the HART slave (see section "FlatStream communication""FlatStream communication").
FlatStream communication is also not real-time capable. It allows unrestricted access to the HART slave.
The user must have sufficient knowledge of the HART protocol command set as well as the capabilities
of the HART slave device.

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PvInput

Name:
PvInput_01 to PvInput_15
These registers return the current value of the process variable that has been read.

Information:
These registers are of data type REAL, which means that the available bytes on the X2X link are filled
more quickly when operated cyclically. If information from several slave nodes is needed, it must be
retrieved acyclically or using FlatStream.
Data type Value Information
REAL IEEE745 SPF 32-bit data type with valid value
0x7FA00000 Not a number (NaN) with invalid value

PvUnit

Name:
PvUnit_01 to PvUnit_15
These registers return a HART-specific code that specifies the unit for the measured value. The coding for this is
established in the HART specification.
Data type Value
USINT See description of the HART slave
See HART specification

PvSampleTime

Name:
PvSampleTime01 to PvSampleTime02
PvSampleTime01_01 to PvSampleTime01_15
PvSampleTime02_01 to PvSampleTime02_15
These registers return the timestamp for when the module reads the current channel mapping. The values are
provided as signed 2-byte or 4-byte values.
Data type Values [µs] Information
INT -32768 to 32767 Nettime timestamp of the current input value
DINT -2,147,483,648 Nettime timestamp of the current input value
to 2,147,483,647

This refers to the point in time when the HART master receives the slave's response. This is a way to check whether
new HART information has been read since the last X2X cycle.

Information:
The cycle times of a HART network are relatively long so that it is not possible to reliably determine
when the measured value is retrieved with just this information.

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PvNodeComStatus

Name:
PvNodeComStatus01 to PvNodeComStatus02
PvNodeComStatus01_01 to PvNodeComStatus01_15
PvNodeComStatus02_01 to PvNodeComStatus02_15
These registers return information about whether a value that has been read is valid. According to the HART
specification, this type of status register consists of two parts. The high byte stores the "response code" and the
low byte the "field device status". This makes it possible to check the current status of a read process variable.
These registers can be checked before further processing information in temporary storage. If the current value
is 0x0000, an error was not detected during the HART transfer and the information from the checked node can
be used. If a different value is present, the situation in the HART network should be checked. This can be done
using an extension register, for example.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Quality - Node information 2 to n 0 Digital measured value okay
1 Measured value outside the permitted range
1 Quality - Node information 1 0 Digital measured value okay
1 Measured value outside the permitted range
2 Limit violation 0 Parameter okay
1 Invalid measured value(s) or encoder supply value
3 Static analog signal 0 Normal value change/fluctuation
1 Constant analog value of Node 1 slave
4 Additional status information 0 Not available
(only supported by a few slaves) 1 Available (only using FlatStream command #48)
5 Reboot 0 Normal operation
1 Field device restarts
6 Device ID 0 Unchanged
1 Changed
7 Device error 0 Measured value okay
1 Questionable measured value information
8 - 14 Response code, if relevant x See HART-specific response code
15 Error - Communication 0 Error-free communication (response code irrelevant)
1 Faulty communication (response code relevant)

HART-specific response code (excerpt):

0x82 ... Receive buffer overflow If a HART communication error occurs, the response code is written. Bit 15 is
0x88 ... Incorrect checksum always set.
0x90 ... Faulty protocol structure
0xA0 ... Overrun
0xC0 ... Parity not allowed
0xFF ... Timeout

Retrieving information that has been read

After the node data has been transferred to the module registers, the information can be retrieved from the module.
A separate register in the module is implemented for each piece of information.

PvCountHartRequest

Name:
PvCountHartRequest01 to PvCountHartRequest02
These registers are increased once the module is ready to transmit a message to the corresponding channel.
Data type Value
UDINT 0 to 4,294,967,295

PvCountHartTimeout

Name:
PvCountHartTimeout01 to PvCountHartTimeout02
These registers are increased if the slave exceeds the maximum permitted time before responding to the module's
request.
Data type Value
UDINT 0 to 4,294,967,295

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PvCountHartRxError

Name:
PvCountHartRxError01 to PvCountHartRxError02
These registers are increased if communication errors occur on Layer 1 of the OSI model (e.g. transmission error
as per parity bit).
Data type Value
UDINT 0 to 4,294,967,295

PvCountHartFrameError

Name:
PvCountHartFrameError01 to PvCountHartFrameError02
These registers are increased if communication errors occur on Layer 2 of the OSI model (e.g. faulty telegram
structure).
Data type Value
UDINT 0 to 4,294,967,295

PvNodeFound

Name:
PvNodeFound01 to PvNodeFound02
These registers provide information about which nodes were detected on which channel (slave identified success-
fully).
Data type Value
UINT See bit structure.

Bit structure:
Bit Name Value Information
0 Node 0 (default mode) 0 Not detected as valid
Node 1 (multidrop mode) 1 Detected as valid
1 Node 2 (multidrop mode) 0 Not detected as valid
1 Detected as valid
... ...
13 Node 14 (multidrop mode) 0 Not detected as valid
1 Detected as valid
14 Node 15 (multidrop mode) 0 Not detected as valid
1 Detected as valid
15 Reserved -

PvNodeError
Name:
PvNodeError01 to PvNodeError02
These registers contain the HART communications error bits. These bits are set if the connection to a node was
established successfully but the node at some point no longer responds as it should (e.g. the HART slave exceeds
the configured timeout / number of retries).
Data type Value
UINT See bit structure.

Bit structure:
Bit Name Value Information
0 Node 0 (default mode) 0 Detected as having no errors
Node 1 (multidrop mode) 1 Detected as having errors
1 Node 2 (multidrop mode) 0 Detected as having no errors
1 Detected as having errors
... ...
13 Node 14 (multidrop mode) 0 Detected as having no errors
1 Detected as having errors
14 Node 15 (multidrop mode) 0 Detected as having no errors
1 Detected as having errors
15 Reserved -

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4.4.3.10.6.3 Extended configuration

The additional configuration registers are specified values when the module is started. In most systems, the user
does not need to make any adjustments here. Register values should only be changed if HART network commu-
nication is not taking place satisfactorily.

HartNodeDisable

Name:
HartNodeDisable_1 to HartNodeDisable_2
These registers are intended for things like maintenance. They make it possible to cut off configured HART nodes
to suppress error messages for a certain period of time. During normal operation, the configured nodes must be
switched active to guarantee that the procedure runs smoothly.
Data type Value
UINT See bit structure.

Bit structure:
Bit Name Value Information
0 Node 0 (default mode) 0 Enabled (bus controller default)
Node 1 (multidrop mode) 1 Disabled
1 Node 2 (multidrop mode) 0 Enabled
1 Disabled (bus controller default)
... ...
13 Node 14 (multidrop mode) 0 Enabled
1 Disabled (bus controller default)
14 Node 15 (multidrop mode) 0 Enabled
1 Disabled (bus controller default)
15 Reserved -

HartProtTimeOut

Name:
HartProtTimeOut_1 to HartProtTimeOut_2
These registers specify the time span within which the slave must respond for the response to be valid.
Data type Values [ms] Information
UINT 0 to 65535 Bus controller default: 256 [ms]

HartProtRetry

Name:
HartProtRetry_1 to HartProtRetry_2
These registers determine how many times the master retries a request if it receives an invalid response or no
response at all.
Data type Value Information
UINT 0 to 65535 Bus controller default: 3 attempts

HartPreamble

Name:
HartPreamble_1 to HartPreamble_2
The length of the preamble can be set in these registers. The preamble is used to synchronize the receiver to the
transmitter. The longer the declared preamble, the less chance that a communication error will occur. Nevertheless,
a useful signal is not transmitted during synchronization so the preamble should be kept as short as possible.
Data type Value Information
UINT 5 to 20 Bus controller default: 20

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4.4.3.10.7 FlatStream communication

4.4.3.10.7.1 Introduction

B&R offers an additional communication method for some modules. "FlatStream" was designed for X2X and
POWERLINK networks and allows data transmission to be adapted to individual demands. Although this method
is not 100% real-time capable, it still allows data transmission to be handled more efficiently than with standard
cyclic polling.
Field device
X2X language

Cyclic call
via I/O mapping

B&R CPU
Cyclic call B&R module Cyclic
PLC or B&R field device
of cached values cached value communication
Bus controller

Acyclic call
via
library functions
B&R CPU
Acyclic call B&R module Cyclic
PLC or B&R field device
of cached values cached value communication
Bus controller

FlatStream

B&R CPU X2X-compatible B&R module

PLC or Device command B&R field device
device command as a bridge
Bus controller

Figure 170: Three types of communication

FlatStream extends cyclic and acyclic data queries. With FlatStream communication, the module acts as a bridge.
It is used to pass CPU queries directly on to the field device.

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4.4.3.10.7.2 Message, segment, sequence, MTU

The physical properties of the bus system limit the amount of data that can be transmitted during one bus cycle.
With FlatStream communication, all messages are viewed as part of a continuous data stream. Long data streams
must be broken down into several fragments that are sent one after the other. To understand how the receiver puts
these fragments back together to get the original information, it is important to understand the difference between
a message, a segment, a sequence and an MTU.
Message
A message refers to information exchanged between two partner stations. The length of a message is not restricted
by the FlatStream communication method. Nevertheless, module-specific limitations must be considered.
Segment (logical division of a message)
A segment has a finite size and can be understood as a section of a message. The number of segments per
message is arbitrary. So that the recipient can correctly reassemble the transmitted segments, each segment
is preceded by a byte with additional information. This control byte contains information such as the length of a
segment and whether the approaching segment completes the message. This makes it possible for the receiving
station to interpret the incoming data stream correctly.
Sequence (how a segment needs to be arranged physically)
The maximum size of a sequence corresponds to the number of enabled Rx or Tx bytes (later: "MTU"). The
transmitting station splits the transmit array into valid sequences. These sequences are then written successively
to the MTU and transmitted to the receiving station where they are put back together again. The receiver stores
the incoming sequences in a receive array, obtaining an image of the data stream in the process.
With FlatStream communication, the number of sequences sent are counted. Successfully transmitted sequences
must be acknowledged by the receiving station to ensure the integrity of the transmission.
MTU (Maximum Transmission Unit) - Physical transport
MTU refers to the enabled USINT registers used with FlatStream. These registers can accept at least one se-
quence and pass it on to the receiving station. A separate MTU is defined for each direction of communication.
The OutputMTU defines the number of FlatStream Tx bytes, and the InputMTU specifies the number of FlatStream
Rx bytes. The MTUs are transported cyclically via the X2X Link, increasing the load with each additional enabled
USINT register.
Features
FlatStream messages are not transmitted cyclically or in 100% real time. Many bus cycles may be needed to trans-
mit a particular message. Although the Rx and Tx registers are exchanged between the transmitter and the receiv-
er cyclically, they are only processed further if explicitly accepted by the "InputSequence" or "OutputSequence"
register.
Behavior in the event of an error (brief summary)
The protocol for X2X and POWERLINK networks specifies that the last valid values should be retained when
disturbances occur. With conventional communication (cyclic/acyclic data queries), this type of error can generally
be ignored.
In order for communication to also take place without errors using FlatStream, all of the sequences issued by the
receiver must be acknowledged. If Forward functionality is not used, then subsequent communication is delayed
for the length of the disturbance.
If Forward functionality is being used, the receiving station receives a transmission counter that is incremented
twice. The receiver stops, i.e. it no longer returns any acknowledgments. The transmitting station uses the Se-
quenceAck to determine that the transmission was faulty and that all affected sequences will have to be repeated.

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4.4.3.10.7.3 The FlatStream principle

Requirements
Before FlatStream can be used, the respective communication direction must be synchronized, i.e. both commu-
nication partners cyclically query the sequence counter on the opposite station. This checks to see if there is new
data that should be accepted.
Communication
If a communication partner wants to transmit a message to its opposite station, it should first create a transmit
array that corresponds to FlatStream conventions. This allows the FlatStream data to be organized very efficiently
without having to block other important resources.
PLC / Bus controller Module
Module-internal Module-internal
Transmit array OutputMTU receive buffer receive array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 TxBytes Cyc. *RxBytes _data_01

_data_02 _data_02
When OutputMTU The transmit buffer If the OutputSequence
_data_03 released: of the module is counter is increased: _data_03
adjusted cyclically to
_data_04 CPU fills OutputMTU via X2X Module adds the transmit buffer _data_04
OutputMTU to the internal array
_data_05 with the next
_data_05
... sequence of the If successful: ...
transmit array InputSequenceAck is
_data_xx adjusted to the _data_xx
transmit counter

Module-internal Module-internal
Receive array InputMTU transmit buffer transmit array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 RxBytes Cyc. *TxBytes _data_01

_data_02 _data_02
If the InputMTU is If permitted:
_data_03 InputSequence adjusted cyclically Module fills the internal _data_03
counter is increased: to the receive transmit buffer with the
_data_04 buffer via X2X next sequence of the _data_04
_data_05 InputMTU must be transmit array _data_05
added to the end
... of the receive array Module increases the ...
(increase InputSequenceAck InputSequence counter
_data_xx to end properly) _data_xx

Figure 171: FlatStream communication

Procedure
The first thing that happens is that the message is broken into valid segments of up to 63 bytes, and the corre-
sponding control bytes are created. The data is formed into a data stream made up of one control bytes per asso-
ciated segment. This data stream can be written to the transmit array. The maximum size of each array element
matches that of the enabled MTU so that one element corresponds to one sequence.
When the array has been completely created, the transmitter checks whether the MTU is allowed to be refilled.
Then it copies the first element of the array or the first sequence to the Tx byte registers. The MTU is transported to
the receiver station via X2X Link and stored in the corresponding Rx byte registers. To signal that the data should
be accepted by the receiver, the transmitter increases its SequenceCounter.
If the communication direction is synchronized, the opposite station detects the incremented SequenceCounter.
The current sequence is appended to the receive array and acknowledged by SequenceAck. This acknowledgment
signals to the transmitter that the MTU can now be refilled.
If the transmission is successful, the data in the receive array will correspond 100% to the data in the transmit array.
During the transmission, the receiving station must detect and evaluate the incoming control bytes. A separate
receive array should be created for each message. This allows the receiver to immediately begin further processing
of messages once they have been completely transmitted.

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4.4.3.10.7.4 Registers for FlatStream mode

Five registers are available for configuring FlatStream. The default configuration can be used to transmit small
amounts of data relatively easily.

Information:
The CPU communicates directly with the field device via the "OutputSequence" and "InputSequence"
as well as the enabled Tx and Rx bytes. For this reason, the user needs to have sufficient knowledge
of the communication protocol being used on the field device.

FlatStream configuration

To use FlatStream, the program sequence must first be expanded. The cycle time of the FlatStream routines must
be set to a multiple of the bus cycle. Other program routines should be implemented in Cyclic #1 to ensure data
consistency.
At the absolute minimum, the "InputMTU" and "OutputMTU" registers need to be configured. All other registers are
filled in with default values at the beginning and can be used immediately. These registers are used for additional
options, e.g. to transmit data in a more compact way or to increase the efficiency of the general procedure.
The Forward registers extend the functionality of the FlatStream protocol. This functionality is useful for substan-
tially increasing the FlatStream data rate, but it also requires quite a bit of extra work when creating the program
sequence.

Number of enabled Tx and Rx bytes

Name:
OutputMTU
InputMTU
These registers define the number of enabled Tx or Rx bytes, i.e. the maximum size of a sequence. The user must
consider that the more bytes made available also means a higher load on the bus system.

Information:
In the rest of this documentation, the names "OutputMTU" and "InputMTU" do not refer to the registers
explained here. Instead, they are used as synonyms for the currently enabled Tx or Rx bytes.
Data type Value
USINT See the module-specific register overview (theoretically: 3 to 27)

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FlatStream operation

When using FlatStream, the communication direction is enormously important. For sending data to a module ("out-
put" direction), the Tx bytes are used. For receiving data from a module ("input" direction), the Rx bytes are used.
The "OutputSequence" and "InputSequence" registers are used to control and ensure that communication is taking
place properly, i.e. the transmitter issues the directive that the data should be accepted and the receiver acknowl-
edges that a sequence has been transmitted successfully.

Transporting the payload data and the control bytes

Name:
TxByte1 to TxByteN
RxByte1 to RxByteN
(The value the number N is different depending on the bus controller model used.)
The Tx and Rx bytes are cyclic registers used to transport the payload data and the necessary control bytes. The
number of active Tx and Rx bytes is taken from the configuration of the "OutputMTU" and "InputMTU" registers,
respectively.
In the user program, only the Tx and Rx bytes from the CPU can be used. The corresponding counterparts are
located in the module and are not accessible to the user. For this reason, names were chosen from the CPU point
of view.
• "T" - "Transmit" → CPU transmits data to the module.
• "R" - "Receive" → CPU receives data from the module.
Data type Value
USINT 0 to 65535

Control bytes

In addition to the payload data, the Tx and Rx bytes also transmit the necessary control bytes. These control bytes
contain additional information about the data stream so that the receiver can reconstruct the original message from
the transmitted segments.
Bit structure of a control byte
Bit Name Value Information
0-5 SegmentLength 0 - 63 Size of the subsequent segment in bytes (default: Max. MTU size - 1)
6 nextCBPos 0 Next control byte at the beginning of the next MTU
1 Next control byte directly after the end of the current segment
7 MessageEndBit 0 Message continues after the subsequent segment
1 Message ended by the subsequent segment

SegmentLength
The segment length lets the receiver know the length of the coming segment. If the configured segment length
is insufficient for a message, then the information must be distributed over several segments. In these cases, the
actual end of the message is detected using bit 7 of the control byte.

Information:
The control byte is not included in the calculation to determine the segment length. The segment length
is only derived from the bytes of payload data.
nextCBPos
This bit indicates the position where the next control byte is to be expected. This information is especially important
when using the "MultiSegmentMTU" option.
When using FlatStream communication with multi-segment MTUs, the next control byte is no longer expected in
the first Rx byte of the subsequent MTU, but directly after the current segment.

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MessageEndBit
The "MessageEndBit" is set if the subsequent segment completes a message. The message has then been com-
pletely transmitted and is ready for further processing.

Information:
In the output direction, this bit must also be set if one individual segment is enough to hold the entire
message. The module will only process a message internally if this identifier is detected.
The size of the message being transmitted can be calculated by adding all of the message's segment
lengths together.
FlatStream formula for calculating message length:
Message [bytes] = SegmentLengths (all CBs without ME) + SegmentLength (of the first CB with CB Control byte
ME) ME MessageEndBit

Communication status of the CPU

Name:
OutputSequence
The "OutputSequence" register contains information about the communication status of the CPU. It is written by
the CPU and read by the module.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-2 OutputSequenceCounter 0-7 Counter for the sequences issued in the output direction
3 OutputSyncBit 0 Output direction disabled
1 Output direction enabled
4-6 InputSequenceAck 0-7 Mirrors the InputSequenceCounter value
7 InputSyncAck 0 Input direction not ready (disabled)
1 Input direction ready (enabled)

OutputSequenceCounter
The OutputSequenceCounter is a continuous counter of sequences that have been issued by the CPU. The CPU
uses the OutputSequenceCounter to direct the module to accept a sequence (the output direction must be syn-
chronized when this happens).
OutputSyncBit
The CPU uses the OutputSyncBit to attempt to synchronize the output channel.
InputSequenceAck
InputSequenceAck is used for acknowledgment. The value of the InputSequenceCounter is mirrored if the CPU
has received a sequence successfully.
InputSyncAck
The InputSyncAck bit acknowledges the synchronization of the input channel for the module. This indicates that
the CPU is ready to receive data.

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Communication status of the module

Name:
InputSequence
The "InputSequence" register contains information about the communication status of the module. It is written by
the module and should only be read by the CPU.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-2 InputSequenceCounter 0-7 Counter for sequences issued in the input direction
3 InputSyncBit 0 Not ready (disabled)
1 Ready (enabled)
4-6 OutputSequenceAck 0-7 Mirrors the InputSequenceCounter value
7 OutputSyncAck 0 Not ready (disabled)
1 Ready (enabled)

InputSequenceCounter
The InputSequenceCounter is a continuous counter of sequences that have been issued by the module. The
module uses the InputSequenceCounter to direct the CPU to accept a sequence (the input direction must be
synchronized when this happens).
InputSyncBit
The module uses the InputSyncBit to attempt to synchronize the input channel.
OutputSequenceAck
OutputSequenceAck is used for acknowledgment. The value of the OutputSequenceCounter is mirrored if the
module has received a sequence successfully.
OutputSyncAck
The OutputSyncAck bit acknowledges the synchronization of the output channel for the CPU. This indicates that
the module is ready to receive data.

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Relationship between OutputSequence and InputSequence

Outputsequenz Input sequence

CPU communication status Module communication status

0-2 OutputSequenceCounter 0-2 InputSequenceCounter

3 OutputSyncBit Intersecting 3 InputSyncBit

4-6 InputSequenceAck Handshakes 4-6 OutputSequenceAck

7 InputSyncAck 7 OutputSyncAck

Figure 172: Relationship between OutputSequence and InputSequence

The "OutputSequence" and "InputSequence" registers are logically composed of two half-bytes. The low part sig-
nals to the opposite station whether a channel should be opened or if data should be accepted. The high part is
to acknowledge that the requested action was carried out.
SyncBit and SyncAck
If SyncBit and SyncAck are set in one communication direction, then the channel is considered "synchronized", i.e.
it is possible to send messages in this direction. The status bit of the opposite station must be checked cyclically.
If SyncAck has been reset, then the SyncBit must be adjusted on that station. Before new data can be transmitted,
the channel needs to be resynchronized.
SequenceCounter and SequenceAck
The communication partners cyclically check whether the low nibble on the opposite station changes. When one
of the communication partners finishes writing a new sequence to the MTU, it increments its SequenceCounter.
The current sequence is then transmitted to the receiver, which acknowledges its receipt with SequenceAck. In
this way, a "handshake" is initiated.

Information:
If communication is interrupted, segments from the unfinished message are discarded. All messages
that were transmitted completely are processed.

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Synchronization

During synchronization, a communication channel is opened. It is important to make sure that a module is present
and that the current value of the SequenceCounter is stored on the station receiving the message.
FlatStream can handle full-duplex communication. This means that both channels / communication directions can
be handled separately. They have to be synchronized independently so that simplex communication can theoret-
ically be carried out as well.

Synchronization in the output direction (CPU as the transmitter)

The corresponding synchronization bits (OutputSyncBit and OutputSyncAck) are reset. Because of this, FlatStream
cannot be used at this point in time to send messages from the CPU to the module.
Algorithm
1) The CPU must write 000 to the OutputSequenceCounter and reset the OutputSyncBit.
The CPU must cyclically query the high nibble of the "InputSequence" register (checks for 000 in OutputSequenceAck and 0 in OutputSyncAck).
The module does not accept the current contents of the InputMTU since the channel is not yet synchronized.
The module matches OutputSequenceAck and OutputSyncAck to the values of the OutputSequenceCounter and OutputSyncBit.
2) If the CPU registers the expected values in OutputSequenceAck and OutputSyncAck, it is allowed to increment the OutputSequenceCounter.
The CPU continues cyclically querying the high nibble of the "OutputSequence" register (checks for 001 in OutputSequenceAck and 0 in InputSyncAck).
The module does not accept the current contents of the InputMTU since the channel is not yet synchronized.
The module matches OutputSequenceAck and OutputSyncAck to the values of the OutputSequenceCounter and OutputSyncBit.
3) When the CPU registers the expected values in OutputSequenceAck and OutputSyncAck, it is allowed to increment the OutputSequenceCounter.
The CPU continues cyclically querying the high nibble of the "OutputSequence" register (checks for 001 in OutputSequenceAck and 1 in InputSyncAck).

Note:
Theoretically, data can be transmitted from this point forward. However, it is still recommended to wait until the output direction is completely synchronized be-
fore transmitting data.
The module sets OutputSyncAck.
The output direction is synchronized, and the CPU can transmit data to the module.

Synchronization in the input direction (CPU as the receiver)

The corresponding synchronization bits (InputSyncBit and InputSyncAck) are reset. Because of this, FlatStream
cannot be used at this point in time to send messages from the module to the CPU.
Algorithm
The module writes 000 to the InputSequenceCounter and resets the InputSyncBit.
The module monitors the high nibble of the "OutputSequence" registers and expects 000 in InputSequenceAck and 0 in InputSyncAck.
1) The CPU is not allowed to accept the current contents of the InputMTU since the channel is not yet synchronized.
The CPU has to match InputSequenceAck and InputSyncAck to the values of InputSequenceCounter and InputSyncBit.
If the module registers the expected values in InputSequenceAck and InputSyncAck, it increments the InputSequenceCounter.
The module monitors the high nibble of the "OutputSequence" registers and expects 001 in InputSequenceAck and 0 in InputSyncAck.
2) The CPU is not allowed to accept the current contents of the InputMTU since the channel is not yet synchronized.
The CPU has to match InputSequenceAck and InputSyncAck to the values of InputSequenceCounter and InputSyncBit.
If the module registers the expected values in InputSequenceAck and InputSyncAck, it sets the InputSyncBit.
The module monitors the high nibble of the "OutputSequence" register and expects 1 in InputSyncAck.
3) The CPU is allowed to set InputSyncAck.

Note:
Theoretically, data can already be transmitted in this cycle.
If the InputSyncBit is set and InputSequenceCounter has been increased by 1, the values in the enabled Rx bytes have to be accepted and acknowledged (see
also "Communication in the input direction").
The input direction is synchronized, and the module can transmit data to the CPU.

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Transmitting and receiving

If a channel is synchronized, then the opposite station is ready to receive messages from the transmitter. Before
the transmitter can send data, it needs to first create a transmit array in order to meet FlatStream requirements.
The transmitting station must also generate a control byte for each segment created. This control byte contains
information about how the subsequent part of the data being transmitted should be processed. The position of the
next control byte in the data stream can vary. For this reason, it must be clearly defined at all times when a new
control byte is being transmitted. The first control byte is always in the first byte of the first sequence. All subsequent
positions are determined recursively.
FlatStream formula for calculating the position of the next control byte:
Position (of the next control byte) = Current position + 1 + Segment length
Example
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The rest of the configuration corresponds to the default settings.

Message 1: Transmit/Receive array

With 7 USINT elements according to

the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Default
Message 2:

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

C2 A7 - - - - - Sequence for bus cycle 2

Message 3:
C3 B1 B2 - - - - Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C4 D1 D2 D3 D4 D5 D6 Sequence for bus cycle 4

No more data to transmit C5 D7 D8 D9 - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 173: Transmit/Receive array (default)

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First, the messages must be split into segments. In the default configuration, it is important to ensure that each
sequence can hold an entire segment, including the associated control byte. The sequence is limited to the size of
the enable MTU. In other words, a segment must be at least 1 byte smaller than the MTU.
MTU = 7 bytes → Max. segment length = 6 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 6 bytes of data

➯ Second segment = Control byte + 1 data byte
• Message 2 (2 bytes)

➯ First segment = Control byte + 2 bytes of data

• Message 3 (9 bytes)

➯ First segment = Control byte + 6 bytes of data

➯ Second segment = Control byte + 3 data bytes
• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C0 (control byte 0) C1 (control byte 1) C2 (control byte 2)
- SegmentLength (0) = 0 - SegmentLength (6) = 6 - SegmentLength (1) = 1
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (0) = 0 - MessageEndBit (0) = 0 - MessageEndBit (1) = 128
Control byte Σ 0 Control byte Σ 6 Control byte Σ 129

Table 85: FlatStream determination of the control bytes for the default configuration example (part 1)
C3 (control byte 3) C4 (control byte 4) C5 (control byte 5)
- SegmentLength (2) = 2 - SegmentLength (6) = 6 - SegmentLength (3) = 3
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (1) = 128 - MessageEndBit (0) = 0 - MessageEndBit (1) = 128
Control byte Σ 130 Control byte Σ 6 Control byte Σ 131

Table 86: FlatStream determination of the control bytes for the default configuration example (part 2)

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Transmitting data to a module (output)

When transmitting data, the transmit array must be generated in the application program. Sequences are then
transmitted one by one using FlatStream and received by the module.

Information:
Although all B&R modules with FlatStream communication always support the most compact trans-
missions in the output direction, it is recommended to use the same design for the transfer arrays in
both communication directions.

PLC / Bus controller Module

Module-internal Module-internal
Transmit array OutputMTU receive buffer receive array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 TxBytes Cyc. *RxBytes _data_01

_data_02 _data_02
When OutputMTU The transmit buffer If the OutputSequence
_data_03 released: of the module is counter is increased: _data_03
adjusted cyclically to
_data_04 CPU fills OutputMTU via X2X Module adds the transmit buffer _data_04
OutputMTU with to the internal array
_data_05 the next sequence
_data_05
... of the transmit array If successful: ...
InputSequenceAck is
_data_xx adjusted to the _data_xx
transmit counter

Figure 174: FlatStream communication (output)

The length of the message is initially smaller than the OutputMTU. In this case, one sequence would be sufficient
to transmit the entire message and the necessary control byte.
Algorithm
Cyclic status query:
- The Module monitors the OutputSequenceCounter.
0) Cyclic checks:
- The CPU must check OutputSyncAck.
→ If OutputSyncAck = 0: Reset the OutputSyncBit and resynchronize the channel.
- The CPU must check whether OutputMTU is enabled.
→ If OutputSequenceCounter > InputSequenceAck: MTU is not enabled because the last sequence has not yet been acknowledged.
1) Preparation (create transmit array):
- The CPU must split up the message into valid segments and create the necessary control bytes.
- The CPU must add the segments and control bytes to the transmit array.
2) Transmit:
- The CPU transfers the current element of the transmit array to the OutputMTU.
→ The OutputMTU is transferred cyclically to the module's transmit buffer but not processed further.
- The CPU must increase the OutputSequenceCounter.
Response:
- The module accepts the bytes from the internal receive buffer and adds them to the internal receive array.
- The module sends acknowledgment and writes the value of the OutputSequenceCounter to OutputSequenceAck.
3) Completion:
- The CPU must monitor the OutputSequenceAck.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via OutputSequenceAck. In order to detect potential trans-
mission errors in the last sequence as well, it is important to make sure that the length of the Completion phase is run through long enough.

Note:
To monitor communication times exactly, the task cycles that have passed since the last increase of the OutputSequenceCounter should be counted. In this
way, the number of previous bus cycles necessary for the transmission can be measured. If the monitoring counter exceeds a predefined threshold, then the
sequence can be considered lost.
(The relationship of bus to task cycle can be influenced by the user so that the threshold value needs to be determined individually.)
- Subsequent sequences can only be transmitted in the next bus cycle after the completion check has been carried out successfully.

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Message larger than the OutputMTU

The transmit array, which needs to be created in the program sequence, consists of several elements. The user
has to arrange the control and data bytes correctly and transfer the array elements one after the other. The transfer
algorithm remains the same and is repeated starting at the point Cyclic checks.
General flow chart

Start

► diff = (OutputSequenceCounter -
OutputSequenceAck) AND 7
► limit = (OutputSequenceCounter -
LastValidAck) AND 7

(diff ≤ limit)
No OutputSequenceAck = No LastValidAck = Yes
AND (OutputSyncAck = 1)
AND (OutputSyncBit = 1) ? OutputSequenceCounter ? OutputSequenceCounter ?

Yes Yes No

No LastValidAck =
diff = 0 ?
OutputSequenceAck

Yes

LastValidAck = No
OutputSequenceAck = 0 ?
OutputSequenceAck

Yes

No OutputSequenceCounter = 0
More sequences to be sent ? OutputSequenceCounter = 1 OutputSyncBit = 1
LastValidAck = 0

Yes

copy next sequence to MTU

increase OutputSequenceCounter

Sequence handling Synchronisation

Figure 175: Flow chart for the output direction

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Receiving data from a module (input)

When receiving data, the transmit array is generated by the module, transferred via FlatStream and must then
be reproduced in the receive array. The structure of the incoming data stream can be configured with the mode
register. The algorithm for receiving the data does not change in this regard.
PLC / Bus controller Module
Module-internal Module-internal
Receive array InputMTU transmit buffer transmit array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 RxBytes Cyc. *TxBytes _data_01

_data_02 _data_02
If the InputMTU is If permitted:
_data_03 InputSequence adjusted cyclically Module fills the internal _data_03
counter is increased: to the receive transmit buffer with the
_data_04 buffer via X2X next sequence of the _data_04
InputMTU must be transmit array
_data_05 added to the end
_data_05
... of the receive array Module increases the ...
(increase InputSequenceAck InputSequence counter
_data_xx to end properly) _data_xx

Figure 176: FlatStream communication (input)

Algorithms
0) Cyclic status query:
- The CPU must monitor the InputSequenceCounter.
Cyclic checks:
- The module checks InputSyncAck.
- The module checks InputSequenceAck.
Preparation:
- The module forms the segments and control bytes and creates the transmit array.
Action:
- The module transfers the current element of the internal transmit array to the internal transmit buffer.
- The module increases the InputSequenceCounter.
1) Receiving (as soon as InputSequenceCounter is increased):
- The CPU must accept data from the InputMTU and append it to the end of the receive array.
- The CPU must match InputSequenceAck to the InputSequenceCounter of the sequence currently being processed.
Completion:
- The module monitors InputSequenceAck.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via InputSequenceAck .
- Subsequent sequences are only transmitted in the next bus cycle after the completion check has been carried out successfully.

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General flow chart

Start

► InputSequenceAck = InputSequenceCounter

Synchronisation
No
InputSyncBit = 1 ? ► RemainingSegmentSize = 0
► SegmentFlags = 0
Yes

No No
InputSyncAck = 1 ? InputSequenceAck > 0 ?

Yes Yes

MTU_Offset = 0 InputSyncAck = 1

(InputSequenceCounter – No
InputSequenceAck)
AND 0x07 = 1 ?

Yes
► RemainingSegmentSize =
Yes MTU_Data[MTU_Offset] AND 0b0011 1111
RemainingSegmentSize = 0 ? ► SegmentFlags =
MTU_Data[MTU_Offset] AND 0b1100 0000
No ► MTU_Offset = MTU_Offset + 1

Yes RemainingSegmentSize > No

(InputMTU_Size – MTU_Offset) ?

Segment data handling

► DataSize = InputMTU_Size – MTU_Offset ► DataSize = RemainingSegmentSize

► copy segment data e.g. memcpy(xxx, ADR(MTU_Data[MTU_Offset]), DataSize)

► MTU_Offset = MTU_Offset + DataSize
► RemainingSegmentSize = RemainingSegmentSize - DataSize

RemainingSegmentSize = 0 AND Yes

► Mark Frame as complete
(SegmentFlags AND 0x80) = 0 ?

No

RemainingSegmentSize = 0 AND Yes

(SegmentFlags AND 0x40) = 0 ?

No

Yes
► InputSequenceAck =
InputMTU_Size = MTU_Offset ?
InputSequenceCounter

No

Figure 177: Flow chart for the input direction

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Details

It is recommended to store transmitted messages in separate receive arrays.

After a set MessageEndBit is transmitted, the subsequent segment should be added to the receive array. The
message is then complete and can be passed on internally for further processing. A new/separate array should
be created for the next message.

Information:
When transmitting with MultiSegmentMTUs, it is possible for several small messages to be part of one
sequence. In the program, it's important to make sure that a sufficient number of receive arrays can
be managed. The entire sequence must be accepted before it is possible to change the Acknowledge
register.
If a SequenceCounter is incremented by more than one value, then an error has occurred.
Note: This situation is very unlikely when operating without "Forward" functionality.
In this case, the receiver stops. All additional incoming sequences are ignored until the transmission with the correct
SequenceCounter is retried. This response prevents the transmitter from receiving any more acknowledgments for
transmitted sequences. The transmitter can identify the last successfully transmitted sequence from the opposite
station's SequenceAck and continue the transmission from this point.
Acknowledgments must be checked for validity.
If the receiver has successfully accepted a sequence, it must be acknowledged. The receiver takes on the Se-
quenceCounter value sent along with the transmission and matches the SequenceAck to it. The transmitter reads
the SequenceAck and registers the successful transmission. If the transmitter acknowledges a sequence that has
not yet been dispatched, then the transmission needs to be interrupted and the channel resynchronized. The syn-
chronization bits are reset and the current/incomplete message is discarded. It needs to be sent again once the
channel has been resynchronized.

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FlatStream mode

Name:
FlatstreamMode
In the input direction, the transmit array is generated automatically. This register offers two options to the user
that allow an incoming data stream to have a more compact arrangement. Once enabled, the program code for
evaluation must be adapted accordingly.

Information:
All B&R modules that offer FlatStream mode support the options "Large segments" and "MultiSeg-
mentMTUs" in the output direction. Compact transmission only needs to be explicitly allowed in the
input direction.
Bit structure:
Bit Name Value Information
0 MultiSegmentMTU 0 Not allowed (default)
1 Allowed
1 Large segments 0 Not allowed (default)
1 Allowed
2-7 Reserved

Default
By default, both options relating to compact transmission in the input direction are disabled.
1. The module only forms segments that are at least one byte smaller than the enabled MTU. Each sequence
begins with a control byte so that the data stream is clearly structured and relatively easy to evaluate.
2. Since a FlatStream message can be of any length, the last segment of the message frequently doesn't fill up
all of the MTU's space. By default, the remaining bytes during this type of transfer cycle are not used.

Bus cycle 1 Bus cycle 2 Bus cycle 3

C C C
- - -
ME0 ME1 ME1

Segment 1 Segment 2 Segment 3

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 178: Message arrangement in the MTU (default)

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MultiSegmentMTUs allowed
With this option, the InputMTU is completely filled (if enough data is pending). The previously unfilled Rx bytes
transmit the next control bytes and their segments. This allows the enabled Rx bytes to be used more efficiently.
Bus cycle 1 Bus cycle 2 Bus cycle 3

C C C C
- -
ME0 ME1 ME0 ME1

Segment 1 Segment 2 3 Segment 4

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 179: Arrangement of messages in the MTU (MultiSegmentMTUs)

Large segments allowed
When transmitting very long messages or when enabling only very few Rx bytes, then a great many segments must
be created by default. The bus system is more stressed than necessary since an additional control byte needs to
be created and transmitted for each segment. With the "Large segments" option, the segment length is limited to
63 bytes independently of the InputMTU. One segment can stretch across several sequences, i.e. it is possible for
"pure" sequences to occur without a control byte.

Information:
It is still possible to split up a message into several segments, however. If this option is used and
messages with more than 63 bytes occur, for example, then messages can still be split up among
several segments.

Bus cycle 1 Bus cycle 2 Bus cycle 3

C C
- - - -
ME1 ME1

Segment 1 Segment 2 Segment 3

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 180: Arrangement of messages in the MTU (large segments)

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Using both options

It is also possible to use both options at the same time.
Bus cycle 1 Bus cycle 2 Bus cycle 3

C C
- - - -
ME1 ME1

Segment 1 Segment 2 Segment 3

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 181: Arrangement of messages in the MTU (large segments and MultiSegmentMTUs)

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Adjusting the FlatStream

If the way messages are structured is changed, then the way data in the transmit/receive array is arranged is also
different. The following changes apply to the example given earlier.
MultiSegmentMTU
If MultiSegmentMTUs are allowed, then "open positions" in an MTU can be used. These "open positions" occur if
the last segment in a message does not fully use the entire MTU. MultiSegmentMTUs allow these bits to be used to
transmit the subsequent control bytes and segments. In the program sequence, the "nextCBPos" bit in the control
byte is set so that the receiver can correctly identify the next control byte.
Example
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The configuration allows transmission of MultiSegmentMTUs.
Message 1: Transmit/Receive array

With 7 USINT elements according to

the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Message 2: MultiSegmentMTU

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

C2 A7 C3 B1 B2 C4 D1 Sequence for bus cycle 2

Message 3:
C5 D2 D3 D4 D5 D6 D7 Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C6 D8 D9 C0 - - - Sequence for bus cycle 4

No more data to transmit C0 - - - - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 182: Transmit/receive array (MultiSegmentMTUs)

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First, the messages must be split into segments. As in the default configuration, it is important for each sequence
to begin with a control byte. The free bits in the MTU at the end of a message are filled with data from the following
message, however. With this option, the "nextCBPos" bit is always set if payload data is sent after the control byte.
MTU = 7 bytes → Max. segment length = 6 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 6 bytes of data (MTU full)

➯ Second segment = Control byte + 1 byte of data (MTU still has 5 open bytes)
• Message 2 (2 bytes)

➯ First segment = Control byte + 2 bytes of data (MTU still has 2 open bytes)
• Message 3 (9 bytes)

➯ First segment = Control byte + 1 byte of data (MTU full)

➯ Second segment = Control byte + 6 bytes of data (MTU full)
➯ Third segment = Control byte + 2 bytes of data (MTU still has 4 open bytes)
• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C1 (control byte 1) C2 (control byte 2) C3 (control byte 3)
- SegmentLength (6) = 6 - SegmentLength (1) = 1 - SegmentLength (2) = 2
- nextCBPos (1) = 64 - nextCBPos (1) = 64 - nextCBPos (1) = 64
- MessageEndBit (0) = 0 - MessageEndBit (1) = 128 - MessageEndBit (1) = 128
Control byte Σ 70 Control byte Σ 193 Control byte Σ 194

Table 87: FlatStream determination of the control bytes for the MultiSegmentMTU example (part 1)

Warning!
The second sequence must have been completely processed before it can be acknowledged with Se-
quenceAck. In this example, there are three different segments within the second sequence, i.e. the
program must include enough receive arrays to handle this situation.
C4 (control byte 4) C5 (control byte 5) C6 (control byte 6)
- SegmentLength (1) = 1 - SegmentLength (6) = 6 - SegmentLength (2) = 2
- nextCBPos (6) = 6 - nextCBPos (1) = 64 - nextCBPos (1) = 64
- MessageEndBit (0) = 0 - MessageEndBit (1) = 0 - MessageEndBit (1) = 128
Control byte Σ 7 Control byte Σ 70 Control byte Σ 194

Table 88: FlatStream determination of the control bytes for the MultiSegmentMTU example (part 2)

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Large segments
Segments are limited to a maximum of 63 bytes. This means they can be larger than the active MTU. These large
segments are divided among several sequences when transmitted. It is possible for sequences to be completely
filled with payload data and not have a control byte.

Information:
It is still possible to subdivide a message into several segments so that the size of a data packet does
not also have to be limited to 63 bytes.
Example
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The configuration allows the transmission of large segments.

Message 1: Transmit/Receive array

With 7 USINT elements according to

the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Message 2: Large segments

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

A7 - - - - - - Sequence for bus cycle 2

Message 3:
C2 B1 B2 - - - - Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C3 D1 D2 D3 D4 D5 D6 Sequence for bus cycle 4

No more data to transmit D7 D8 D9 - - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 183: Transmit/receive array (large segments)

First, the messages must be split into segments. The ability to form large segments means that messages are split
up less frequently, which results in fewer control bytes generated.
Large segments allowed → Max. segment length = 63 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 7 bytes of data

• Message 2 (2 bytes)

➯ First segment = Control byte + 2 bytes of data

• Message 3 (9 bytes)

➯ First segment = Control byte + 9 bytes of data

• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C1 (control byte 1) C2 (control byte 2) C3 (control byte 3)
- SegmentLength (7) = 7 - SegmentLength (2) = 2 - SegmentLength (9) = 9
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (1) = 128 - MessageEndBit (1) = 128 - MessageEndBit (1) = 128
Control byte Σ 135 Control byte Σ 130 Control byte Σ 137

Table 89: FlatStream determination of the control bytes for the large segment example

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Large segments and MultiSegmentMTU

Example
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The configuration allows transmission of large segments as well as MultiSegmentMTUs.
Message 1: Transmit/Receive array
With 7 USINT elements according to
the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Message 2: Both options

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

A7 C2 B1 B2 C3 D1 D2 Sequence for bus cycle 2

Message 3:
D3 D4 D5 D6 D7 D8 D9 Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C0 - - - - - - Sequence for bus cycle 4

No more data to transmit C0 - - - - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 184: Transmit/receive array (large segments and MultiSegmentMTUs)

First, the messages must be split into segments. If the last segment of a message does not completely fill the
MTU, it can be used for other data in the data stream. The "nextCBPos" bit must always be set if the control byte
belongs to a segment with payload data.
The ability to form large segments means that messages are split up less frequently, which results in fewer control
bytes generated. Control bytes are generated in the same way as with the "Large segments" option.
Large segments allowed → Max. segment length = 63 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 7 bytes of data

• Message 2 (2 bytes)

➯ First segment = Control byte + 2 bytes of data

• Message 3 (9 bytes)

➯ First segment = Control byte + 9 bytes of data

• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C1 (control byte 1) C2 (control byte 2) C3 (control byte 3)
- SegmentLength (7) = 7 - SegmentLength (2) = 2 - SegmentLength (9) = 9
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (1) = 128 - MessageEndBit (1) = 128 - MessageEndBit (1) = 128
Control byte Σ 135 Control byte Σ 130 Control byte Σ 137

Table 90: FlatStream determination of the control bytes for the large segment and MultiSegmentMTU example

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4.4.3.10.7.5 Example of Forward functionality on X2X Link

Forward functionality is a method that can be used to substantially increase the FlatStream data rate. The basic
principle is also used in other technical areas such as "pipelining" for microprocessors.

Operating principle

X2X Link communication cycles through five different steps to transmit a FlatStream sequence. At least five bus
cycles are therefore required to successfully transfer the sequence.
Step I Step II Step III Step IV Step V
Actions Transfer sequence from Cyclic matching of MTU and Append sequence to re- Cyclic matching of Check SequenceAck
transmit array, module buffer ceive array MTU and module buffer
increase Sequence- Adjust SequenceAck
Counter
Resource Transmitter Bus system Recipient Bus system Transmitter
(task to transmit) (direction 1) (task to receive) (direction 2) (task for Ack checking)

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 ...

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Figure 185: Comparison of transmission without/with Forward

Each of the five steps (tasks) requires different resources. If Forward functionality is not used, the sequences are
executed one after the other. Each resource is then only active if it is needed for the current sub-action.
With Forward, a resource that has executed its task can already be used for the next message. The condition for
enabling the MTU is changed to allow for this. Sequences are then passed to the MTU according to the timing. The
transmitting station no longer waits for an acknowledgment from SequenceAck, which means that the available
bandwidth can be used much more efficiently.
In the most ideal situation, all resources are working during each bus cycle. The receiver still has to acknowledge
every sequence received. Only when SequenceAck has been changed and checked by the transmitter is the
sequence considered as having been transmitted successfully.

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Configuration

The Forward function only has to be enabled for the input direction. Two additional configuration registers are
available for doing so. FlatStream modules have been optimized in such a way that they support this function. In
the output direction, the Forward function can be used as soon as the size of the OutputMTU is specified.

Number of unconfirmed sequences

Name:
Forward
With the "Forward" register, the user specifies how many unacknowledged sequences the module is allowed to
transmit.
Recommendation:
X2X Link: Max. 5
POWERLINK: Max. 7
Data type Value
USINT 1 to 7
Default: 1

Delay time

Name:
ForwardDelay
The "ForwardDelay" register is used to specify the delay time in µs. This is the amount of time the module has
to wait after sending a sequence until it is allowed to write new data to the MTU in the following bus cycle. The
program routine for receiving sequences from a module can therefore be run in a task class whose cycle time is
slower than the bus cycle.
Data type Value
UINT 0 to 65,535 [µs]
Default: 0

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Zeit

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Zeit

Figure 186: Effect of ForwardDelay when using FlatStream communication with the Forward function
In the program, it is important to make sure that the CPU is processing all of the incoming InputSequences and In-
putMTUs. The ForwardDelay value causes delayed acknowledgment in the output direction and delayed reception
in the input direction. In this way, the CPU has more time to process the incoming InputSequence or InputMTU.

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Transmitting and receiving with Forward

The basic algorithm for transmitting and receiving data remains the same. With the Forward function, up to seven
unacknowledged sequences can be transmitted. Sequences can be transmitted without having to wait for the
previous message to be acknowledged. Since the delay between writing and response is eliminated, a considerable
amount of additional data can be transferred in the same time window.
Algorithm for transmitting
Cyclic status query:
- The Module monitors the OutputSequenceCounter.
0) Cyclic checks:
- The CPU must check OutputSyncAck.
→ If OutputSyncAck = 0: Reset the OutputSyncBit and resynchronize the channel.
- The CPU must check whether OutputMTU is enabled.
→ If OutputSequenceCounter > OutputSequenceAck + 7, then it is not enabled because the last sequence has not yet been acknowledged.
1) Preparation (create transmit array):
- The CPU must split up the message into valid segments and create the necessary control bytes.
- The CPU must add the segments and control bytes to the transmit array.
2) Transmit:
- The CPU must transfer the current part of the transmit array to the OutputMTU.
- The CPU must increase the OutputSequenceCounter for the sequence to be accepted by the module.
- The CPU can then transmit in the next bus cycle if the MTU has been enabled.
The module responds since OutputSequenceCounter > OutputSequenceAck:
- The module accepts data from the internal receive buffer and appends it to the end of the internal receive array.
- The module is acknowledged and the currently received value of the OutputSequenceCounter is transferred to OutputSequenceAck.
- The module requests the status cyclically again.
3) Completion (acknowledgment):
- The CPU must check OutputSequenceAck cyclically.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via OutputSequenceAck. In order to detect potential trans-
mission errors in the last sequence as well, it is important to make sure that the algorithm is run through long enough.

Note:
To monitor communication times exactly, the task cycles that have passed since the last increase of the OutputSequenceCounter should be counted. In this
way, the number of previous bus cycles necessary for the transmission can be measured. If the monitoring counter exceeds a predefined threshold, then the
sequence can be considered lost (the relationship of bus to task cycle can be influenced by the user so that the threshold value needs to be determined individ-
ually).

Algorithm for receiving

0) Cyclic status query:
- The CPU must monitor the InputSequenceCounter.
Cyclic checks:
- The module checks InputSyncAck.
- The module checks if InputMTU is enabled.
→ Enabling criteria: InputSequenceCounter > InputSequenceAck + Forward
Preparation:
- The module forms the control bytes / segments and creates the transmit array.
Action:
- The module transmits the current part of the transmit array to the receive buffer.
- The module increases the InputSequenceCounter.
- The module waits for a new bus cycle after the ForwardDelay time has expired.
- The module repeats the action if the InputMTU is enabled.
1) Receiving (InputSequenceCounter > InputSequenceAck):
- The CPU must accept data from the InputMTU and append it to the end of the receive array.
- The CPU must match InputSequenceAck to the InputSequenceCounter of the sequence currently being processed.
Completion:
- The module monitors InputSequenceAck.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via InputSequenceAck .

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Details/Background
1. Illegal SequenceCounter size (counter offset)
Error situation: MTU not enabled
If the difference between SequenceCounter and SequenceAck is larger than allowed during transmission,
then a transmission error has occurred. In this case, all unacknowledged sequences must be repeated with
the old SequenceCounter value.
2. Checking an acknowledgment
After an acknowledgment has been received, a check must verify whether the acknowledged sequence has
been transmitted and had not yet been unacknowledged. If a sequence has been acknowledged more than
once, then a fatal error has occurred. The channel must be closed and resynchronized (same behavior as
when not using Forward).

Information:
In exceptional cases, the module can increment OutputSequenceAck by more than 1 when using
Forward.
This is not an error. The CPU is permitted to consider all sequences up to the one being acknowl-
edged as having been transmitted successfully.

3. Transmit and receive arrays

The Forward function has no effect on the structure of the transmit and receive arrays. They are created and
must be evaluated in the same way.

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Errors when using Forward

In industrial environments, it is often the case that many different devices from various manufacturers are being
used side by side. The electrical and/or electromagnetic properties of these technical devices can sometimes cause
them to interfere with one another. These kinds of situations can be reproduced and protected against in laboratory
conditions only to a certain point.
Precautions have been taken for X2X Link transmissions if this type of interference occurs. For example, if an
invalid checksum occurs, the I/O system will ignore the data from this bus cycle and the receiver receives the last
valid data once more. With conventional (cyclic) data points, this error can often be ignored. In the following cycle,
the same data point is again retrieved, adjusted and transmitted.
Using Forward functionality with FlatStream communication makes this situation more complex. The receiver re-
ceives the old data again in this situation as well, i.e. the previous values for SequenceAck/SequenceCounter and
the old MTU.
Loss of acknowledgment (SequenceAck)
If a SequenceAck value is lost, then the MTU was already transmitted properly. For this reason, the receiver is per-
mitted to continue processing with the next sequence. The SequenceAck is aligned with the associated Sequence-
Counter and sent back to the transmitter. Checking the incoming acknowledgments shows that all sequences up
to the last one acknowledged have been transmitted successfully (see sequences 1 and 2 in the image).
Loss of transmission (SequenceCounter, MTU)
If a bus cycle drops out and the SequenceCounter value and/or filled MTU are lost, then no data reaches the
receiver. At this point, the transmission routine is not yet affected by the error. The time-controlled MTU is released
again and can be rewritten to.
The receiver receives SequenceCounter values that have been incremented several times. For the receive array
to be put together correctly, the receiver is only allowed to process transmissions whose SequenceCounter has
been increased by one. The incoming sequences must be ignored, i.e. the receiver stops and no longer transmits
back any acknowledgments.
If the maximum number of unacknowledged sequences has been sent and no acknowledgments are returned, the
transmitter must repeat the affected SequenceCounter and associated MTUs (see sequence 3 and 4 in the image).

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Sequence 4 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Sequence 1 Step I Step II Step III

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step I Step II Step III

Sequence 4 Step I Step II Step I Step II

Bus cycle 1 Bus cycle 2 Bus cycle 3 EMC Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Figure 187: Effect of a lost bus cycle

Loss of acknowledgment
In sequence 1, the acknowledgment is lost due to disturbance. Sequences 1 and 2 are therefore acknowledged
in Step V of sequence 2.
Loss of transmission
In sequence 3, the entire transmission is lost due to disturbance. The receiver stops and no longer sends back
any acknowledgments.
The transmitting station continues transmitting until it has issued the maximum permitted number of unacknowl-
edged transmissions.
Five bus cycles later at the earliest (depending on the configuration), it begins resending the unsuccessfully sent
transmissions.

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4.4.3.10.8 HART with FlatStream

When using FlatStream communication, the module acts as a bridge between the X2X master and an intelligent
field device connected to the module. FlatStream mode can be used for either point-to-point connections as well
as for multidrop systems. Specific algorithms such as timeout and checksum monitoring are usually managed
automatically. During normal operation, the user does not have access to these details.
HART is considered a master-slave network where half-duplex communication takes place asynchronously. Vari-
ous features have been included to ensure that signals are transmitted without errors.
For example, the user can increase the length of the preamble, thus making the transmission more secure. How-
ever, this also has an effect on the percentage of payload data and overhead.
Additional information about HART can be found at www.HARTcomm.org.

Operation
The module has two independent channels. When using FlatStream, the channel number must therefore be spec-
ified. The general structure of a FlatStream frame is extended as follows.
Input/Output sequence Tx/Rx bytes
(unchanged) Control byte Channel number HART frame
(unchanged) (without preamble and checksum)

HART frame with FlatStream

Start ADDR CMD BCNT (STS) (DATA)

Start Start identification

ADDR Address within the HART network
CMD HART command
BCNT Byte counters (number of remaining bytes)
*STS Status of the last command received. Information about the working mode of the HART Slave and communication
errors (if supported, return data from the HART Slave)
*DATA Data (if necessary for the command)

Examples of HART commands

Command Function
0x00 Read slave ID
0x03 Read current value and up to four variables
0x09 Read up to four variables including status
0x21 Read variables

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4.4.3.10.9 "OSP" function model

In the "OSP" function model (Operator Set Predefined), the user defines an analog value or digital pattern. This
OSP value is output as soon as communication between the module and master is interrupted.
Functionality
The user can choose between two OSP modes:
• Retain last valid value
• Replace with static value
In the first case, the module retains the last value as validly recognized output state.
When selecting the mode, "Replace with static value" a plausible output value must be entered in the corresponding
value register. If an OSP event occurs, this value will be output instead of the value currently requested by the task.

4.4.3.10.9.1 Activating the OSP output in the module

Name:
OSPValid
This data point offers the possibility to start module output and request OSP operation during running operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 OSPValid 0 Request OSP operation (after initial start or module in Standby)
1 Request normal operation
1-7 Reserved 0

There is one OSPValid bit on the module, which is managed by the user task. It must be set when the enabled
channels are started. As long as the OSPValid bit remains set in the module, the module behaves the same as
the "Standard" function model.
If an OSP event occurs (e.g. communication between the module and master CPU interrupted) then the OSPValid
bit will be reset on the module. The module enters OSP mode and the output occurs in the "OSPMode" register
according to the configuration.
The following applies:
The OSP replacement value remains even after the communication channel has recovered. OSP mode
is only exited when a set OSPValid bit is transferred.
When the master CPU is restarted, the OSPValid bit is re-initialized on the master CPU. It must once
more be set by the application and transferred via the bus.
When temporary communication errors occur between the module and master CPU (e.g. due to EMC),
a few bus cycles will pass without refreshing the cyclic registers. The OSPValid bit is reset internally in
the module - the bit in the CPU however remains set. Upon the next successful transfer, the OSPValid
bit in the module is set again and the module returns to normal operation.
The ModulOK bit can be evaluated if the task in the master CPU needs to know which output mode the module
is currently in.

Warning!
If the OSPValid bit is reset to "0" on the module, then the output state no longer depends on the relevant
task in the master CPU. However, an output still occurs depending on the configuration of the OSP
replacement value.

4.4.3.10.9.2 Setting the OSP mode

Name:
CfgOSPMode01 to CfgOSPMode02
This register essentially controls a channel's behavior when OSP is being used.
Data type Value Description
USINT 0 Replace with static value
1 Retain last valid value

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4.4.3.10.9.3 Define the OSP analog output value

Name:
CfgOSPValue01 to CfgOSPValue02
This register contains the analog output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
Corresponds to Corresponds to AnalogOutput0x
AnalogOutput0x

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.4.3.10.10 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
200 µs

4.4.3.10.11 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Analog outputs 1 ms

Minimum I/O update time Hart Communication

Point-to-point 500 ms
Multidrop Number of stations * 1000 ms

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4.4.4 X20AO2622

4.4.4.1 General information

The module is equipped with two outputs with 13-bit (including sign) digital converter resolution. It is possible to
select between the current and voltage signal using different connection terminal points.
This module is designed for X20 6-pin terminal blocks. If needed (e.g. for logistical reasons), the 12-pin terminal
block can also be used.
• 2 analog outputs
• Either current or voltage signal possible
• 13-bit digital converter resolution

4.4.4.2 Order data

Model number Short description Figure

Analog output modules
X20AO2622 X20 analog output module, 2 outputs, ±10 V / 0 to 20 mA / 4 to
20 mA, 13-bit resolution
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 91: X20AO2622 - Order data

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4.4.4.3 Technical data

Product ID X20AO2622
Short description
I/O module 2 analog outputs ±10 V or 0 to 20 mA / 4 to 20 mA 1)
General information
B&R ID code 0x1BA2
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Channel type Yes, using software
Power consumption
Bus 0.01 W
Internal I/O 1.1 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Analog outputs
Output ±10 V or 0 to 20 mA / 4 to 20 mA, via different terminal connections 1)
Max. output current 10 mA at voltages >5 V
15 mA at voltages <5 V
Digital converter resolution
Voltage ±12-bit
Current 12 Bit
Conversion time 200 µs for all outputs
Settling time for output changes over entire range 1 ms
Power on/off behavior Internal enable relay for booting
Max. error at 25°C
Voltage
Gain 0.150% 2)
Offset 0.050% 3)
Current
Gain 0.150% 2)
Offset 0.050% 3)
Output protection Short circuit protection
Output format
Voltage INT 0x8001 - 0x7FFF / 1 LSB = 0x0010 = 4.882 mV
Current INT 0x8001 - 0x7FFF / 1 LSB = 0x0010 = 9.766 µA
Load per channel
Voltage Max. ±10 mA, load ≥1 kΩ
Current Load max. 600 Ω (Rev. ≥ J0); 500 Ω (Rev. < J0)
Short circuit protection Current limiting ±40 mA
Output filter 1st-order low pass / cutoff frequency 10 kHz
Max. gain drift
Voltage 0.020 %/°C 2)
Current 0.020 %/°C 2)
Max. offset drift
Voltage 0.032 %/°C 3)
Current 0.032 %/°C 3)
Error caused by load change
Voltage Max. 0.11%, from 10 MΩ → 1 kΩ, resistive
Current Max. 0.50%, from 1 Ω → 600 Ω, resistive
Non-linearity <0.007% 4)
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20

Table 92: X20AO2622 - Technical data

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Product ID X20AO2622
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 92: X20AO2622 - Technical data

1) 4 to 20 mA: From upgrade version 1.0.2.0 or hardware revision "I0"
2) Based on the current output value.
3) Based on the entire output range.
4) Based on the output range.

4.4.4.4 LED status indicators

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
e+r Red on / Green single flash Invalid firmware
1-2 Orange Off Value = 0
On Value ≠ 0

1) Depending on the configuration, a firmware update can take up to several minutes.

4.4.4.5 Pinout

Each channel can be configured for either current or voltage signals. The type of signal is also determined by the
connection terminals used.

r e
X20 AO 2622

1 2

AO + 1 I AO + 2 I

AO + 1 U AO + 2 U

AO - 1 U/I AO - 2 U/I

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4.4.4.6 Connection example

AO

Voltage Current

Load
+

Load
+24 VDC +24 VDC
GND GND

4.4.4.7 Output circuit diagram

AO + x I

Reset

Output value D/A

converter SSR

I/O status
AO + x U

LED (orange) AO - x U/I

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4.4.4.8 Register description

4.4.4.8.1 Function model 0 - Standard

and function model 1 - I/O with fast reaction

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Configuration
18 ConfigOutput01 USINT ●
Communication
0 AnalogOutput01 INT ●
2 AnalogOutput02 INT ●

4.4.4.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Configuration
18 - ConfigOutput01 USINT ●
Communication
0 0 AnalogOutput01 INT ●
2 2 AnalogOutput02 INT ●

1) The offset specifies the position of the register within the CAN object.

4.4.4.8.3 Function model comparison

Function model 0: I/O without jitter (standard)

Corrected values are output in the next cycle if the minimum cycle is ≥300 μs in order to reduce jitter to a minimum.
Function model 1: I/O with fast reaction
Corrected values are output in the same cycle if the minimum cycle is ≥300 μs (optimized reactions).
Comparison of the two function models
Function model 0: I/O without jitter

Value transfer Internal processing time of the I/O module

0 1 2 3 4 5

X2X

I/O
0 1 2 3 4 5
Values output in the next cycle

Function model 1: I/O with fast reaction

Value transfer
0 1 2 3 4 5

X2X

I/O
0 1 2 3 4 5
Values output in the same cycle

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4.4.4.8.4 Analog outputs

Each channel can be configured for either current or voltage signals. The type of signal is also determined by the
connection terminals used.

4.4.4.8.4.1 Output values of the analog outputs

Name:
AnalogOutput01 to AnalogOutput02
These registers provide the standardized output values. Once a permitted value is received the module outputs
the respective current or voltage.
Data type Value Information
INT -32768 to 32767 Voltage signal -10 to 10 VDC
0 to 32767 Current signal 0 to 20 mA
0 to 32767 Current signal 4 to 20 mA1)

1) From upgrade version 1.0.2.0 or hardware revision "I0"

4.4.4.8.4.2 Setting the channel type

Name:
ConfigOutput01
This register can be used to set the channel type of the outputs.
Each channel is capable of handling either current or voltage signals. The type of signal is determined by the
connection terminals used. Since current and voltage require different adjustment values, it is also necessary to
configure the desired type of output signal. The following output signals can be set:
• ±10 V voltage signal (default)
• 0 to 20 mA current signal
• 4 to 20 mA current signal
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Channel 1 0 Voltage signal
1 Current signal, measurement range corresponding to bit 4
1 Channel 2 0 Voltage signal
1 Current signal, measurement range corresponding to bit 5
2-3 Reserved 0
4 Channel 1: Current measurement range 0 0 to 20 mA current signal
1 4 to 20 mA current signal
5 Channel 2: Current measurement range 0 0 to 20 mA current signal
1 4 to 20 mA current signal
6-7 Reserved 0

4.4.4.8.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
250 μs

4.4.4.8.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
300 μs

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4.4.5 X20AO2632

4.4.5.1 General information

The module is equipped with two outputs with 16-bit (including sign) digital converter resolution. It is possible to
select between the current and voltage signal using different connection terminal points.
This module is designed for X20 6-pin terminal blocks. If needed (e.g. for logistical reasons), the 12-pin terminal
block can also be used.
• 2 analog outputs
• Either current or voltage signal possible
• 16-bit digital converter resolution

4.4.5.2 Order data

Model number Short description Figure

Analog output modules
X20AO2632 X20 analog output module, 2 outputs, ±10 V / 0 to 20 mA, 16-
bit resolution
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 93: X20AO2632 - Order data

4.4.5.3 Technical data

Product ID X20AO2632
Short description
I/O module 2 analog outputs, ±10 V or 0 to 20 mA
General information
B&R ID code 0x1BA4
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Channel type Yes, using software
Power consumption
Bus 0.01 W
Internal I/O 1.1 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Analog outputs
Output ±10 V or 0 to 20 mA, via different terminal connections
Digital converter resolution
Voltage ±15-bit
Current 15 Bit
Conversion time 50 µs for all outputs
Settling time for output changes over entire range 500 μs (Rev. <H0: 1 ms)
Power on/off behavior Internal enable relay for booting

Table 94: X20AO2632 - Technical data

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Product ID X20AO2632
Max. error at 25°C
Voltage
Gain 0.045% 1)
Offset 0.025% 2)
Current
Gain 0.090% 1)
Offset 0.045% 2)
Output protection Short circuit protection
Output format
Voltage INT 0x8000 - 0x7FFF / 1 LSB = 0x0001 = 305.176 µV
Current INT 0x0000 - 0x7FFF / 1 LSB = 0x0001 = 610.352 nA
Load per channel
Voltage Max. ±10 mA, load ≥1 kΩ
Current Load max. 600 Ω (Rev. ≥ J0); 500 Ω (Rev. < J0)
Short circuit protection Current limiting ±40 mA
Output filter 1st-order low pass / cutoff frequency 10 kHz
Max. gain drift
Voltage 0.015 %/°C 1)
Current 0.020 %/°C 1)
Max. offset drift
Voltage 0.013 %/°C 2)
Current 0.013 %/°C 2)
Error caused by load change
Voltage Max. 0.11%, from 10 MΩ → 1 kΩ, resistive
Current Max. 0.50%, from 1 Ω → 600 Ω, resistive
Non-linearity <0.007% 3)
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 94: X20AO2632 - Technical data

1) Based on the current output value.
2) Based on the entire output range.
3) Based on the output range.

4.4.5.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
1-2 Orange Off Value = 0
On Value ≠ 0

Table 95: LED status indicators

1) Depending on the configuration, a firmware update can take up to several minutes.

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4.4.5.5 Pinout

Each channel can be configured for either current or voltage signals. The type of signal is also determined by the
connection terminals used.

r e

X20 AO 2632
1 2

AO + 1 I AO + 2 I

AO + 1 U AO + 2 U

AO - 1 U/I AO - 2 U/I

Figure 188: Pinout

4.4.5.6 Connection example

AO
Voltage Current
Load Load

+24 VDC +24 VDC

GND GND

4.4.5.7 Output circuit diagram

AO + x I

Reset

Output value D/A

converter SSR

I/O status
AO + x U

LED (orange) AO - x U/I

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4.4.5.8 Register description

4.4.5.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog output - Configuration
0 ConfigOutput01 UINT ●
594 Cfo_Channel01TimeMode UINT ●
598 Cfo_Channel02TimeMode
Analog output - Communication
2 AnalogOutput01 INT ●
4 AnalogOutput02
457 SDCLifeCount SINT ●
802 ValidationTimer01 INT ●
810 ValidationTimer02
804 ValidationTimer01 DINT ●
812 ValidationTimer02
833 Enabling/disabling the output channels USINT ● ●
AnalogOutput01Enable, ~Readback Bit 0
AnalogOutput02Enable, ~Readback Bit 1
835 Checking the output values USINT ●
AnalogOutput01OK Bit 0
AnalogOutput02OK Bit 1

4.4.5.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog output - Configuration
0 - ConfigOutput01 UINT ●
Analog output - Communication
2 0 AnalogOutput01 INT ●
4 2 AnalogOutput02

1) The offset specifies the position of the register within the CAN object.

4.4.5.8.3 General information

The module provides two analog outputs. Each channel can output a voltage range of ±10 V or a current range
of 0 to 20 mA.
The module also has a time-based watchdog monitor. The user can activate this feature channel-by-channel as
needed.

4.4.5.8.4 Analog output - Configuration

Each channel is configured independently. The user can also define an optional time-based monitor. To make this
possible, two watchdog timers were implemented, which can be assigned to the outputs.

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4.4.5.8.4.1 Setting the channel type

Name:
ConfigOutput01
This register can be used to set the channel type of the outputs.
Each channel is capable of handling either current or voltage signals. The type of signal is determined by the
connection terminals used. Since current and voltage require different adjustment values, it is also necessary to
configure the desired type of output signal. The following output signals can be set:
• ±10 V voltage signal (default)
• 0 to 20 mA current signal
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-7 Reserved 0
8 Channel 1 0 Voltage signal
1 Current signal
9 Channel 2 0 Voltage signal
1 Current signal
10 - 15 Reserved 0

4.4.5.8.4.2 Configuring the time-based watchdog monitor

Name:
Cfo_Channel01TimeMode to Cfo_Channel02TimeMode
This register is used to activate or configure the time-based watchdog monitor for the analog output channels.
Possibilities per channel:
• Validation timer data type: General choice 16 or 32 bit
• Validation window: The maximum value can be further limited within the data type.
• Timer allocation: A separate timer is available for each channel. However, all channels can be configured
with the same validation timer, whereby the same settings must be made for the data type and window
in the TimeMode registers.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-4 Max. validation time 00000 Disabled
00001 2 µs
00010 4 µs
00011 8 µs
... ...
11111 2,147,483,648 µs (~35 min)
5-7 Reserved 0
8 Timer allocation 0 ValidationTimer01 (default for channel 1)
1 ValidationTimer02 (default for channel 2)
9 - 14 Reserved 0
15 Time format 0 16-bit
1 32-bit

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4.4.5.8.5 Analog output - Communication

In standard mode, the module's outputs are enabled. Based on the configuration and AnalogOutput value, they
output the corresponding current or voltage.
If the application requires time-based monitoring of the outputs, then a validation timer can be assigned to each
channel. The validation timer register assigns a validity duration to the current output value. When validation is
enabled, the module compares the validation time with the Nettime of the X2X Link. If the transferred validity
duration is exceeded, the module disables the channel and resets the output. The "safety shutdown" state will not
be reset until a new and valid validation time has been transferred. If enabled, the module reports which state it
is currently in via the channel's error status bit.
If the value of the validation timer is incremented in each task cycle, the valid validation time will be calculated
as follows:
Nettime of the X2X Link master (which the module is connected to)
+ Timespan for transferring data from the X2X Link master to the CPU (higher-level system)
+ Cycle time of task class (including tolerance)
+ Timespan for transferring the data from the CPU to the module
+ Timespan allowed by the application (e.g. for tolerating failure of an X2X Link cycle)
= Valid validation time

The AnalogOutputEnableByte is enabled during time-based monitoring. If the timer expires prematurely, the corre-
sponding bit in the AnalogOutputOkayByte is reset and the output drops out. This provides an easy way to achieve
a defined state.

4.4.5.8.5.1 Output values of the analog outputs

Name:
AnalogOutput01 to AnalogOutput02
These registers provide the standardized output values. Once a permitted value is received, the module outputs
the respective current or voltage.

Information:
The value "0" disables the channel status LED.
Data type Value
INT -32767 to 32767 Voltage; Bus controller default setting: 0
0 to 32767 Current

4.4.5.8.5.2 SDC counter register

Name:
SDCLifeCount
The 8-bit counter register is needed for the SDC software package. It is incremented with the system clock to allow
the SDC to check the validity of the data frame.
Data type Value
SINT -128 to 127

4.4.5.8.5.3 Transfer of the timestamp

Name:
ValidationTimer01 to ValidationTimer02
When an output is being monitored, these registers must provide the timestamp which, when reached, will cause
the output to shut down automatically. The values must be provided as signed 2-byte or 4-byte values.
Data type Values [µs]
INT -32768 to 32767 Nettime timestamp of the current output value
DINT -2,147,483,648 Nettime timestamp of the current output value
to 2,147,483,647

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4.4.5.8.5.4 Enabling/disabling the output channels

Name:
AnalogOutput01Enable to AnalogOutput02Enable
AnalogOutput01EnableReadback to AnalogOutput02EnableReadback
The "OutputEnable" byte is only needed for the channels with activated time-based monitoring. The individual bits
are used to enable/disable the respective channels. To receive reliable feedback about the current state of the
module, the byte was also implemented so that it can be read cyclically.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Value Information
0 AnalogOutput01Enable 0 Output deactivated
AnalogOutput01EnableReadback 1 Output activated
1 AnalogOutput02Enable 0 Output deactivated
AnalogOutput02EnableReadback 1 Output activated
2-7 Reserved 0

4.4.5.8.5.5 Checking the output values

Name:
AnalogOutput01OK to AnalogOutput02OK
These registers are only needed for channels with activated time-based monitoring. The individual bits report
whether the respective channel is actually generating the required voltage or current.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Value Information
0 AnalogOutput01OK 0 Electrical signal deactivated
1 Electrical signal activated
1 AnalogOutput02OK 0 Electrical signal deactivated
1 Electrical signal activated
2-7 Reserved 0

4.4.5.8.6 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
200 µs

4.4.5.8.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
200 µs

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4.4.6 X20AO2632-1

4.4.6.1 General information

The module is equipped with two outputs with 16-bit (including sign) digital converter resolution. It is possible to
select between the current and voltage signal using different connection terminal points.
This module is designed for X20 6-pin terminal blocks. If needed (e.g. for logistical reasons), the 12-pin terminal
block can also be used.
• 2 analog outputs
• Either current or voltage signal possible
• Extended signal range
• 16-bit digital converter resolution

4.4.6.2 Order data

Model number Short description Figure

Analog output modules
X20AO2632-1 X20 analog output module, 2 outputs, ±11 V / 0 to 22 mA, 16-
bit resolution
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 96: X20AO2632-1 - Order data

4.4.6.3 Technical data

Product ID X20AO2632-1
Short description
I/O module 2 analog outputs, ±11 V or 0 to 22 mA
General information
B&R ID code 0xC36E
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Channel type Yes, using software
Power consumption
Bus 0.01 W
Internal I/O 1.25 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Analog outputs
Output ±11 V or 0 to 22 mA, via different terminal connections
Digital converter resolution
Voltage ±15-bit
Current 15-bit
Conversion time 50 µs for all outputs
Settling time for output changes over entire range 500 µs
Power on/off behavior Internal enable relay for booting

Table 97: X20AO2632-1 - Technical data

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Product ID X20AO2632-1
Max. error at 25°C
Voltage
Gain 0.050% 1)
Offset 0.015% 2)
Current
Gain 0.080% 1)
Offset 0.050% 2)
Output protection Short circuit protection
Output format
Voltage INT 0x8000 - 0x7FFF / 1 LSB = 0x0001 = 335.693 µV
Current INT 0x0000 - 0x7FFF / 1 LSB = 0x0001 = 671.386 nA
Load per channel
Voltage Max. ±11 mA, load ≥1 kΩ
Current Max. load is 600 Ω
Short circuit protection Current limiting ±40 mA
Output filter 1st-order low pass / cutoff frequency 10 kHz
Max. gain drift
Voltage 0.008 %/°C 1)
Current 0.011 %/°C 1)
Max. offset drift
Voltage 0.003 %/°C 2)
Current 0.008 %/°C 2)
Error caused by load change
Voltage Max. 0.10%, from 10 MΩ → 1 kΩ, resistive
Current Max. 0.50%, from 1 Ω → 600 Ω, resistive
Non-linearity <0.007% 3)
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 97: X20AO2632-1 - Technical data

1) Based on the current output value.
2) Based on the entire output range.
3) Based on the output range.

4.4.6.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
1-2 Orange Off Value = 0
On Value ≠ 0

Table 98: LED status indicators

1) Depending on the configuration, a firmware update can take up to several minutes.

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4.4.6.5 Pinout

Each channel can be configured for either current or voltage signals. The type of signal is also determined by the
connection terminals used.

r e

X20 AO 2632-1
1 2

AO + 1 I AO + 2 I

AO + 1 U AO + 2 U

AO - 1 U/I AO - 2 U/I

Figure 189: Pinout

4.4.6.6 Connection example

AO
Voltage Current
Load Load

+24 VDC +24 VDC

GND GND

4.4.6.7 Output circuit diagram

AO + x I

Reset

Output value D/A

converter SSR

I/O status
AO + x U

LED (orange) AO - x U/I

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4.4.6.8 Register description

4.4.6.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog output - Configuration
0 ConfigOutput01 UINT ●
594 Cfo_Channel01TimeMode UINT ●
598 Cfo_Channel02TimeMode
Analog output - Communication
2 AnalogOutput01 INT ●
4 AnalogOutput02
457 SDCLifeCount SINT ●
802 ValidationTimer01 INT ●
810 ValidationTimer02
804 ValidationTimer01 DINT ●
812 ValidationTimer02
833 Enabling/disabling the output channels USINT ● ●
AnalogOutput01Enable, ~Readback Bit 0
AnalogOutput02Enable, ~Readback Bit 1
835 Checking the output values USINT ●
AnalogOutput01OK Bit 0
AnalogOutput02OK Bit 1

4.4.6.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog output - Configuration
0 - ConfigOutput01 UINT ●
Analog output - Communication
2 0 AnalogOutput01 INT ●
4 2 AnalogOutput02

1) The offset specifies the position of the register within the CAN object.

4.4.6.8.3 General information

The module provides two analog outputs. Each channel can output a voltage range of ±11 V or a current range
of 0 to 22 mA.
The module also has a time-based watchdog monitor. The user can activate this feature channel-by-channel as
needed.

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4.4.6.8.4 Analog output - Configuration

Each channel is configured independently. The user can also define an optional time-based monitor. To make this
possible, two watchdog timers were implemented, which can be assigned to the outputs.

4.4.6.8.4.1 Setting the channel type

Name:
ConfigOutput01
This register can be used to set the channel type of the outputs.
Each channel is capable of handling either current or voltage signals. The type of signal is determined by the
connection terminals used. Since current and voltage require different adjustment values, it is also necessary to
configure the desired type of output signal. The following output signals can be set:
• ±11 V voltage signal (default)
• 0 to 22 mA current signal
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-7 Reserved 0
8 Channel 1 0 Voltage signal
1 Current signal
9 Channel 2 0 Voltage signal
1 Current signal
10 - 15 Reserved 0

4.4.6.8.4.2 Configuring the time-based watchdog monitor

Name:
Cfo_Channel01TimeMode to Cfo_Channel02TimeMode
This register is used to activate or configure the time-based watchdog monitor for the analog output channels.
Possibilities per channel:
• Validation timer data type: General choice 16 or 32 bit
• Validation window: The maximum value can be further limited within the data type.
• Timer allocation: A separate timer is available for each channel. However, all channels can be configured
with the same validation timer, whereby the same settings must be made for the data type and window
in the TimeMode registers.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-4 Max. validation time 00000 Disabled
00001 2 µs
00010 4 µs
00011 8 µs
... ...
11111 2,147,483,648 µs (~35 min)
5-7 Reserved 0
8 Timer allocation 0 ValidationTimer01 (default for channel 1)
1 ValidationTimer02 (default for channel 2)
9 - 14 Reserved 0
15 Time format 0 16-bit
1 32-bit

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4.4.6.8.5 Analog output - Communication

In standard mode, the module's outputs are enabled. Based on the configuration and AnalogOutput value, they
output the corresponding current or voltage.
If the application requires time-based monitoring of the outputs, then a validation timer can be assigned to each
channel. The validation timer register assigns a validity duration to the current output value. When validation is
enabled, the module compares the validation time with the Nettime of the X2X Link. If the transferred validity
duration is exceeded, the module disables the channel and resets the output. The "safety shutdown" state will not
be reset until a new and valid validation time has been transferred. If enabled, the module reports which state it
is currently in via the channel's error status bit.
If the value of the validation timer is incremented in each task cycle, the valid validation time will be calculated
as follows:
Nettime of the X2X Link master (which the module is connected to)
+ Timespan for transferring data from the X2X Link master to the CPU (higher-level system)
+ Cycle time of task class (including tolerance)
+ Timespan for transferring the data from the CPU to the module
+ Timespan allowed by the application (e.g. for tolerating failure of an X2X Link cycle)
= Valid validation time

The AnalogOutputEnableByte is enabled during time-based monitoring. If the timer expires prematurely, the corre-
sponding bit in the AnalogOutputOkayByte is reset and the output drops out. This provides an easy way to achieve
a defined state.

4.4.6.8.5.1 Output values of the analog outputs

Name:
AnalogOutput01 to AnalogOutput02
These registers provide the standardized output values. Once a permitted value is received, the module outputs
the respective current or voltage.

Information:
The value "0" disables the channel status LED.
Data type Value
INT -32767 to 32767 Voltage; Bus controller default setting: 0
0 to 32767 Current

4.4.6.8.5.2 SDC counter register

Name:
SDCLifeCount
The 8-bit counter register is needed for the SDC software package. It is incremented with the system clock to allow
the SDC to check the validity of the data frame.
Data type Value
SINT -128 to 127

4.4.6.8.5.3 Transfer of the timestamp

Name:
ValidationTimer01 to ValidationTimer02
When an output is being monitored, these registers must provide the timestamp which, when reached, will cause
the output to shut down automatically. The values must be provided as signed 2-byte or 4-byte values.
Data type Values [µs]
INT -32768 to 32767 Nettime timestamp of the current output value
DINT -2,147,483,648 Nettime timestamp of the current output value
to 2,147,483,647

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4.4.6.8.5.4 Enabling/disabling the output channels

Name:
AnalogOutput01Enable to AnalogOutput02Enable
AnalogOutput01EnableReadback to AnalogOutput02EnableReadback
The "OutputEnable" byte is only needed for the channels with activated time-based monitoring. The individual bits
are used to enable/disable the respective channels. To receive reliable feedback about the current state of the
module, the byte was also implemented so that it can be read cyclically.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Value Information
0 AnalogOutput01Enable 0 Output deactivated
AnalogOutput01EnableReadback 1 Output activated
1 AnalogOutput02Enable 0 Output deactivated
AnalogOutput02EnableReadback 1 Output activated
2-7 Reserved 0

4.4.6.8.5.5 Checking the output values

Name:
AnalogOutput01OK to AnalogOutput02OK
These registers are only needed for channels with activated time-based monitoring. The individual bits report
whether the respective channel is actually generating the required voltage or current.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Value Information
0 AnalogOutput01OK 0 Electrical signal deactivated
1 Electrical signal activated
1 AnalogOutput02OK 0 Electrical signal deactivated
1 Electrical signal activated
2-7 Reserved 0

4.4.6.8.6 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
200 µs

4.4.6.8.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
200 µs

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4.4.7 X20AO4622

4.4.7.1 General information

The module is equipped with four outputs with 13-bit (including sign) digital converter resolution. It is possible to
select between the current and voltage signal using different connection terminal points.
• 4 analog outputs
• Either current or voltage signal possible
• 13-bit digital converter resolution

4.4.7.2 Order data

Model number Short description Figure

Analog output modules
X20AO4622 X20 analog output module, 4 outputs, ±10 V / 0 to 20 mA / 4 to
20 mA, 13-bit resolution
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 99: X20AO4622 - Order data

4.4.7.3 Technical data

Product ID X20AO4622
Short description
I/O module 4 analog outputs ±10 V or 0 to 20 mA / 4 to 20 mA 1)
General information
B&R ID code 0x1BA3
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Channel type Yes, using software
Power consumption
Bus 0.01 W
Internal I/O 1.8 W (Rev. ≥ J0); 2.2 W (Rev. < J0)
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Analog outputs
Output ±10 V or 0 to 20 mA / 4 to 20 mA, via different terminal connections 1)
Max. output current 10 mA at voltages >5 V
15 mA at voltages <5 V
Digital converter resolution
Voltage ±12-bit
Current 12 Bit
Conversion time 300 µs for all outputs
Settling time for output changes over entire range 500 µs
Power on/off behavior Internal enable relay for booting

Table 100: X20AO4622 - Technical data

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Product ID X20AO4622
Max. error at 25°C
Voltage
Gain 0.080% 2)
Offset 0.050% 3)
Current
Gain 0.090% 2)
Offset 0.050% 3)
Output protection Short circuit protection
Output format
Voltage INT 0x8001 - 0x7FFF / 1 LSB = 0x0010 = 4.882 mV
Current INT 0x8001 - 0x7FFF / 1 LSB = 0x0010 = 9.766 µA
Load per channel
Voltage Max. ±10 mA, load ≥1 kΩ
Current Load max. 600 Ω (Rev. ≥ J0); 500 Ω (Rev. < J0)
Short circuit protection Current limiting ±40 mA
Output filter 1st-order low pass / cutoff frequency 10 kHz
Max. gain drift
Voltage 0.015 %/°C 2)
Current 0.020 %/°C 2)
Max. offset drift
Voltage 0.032 %/°C 3)
Current 0.032 %/°C 3)
Error caused by load change
Voltage Max. 0.11%, from 10 MΩ → 1 kΩ, resistive
Current Max. 0.50%, from 1 Ω → 600 Ω, resistive
Non-linearity <0.005% 4)
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C (Rev. ≥ J0); 0 to 55°C (Rev. < J0)
Vertical installation -25 to 50°C (Rev. ≥ J0); 0 to 50°C (Rev. < J0)
Derating See section "Module operation"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 100: X20AO4622 - Technical data

1) 4 to 20 mA: From upgrade version 1.0.2.0 or hardware revision "I0"
2) Based on the current output value.
3) Based on the entire output range.
4) Based on the output range.

4.4.7.4 LED status indicators

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
e+r Red on / Green single flash Invalid firmware
1-4 Orange Off Value = 0
On Value ≠ 0

1) Depending on the configuration, a firmware update can take up to several minutes.

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4.4.7.5 Pinout

Each channel can be configured for either current or voltage signals. The type of signal is also determined by the
connection terminals used.

r e

X20 AO 4622
1 2
3 4

AO + 1 I AO + 2 I

AO + 1 U AO + 2 U

AO - 1 U/I AO - 2 U/I

AO + 3 I AO + 4 I

AO + 3 U AO + 4 U

AO - 3 U/I AO - 4 U/I

4.4.7.6 Connection example

AO

Voltage Current
Load

+
Load

Load

+
Load

+24 VDC +24 VDC

GND GND

4.4.7.7 Output circuit diagram

AO + x I

Reset

Output value D/A

converter SSR

I/O status
AO + x U

LED (orange) AO - x U/I

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4.4.7.8 Module operation

To ensure proper operation, the following items must be taken into consideration:
• The following derating listings must be taken into consideration
• For mixed operation with one current output, the average of both derating curves should be used
• For mixed operation with two or three current outputs, the derating for the current outputs should be used

Horizontal installation
From revision J0 Before revision J0
Voltage output Voltage output

10 10

8 8

Load [kΩ]
6 6
Load [kΩ]

Prohibited Prohibited
range range
4 4

2 2
1 1
-20 -10 20 30 40 50 60 0 10 20 30 40 50

Ambient temperature [°C] Ambient temperature [°C]

Current output Current output

600 500

500 400
Working resistance [Ω]
Working resistance [Ω]

400 300
Prohibited
Prohibited range
300 200
range

200 100

100 0
0 10 20 30 40 50
0 Ambient temperature [°C]
-20 -10 20 30 40 50 60

Ambient temperature [°C]

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Vertical installation
From revision J0 Before revision J0
Voltage output Voltage output

10 10

8 8

Load [kΩ]
6 Prohibited 6 Prohibited
Load [kΩ]

range range
4 4

2 2
1 1
-20 -10 20 30 40 50 60 0 10 20 30 40 50

Ambient temperature [°C] Ambient temperature [°C]

Current output Current output

600 500

500 400

Working resistance [Ω]

Working resistance [Ω]

400 300
Prohibited
Prohibited range
300 200
range

200 100

100 0
0 10 20 30 40 50
0
Ambient temperature [°C]
-20 -10 20 30 40 50 60

Ambient temperature [°C]

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4.4.7.9 Register description

4.4.7.9.1 Function model 0 - Standard

and function model 1 - I/O with fast reaction

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
18 ConfigOutput01 USINT ●
Analog signal - Communication
0 AnalogOutput01 INT ●
2 AnalogOutput02 INT ●
4 AnalogOutput03 INT ●
6 AnalogOutput04 INT ●

4.4.7.9.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
18 - ConfigOutput01 USINT ●
Analog signal - Communication
0 0 AnalogOutput01 INT ●
2 2 AnalogOutput02 INT ●
4 4 AnalogOutput03 INT ●
6 6 AnalogOutput04 INT ●

1) The offset specifies the position of the register within the CAN object.

4.4.7.9.3 Function model comparison

Function model 0: I/O without jitter (standard)

Corrected values are output in the next cycle if the minimum cycle is ≥400 μs in order to reduce jitter to a minimum.
Function model 1: I/O with fast reaction
Corrected values are output in the same cycle if the minimum cycle is ≥400 μs (optimized reactions).
Comparison of the two function models
Function model 0: I/O without jitter

Value transfer Internal processing time of the I/O module

0 1 2 3 4 5

X2X

I/O
0 1 2 3 4 5
Values output in the next cycle

Function model 1: I/O with fast reaction

Value transfer
0 1 2 3 4 5

X2X

I/O
0 1 2 3 4 5
Values output in the same cycle

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4.4.7.9.4 Analog outputs

Each channel can be configured for either current or voltage signals. The type of signal is also determined by the
connection terminals used.

4.4.7.9.4.1 Output values of the analog output

Name:
AnalogOutput01 to AnalogOutput04
These registers provide the standardized output values. Once a permitted value is received the module outputs
the respective current or voltage.
Data type Value Information
INT -32768 to 32767 Voltage signal -10 to 10 VDC
0 to 32767 Current signal 0 to 20 mA
0 to 32767 Current signal 4 to 20 mA1)

1) From upgrade version 1.0.2.0 or hardware revision "I0"

4.4.7.9.4.2 Setting the channel type

Name:
ConfigOutput01
This register can be used to set the channel type of the outputs.
Each channel is capable of handling either current or voltage signals. The type of signal is determined by the
connection terminals used. Since current and voltage require different adjustment values, it is also necessary to
configure the desired type of output signal. The following output signals can be set:
• ±10 V voltage signal (default)
• 0 to 20 mA current signal
• 4 to 20 mA current signal
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Channel 1 0 Voltage signal
1 Current signal, measurement range corresponding to bit 4
... ...
3 Channel 4 0 Voltage signal
1 Current signal, measurement range corresponding to bit 7
4 Channel 1: Current measurement range 0 0 to 20 mA current signal
1 4 to 20 mA current signal
... ...
7 Channel 4: Current measurement range 0 0 to 20 mA current signal
1 4 to 20 mA current signal

4.4.7.9.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
250 μs

4.4.7.9.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
400 μs

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4.4.8 X20AO4632

4.4.8.1 General information

The module is equipped with four outputs with 16-bit (including sign) digital converter resolution. It is possible to
select between the current and voltage signal using different connection terminal points.
• 4 analog outputs
• Either current or voltage signal possible
• 16-bit digital converter resolution

4.4.8.2 Order data

Model number Short description Figure

Analog output modules
X20AO4632 X20 analog output module, 4 outputs, ±10 V / 0 to 20 mA, 16-
bit resolution
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 101: X20AO4632 - Order data

4.4.8.3 Technical data

Product ID X20AO4632
Short description
I/O module 4 analog outputs, ±10 V or 0 to 20 mA
General information
B&R ID code 0x1BA5
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Channel type Yes, using software
Power consumption
Bus 0.01 W
Internal I/O 1.8 W (Rev. ≥ J0); 2.2 W (Rev. < J0)
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Analog outputs
Output ±10 V or 0 to 20 mA, via different terminal connections
Digital converter resolution
Voltage ±15-bit
Current 15 Bit
Conversion time 50 µs for all outputs
Settling time for output changes over entire range 500 µs
Power on/off behavior Internal enable relay for booting

Table 102: X20AO4632 - Technical data

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Product ID X20AO4632
Max. error at 25°C
Voltage
Gain 0.040% 1)
Offset 0.022% 2)
Current
Gain 0.090% 1)
Offset 0.045% 2)
Output protection Short circuit protection
Output format
Voltage INT 0x8001 - 0x7FFF / 1 LSB = 0x0001 = 305.176 µV
Current INT 0x0000 - 0x7FFF / 1 LSB = 0x0001 = 610.352 nA
Load per channel
Voltage Max. ±10 mA, load ≥1 kΩ
Current Load max. 600 Ω (Rev. ≥ J0); 500 Ω (Rev. < J0)
Short circuit protection Current limiting ±40 mA
Output filter 1st-order low pass / cutoff frequency 10 kHz
Max. gain drift
Voltage 0.010 %/°C 1)
Current 0.020 %/°C 1)
Max. offset drift
Voltage 0.012 %/°C 2)
Current 0.012 %/°C 2)
Error caused by load change
Voltage Max. 0.11%, from 10 MΩ → 1 kΩ, resistive
Current Max. 0.50%, from 1 Ω → 600 Ω, resistive
Non-linearity <0.005% 3)
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C (Rev. ≥ J0); 0 to 55°C (Rev. < J0)
Vertical installation -25 to 50°C (Rev. ≥ J0); 0 to 50°C (Rev. < J0)
Derating See section "Module operation"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 102: X20AO4632 - Technical data

1) Based on the current output value.
2) Based on the entire output range.
3) Based on the output range.

4.4.8.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
1-4 Orange Off Value = 0
On Value ≠ 0

Table 103: LED status indicators

1) Depending on the configuration, a firmware update can take up to several minutes.

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4.4.8.5 Pinout

Each channel can be configured for either current or voltage signals. The type of signal is also determined by the
connection terminals used.

r e

X20 AO 4632
1 2
3 4

AO + 1 I AO+ 2 I

AO+ 1 U AO+ 2 U

AO- 1 U/I AO - 2 U/I

AO + 3 I AO + 4 I

AO + 3 U AO + 4 U

AO - 3 U/I AO - 4 U/I

Figure 190: Pinout

4.4.8.6 Connection example

AO

Voltage Current
Load

+
Load

Load

+
Load

+24 VDC +24 VDC

GND GND

4.4.8.7 Output circuit diagram

AO + x I

Reset

Output value D/A

converter SSR

I/O status
AO + x U

LED (orange) AO - x U/I

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4.4.8.8 Module operation

To ensure proper operation, the following items must be taken into consideration:
• The following derating listings must be taken into consideration
• For mixed operation with one current output, the average of both derating curves should be used
• For mixed operation with two or three current outputs, the derating for the current outputs should be used

Horizontal installation
From revision J0 Before revision J0
Voltage output Voltage output

10 10

8 8

Load [kΩ]
6 6
Load [kΩ]

Prohibited Prohibited
range range
4 4

2 2
1 1
-20 -10 20 30 40 50 60 0 10 20 30 40 50

Ambient temperature [°C] Ambient temperature [°C]

Current output Current output

600 500

500 400
Working resistance [Ω]
Working resistance [Ω]

400 300
Prohibited
Prohibited range
300 200
range

200 100

100 0
0 10 20 30 40 50
0 Ambient temperature [°C]
-20 -10 20 30 40 50 60

Ambient temperature [°C]

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Vertical installation
From revision J0 Before revision J0
Voltage output Voltage output

10 10

8 8

Load [kΩ]
6 Prohibited 6 Prohibited
Load [kΩ]

range range
4 4

2 2
1 1
-20 -10 20 30 40 50 60 0 10 20 30 40 50

Ambient temperature [°C] Ambient temperature [°C]

Current output Current output

600 500

500 400

Working resistance [Ω]

Working resistance [Ω]

400 300
Prohibited
Prohibited range
300 200
range

200 100

100 0
0 10 20 30 40 50
0
Ambient temperature [°C]
-20 -10 20 30 40 50 60

Ambient temperature [°C]

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4.4.8.9 Register description

4.4.8.9.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
0 ConfigOutput01 UINT ●
Analog signal - Communication
Index * 2 AnalogOutput0N (Index N = 1 to 4) INT ●
10 + Index * 4 AnalogOutputDelayed0N (Index N = 0 to 3) INT ●
12 OutputDelayConfig00 UINT ●
18 OutputDelayConfig01 UINT ●
14 AnalogOutputLatchTime00 UINT ●
22 AnalogOutputLatchTime01 UINT ●
20 Error UINT ●

4.4.8.9.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog signal - Configuration
0 - ConfigOutput01 UINT ●
Analog signal - Communication
10 + Index * 4 Index * 2 - 2 AnalogOutput0N (Index N = 1 to 4) INT ●

1) The offset specifies the position of the register within the CAN object.

4.4.8.9.3 Analog output - Configuration

4.4.8.9.3.1 Setting the channel type

Name:
ConfigOutput01
This register can be used to set the channel type of the outputs.
Each channel is capable of handling either current or voltage signals. The type of signal is determined by the
connection terminals used. Since current and voltage require different adjustment values, it is also necessary to
configure the desired type of output signal. The following output signals can be set:
• ±10 V voltage signal (default)
• 0 to 20 mA current signal
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-7 Reserved 0
8 Channel 1 0 Voltage signal
1 Current signal
... ...
11 Channel 4 0 Voltage signal
1 Current signal
12 - 15 Reserved 0

4.4.8.9.4 Analog output - Configuration

4.4.8.9.4.1 Output values of the analog outputs

Name:
AnalogOutput01 to AnalogOutput04
These registers provide the standardized output values. Once a permitted value is received, the module outputs
the respective current or voltage.

Information:
The value "0" disables the channel status LED.
Data type Value
INT -32767 to 32767 Voltage; Bus controller default setting: 0
0 to 32767 Current

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4.4.8.9.4.2 Value for delayed output

Name:
AnalogOutputDelayed00 to AnalogOutputDelayed03
These registers contain the values with which the analog outputs are overwritten after the delay configured with
OutputDelayConfig0x has expired.
Data type Value Output Signal
INT -32768 to 32767 Voltage signal -10 VDC to 10 VDC
0 to 32767 Current signal 0 mA to 20 mA

4.4.8.9.4.3 Configuration of the output delay

Name:
OutputDelayConfig00 to OutputDelayConfig01
Two configurations independent from each other can be created using these registers.
The delay time after which AnalogOutputDelay0x should overwrite the channel can be configured using bits 0 to
13. Using bits 14 and 15, the channel is determined for which the configuration is valid.
Each channel can only be overwritten once. No additional channel can be overwritten while the respective time
is running.
Data type Value
UINT See bit structure.

Bit structure:
Bit Description Value Information
0 - 13 Delay time for the selected channel x Time in μs
14 - 15 Channel 00 Analog output 01
01 Analog output 02
10 Analog output 03
11 Analog output 04

4.4.8.9.4.4 Delay time for the output value

Name:
AnalogOutputLatchTime00 to AnalogOutputLatchTime01
These registers can be used to read when the respective overwrite value was actually written on the output.
Data type Value
UINT Actual delay time

4.4.8.9.4.5 Error register for counter

Name:
Error
There are some limitations because two timers are used. This register is available to the user for reporting these
potential errors.
The error bits are deleted as soon as a valid state is reset.
Data type Value
UINT See bit structure.

Bit structure:
Bit Description Value Information
0 Analog output 01 0 OK
1 Has already been overwritten
... ...
3 Analog output 04 0 OK
1 Has already been overwritten
4 Timer 01 0 OK
1 Already in use
5 Timer 02 0 OK
1 Already in use
6 Timer 01 and 02 0 OK
1 Both timers refer to the same channel number
7 - 15 Reserved

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4.4.8.9.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
200 µs

4.4.8.9.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
200 µs

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4.4.9 X20AO4632-1

4.4.9.1 General information

The module is equipped with four outputs with 16-bit (including sign) digital converter resolution. It is possible to
select between the current and voltage signal using different connection terminal points.
• 4 analog outputs
• Either current or voltage signal possible
• Extended signal range
• 16-bit digital converter resolution

4.4.9.2 Order data

Model number Short description Figure

Analog output modules
X20AO4632-1 X20 analog output module, 4 outputs, ±11 V / 0 to 22 mA, 16-
bit resolution
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 104: X20AO4632-1 - Order data

4.4.9.3 Technical data

Product ID X20AO4632-1
Short description
I/O module 4 analog outputs, ±11 V or 0 to 22 mA
General information
B&R ID code 0xC36F
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Channel type Yes, using software
Power consumption
Bus 0.01 W
I/O internal 2.15 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
GOST-R Yes
Analog outputs
Output ±11 V or 0 to 22 mA, via different terminal connections
Digital converter resolution
Voltage ±15-bit
Flow 15-bit
Conversion time 50 µs for all outputs
Settling time for output changes over entire range 500 µs
Power on/off behavior Internal enable relay for booting
Max. error at 25°C
Voltage
Gain 0.050% 1)
Offset 0.015% 2)
Flow
Gain 0.080% 1)
Offset 0.050% 2)
Output protection Short circuit protection

Table 105: X20AO4632-1 - Technical data

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Product ID X20AO4632-1
Output format
Voltage INT 0x8000 - 0x7FFF / 1 LSB = 0x0001 = 335.693 µV
Flow INT 0x0000 - 0x7FFF / 1 LSB = 0x0001 = 671.386 nA
Load per channel
Voltage Max. ±11 mA, load ≥1 kΩ
Flow Max. load is 600 Ω
Short circuit proof Current limiting ±40 mA
Output filter 1st-order low pass / cutoff frequency 10 kHz
Max. gain drift
Voltage 0.008 %/°C 1)
Flow 0.011 %/°C 1)
Max. offset drift
Voltage 0.003 %/°C 2)
Flow 0.008 %/°C 2)
Error caused by load change
Voltage Max. 0.10%, from 10 MΩ → 1 kΩ, resistive
Flow Max. 0.50%, from 1 Ω → 600 Ω, resistive
Non-linearity <0.007% 3)
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Module operation"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 105: X20AO4632-1 - Technical data

1) Based on the current output value.
2) Based on the entire output range.
3) Based on the output range.

4.4.9.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
1-4 Orange Off Value = 0
On Value ≠ 0

Table 106: LED status indicators

1) Depending on the configuration, a firmware update can take up to several minutes.

4.4.9.5 Pinout

Each channel can be configured for either current or voltage signals. The type of signal is also determined by the
connection terminals used.

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r e

X20 AO 4632-1
1 2
3 4

AO + 1 I AO + 2 I

AO + 1 U AO + 2 U

AO - 1 U/I AO - 2 U/I

AO + 3 I AO + 4 I

AO + 3 U AO + 4 U

AO - 3 U/I AO - 4 U/I

Figure 191: Pinout

4.4.9.6 Connection example

AO

Voltage Current

Load
+
Load

Load

+
Load

+24 VDC +24 VDC

GND GND

4.4.9.7 Output circuit diagram

AO + x I

Reset

Output value D/A

converter SSR

I/O status
AO + x U

LED (orange) AO - x U/I

4.4.9.8 Module operation

To ensure proper operation, the following items must be taken into consideration:
• The following derating listings must be taken into consideration
• For mixed operation with one current output, the average of both derating curves should be used
• For mixed operation with two or three current outputs, the derating for the current outputs should be used
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Horizontal installation
Voltage output

Horizontal installation
10

Load [k Ω] 6 Prohibited
Range
4

2
1
-20 -10 0 10 20 30 40 50

Ambient temperature [°C]

Figure 192: Derating the load with a voltage output and horizontal mounting

Current output

Horizontal installation
600

500
Working resistance [ Ω]

400

Prohibited
300
Range

200

100

0
-20 -10 0 10 20 30 40 50

Ambient temperature [°C]

Figure 193: Derating the load with a current output and horizontal mounting

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Vertical installation
Voltage output

Vertical installation
10

Load [k Ω ] 6 Prohibited
Range
4

2
1
-20 -10 0 10 20 30 40 50

Ambient temperature [°C]

Figure 194: Derating the load with a voltage output and vertical mounting

Current output

Vertical installation
600

500
Working resistance [Ω]

400

Prohibited
300
Range

200

100

0
-20 -10 0 10 20 30 40 50

Ambient temperature [°C]

Figure 195: Derating the load with a current output and vertical mounting

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4.4.9.9 Register description

4.4.9.9.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog output - Configuration
0 ConfigOutput01 UINT ●
590 + Index*4 Cfo_Channel0NTimeMode (Index N = 1 to 4) UINT ●
Analog output - Communication
Index * 2 AnalogOutput0N (Index N = 1 to 4) INT ●
457 SDCLifeCount SINT ●
794 + Index*8 ValidationTimer0N (Index N = 1 to 4) INT ●
796 + Index*8 ValidationTimer0N (Index N = 1 to 4) DINT ●
833 Enabling/disabling the output channels USINT ● ●
AnalogOutput01Enable, ~Readback Bit 0
... ...
AnalogOutput04Enable, ~Readback Bit 3
835 Checking the output values USINT ●
AnalogOutput01OK Bit 0
... ...
AnalogOutput04OK Bit 3

4.4.9.9.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Analog output - Configuration
0 - ConfigOutput01 UINT ●
Analog output - Communication
10 + Index * 4 Index * 2 - 2 AnalogOutput0N (Index N = 1 to 4) INT ●

1) The offset specifies the position of the register within the CAN object.

4.4.9.9.3 General information

The module provides four analog outputs. Each channel can output a voltage range of ±11 V or a current range
of 0 to 22 mA.
The module also has a time-based watchdog monitor. The user can activate this feature on a channel-by-channel
basis as needed.

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4.4.9.9.4 Analog output - Configuration

Each channel is configured independently. The user can also define an optional time-based monitor. To make this
possible, four watchdog timers were implemented, which can be assigned to the outputs.

4.4.9.9.4.1 Setting the channel type

Name:
ConfigOutput01
This register can be used to set the channel type of the outputs.
Each channel is capable of handling either current or voltage signals. The type of signal is determined by the
connection terminals used. Since current and voltage require different adjustment values, it is also necessary to
configure the desired type of output signal. The following output signals can be set:
• ±11 V voltage signal (default)
• 0 to 22 mA current signal
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-7 Reserved 0
8 Channel 1 0 Voltage signal
1 Current signal
... ...
11 Channel 4 0 Voltage signal
1 Current signal
12 - 15 Reserved 0

4.4.9.9.4.2 Configuring the time-based watchdog monitor

Name:
Cfo_Channel01TimeMode to Cfo_Channel04TimeMode
This register is used to activate or configure the time-based watchdog monitor for the analog output channels.
Possibilities per channel:
• Validation timer data type: General choice 16 or 32 bit
• Validation window: The maximum value can be further limited within the data type.
• Timer allocation: A separate timer is available for each channel. However, all channels can be configured
with the same validation timer, whereby the same settings must be made for the data type and window
in the TimeMode registers.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-4 Max. validation time 00000 Disabled
00001 2 µs
00010 4 µs
00011 8 µs
... ...
11111 2,147,483,648 µs (~35 min)
5-7 Reserved 0
8-9 Timer allocation 00 ValidationTimer01 (default for channel 1)
01 ValidationTimer02 (default for channel 2)
10 ValidationTimer03 (default for channel 3)
11 ValidationTimer04 (default for channel 4)
10 - 14 Reserved 0
15 Time format 0 16-bit
1 32-bit

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4.4.9.9.5 Analog output - Communication

In standard mode, the module's outputs are enabled. Based on the configuration and AnalogOutput value, they
output the corresponding current or voltage.
If the application requires time-based monitoring of the outputs, then a validation timer can be assigned to each
channel. The validation timer register assigns a validity duration to the current output value. When validation is
enabled, the module compares the validation time with the Nettime of the X2X Link. If the transferred validity
duration is exceeded, the module disables the channel and resets the output. The "safety shutdown" state will not
be reset until a new and valid validation time has been transferred. If enabled, the module reports which state it
is currently in via the channel's error status bit.
If the value of the validation timer is incremented in each task cycle, the valid validation time will be calculated
as follows:
Nettime of the X2X Link master (which the module is connected to)
+ Timespan for transferring data from the X2X Link master to the CPU (higher-level system)
+ Cycle time of task class (including tolerance)
+ Timespan for transferring the data from the CPU to the module
+ Timespan allowed by the application (e.g. for tolerating failure of an X2X Link cycle)
= Valid validation time

The AnalogOutputEnableByte is enabled during time-based monitoring. If the timer expires prematurely, the corre-
sponding bit in the AnalogOutputOkayByte is reset and the output drops out. This provides an easy way to achieve
a defined state.

4.4.9.9.5.1 Output values of the analog outputs

Name:
AnalogOutput01 to AnalogOutput04
These registers provide the standardized output values. Once a permitted value is received, the module outputs
the respective current or voltage.

Information:
The value "0" disables the channel status LED.
Data type Value
INT -32767 to 32767 Voltage; Bus controller default setting: 0
0 to 32767 Current

4.4.9.9.5.2 SDC counter register

Name:
SDCLifeCount
The 8-bit counter register is needed for the SDC software package. It is incremented with the system clock to allow
the SDC to check the validity of the data frame.
Data type Value
SINT -128 to 127

4.4.9.9.5.3 Transfer of the timestamp

Name:
ValidationTimer01 to ValidationTimer04
When an output is being monitored, these registers must provide the timestamp which, when reached, will cause
the output to shut down automatically. The values must be provided as signed 2-byte or 4-byte values.
Data type Values [µs]
INT -32768 to 32767 Nettime timestamp of the current output value
DINT -2,147,483,648 Nettime timestamp of the current output value
to 2,147,483,647

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4.4.9.9.5.4 Enabling/disabling the output channels

Name:
AnalogOutput01Enable to AnalogOutput04Enable
AnalogOutput01EnableReadback to AnalogOutput04EnableReadback
The "OutputEnable" byte is only needed for the channels with activated time-based monitoring. The individual bits
are used to enable/disable the respective channels. To receive reliable feedback about the current state of the
module, the byte was also implemented so that it can be read cyclically.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Value Information
0 AnalogOutput01Enable 0 Output deactivated
AnalogOutput01EnableReadback 1 Output activated
... ...
3 AnalogOutput04Enable 0 Output deactivated
AnalogOutput04EnableReadback 1 Output activated
4-7 Reserved 0

4.4.9.9.5.5 Checking the output values

Name:
AnalogOutput01OK to AnalogOutput04OK
These registers are only needed for channels with activated time-based monitoring. The individual bits report
whether the respective channel is actually generating the required voltage or current.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Value Information
0 AnalogOutput01OK 0 Electrical signal deactivated
1 Electrical signal activated
... ...
3 AnalogOutput04OK 0 Electrical signal deactivated
1 Electrical signal activated
4-7 Reserved 0

4.4.9.9.6 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
200 µs

4.4.9.9.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
200 µs

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4.4.10 X20AO4635

4.4.10.1 General information

The module is equipped with four outputs with 16-bit (including sign) digital converter resolution. It is possible to
select between the current and voltage signal using different connection terminal points.
• 4 analog outputs
• Either current or voltage signal possible
• 16-bit digital converter resolution
• Low temperature drift

4.4.10.2 Order data

Model number Short description Figure

Analog output modules
X20AO4635 X20 analog output module, 4 outputs, ±10 V / 0 to 20 mA, 16-
bit resolution low temperature drift
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 107: X20AO4635 - Order data

4.4.10.3 Technical data

Product ID X20AO4635
Short description
I/O module 4 analog outputs, ±10 V or 0 to 20 mA, low temperature drift
General information
B&R ID code 0xA7FE
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Channel type Yes, using software
Power consumption
Bus 0.01 W
Internal I/O 1.5 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Analog outputs
Output ±10 V or 0 to 20 mA, via different connection terminal points
Digital converter resolution
Voltage ±15-bit
Current 15-bit
Conversion time 50 µs for all outputs
Settling time for output changes over entire range 500 µs
Power on/off behavior Internal enable relay for booting
Max. error at 25°C
Gain 0.040% 1)
Offset 0.022% 2)

Table 108: X20AO4635 - Technical data

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Product ID X20AO4635
Output protection Short circuit protection
Output format
Voltage INT 0x8000 - 0x7FFF / 1 LSB = 0x0001 = 305.176 µV
Current INT 0x0000 - 0x7FFF / 1 LSB = 0x0001 = 610.352 nA
Load per channel
Voltage Max. ±10 mA, load ≥ 1kΩ
Current Max. load is 500 Ω
Short circuit protection Current limiting ±40 mA
Output filter 1st-order low pass / cut-off frequency 10 kHz
Error caused by load change
Voltage Max. 0.02%, from 10 MΩ → 1 kΩ, resistive
Current Max. 0.5%, from 1 Ω → 500 Ω, resistive
Non-linearity <0.005%
Isolation voltage between channel and bus 500 Veff
Signal
0 to 20 mA
Max. gain drift 0.01 %/°C 1)
Max. offset drift 0.012 %/°C 2)
±10 V
Max. gain drift 0.0025 %/°C 1)
Max. offset drift 0.001 %/°C 2)
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 55°C
Vertical installation -25 to 50°C
Derating See section "Module operation"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 108: X20AO4635 - Technical data

1) Based on the current output value.
2) Based on the entire output range.

4.4.10.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
1-4 Orange Off Value = 0
On Value ≠ 0

Table 109: LED status indicators

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4.4.10.5 Pinout

Each channel can be configured for either current or voltage signals. The type of signal is also determined by the
connection terminals used.

r e

X20 AO 4635
1 2
3 4

AO + 1 I AO + 2 I

AO + 1 U AO + 2 U

AO - 1 U/I AO - 2 U/I

AO + 3 I AO + 4 I

AO + 3 U AO + 4 U

AO - 3 U/I AO - 4 U/I

Figure 196: Pinout

4.4.10.6 Connection example

AO

Voltage Current
Load

+
Load

Load

+
Load

+24 VDC +24 VDC

GND GND

4.4.10.7 Output circuit diagram

AO + x I

Output value
D/A
Conversion Enable relay AO + x U
I/O status

AO - x U/I

LED (orange)
Reset

Figure 197: Output circuit diagram

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4.4.10.8 Module operation

To ensure proper operation, the following items must be taken into consideration:
• The following derating listings must be taken into consideration
• For mixed operation with one current output, the average of both derating curves should be used
• For mixed operation with two or three current outputs, the derating for the current outputs should be used

Horizontal installation
Voltage output

Horizontal installation
10

8
Load [k Ω]

6 Prohibited
Range
4

2
1
-20 -10 0 10 20 30 40 50

Ambient temperature [°C]

Figure 198: Derating the load with a voltage output and horizontal mounting
Current output

Horizontal installation
500

400

Prohibited
300
Load [Ω]

Range

200

100

0
-20 -10 0 10 20 30 40 50

Ambient temperature [°C]

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Vertical installation
Voltage output

Vertical installation
10

Load [k Ω ] 6 Prohibited
Range
4

2
1
-20 -10 0 10 20 30 40 50

Ambient temperature [°C]

Figure 199: Derating the load with a voltage output and vertical mounting
Current output

Vertical installation
500

400

Prohibited
300
Load [Ω]

Range

200

100

0
-20 -10 0 10 20 30 40 50

Ambient temperature [°C]

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4.4.10.9 Register description

4.4.10.9.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Configuration
0 ConfigOutput01 UINT ●
Communication
2 AnalogOutput01 INT ●
4 AnalogOutput02 INT ●
6 AnalogOutput03 INT ●
8 AnalogOutput04 INT ●

4.4.10.9.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Configuration
0 - ConfigOutput01 UINT ●
Communication
2 0 AnalogOutput01 INT ●
4 2 AnalogOutput02 INT ●
6 4 AnalogOutput03 INT ●
8 6 AnalogOutput04 INT ●

1) The offset specifies the position of the register within the CAN object.

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4.4.10.9.3 Analog outputs

Each channel can be configured for either current or voltage signals. The type of signal is also determined by the
connection terminals used.

4.4.10.9.3.1 Output values of the analog outputs

Name:
AnalogOutput01 to AnalogOutput04
These registers provide the standardized output values. Once a permitted value is received, the module outputs
the respective current or voltage.

Information:
The value "0" disables the channel status LED.
Data type Value
INT -32767 to 32767 Voltage; Bus controller default setting: 0
0 to 32767 Current

4.4.10.9.3.2 Setting the channel type

Name:
ConfigOutput01
This register can be used to set the channel type of the outputs.
Each channel is capable of handling either current or voltage signals. The type of signal is determined by the
connection terminals used. Since current and voltage require different adjustment values, it is also necessary to
configure the desired type of output signal. The following output signals can be set:
• ±10 V voltage signal (default)
• 0 to 20 mA current signal
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-7 Reserved 0
8 Channel 1 0 Voltage signal
1 Current signal
... ...
11 Channel 4 0 Voltage signal
1 Current signal
12 - 15 Reserved 0

4.4.10.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
200 µs

4.4.10.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
200 µs

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4.5 Bus controllers

The bus controllers adhere to the completely modular strategy used for the I/O modules. Made up of a base
module, a supply module to supply the voltage for the entire system, and a fieldbus interface, the bus controller
is an extremely flexible fieldbus connection.
Bus controller base
X20 BB 80

Bus controller supply module

X20 PS 940x

Bus controller fieldbus interface

X20 BC 00xx

Terminal block
X20 TB 12

Figure 200: The four parts of a bus controller - fieldbus interface, base module, supply module, terminal block
The entire backplane can be preinstalled. With the removable terminals, the entire system can be wired separately
from the electronics module. The individual modules are put in place during commissioning. This is where the I/
O system is adapted to the fieldbus being used.
Unlike the Compact CPU with integrated fieldbus connection, the bus controller does not need to be programmed
in order to transfer or receive the I/O data on the fieldbus. It can be configured on the fieldbus master.

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4.5.1 Brief information

Product ID Short description on page
X20BC0043 X20 bus controller, CANopen interface, order 1x TB2105 terminal block separately. Order bus base, power 507
supply module and terminal block separately.
X20BC0043-10 X20 bus controller, CANopen interface, configuration supported by the B&R FieldbusDESIGNER, order 1x 514
TB2105 terminal block separately. Order bus base, power supply module and terminal block separately.
X20BC0053 X20 bus controller, DeviceNet interface, order 1x TB2105 terminal block separately. Order bus base, power 521
supply module and terminal block separately.
X20BC0063 X20 bus controller, PROFIBUS DP interface, 9-pin DSUB connection, order bus base, power supply module 527
and terminal block separately.
X20BC0073 X20 bus controller, CAN I/O interface, order 1x TB2105 terminal block separately. Order bus base, power supply 532
module and terminal block separately.
X20BC0083 X20 bus controller, POWERLINK interface, integrated 2x hub, 2x RJ45 connection, order bus base, power 537
supply module and terminal block separately.
X20BC0087 X20 bus controller, Modbus/TCP or Modbus/UDP interface, integrated 2x switch, 2x RJ45 connection, order 542
bus base, power supply module and terminal block separately.
X20BC0088 X20 bus controller, EtherNet/IP interface, integrated switch, web interface 2x RJ45 connection, order bus base, 547
power supply module and terminal block separately.
X20BC00E3 X20 bus controller, PROFINET interface, integrated 2x switch, 2x RJ45 connection, order bus base, power 552
supply module and terminal block separately.
X20BC00G3 X20 bus controller, EtherCAT interface, 2x RJ45 connection, order bus base, power supply module and terminal 558
block separately.
X20BC0143-10 X20 bus controller, CANopen interface, 9-pin DSUB, configuration supported by the B&R FieldbusDESIGNER, 562
order 1x 7AC911.9 connector separately. Order bus base, power supply module and terminal block separately.

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4.5.2 X20BC0043

4.5.2.1 General information

CAN (Controller Area Network) systems are widespread in the field of automation technology. CAN topology is
based on a line structure and uses twisted pair wires for data transfer. CANopen is a higher-layer protocol based
on CAN. This standardized protocol offers highly flexible configuration possibilities.
The bus controller makes it possible to connect up to 253 X2X Link I/O nodes to CANopen. A transition between
IP20 and IP67 protection outside of the control cabinet is possible by aligning X20, X67 or XV modules one after
the other as needed at distances up to 100 m. All CANopen transmission types such as synchronous, event and
polling modes are supported together with PDO linking, life/node guarding, emergency objects, and much more.
• Fieldbus: CANopen
• I/O configuration via the fieldbus
• 20 receiver PDOs and 20 sender PDOs
• Select between entry of a fixed transfer rate or automatic transfer rate detection.
• Integrated terminating resistor

Information:
Only the standard function model (see the respective module description) is supported when the bus
controller is used together with multi-function modules it has automatically configured itself.
The B&R FieldbusDESIGNER can be used to create configuration files (e.g. DCF files) in six easy steps.
All other function models are also supported by transferring configuration data to the bus controller
(e.g. from the master environment with an SDO download or via the serial interface).
The B&R FieldbusDESIGNER is available free of charge in the download section of the B&R website
www.br-automation.com.

4.5.2.2 Order data

Model number Short description Figure

Bus controllers
X20BC0043 X20 bus controller, CANopen interface, order 1x TB2105 termi-
nal block separately. Order bus base, power supply module and
terminal block separately.
Required accessories
System modules for bus controllers
X20BB80 X20 bus base, for X20 base module (BC, HB, etc.) and X20 pow-
er supply module, X20 end plates X20AC0SL1/X20AC0SR1 (left
and right) included
X20PS9400 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply
X20PS9402 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply, supply not electrically isolated
Terminal blocks
0TB2105.9010 Accessory terminal block, 5-pin, screw clamp 2.5 mm²
0TB2105.9110 Accessory terminal block, 5-pin, cage clamp 2.5 mm²
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 110: X20BC0043 - Order data

4.5.2.3 Technical data

Product ID X20BC0043
Short description
Bus controller CANopen slave
General information
B&R ID code 0x1F1A
Status indicators Module status, bus function, data transfer, terminating resistor
Diagnostics
Module status Yes, with status LED and software status
Bus function Yes, with status LED
Data transfer Yes, with status LED
Terminating resistor Yes, with status LED
Power consumption
Bus 1.5 W

Table 111: X20BC0043 - Technical data

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Product ID X20BC0043
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Fieldbus - X2X Link No
Fieldbus - I/O Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Interfaces
Fieldbus CANopen slave
Design 5-pin male multipoint connector
Max. distance 1000 m
Transfer rate Max. 1 Mbit/s
Determination of transfer rate Automatic transfer rate detection or fixed rate setting
Terminating resistor Integrated in the module
Min. cycle time 1)
Fieldbus No limitations
X2X Link 400 μs
Synchronization between bus systems possible No
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation 0 to 55°C
Vertical installation 0 to 50°C
Derating -
Storage -25 to 70°C
Transport -25 to 70°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x TB2105 terminal block separately
Order 1x X20TB12 terminal block separately
Order 1x X20PS9400 or X20PS9402 power supply module separately
Order 1x X20BB80 bus base separately
Spacing 2) 37.5 +0.2 mm

Table 111: X20BC0043 - Technical data

1) The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
2) Spacing is based on the width of the X20BB80 bus base. In addition, an X20PS9400 or X20PS9402 supply module is always required for the bus controller.

4.5.2.4 LED status indicators

Figure LED Color Status Description

STATUS1) Green Off No power supply
Blinking PREOPERATIONAL mode
On RUN mode
Single flash STOP mode
Flashing Flash delete in progress
Red Off No power supply or everything is OK
Single flash Bus errors
On Bus errors: Bus is off
Triple flash Transfer rate selection
Long flash Invalid node switch position
Green/red Flickering Transfer rate detection in progress
TxD Yellow Off The bus controller is not transmitting any data via the CANopen fieldbus
On The bus controller is transmitting data via the CANopen fieldbus
TERM Yellow Off The terminating resistor integrated in the bus controller is turned off
On The terminating resistor integrated in the bus controller is turned on

Table 112: LED status indicators

1) The "STATUS" LED is a green/red dual LED.

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Long flash
400 800

Triple flash
200 200 200 200 200 1000

Single flash
200 1000

Blinking
200 200
3
Flashing
500

Green/red
Flickering
50
All times in ms

Figure 201: Status LED - Blinking patterns

4.5.2.5 Operating and connection elements

LED status indicator

Node number switches

Terminal block for bus controller

and I/O supply

CANopen interface

Terminating resistor switch

on the bottom of the module

Figure 202: Operating and connection elements

4.5.2.6 CAN bus interface

The interface is a 5-pin multipoint plug. The 0TB2105 terminal block must be ordered separately.
Interface Pinout
Terminal Function
1
1 CAN⊥ CAN ground
2 CAN_L CAN low
3 SHLD Shield
5 4 CAN_H CAN high
5 NC
5-pin male multipoint connector

Table 113: Pinout

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4.5.2.7 Terminating resistor

Terminating resistor switch

On Off

A terminating resistor is already integrated on the bus controller. It can be turned on and off with a switch on the
bottom of the housing. An active terminating resistor is indicated by the "TERM" LED.

4.5.2.8 Node number and transfer rate

Node numbers and transfer rates are configured using the two bus controller number switches.
The transfer rate can be specified in two ways:
• Automatic detection by bus controller (see 4.5.2.9 "Automatic transfer rate detection" on page 511)
• Fixed definition by user (see 4.5.2.10 "Setting the transfer rate" on page 511)

Switch position Node number Transfer rate

0x00 Not allowed -
0x01 - 0x7F 1 - 127 Automatically set by the bus controller (default) or fixed setting
by the user
0x80 - 0x88 - Sets a fixed transfer rate
0x89 - Sets automatic transfer rate detection
0x8A - 0x8F Not allowed -
0x90 Clearing the parameters -
See section 4.5.2.11 "Deleting parameters" on page 512
0x91 - 0xFF Not allowed -

Table 114: Node numbers and transfer rate

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4.5.2.9 Automatic transfer rate detection

After booting, the bus controller goes into "Listen only" mode. This means the bus controller behaves passively
on the bus and only listens.
The bus controller attempts to receive valid objects. If receive errors occur, the controller switches to the next
transfer rate in the lookup table.
If no objects are received, all transfer rates are tested cyclically. This procedure is repeated until valid objects are
received.
Lookup table
The controller tests the transfer rate according to this table. Beginning with the starting transfer rate (1000 kbit/s),
the controller switches to the next lower transfer rate. At the end of the table, the bus controller restarts the search
from the beginning.
Transfer rate
1000 kbit/s
800 kbit/s
500 kbit/s
250 kbit/s
125 kbit/s
100 kbit/s
50 kbit/s
20 kbit/s
10 kbit/s

Table 115: Transfer rate lookup table

4.5.2.10 Setting the transfer rate

The bus controller will detect the transfer rate automatically by default. Switch positions 0x80 - 0x88 can be used
to set a fixed transfer rate, or 0x89 can be used to enable automatic transfer rate detection.
Switch position Transfer rate
0x80 1000 kbit/s
0x81 800 kbit/s
0x82 500 kbit/s
0x83 250 kbit/s
0x84 125 kbit/s
0x85 100 kbit/s
0x86 50 kbit/s
0x87 20 kbit/s
0x88 10 kbit/s
0x89 Automatic transfer rate detection

Table 116: Possible transfer rates

Programming the transfer rate

1. Turn off the power supply to the bus controller.
2. Define the transfer rate to be programmed by setting the node numbers (0x80 - 0x89)
3. Turn on the power supply to the bus controller.
4. Wait until the "MS" LED blinks with a red triple-flash (transfer rate is now programmed).
5. Turn off the power supply to the bus controller.
6. Set the desired node number (0x01 - 0x7F).
7. Turn on the power supply to the bus controller.
8. The bus controller now boots with the set node number and the programmed transfer rate.

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4.5.2.11 Deleting parameters

Various parameters can be stored in the bus controller's flash memory:

• Communication parameters
• Vendor-specific parameters
• Application parameters (device profile)
• Fixed transfer rate
Deleting these parameters using switch position 0x90 returns the bus controller to its factory settings.

Clearing the parameters listed above

1. Turn off the power supply to the bus controller.
2. Set the node number to 0x90.
3. Turn on the power supply to the bus controller.
4. Wait until the "MS" LED starts blinking green (100 ms on / 200 ms off). The node number switch must be set
to 0x00 and then back to 0x090 within this time window of 5 seconds (rotate the top switch).
5. Wait until the "MS" LED blinks with a red double-flash (parameters have been cleared).
6. Turn off the power supply to the bus controller.
7. Set the desired node number (0x01 - 0x7F)
8. Turn on the power supply to the bus controller.
9. The bus controller boots with the set node number and automatic transfer rate detection.

4.5.2.12 Additional documentation and import files (EDS)

Additional documentation about bus controller functions as well as the necessary import files for the master engi-
neering tool are available in the Downloads section of the B&R website (www.br-automation.com).

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4.5.3 X20BC0043-10

4.5.3.1 General information

CAN (Controller Area Network) systems are widespread in the field of automation technology. CAN topology is
based on a line structure and uses twisted pair wires for data transfer. CANopen is a higher-layer protocol based
on CAN. This standardized protocol offers highly flexible configuration possibilities.
The bus controller makes it possible to connect up to 253 X2X Link I/O nodes to CANopen. A transition between
IP20 and IP67 protection outside of the control cabinet is possible by aligning X20, X67 or XV modules one after
the other as needed at distances up to 100 m. All CANopen transmission types such as synchronous, event and
polling modes are supported together with PDO linking, life/node guarding, emergency objects, and much more.
• Fieldbus: CANopen
• Auto-configuration of I/O modules
• I/O configuration via the fieldbus (also supported by the B&R FieldbusDESIGNER)
• Constant response times even with large amounts of data (max. 32 Rx and 32 Tx PDOs)
• Configurable I/O cycle (0.5 - 4 ms)
• Possible to configure the transfer rate or have it detected automatically
• Heartbeat consumer and producer
• Emergency producer
• 2x SDO server, NMT slave
• Simple bootup (autostart)
• Terminal access via the serial interface on the X20PS9400
• Integrated terminating resistor

Information:
Only the standard function model (see the respective module description) is supported when the bus
controller is used together with multi-function modules it has automatically configured itself.
The B&R FieldbusDESIGNER can be used to create configuration files (e.g. DCF files) in six easy steps.
All other function models are also supported by transferring configuration data to the bus controller
(e.g. from the master environment with an SDO download or via the serial interface).
The B&R FieldbusDESIGNER is available free of charge in the download section of the B&R website
www.br-automation.com.

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4.5.3.2 Order data

Model number Short description Figure

Bus controllers
X20BC0043-10 X20 bus controller, CANopen interface, configuration support-
ed by the B&R FieldbusDESIGNER, order 1x TB2105 terminal
block separately. Order bus base, power supply module and ter-
minal block separately.
Required accessories
System modules for bus controllers
X20BB80 X20 bus base, for X20 base module (BC, HB, etc.) and X20 pow-
er supply module, X20 end plates X20AC0SL1/X20AC0SR1 (left
and right) included
X20PS9400 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply
X20PS9402 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply, supply not electrically isolated
Terminal blocks
0TB2105.9010 Accessory terminal block, 5-pin, screw clamp 2.5 mm²
0TB2105.9110 Accessory terminal block, 5-pin, cage clamp 2.5 mm²
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 117: X20BC0043-10 - Order data

4.5.3.3 Technical data

Product ID X20BC0043-10
Short description
Bus controller CANopen slave
General information
B&R ID code 0xA8B8
Status indicators Module status, bus function, data transfer, terminating resistor
Diagnostics
Module status Yes, with status LED and software status
Bus function Yes, with status LED and software status
Data transfer Yes, with status LED
Terminating resistor Yes, with status LED
Power consumption
Bus 2W
Electrical isolation
Fieldbus - X2X Link No
Fieldbus - I/O Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
GOST-R Yes
Interfaces
Fieldbus CANopen slave
Design 5-pin male multipoint connector
Max. distance 1000 m
Transfer rate Max. 1 Mbit/s
Determination of transfer rate Automatic transfer rate detection or fixed rate setting
Terminating resistor Integrated in the module
Min. cycle time 1)
Fieldbus No limitations
X2X Link 500 μs
Synchronization between bus systems possible No
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C

Table 118: X20BC0043-10 - Technical data

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Product ID X20BC0043-10
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x TB2105 terminal block separately
Order 1x X20TB12 terminal block separately
Order 1x X20PS9400 or X20PS9402 power supply module separately
Order 1x X20BB80 bus base separately
Spacing 2) 37.5 +0.2 mm

Table 118: X20BC0043-10 - Technical data

1) The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
2) Spacing is based on the width of the X20BB80 bus base. In addition, an X20PS9400 or X20PS9402 supply module is always required for the bus controller.

4.5.3.4 LED status indicators

Figure LED Color Status Description

MS1) Green Off No power supply
Flashing 5 second window for deleting all configuration settings
On Boot procedure OK, I/O modules OK
Red Double flash Successfully erased flash memory
Triple flash Successfully saved transfer rate
Quad flash Successfully saved configuration
On I/O modules: Error message or incorrect configuration
RUN Green Off No power supply
Single flash STOP mode
Triple flash Firmware download in progress
Blinking PREOPERATIONAL mode
On OPERATIONAL mode
ERR Red Off No power supply or everything is OK
Single flash CAN warning limit reached
Double flash Node guarding / heartbeat error
Blinking Invalid node number or configuration
On Bus errors: Bus off
RUN/ERR Green/red Flickering Transfer rate detection in progress
TxD Yellow Off The bus controller is not transmitting any data via the CANopen fieldbus
On The bus controller is transmitting data via the CANopen fieldbus
TERM Yellow Off The terminating resistor integrated in the bus controller is turned off
On The terminating resistor integrated in the bus controller is turned on

Table 119: LED status indicators

1) The "MS" LED is a green/red dual LED. The LED blinks red several times immediately after startup. This is a boot message, however, and not an error.

quad Flash
200 200 200 200 200 200 200 1000

triple Flash
200 200 200 200 200 1000

double Flash
200 200 200 1000

single Flash
200 1000

blinkend
200 200
3
blitzend
500

grün/rot
Flickering
50
All times in ms

Figure 203: Status LEDs - Blinking patterns

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4.5.3.5 Operating and connection elements

LED status indicator

Node number switches

Terminal block for bus controller

and I/O supply

CANopen interface

Terminating resistor switch

on the bottom of the module

Figure 204: Operating and connection elements

4.5.3.6 CAN bus interface

The interface is a 5-pin multipoint plug. The 0TB2105 terminal block must be ordered separately.
Interface Pinout
Terminal Function
1
1 CAN⊥ CAN ground
2 CAN_L CAN low
3 SHLD Shield
5 4 CAN_H CAN high
5 NC
5-pin male multipoint connector

Table 120: Pinout

4.5.3.7 Terminating resistor

Terminating resistor switch

On Off

A terminating resistor is already integrated on the bus controller. It can be turned on and off with a switch on the
bottom of the housing. An active terminating resistor is indicated by the "TERM" LED.

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4.5.3.8 Node number and transfer rate

Node numbers and transfer rates are configured using the two bus controller number switches.
The transfer rate can be specified in two ways:
• Automatic detection by bus controller (see 4.5.3.9 "Automatic transfer rate detection" on page 517)
• Fixed definition by user (see 4.5.3.10 "Setting the transfer rate" on page 518)

Switch position Node number Transfer rate

0x00 Not allowed -
0x01 - 0x7F 1 - 127 Automatically set by the bus controller (default) or fixed setting
by the user
0x80 - 0x88 - Sets a fixed transfer rate
0x89 - Sets automatic transfer rate detection
0x8A - 0x8F Not allowed -
0x90 Clearing the parameters -
See section 4.5.3.12 "Deleting parameters" on page 520
0x91 Not allowed -
0x92 Save configuration1) -
See section 4.5.3.11 "Save auto-
matic configuration" on page 519
0x93 - 0xFF Not allowed -

Table 121: Node numbers and transfer rate

1) This function is available starting with Hardware version E0 or Firmware version V0001.0107.

4.5.3.9 Automatic transfer rate detection

After booting, the bus controller goes into "Listen only" mode. This means the bus controller behaves passively
on the bus and only listens.
The bus controller attempts to receive valid objects. If receive errors occur, the controller switches to the next
transfer rate in the lookup table.
If no objects are received, all transfer rates are tested cyclically. This procedure is repeated until valid objects are
received.
Lookup table
The controller tests the transfer rate according to this table. Beginning with the starting transfer rate (1000 kbit/s),
the controller switches to the next lower transfer rate. At the end of the table, the bus controller restarts the search
from the beginning.
Transfer rate
1000 kbit/s
800 kbit/s
500 kbit/s
250 kbit/s
125 kbit/s
100 kbit/s
50 kbit/s
20 kbit/s
10 kbit/s

Table 122: Transfer rate lookup table

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4.5.3.10 Setting the transfer rate

The bus controller will detect the transfer rate automatically by default. Switch positions 0x80 - 0x88 can be used
to set a fixed transfer rate, or 0x89 can be used to enable automatic transfer rate detection.
Switch position Transfer rate
0x80 1000 kbit/s
0x81 800 kbit/s
0x82 500 kbit/s
0x83 250 kbit/s
0x84 125 kbit/s
0x85 100 kbit/s
0x86 50 kbit/s
0x87 20 kbit/s
0x88 10 kbit/s
0x89 Automatic transfer rate detection

Table 123: Possible transfer rates

Programming the transfer rate

1. Turn off the power supply to the bus controller.
2. Define the transfer rate to be programmed by setting the node numbers (0x80 - 0x89)
3. Turn on the power supply to the bus controller.
4. Wait until the "MS" LED blinks with a red triple-flash (transfer rate is now programmed).
5. Turn off the power supply to the bus controller.
6. Set the desired node number (0x01 - 0x7F).
7. Turn on the power supply to the bus controller.
8. The bus controller now boots with the set node number and the programmed transfer rate.

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4.5.3.11 Save automatic configuration

The node number position 0x92 can be used to save automatically generated configurations. This makes it possible
to work with a standardized configuration without having to adapt the application to changes associated with service
work or different development stages for example.
1. Turn off the power supply to the bus controller.
2. Set the node number to 0x90.
3. Turn on the power supply to the bus controller.
4. Wait until the "MS" LED starts blinking green (100 ms on / 200 ms off).
5. The node number switch must be set to 0x00 and then back to 0x90 within this time window of 5 seconds
(rotate the top switch).
6. Wait until the "MS" LED blinks with a red double-flash (parameters have been cleared).
7. Turn off the power supply to the bus controller.
8. Set the node number to 0x92.
9. Turn on the power supply to the bus controller.
10.Wait until the "MS" LED starts blinking green (100 ms on / 200 ms off).
11. The node number switch must be set to 0x02 and then back to 0x092 within this time window of 5 seconds
(rotate the top switch).
12.Wait until the "MS" LED blinks with a red quad-flash (parameters have been saved).
13.Turn off the power supply to the bus controller.
14.Set the desired node number (0x01 - 0x7F).
15.Turn on the power supply to the bus controller.
16.The bus controller boots with the set node number and automatic transfer rate detection.

Information:
A mapping tool for decoding the saved PDO mapping is available in the Download section of the B&R
website (www.br-automation.com).

Information:
This function is available starting with Hardware version E0 or Firmware version V0001.0107.

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4.5.3.12 Deleting parameters

Various parameters can be stored in the bus controller's flash memory:

• Communication parameters
• Vendor-specific parameters
• Application parameters (device profile)
• Fixed transfer rate
Deleting these parameters using switch position 0x90 returns the bus controller to its factory settings.

Clearing the parameters listed above

1. Turn off the power supply to the bus controller.
2. Set the node number to 0x90.
3. Turn on the power supply to the bus controller.
4. Wait until the "MS" LED starts blinking green (100 ms on / 200 ms off). The node number switch must be set
to 0x00 and then back to 0x090 within this time window of 5 seconds (rotate the top switch).
5. Wait until the "MS" LED blinks with a red double-flash (parameters have been cleared).
6. Turn off the power supply to the bus controller.
7. Set the desired node number (0x01 - 0x7F)
8. Turn on the power supply to the bus controller.
9. The bus controller boots with the set node number and automatic transfer rate detection.

4.5.3.13 Additional documentation and import files (EDS)

Additional documentation about bus controller functions as well as the necessary import files for the master engi-
neering tool are available in the Downloads section of the B&R website (www.br-automation.com).

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4.5.4 X20BC0053

4.5.4.1 General information

DeviceNet was developed by Allen Bradley as a CAN bus based automation network. It is based on a produc-
er/consumer protocol. From the user's point of view, all data is handled separately from CAN bus transfer possi-
bilities (e.g. longer data packets are automatically fragmented by DeviceNet). Access occurs using I/O messages
with defined properties.
The X20BC0053 bus controller makes it possible to connect X2X Link I/O nodes to DeviceNet. It has automatic
transfer rate detection, auto scan, automatic mapping and automatic configuration of the I/O modules. Explicit mes-
saging, change of state, cyclic, polled and bit strobe are supported as transfer modes. In addition to the standard
communication objects, there are also manufacturer-specific objects used to represent the modular X20 System
in the best manner possible.
X20 and other modules that are based on X2X Link can be connected to the bus controller. The entire configuration
of this type of modular system is supported by the DeviceNet standard. Allen Bradley developed the modular I/O
configuration to simplify the necessary configuration steps. The DeviceNet bus controllers from B&R also support
this type of configuration.
• Fieldbus: DeviceNet
• I/O configuration via the fieldbus
• Support of both linear and modular (Allen Bradley) configuration systems
• Auto scan, automatic I/O mapping of the I/Os
• Automatic I/O configuration (starting with Rev. D0, firmware version 1.23)
• Integrated terminating resistor

Information:
Only the standard function model (see the respective module description) is supported when the bus
controller is used together with multi-function modules it has automatically configured itself.

4.5.4.2 Order data

Model number Short description Figure

Bus controllers
X20BC0053 X20 bus controller, DeviceNet interface, order 1x TB2105 termi-
nal block separately. Order bus base, power supply module and
terminal block separately.
Required accessories
System modules for bus controllers
X20BB80 X20 bus base, for X20 base module (BC, HB, etc.) and X20 pow-
er supply module, X20 end plates X20AC0SL1/X20AC0SR1 (left
and right) included
X20PS9400 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply
X20PS9402 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply, supply not electrically isolated
Terminal blocks
0TB2105.9010 Accessory terminal block, 5-pin, screw clamp 2.5 mm²
0TB2105.9110 Accessory terminal block, 5-pin, cage clamp 2.5 mm²
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 124: X20BC0053 - Order data

4.5.4.3 Technical data

Product ID X20BC0053
Short description
Bus controller DeviceNet adapter (slave)
General information
B&R ID code 0x1F1B
Status indicators Module status, bus function, 24V DeviceNet voltage, data transfer, terminating resistor.
Diagnostics
24 V DeviceNet voltage Yes, with status LEDs (MOD and NET)
Module status Yes, with status LED and software status
Bus function Yes, with status LED
Data transfer Yes, with status LED
Terminating resistor Yes, with status LED

Table 125: X20BC0053 - Technical data

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Product ID X20BC0053
Power consumption
Bus 1.5 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Fieldbus - X2X Link No
Fieldbus - I/O Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Interfaces
Fieldbus DeviceNet adapter (slave)
Design 5-pin male multipoint connector
Max. distance 500 m
Transfer rate Max. 500 kbit/s
Determination of transfer rate Automatic transfer rate detection
Terminating resistor Integrated in the module
Min. cycle time 1)
Fieldbus No limitations
X2X Link 400 μs
Synchronization between bus systems possible No
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation 0 to 55°C
Vertical installation 0 to 50°C
Derating -
Storage -25 to 70°C
Transport -25 to 70°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x TB2105 terminal block separately
Order 1x X20TB12 terminal block separately
Order 1x X20PS9400 or X20PS9402 power supply module separately
Order 1x X20BB80 bus base separately
Spacing 2) 37.5 +0.2 mm

Table 125: X20BC0053 - Technical data

1) The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
2) Spacing is based on the width of the X20BB80 bus base. In addition, an X20PS9400 or X20PS9402 supply module is always required for the bus controller.

4.5.4.4 LED status indicators

Figure LED Color Status Description

MOD1) Green Off Bus sense error:
If the "NET" LED is also "off", there is no 24 V DeviceNet voltage.

No transfer rate:
If the PS9400's "RUN" LED is active (PREOPERATIONAL or RUN mode), the
automatic transfer rate detection is still running or no transfer rate could be de-
tected.
On RUN mode:
The 24 V DeviceNet voltage is OK and the module is operating under normal
conditions.
Blinking Standby mode:
Configuration is missing, incomplete, or incorrect.
Red Blinking Recoverable Fault mode:
Green/red Blinking Module is performing a self test.

Table 126: LED status indicators

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Figure LED Color Status Description
NET1) Green Off No power, offline:
• Bus sense error: If the "MOD" LED is also off, there is no 24 V DeviceNet
voltage.
• No transfer rate: If the PS9400's "RUN" LED is active
(PREOPERATIONAL or RUN mode), the automatic transfer rate detec-
tion is still running or no transfer rate could be detected.
• Module has not yet completed a duplicate MAC-ID test.
Blinking Online, not connected:
• The module has carried out the duplicate MAC-ID test and is online.
• There is no established connection to a master/scanner.
On Everything is OK:
A connection to the master/scanner (explicit or I/O) is set up.
Red Blinking Connection timeout:
The time for an I/O connection has expired.
On Critical connection error - fieldbus communication no longer possible:
• Duplicate MAC ID error
• Bus off
• Receive/transmit overrun
TxD Yellow Off The bus controller is not transmitting any data via the DeviceNet fieldbus
On The bus controller is transmitting data via the DeviceNet fieldbus
TERM Yellow Off The terminating resistor integrated in the bus controller is turned off
On The terminating resistor integrated in the bus controller is turned on

Table 126: LED status indicators

1) The "MOD" and "NET" LEDs are green/red dual LEDs.

4.5.4.5 Operating and connection elements

LED status indicator

Node number switches

Terminal block for bus controller

and I/O supply

DeviceNet interface

Terminating resistor switch

on the bottom of the module

Figure 205: Operating and connection elements

4.5.4.6 DeviceNet interface

The interface is a 5-pin multipoint plug. The 0TB2105 terminal block must be ordered separately.
Interface Pinout
Terminal DeviceNet
1
1 CAN⊥ (V-) CAN ground
2 CAN_L CAN low
3 SHLD Shield
5 4 CAN_H CAN high
5 V+ Supply voltage1)
5-pin male multipoint connector

Table 127: Pinout

1) A 24 V supply voltage can be connected here for non-B&R products. The supply is only passed through. B&R modules neither provide nor require this
voltage supply.

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4.5.4.7 Terminating resistor

Terminating resistor switch

On Off

A terminating resistor is already integrated on the bus controller. It can be turned on and off with a switch on the
bottom of the housing. An active terminating resistor is indicated by the "TERM" LED.

4.5.4.8 Node number

The MAC ID is configured using the two address switches on the bus controller.
The configurable range lies between 0 and 63. This value range is required in the DeviceNet specifications for a
DeviceNet device.

Figure 206: Address switch

Switch position MAC ID
00 - 63 0 - 63
64 The MAC ID can be configured by setting the address switch using the master/scanner software.
65 - 89 Not permitted
90 "Clearing the parameters"
91 - 94 Not permitted
95 "Automatic configuration"
96 - 99 Not permitted

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4.5.4.9 Automatic transfer rate detection

After booting, the bus controller goes into "Listen only" mode. This means the bus controller behaves passively
on the bus and only listens.
The bus controller attempts to receive valid objects. If receive errors occur, the controller switches to the next
transfer rate in the lookup table.
If no objects are received, all transfer rates are tested cyclically. This procedure is repeated until valid objects
are received, indicating that the correct transfer rate has been determined. Only transfer rates permitted by the
DeviceNet specification are tested.
Lookup table
The controller tests the transfer rate according to this table. Beginning with the starting transfer rate (500 kbit/s),
the controller switches to the next lower transfer rate. At the end of the table, the bus controller restarts the search
from the beginning.
Transfer rate
500 kbit/s
250 kbit/s
125 kbit/s

Table 128: Transfer rate lookup table

Information:
While automatic transfer rate recognition is running, both DeviceNet LEDs are switched off (because
there is no LED status definition in the DeviceNet specifications for this status).
To ensure that the module has been supplied and booted, this manufacturer specific status definition
requires the X20PS9400 RUN LED to be active.

4.5.4.10 Clearing the parameters

Multiple parameters can be stored in the bus controller flash memory. Deleting the parameters using the switch
position 90 returns the bus controller to its factory settings.

Deleting parameters
1. Turn off the power supply to the bus controller.
2. Set the node number to 90
3. Turn the power supply to the bus controller back on.
4. Wait until the "MOD" LED blinks green for 5 s (3 ms on / 500 ms off). The node number switch must be set
to 00 and then back to 90 within this time window.
5. Wait until the "MOD" LED blinks with a red double-flash (parameters have been cleared).
6. Turn off the power supply to the bus controller.
7. Set desired node number (00 - 63)
8. Turn the power supply to the bus controller back on.
9. The bus controller boots with the set node number and automatic transfer rate detection.

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4.5.4.11 Automatic configuration of the I/O modules

The automatic configuration of the connected I/O modules by the bus controller is supported starting with Rev.D0
(firmware ≥V 1.23) of the bus controller.
To prevent the configuration data from being accidentally overwritten on the bus controller, the procedure described
below must be followed when creating the configuration data. When doing this, it is important that all required I/
O modules are also started when booting the bus controller (i.e. supplied with power). This is especially important
when using potential groups (E-stop switches).
The automatic configuration sets the following attributes of class 0x65 on the individual I/O modules:
• Module type (0x01)
• Input length (0x03)
• Output length (0x05)
Additional parameters are not set. That means that the connected modules are configured with their standard
settings and standard I/O lengths. This can be changed by editing the parameters in the respective master engi-
neering tool.

Automatic configuration
1. Turn off the power supply to the bus controller.
2. Set node number switch to 95 (this is done by turning "x10" switch right to the position "P" and the "x1" switch
to 5).
3. Turn on the power supply to the bus controller.
4. Wait until the "MOD" LED starts blinking green (3 ms on / 500 ms off). This phase of green blinking lasts 5 s.
The node number "x10" switch must be set to 0 within this time frame and then set back to 9.
5. Wait until the "MOD" LED blinks (4 red flashes). The old configuration data is now deleted completely and
overwritten with the new values from the connected I/O modules.
6. Turn off the power supply to the bus controller.
7. Set the desired node number (00 - 63).
8. Turn on the power supply to the bus controller.
9. The bus controller boots using the set node number, automatic transfer rate recognition and standard settings
from the connected I/O modules.

4.5.4.12 Additional documentation and import files (EDS)

Additional documentation about bus controller functions as well as the necessary import files for the master engi-
neering tool are available in the Downloads section of the B&R website (www.br-automation.com).

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4.5.5 X20BC0063

4.5.5.1 General information

PROFIBUS DP is based on the physics of the RS485 interface. Data transfer is controlled using a hybrid bus access
procedure. Active stations receive communication rights via a token passing procedure and can then access all
stations on the network according to the master-slave principle. The maximum time of circulation for a token can
be configured, which results in a defined cycle time.
Access represents various services for the user for both cyclic and for non-cyclic data transfer.
The X20BC0063 bus controller makes it possible to connect X2X Link I/O nodes to PROFIBUS DP. It supports
PROFIBUS DP with all of its options and other additional properties. In addition to the device, module, and channel
diagnostics provided in the PROFIBUS standard, it is also possible, for example, to switch to the slot diagnostics
option in S7 format. X20 or other modules that are based on X2X Link can be connected to the bus controller.
Modular system configurations are optimally supported by PROFIBUS DP.
• Fieldbus: PROFIBUS DP
• I/O configuration via the fieldbus
• Extensive device, module, and channel diagnosis according to PROFIBUS DP standard
• Communication with X2X Link I/O nodes even works when some nodes are missing or without power

Information:
Only the standard function model (see the respective module description) is supported when the bus
controller is used together with multi-function modules it has automatically configured itself.

4.5.5.2 Order data

Model number Short description Figure

Bus controllers
X20BC0063 X20 bus controller, PROFIBUS DP interface, 9-pin DSUB con-
nection, order bus base, power supply module and terminal
block separately.
Required accessories
System modules for bus controllers
X20BB80 X20 bus base, for X20 base module (BC, HB, etc.) and X20 pow-
er supply module, X20 end plates X20AC0SL1/X20AC0SR1 (left
and right) included
X20PS9400 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply
X20PS9402 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply, supply not electrically isolated
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed
Optional accessories
Infrastructure components
0G1000.00-090 Bus connector, RS485, for PROFIBUS networks

Table 129: X20BC0063 - Order data

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4.5.5.3 Technical data

Product ID X20BC0063
Short description
Bus controller PROFIBUS DP V0 slave
General information
B&R ID code 0x1F1C
Status indicators Module status, bus function, data transfer
Diagnostics
Module status Yes, with status LED and software status
Bus function Yes, with status LED
Data transfer Yes, with status LED
Power consumption
Bus 2.3 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Fieldbus - X2X Link No
Fieldbus - I/O Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Interfaces
Fieldbus PROFIBUS DP V0 slave
Design 9-pin DSUB socket
Max. distance 1200 m
Transfer rate Max. 12 Mbit/s
Determination of transfer rate Automatic transfer rate detection
Min. cycle time 1)
Fieldbus No limitations
X2X Link 400 μs
Synchronization between bus systems possible No
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20PS9400 or X20PS9402 power supply module separately
Order 1x X20BB80 bus base separately
Spacing 2) 37.5 +0.2 mm

Table 130: X20BC0063 - Technical data

1) The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
2) Spacing is based on the width of the X20BB80 bus base. In addition, an X20PS9400 or X20PS9402 supply module is always required for the bus controller.

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4.5.5.4 LED status indicators

Figure LED Description

STATUS and ERROR Status indicator for PROFIBUS DP bus controller.
STATUS (green) ERROR (red) Description
Off Off HARDWARE FAULT / POWER FAIL
On On BUS OFF
On Blinking WAIT FOR CONFIG
Blinking Off DATA EXCHANGE - DIAGNOSTICS
On Off DATA EXCHANGE - NO ERROR
Blinking Blinking CONFIG ERROR
Off Blinking SERVICE MODE - BOOT
Single flash Single flash HARDWARE FAULT
For a more detailed description see the section 4.5.5.5 "State diagnostics via the Status/Error LEDs" on
page 529.
RxD This yellow LED lights up when the bus controller is receiving data from the PROFIBUS DP fieldbus.
TxD This yellow LED lights up when the bus controller is sending data via the PROFIBUS DP fieldbus.

Table 131: LED status indicators

4.5.5.5 State diagnostics via the Status/Error LEDs

The condition of the PROFIBUS DP bus controller is diagnosed using the LED status indicators "STATUS" and
"ERROR".
STATUS ERROR Function Solution
(green) (red)
Off Off HARDWARE FAULT / POWER FAIL • Check wiring of supply voltage.
On On BUS OFF • Check the PROFIBUS network
• Baud rate not detected • Check the PROFIBUS master
• No connection to the DP master
• DP master not active
On Blinking WAIT FOR CONFIG • Check the node number switch
• Transfer rate has been detected, but the PROFIBUS • Check the slave address in the master configuration
master has not yet configured the bus controller
Blinking Off DATA EXCHANGE - DIAGNOSTICS • Initialization can take a few seconds depending on the
• The bus controller is still initializing the I/O modules number of I/O modules connected
• The I/O modules configured by the master cannot be • Check the wiring and power supply for the I/O modules
found • Read diagnostic messages in the respective PROFIBUS
• An error has occurred on one or more I/O modules (short master's engineering tool
circuit, etc.)
On Off DATA EXCHANGE
• Cyclic data exchange with the PROFIBUS DP master
Blinking Blinking CONFIG ERROR • Check the wiring of the X2X Link and the order of I/O
• One or more I/O modules found do not match with the modules
configuration of the PROFIBUS DP master • Check configuration of the PROFIBUS master
• The configuration received from the PROFIBUS master • Read diagnostic messages in the respective PROFIBUS
is invalid master's engineering tool
• Check the configuration being used - it is possible that
the number of configured I/O modules is too high
Off Blinking SERVICE MODE - BOOT • Set a valid node number
• The bus controller's node number has been set to 255
(0xFF) - after 2 s the bus controller starts in service mode
Single flash Single flash HARDWARE FAULT

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4.5.5.6 Operating and connection elements

LED status indicator

Node number switches

Terminal block for bus controller

and I/O supply

PROFIBUS DP interface

Figure 207: Operating and connection elements

4.5.5.7 PROFIBUS DP interface

Interface Pinout
Pin RS485
1 Reserved
2 Reserved
9 5 3 RxD/TxD-P Data1)
4 CNTR-P Transmit enable
6 5 DGND Electrically isolated supply
1
6 CP Electrically isolated supply
7 Reserved
9-pin female DSUB connector
8 RxD/TxD-N Data\2)
9 CNTR-N Transmit enable\
CNTR ... Directional switch for external repeater

Table 132: Pinout

1) Cable color: Red
2) Cable color: Green

4.5.5.8 PROFIBUS DP node number switches

The PROFIBUS DP node number is configured using both number switches of the bus controller.

Switch position Node number

0x00 Not allowed
0x01 - 0x7D 1 - 125
0x7E - 0xFF Not allowed

Table 133: Node numbers

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4.5.5.9 Automatic transfer rate detection

After booting or after a communication timeout, the bus controller goes into the status "Baud Search". This means
the bus controller behaves passively on the bus.
The bus controller always begins the search for the configured transfer rate with the highest transfer rate. If a
complete error-free telegram is not received during monitoring time, then the search is continued using the next
lowest transfer rate.
Transfer rate
12 Mbit/s
6 Mbit/s
3 Mbit/s
1.5 Mbit/s
500 kbit/s
187.5 kbit/s
93.75 kbit/s
45.45 kbit/s
19.2 kbit/s
9.6 kbit/s

Table 134: Transfer rates supported by the bus controller

4.5.5.10 Additional documentation and import files (EDS)

Additional documentation about bus controller functions as well as the necessary import files for the master engi-
neering tool are available in the Downloads section of the B&R website (www.br-automation.com).

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4.5.6 X20BC0073

4.5.6.1 General information

The X20BC0073 bus controller makes it possible to connect X2X Link I/O nodes to CAN I/O. CAN I/O is a transfer
protocol based on standard CAN bus fully integrated in the B&R system. From the user's point of view, it doesn't
matter if I/O points are operated locally or remotely via CAN I/O.
Up to 43 I/O modules can be connected to the bus controller. Up to 16 of them can be analog modules.
• Fieldbus: CAN bus
• Automatic firmware update via the fieldbus
• Integrated I/O access in B&R Automation Studio
• Integrated terminating resistor

Information:
The bus controller is unable to detect modules after a gap in the X2X Link station numbers. This can
be caused by:
• X20 modules not being connected
• Modules with integrated node number switch, such as the X20BM05

Information:
Only the standard function model (see the respective module description) is supported when the bus
controller is used together with multi-function modules it has automatically configured itself.

4.5.6.2 Order data

Model number Short description Figure

Bus controllers
X20BC0073 X20 bus controller, CAN I/O interface, order 1x TB2105 termi-
nal block separately. Order bus base, power supply module and
terminal block separately.
Required accessories
System modules for bus controllers
X20BB80 X20 bus base, for X20 base module (BC, HB, etc.) and X20 pow-
er supply module, X20 end plates X20AC0SL1/X20AC0SR1 (left
and right) included
X20PS9400 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply
X20PS9402 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply, supply not electrically isolated
Terminal blocks
0TB2105.9010 Accessory terminal block, 5-pin, screw clamp 2.5 mm²
0TB2105.9110 Accessory terminal block, 5-pin, cage clamp 2.5 mm²
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 135: X20BC0073 - Order data

4.5.6.3 Technical data

Product ID X20BC0073
Short description
Bus controller CAN I/O slave
General information
B&R ID code 0x1F1D
Status indicators Module status, bus function, data transfer, terminating resistor
Diagnostics
Module status Yes, with status LED and software status
Bus function Yes, with status LED
Data transfer Yes, with status LED
Terminating resistor Yes, with status LED
Power consumption
Bus 1.5 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Fieldbus - X2X Link No
Fieldbus - I/O Yes

Table 136: X20BC0073 - Technical data

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Product ID X20BC0073
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Interfaces
Fieldbus CAN I/O slave
Design 5-pin male multipoint connector
Max. distance 1000 m
Transfer rate Max. 1 Mbit/s
Determination of transfer rate Automatic transfer rate detection or fixed rate setting
Terminating resistor Integrated in the module
Min. cycle time 1)
Fieldbus 1 ms
X2X Link 1 ms
Synchronization between bus systems possible No
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x TB2105 terminal block separately
Order 1x X20TB12 terminal block separately
Order 1x X20PS9400 or X20PS9402 power supply module separately
Order 1x X20BB80 bus base separately
Spacing 2) 37.5 +0.2 mm

Table 136: X20BC0073 - Technical data

1) The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
2) Spacing is based on the width of the X20BB80 bus base. In addition, an X20PS9400 or X20PS9402 supply module is always required for the bus controller.

4.5.6.4 LED status indicators

Figure LED Color Status Description

STATUS1) Green Off No power supply
Blinking PREOPERATIONAL mode
On RUN mode
Red On CAN connection reports BusOff status
Green/red Flickering Transfer rate detection in progress
Green blinking / PREOPERATIONAL mode; CAN connection reports: Warning limit reached
red single flash
Steady green / single red flash RUN mode; CAN connection reports: Warning limit reached
TxD Yellow Off The bus controller is not transmitting any data via the CAN I/O fieldbus
On The bus controller is transmitting data via the CAN I/O fieldbus
TERM Yellow Off The terminating resistor integrated in the bus controller is turned off
On The terminating resistor integrated in the bus controller is turned on

Table 137: LED status indicators

1) The "STATUS" LED is a green/red dual LED.

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4.5.6.5 Operating and connection elements

LED status indicator

Node number switches

Terminal block for bus controller

and I/O supply

CAN I/O connection

Terminating resistor switch

on the bottom of the module

Figure 208: Operating and connection elements

4.5.6.6 CAN bus interface

The interface is a 5-pin multipoint plug. The 0TB2105 terminal block must be ordered separately.
Interface Pinout
Terminal Function
1
1 CAN⊥ CAN ground
2 CAN_L CAN low
3 SHLD Shield
5 4 CAN_H CAN high
5 NC
5-pin male multipoint connector

Table 138: Pinout

4.5.6.7 Terminating resistor

Terminating resistor switch

On Off

A terminating resistor is already integrated on the bus controller. It can be turned on and off with a switch on the
bottom of the housing. An active terminating resistor is indicated by the "TERM" LED.

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4.5.6.8 Node number and transfer rate

Node numbers and transfer rates are configured using the two bus controller number switches. The switch posi-
tions 0x00 to 0x40 and 0x60 enable automatic transfer rate detection (see section 4.5.6.9 "Automatic transfer rate
detection" on page 535). The rest of the switch positions have a fixed transfer rate (see table).

Switch position Node number Transfer rate

0x001) From EEPROM From EEPROM
0x01 - 0x3F 1 - 63 Automatic
0x401) From EEPROM From EEPROM
0x41 - 0x5F 1 - 31 1000 kbit/s
0x601) From EEPROM From EEPROM
0x61 - 0x7F 1 - 31 800 kbit/s
0x80 Reserved -
0x81 - 0x9F 1 - 31 500 kbit/s
0xA0 Reserved -
0xA1 - 0xBF 1 - 31 250 kbit/s
0xC0 Reserved -
0xC1 - 0xDF 1 - 31 125 kbit/s
0xE0 Reserved -
0xE1 - 0xFE 1 - 31 20 kbit/s
0xFF Reserved -

Table 139: Node numbers and transfer rate

1) When one of these numbers is configured, the bus controller uses the operating parameters from the internal EEPROM. The EEPROM is programmed
using the CANIO library.

4.5.6.9 Automatic transfer rate detection

After booting, the bus controller goes into "Listen only" mode. This means the bus controller behaves passively
on the bus and only listens.
The bus controller attempts to receive valid objects. If receive errors occur, the controller switches to the next
transfer rate in the lookup table.
If no objects are received, all transfer rates are tested cyclically. This procedure is repeated until valid objects are
received.
Starting transfer rate
The bus controller begins the search with this transfer rate. The starting transfer rate can be defined in two different
ways:
• Read from EEPROM
• Using the last detected transfer rate after a software reset (Command Code 20)
Search table
The controller tests the transfer rate according to this table. Beginning with the starting transfer rate, the controller
switches to the next lower transfer rate. At the end of the table, the bus controller starts searching from the beginning
again.
Transfer rate
1000 kbit/s
500 kbit/s
250 kbit/s
125 kbit/s
50 kbit/s
20 kbit/s
10 kbit/s

Table 140: Transfer rate lookup table

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4.5.6.10 SG4

The module comes with preinstalled firmware. The firmware is also part of the B&R Automation Runtime operating
system for the PLC. If the two versions are different, the Automation Runtime firmware is loaded to the module.
The latest firmware is available automatically when updating B&R Automation Runtime.

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4.5.7 X20BC0083

4.5.7.1 General information

The X20BC0083 bus controller makes it possible to connect X2X Link I/O nodes to POWERLINK. It is also possible
to operate the X2X Link cycle synchronously 1:1 or synchronous to POWERLINK using a prescaler.
POWERLINK is a standard protocol for Fast Ethernet with hard real-time properties. The Ethernet POWER-
LINK Standardization Group (EPSG) ensures that the standard remains open and is continually developed:
www.ethernet-powerlink.org
• POWERLINK
• I/O configuration and FW update via the fieldbus
• Integrated hub for efficient cabling

4.5.7.2 Order data

Model number Short description Figure

Bus controllers
X20BC0083 X20 bus controller, POWERLINK interface, integrated 2x hub,
2x RJ45 connection, order bus base, power supply module and
terminal block separately.
Required accessories
System modules for bus controllers
X20BB80 X20 bus base, for X20 base module (BC, HB, etc.) and X20 pow-
er supply module, X20 end plates X20AC0SL1/X20AC0SR1 (left
and right) included
X20PS9400 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply
X20PS9402 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply, supply not electrically isolated
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 141: X20BC0083 - Order data

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4.5.7.3 Technical data

Product ID X20BC0083
Short description
Bus controller POWERLINK (V1/V2) controlled node
General information
B&R ID code 0x1F1E
Status indicators Module status, bus function
Diagnostics
Module status Yes, with status LED and software status
Bus function Yes, with status LED and software status
Power consumption
Bus 2.0 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Fieldbus - X2X Link Yes
Fieldbus - I/O Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Interfaces
Fieldbus POWERLINK (V1/V2) controlled node
Design 2x shielded RJ45 port (hub)
Cable length Max. 100 m between two stations (segment length)
Transfer rate 100 Mbit/s
Transmission
Physical interfaces 100 BASE-TX
Half-duplex Yes
Full-duplex No
Autonegotiation Yes
Auto-MDI / MDIX Yes
Min. cycle time 1)
Fieldbus 200 μs
X2X Link 200 μs
Synchronization between bus systems possible Yes
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20PS9400 or X20PS9402 power supply module separately
Order 1x X20BB80 bus base separately
Spacing 2) 37.5 +0.2 mm

Table 142: X20BC0083 - Technical data

1) The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
2) Spacing is based on the width of the X20BB80 bus base. In addition, an X20PS9400 or X20PS9402 supply module is always required for the bus controller.

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4.5.7.4 LED status indicators

Figure LED Color Status Description

S/E1) Green Off No power supply or mode is NOT_ACTIVE.
In this mode, the bus controller waits for about 5 seconds after restarting. No
communication with the bus controller is possible.
If no POWERLINK communication is detected during these 5 seconds, the bus
controller goes into the BASIC_ETHERNET mode.
If POWERLINK communication is detected before this time passes, however,
the bus controller goes into the PRE_OPERATIONAL_1 mode.
Flickering BASIC_ETHERNET mode.
The bus controller did not detect any POWERLINK communication. In this mode,
direct communication with the bus controller is possible using UDP.
If POWERLINK communication is detected while in this mode, the bus controller
goes into the PRE_OPERATIONAL_1 mode.
Single flash PRE_OPERATIONAL_1 mode.
With operation on a POWERLINK V1 master, the bus controller goes directly into
PRE_OPERATIONAL_2 mode.
With operation on an POWERLINK V2 manager, the CN (Controlled Node)
waits for the reception of a SoC frame and then switches over to
PRE_OPERATIONAL_2 mode.
Double flash PRE_OPERATIONAL_2 mode.
In this mode the bus controller is normally configured by the manager. A com-
mand (POWERLINK V2) or setting the data valid flag in the output data (POW-
ERLINK V1) then switches the mode to READY_TO_OPERATE.
Triple flash READY_TO_OPERATE mode.
In a POWERLINK V2 network, the manager then switches via command to OP-
ERATIONAL mode.
In a POWERLINK V1 network, the bus controller then switches automatically to
OPERATIONAL mode as soon as input data are present.
On OPERATIONAL mode
Blinking STOPPED mode.
No output data sent nor input data received. Only the appropriate command from
the manager can enter or leave this mode.
Red On The bus controller has encountered an error (failed Ethernet frames, increased
number of collisions on the network, etc.).
Note: The LED blinks red several times immediately after startup. This is not an
error.
L/A IFx Green On Link established to the remote station
Blinking A link to the remote station has been established and there is activity on bus.

Table 143: LED status indicators

1) The Status/Error LED "S/E" is a green/red dual LED.

Triple flash
200 200 200 200 200 1000

Double flash
200 200 200 1000

Single flash
200 1000

Blinking
200 200

Flickering
All times in ms

Figure 209: Status LEDs - Blinking patterns

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4.5.7.5 Operating and connection elements

LED status indicator

Node number switches

Terminal block for bus controller

and I/O supply

POWERLINK connection with

2 x RJ45 connectors for simple wiring

Figure 210: Operating and connection elements

4.5.7.6 POWERLINK station number

The station number for the POWERLINK station is set using the two number switches. Station numbers are per-
mitted between 0x01 and 0xEF.
Switch position Description
0x00 Reserved, switch position not permitted.
0x01 - 0xEF Station number of the POWERLINK station. Operation as controlled node.
0xF0 - 0xFF Reserved, switch position not permitted.

Table 144: Station number

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4.5.7.7 RJ45 ports

Information about cabling X20 modules with an Ethernet interface can be found in the module's download section
on the B&R website (www.br-automation.com).

RJ45 port 1 (IF1)

RJ45 port 2 (IF2)

Interface Pinout
Pin Ethernet
1 RXD Receive data
2 RXD\ Receive data\
1
3 TXD Transmit data
4 Termination
5 Termination
6 TXD\ Transmit data\
Shielded RJ45 port 7 Termination
8 Termination

Table 145: Pinout for RJ45 port

4.5.7.8 SG3

This module is not supported on SG3 targets.

4.5.7.9 SG4

The module comes with preinstalled firmware. The firmware is also part of the B&R Automation Runtime operating
system for the PLC. If the two versions are different, the Automation Runtime firmware is loaded to the module.
The latest firmware is available automatically when updating B&R Automation Runtime.

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4.5.8 X20BC0087

4.5.8.1 General information

Established in 1979, the Modbus protocol has approved the use of Ethernet with both Modbus/TCP and Mod-
bus/UDP. Today, Modbus/TCP is an open Internet draft standard introduced by Schneider Automation to the In-
ternet Engineering Task Force (IETF), the organization responsible for Internet standardization. The Modbus ser-
vices and object model have been preserved since the original version and left unchanged for use with the TCP/
IP transmission medium.
Modbus/UDP differs from Modbus/TCP in that it uses connectionless communication via UDP/IP. The advantages
of faster and easier communication with UDP/IP also brings with it the disadvantage of requiring error detection
and correction in the application layer.
This bus controller makes it possible to connect X2X Link I/O nodes to Modbus via Ethernet. The bus controller can
be operated on B&R controllers through the use of Automation Studio or on third-party systems with Modbus/TCP
or -UDP master functionality.
• Fieldbus: Modbus/TCP, Modbus/UDP
• I/O configuration via the fieldbus
• DHCP-capable
• Bootp-capable
• Integrated double switch for efficient cabling
• Configurable I/O cycle (0.5 to 4 ms)
• Response time: <1 - 8 ms (depending on the load on the integrated switch)
• Validity check for command sequences before execution

Information:
Only the standard function model (see the respective module description) is supported when the bus
controller is used together with multi-function modules it has automatically configured itself.
All other function models are supported when configured accordingly. The B&R FieldbusDESIGNER
is available at no cost in the Downloads section of the B&R website www.br-automation.com.

4.5.8.2 Order data

Model number Short description Figure

Bus controllers
X20BC0087 X20 bus controller, Modbus/TCP or Modbus/UDP interface, in-
tegrated 2x switch, 2x RJ45 connection, order bus base, power
supply module and terminal block separately.
Required accessories
System modules for bus controllers
X20BB80 X20 bus base, for X20 base module (BC, HB, etc.) and X20 pow-
er supply module, X20 end plates X20AC0SL1/X20AC0SR1 (left
and right) included
X20PS9400 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply
X20PS9402 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply, supply not electrically isolated
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 146: X20BC0087 - Order data

4.5.8.3 Technical data

Product ID X20BC0087
Short description
Bus controller Modbus TCP/UDP slave
General information
B&R ID code 0x227C
Status indicators Module status, bus function
Diagnostics
Module status Yes, with status LED and software
Bus function Yes, with status LED and software

Table 147: X20BC0087 - Technical data

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Product ID X20BC0087
Power consumption
Bus 2.0 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Fieldbus - X2X Link Yes
Fieldbus - I/O Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Interfaces
Fieldbus Modbus TCP/UDP slave
Design 2x shielded RJ45 port (switch)
Cable length Max. 100 m between two stations (segment length)
Transfer rate 10/100 Mbit/s
Transmission
Physical interfaces 10 BASE-T/100 BASE-TX
Half-duplex Yes
Full-duplex Yes
Autonegotiation Yes
Auto-MDI / MDIX Yes
Min. cycle time 1)
Fieldbus 1 ms
X2X Link 500 μs
Synchronization between bus systems possible No
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20PS9400 or X20PS9402 power supply module separately
Order 1x X20BB80 bus base separately
Spacing 2) 37.5 +0.2 mm

Table 147: X20BC0087 - Technical data

1) The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
2) Spacing is based on the width of the X20BB80 bus base. In addition, an X20PS9400 or X20PS9402 supply module is always required for the bus controller.

4.5.8.4 LED status indicators

Figure LED Color Status Description

S/E1) Green On Indicates that there is at least one client connection
2 pulses Indicates that there are no client connections
4 pulses Indicates that the controller is waiting for an address from the DHCP server
Blinking Initialization of connected I/O modules
Red 2 pulses Watchdog timeout
3 pulses Faulty I/O module configuration data
4 pulses Indicates that the controller has detected an IP address being used twice
5 pulses Indicates a missing, defective or incorrect I/O module
6 pulses Error reading from or writing to flash memory
On Indicates a major unrecoverable fault

Table 148: LED status indicators

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Figure LED Color Status Description
L/A IFx Green Blinking Ethernet activity taking place on the RJ45 port (IF1, IF2) indicated by the respec-
tive LED
On Indicates an established connection (link), but no communication is taking place
Off Indicates that no physical Ethernet connection exists

Table 148: LED status indicators

1) The Status/Error LED "S/E" is a green/red dual LED. The LED blinks red several times immediately after startup. This is a boot message, however, and
not an error.

4.5.8.5 Operating and connection elements

LED status indicators

Network address switches

Terminal block for bus controller

and I/O supply

Modbus/TCP connection with

2x RJ45 ports for easy wiring

Figure 211: Operating and connection elements

4.5.8.6 RJ45 ports

Information about cabling X20 modules with an Ethernet interface can be found in the module's download section
on the B&R website (www.br-automation.com).

RJ45 port 1 (IF1)

RJ45 port 2 (IF2)

Interface Pinout
Pin Ethernet
1 RXD Receive data
2 RXD\ Receive data\
1
3 TXD Transmit data
4 Termination
5 Termination
6 TXD\ Transmit data\
Shielded RJ45 port 7 Termination
8 Termination

Table 149: RJ45 port - Pinout

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4.5.8.7 Modbus/TCP network address switch

Switch position Description

0x00 This switch position is the factory default setting. In this position, the address switches have no effect on system parame-
ters. The bus controller parameters in flash memory are used (IP address and port number). The bus controller is started
with factory default values if valid flash data is not present.
0x01 - 0x7F The last position of the IP address saved in flash memory is changed to the address switch value. The IP address saved
in flash memory is not changed. The port number is read from flash memory.
0x80 - 0xEF When set within this range, the bus controller runs in DHCP mode. The current hostname is then passed on to the DNS
server. A hostname is generated according to how the address switches are set.

Example The generated hostname is made up of three elements:

"br" + "mb" + address switch value (three decimal places).
This means, for example, that the following hostname is generated for address switch setting 0xD7 (dec.
215): "brmb215"
0xF0 Auto Store mode: The IP settings are taken from the DHCP or BooTP server. If the IP settings differ from the values
stored in the flash memory, then the current IP parameters are saved.
This function is only available with Firmware version >= 1.39.
0xF1 - 0xFD Reserved (same function as position 0xFF)
0xFE Initializes all bus controller parameters with default values during booting. No values are read from flash memory. The
communication parameters correspond to the values assigned with switch setting 0xFF.
0xFF Initializes all communication parameters with default values. All other bus controller parameters are read from flash mem-
ory.
Default parameters:
• IP address: 192.168.100.1
• Subnet mask: 255.255.255.0
• Gateway: 192.168.100.254
• Primary NetBIOS name: "br" + MAC address
• Secondary NetBIOS name: "br" + "mb" + address switch value (decimal)
• Port number: 502
• X2X Link configuration: 4 ms cycle time
• X2X Link cable length: 0m

Table 150: Network address switch values

4.5.8.8 Setting the IP address (default value)

Changes to the network address switches are only applied after a restart. If the bus controller is restarted with
the address switch value 0xFF, it is initialized with the IP address 192.168.100.1. This address is also the factory
default setting. The port number is set to 502 (reserved for Modbus).
This IP address can be used to establish a connection to the bus controller. The internationally unique MAC address
is listed on the housing side of the bus controller. The combination of "br" and the MAC address results in a unique
name (primary NetBIOS name) that also makes it possible to access the bus controller.
Example of the primary NetBIOS name:
MAC address: 00-60-65-00-49-02
Resulting NetBIOS name: br006065004902
This means that, without additional parameter changes, either the default IP address 192.168.100.1 or the NetBIOS
name "br+MAC" can be used to communicate with the controller.
Since NetBIOS is being used, the bus controller can only be accessed via this name if there are no intermediary
routers or gateways in the way.

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4.5.8.9 Automatic IP assignment by a DHCP server

If a network address switch setting between 0x80 and 0xEF is configured, the bus controller will attempt to request
an IP address from the DHCP server. To query this IP address, simply run a "ping" command with the hostname.
The bus controller registers this hostname on the DHCP server, which should forward it to a DNS server.
Example The hostname (DNS name) is made up of three elements:
"br" + "mb" + address switch value (three decimal places).
This means, for example, that the following hostname is generated for address switch setting
0xD7 (dec. 215): "brmb215"
If the DNS service is not available on the network, the bus controller's two NetBIOS names can also be used for
access. The secondary NetBIOS name is identical to the hostname. If the address switches are set to 0x00, it is
identical to the primary NetBIOS name. The bus controller can only be reached via its NetBIOS name if no other
routers or gateways are in the way.

4.5.8.10 Changing the IP address with the network address switches

The address switches can be used to change the last byte in the IP address configured on the bus controller. The
IP address saved in flash memory is not changed. If the address switches are set to 0x00, the bus controller applies
the IP address last saved to flash memory. Switch positions between 0x01 and 0x7F cause the last position of the
IP address (the lowest byte) to be overwritten by the value of the address switch. This provides the user a quick
and easy way to address a large number of bus controllers. In short, an IP address between 192.168.100.1 and
192.168.100.127 can be selected for a bus controller using the address switches without requiring any additional
software configuration.

4.5.8.11 Information about NetBIOS names

In addition to the hostname used to register on the DHCP server, the bus controller also has so-called NetBIOS
names. These are used to access the bus controller from a PC using its name (as opposed to its IP address). This
is only possible if no routers or gateways are in the way, however.
The primary NetBIOS name is always composed of the prefix "br" and the MAC address from the bus controller
(see 4.5.8.9 "Automatic IP assignment by a DHCP server" on page 546).
The secondary NetBIOS name corresponds to the primary NetBIOS name at address switch position 0x00. This
is necessary because there may be several bus controllers with the address switch 0x00 in a network segment.
In this case, the IP address from flash memory is used.
For all other address switch positions, the secondary NetBIOS name is generated from the network address switch
value (as in DHCP mode): "br" + "mb" + address switch value (3 decimal places).
A hostname defined explicitly by the user will be used for the secondary NetBIOS name regardless of the address
switch value.
This makes it possible to access the bus controller with the NetBIOS name configured using the address switches.
This is also possible if the controller was not configured for use with a DHCP server (address switch setting between
0x01 and 0x7F).

4.5.8.12 Saving an IP address to flash memory

The IP parameters in flash memory can be changed via the Modbus protocol, the ModbusTCP Toolbox or the
Telnet interface. The ModbusTCP Toolbox can be downloaded from the B&R website.
The IP address, subnet and gateway are all defined in the address range 0x1003 to 0x100E. Each has a length
of 4 words. The data is applied by writing the constant 0xC1 to the address 0x1140 ("Write Single Register" fc6,
addr. 0x1140, data 0xC1). The new settings are applied after the bus controller is restarted.

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4.5.9 X20BC0088

4.5.9.1 General information

EtherNet/IP is a fieldbus based on EtherNet/IP that was developed by Allen-Bradley (Rockwell Automation) and
later handed off to the Open DeviceNet Vendor Association (ODVA) as an open standard. In 1998, a working group
at ControlNet International developed a procedure for setting the published Common Industrial Protocol to Ethernet.
EtherNet/IP was published in March 2000 as an open industrial automation standard based on this procedure.
The X20BC0088 bus controller makes it possible to connect X2X Link I/O nodes to EtherNet/IP. The bus controller
can be operated via the X20IF10D1-1 interface module or by 3rd-party systems with EtherNet/IP scanner func-
tionality.
• Fieldbus: EtherNet/IP
• Integrated 3-port switch for efficient cabling
• Auto-configuration of I/O modules
• Can be configured by the scanner (master) using configuration assembly
• Web interface
• DHCP-capable
• Configurable I/O cycle (0.5 to 4 ms)
• Minimum fieldbus cycle time (also requested packet interval or RPI): 1 ms

Information:
Only the standard function model (see the respective module description) is supported when the bus
controller is used together with multi-function modules it has automatically configured itself.
The B&R FieldbusDESIGNER can be used to create configuration files (e.g. EDS files) in six easy steps.
All other function models are also supported by transferring configuration data to the bus controller
(e.g. using its web interface or the scanner via a "Configuration Assembly").
The B&R FieldbusDESIGNER is available free of charge in the download section of the B&R website
www.br-automation.com.

4.5.9.2 Order data

Model number Short description Figure

Bus controllers
X20BC0088 X20 bus controller, EtherNet/IP interface, integrated switch, web
interface 2x RJ45 connection, order bus base, power supply
module and terminal block separately.
Required accessories
System modules for bus controllers
X20BB80 X20 bus base, for X20 base module (BC, HB, etc.) and X20 pow-
er supply module, X20 end plates X20AC0SL1/X20AC0SR1 (left
and right) included
X20PS9400 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply
X20PS9402 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply, supply not electrically isolated
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 151: X20BC0088 - Order data

4.5.9.3 Technical data

Product ID X20BC0088
Short description
Bus controller EtherNet/IP adapter (slave)
General information
B&R ID code 0x26D8
Status indicators Module status, network status, bus function
Diagnostics
Module status Yes, with status LED and software status
Bus function Yes, with status LED and software status
Network status Yes, with status LED and software status

Table 152: X20BC0088 - Technical data

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Product ID X20BC0088
Power consumption
Bus 2.0 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Fieldbus - X2X Link Yes
Fieldbus - I/O Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Interfaces
Fieldbus EtherNet/IP adapter (slave)
Design 2x shielded RJ45 port (switch)
Cable length Max. 100 m between two stations (segment length)
Transfer rate 10/100 Mbit/s
Transmission
Physical interfaces 10 BASE-T/100 BASE-TX
Half-duplex Yes
Full-duplex Yes
Autonegotiation Yes
Auto-MDI / MDIX Yes
Min. cycle time 1)
Fieldbus 1 ms
X2X Link 500 μs
Synchronization between bus systems possible No
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20PS9400 or X20PS9402 power supply module separately
Order 1x X20BB80 bus base separately
Spacing 2) 37.5 +0.2 mm

Table 152: X20BC0088 - Technical data

1) The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
2) Spacing is based on the width of the X20BB80 bus base. In addition, an X20PS9400 or X20PS9402 supply module is always required for the bus controller.

4.5.9.4 LED status indicators

Figure LED Color Status Description

Mod status1) Green On There is at least one client connection.
Blinking Bus controller not yet configured.
Red On Major unrecoverable fault.
Blinking Major recoverable fault.
Green/red Blinking Initialization / self test
Net status1) Green On At least one active master (scanner) connection is established.
Blinking No active master (scanner) connection established.
Red On An IP address has been used repeatedly.
Blinking Timeout occurred on at least one connection.
Green/red Blinking Initialization / self test

Table 153: LED status indicators

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Figure LED Color Status Description
L/A IFx Green Blinking The respective LED blinks when Ethernet activity is detected on the correspond-
ing RJ45 port (IF1, IF2).
On Connection (link) established, but no communication is taking place.
Off No physical Ethernet connection exists.

Table 153: LED status indicators

1) The "Mod status" and "Net status" LEDs are green/red dual LEDs.

4.5.9.5 Operating and connection elements

LED status indicators

Network address switches

Terminal block for bus controller

and I/O supply

EtherNet/IP connection with

2x RJ45 ports for easy wiring

Figure 212: Operating and connection elements

4.5.9.6 RJ45 ports

Information about cabling X20 modules with an Ethernet interface can be found in the module's download section
on the B&R website (www.br-automation.com).

RJ45 port 1 (IF1)

RJ45 port 2 (IF2)

Interface Pinout
Pin Ethernet
1 RXD Receive data
2 RXD\ Receive data\
1
3 TXD Transmit data
4 Termination
5 Termination
6 TXD\ Transmit data\
Shielded RJ45 port 7 Termination
8 Termination

Table 154: Pinout for RJ45 port

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4.5.9.7 EtherNet/IP address switching positions

Switch position Description

0x00 The IP address saved in flash memory is used. The adapter is started via DHCP if attribute 3 (configuration control) of
the TCP/IP interface object was set to DHCP.
0x01 to 0x7F The last position of the IP address saved in flash memory is changed to the address switch value. The IP address saved
in the flash memory is not changed. All other adapter parameters are read from the flash memory and are used without
being changed.
0x80 to 0xEF The bus controller runs in this range in DHCP mode. The DNS server is informed of the current host name. A host name
is generated according to the setting of the network address switch.

Example: The generated host name is made up of three elements:

"br" + "eip" + address switch number (three decimal places)
This means that a address switch number of e.g. 0xD7 (dec. 215) would result in the following host name:
"breip215"
0xF0 to 0xFD Reserved (same function as position 0xFF).
0xFE All bus controller parameters are initialized with default values during the boot procedure. No values are read from the
flash. The communication parameters are equal to the values as with the switch setting 0xFF.
0xFF All communication parameters are initialized with default values. All other bus controller parameters are read from the
flash.

The default parameters:

• IP address: 192,168,100.1
• Network mask: 255,255,255.0
• Gateway: 192,168,100,254
• Primary NetBIOS name: "br" + MAC address
• Secondary NetBIOS name: "br" + "eip" + address switch number (decimal)
• X2X Link configuration: 1 ms cycle time
• X2X Link cable length: 0m

Table 155: Network address switches

4.5.9.8 Setting the IP address (default value)

Changes to the network address switch are only applied after a restart (power cycle). If the bus controller is restarted
with the address switch number 0xFF, it is initialized with the IP address 192.168.100.1. This address is also the
default address upon delivery.
This IP can be used to establish a connection to the bus controller. The internationally unique MAC address is
listed on the housing side of the bus controller. The combination of "br" and the MAC address results in a unique
name (primary NetBIOS name) that also makes it possible to access the bus controller.
Example for the primary NetBIOS names:
MAC address: 00-60-65-00-49-02
Resulting NetBIOS name: br006065004902
This means that, without additional parameter changes, either the default IP address 192.168.100.1 or the NetBIOS
name "br+MAC" can be used to communicate with the controller.
The bus controller can only be accessed via this name if there are no intermediary routers or gateways because
the NetBIOS method is used.

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4.5.9.9 Automatic IP assignment by DHCP server

At an address switch position between 0x80 and 0xEF, the bus controller attempts to request an IP address from
the DHCP server. To query this IP address, simply run a "ping" command with the host name. The bus controller
registers this host name on the DHCP server, which should forward it to a DNS server.
Example: The host name (DNS name) is made up of three elements:
"br" + "eip" + address switch value (three decimal places)
This means that a address switch value of e.g. 0xD7 (dec. 215) would result in the following host name:
"breip215"
If DNS service is not available on the network, the bus controller's two NetBIOS names can also be used for
access. The secondary NetBIOS name is identical to the host name; at address switch value 0x00, it is identical
with the primary NetBIOS name. The bus controller can only be reached via its NetBIOS name if no other routers
or gateways are in the way.

4.5.9.10 Changing the IP address with the network address switch

The address switches can be used to change the last position (octet) in the IP address configured on the bus
controller. The IP address saved in flash memory is not changed. If the address switches are set to 0x00, the
bus controller applies the IP address last saved to flash memory. Switch positions between 0x01 and 0x7F cause
the last position of the IP address (the lowest byte) to be overwritten by the value of the address switch. This
provides the user a quick and easy way to address a large number of bus controllers. In short, an IP address
between 192.168.100.1 and 192.168.100.127 can be selected for a bus controller using the address switches
without requiring any additional software configuration.

4.5.9.11 Saving an IP address in flash memory

The IP parameters in the flash memory can be changed via the EtherNet/IP protocol or using the Telnet interface
(see EtherNet/IP in User's Manual). If the IP address should be set via the TCP/IP object (class 0xF5), then the
new address is only saved in the flash if the instance attribute 3 (Configuration Control) of the TCP/IP object is
set at 0 (see CIP specification).

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4.5.10 X20BC00E3

4.5.10.1 General information

PROFINET (Process Field Network) is an Industrial Ethernet protocol. It uses TCP/IP and is real-time capable.
PROFINET IO was developed for real-time (RT) and synchronous communication (IRT = Isochronous Real Time).
The designations RT and IRT merely describe the real-time properties for communication taking place within
PROFINET IO. PROFINET IO defines how all data is exchanged between controllers (masters) and devices
(slaves) and how parameter settings and diagnostics are handled. The bus system is designed to exchange data
between Ethernet-based field devices using the producer/consumer model.
X20 modules or other modules that are based on X2X Link can be connected to the bus controller. Modular system
configurations are optimally supported by PROFINET. Using the device description file (GSDML format), it is very
easy to handle project configuration in the respective engineering tool from the manufacturer of the master device.
• Fieldbus: PROFINET RT
• I/O configuration via the fieldbus
• Conformance Class B
• Minimum cycle time 1 ms
• Integrated switch for cabling multiple slaves
• 100 Mbit/s full duplex mode
• Up to 1440 bytes of input data and up to 1440 bytes of output data are possible
• Web interface that has been implemented
• PROFINET diagnostics and module diagnostics during runtime from within the master environment
• Module and switch diagnostics during runtime using the Web interface or SNMP

4.5.10.2 Order data

Model number Short description Figure

Bus controllers
X20BC00E3 X20 bus controller, PROFINET interface, integrated 2x switch,
2x RJ45 connection, order bus base, power supply module and
terminal block separately.
Required accessories
System modules for bus controllers
X20BB80 X20 bus base, for X20 base module (BC, HB, etc.) and X20 pow-
er supply module, X20 end plates X20AC0SL1/X20AC0SR1 (left
and right) included
X20PS9400 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply
X20PS9402 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply, supply not electrically isolated
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 156: X20BC00E3 - Order data

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4.5.10.3 Technical data

Product ID X20BC00E3
Short description
Bus controller PROFINET RT slave
General information
B&R ID code 0xBB7D
Status indicators Module status, bus function
Diagnostics
Module status Yes, with status LED and software status
Bus function Yes, with status LED and software status
Power consumption
Bus 2.5 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Fieldbus - X2X Link Yes
Fieldbus - I/O Yes
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
GOST-R Yes
Interfaces
Fieldbus PROFINET RT slave
Design 2x shielded RJ45 port (switch)
Cable length Max. 100 m between two stations (segment length)
Transfer rate 100 Mbit/s
Transmission
Physical interfaces 100 BASE-TX
Half-duplex Yes
Full-duplex Yes
Autonegotiation Yes
Auto-MDI / MDIX Yes
Min. cycle time 1)
Fieldbus 1 ms
X2X Link 250 μs
Synchronization between bus systems possible Yes
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20PS9400 or X20PS9402 power supply module separately
Order 1x X20BB80 bus base separately
Spacing 2) 37.5 +0.2 mm

Table 157: X20BC00E3 - Technical data

1) The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
2) Spacing is based on the width of the X20BB80 bus base. In addition, an X20PS9400 or X20PS9402 supply module is always required for the bus controller.

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4.5.10.4 LED status indicators

The following table lists the status LEDs available on the bus controller. Exact blink times are specified in the timing
diagram in the next section.
Figure LED Color Status Description
MS1) Green Off The PROFINET master is in "Stop" mode.
Quad flash The bus controller does not have a valid IP address (0.0.0.0). It will wait in this
state until it is assigned an IP address from the PROFINET master or from an
external source. This state can also occur if the bus controller is being operated
in DHCP mode.
Double flash An unacknowledged alarm is pending on the bus controller.
Blinking 1 The bus controller is in the initialization phase. This boot phase is where all con-
nected I/O modules are initialized.
Blinking 3 The bus controller is configuring the connected I/O modules. The configuration
is transferred to the bus controller via the PROFINET master.
On A connection to a PROFINET master has been established. The master and
slave are both in OPERATIONAL mode and data is being exchanged between
them.
This mode also indicates that the master itself is in RUN mode.
Red Blinking 4 The bus controller has detected an error. However, it can still be corrected in the
master environment during runtime.
Blinking 1 The bus controller has detected an error. This error cannot be corrected during
runtime; a restart is required.
BF1) Green Blinking 2 Device identification ("blink" function in step 7 when searching for existing Eth-
ernet stations).
On A connection to a PROFINET master has been established.
Red On Not connected to a PROFINET Master
L/A IFx Green Off No physical Ethernet connection exists.
Blinking The respective LED blinks when Ethernet activity is detected on the correspond-
ing RJ45 port (IF1, IF2).
On Connection (link) established, but no communication is taking place.

Table 158: LED status indicators

1) The "MS" and "BF" LEDs are green/red dual LEDs.

Blinking 1
150

Blinking 2
250

Blinking 3
500

Blinking 4
1000

Quad flash
300 300 300 300 300 300 300 1500

Double flash
300 300 300 1500

All times in ms

Figure 213: Status LEDs - Blinking patterns

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4.5.10.5 Operating and connection elements

LED status indicator

Node number switches

Terminal block for bus controller

and I/O supply

PROFINET RT connection with

2 x RJ45 connectors for simple wiring

Figure 214: Operating and connection elements

4.5.10.6 RJ45 ports

Information about cabling X20 modules with an Ethernet interface can be found in the module's download section
on the B&R website (www.br-automation.com).

RJ45 port P1 (IF1) P1

RJ45 port P2 (IF2) P2

Interface Pinout
Pin Ethernet
1 RXD Receive data
2 RXD\ Receive data\
1
3 TXD Transmit data
4 Termination
5 Termination
6 TXD\ Transmit data\
Shielded RJ45 port 7 Termination
8 Termination

Table 159: Pinout for RJ45 port

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4.5.10.7 Node number switches

The bus controller has 2 node number switches. The bus controller can be set to different operating modes using
certain, pre-defined switch positions. They can also be used to configure various additional parameters (PROFINET
device name, DHCP mode, etc.).
Switch position Description
0x00 All parameters are loaded from flash memory: Default PROFINET initialization via the DCP protocol (factory state)
0x01 - 0xEF These switch positions generate a valid PROFINET device name. This name is composed as follows: "brpnXXX".
XXX refers to the decimal value of the node number switch position. The system automatically adds any necessary
leading zeros.
0xF0 Clears flash (see 4.5.10.8 "Erasing flash memory" on page 556)
0xF1 - 0xFD Reserved, switch position not permitted
0xFE IP address via DHCP server
0xFF All parameters set to default: PME mode

Table 160: X20BC00E3 - Node numbers

Default PROFINET factory state - Node number switch position 0x00

Parameter Value
IP address 0.0.0.0
Subnet mask 0.0.0.0
Gateway 0.0.0.0
PROFINET device name "" ... no factory default name

Table 161: Factory settings: Node number switch position 0x00

Default parameters - Node number switch position 0xFF

Parameters cannot be changed by the master in node switch position 0xFF.
Parameter Value
IP address 192,168,100.1
Subnet mask 255,255,255.0
Gateway 192,168,100,254
PROFINET device name x20bc00e3

Table 162: Default parameters: Node number switch position 0xFF

4.5.10.8 Erasing flash memory

Erasing flash memory using switch position 0xF0 returns the bus controller to its factory state.
Procedure
1. Turn off the power supply to the bus controller.
2. Set the node number to 0xF0.
3. Turn the power supply to the bus controller back on.
4. Wait until the "MS" LED flashes green for 5 s. The node number switch must be set to 0x00 and then back
to 0xF0 within this time window of 5 seconds (rotate the top switch).
5. Wait until the "MS" LED blinks with a red double-flash (flash has been cleared).
6. Turn off the power supply to the bus controller.
7. Set the desired node number (0x00 - 0xEF)
8. Turn the power supply to the bus controller back on.
9. The bus controller boots with the configured node number.

4.5.10.9 Web interface

The integrated Web interface gives the user an overview of the bus controller's network parameters, the configured
I/O modules and the switch configuration. The starting page includes information regarding specific bus controller
settings such as IP address, host name and the PROFINET device name. In addition, the web page provides
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information about the current firmware version. Information concerning module diagnostics is incorporated into a
tree structure. Expanding and collapsing the individual module nodes provides an overview of the configured I/O
modules. In addition, various package counters are read from the integrated switch. This makes diagnosing errors
on the network quick and easy.
Network parameters concerning the bus controller itself can be read, but they cannot be modified. The bus
controller's IP configuration is handled during booting or by the PROFINET master when a connection is estab-
lished.
Each page of the Web interface contains help information that describes the functions and parameters displayed
on that page. The link to this information can be found in the upper right corner of the page in the form of a question
mark.
A connection to the web interface is established by entering the current IP address or the unique host name in
a Web browser. Some functions require authentication.
The host name is composed of a predefined text and a unique MAC address. For example, if the bus controller
has the MAC address 00:60:65:11:22:33, this will result in the following host name: br006065112233.
Default parameters for the web interface
IP address: 192,168,100.1
User name: admin
Password: B&R

Information:
Take note of the node number switch position.
Be aware that the authentication parameters are case sensitive.

Figure 215: X20BC00E3 Web interface

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4.5.11 X20BC00G3

4.5.11.1 General information

EtherCAT is an Ethernet-based fieldbus developed by Beckhoff. The protocol is suitable for hard and soft real-time
requirements in automation technology. In addition to a ring structure, which becomes logically necessary because
of the summation frame telegram used, the EtherCAT technology also physically supports topologies such as line,
tree, star (limited) and combinations of these topologies. B&R's X20BC80G3 (expandable bus controller module)
and X20HB88G0 (stand alone junction base module) are available for implementing these topologies.
EtherCAT slave devices take the data designated for them from a telegram as it is passing through the device.
Input data is also inserted in the telegram as it is passing through. The X20BC00G3 bus controller allows X2X
Link I/O modules to be coupled to EtherCAT and can be operated on any EtherCAT master system. A transition
between IP20 and IP67 protection outside of the control cabinet is possible by aligning X20, X67 or XV modules
one after the other as needed at distances up to 100 m.
Master systems without FoE (File Access over EtherCAT) support require an appropriate configuration tool to
transfer the configuration (optional).
• Fieldbus: EtherCAT
• Auto-configuration of I/O modules
• I/O configuration and firmware update via the fieldbus (FoE)
• Full support of the modular slice concept via CoE (CANopen over EtherCAT)
• Configurable I/O cycle (0.2 - 4 ms)
• Synchronization between the fieldbus and X2X Link
• X20BC80G3 module type with two additional output ports (X20HB28G0)

Information:
Only the default function model is supported (see respective module description) when the bus con-
troller automatically configures multi-function modules.
All other function models are supported when configured accordingly (see EtherCAT user's manual).
The easy-to-use B&R FieldbusDESIGNER can help in this regard and is available for free download
from www.br-automation.com/designer.

4.5.11.2 Order data

Model number Short description Figure

Bus controllers
X20BC00G3 X20 bus controller, EtherCAT interface, 2x RJ45 connection, or-
der bus base, power supply module and terminal block sepa-
rately.
Required accessories
System modules for bus controllers
X20BB80 X20 bus base, for X20 base module (BC, HB, etc.) and X20 pow-
er supply module, X20 end plates X20AC0SL1/X20AC0SR1 (left
and right) included
X20PS9400 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply
X20PS9402 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply, supply not electrically isolated
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 163: X20BC00G3 - Order data

4.5.11.3 Technical data

Product ID X20BC00G3
Short description
Bus controller EtherCAT slave
General information
B&R ID code 0xAC23
Status indicators Module status, bus function

Table 164: X20BC00G3 - Technical data

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 X20 system modules • Bus controllers • X20BC00G3
Product ID X20BC00G3
Diagnostics
Module status Yes, with status LED and software status
Bus function Yes, with status LED and software status
Power consumption
Bus 1.68 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Fieldbus - X2X Link Yes
Fieldbus - I/O Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Interfaces
Fieldbus EtherCAT slave
Design 2x shielded RJ45 port
Cable length Max. 100 m between two stations (segment length)
Transfer rate 100 Mbit/s
Transmission
Physical interfaces 100 BASE-TX
Half-duplex Yes
Full-duplex Yes
Autonegotiation Yes
Auto-MDI / MDIX Yes
Min. cycle time 1)
Fieldbus 200 μs
X2X Link 200 μs
Synchronization between bus systems possible Yes
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation 0 to 55°C
Vertical installation 0 to 50°C
Derating -
Storage -25 to 70°C
Transport -25 to 70°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20PS9400 or X20PS9402 power supply module separately
Order 1x X20BB80 bus base separately
Spacing 2) 37.5 +0.2 mm

Table 164: X20BC00G3 - Technical data

1) The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
2) Spacing is based on the width of the X20BB80 bus base. In addition, an X20PS9400 or X20PS9402 supply module is always required for the bus controller.

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4.5.11.4 LED status indicators

Figure LED Color Status Description

STATUS1) Green On The bus controller is OPERATIONAL.
Blinking PRE-OPERATIONAL status
Single flash SAFE-OPERATIONAL status
Flickering The bus controller has started and is not yet in INIT status or it is in BOOTSTRAP
status (e.g.while downloading firmware).
Off INIT status
Red On A critical communication or application error has occurred.
Blinking Invalid configuration data
Single flash The bus controller has an internal error and changed the EtherCAT status on
its own
Double flash Watchdog timeout (process data watchdog or EtherCAT watchdog)
Flickering Error in the start procedure (INIT status has been achieved, but the error indicator
bit in the AL status register is set)
Off No error
L/A IN Green Blinking The respective LED blinks when Ethernet activity is present (PORT OPEN) on
L/A OUT the corresponding RJ45 port (IN, OUT).
On Connection (link) established, however no communication (PORT OPEN).
Off No physical Ethernet connection exists (PORT CLOSED).

Table 165: LED status indicators

1) The "STATUS" LED is a green/red dual LED and is used to indicate EtherCAT states ERROR and RUN.

Double flash
200 200 200 1000

Single flash
200 1000

Blinking
200 200

Flickering
All times in ms

Figure 216: Status LEDs - Blinking patterns

4.5.11.5 Operating and connection elements

LED status indicator

Network address switches

Terminal block for bus controller

and I/O supply

EtherCAT connection with

2 x RJ45 connectors for simple wiring

Figure 217: Operating and connection elements

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 X20 system modules • Bus controllers • X20BC00G3

4.5.11.6 RJ45 ports

Information about cabling X20 modules with an Ethernet interface can be found in the module's download section
on the B&R website (www.br-automation.com).

IN (IF1) IN

OUT (IF2) OUT

Interface Pinout
Pin Ethernet
1 TXD Transmit data
2 TXD\ Transmit data\
1
3 RXD Receive data
4 Termination
5 Termination
6 RXD\ Receive data\
Shielded RJ45 port 7 Termination
8 Termination

Table 166: Pinout for RJ45 port

4.5.11.7 EtherCAT network address switch

A slave alias address can be set using the two network address switches on the bus controller. During the initial-
ization phase (during start-up), the bus controller writes the value of the address switch to the ESC register 0x12
or 0x13. However, the value is only accepted in the register if the value of the switch value is between 0x00 and
0xFA (decimal 250).
Switch position Description
0x00 to 0xFA Writes the address switch value to the "Station Alias" register.
0xFB to 0xFE Address switch value not used. ESC Alias registers not changed.
0xFF Address switch value not used. ESC Alias registers not changed. The bus controller boots with the default values
if the address switch is set to the value "0xFF" before a restart. All set parameters remain unchanged in flash
memory.

Table 167: Addresses

The master determines whether the alias address is used for the slave addressing by setting the corresponding
bit in the ESC DL control register (bit 24).

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4.5.12 X20BC0143-10

4.5.12.1 General information

CAN (Controller Area Network) systems are widespread in the field of automation technology. CAN topology is
based on a line structure and uses twisted pair wires for data transfer. CANopen is a higher-layer protocol based
on CAN. This standardized protocol offers highly flexible configuration possibilities.
The bus controller makes it possible to connect up to 253 X2X Link I/O nodes to CANopen. A transition between
IP20 and IP67 protection outside of the control cabinet is possible by aligning X20, X67 or XV modules one after
the other as needed at distances up to 100 m. All CANopen transmission types such as synchronous, event and
polling modes are supported together with PDO linking, life/node guarding, emergency objects, and much more.
• Fieldbus: CANopen
• Auto-configuration of I/O modules
• I/O configuration via the fieldbus (also supported by the B&R FieldbusDESIGNER)
• Constant response times even with large amounts of data (max. 32 Rx and 32 Tx PDOs)
• Configurable I/O cycle (0.5 - 4 ms)
• Possible to configure the transfer rate or have it detected automatically
• Heartbeat consumer and producer
• Emergency producer
• 2x SDO server, NMT slave
• Simple bootup (autostart)
• Terminal access via the serial interface on the X20PS9400

Information:
Only the standard function model (see the respective module description) is supported when the bus
controller is used together with multi-function modules it has automatically configured itself.
The B&R FieldbusDESIGNER can be used to create configuration files (e.g. DCF files) in six easy steps.
All other function models are also supported by transferring configuration data to the bus controller
(e.g. from the master environment with an SDO download or via the serial interface).
The B&R FieldbusDESIGNER is available free of charge in the download section of the B&R website
www.br-automation.com.

4.5.12.2 Order data

Model number Short description Figure

Bus controllers
X20BC0143-10 X20 bus controller, CANopen interface, 9-pin DSUB, config-
uration supported by the B&R FieldbusDESIGNER, order 1x
7AC911.9 connector separately. Order bus base, power supply
module and terminal block separately.
Required accessories
System modules for bus controllers
X20BB80 X20 bus base, for X20 base module (BC, HB, etc.) and X20 pow-
er supply module, X20 end plates X20AC0SL1/X20AC0SR1 (left
and right) included
X20PS9400 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply
X20PS9402 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply, supply not electrically isolated
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed
Optional accessories
Infrastructure components
0AC912.9 Bus adapter, CAN, 1 CAN interface
0AC913.92 Bus adapter, CAN, 2 CAN interfaces, including 30 cm attach-
ment cable (DSUB)
7AC911.9 Bus connector, CAN

Table 168: X20BC0143-10 - Order data

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4.5.12.3 Technical data

Product ID X20BC0143-10
Short description
Bus controller CANopen slave
General information
B&R ID code 0xAD3E
Status indicators Module status, bus function, data transfer
Diagnostics
Module status Yes, with status LED and software status
Bus function Yes, with status LED and software status
Data transfer Yes, with status LED
Power consumption
Bus 1.5 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Fieldbus - X2X Link No
Fieldbus - I/O Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
GOST-R Yes
Interfaces
Fieldbus CANopen slave
Design 9-pin male DSUB connector
Max. distance 1000 m
Transfer rate Max. 1 Mbit/s
Determination of transfer rate Automatic transfer rate detection or fixed rate setting
Min. cycle time 1)
Fieldbus No limitations
X2X Link 500 μs
Synchronization between bus systems possible No
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation 0 to 55°C
Vertical installation 0 to 50°C
Derating -
Storage -25 to 70°C
Transport -25 to 70°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20PS9400 or X20PS9402 power supply module separately
Order 1x X20BB80 bus base separately
Spacing 2) 37.5 +0.2 mm

Table 169: X20BC0143-10 - Technical data

1) The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
2) Spacing is based on the width of the X20BB80 bus base. In addition, an X20PS9400 or X20PS9402 supply module is always required for the bus controller.

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4.5.12.4 LED status indicators

Figure LED Color Status Description

MS 1) Green Off No power supply
Flashing 5 s window for deleting all configuration settings
On Boot procedure OK, I/O modules OK
Red Double flash Successfully erased flash memory
Triple flash Successfully saved transfer rate
Quad flash Successfully saved configuration
On I/O modules: Error message or incorrect configuration
RUN Green Off No power supply
Single flash STOP mode
Triple flash Firmware download in progress
Blinking PREOPERATIONAL mode
On OPERATIONAL mode
ERR Red Off No power supply or everything is OK
Single flash CAN warning limit reached
Double flash Node guarding / heartbeat error
Blinking Invalid node number or configuration
On Bus errors: Bus off
RUN/ERR Green/red Flickering Transfer rate detection in progress
TxD Yellow Off The bus controller is not transmitting any data via the CANopen fieldbus
On The bus controller is transmitting data via the CANopen fieldbus

Table 170: LED status indicators

1) The "MS" LED is a green/red dual LED. The LED blinks red several times immediately after startup. This is a boot message, however, and not an error.

quad Flash
200 200 200 200 200 200 200 1000

triple Flash
200 200 200 200 200 1000

double Flash
200 200 200 1000

single Flash
200 1000

blinkend
200 200
3
blitzend
500

grün/rot
Flickering
50
All times in ms

Figure 218: Status LEDs - Blinking patterns

4.5.12.5 Operating and connection elements

LED status indicator

Node number switches

Terminal block for bus controller

and I/O supply

CANopen interface

Figure 219: Operating and connection elements

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4.5.12.6 CAN bus interface

The CAN bus interface is a 9-pin DSUB plug.

Interface Pin CAN
1 Reserved
2 CAN_L CAN low
3 CAN_GND CAN ground
1 4 Reserved
6
5 Reserved
9 6 Reserved
5 7 CAN_H CAN high
8 Reserved
9 Reserved

Table 171: CAN bus interface - Pinout

4.5.12.7 Node number and transfer rate

Node numbers and transfer rates are configured using the two bus controller number switches.
The transfer rate can be specified in two ways:
• Automatic detection by bus controller (see 4.5.12.8 "Automatic transfer rate detection" on page 566)
• Fixed definition by user (see 4.5.12.9 "Setting the transfer rate" on page 566)

Switch position Node number Transfer rate

0x00 Not allowed -
0x01 - 0x7F 1 - 127 Automatically set by the bus controller (default) or fixed setting
by the user
0x80 - 0x88 - Sets a fixed transfer rate
0x89 - Sets automatic transfer rate detection
0x8A - 0x8F Not allowed -
0x90 Clearing the parameters -
See section 4.5.12.11 "Deleting parameters" on page 568
0x91 Not allowed -
0x92 Save configuration -
See section 4.5.12.10 "Save auto-
matic configuration" on page 567
0x93 - 0xFF Not allowed -

Table 172: Node numbers and transfer rate

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4.5.12.8 Automatic transfer rate detection

After booting, the bus controller goes into "Listen only" mode. This means the bus controller behaves passively
on the bus and only listens.
The bus controller attempts to receive valid objects. If receive errors occur, the controller switches to the next
transfer rate in the lookup table.
If no objects are received, all transfer rates are tested cyclically. This procedure is repeated until valid objects are
received.
Lookup table
The controller tests the transfer rate according to this table. Beginning with the starting transfer rate (1000 kbit/s),
the controller switches to the next lower transfer rate. At the end of the table, the bus controller restarts the search
from the beginning.
Transfer rate
1000 kbit/s
800 kbit/s
500 kbit/s
250 kbit/s
125 kbit/s
100 kbit/s
50 kbit/s
20 kbit/s
10 kbit/s

Table 173: Transfer rate lookup table

4.5.12.9 Setting the transfer rate

The bus controller will detect the transfer rate automatically by default. Switch positions 0x80 - 0x88 can be used
to set a fixed transfer rate, or 0x89 can be used to enable automatic transfer rate detection.
Switch position Transfer rate
0x80 1000 kbit/s
0x81 800 kbit/s
0x82 500 kbit/s
0x83 250 kbit/s
0x84 125 kbit/s
0x85 100 kbit/s
0x86 50 kbit/s
0x87 20 kbit/s
0x88 10 kbit/s
0x89 Automatic transfer rate detection

Table 174: Possible transfer rates

Programming the transfer rate

1. Turn off the power supply to the bus controller.
2. Define the transfer rate to be programmed by setting the node numbers (0x80 - 0x89)
3. Turn on the power supply to the bus controller.
4. Wait until the "MS" LED blinks with a red triple-flash (transfer rate is now programmed).
5. Turn off the power supply to the bus controller.
6. Set the desired node number (0x01 - 0x7F).
7. Turn on the power supply to the bus controller.
8. The bus controller now boots with the set node number and the programmed transfer rate.

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4.5.12.10 Save automatic configuration

The node number position 0x92 can be used to save automatically generated configurations. This makes it possible
to work with a standardized configuration without having to adapt the application to changes associated with service
work or different development stages for example.
1. Turn off the power supply to the bus controller.
2. Set the node number to 0x90.
3. Turn on the power supply to the bus controller.
4. Wait until the "MS" LED starts blinking green (100 ms on / 200 ms off).
5. The node number switch must be set to 0x00 and then back to 0x90 within this time window of 5 seconds
(rotate the top switch).
6. Wait until the "MS" LED blinks with a red double-flash (parameters have been cleared).
7. Turn off the power supply to the bus controller.
8. Set the node number to 0x92.
9. Turn on the power supply to the bus controller.
10.Wait until the "MS" LED starts blinking green (100 ms on / 200 ms off).
11. The node number switch must be set to 0x02 and then back to 0x092 within this time window of 5 seconds
(rotate the top switch).
12.Wait until the "MS" LED blinks with a red quad-flash (parameters have been saved).
13.Turn off the power supply to the bus controller.
14.Set the desired node number (0x01 - 0x7F).
15.Turn on the power supply to the bus controller.
16.The bus controller boots with the set node number and automatic transfer rate detection.

Information:
A mapping tool for decoding the saved PDO mapping is available in the Download section of the B&R
website (www.br-automation.com).

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4.5.12.11 Deleting parameters

Various parameters can be stored in the bus controller's flash memory:

• Communication parameters
• Vendor-specific parameters
• Application parameters (device profile)
• Fixed transfer rate
Deleting these parameters using switch position 0x90 returns the bus controller to its factory settings.

Clearing the parameters listed above

1. Turn off the power supply to the bus controller.
2. Set the node number to 0x90.
3. Turn on the power supply to the bus controller.
4. Wait until the "MS" LED starts blinking green (100 ms on / 200 ms off). The node number switch must be set
to 0x00 and then back to 0x090 within this time window of 5 seconds (rotate the top switch).
5. Wait until the "MS" LED blinks with a red double-flash (parameters have been cleared).
6. Turn off the power supply to the bus controller.
7. Set the desired node number (0x01 - 0x7F)
8. Turn on the power supply to the bus controller.
9. The bus controller boots with the set node number and automatic transfer rate detection.

4.5.12.12 Additional documentation and import files (EDS)

Additional documentation about bus controller functions as well as the necessary import files for the master engi-
neering tool are available in the Downloads section of the B&R website (www.br-automation.com).

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 X20 system modules • Bus controllers System modules • Brief information

4.6 Bus controllers System modules

The X20 system bus controllers are made up of a bus controller fieldbus interface, a bus controller system module
and an X20TB12 terminal block.
Bus controller system modules include the base module and the supply modules.

4.6.1 Brief information

Product ID Short description on page
X20BB80 X20 bus base for X20 base module (BC, HB, ...) and X20 supply module, X20AC0SL1/X20AC0SR1 X20 end 570
plates left and right included
X20PS9400 X20 supply module for bus controller and internal I/O supply, X2X Link supply 572
X20PS9402 X20 supply module, for bus controller and internal I/O supply, X2X Link supply, supply not electrically isolated 578

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4.6.2 X20BB80

4.6.2.1 General information

The following modules are used on the X20BB80 bus module:

• X20 base module (BC, HB, etc.)
• X20 supply module
The left and right end plates are included in the delivery.
• X20 bus base

4.6.2.2 Order data

Model number Short description Figure

System modules for bus controllers
X20BB80 X20 bus base for X20 base module (BC, HB, ...) and X20 supply
module, X20AC0SL1/X20AC0SR1 X20 end plates left and right
included

Table 175: X20BB80 - Order data

4.6.2.3 Technical data

Product ID X20BB80
Short description
Bus module Bus base - backplane for bus controller fieldbus interface and bus controller supply module
General information
Power consumption
Bus 0.35 W
Internal I/O -
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
I/O supply
Nominal voltage 24 VDC
Permitted contact load 10.0 A
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0,5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C

Table 176: X20BB80 - Technical data

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Product ID X20BB80
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Left and right X20 end plates included in delivery
Spacing 37.5 +0.2 mm

Table 176: X20BB80 - Technical data

4.6.2.4 Voltage routing

+24 VDC
GND

Figure 220: Voltage routing

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4.6.3 X20PS9400

4.6.3.1 General information

The supply module is used together with an X20 bus controller. It is equipped with a feed for the bus controller,
the X2X Link and the internal I/O supply.
• Supply for the bus controller, X2X Link and internal I/O supply
• Feed and bus controller / X2X Link supply electrically isolated
• Redundancy of bus controller / X2X Link supply possible by operating multiple supply modules simultane-
ously
• Service interface (RS232)

4.6.3.2 Order data

Model number Short description Figure

System modules for bus controllers
X20PS9400 X20 supply module for bus controller and internal I/O supply,
X2X Link supply
Required accessories
System modules for bus controllers
X20BB80 X20 bus base, for X20 base module (BC, HB, etc.) and X20 pow-
er supply module, X20 end plates X20AC0SL1/X20AC0SR1 (left
and right) included
System modules for expandable bus controllers
X20BB81 X20 bus base, for X20 base module (BC, HB, etc.) and X20
power supply module, with one expansion slot for an X20 add-
on module (IF, HB, etc.), X20 locking plates (left and right)
X20AC0SL1/X20AC0SR1 included
X20BB82 X20 bus base, for X20 base module (BC, HB, etc.) and X20
power supply module, with 2 expansion slots for 2 X20 add-
on modules (IF, HB, etc.), X20 locking plates (left and right)
X20AC0SL1/X20AC0SR1 included
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 177: X20PS9400 - Order data

4.6.3.3 Technical data

Product ID X20PS9400
Brief description
Power supply module 24 VDC supply module for bus controller, X2X Link supply and I/O
Interfaces 1x RS232 service interface
General information
B&R ID code 0x1F8C
Status indicators Overload, operating status, module status, RS232
Diagnostics
Module run/error Yes, using status LED and software
RS232 data transfer Yes, using status LED
Overload Yes, using status LED and software
Power consumption 1)
Bus 1.42 W
Internal I/O 0.6 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Bus - RS232 No
I/O feed - I/O supply No
BC/X2X Link feed - BC/X2X Link supply Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Bus controller / X2X Link supply input
Input voltage 24 VDC -15% / +20%
Input current Max. 0.7 A
Fuse Integrated, cannot be replaced
Reverse polarity protection Yes

Table 178: X20PS9400 - Technical data

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Product ID X20PS9400
Bus controller / X2X Link supply output
Nominal output power 7.0 W
Parallel operation Yes 2)
Redundant operation Yes
Overload behavior Short circuit / temporary overload protection
Input I/O supply
Input voltage 24 VDC -15% / +20%
Fuse Required line fuse: Max. 10 A, slow-blow
Reverse polarity protection No
Output I/O supply
Rated output voltage 24 VDC
Behavior if a short circuit occurs Required line fuse
Permitted contact load 10.0 A
Interfaces
Service interface
Signal RS232
Design Connection made using 12-pin X20TB12 terminal block
Max. transfer rate 115.2 kbit/s
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BB8x bus base separately
Spacing 12.5 +0.2 mm

Table 178: X20PS9400 - Technical data

1) The specified values are maximum values. The exact calculation is also available for download as a data sheet with the other module documentation on
the B&R website.
2) In parallel operation, only 75% of the rated power can be assumed. It is important to make sure that all power supplies operating in parallel are switched
on and off at the same time.

4.6.3.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Double flash LED indicates one of the following states:
• The bus controller / X2X Link supply for the power supply is overloaded
• I/O supply too low
• Input voltage for bus controller / X2X Link supply too low
e+r Red on / Green single flash Invalid firmware
l Red Off The bus controller / X2X Link supply is within the valid limits
On The bus controller / X2X Link supply for the power supply is overloaded
S Yellow Off No data traffic via service interface
On Data is being transmitted via the service interface

Table 179: LED status indicators

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4.6.3.5 Pinout

r e

X20 PS 9400
S I

RS232 TxD RS232 RxD

Reserved RS232 GND

Reserved Reserved

+24 V BC/X2X L. +24 V I/O

+24 V BC/X2X L. +24 V I/O

GND GND

Figure 221: Pinout

4.6.3.6 Using the service interface

The RS232 service interface is not for use in a machine or system application. It is only intended to be used to
update the firmware on various bus controllers and X2X modules as well as to save settings.

4.6.3.7 Connection examples

With 2 separate supplies

PS

10 A slow-blow
BC/X2X Link + + I/O
Power supply _ _ Power supply

+24 VDC
GND

Figure 222: Connection example with 2 separate supplies

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 X20 system modules • Bus controllers System modules • X20PS9400

With a supply and jumper

PS

Jumper

10 A slow-blow
+ I/O-
_ Power supply

+24 VDC
GND

Figure 223: Connection example with a supply and jumper

4.6.3.8 Derating

The rated output current for the supply is 7.0 W. Derating must be taken into consideration based on mounting
orientation.
Installation position

Horizontal

Vertical

7
Nominal output power

4
[W]

0
-25 40 45 50 55 60

Ambient temperature [°C]

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4.6.3.9 Register description

4.6.3.9.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
0 Module status USINT ●
StatusInput01 Bit 0
StatusInput02 Bit 2
2 SupplyCurrent USINT ●
4 SupplyVoltage USINT ●

4.6.3.9.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
0 0 Module status UINT ●
StatusInput01 Bit 0
StatusInput02 Bit 2
2 2 SupplyCurrent UINT ●
4 4 SupplyVoltage UINT ●

1) The offset specifies the position of the register within the CAN object.

4.6.3.9.3 Module status

Name:
Module status
The following voltage and current states of the module are monitored in this register:
Bus supply current: A bus supply current of >2.3A is displayed as a warning.
Bus supply voltage: A bus supply voltage of <4.7V is displayed as a warning.
24 VDC I/O supply voltage: An I/O supply voltage of <20.4 V is displayed as a warning.
Function model Data type Value
0 - Standard USINT See bit structure.
254 - Bus controller UINT See bit structure.

Bit structure:
Bit Name Value Information
0 StatusInput01 0 No error
1 Warning - overcurrent (>2.3 A) or undervoltage (<4.7 V)
1 Reserved 0
2 StatusInput02 0 I/O supply above the warning level of 20.4 V
1 I/O supply below the warning level of 20.4 V
3-x Reserved 0

4.6.3.9.4 Bus supply current

Name:
SupplyCurrent
This register displays the bus supply current measured at a resolution of 0.1 A.
Function model Data type
0 - Standard USINT
254 - Bus controller UINT

4.6.3.9.5 Bus supply voltage

Name:
SupplyVoltage
This register displays the bus supply voltage measured at a resolution of 0.1 V.
Function model Data type
0 - Standard USINT
254 - Bus controller UINT

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4.6.3.9.6 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.6.3.9.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
2 ms

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X20 system modules • Bus controllers System modules • X20PS9402

4.6.4 X20PS9402

4.6.4.1 General information

The supply module is used together with an X20 bus controller. It is equipped with a feed for the bus controller,
the X2X Link and the internal I/O supply.
The module is designed to supply power for smaller X20 systems. Potential groups are able to be formed. An
expansion or redundancy of the X2X Link with the X20PS3300 or X20PS3310 supply module is not possible.
Expansion of the X20 system with a bus transmitter is not permitted either.
• Supply for the bus controller, X2X Link and internal I/O supply
• Low-cost supply module for small X20 system
• Feed and bus controller / X2X Link supply not electrically isolated
• Expansion or redundancy of bus controller / X2X Link supply not possible by operating multiple supply
modules simultaneously

4.6.4.2 Order data

Model number Short description Figure

System modules for bus controllers
X20PS9402 X20 supply module, for bus controller and internal I/O supply,
X2X Link supply, supply not electrically isolated
Required accessories
System modules for bus controllers
X20BB80 X20 bus base, for X20 base module (BC, HB, etc.) and X20 pow-
er supply module, X20 end plates X20AC0SL1/X20AC0SR1 (left
and right) included
System modules for expandable bus controllers
X20BB81 X20 bus base, for X20 base module (BC, HB, etc.) and X20
power supply module, with one expansion slot for an X20 add-
on module (IF, HB, etc.), X20 locking plates (left and right)
X20AC0SL1/X20AC0SR1 included
X20BB82 X20 bus base, for X20 base module (BC, HB, etc.) and X20
power supply module, with 2 expansion slots for 2 X20 add-
on modules (IF, HB, etc.), X20 locking plates (left and right)
X20AC0SL1/X20AC0SR1 included
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 180: X20PS9402 - Order data

4.6.4.3 Technical data

Product ID X20PS9402
Brief description
Power supply module 24 VDC supply module for bus controller, X2X Link supply and I/O
General information
B&R ID code 0xA389
Status indicators Operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Overload Yes, using status LED and software
Power consumption 1)
Bus 1.44 W
Internal I/O 0.6 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
I/O feed - I/O supply No
BC/X2X Link feed - BC/X2X Link supply No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Bus controller / X2X Link supply input
Input voltage 24 VDC -15% / +20%
Input current Max. 0.7 A
Fuse Integrated, cannot be replaced

Table 181: X20PS9402 - Technical data

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Product ID X20PS9402
Reverse polarity protection Yes
Bus controller / X2X Link supply output
Nominal output power
Horizontal installation 7.0 W at 45°C and 5.0 W at 55°C
Vertical installation 7.0 W at 40°C and 5.0 W at 50°C
Parallel operation No
Redundant operation No
Overload behavior Short circuit / temporary overload protection
Input I/O supply
Input voltage 24 VDC -15% / +20%
Fuse Required line fuse: Max. 10 A, slow-blow
Reverse polarity protection No
Output I/O supply
Rated output voltage 24 VDC
Behavior if a short circuit occurs Required line fuse
Permitted contact load 10.0 A
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BB8x bus base separately
Spacing 12.5 +0.2 mm

Table 181: X20PS9402 - Technical data

1) The values specified here are maximum values. The exact calculation is also available for download as a data sheet with the other module documentation
on the B&R website.

4.6.4.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Double flash LED indicates one of the following states:
• The bus controller / X2X Link supply for the power supply is overloaded
• I/O supply too low
• Input voltage for bus controller / X2X Link supply too low
e+r Red on / Green single flash Invalid firmware

Table 182: LED status indicators

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X20 system modules • Bus controllers System modules • X20PS9402

4.6.4.5 Pinout

r e

X20 PS 9402
I

Reserved Reserved

Reserved Reserved

Reserved Reserved

+24 V BC/X2X L. +24 V I/O

+24 V BC/X2X L. +24 V I/O

GND GND

Figure 224: X20PS9402 - Pinout

4.6.4.6 Connection examples

With 2 separate supplies

PS

10 A slow-blow
BC/X2X Link + + I/O
Power supply _ _ Power supply

+24 VDC
GND

Figure 225: Connection example with 2 separate supplies

With a supply and jumper

PS

Jumper

10 A slow-blow
+ I/O-
_ Power supply

+24 VDC
GND

Figure 226: Connection example with a supply and jumper

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4.6.4.7 Derating for bus controller / X2X Link supply

The rated output current for the bus controller / X2X Link supply is 7.0 W. Derating must be taken into consideration
based on mounting orientation.
Installation position

Horizontal

Vertical

Nominal output power

BC / X2X Link supply
5

4
[W]

0
-25 40 45 50 55 60

Ambient temperature [°C]

Figure 227: Derating for bus controller / X2X Link supply

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4.6.4.8 Register description

4.6.4.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
0 Module status USINT ●
StatusInput01 Bit 0
StatusInput02 Bit 2
4 SupplyVoltage USINT ●

4.6.4.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
0 0 Module status UINT ●
StatusInput01 Bit 0
StatusInput02 Bit 2
4 4 SupplyVoltage UINT ●

1) The offset specifies the position of the register within the CAN object.

4.6.4.8.3 Module status

Name:
Module status
The following module supply voltages are monitored in this register:
Bus supply voltage: A bus supply voltage of <4.7V is displayed as a warning.
24 VDC I/O supply voltage: An I/O supply voltage of <20.4 V is displayed as a warning.
Function model Data type Value
0 - Standard USINT See bit structure.
254 - Bus controller UINT See bit structure.

Bit structure:
Bit Name Value Information
0 StatusInput01 0 No error
1 Bus supply warning - Undervoltage (<4.7V)
1 Reserved 0
2 StatusInput02 0 I/O supply above the warning level of 20.4 V
1 I/O supply below the warning level of 20.4 V
3-x Reserved 0

4.6.4.8.4 Bus supply voltage

Name:
SupplyVoltage
This register displays the bus supply voltage measured at a resolution of 0.1 V.
Function model Data type
0 - Standard USINT
254 - Bus controller UINT

4.6.4.8.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.6.4.8.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
2 ms

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 X20 system modules • Bus modules • Brief information

4.7 Bus modules

In the X20 system, a bus module takes the place of a rack.

Bus supply contacts

Bus data contacts

I/O supply contacts

X20BM11 X20BM01

Figure 228: The bus module replaces the rack in the X20 system
The bus module is the backbone of the X20 system regarding the bus supply and bus data as well as the I/O supply
for the electronics modules. Each bus module is an active bus station, even without an electronics module. There
are two variations of the bus module:
• Interconnected I/O supply
• I/O supply isolated to the left (for power supply modules)

4.7.1 Brief information

Product ID Short description on page
X20BM01 X20 supply bus module, internal I/O supply interrupted to the left 584
X20BM05 X20 supply bus module with node number switch, internal I/O supply is isolated to the left 586
X20BM11 X20 bus module, 24 V coded, internal I/O supply is interconnected 588
X20BM12 X20 bus module, 240 V coded, internal I/O supply is interconnected 590
X20BM15 X20 bus module with node number switches, internal I/O supply is interconnected 592
X20BM21 X20 bus module for double-width modules, internal I/O supply is isolated to the left 594
X20BM31 X20 bus module for double-width modules, internal I/O supply is interconnected 596
X20BM32 X20 bus module, 240 V coded, for double wide modules, internal I/O supply is interconnected 598

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X20 system modules • Bus modules • X20BM01

4.7.2 X20BM01

4.7.2.1 General information

The X20BM01 bus module is the base for all X20 supply modules.
• Basis for all X20 supply modules
• For creating voltage groups
• The internal I/O supply is isolated to the left

4.7.2.2 Order data

Model number Short description Figure

Bus modules
X20BM01 X20 supply bus module, internal I/O supply interrupted to the left

Table 183: X20BM01 - Order data

4.7.2.3 Technical data

Product ID X20BM01
Brief description
Bus module Power supply bus module, 24 VDC keyed, internal I/O supply interrupted to the left
General information
Power consumption
Bus 0.13 W
Internal I/O -
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
I/O supply
Nominal voltage 24 VDC
Permitted contact load 10.0 A
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C

Table 184: X20BM01 - Technical data

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Product ID X20BM01
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Spacing 12.5 +0.2 mm

Table 184: X20BM01 - Technical data

4.7.2.4 Voltage routing

+24 VDC
GND

Figure 229: Voltage routing

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X20 system modules • Bus modules • X20BM05

4.7.3 X20BM05

4.7.3.1 General information

The X20BMx5 safety bus modules have node number switches that can be used to set permanent addresses.
Placing one of these modules at the beginning of an X20 block ensures a unique address. The addresses of
subsequent modules are automatically set in ascending order starting at this address. This simple feature greatly
increases the flexibility of applications.
Another advantage: Addresses can be set independently of which specific I/O modules are used. All that is required
are the respective bus modules. This provides logistical advantages with respect to cost and the variety of parts.
• The X20BM05 is the base for all X20 supply modules
• For creating voltage groups
• The internal I/O supply is isolated to the left
• Manual node number assignment
• Independent of electronics module
• Manual and automatic addressing can be combined as desired

4.7.3.2 Order data

Model number Short description Figure

Bus modules
X20BM05 X20 supply bus module with node number switch, internal I/O
supply is isolated to the left

Table 185: X20BM05 - Order data

4.7.3.3 Technical data

Product ID X20BM05
Short description
Bus module Supply bus module, internal I/O supply is isolated to the left, manual node number assignment
General information
Power consumption
Bus 0.13 W
Internal I/O -
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
I/O supply
Nominal voltage 24 VDC
Permitted contact load 10.0 A
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0,5°C per 100 m
Protection in accordance with EN 60529 IP20

Table 186: X20BM05 - Technical data

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Product ID X20BM05
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Spacing 12.5 +0.2 mm

Table 186: X20BM05 - Technical data

4.7.3.4 Voltage routing

+24 VDC
GND

Figure 230: Voltage routing

4.7.3.5 Node number switches

x16

x1

Figure 231: Node number switches

The X2X Link address of the module is set using the node number switches (0x01 to 0xFD).
Setting node number 0x00 causes the X2X Link address to be assigned automatically.

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X20 system modules • Bus modules • X20BM11

4.7.4 X20BM11

4.7.4.1 General information

The bus module serves as the base for all 24 VDC X20 I/O modules. The internal I/O supply is interconnected.
• Bus module for 24 VDC I/O modules
• The internal I/O supply is interconnected

4.7.4.2 Order data

Model number Short description Figure

Bus modules
X20BM11 X20 bus module, 24 V coded, internal I/O supply is interconnect-
ed

Table 187: X20BM11 - Order data

4.7.4.3 Technical data

Product ID X20BM11
Short description
Bus module Bus module for 24 VDC I/O modules, the internal I/O supply is interconnected
General information
Power consumption
Bus 0.13 W
Internal I/O -
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
I/O supply
Nominal voltage 24 VDC
Permitted contact load 10.0 A
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0,5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C

Table 188: X20BM11 - Technical data

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Product ID X20BM11
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Spacing 12.5 +0.2 mm

Table 188: X20BM11 - Technical data

4.7.4.4 Voltage routing

+24 VDC +24 VDC

GND GND

Figure 232: Voltage routing

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X20 system modules • Bus modules • X20BM12

4.7.5 X20BM12

4.7.5.1 General information

The bus module serves as the base for all 240 VAC X20 I/O modules. The internal I/O supply is interconnected.
• Bus module for 240 VAC I/O modules
• The internal I/O supply is interconnected
• 240 V coding for bus module, electronic module and terminal block

4.7.5.2 Order data

Model number Short description Figure

Bus modules
X20BM12 X20 bus module, 240 V coded, internal I/O supply is intercon-
nected

Table 189: X20BM12 - Order data

4.7.5.3 Technical data

Product ID X20BM12
Short description
Bus module Bus module for 240 VAC I/O modules, the internal I/O supply is interconnected
General information
Power consumption
Bus 0.13 W
Internal I/O -
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
I/O supply
Nominal voltage 24 VDC
Permitted contact load 10.0 A
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C

Table 190: X20BM12 - Technical data

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Product ID X20BM12
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Spacing 12.5 +0.2 mm

Table 190: X20BM12 - Technical data

4.7.5.4 Voltage routing

+24 VDC +24 VDC

GND GND

Figure 233: Voltage routing

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X20 system modules • Bus modules • X20BM15

4.7.6 X20BM15

4.7.6.1 General information

The X20BMx5 safety bus modules have node number switches that can be used to set permanent addresses.
Placing one of these modules at the beginning of an X20 block ensures a unique address. The addresses of
subsequent modules are automatically set in ascending order starting at this address. This simple feature greatly
increases the flexibility of applications.
Another advantage: Addresses can be set independently of which specific I/O modules are used. All that is required
are the respective bus modules. This provides logistical advantages with respect to cost and the variety of parts.
• The X20BM15 is the base for all X20 24 VDC I/O modules
• The internal I/O supply is interconnected
• Manual node number assignment
• Independent of electronics module
• Manual and automatic addressing can be combined as desired

4.7.6.2 Order data

Model number Short description Figure

Bus modules
X20BM15 X20 bus module with node number switches, internal I/O supply
is interconnected

Table 191: X20BM15 - Order data

4.7.6.3 Technical data

Product ID X20BM15
Short description
Bus module Bus module for 24 VDC I/O modules, the internal I/O sup-
ply is interconnected, manual node number assignment
General information
Power consumption
Bus 0.13 W
Internal I/O -
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
I/O supply
Nominal voltage 24 VDC
Permitted contact load 10.0 A
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0,5°C per 100 m
Protection in accordance with EN 60529 IP20

Table 192: X20BM15 - Technical data

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Product ID X20BM15
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Spacing 12.5 +0.2 mm

Table 192: X20BM15 - Technical data

4.7.6.4 Voltage routing

+24 VDC +24 VDC

GND GND

Figure 234: Voltage routing

4.7.6.5 Node number switches

x16

x1

Figure 235: Node number switches

The X2X Link address of the module is set using the node number switches (0x01 to 0xFD).
Setting node number 0x00 causes the X2X Link address to be assigned automatically.

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X20 system modules • Bus modules • X20BM21

4.7.7 X20BM21

4.7.7.1 General information

The X20BM21 bus module serves as a basis for all double-width X20 I/O modules. The internal I/O supply is
isolated to the left. This allows the X20BM21 bus module to be used to set up a separate voltage group if the
X20BT9100 bus transmitter is used for the supply.
• For creating voltage groups
• The internal I/O supply is isolated to the left

4.7.7.2 Order data

Model number Short description Figure

Bus modules
X20BM21 X20 bus module for double-width modules, internal I/O supply
is isolated to the left

Table 193: X20BM21 - Order data

4.7.7.3 Technical data

Product ID X20BM21
Short description
Bus module Double-width bus module, internal I/O supply is isolated to the left
General information
Power consumption
Bus 0.13 W
Internal I/O -
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
I/O supply
Nominal voltage 24 VDC
Permitted contact load 10.0 A
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0,5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C

Table 194: X20BM21 - Technical data

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 X20 system modules • Bus modules • X20BM21
Product ID X20BM21
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Spacing 25 +0.2 mm

Table 194: X20BM21 - Technical data

4.7.7.4 Voltage routing

+24 VDC
GND

Figure 236: Voltage routing

X20 system User's Manual 3.10 595

X20 system modules • Bus modules • X20BM31

4.7.8 X20BM31

4.7.8.1 General information

The X20BM31 bus module serves as a basis for all double-width X20 I/O modules. The internal I/O supply is
interconnected.
• Bus module for double-width I/O modules
• The internal I/O supply is interconnected

4.7.8.2 Order data

Model number Short description Figure

Bus modules
X20BM31 X20 bus module for double-width modules, internal I/O supply
is interconnected

Table 195: X20BM31 - Order data

4.7.8.3 Technical data

Product ID X20BM31
Short description
Bus module Double-width bus module, the internal I/O supply is interconnected
General information
Power consumption
Bus 0.13 W
Internal I/O -
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
I/O supply
Nominal voltage 24 VDC
Permitted contact load 10.0 A
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0,5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C

Table 196: X20BM31 - Technical data

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 X20 system modules • Bus modules • X20BM31
Product ID X20BM31
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Spacing 25 +0.2 mm

Table 196: X20BM31 - Technical data

4.7.8.4 Voltage routing

+24 VDC +24 VDC

GND GND

Figure 237: Voltage routing

X20 system User's Manual 3.10 597

X20 system modules • Bus modules • X20BM32

4.7.9 X20BM32

4.7.9.1 General information

The bus module serves as the base for all double-width 240 VAC X20 I/O modules. The internal I/O supply is
interconnected.
• Bus module for double-width 240 VAC I/O modules
• The internal I/O supply is interconnected
• 240 V coding for bus module, electronic module and terminal block

4.7.9.2 Order data

Model number Short description Figure

Bus modules
X20BM32 X20 bus module, 240 V coded, for double wide modules, internal
I/O supply is interconnected

Table 197: X20BM32 - Order data

4.7.9.3 Technical data

Product ID X20BM32
Short description
Bus module Double-width bus module for 240 VAC I/O modules, the internal I/O supply is interconnected
General information
Power consumption
Bus 0.13 W
Internal I/O -
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
I/O supply
Nominal voltage 24 VDC
Permitted contact load 10.0 A
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0,5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C

Table 198: X20BM32 - Technical data

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Product ID X20BM32
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Spacing 25 +0.2 mm

Table 198: X20BM32 - Technical data

4.7.9.4 Voltage routing

+24 VDC +24 VDC

GND GND

Figure 238: Voltage routing

X20 system User's Manual 3.10 599

X20 system modules • Bus receivers and Bus transmitters • Brief information

4.8 Bus receivers and Bus transmitters

The bus receiver X20BR9300is used to connect the X20 system directly to the remote X2X Link backplane. The
bus transmitter X20BT9100 is used to connect to the next station.

4.8.1 Brief information

Product ID Short description on page
X20BR9300 X20 bus receiver, X2X Link, supply for X2X Link and internal I/O supply, X20 locking plates (left and right) 601
X20AC0SL1/X20AC0SR1 included
X20BT9100 X20 bus transmitter, X2X Link, supply for internal I/O supply 607
X20BT9400 X20 bus transmitter X2X Link, feed for internal I/O supply, X2X Link supply for X67 modules, reverse polari- 613
ty protection, short circuit protection, overload protection, parallel connection possible, redundancy operation
possible

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 X20 system modules • Bus receivers and Bus transmitters • X20BR9300

4.8.2 X20BR9300

4.8.2.1 General information

The bus receiver X20BR9300 is used to connect the X20 System to the X2X Link. The module is equipped with
a feed for the X2X Link as well as the internal I/O supply.
The left and right end plates are included in the delivery.
• X2X Link bus receiver
• Feed for X2X Link and internal I/O supply
• Electrical isolation of feed and X2X Link supply
• Redundancy of X2X Link supply possible by operating multiple supply modules simultaneously
• Operation only on the slot to the far left

4.8.2.2 Order data

Model number Short description Figure

Bus receivers and transmitters
X20BR9300 X20 bus receiver, X2X Link, supply for X2X Link and inter-
nal I/O supply, X20 locking plates (left and right) X20AC0SL1/
X20AC0SR1 included
Required accessories
Bus modules
X20BM01 X20 power supply bus module, 24 VDC keyed, internal I/O sup-
ply interrupted to the left
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed
Optional accessories
X2X Link cable
X67CA0X99.1000 Cable for custom assembly, 100 m
X67CA0X99.5000 Cable for custom assembly, 500 m

Table 199: X20BR9300 - Order data

Information:
This module is NOT PERMITTED to be used together with continuous power supply modules (e.g.
X20BM11 or X20BM15) since this can result in problems with X2X Link!

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X20 system modules • Bus receivers and Bus transmitters • X20BR9300

4.8.2.3 Technical data

Product ID X20BR9300
Short description
Bus receiver X2X Link bus receiver with supply for I/O and bus
General information
B&R ID code 0x1BC1
Status indicators X2X bus function, overload, operating status, module status
Diagnostics
Module run/error Yes, with status LED and software status
Overload Yes, with status LED and software status
X2X bus function Yes, with status LED
Power consumption 1)
Bus 1.62 W
Internal I/O 0.6 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
I/O feed - I/O supply No
X2X Link feed - X2X Link supply Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
X2X Link supply input
Input voltage 24 VDC -15% / +20%
Input current Max. 0.7 A
Fuse Integrated, cannot be replaced
Reverse polarity protection Yes
X2X Link supply output
Nominal output power 7.0 W
Parallel operation Yes 2)
Redundant operation Yes
Overload behavior Short circuit / temporary overload protection
Input I/O supply
Input voltage 24 VDC -15% / +20%
Fuse Required line fuse: Max. 10 A, slow-blow
Reverse polarity protection No
Output I/O supply
Rated output voltage 24 VDC
Behavior if a short circuit occurs Required line fuse
Permitted contact load 10.0 A
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating For >55°C nominal output power for X2X Link supply is limited to max. 5 W
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM01 supply bus module separately
Left and right X20 locking plates included in delivery
Spacing 12.5 +0.2 mm

Table 200: X20BR9300 - Technical data

1) The specified values are maximum values. The exact calculation is also available for download as a data sheet with the other module documentation on
the B&R homepage.
2) In parallel operation, only 75% of the rated power can be assumed. It is important to make sure that all power supplies operating in parallel are switched
on and off at the same time.

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 X20 system modules • Bus receivers and Bus transmitters • X20BR9300

4.8.2.4 LED status indicators

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Double flash LED indicates one of the following states:
• X2X Link power supply is overloaded
• I/O supply too low
• Input voltage for X2X Link supply too low
e+r Red on / Green single flash Invalid firmware
X Orange Off No communication at the X2X Link
On X2X Link communication in progress
l Red Off X2X Link supply in the acceptable range
On X2X Link power supply is overloaded
Solution: Use an additional feed module X20PS3300

4.8.2.5 Pinout

r e
X20 BR 9300

X I

X2X X2X\

X2X⊥

+24 V X2X Link +24 V I/O

+24 V X2X Link +24 V I/O

GND GND

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X20 system modules • Bus receivers and Bus transmitters • X20BR9300

4.8.2.6 Connection examples

With two separate supplies

BR

X2X
X2X\
X2X⊥

10 A slow-blow
X2X Link + + I/O
Power supply _ _ Power supply

+24 VDC
GND

With a supply and jumper

BR

X2X
X2X\
X2X⊥

Jumper

10 A slow-blow
+ I/O
_ Power supply

+24 VDC
GND

4.8.2.7 Derating

The rated output current for the supply is 7.0 W. Derating must be taken into consideration based on mounting
orientation.
Installation position

Horizontal

Vertical

7
Nominal output power

4
[W]

0
-25 40 45 50 55 60

Ambient temperature [°C]

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 X20 system modules • Bus receivers and Bus transmitters • X20BR9300

4.8.2.8 Register description

4.8.2.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
0 Module status USINT ●
StatusInput01 Bit 0
StatusInput02 Bit 2
2 SupplyCurrent USINT ●
4 SupplyVoltage USINT ●

4.8.2.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
0 0 Module status UINT ●
StatusInput01 Bit 0
StatusInput02 Bit 2
2 2 SupplyCurrent UINT ●
4 4 SupplyVoltage UINT ●

1) The offset specifies the position of the register within the CAN object.

4.8.2.8.3 Module status

Name:
Module status
The following voltage and current states of the module are monitored in this register:
Bus supply current: A bus supply current of >2.3A is displayed as a warning.
Bus supply voltage: A bus supply voltage of <4.7V is displayed as a warning.
24 VDC I/O supply voltage: An I/O supply voltage of <20.4 V is displayed as a warning.
Function model Data type Value
0 - Standard USINT See bit structure.
254 - Bus controller UINT See bit structure.

Bit structure:
Bit Name Value Information
0 StatusInput01 0 No error
1 Warning - overcurrent (>2.3 A) or undervoltage (<4.7 V)
1 Reserved 0
2 StatusInput02 0 I/O supply above the warning level of 20.4 V
1 I/O supply below the warning level of 20.4 V
3-x Reserved 0

4.8.2.8.4 Bus supply current

Name:
SupplyCurrent
This register displays the bus supply current measured at a resolution of 0.1 A.
Function model Data type
0 - Standard USINT
254 - Bus controller UINT

4.8.2.8.5 Bus supply voltage

Name:
SupplyVoltage
This register displays the bus supply voltage measured at a resolution of 0.1 V.
Function model Data type
0 - Standard USINT
254 - Bus controller UINT

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X20 system modules • Bus receivers and Bus transmitters • X20BR9300

4.8.2.8.6 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.8.2.8.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
2 ms

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 X20 system modules • Bus receivers and Bus transmitters • X20BT9100

4.8.3 X20BT9100

4.8.3.1 General information

The bus transmitter provides for the seamless expansion of the X20 System. The stations can be up to 100 m
away from each other.
• X2X Link bus transmitter
• For seamless expansion of the system
• Up to 100 m segment lengths
• Feed for internal I/O supply
• Operation only on the slot to the far right

Information:
The bus transmitter modules may only be operated with a bus module where the internal I/O supply
is connected through (e.g. X20BM11).
If the incoming voltage is used for internal I/O supply, then this potential group must not be supplied by
any other module. An I/O module with bus module X20BM01 should be used to separate the potential
group.

4.8.3.2 Order data

Model number Short description Figure

Bus receivers and transmitters
X20BT9100 X20 bus transmitter, X2X Link, supply for internal I/O supply
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed
Optional accessories
X2X Link cable
X67CA0X99.1000 Cable for custom assembly, 100 m
X67CA0X99.5000 Cable for custom assembly, 500 m

Table 201: X20BT9100 - Order data

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X20 system modules • Bus receivers and Bus transmitters • X20BT9100

4.8.3.3 Technical data

Product ID X20BT9100
Short description
Bus transmitter X2X Link bus transmitter with supply for I/O
General information
B&R ID code 0x1BC2
Status indicators X2X bus function, operating status, module status
Diagnostics
Module run/error Yes, using status LED and software
X2X bus function Yes, using status LED
Power consumption 1)
Bus 0.5 W
Internal I/O
As bus transmitter 0.1 W
Additionally as supply module 0.6 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Input I/O supply
Input voltage 24 VDC -15% / +20%
Fuse Required line fuse: Max. 10 A, slow-blow
Reverse polarity protection No
Output I/O supply
Rated output voltage 24 VDC
Behavior if a short circuit occurs Required line fuse
Permitted contact load 10.0 A
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 or X20BM15 bus module separately
Spacing 12.5 +0.2 mm

Table 202: X20BT9100 - Technical data

1) The specified values are maximum values. The exact calculation is also available for download as a data sheet with the other module documentation on
the B&R website.

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 X20 system modules • Bus receivers and Bus transmitters • X20BT9100

4.8.3.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Double flash LED indicates one of the following states:
• I/O supply too low
• X2X bus supply too low
e+r Red on / Green single flash Invalid firmware
X Orange Off No communication at the X2X Link
On X2X Link communication in progress

Table 203: LED status indicators

4.8.3.5 Pinout

r e

X20 BT 9100
X

X2X X2X\

X2X⊥

+24 V I/O

GND

4.8.3.6 Connection examples

No feed for internal I/O supply

BT

X2X\
X2X
X2X⊥

+24 VDC
GND

Figure 239: Connection example - No feed for internal I/O supply

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X20 system modules • Bus receivers and Bus transmitters • X20BT9100

With feed for internal I/O supply

See also 4.8.3.7 "Supply via bus transmitter".

BT

X2X\
X2X
X2X⊥

10 A slow-blow
+ I/O
_ Power supply

+24 VDC
GND

Figure 240: Connection example - With feed for internal I/O supply

4.8.3.7 Supply via bus transmitter

The bus transmitter has an integrated internal I/O supply feed. This saves a power supply module for the last
potential group.
Keep in mind: this potential group is separated from the rest of the potential groups by an I/O module with the
X20BM01 bus module.
I/O module + BM01
BR9300 + BM01

PS2100 + BM01

BT9x00 + BM11

X2X
I/O I/O I/O
Link

1 A slow-blow 1) 10 A slow-blow 10 A slow-blow 10 A slow-blow

U1/24 VDC

U2/24 VDC

Figure 241: Protection when supplied via bus transmitter

1) Recommended for line protection.

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 X20 system modules • Bus receivers and Bus transmitters • X20BT9100

4.8.3.8 Connection to next X2X Link I/O node

The bus transmitter establishes the connection to the next X2X Link based I/O node. It is important to be sure that
only the data lines are connected on. X2X Link supply is system dependant.
System X2X Link supply
X67 system System supply X67PS1300
Remote I/O with X2X Link (XX modules) 24 VDC external supply
Remote valve terminal connection (XV modules) 24 VDC external supply

Table 204: X20BT9100 - System-dependent X2X Link supply

X2X Link supply:

Via external 24 VDC feed

X20 system X20 system

XV
X20 system
Compact I/O

X20 system X67 X67 X67 X20 system

X2X Link supply:

Via system supply X67PS1300

Figure 242: X2X Link supply depending on the system

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X20 system modules • Bus receivers and Bus transmitters • X20BT9100

4.8.3.9 Register description

4.8.3.9.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
0 Module status USINT ●
StatusInput01 Bit 0
StatusInput02 Bit 2
4 SupplyVoltage USINT ●

4.8.3.9.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
0 0 Module status UINT ●
StatusInput01 Bit 0
StatusInput02 Bit 2
4 4 SupplyVoltage UINT ●

1) The offset specifies the position of the register within the CAN object.

4.8.3.9.3 Module status

Name:
Module status
The following module supply voltages are monitored in this register:
Bus supply voltage: A bus supply voltage of <4.7V is displayed as a warning.
24 VDC I/O supply voltage: An I/O supply voltage of <20.4 V is displayed as a warning.
Function model Data type Value
0 - Standard USINT See bit structure.
254 - Bus controller UINT See bit structure.

Bit structure:
Bit Name Value Information
0 StatusInput01 0 No error
1 Bus supply warning - Undervoltage (<4.7V)
1 Reserved 0
2 StatusInput02 0 I/O supply above the warning level of 20.4 V
1 I/O supply below the warning level of 20.4 V
3-x Reserved 0

4.8.3.9.4 Bus supply voltage

Name:
SupplyVoltage
This register displays the bus supply voltage measured at a resolution of 0.1 V.
Function model Data type
0 - Standard USINT
254 - Bus controller UINT

4.8.3.9.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.8.3.9.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
2 ms

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 X20 system modules • Bus receivers and Bus transmitters • X20BT9400

4.8.4 X20BT9400

4.8.4.1 General information

To connect an X20 system to an X67 system, a bus transmitter is simple added to the end of the X20 block, so
that the X2X Link cable can be connected. The bus transmitter also provides the X2X supply voltage for the X67
system. There is no longer a need for an X67 system supply module.
• X2X Link bus transmitter
• For seamless expansion of the system
• Up to 100 m segment lengths
• Feed for internal I/O supply
• Integrated X2X Link supply for the X67 system
• Operation only on the slot to the far right

Information:
The bus transmitter modules may only be operated with a bus module where the internal I/O supply
is connected through (e.g. X20BM11).
If the incoming voltage is used for internal I/O supply, then this potential group must not be supplied by
any other module. An I/O module with bus module X20BM01 should be used to separate the potential
group.

4.8.4.2 Order data

Model number Short description Figure

Bus receivers and transmitters
X20BT9400 X20 bus transmitter X2X Link, feed for internal I/O supply, X2X
Link supply for X67 modules, reverse polarity protection, short
circuit protection, overload protection, parallel connection pos-
sible, redundancy operation possible
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
X20BM15 X20 bus module, with node number switch, 24 VDC keyed, in-
ternal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed
Optional accessories
X2X Link cable
X67CA0X99.1000 Cable for custom assembly, 100 m
X67CA0X99.5000 Cable for custom assembly, 500 m

Table 205: X20BT9400 - Order data

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X20 system modules • Bus receivers and Bus transmitters • X20BT9400

4.8.4.3 Technical data

Product ID X20BT9400
Short description
Bus transmitter X2X Link bus transmitter with supply for I/O and integrated supply for the X67 system
General information
B&R ID code 0xA238
Status indicators X2X bus function, operating status, module status
Diagnostics
Module run/error Yes, using status LED and software
X2X bus function Yes, using status LED
Power consumption 1)
Bus 0.5 W
Internal X67 X2X Link 1.38 W
Internal I/O
As bus transmitter 0.1 W
Additionally as supply module 0.6 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
X67 X2X Link supply input
Input voltage 24 VDC -15% / +20%
Input current Max. 0.5 A
Fuse Integrated, cannot be replaced
Reverse polarity protection Yes
X67 X2X Link supply output
Parallel connection with X67PS1300 Yes 2)
Overload behavior Temporarily protected against short circuit, overload
Be aware of corresponding status message (LED "I") or evaluate software status
X67 modules supplied by BT9400
Horizontal installation Max. 8 (Nominal output power: 6 W)
Vertical installation Max. 6 (Nominal output power: 4.5 W)
Input I/O supply
Input voltage 24 VDC -15% / +20%
Fuse Required line fuse: Max. 10 A, slow-blow
Reverse polarity protection No
Output I/O supply
Rated output voltage 24 VDC
Behavior if a short circuit occurs Required line fuse
Permitted contact load 10 A
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 or 1x X20BM15 bus module separately
Spacing 12.5 +0.2 mm

Table 206: X20BT9400 - Technical data

1) The specified values are maximum values. The exact calculation is also available for download as a data sheet with the other module documentation on
the B&R website.
2) Only the PS1300 can be used for calculating the total number of X67 modules.

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4.8.4.4 LED status indicators

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Double flash LED indicates one of the following states:
• I/O supply too low
• X2X Link voltage too low
e+r Red on / Green single flash Invalid firmware
X Orange Off No X2X Link communication
On X2X Link communication active
l Red Off The X67 / X2X Link supply is within the valid limits
On The X67 / X2X Link supply for the power supply is overloaded
Remedy: Use additional X67PS1300 supply modules

4.8.4.5 Pinout

r e
X20 BT 9400
X I

X2X X2X\

X2X+ X2X⊥

+24 V X2X X67 +24 V I/O

+24 V X2X X67 +24 V I/O

GND GND

4.8.4.6 Connection examples

With 2 separate supplies

BT

X2X\
X2X
X2X⊥
X2X+

10 A slow-blow
X67 X2X Link + + I/O
Power supply _ _ Power supply

+24 VDC
GND

Figure 243: Connection example with 2 separate supplies

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With a supply and jumper

BT

X2X\
X2X
X2X⊥
X2X+

Jumper

10 A slow-blow
+ I/O
_ Power supply

+24 VDC
GND

Figure 244: Connection example with a supply and jumper

No feed for internal I/O supply

BT

X2X\
X2X
X2X⊥
X2X+

Jumper

+24 VDC
GND

Figure 245: Connection example - No feed for internal I/O supply

4.8.4.7 Supply via bus transmitter

The bus transmitter has an integrated internal I/O supply feed. This saves a power supply module for the last
potential group.
Keep in mind: this potential group is separated from the rest of the potential groups by an I/O module with the
X20BM01 bus module.

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I/O module + BM01

BR9300 + BM01

PS2100 + BM01

BT9x00 + BM11
X2X
I/O I/O I/O
Link

1 A slow-blow 1) 10 A slow-blow 10 A slow-blow 10 A slow-blow

U1/24 VDC

U2/24 VDC

Figure 246: Protection when supplied via bus transmitter

1) Recommended for line protection.

4.8.4.8 Connection between X20 and X67 system

The bus transmitter establishes the link between the X20 system and the X67 system. In addition to the data lines,
the X2X Link supply is also fed through. The module can supply up to 8 X67 modules. An additional X67 supply
module is only needed if operating more than 8 X67 modules.

Information:
Only the X67PS1300 system supply module can be used for calculating the total number of X67 mod-
ules.

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4.8.4.9 Register description

4.8.4.9.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
0 Module status USINT ●
StatusInput01 Bit 0
StatusInput02 Bit 2
2 SupplyCurrent USINT ●
4 SupplyVoltage USINT ●

4.8.4.9.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
0 0 Module status UINT ●
StatusInput01 Bit 0
StatusInput02 Bit 2
2 2 SupplyCurrent UINT ●
4 4 SupplyVoltage UINT ●

1) The offset specifies the position of the register within the CAN object.

4.8.4.9.3 Module status

Name:
Module status
The following module supply voltages are monitored in this register:
X67 bus supply current: An X67 bus supply current of >0.4 A is displayed as a warning.
X67 bus supply voltage: A bus supply voltage of <18 V is displayed as a warning.
24 VDC I/O supply voltage: An I/O supply voltage of <20.4 V is displayed as a warning.
Function model Data type Value
0 - Standard USINT See bit structure.
254 - Bus controller UINT See bit structure.

Bit structure:
Bit Name Value Information
0 No error
0 StatusInput01 X67 bus supply warning for undervoltage (18 V) or when over-
1
current (0.4 A)
1 Reserved 0
0 I/O supply above the warning level of 20.4 V
2 StatusInput02
1 I/O supply below the warning level of 20.4 V
3-x Reserved 0

4.8.4.9.4 X67 bus supply current

Name:
SupplyCurrent
This register shows the X67 bus supply current with a resolution of 0.01 A.
Function model Data type
0 - Standard USINT
254 - Bus controller UINT

4.8.4.9.5 X67 bus supply voltage

Name:
SupplyVoltage
This register shows the X67 bus supply voltage with a resolution of 0.1 V.
Function model Data type
0 - Standard USINT
254 - Bus controller UINT

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4.8.4.9.6 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.8.4.9.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
2 ms

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X20 system modules • Compact CPUs

4.9 Compact CPUs

The modular structure of the Compact CPUs allows the user to assemble a CPU that meets their unique power
supply and interface requirements.
Compact CPU base
X20 BB 2x

Compact CPU Supply module

X20 PS 950x

Compact CPU
X20 CP 02xx

Terminal block
X20 TB 12

Figure 247: The four parts of the Compact CPU - Compact CPU, bus module, supply module, terminal block
Adaptable to individual requirements
• Embedded µP 25 with Ethernet on-board
• Embedded μP 16 with or without Ethernet on-board

• Bus module with RS232 connection

• Bus module with RS232 and CAN bus connections

• Supply module for Compact CPU, X2X Link bus supply and I/O
• RS232 interface connection
• CAN bus connection
• Without or without electrical isolation of the CPU/X2X Link supply
• 12-pin terminal block
The battery-free CPU
To meet the high demands of the market, the Compact CPU was designed to run without a battery. This makes it
completely maintenance-free. The following features make operation without a buffer battery possible.
The real-time clock is buffered for approx. 1000 hours by a gold foil capacitor.
This FRAM stores its contents ferroelectrically. Unlike normal SRAM, this does not require a battery.
Compact design
Despite the sleek profile of only 37.5 mm, the CPU supply, the X2X Link bus supply, and the I/O module supply
are integrated in the CPU. No additional power modules are necessary.

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4.9.1 Brief information

Product ID Short description on page
X20CP0201 X20 CPU, compact CPU µP 16, 100 kB SRAM, 1 MB FlashPROM, support of RS232 and CAN according to 623
compact CPU base, order bus base, power supply module and terminal block separately
X20CP0291 X20 CPU, compact CPU µP 16, 100 kB SRAM, 1 MB FlashPROM, support of RS232 and CAN according to 623
compact CPU base, 1 Ethernet interface 100 Base-T, order bus base, power supply module and terminal block
separately
X20CP0292 X20 CPU, compact CPU µP 25, 100 kB SRAM, 1 MB FlashPROM, support of RS232 and CAN according to 623
compact CPU base, 3 Ethernet interface 750 Base-T, order bus base, power supply module and terminal block
separately

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X20 system modules • Compact CPUs • X20CP0201, X20CP0291, X20CP0292

4.9.2 X20CP0201, X20CP0291, X20CP0292

4.9.2.1 General information

Compact CPUs are ideal for situations where cycle times in the millisecond range are sufficient and a cost-benefit
analysis plays a decisive role. A range of models with CAN and Ethernet can adapt optimally to all demands. The
result: extremely sleek automation solutions.
• Embedded µP 16 / μP 25 with additional I/O processor
• 100/750 kB User SRAM
• 1 MB / 3 MB User FlashPROM
• X20CP0291 and X20CP0292: Onboard Ethernet
• Only 37.5 mm wide
• No battery

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4.9.2.2 Order data

CP0201 CP0291, CP0292

Model number Short description

Compact CPUs
X20CP0201 X20 CPU, compact CPU µP 16, 100 kB SRAM, 1 MB FlashPROM, support of RS232 and CAN
according to compact CPU base, order bus base, power supply module and terminal block sep-
arately
X20CP0291 X20 CPU, compact CPU µP 16, 100 kB SRAM, 1 MB FlashPROM, support of RS232 and CAN
according to compact CPU base, 1 Ethernet interface 100 Base-T, order bus base, power supply
module and terminal block separately
X20CP0292 X20 CPU, compact CPU µP 25, 100 kB SRAM, 1 MB FlashPROM, support of RS232 and CAN
according to compact CPU base, 3 Ethernet interface 750 Base-T, order bus base, power supply
module and terminal block separately
Required accessories
System modules for compact CPUs
X20BB22 X20 compact CPU base, for compact CPU and compact CPU power supply module, base for
integrated RS232 interface, X20 connection, X20 locking plates X20AC0SL1/X20AC0SR1 (left
and right) included
X20BB27 X20 compact CPU base, for compact CPU and compact CPU power supply module, base for
integrated RS232 and CAN bus interface, X20 connection, X20 locking plates X20AC0SL1/
X20AC0SR1 (left and right) included
X20PS9500 X20 supply module for compact and fieldbus CPUs and internal I/O supply, X2X Link supply
X20PS9502 X20 supply module, for compact and fieldbus CPUs and internal I/O supply, X2X Link supply,
supply not electrically isolated
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 207: X20CP0201, X20CP0291, X20CP0292 - Order data

Model number Included in delivery
X20AC0SL1 X20 locking plate, left
X20AC0SR1 X20 locking plate, right

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X20 system modules • Compact CPUs • X20CP0201, X20CP0291, X20CP0292

4.9.2.3 Technical data

Product ID X20CP0201 X20CP0291 X20CP0292

Short description
Interfaces - 1x Ethernet onboard 1x onboard Ethernet
System module CPU
General information
B&R ID code 0x22A2 0x22A4 0x22A6
Status indicators CPU function CPU function, Ethernet
Diagnostics
CPU function Yes, using status LED
Ethernet - Yes, using status LED
Overtemperature - Yes, using software
Power consumption 2.2 W 2.7 W 3.0 W
Temperature sensor No Yes
ACOPOS capability Limited (User PROM) Yes
Visual Components support Limited (User PROM) Yes
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
PLC - IF2 - Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Controller
Real-time clock 1) Yes, resolution 1 s
Processor
Type Embedded µP 16 Embedded µP 25
Integrated I/O processor Processes I/O data points in the background
Backup battery No
Shortest task class cycle time 4 ms 2 ms
Typical instruction cycle time 0.8 µs 0.5 µs
Permanent variables
Buffer duration >10 years
Memory 2.75 kB FRAM 2)
Standard memory
User PROM 1 MB FlashPROM 3 MB FlashPROM
User RAM 100 kB SRAM 3) 750 kB SRAM 3)
Interfaces
IF2 interface
Signal - Ethernet
Design - 1x shielded RJ45 port
Cable length - Max. 100 m between two stations (segment length)
Transfer rate - 100 Mbit/s
Transmission
Physical interfaces - 100 BASE-TX
Half-duplex - Yes
Full-duplex - No
Autonegotiation - No
Auto-MDI / MDIX - Yes
On base module
X20BB22 4) Compact CPU base module with integrated RS232 interface
X20BB27 5) Compact CPU base module with integrated RS232 and CAN interfaces
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C

Table 208: X20CP0201, X20CP0291, X20CP0292 - Technical data

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Product ID X20CP0201 X20CP0291 X20CP0292
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20PS9500 or X20PS9502 power supply module separately
Order 1x X20BB22 or X20BB27 compact CPU base separately
Spacing 6) 37.5+0.2 mm

Table 208: X20CP0201, X20CP0291, X20CP0292 - Technical data

1) The real-time clock is buffered for approx. 1000 hours by a gold foil capacitor. The gold foil capacitor is completely charged after 18 continuous hours of
operation.
2) This FRAM stores its contents ferroelectrically. A backup battery is therefore not necessary.
3) Not buffered.
4) For technical data, see the data sheet for the X20PS9500 power supply module.
5) For technical data, see the data sheet for the X20PS9502 power supply module.
6) Spacing is based on the width of the X20BB22 or X20BB27 compact CPU base. An X20PS9500 or X20PS9502 power supply module is also always required
for the CPU.

4.9.2.4 LED status indicators

Figure LED Color Status Description

R/E Green On Application running
Red On SERVICE mode
Off 1)

RDY Yellow On SERVICE mode

Off 1)

Table 209: X20CP0201 - Status LEDs

1) BOOT mode: R/E and RDY LEDs are off and the power supply LED is blinking

Figure LED Color Status Description

R/E Green On Application running
Red On SERVICE mode
Off 1)

RDY Yellow On SERVICE mode

Off 1)

L/A Green On A link to the peer station has been established.

Blinking A link to the peer station has been established. Indicates Ethernet activity is
taking place on the bus.

Table 210: X20CP029x - Status LEDs

1) BOOT mode: R/E and RDY LEDs are off and the power supply LED is blinking

4.9.2.5 Operating and connection elements

X20CP0201

LED status indicators

Node number switch

IF1 - RS232
IF3 - CAN bus (with BB27)

Terminal block for CPU

and I/O supply
RS232 connection
CAN bus connection (with BB27)

Switch for CAN bus terminating

resistor on BB27

Figure 248: X20 compact CPUs - Operating elements for X20CP0201

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X20 system modules • Compact CPUs • X20CP0201, X20CP0291, X20CP0292

X20CP0291 and X20CP0292

LED status indicators

Node number switch

IF1 - RS232
IF3 - CAN bus (with BB27)

IF2 - Ethernet
Terminal block for CPU
and I/O supply
RS232 connection
CAN bus connection (with BB27)

Switch for CAN bus terminating

resistor on BB27

Figure 249: X20 compact CPUs - Operating elements for X20CP0291 and X20CP0292

4.9.2.6 Node number switches

Figure 250: Node number switches

The node number is set using the two hex switches. The switch setting can be evaluated by the application program
at any time. The operating system only evaluates the switch position when the device is switched on.
Switch position Operating mode Description
0x00 BOOT In this switch position, the operating system can be installed via the RS232 interface configured
as the online interface. User Flash is deleted only after the update begins.
0x01 - 0xFE RUN RUN mode, the application is running.
0xFF Diagnostics Boots the CPU in Diagnostics mode. Program sections in User RAM and User FlashPROM are
not initialized. Following diagnostics mode, the CPU always boots with a cold restart.

Table 211: X20 CPUs - Operating modes

X20CP0201
When used with the X20BB27 bus module, the X20CP0201 has access to a CAN bus interface. The INA2000
station number for CAN is set using the node number switches.
X20CP0291 and X20CP0292
Both of these CPUs are equipped with an onboard Ethernet interface. When used with the X20BB27 bus module,
they also have access to a CAN bus interface.
The number set using the two hex switches defines the INA2000 station number of both the CAN and the Ethernet
interface.

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4.9.2.7 Ethernet interface (IF2)

Figure 251: X20 compact CPUs - Ethernet interface for X20CP0291 and X20CP0292
The X20CP0291 and X20CP0292 are equipped with an Ethernet interface. The connection is made using a 100
BASE-T twisted pair RJ45 socket.
Pinout
Interface Pinout
Pin Ethernet
1 RXD Receive data
2 RXD\ Receive data\
1
3 TXD Transmit data
4 Termination
5 Termination
6 TXD\ Transmit data\
Shielded RJ45 port 7 Termination
8 Termination

Table 212: RJ45 port - Pinout

Information about cabling X20 modules with an Ethernet interface can be found in the module's download section
on the B&R website (www.br-automation.com).

Information:
The Ethernet interface (IF2) is not suited for POWERLINK.
Starting with operating system version 1.07, CPUs have a default IP address.
IP address: 192.168.0.1
Subnet mask: 255.255.0.0

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X20 system modules • Compact CPUs • X20CP0201, X20CP0291, X20CP0292

4.9.2.8 Programming the system flash memory

General information
CPUs are delivered with a runtime system. When delivered, the node number switch is set to switch position 0x00
(bootstrap loader mode).
A suitable switch position must be set (0x01 to 0xFE) in order to boot the PLC in RUN mode. Updating the runtime
system is only possible in RUN mode.
Runtime system update
The runtime system can be updated via the programming environment. When updating the runtime system via an
online connection, the following procedure must be carried out:
1. An online runtime system update is only possible if the processor is in RUN mode. For this to be true, the
node number must be set to a value in the range 0x01 to 0xFE.
2. Switch on the power.
3. The runtime system update is performed via the existing online connection. The online connection can be
established via the onboard serial RS232 interface, for example. If a CPU has an Ethernet interface, then it
too can be used to perform the update.
4. Start B&R Automation Studio.
5. Start the update procedure by selecting Online from the Project menu. Select Transfer Automation Run-
time from the pop-up menu. Now follow the instructions given by B&R Automation Studio.
6. A window opens up for setting the runtime system version. The runtime system version is already pre-selected
by the project settings made by the user. The drop-down menu can be used to select one of the runtime
system versions stored in the project. Clicking on the Browse button allows a runtime system version to be
loaded from the hard drive or CD.

Clicking on Next opens a pop-up window that allows the user to select whether modules with target memory
SYSTEM ROM should be transferred during the subsequent runtime system update. If not, these modules
can also be transferred later during an application download.

Clicking on Next opens a dialog box where the user can set the CAN transfer rate, CAN ID and CAN node
number (the CAN node number set here is only relevant if an interface module does not have a CAN node
number switch). The CAN node number must be between decimal 01 and 99. Assigning a unique node
number is especially important with online communication over a CAN network (INA2000 protocol).
7. The update procedure is started by clicking on Next. Update progress is shown in a message box.

Information:
User flash memory is deleted.

8. When the update procedure is complete, the online connection is reestablished automatically.
9. The PLC is now ready for use.

Updating the runtime system is possible not only via an online connection, but also via a CAN network, serial
network (INA2000 protocol) or Ethernet network, depending on the system configuration.

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 X20 system modules • Compact CPUs System modules • Brief information

4.10 Compact CPUs System modules

The X20 system Compact CPUs consist of the Compact CPU, Compact CPU system modules and the X20TB12
terminal block.
The Compact CPU system modules also include the X20BB22 and X20BB27 base modules as well as the
X20PS9500 supply module for supplying the entire system with voltage.

4.10.1 Brief information

Product ID Short description on page
X20BB22 X20 Compact CPU base, for Compact CPU and Compact CPU power supply module, base for integrated RS232 630
interface, X20 connection, X20AC0SL1/X20AC0SR1 X20 end plates left and right included
X20BB27 X20 Compact CPU base, for Compact CPU and Compact CPU power supply module, base for integrated RS232 632
and CAN interface, X20 connection, X20AC0SL1/X20AC0SR1 X20 end plates left and right included
X20PS9500 X20 supply module for compact and fieldbus CPUs and internal I/O supply, X2X Link supply 634
X20PS9502 X20 power supply module for compact and fieldbus and internal I/O supply, X2X Link bus supply, supply not 639
electrically isolated

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X20 system modules • Compact CPUs System modules • X20BB22

4.10.2 X20BB22

4.10.2.1 General information

The X20BB22 bus module is the base for all X20 Compact CPUs.
The left and right end plates are included in the delivery.
• Base for all X20 Compact CPUs
• RS232 connection

4.10.2.2 Order data

Model number Short description Figure

System modules for compact CPUs
X20BB22 X20 Compact CPU base, for Compact CPU and Compact CPU
power supply module, base for integrated RS232 interface, X20
connection, X20AC0SL1/X20AC0SR1 X20 end plates left and
right included

Table 213: X20BB22 - Order data

4.10.2.3 Technical data

Product ID X20BB22
Short description
Bus module X20 Compact CPU base - backplane for Compact CPU and Compact CPU supply module
Interfaces 1x RS232 connection
General information
Power consumption
Bus 0.32 W
Internal I/O -
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Bus - RS232 No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
I/O supply
Nominal voltage 24 VDC
Permitted contact load 10.0 A
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No derating
>2000 m Reduction of ambient temperature by 0,5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Storage -40 to 85°C
Transport -40 to 85°C

Table 214: X20BB22 - Technical data

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Product ID X20BB22
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Left and right X20 end plates included in delivery
Spacing 37.5 +0.2 mm

Table 214: X20BB22 - Technical data

4.10.2.4 Voltage routing

+24 VDC
GND

Figure 252: Voltage routing

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X20 system modules • Compact CPUs System modules • X20BB27

4.10.3 X20BB27

4.10.3.1 General information

The X20BB27 bus module is the base for all X20 Compact CPUs.
The left and right end plates are included in the delivery.
• Base for all X20 Compact CPUs
• RS232 connection
• CAN bus connection
• Integrated terminating resistor for CAN bus

4.10.3.2 Order data

Model number Short description Figure

System modules for compact CPUs
X20BB27 X20 Compact CPU base, for Compact CPU and Compact CPU
power supply module, base for integrated RS232 and CAN inter-
face, X20 connection, X20AC0SL1/X20AC0SR1 X20 end plates
left and right included

Table 215: X20BB27 - Order data

4.10.3.3 Technical data

Product ID X20BB27
Short description
Bus module X20 Compact CPU base - backplane for Compact CPU and Compact CPU supply module
Interfaces 1x RS232 connection, 1x CAN bus connection
General information
Power consumption
Bus 0.53 W
Internal I/O -
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Bus - CAN bus No
Bus - RS232 No
RS232 - CAN bus No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
I/O supply
Nominal voltage 24 VDC
Permitted contact load 10.0 A
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No derating
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20

Table 216: X20BB27 - Technical data

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Product ID X20BB27
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Left and right X20 end plates included in delivery
Spacing 37.5 +0.2 mm

Table 216: X20BB27 - Technical data

4.10.3.4 Voltage routing

+24 VDC
GND

Figure 253: Voltage routing

4.10.3.5 Terminating resistor for CAN bus

On Off

Terminating resistor switch

The bus module has an integrated CAN bus terminating resistor. The terminating resistor is turned on and off with
a switch. An active terminating resistor is indicated on the supply module by the T LED.

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X20 system modules • Compact CPUs System modules • X20PS9500

4.10.4 X20PS9500

4.10.4.1 General information

The X20PS9500 supply module is used together with an X20 compact or fieldbus CPU. It has a feed for the compact
or fieldbus CPU, the X2X Link and the internal I/O supply.
• Supply for the compact or fieldbus CPU, X2X Link, and internal I/O supply
• Electrical isolation of feed and CPU / X2X Link supply
• Redundancy of CPU / X2X Link supply possible by operating multiple supply modules simultaneously
• RS232 interface configurable as online interface
• CAN bus

4.10.4.2 Order data

Model number Short description Figure

System modules for compact CPUs
X20PS9500 X20 supply module for compact and fieldbus CPUs and internal
I/O supply, X2X Link supply
Required accessories
System modules for compact CPUs
X20BB22 X20 compact CPU base, for compact CPU and compact CPU
power supply module, base for integrated RS232 interface, X20
connection, X20 locking plates X20AC0SL1/X20AC0SR1 (left
and right) included
X20BB27 X20 compact CPU base, for compact CPU and compact CPU
power supply module, base for integrated RS232 and CAN
bus interface, X20 connection, X20 locking plates X20AC0SL1/
X20AC0SR1 (left and right) included
System modules for fieldbus CPUs
X20BB32 X20 fieldbus CPU base, for fieldbus CPU and compact CPU
power supply module, base for integrated RS232 interface, Slot
for X20 interface module, X20 connection, X20 locking plates
X20AC0SL1/X20AC0SR1 (left and right) included
X20BB37 X20 fieldbus CPU base, for fieldbus CPU and compact CPU
power supply module, base for integrated RS232 and CAN bus
interface, Slot for X20 interface module, X20 connection, X20
locking plates X20AC0SL1/X20AC0SR1 (left and right) included
X20BB42 X20 fieldbus CPU base, for fieldbus CPU and compact CPU
power supply module, base for integrated RS232 interface, 2
slots for X20 interface modules, X20 connection, X20 locking
plates X20AC0SL1/X20AC0SR1 (left and right) included
X20BB47 X20 fieldbus CPU base, for fieldbus CPU and compact CPU
power supply module, base for integrated RS232 and CAN bus
interface, 2 slots for X20 interface modules, X20 connection,
X20 locking plates X20AC0SL1/X20AC0SR1 (left and right) in-
cluded
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 217: X20PS9500 - Order data

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 X20 system modules • Compact CPUs System modules • X20PS9500

4.10.4.3 Technical data

Product ID X20PS9500
Brief description
Power supply module 24 VDC supply module for compact or fieldbus CPU, X2X Link supply and I/O
Interfaces 1x RS232, 1x CAN bus 1)
General information
B&R ID code 0x2018
Status indicators Overload, operating state, module status, RS232, CAN bus 1)
Diagnostics
Module run/error Yes, using status LED and software
CAN bus data transfer 1) Yes, using status LED
RS232 data transfer Yes, using status LED
Overload Yes, using status LED and software
Power consumption 2)
Bus 1.42 W
Internal I/O 0.6 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
CPU/X2X Link feed - CPU/X2X Link supply Yes
I/O feed - I/O supply No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
CPU / X2X Link supply input
Input voltage 24 VDC -15% / +20%
Input current Max. 0.7 A
Fuse Integrated, cannot be replaced
Reverse polarity protection Yes
CPU / X2X Link supply output
Nominal output power 7.0 W
Parallel operation Yes 3)
Redundant operation Yes
Overload behavior Short circuit / temporary overload protection
Input I/O supply
Input voltage 24 VDC -15% / +20%
Fuse Required line fuse: Max. 10 A, slow-blow
Reverse polarity protection No
Output I/O supply
Rated output voltage 24 VDC
Behavior if a short circuit occurs Required line fuse
Permitted contact load 10.0 A
Interfaces
IF1 interface
Signal RS232
Design Connection made using 12-pin X20TB12 terminal block
Transfer rate Max. 115.2 kbit/s
IF3 interface 1)
Signal CAN bus
Design Connection made using 12-pin X20TB12 terminal block
Transfer rate Max. 1 Mbit/s
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C

Table 218: X20PS9500 - Technical data

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X20 system modules • Compact CPUs System modules • X20PS9500
Product ID X20PS9500
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BB22 or X20BB27 compact CPU base separately
Order 1x X20BB3x/4x fieldbus CPU base separately
Spacing 12.5 +0.2 mm

Table 218: X20PS9500 - Technical data

1) CAN bus only when used with the X20BB27, X20BB37 or X20BB47 bus module.
2) The specified values are maximum values. The calculation is also available for download as a data sheet with the other module documentation on the B&R
website.
3) In parallel operation, only 75% of the rated power can be assumed. It is important to make sure that all power supplies operating in parallel are switched
on and off at the same time.

4.10.4.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Double flash LED indicates one of the following states:
• The CPU / X2X Link supply for the power supply is overloaded
• I/O supply too low
• Input voltage for CPU / X2X Link supply too low
e+r Red on / Green single flash Invalid firmware
l Red Off The CPU / X2X Link supply is within the valid limits
On The CPU / X2X Link supply for the power supply is overloaded
S Yellow Off The CPU does not send data via the RS232 interface.
On The CPU sends data via the RS232 interface.
C Yellow Off The CPU is not sending data via the CAN bus interface.
On The CPU is sending data via the CAN bus interface.
T Yellow Off The terminating resistor integrated in the BB27 or BB37 bus module is turned off.
On The terminating resistor integrated in the BB27 or BB37 bus module is turned on.

Table 219: LED status indicators

4.10.4.5 Pinout

r e
X20 PS 9500

S I
C T

RS232 TxD RS232 RxD

CAN GND RS232 GND

CAN high CAN low

+24 V CPU/X2X L. +24 V I/O

+24 V CPU/X2X L. +24 V I/O

GND GND

Figure 254: Pinout

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 X20 system modules • Compact CPUs System modules • X20PS9500

4.10.4.6 Connection examples

With 2 separate supplies

PS

10 A slow-blow
CPU / X2X Link + + I/O
supply _ _ supply

+24 VDC
GND

Figure 255: Connection example with 2 separate supplies

With a supply and jumper

PS

Jumper

10 A slow-blow
+ I/O-
_ Power supply

+24 VDC
GND

Figure 256: Connection example with a supply and jumper

4.10.4.7 Derating

The rated output current for the supply is 7.0 W. Derating must be taken into consideration based on mounting
orientation.
Installation position

Horizontal

Vertical

7
Nominal output power

4
[W]

0
-25 40 45 50 55 60

Ambient temperature [°C]

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X20 system modules • Compact CPUs System modules • X20PS9500

4.10.4.8 Register description

4.10.4.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
0 Module status USINT ●
StatusInput01 Bit 0
StatusInput02 Bit 2
2 SupplyCurrent USINT ●
4 SupplyVoltage USINT ●

4.10.4.8.2 Module status

Name:
Module status
The following module supply voltages are monitored in this register:
Bus supply current: A bus supply current of >2.3A is displayed as a warning.
Bus supply voltage: A bus supply voltage of <4.7V is displayed as a warning.
24 VDC I/O supply voltage: An I/O supply voltage of <20.4 V is displayed as a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 StatusInput01 0 No error
1 Warning - overcurrent (>2.3 A) or undervoltage (<4.7 V)
1 Reserved 0
2 StatusInput02 0 I/O supply above the warning level of 20.4 V
1 I/O supply below the warning level of 20.4 V
3-x Reserved 0

4.10.4.8.3 Bus supply current

Name:
SupplyCurrent
This register displays the bus supply current measured at a resolution of 0.1 A.
Function model Data type
0 - Standard USINT

4.10.4.8.4 Bus supply voltage

Name:
SupplyVoltage
This register displays the bus supply voltage measured at a resolution of 0.1 V.
Function model Data type
0 - Standard USINT

4.10.4.8.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.10.4.8.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
2 ms

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 X20 system modules • Compact CPUs System modules • X20PS9502

4.10.5 X20PS9502

4.10.5.1 General information

The X20PS9502 supply module is used together with an X20 Compact or Fieldbus CPU. It is equipped with a feed
for the Compact or Fieldbus CPU, the X2X Link and the internal I/O supply.
The module is intended as a low-cost supply module for small X20 Systems. Voltage groups are able to be formed.
An expansion or redundancy of the X2X Link with the X20PS3300 or X20PS3310 supply module is not possible.
Expansion of the X20 System with a bus transmitter is not permitted either.
• Supply for the Compact or Fieldbus CPU, X2X Link, and internal I/O supply
• Low-cost supply module for small X20 Systems
• No electrical isolation of feed and CPU / X2X Link supply
• Expansion or redundancy of CPU / X2X Link supply not possible by operating multiple supply modules
simultaneously
• RS232 can be configured as an online interface
• CAN bus

4.10.5.2 Order data

Model number Short description Figure

System modules for compact CPUs
X20PS9502 X20 power supply module for compact and fieldbus and internal
I/O supply, X2X Link bus supply, supply not electrically isolated
Required accessories
System modules for compact CPUs
X20BB22 X20 compact CPU base, for compact CPU and compact CPU
power supply module, base for integrated RS232 interface, X20
connection, X20 locking plates X20AC0SL1/X20AC0SR1 (left
and right) included
X20BB27 X20 compact CPU base, for compact CPU and compact CPU
power supply module, base for integrated RS232 and CAN
bus interface, X20 connection, X20 locking plates X20AC0SL1/
X20AC0SR1 (left and right) included
System modules for fieldbus CPUs
X20BB32 X20 fieldbus CPU base, for fieldbus CPU and compact CPU
power supply module, base for integrated RS232 interface, Slot
for X20 interface module, X20 connection, X20 locking plates
X20AC0SL1/X20AC0SR1 (left and right) included
X20BB37 X20 fieldbus CPU base, for fieldbus CPU and compact CPU
power supply module, base for integrated RS232 and CAN bus
interface, Slot for X20 interface module, X20 connection, X20
locking plates X20AC0SL1/X20AC0SR1 (left and right) included
X20BB42 X20 fieldbus CPU base, for fieldbus CPU and compact CPU
power supply module, base for integrated RS232 interface, 2
slots for X20 interface modules, X20 connection, X20 locking
plates X20AC0SL1/X20AC0SR1 (left and right) included
X20BB47 X20 fieldbus CPU base, for fieldbus CPU and compact CPU
power supply module, base for integrated RS232 and CAN bus
interface, 2 slots for X20 interface modules, X20 connection,
X20 locking plates X20AC0SL1/X20AC0SR1 (left and right) in-
cluded
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 220: X20PS9502 - Order data

4.10.5.3 Technical data

Product ID X20PS9502
Short description
Power supply module 24 VDC supply module for compact or fieldbus CPU, X2X Link bus supply and I/O
Interfaces 1x RS232, 1x CAN bus 1)
General information
B&R ID code 0xA38A
Status indicators Operating state, module status, RS232, CAN bus 1)
Diagnostics
Module run/error Yes, with status LED and software status
CAN bus data transfer 1) Yes, with status LED
RS232 data transfer Yes, with status LED
Overload Yes, with status LED and software status

Table 221: X20PS9502 - Technical data

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X20 system modules • Compact CPUs System modules • X20PS9502
Product ID X20PS9502
Power consumption 2)
Bus 1.44 W
Internal I/O 0.6 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
CPU/X2X Link feed - CPU/X2X Link supply No
I/O feed - I/O supply No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
CPU / X2X Link supply input
Input voltage 24 VDC -15% / +20%
Input current Max. 0.7 A
Fuse Integrated, cannot be replaced
Reverse polarity protection Yes
CPU / X2X Link supply output
Nominal output power
Horizontal installation 7.0 W at 45°C and 5.0 W at 55°C
Vertical installation 7.0 W at 40°C and 5.0 W at 50°C
Parallel operation No
Redundant operation No
Overload behavior Short circuit / temporary overload protection
Input I/O supply
Input voltage 24 VDC -15% / +20%
Fuse Required line fuse: Max. 10 A, slow-blow
Reverse polarity protection No
Output I/O supply
Rated output voltage 24 VDC
Behavior if a short circuit occurs Required line fuse
Permitted contact load 10.0 A
Interfaces
IF1 interface
Signal RS232
Design Connection made using 12-pin X20TB12 terminal block
Transfer rate Max. 115.2 kbit/s
IF3 interface 1)
Signal CAN bus
Design Connection made using 12-pin X20TB12 terminal block
Transfer rate Max. 1 Mbit/s
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BB22 or X20BB27 compact CPU base separately
Order 1x X20BB32 or X20BB37 fieldbus CPU base separately
Spacing 12.5 +0.2 mm

Table 221: X20PS9502 - Technical data

1) CAN bus only when used with the X20BB27 or X20BB37 bus module.
2) The specified values are maximum values. The calculation is also available for download as a data sheet with the other module documentation on the B&R
homepage.

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 X20 system modules • Compact CPUs System modules • X20PS9502

4.10.5.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Double flash LED indicates one of the following states:
• The CPU / X2X Link power supply is overloaded
• I/O supply too low
• Input voltage for CPU / X2X Link too low
e+r Red on / Green single flash Invalid firmware
S Yellow Off The CPU does not send data via the RS232 interface.
On The CPU sends data via the RS232 interface.
C Yellow Off The CPU does not send data via the CAN bus interface.
On The CPU sends data via the CAN bus interface.
T Yellow Off The terminating resistor integrated in the X20BB27 or X20BB37 bus module is
turned off.
On The terminating resistor integrated in the X20BB27 or X20BB37 bus module is
turned on.

Table 222: LED status indicators

4.10.5.5 Pinout

r e
X20 PS 9502

S
C T

RS232 TxD RS232 RxD

CAN GND RS232 GND

CAN high CAN low

+24 V CPU/BUS +24 V I/O

+24 V CPU/BUS +24 V I/O

GND GND

Figure 257: Pinout

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X20 system modules • Compact CPUs System modules • X20PS9502

4.10.5.6 Connection examples

With 2 separate supplies

PS

10 A slow-blow
CPU / X2X Link + + I/O
supply _ _ supply

+24 VDC
GND

Figure 258: Connection example with 2 separate supplies

With a supply and jumper

PS

Jumper

10 A slow-blow
+ I/O-
_ Power supply

+24 VDC
GND

Figure 259: Connection example with a supply and jumper

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 X20 system modules • Compact CPUs System modules • X20PS9502

4.10.5.7 Derating for CPU / X2X Link supply

The rated output power for the CPU / X2X Link supply is 7.0W. Derating may be necessary depending on the
mounting orientation.
Installation position

Horizontal

Vertical

CPU / X2X Link supply

Rated output power
5

4
[W]

0
-25 40 45 50 55 60

Ambient temperature [°C]

Figure 260: Derating for CPU / X2X Link supply

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X20 system modules • Compact CPUs System modules • X20PS9502

4.10.5.8 Register description

4.10.5.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 Module status USINT ●
StatusInput01 Bit 0
StatusInput02 Bit 2
4 SupplyVoltage USINT ●

4.10.5.8.2 Module status

Name:
Module status
The following module supply voltages are monitored in this register:
Bus supply voltage: A bus supply voltage of <4.7V is displayed as a warning.
24 VDC I/O supply voltage: A supply voltage of <20.4V is displayed as a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 No error
0 StatusInput01
1 Bus supply warning - Undervoltage (<4.7V)
1 0 Reserved
0 I/O supply above the warning level of 20.4V
2 StatusInput02
1 I/O supply below the warning level of 20.4V
3-x 0 Reserved

4.10.5.8.3 Bus supply voltage

Name:
SupplyVoltage
This register displays the bus supply voltage measured at a resolution of 0.1 V.
Function model Data type
0 - Standard USINT
254 - Bus controller UINT

4.10.5.8.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.10.5.8.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
2 ms

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 X20 system modules • Counter modules • Brief information

4.11 Counter modules

Counter modules are used for position detection. Each signal on a counter module is assigned to a status LED.

4.11.1 Brief information

Product ID Short description on page
X20CM1941 X20 resolver module, 14-bit resolver input, converter up to 12-bit ABR output 646
X20DC1176 X20 digital counter module, 1 ABR incremental encoder, 5 V 600 kHz input frequency, 4x evaluation, encoder 653
monitoring, NetTime module
X20DC1178 X20 digital counter module, 1 SSI absolute encoders, 5 V, 1 MBit/s, 32-bit, encoder monitoring, NetTime module 669
X20DC1196 X20 digital counter module, 1 ABR incremental encoders, 5 V, 600 kHz input frequency, 4x evaluation 684
X20DC1198 X20 digital counter module, 1 SSI absolute encoder, 5 V, 1 MBit/s, 32-bit 694
X20DC11A6 X20 digital counter module, 1 ABR incremental encoders, 5 V, 5 MHz input frequency, 4x evaluation 701
X20DC1376 X20 digital counter module, 1 ABR incremental encoder, 24 V 100 kHz input frequency, 4x evaluation, encoder 717
monitoring, NetTime module
X20DC137A X20 digital counter module, 1x ABR incremental encoder, 24 V (differential), 300 kHz input frequency, 4x eval- 732
uation, encoder monitoring, NetTime module
X20DC1396 X20 digital counter module, 1 ABR incremental encoders, 24 V, 100 kHz input frequency, 4x evaluation 747
X20DC1398 X20 digital counter module, 1 SSI absolute encoder, 24 V, 125 kbit/s, 32-bit 757
X20DC1976 X20 digital counter module, 1x ABR incremental encoder, 5 V (single ended), 250 kHz input frequency, 4x 764
evaluation, encoder monitoring, NetTime module
X20DC2190 X20 digital counter module, ultrasonic transducer module, interfaces: EP start/stop, DPI/IP, 2 transducer rods, 780
4 path evaluation
X20DC2395 X20 digital counter module, 1 SSI absolute encoder, 24 V, 1 ABR incremental encoder, 24 V, 2 AB incremental 793
encoders, 24 V, 4 event counters or 2 PWM, local time measurement function
X20DC2396 X20 digital counter module, 2 ABR incremental encoders, 24 V, 100 kHz input frequency, 4x evaluation 833
X20DC2398 X20 digital counter module, 2 SSI absolute encoder, 24 V, 125 kbit/s, 32-bit 843
X20DC4395 X20 digital counter module, 2 SSI absolute encoder, 24 V, 2 ABR incremental encoder, 24 V, 4 AB incremental 850
encoders, 24 V, 8 event counters or 4 PWM, local time measurement function

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X20 system modules • Counter modules • X20CM1941

4.11.2 X20CM1941

4.11.2.1 General information

The module is equipped with a resolver input and a configurable ABR output.
• Resolver input (differential), with angular position and cyclic counter
• 14-bit resolution for the angular position
• ABR output (configurable)

4.11.2.2 Order data

Model number Short description Figure

Counter functions
X20CM1941 X20 resolver module, 14-bit resolver input, converter up to 12-
bit ABR output
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 223: X20CM1941 - Order data

4.11.2.3 Technical data

Product ID X20CM1941
Short description
I/O module 1 resolver input, 1 ABR output
General information
B&R ID code 0x1E85
Status indicators Input, output, operating status, module status
Diagnostics
Module run/error Yes, using status LED and software
Resolver input (OK, open line) Yes, using status LED and software
Resolver input (counter direction) Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.5 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Input/Output - Bus Yes
Input/Output - Module supply No
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Resolver inputs
Resolver transformation ratio 0.5 (±10%)
Reference output
Output voltage 34 Veff
Output current Max. 50 mAeff
Frequency 10 kHz
Type Differential
Angular position resolution 14-bit
Short circuit protection (reference output) Yes
Input impedance 10.4 kΩ - j 11.1 kΩ
Resolver type BRX
BRT with limitations

Table 224: X20CM1941 - Technical data

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 X20 system modules • Counter modules • X20CM1941
Product ID X20CM1941
ABR output
Encoder signal RS422
Type ABR differential
ABR output (starting with firmware version 5)
8-bit to 12-bit 3500 rpm
ABR output (up to firmware version 4) 1)
8-bit Max. 2343 rpm
9-bit Max. 1171 rpm
10-bit Max. 585 rpm
Short circuit protection Yes (reference output)
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation 0 to 55°C
Vertical installation 0 to 50°C
Derating -
Storage -25 to 70°C
Transport -25 to 70°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 224: X20CM1941 - Technical data

1) Configurable

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X20 system modules • Counter modules • X20CM1941

4.11.2.4 LED status indicators

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
e+r Red on / Green single flash Invalid firmware
1 Green On Resolver connected and OK
Off Open line or no resolver connected
U Orange UP: Counts up
D Orange DOWN: Counts down

1) Depending on the configuration, a firmware update can take up to several minutes.

4.11.2.5 Pinout

r e
X20 CM 1941
1
U
D

COS A

/COS /A

SIN B

/SIN /B

REF R

/REF /R

4.11.2.6 Connection example

CM
Resolver
COS

/COS

SIN

/SIN

REF

/REF

+24 VDC +24 VDC

GND GND

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 X20 system modules • Counter modules • X20CM1941

4.11.2.7 Input circuit diagram

COS
ADC
/COS
Band-pass
10 kHz
SIN
ADC
/SIN

4.11.2.8 Output circuit diagram

Ref
FPGA

/Ref
Band-pass
10 kHz

/A

/B

/R

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X20 system modules • Counter modules • X20CM1941

4.11.2.9 ABR encoder

Up to firmware version 4
The module measures the resolver's current angular position every 100 µs. The value for A, B or R is generated
immediately from the highest value bits (depending on configuration bit 8 to 10).
Firmware version 5 or higher
The procedure shown above reaches its limits as soon as more than one LSB difference occurs from one position
measurement to the next since only one edge of A or B is possible every 100 µs.
To achieve higher clock rates on the ABR encoder (and therefore higher rotational speeds) while simultaneously
improving temporal jitter, the ABR signal is no longer derived directly from the most recent measurement value,
but rather generated through interpolation between consecutive position measurements determined every 100 µs.

Information:
In comparison to firmware versions ≤4, the ABR outputs have a constant time offset of 250 μs. See
also "Comparison of the timing of the ABR outputs between Firmware version 4 and 5".

Comparison of the timing of the ABR outputs between Firmware version 4 and 5
Angular position

0x0180

0x0100

0x0080

0x0000

0xFF80

0xFF00

0xFE80
100 µs

Mode: New (firmware 5 or higher)

A
8-bit

B
R

A
9-bit

B
R

A
10-bit

B
R

Mode: Old (up to firmware 4)

A
8-bit

B
R

A
9-bit

B
R

A
10-bit

B
R

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 X20 system modules • Counter modules • X20CM1941

4.11.2.10 Register description

4.11.2.10.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Configuration
20 ConfigOutput01 UINT ●
22 ConfigOutput02 USINT ●
Communication
0 Position DINT ●
10 StatusInput USINT ●

4.11.2.10.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Configuration
20 - ConfigOutput01 UINT ●
22 - ConfigOutput02 USINT ●
Communication
0 0 Position DINT ●
10 4 StatusInput USINT ●

1) The offset specifies the position of the register within the CAN object.

4.11.2.10.3 Set the zero position

Name:
ConfigOutput01
This register can be used to set or move the zero position for the resolver. The zero position/offset specification
refers to the current resolver position.
Data type Value
UINT 0 to 65,535

4.11.2.10.4 Encoder emulation configuration

Name:
ConfigOutput02
This register can be used to configure the resolution of the ABR emulation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-2 Number of bits 0 8-bit = 256 increments/rotation
1 9-bit = 512 increments/rotation
2 10-bit = 1024 increments/rotation
3 11-bit = 2048 increments/rotation
4 12-bit = 4096 increments/rotation
5-7 Not permitted
3-7 Reserved -

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4.11.2.10.5 Current encoder position

Name:
Position
The current angle position of the resolver is shown in this register. The value consists of:
• The two upper bytes, which correspond to the number of rotations counted from -32768 (0x8000xxxx) to
+32767 (0x7FFFxxxx)
• The two lower bytes, which correspond to the angle position within the current rotation 1 LSB = 360° / 65536
The position value can, however, be interpreted exactly as an individual 32-bit long angle with resolution 1 / 65536
* 360°.
Data type Value Information
DINT 0x0000xxxx to 0xFFFFxxxx Number of rotations (cyclic)
0xxxxx0000 to 0xxxxxFFFF Angle position within the current rotation

Example
0x7FFF0080 corresponds to 32767 rotations, and 128 / 65536 * 360 = 0.703°.

4.11.2.10.6 Connection status

Name:
StatusInput
This register shows a potential open line between the module and the encoder.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Open line 0 No open line
1 Open line
1- 7 Reserved -

4.11.2.10.7 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.11.2.10.8 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
200 µs

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4.11.3 X20DC1176

4.11.3.1 General information

The module is equipped with 1 input for an ABR incremental encoder with 5 V encoder signal. The encoder inputs
are monitored (A, B, R, A\, B\, R\).
• 1 ABR incremental encoder 5 V
• Encoder input monitoring
• 2 additional inputs, e.g. for latch input
• 5 VDC, 24 VDC and GND for encoder supply

4.11.3.2 Order data

Model number Short description Figure

Counter functions
X20DC1176 X20 digital counter module, 1 ABR incremental encoder, 5 V 600
kHz input frequency, 4x evaluation, encoder monitoring, Net-
Time module
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 225: X20DC1176 - Order data

4.11.3.3 Technical data

Product ID X20DC1176
Brief description
I/O module 1 ABR incremental encoder 5 V
General information
B&R ID code 0xA706
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.0 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Type of signal lines Shielded cables must be used for all signal lines
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Quantity 2
Nominal voltage 24 VDC
Input voltage 24 VDC (-15% / +20%)
Input current at 24 VDC Approx. 3.3 mA
Input filter
Hardware ≤2 µs
Software -
Connection type 3-wire connections
Input circuit Sink
Additional functions Latch input
Input resistance 7.03 kΩ

Table 226: X20DC1176 - Technical data

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Product ID X20DC1176
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
ABR incremental encoder
Encoder inputs 5 V, symmetrical
Counter size 16/32-bit
Input frequency Max. 600 kHz
Evaluation 4x
Encoder supply
5 VDC ±5%, module-internal, max. 300 mA
24 VDC Module-internal, max. 300 mA
Input filter
Hardware ≤400 ns
Software -
Common-mode range -10 V ≤ VCM ≤ +13.2 V
Overload behavior of the encoder supply Short circuit protection, overload protection
Isolation voltage between encoder and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 226: X20DC1176 - Technical data

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4.11.3.4 LED status indicators

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Single flash The encoder monitor has detected a line fault on the encoder inputs. The status
bits must be evaluated in order to provide a more detailed definition of this error.
The following error states are detected:
• Open line
• Short-circuit or voltage level too low
On Error or reset status
A1 Green Input state of counter input A
B1 Green Input state of counter input B
R1 Green Input state of reference pulse R
1-2 Green Input state of the corresponding digital input

1) Depending on the configuration, a firmware update can take up to several minutes.

4.11.3.5 Pinout

Shielded cables must be used for all signal lines.

r e
X20 DC 1176

A1
B1
R1
1 2

A A\

B B\

R R\

DI 1 DI 2

Encoder 24 V+ Encoder 5 V+

GND GND

4.11.3.6 Connection example

DC

A
A\
Counter 1

B
B\
R
R\
Sensor 1

+24 VDC +24 VDC

GND GND

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4.11.3.7 Input circuit diagram

Counter inputs

ABR

Recipient Input status

with monitoring

ABR I/O status

LED (green)
24 V
PTC
Encoder 24 V

24 V
DC
Encoder 5 V
DC

GND

GND

Standard inputs

Input x

VDR
Input status

I/O status

Led (green)

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4.11.3.8 Register description

4.11.3.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Encoder - Communication
683 SDCLifeCount SINT ●
6342 Encoder01 INT ●
6340 DINT
6310 Encoder01TimeValid INT ●
6308 DINT
6358 Encoder01Latch INT ●
6356 DINT
6153 Encoder commands USINT ●
Encoder01Reset Bit 0
Encoder01LatchEnable Bit 1
927 Input status of signal lines USINT ●
Encoder01_A Bit 0
Encoder01_B Bit 1
Encoder01_R Bit 2
DigitalInput01 Bit 4
DigitalInput02 Bit 5
847 Status of signal lines USINT ●
BW_Channel_A Bit 0
BW_Channel_B Bit 1
BW_Channel_R Bit 2
811 Acknowledging error status of signal lines USINT ●
BW_QuitChannel_A Bit 0
BW_QuitChannel_B Bit 1
BW_QuitChannel_R Bit 2
6326 Encoder01TimeChanged INT ●
6324 DINT
6303 Encoder01LatchCount SINT ●
843 Status of encoder supplies USINT ●
PowerSupply01 Bit 0
PowerSupply02 Bit 1
Encoder - Configuration
513 CfO_SIframeGenID USINT ●
642 CfO_SystemCycleTime UINT ●
769 CfO_PhyIOConfigCh01 USINT ●
771 CfO_PhyIOConfigCh02 USINT ●
773 CfO_PhyIOConfigCh03 USINT ●
777 CfO_PhyIOConfigCh04 USINT ●
779 CfO_PhyIOConfigCh05 USINT ●
815 CfO_BWQuitTimeSelChannel7_0 USINT ●
820 CfO_BWQuitTime_0 UDINT ●
6145 CfO_CounterCycleSelect USINT ●
6147 CfO_CounterMode USINT ●
6149 CfO_LatchMode USINT ●
6151 CfO_LatchComparator USINT ●
6159 CfO_BWCNTEnableMaskChannel7_0 USINT ●

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4.11.3.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Encoder - Communication
6342 0 Encoder01 INT ●
6310 2 Encoder01TimeValid INT ●
6358 4 Encoder01Latch INT ●
6153 1 Encoder commands USINT ●
Encoder01Reset Bit 0
Encoder01LatchEnable Bit 1
927 7 Input status of signal lines USINT ●
Encoder01_A Bit 0
Encoder01_B Bit 1
Encoder01_R Bit 2
DigitalInput01 Bit 4
DigitalInput02 Bit 5
847 6 Status of signal lines USINT ●
BW_Channel_A Bit 0
BW_Channel_B Bit 1
BW_Channel_R Bit 2
811 0 Acknowledging error status of signal lines USINT ●
BW_QuitChannel_A Bit 0
BW_QuitChannel_B Bit 1
BW_QuitChannel_R Bit 2
6326 - Encoder01TimeChanged INT ●
6303 - Encoder01LatchCount SINT ●
843 - Status of encoder supplies USINT ●
PowerSupply01 Bit 0
PowerSupply02 Bit 1
Encoder - Configuration
513 - CfO_SIframeGenID USINT ●
642 - CfO_SystemCycleTime UINT ●
769 - CfO_PhyIOConfigCh01 USINT ●
771 - CfO_PhyIOConfigCh02 USINT ●
773 - CfO_PhyIOConfigCh03 USINT ●
777 - CfO_PhyIOConfigCh04 USINT ●
779 - CfO_PhyIOConfigCh05 USINT ●
815 - CfO_BWQuitTimeSelChannel7_0 USINT ●
820 - CfO_BWQuitTime_0 UDINT ●
6145 - CfO_CounterCycleSelect USINT ●
6147 - CfO_CounterMode USINT ●
6149 - CfO_LatchMode USINT ●
6151 - CfO_LatchComparator USINT ●
6159 - CfO_BWCNTEnableMaskChannel7_0 USINT ●

1) The offset specifies the position of the register within the CAN object.

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4.11.3.8.3 Encoder - Configuration

The following registers are used for setting functions and configuring the module.

4.11.3.8.3.1 Enabling error monitoring for the signal lines

Name:
CfO_BWCNTEnableMaskChannel7_0
This register requires individually enabling error monitoring for each of the signal channels. "Open line", "short
circuit" and "voltage level too low" are reported as error states. Any errors that occur are reported in the error status
registers BW_Channel_x.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Enable error monitoring for signal A lines 0 Error monitoring - Encoder Signal A disabled
1 Error monitoring - Encoder Signal A enabled - Only default in
bus controller function model
1 Enable error monitoring for signal B lines 0 Error monitoring - Encoder Signal B disabled
1 Error monitoring - Encoder Signal B enabled - Only default in
bus controller function model
2 Enable error monitoring for signal R lines 0 Error monitoring - Encoder Signal R disabled
1 Error monitoring - Encoder Signal R enabled - Only default in
bus controller function model
3-7 Reserved 0

4.11.3.8.3.2 Timing for automatic error acknowledgment

Name:
CfO_BWQuitTime_0
This register can be used to enable an additional automatic acknowledgment of the error status through timing.
If a valid time is set, then the acknowledgment can still be made manually, the only difference is that automatic
acknowledgment will take place on the module after the defined amount of time has passed. If the error state has
not yet been corrected, then the error status remains and the time is reset. Make sure that the time is set long
enough for the higher-level system to reliably detect the status messages.
If the timing = 0, then acknowledgment is only possible using the cyclic acknowledgment registers.
Data type Value Information
UDINT 0 No automatic acknowledgment - Only default in bus controller function model
1 to 2.147.483.647 Time for automatic acknowledgment [μs]

4.11.3.8.3.3 Setting the latch mode

Name:
CfO_LatchMode
This register is used to set the latch mode:
• Single shot latch mode:
The latch function must be enabled/set. After a successful latch procedure, the activation must be reset in
order for a new latch procedure to be activated.
• Continuous latch mode:
The latch function only has to be enabled/set as long as latching is desired.
A changed counter state on Encoder01LatchCount indicates that the latch procedure has been performed. The
counter value is stored in the latch register Encoder01Latch.
Data type Value Information
USINT 0 Single shot latch procedure
1 Continuous latch procedure

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4.11.3.8.3.4 Signal channels for triggering latch procedure

Name:
CfO_LatchComparator
This register defines the signal channels and their level for triggering the latch procedure.
• This mainly configures which channels are linked to generate the latch event. All three signals from the
encoder and digital input 1 can be used for the "AND" operation.
• The "active voltage level" needed for the latch procedure can now be used according to the physical signals.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Defines signal level for encoder signal A 0 Low
1 High
1 Defines signal level for encoder signal B 0 Low
1 High
2 Defines signal level for encoder signal R 0 Low
1 High
3 Defines signal level for digital input 1 0 Low
1 High
4 Use encoder signal A to trigger latch procedure 0 Disabled
1 Latch function linked to encoder signal A
5 Use encoder signal B to trigger latch procedure 0 Disabled
1 Latch function linked to encoder signal B
6 Use encoder signal R to trigger latch procedure 0 Disabled
1 Latch function linked to encoder signal R
7 Use digital input 1 to trigger latch procedure 0 Disabled
1 Latch function linked to digital input 1

4.11.3.8.3.5 Physical configuration

The following registers must be set to the specified constant value for correct physical configuration:

Constant register "CfO_SIframeGenID"

Name:
CfO_SIframeGenID
Data type Value Information
USINT 9 Only default in the bus controller module

Constant register "CfO_SystemCycleTime"

Name:
CfO_SystemCycleTime
Data type Value Information
UINT 800 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh01"

Name:
CfO_PhyIOConfigCh01
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh02"

Name:
CfO_PhyIOConfigCh02
Data type Value Information
USINT 0 Only default in the bus controller module

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Constant register "CfO_PhyIOConfigCh03"

Name:
CfO_PhyIOConfigCh03
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh04"

Name:
CfO_PhyIOConfigCh04
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh05"

Name:
CfO_PhyIOConfigCh05
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_BWQuitTimeSelChannel7_0"

Name:
CfO_BWQuitTimeSelChannel7_0
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_CounterCycleSelect"

Name:
CfO_CounterCycleSelect
Data type Value Information
USINT 2 Only default in the bus controller module

Constant register "CfO_CounterMode"

Name:
CfO_CounterMode
Data type Value Information
USINT 3 Only default in the bus controller module

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4.11.3.8.4 Encoder - Communication

4.11.3.8.4.1 Counter for verifying the data frame

Name:
SDCLifeCount
The 8-bit counter register is needed for the SDC software package. It is incremented with the system clock to allow
the SDC to check the validity of the data frame.
Data type Value
SINT -128 to 127

4.11.3.8.4.2 Display of the counter state

Name:
Encoder01
The counter state of the incremental encoder is displayed as a 16 or 32-bit counter value. Only the 16-bit value
is available in the bus controller function model.
Data type Value
INT -32768 to 32767
DINT1) -2.147.483.648 bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.3.8.4.3 Net time of the last valid counter value

Name:
Encoder01TimeValid
The net time of the last valid counter value is the time of the last valid counter value recorded on the module. The
user is able to determine the validity of the counter value by evaluating its age in the program. This means that the
module and error status bits do not have to be checked additionally to determine the validity of the value.
The net time of the last valid counter value that was read is displayed as a 16 or 32-bit value. Only the 16-bit value
is available in the bus controller function model.
Data type Value Information
INT -32768 to 32767 NetTime in µsec.
DINT1) -2.147.483.648
bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.3.8.4.4 Net time of the last counter value change

Name:
Encoder01TimeChanged
For slow X2X Link cycles, the net time of the last counter value change can be used to more accurately determine
the speed.
The net time of the last counter value change is displayed as 16 or 32-bit value. Only the 16-bit value is available
in the bus controller function model.
Data type Value Information
INT -32768 to 32767 NetTime in µsec.
DINT1) -2.147.483.648
bis 2.147.483.647

1) Can only be configured in the standard function model

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4.11.3.8.4.5 Counter value at the time of the last latch

Name:
Encoder01Latch
The counter value at the time of the last latch is displayed as a 16 or 32-bit value. Only the 16-bit value is available
in the bus controller function model.
Data type Value
INT -32768 to 32767
DINT1) -2.147.483.648 bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.3.8.4.6 Counter value of latch event

Name:
Encoder01LatchCount
The latch events are counted and stored in a cyclic 8-bit counter. This counter is incremented with each latch event,
thereby indicating a new occurrence. The new latched counter value is stored in the respective latch register.
Data type Value
SINT -128 to 127

4.11.3.8.4.7 Encoder commands

Name:
Encoder01Command
This register can be used to
1 reset the counter value. The counter is kept at zero until this command is reset.
2 enable the latch procedure. If the latch configuration is valid and matches the hardware signals, then this
activation causes the counter value to be saved in the latch register.
The two different latch configurations that are possible (see section 4.11.3.8.3.3 "Setting the latch mode") must
be handled as follows:
• Single shot latch mode:
After successful latching, indicated by the latch event counter, activation must be reset before any more
latching is possible. The activation must be set again if additional latching is needed.
• Continuous latch mode:
The latch function only has to be enabled/set as long as latching is desired. The latch event counter is
incremented with each event.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Encoder01Reset 0 Do not reset
1 Set encoder value to 0
1 Encoder01LatchEnable 0 Do not activate latch
1 Latching
2-7 Reserved 0

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4.11.3.8.4.8 Input status of signal lines

Name:
Encoder01_A
Encoder01_B
Encoder01_R
DigitalInput01 to DigitalInput02
This register displays the input status of the signal lines from the encoder and the digital inputs.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Encoder01_A 0/1 Input state of encoder signal A
1 Encoder01_B 0/1 Input state of encoder signal B
2 Encoder01_R 0/1 Input state of encoder signal R
3 Reserved 0
4 DigitalInput01 0/1 Input state - Digital input 1
5 DigitalInput02 0/1 Input state - Digital input 2
6-7 Reserved 0

4.11.3.8.4.9 Error status of signal lines

The error states are latched when they occur and are maintained until acknowledged. The counter and time reg-
isters are not updated if there are pending or unacknowledged errors.

Status of signal lines

Name:
BW_Channel_A
BW_Channel_B
BW_Channel_R
This register displays the error states of the signal lines from the encoder. The error states are latched when they
occur and are maintained until acknowledged. The counter and time registers are not updated if there are pending
or unacknowledged errors.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 BW_Channel_A 0 No error in encoder signal A
1 Open line, short circuit or voltage level too low
1 BW_Channel_B 0 No error in encoder signal B
1 Open line, short circuit or voltage level too low
2 BW_Channel_R 0 No error in encoder signal R
1 Open line, short circuit or voltage level too low
3-7 Reserved 0

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Acknowledging error status of signal lines

Name:
BW_QuitChannel_A
BW_QuitChannel_B
BW_QuitChannel_R
This register can be used to acknowledge the latched error states of the signal lines from the encoder. However,
if there are still pending errors remaining, then the error status remains active. After acknowledging the errors, the
bits must also be reset or else any repetition of the error would be undetected.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 BW_QuitChannel_A 0 No acknowledgment
1 Acknowledgment of error status - Encoder signal A
1 BW_QuitChannel_B 0 No acknowledgment
1 Acknowledgment of error status - Encoder signal B
2 BW_QuitChannel_R 0 No acknowledgment
1 Acknowledgment of error status - Encoder signal R
3-7 Reserved 0

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Manual acknowledgment of latched error states

The latched error states of the signal lines from the encoder can be acknowledged manually. However, if there
are still pending errors remaining, then the error status remains active. After successfully acknowledging the errors
(latched error status = 0), the acknowledge bits must still be reset by the user or else a re-occurrence of an error
could be overlooked by the user.
Example 1: Cause of error corrected before being acknowledged
An error has occurred on a signal line. The error state is detected and latched by the module.
The error is acknowledged by the user after the cause of error has been corrected. The latched
error status changes to zero.
The manual acknowledge must now be reset so that any new errors will be recognized by the
user.

Error on signal line

Latched error state

Manual acknowledgment

Latched error state = 0

⇒ Reset manual acknowledgment

Figure 261: Cause of error corrected before being acknowledged

Example 2: Cause of error not yet corrected before being acknowledged

An error has occurred on a signal line. The error state is detected and latched by the module.
The error is acknowledged by the user before the cause of error has been corrected. The latched
error status remains set because the error is still remaining.
Acknowledgment is only successful after the cause of error has been corrected. The latched
error status changes to zero. The manual acknowledge must now be reset so that any new errors
will be recognized by the user.

Error on signal line

Latched error state

Manual acknowledgment

Latched error state = 0

⇒ Reset manual acknowledgment

Figure 262: Cause of error not yet corrected before being acknowledged

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Automatic acknowledgment of latched error states

In addition to manual acknowledgment, automatic acknowledgment of the latched error states after a specified
amount of time can also be enabled. Make sure that the time is set long enough for the higher-level system to
reliably detect the status messages and for the validity of the counter value to be determined using its age.
If the time specification = 0, then only manual acknowledgment is possible.
Example 1: An error has occurred on a signal line. The error state is detected and latched by the module. The
time for automatic acknowledgment starts counting after the cause of error has been corrected.
The error is acknowledged as soon as the time expires. The latched error status changes to zero.

Error on signal line

Latched error state

Automatic acknowledgment

Time Time
start expired

Figure 263: Latched error state acknowledged automatically

Example 2: Automatic and manual acknowledge used

An error has occurred on a signal line. The error state is detected and latched by the module. The
time for automatic acknowledgment starts counting after the cause of error has been corrected.
The error is acknowledged manually by the user before the time expires. The latched error status
changes to zero. The manual acknowledge must now be reset so that any new errors will be
recognized by the user.

Error on signal line

Latched error state

Automatic acknowledgment

Time Time
start expired here

Manual acknowledgment

After successful error evaluation,

the error is manually acknowledged by the user

Figure 264: Automatic and manual acknowledge used

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4.11.3.8.4.10 Status of encoder supplies

Name:
PowerSupply01 to PowerSupply02
This register shows the status of the integrated encoder supplies. A faulty encoder power supply is displayed as
a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 PowerSupply01 0 24 VDC encoder power supply OK
1 24 VDC encoder power supply faulty
1 PowerSupply02 0 5 VDC encoder power supply OK
1 5 VDC encoder power supply faulty
2-7 Reserved -

4.11.3.8.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without causing a communication error
or impaired functionality. It should be noted that very fast cycles decrease the idle time available for handling
monitoring, diagnostics and acyclic commands.
Minimum cycle time
150 µs

4.11.3.8.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
150 µs

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4.11.4 X20DC1178

4.11.4.1 General information

This module is equipped with one input for SSI absolute encoders with 5 V encoder signal. The data signal is
monitored (Data, Data\).
• 1 SSI absolute encoder 5 V
• Monitoring the data signal
• 2 additional inputs
• 5 VDC, 24 VDC and GND for encoder supply

4.11.4.2 Order data

Model number Short description Figure

Counter functions
X20DC1178 X20 digital counter module, 1 SSI absolute encoders, 5 V, 1
MBit/s, 32-bit, encoder monitoring, NetTime module
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 227: X20DC1178 - Order data

4.11.4.3 Technical data

Product ID X20DC1178
Brief description
I/O module 1 SSI absolute encoder 5 V
General information
B&R ID code 0xA708
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.1 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Type of signal lines Shielded cables must be used for all signal lines
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Quantity 2
Nominal voltage 24 VDC
Input voltage 24 VDC (-15% / +20%)
Input current at 24 VDC Approx. 3.3 mA
Input filter
Hardware ≥2 µs
Software -
Connection type 3-wire connections
Input circuit Sink
Input resistance 7.03 kΩ

Table 228: X20DC1178 - Technical data

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Product ID X20DC1178
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
SSI absolute encoder
Counter size Encoder-dependent up to 32-bit
Max. transfer rate 1 Mbit/s
Keying Gray/Binary
Encoder signal 5 V, symmetrical
Isolation voltage between encoder and bus 500 Veff
Overload behavior of the encoder supply Short circuit protection, overload protection
Transfer rate 125 kbit/s / 250 kbit/s / 500 kbit/s / 1 Mbit/s
Encoder supply
5 VDC ±5%, module-internal, max. 300 mA
24 VDC Module-internal, max. 300 mA
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 228: X20DC1178 - Technical data

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4.11.4.4 LED status indicators

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Single flash Either the encoder monitor has detected a line fault on the encoder inputs or a
transfer error has occurred. The status bits must be evaluated in order to provide
a more detailed definition of this error.
The following error states are detected:
• Open line
• Short-circuit or voltage level too low
• SSI cycle time violation
• Parity error
On Error or reset status
D1 Green Input status - Data signal
1-2 Green Input state of the corresponding digital input

1) Depending on the configuration, a firmware update can take up to several minutes.

4.11.4.5 Pinout

Shielded cables must be used for all signal lines.

r e
X20 DC 1178

D1
1 2

Data Data\

Clock Clock\

DI 1 DI 2

Encoder 24 V + Encoder 5 V +

GND GND

4.11.4.6 Connection example

DC
Data
Counter 1

Data\
Clock

Clock\
Sensor 1

+24 VDC +24 VDC

GND GND

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4.11.4.7 Input circuit diagram

Counter input

Data

Recipient Input status

with monitoring

Data I/O status

LED (green)
24 V
PTC
Encoder 24 V

24 V
DC
Encoder 5 V
DC

GND

GND

Standard inputs

Input x

VDR
Input status

I/O status

Led (green)

4.11.4.8 Output circuit diagram

PTC
Clock
Output status
Transmitter
PTC
Clock

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4.11.4.9 Register description

4.11.4.9.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Configuration
650 CfO_SystemCyclePrescaler UINT ●
2049 CfO_CycleSelect USINT ●
2951 CfO_PhysicalMode USINT ●
2053 CfO_DataBits USINT ●
2055 CfO_NullBits USINT ●
820 CfO_BWQuitTime_0 UDINT ●
815 CfO_BWQuitTimeSelChannel7_0 USINT ●
2059 CfO_BWSSIEnableMaskChannel7_0 USINT ●
Communication
683 SDCLifeCount SINT ●
927 Input status of signal lines USINT ●
DigitalInput01 Bit 4
DigitalInput02 Bit 5
2100 Encoder01 (U)DINT ●
2102 Encoder01 UINT ●
2086 Encoder01TimeValid INT ●
2084 Encoder01TimeValid DINT ●
2094 Encoder01TimeChanged INT ●
2092 Encoder01TimeChanged DINT ●
259 State of the encoder USINT ●
EncoderCycleTimeViolation Bit 0
EncoderDataError Bit 1
323 Acknowledging error status of the encoder USINT ●
EncoderQuitCycleTimeViolation Bit 0
EncoderQuitDataError Bit 1
847 Status of signal lines USINT ●
BW_Channel_D Bit 0
811 Acknowledging error status of the signal line USINT ●
BW_QuitChannel_D Bit 0
843 Status of encoder supplies USINT ●
PowerSupply01 Bit 0
PowerSupply02 Bit 1

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4.11.4.9.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Configuration
650 - CfO_SystemCyclePrescaler UINT ●
2049 - CfO_CycleSelect USINT ●
2951 - CfO_PhysicalMode USINT ●
2053 - CfO_DataBits USINT ●
2055 - CfO_NullBits USINT ●
820 - CfO_BWQuitTime_0 UDINT ●
815 - CfO_BWQuitTimeSelChannel7_0 USINT ●
2059 - CfO_BWSSIEnableMaskChannel7_0 USINT ●
Communication
683 SDCLifeCount SINT ●
927 7 Input status of signal lines USINT ●
DigitalInput01 Bit 4
DigitalInput02 Bit 5
2100 - Encoder01 (U)DINT ●
2086 4 Encoder01TimeValid INT ●
2094 - Encoder01TimeChanged INT ●
259 - State of the encoder USINT ●
EncoderCycleTimeViolation Bit 0
EncoderDataError Bit 1
323 - Acknowledging error status of the encoder USINT ●
EncoderQuitCycleTimeViolation Bit 0
EncoderQuitDataError Bit 1
847 6 Status of signal lines USINT ●
BW_Channel_D Bit 0
811 0 Acknowledging error status of the signal line USINT ●
BW_QuitChannel_D Bit 0
843 - Status of encoder supplies USINT ●
PowerSupply01 Bit 0
PowerSupply02 Bit 1

1) The offset specifies the position of the register within the CAN object.

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4.11.4.9.3 Encoder - Configuration

The following registers are used for setting functions and configuring the module.

4.11.4.9.3.1 Setting the SSI sampling cycle time

The following two registers define the cycle time for SSI sampling.

Setting the interrupt

Name:
CfO_CycleSelect
This register assigns the principle interrupt setting:
• Timer configuration (time setting with CfO_SystemCyclePrescaler register): The SSI transfer can be
started independently of the X2X cycle. The timer is synchronized with X2X Link.
• AOAI: Configuration with X2X interrupt, one-time start of the SSI transfer in the X2X cycle. The SSI transfer
may require an entire X2X cycle.
• SOSI: Configuration with X2X interrupt, one-time start of the SSI transfer in the X2X cycle. The reaction
time can be optimized with this setting if the SSI transfer doesn't exceed half of an X2X cycle.
Data type Value Filter
USINT 3 Timer [μsec] ... Time setting with register CfO_SystemCyclePrescaler
10 AOAI
14 SOSI

Setting the cycle time

Name:
CfO_SystemCyclePrescaler
The desired cycle time must be configured additionally for the timer setting using this register.
Data type Value Filter
USINT 1 50 μs
2 100 μs
4 200 μs
8 400 μs
16 800 μs
0 All other settings in the CfO_CycleSelect register

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4.11.4.9.3.2 Setting operating parameters

Name:
CfO_PhysicalMode
This register defines the operating parameters for the SSI encoder to correctly evaluate the data from the encoder.
• Parity: Data with or without parity; an error is reported if there is an even or uneven parity mismatch.
• Monoflop check: The encoder uses the monoflop to signal the readiness to accept a new clock cycle.
• Data coding: Binary or gray coding of the data bits
• Clock rate: Speed of data transfer
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-1 Parity bit 00 No parity bit (no clock bit output)
01 Even parity bit
10 Uneven parity bit
11 Ignore parity bit (clock bit is output, but the result is ignored)
2-3 Monostable multivibrator testing 00 No monostable multivibrator check (no clock bit output)
01 Check - Low level
10 Check - High level
11 Check - Ignore level (clock bit is output, but the result is ignored)
4 Data coding 0 Binary coding
1 Gray coding
5 Reserved 0
6-7 Clock rate 00 1 MHz
01 500 kHz
10 250 kHz
11 125 kHz

Transfer to synchronous serial interface

1 2 3 4

Clock

Data Bit n Bit n - 1 Bit n - 3 Bit 1 Bit 0

Measurement value processing

1 Starting bit ... Stores the measurement value
2 Output of first data bit
3 All data bits are transferred, monostable multivibrator time starts counting down.
4 Monostable multivibrator returns to its initial state. A new transfer can be started.

4.11.4.9.3.3 Number of data bits

Name:
Cfo_DataBits
This register can be used to define the number of SSI encoder data bits.
Data type Value Filter
USINT 1 to 32 Number of SSI data bits

4.11.4.9.3.4 Leading zeros of the encoder

Name:
Cfo_NullBits
This register can be used to define the number of SSI encoder leading zeros.
Data type Value Filter
USINT 1 to 32 Number of leading zeros

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4.11.4.9.3.5 Timing for automatic error acknowledgment

Name:
CfO_BWQuitTime_0
This register can be used to enable an additional automatic acknowledgment of the error status through timing.
If a valid time is set, then the acknowledgment can still be made manually, the only difference is that automatic
acknowledgment will take place on the module after the defined amount of time has passed. If the error state has
not yet been corrected, then the error status remains and the time is reset. Make sure that the time is set long
enough for the higher-level system to reliably detect the status messages.
If the timing = 0, then acknowledgment is only possible using the cyclic acknowledgment registers.
Data type Value Information
UDINT 0 No automatic acknowledgment - Only default in bus controller function model
1 to 2.147.483.647 Time for automatic acknowledgment [μs]

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Automatic acknowledgment of latched error states

In addition to manual acknowledgment, automatic acknowledgment of the latched error states after a specified
amount of time can also be enabled. Make sure that the time is set long enough for the higher-level system to
reliably detect the status messages and for the validity of the counter value to be determined using its age.
If the time specification = 0, then only manual acknowledgment is possible.
Example 1: An error has occurred on a signal line. The error state is detected and latched by the module. The
time for automatic acknowledgment starts counting after the cause of error has been corrected.
The error is acknowledged as soon as the time expires. The latched error status changes to zero.

Error on signal line

Latched error state

Automatic acknowledgment

Time Time
start expired

Figure 265: Latched error state acknowledged automatically

Example 2: Automatic and manual acknowledge used

An error has occurred on a signal line. The error state is detected and latched by the module. The
time for automatic acknowledgment starts counting after the cause of error has been corrected.
The error is acknowledged manually by the user before the time expires. The latched error status
changes to zero. The manual acknowledge must now be reset so that any new errors will be
recognized by the user.

Error on signal line

Latched error state

Automatic acknowledgment

Time Time
start expired here

Manual acknowledgment

After successful error evaluation,

the error is manually acknowledged by the user

Figure 266: Automatic and manual acknowledge used

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Manual acknowledgment of latched error states

The latched error states of the signal lines from the encoder can be acknowledged manually. However, if there
are still pending errors remaining, then the error status remains active. After successfully acknowledging the errors
(latched error status = 0), the acknowledge bits must still be reset by the user or else a re-occurrence of an error
could be overlooked by the user.
Example 1: Cause of error corrected before being acknowledged
An error has occurred on a signal line. The error state is detected and latched by the module.
The error is acknowledged by the user after the cause of error has been corrected. The latched
error status changes to zero.
The manual acknowledge must now be reset so that any new errors will be recognized by the
user.

Error on signal line

Latched error state

Manual acknowledgment

Latched error state = 0

⇒ Reset manual acknowledgment

Figure 267: Cause of error corrected before being acknowledged

Example 2: Cause of error not yet corrected before being acknowledged

An error has occurred on a signal line. The error state is detected and latched by the module.
The error is acknowledged by the user before the cause of error has been corrected. The latched
error status remains set because the error is still remaining.
Acknowledgment is only successful after the cause of error has been corrected. The latched
error status changes to zero. The manual acknowledge must now be reset so that any new errors
will be recognized by the user.

Error on signal line

Latched error state

Manual acknowledgment

Latched error state = 0

⇒ Reset manual acknowledgment

Figure 268: Cause of error not yet corrected before being acknowledged

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4.11.4.9.3.6 Enable/disable error monitoring for the signal channels

Name:
CfO_BWSSIEnableMaskChannel7_0
This register allows error monitoring for each of the signal channels to be enabled individually. "Open line", "short
circuit" and "voltage level too low" are reported as error states. Any errors that occur are reported in the error
status registers.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Encoder signal D 0 Error monitoring switched off
1 Error monitoring enabled
1-7 Reserved 0

4.11.4.9.3.7 Physical configuration

The following registers must be set to the specified constant value for correct physical configuration:

Constant register "CfO_BWQuitTimeSelChannel7_0"

Name:
CfO_BWQuitTimeSelChannel7_0
Data type Value Information
USINT 0 Only default in the bus controller module

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4.11.4.9.4 Encoder - Communication

4.11.4.9.4.1 Counter for verifying the data frame

Name:
SDCLifeCount
The 8-bit counter register is needed for the SDC software package. It is incremented with the system clock to allow
the SDC to check the validity of the data frame.
Data type Value
SINT -128 to 127

4.11.4.9.4.2 Input status of signal lines

Name:
DigitalInput0 to DigitalInput02
This register displays the input states for the digital inputs.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-3 Reserved 0
4 DigitalInput01 0 or 1 Input state - Digital input 1
5 DigitalInput02 0 or 1 Input state - Digital input 2
6-7 Reserved 0

4.11.4.9.4.3 Display of the counter state

Name:
Encoder01
The counter state of the incremental encoder is displayed as a 16 or 32-bit counter value.
Data type Value
UDINT 0 to 4.294.967.295
DINT -2.147.483.648 to 2.147.483.647
UINT1) 0 to 65535

1) Only available in function model 0

4.11.4.9.4.4 Net time of the last valid counter value

Name:
Encoder01TimeValid
The net time of the last valid counter value is the time of the last valid counter value recorded on the module. The
user is able to determine the validity of the counter value by evaluating its age in the program. This means that the
module and error status bits do not have to be checked additionally to determine the validity of the value.
The net time of the last valid counter value that was read is displayed as a 16 or 32-bit value. Only the 16-bit value
is available in the bus controller function model.
Data type Value Information
INT -32768 to 32767 NetTime in µsec.
DINT1) -2.147.483.648
bis 2.147.483.647

1) Can only be configured in the standard function model

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4.11.4.9.4.5 Net time of the last counter value change

Name:
Encoder01TimeChanged
For slow X2X Link cycles, the net time of the last counter value change can be used to more accurately determine
the speed.
The net time of the last counter value change is displayed as 16 or 32-bit value. Only the 16-bit value is available
in the bus controller function model.
Data type Value Information
INT -32768 to 32767 NetTime in µsec.
DINT1) -2.147.483.648
bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.4.9.4.6 State of the encoder

Name:
EncoderCycleTimeViolation
EncoderDataError
This register displays the error states that occurred while determining the position. The error states are latched
when they occur and are maintained until acknowledged.
A cycle time error is triggered if:
• Transfer is still active: This means that the defined cycle time is shorter than the time resulting from the
sum of the data bits and stop bits and the clock rate.
• The monoflop level does not match the defined start level
• There is an error pending on the signal line (open line, short circuit).
A data error is triggered if:
• The parity bit does not match.
• An error occurs on the signal line (open line, short circuit) during transfer.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 EncoderCycleTimeViolation 0 No error
1 Error status - Cycle time violation
1 EncoderDataError 0 No error
1 Error status - Data error
2-7 Reserved 0

4.11.4.9.4.7 Acknowledging error status of the encoder

Name:
EncoderQuitCycleTimeViolation
EncoderQuitDataError
This register can be used to acknowledge the latched data error states from the encoder. However, if there are still
pending errors remaining, then the error status remains active. After acknowledging the errors, the bits must also
be reset or else any repetition of the error would be undetected.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 EncoderQuitCycleTimeViolation 0 No acknowledgment
1 Confirmation of error status - Cycle time violation
1 EncoderQuitDataError 0 No acknowledgment
1 Confirmation of error status - Data error
2-7 Reserved 0

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4.11.4.9.4.8 Status of signal lines

Name:
BW_Channel_D
This register displays the error state of the signal line from the encoder. The error state is latched when it occurs
and is maintained until acknowledged. The counter and time registers are not updated if there are pending or
unacknowledged errors.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 BW_Channel_D 0 No error - Encoder signal D
1 Error status - Open line or short circuit (voltage level too low)
1-7 Reserved 0

4.11.4.9.4.9 Acknowledging error status of the signal line

Name:
BW_QuitChannel_D
This register can be used to acknowledge the latched error states of the signal lines from the encoder. However,
if there are still pending errors remaining, then the error status remains active. After acknowledging the errors, the
bit must also be reset or else any repetition of the error will be undetected.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 BW_QuitChannel_D 0 No acknowledgment
1 Acknowledgment of error status
1-7 Reserved 0

4.11.4.9.4.10 Status of encoder supplies

Name:
PowerSupply01 to PowerSupply02
This register shows the status of the integrated encoder supplies. A faulty encoder power supply is displayed as
a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 PowerSupply01 0 24 VDC encoder power supply OK
1 24 VDC encoder power supply faulty
1 PowerSupply02 0 5 VDC encoder power supply OK
1 5 VDC encoder power supply faulty
2-7 Reserved -

4.11.4.9.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without causing a communication error
or impaired functionality. It should be noted that very fast cycles decrease the idle time available for handling
monitoring, diagnostics and acyclic commands.
Minimum cycle time
150 µs

4.11.4.9.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
150 µs

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4.11.5 X20DC1196

4.11.5.1 General information

The module is equipped with 1 input for an ABR incremental encoder with 5 V encoder signal.
• 1 ABR incremental encoder 5 V
• 2 additional inputs e.g. for home enable switch
• 5 VDC, 24 VDC and GND for encoder supply

4.11.5.2 Order data

Model number Short description Figure

Counter functions
X20DC1196 X20 digital counter module, 1 ABR incremental encoders, 5 V,
600 kHz input frequency, 4x evaluation
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 229: X20DC1196 - Order data

4.11.5.3 Technical data

Product ID X20DC1196
Brief description
I/O module 1 ABR incremental encoder 5 V
General information
B&R ID code 0x1BAF
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.5 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Encoder - Bus Yes
Channel - Bus Yes
Channel - Encoder No
Channel - Channel No
Type of signal lines Shielded cables must be used for all signal lines.
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Quantity 2
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Approx. 3.3 mA
Input filter
Hardware ≤2 μs
Software -
Connection type 3-wire connections
Input circuit Sink
Additional functions Home enable switch

Table 230: X20DC1196 - Technical data

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Product ID X20DC1196
Input resistance 7.19 kΩ
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
ABR incremental encoder
Encoder inputs 5 V, symmetrical
Counter size 16/32-bit
Input frequency Max. 600 kHz
Evaluation 4x
Encoder supply
5 VDC ±5%, module-internal, max. 300 mA
24 VDC Module-internal, max. 300 mA
Input filter
Hardware ≤200 ns
Software -
Common-mode range -7 V ≤ VCM ≤ +12 V
Overload behavior of the encoder supply Short circuit protection, overload protection
Isolation voltage between encoder and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 230: X20DC1196 - Technical data

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4.11.5.4 LED status indicators

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
A1 Green Input state of counter input A
B1 Green Input state of counter input B
R1 Green Input state of reference pulse R
1-2 Green Input state of the corresponding digital input

1) Depending on the configuration, a firmware update can take up to several minutes.

4.11.5.5 Pinout

Shielded cables must be used for all signal lines.

r e
X20 DC 1196
A1
B1
R1
1 2

A A\

B B\

R R\

DI 1 DI 2

Encoder 24 V + Encoder 5 V +

GND GND

4.11.5.6 Connection example

DC

A
A\
Counter 1

B
B\
R
R\
Sensor 1

+24 VDC +24 VDC

GND GND

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4.11.5.7 Input circuit diagram

Counter inputs

ABR
RS485
driver Input status

Recipient I/O status

ABR

LED (green)

24 V
PTC
Encoder 24 V

24 V
DC
Encoder 5 V
DC

GND

GND

Standard inputs

Input x

VDR
Input status

I/O status

Led (green)

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4.11.5.8 Register description

4.11.5.8.1 Function model 0 - Standard and

Function model 1 - Standard with 32-bit encoder counter value

The difference between function model 0 and function model 1 is the size of the data type for some registers.
• Function model 0 uses data type INT
• Function model 1 uses data type DINT (specified in parentheses)
Register Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
Configuration
4104 CfO_EdgeDetectFalling USINT ●
4106 CfO_EdgeDetectRising USINT ●
2064 CfO_PresetABR01_1(_32Bit) (D)INT ●
2068 CfO_PresetABR01_2(_32Bit) (D)INT ●
512 ConfigOutput24 UINT ●
522 ConfigOutput26 USINT ●
520 ConfigOutput27 USINT ●
Communication
2116 ReferenceModeEncoder01 USINT ●
2080 Encoder01 (D)INT ●
264 Input state of digital inputs 1 to 2 USINT ●
DigitalInput01 Bit 4
DigitalInput02 Bit 5
2118 StatusInput01 USINT ●
40 Status of encoder supplies USINT ●
PowerSupply01 Bit 0
PowerSupply02 Bit 1

4.11.5.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Configuration
4104 - CfO_EdgeDetectFalling USINT ●
4106 - CfO_EdgeDetectRising USINT ●
2064 - CfO_PresetABR01_1 INT ●
2068 - CfO_PresetABR01_2 INT ●
512 - ConfigOutput24 UINT ●
522 - ConfigOutput26 USINT ●
520 - ConfigOutput27 USINT ●
Communication
2116 0 ReferenceModeEncoder01 USINT ●
2080 0 Encoder01 INT ●
264 2 Input state of digital inputs 1 to 2 USINT ●
DigitalInput01 Bit 4
DigitalInput02 Bit 5
2118 4 StatusInput01 USINT ●
40 3 Status of encoder supplies USINT ●
PowerSupply01 Bit 0
PowerSupply02 Bit 1

1) The offset specifies the position of the register within the CAN object.

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4.11.5.8.3 ABR encoder - Configuration registers

4.11.5.8.3.1 Reference pulse

The following registers must be configured by a single acyclic write with the listed values so that the homing
procedure is completed on the edge of the reference pulse.
The homing procedure can take place on:
• Rising edge
• Falling edge (default configuration)

Constant register "CfO_EdgeDetectFalling"

Name:
CfO_EdgeDetectFalling
Data type Value Filter
USINT 0x00 Configuration value for rising edge
0x04 Configuration value for falling edge

Constant register "CfO_EdgeDetectRising"

Name:
CfO_EdgeDetectRising
Data type Value Filter
USINT 0x04 Configuration value for rising edge
0x00 Configuration value for falling edge

Constant register "ConfigOutput24"

Name:
ConfigOutput24
This register contains the value for ABR encoder 1.
Data type Value Filter
UINT 0x1012 Configuration value for rising edge
0x1002 Configuration value for falling edge

4.11.5.8.3.2 Setting the home position

Name:
Cfo_PresetABR01_1 to Cfo_PresetABR01_2
CfO_PresetABR01_1_32Bit to CfO_PresetABR01_2_32Bit (only in function model 1)
It is possible to specify two home positions with these registers through a one-off acyclic write, for example (default
= 0). The configured values are applied to the counter values after a completed homing procedure.
Data type Value
INT -32,768 to 32,767
DINT1) -2,147,483,648 to 2,147,483,647

1) Only in function model 1

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4.11.5.8.3.3 Homing with reference enable input

Regardless of the referencing mode, it is possible using this register to prevent the home position from being
applied when the corresponding reference input voltage level occurs (see 4.11.5.8.4.2 "Input state of digital inputs
1 to 2": bit 4). The desired setting can be configured by a one-off acyclic write.

Voltage level for reference enable activation

Name:
ConfigOutput26
The voltage level of the digital inputs to activate reference enable is configured with this register.
Data type Value Filter
USINT 0x00 Reference enable is active at 0 VDC
0x10 Reference enable for digital input 1 is active at 24 VDC
0x20 Reference enable for digital input 2 is active at 24 VDC
0x30 Reference enable for both digital inputs is active at 24 VDC

Reference enable of the input

Name:
ConfigOutput27
This register can be used to define whether the reference enable is activated.
Data type Value Filter
USINT 0x00 Reference enable input OFF (default)
0x10 Reference enable input 1 enabled
0x20 Reference enable input 2 enabled
0x30 Reference enable input 1 and 2 enabled

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4.11.5.8.4 ABR encoder - Configuration registers

4.11.5.8.4.1 Counter state of the encoder

Name:
Encoder01
The encoder values are represented as 16-bit or 32-bit counter values in this register.
Data type Value
INT -32,768 to 32,767
DINT1) -2,147,483,648 to 2,147,483,647

1) Only in function model 1

4.11.5.8.4.2 Input state of digital inputs 1 to 2

Name:
DigitalInput01 to DigitalInput02.
This register displays the input status of the encoders and the digital inputs.
Data type Value
USINT See bit structure.

Bit Name Value Information

0 Encoder A 0 or 1 Input state
1 Encoder B 0 or 1 Input state
2 Encoder A + B 0 or 1 Input state of reference pulse
4 DigitalInput01 0 or 1 Input state - Digital input 1
5 DigitalInput02 0 or 1 Input state - Digital input 2

4.11.5.8.4.3 Reading the referencing mode

Name:
ReferenceModeEncoder01
This register determines the referencing mode.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-1 00 Referencing OFF
01 Single shot referencing
11 Continuous referencing
2-5 0 Bits permanently set = 0
6-7 00 Referencing OFF
11 Bits permanently set = 1

This results in the following values:

Binary Hex Function
00000000 0x00 Referencing OFF
11000001 0xC1 Single shot referencing
For a new start after the completed homing procedure:
• Write value 0x00
• Wait until bit 0 to bit 3 of the StatusInput01 register takes on the value 0. Counter
bits 4 to 7 are not erased
• Switch homing procedure on again
11000011 0xC3 Continuous referencing
Referencing occurs at every reference pulse.
It is important to know how the optional reference enable is configured. See section 4.11.5.8.3.3 "Homing with
reference enable input"

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4.11.5.8.4.4 Status of the homing procedure

Name:
StatusInput01
This register contains information regarding whether the referencing process is off, active or complete.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Reference pulse without homing1) 0 No reference impulse without homing has occurred yet
1 At least a reference impulse without homing has occurred
1 State change 0 or 1 Changes with each reference pulse without homing
2 Reference pulse with homing1) 0 No homing has occurred yet
1 At least one homing procedure has occurred
3 State change 0 or 1 Changes with each homing procedure that has taken place
4 Reference pulse 0 The last reference pulse didn't bring about a homing procedure
1 The last reference pulse brought about a homing procedure
5-7 Counter x Free-running counter, increased with each reference pulse

1) Always 1 after the first reference pulse that has occurred

Examples of possible values:

Binary Hex Function
0x00000000 0x00 Referencing OFF or homing procedure already active
0x00111100 0x3CE First homing procedure complete Reference value applied in the Encoder01 register
0xxxx11100 0xxB Bits 5 to 7 are changed with each reference pulse
0xxxx1x100 0xxx Continuously changing the bits with the "Continuous referencing" setting. The refer-
ence value is applied to the Encoder01 register on each reference pulse.
It is important to know how the optional reference enable (see section 4.11.5.8.3.3 "Homing with reference enable
input" on page 690) is configured.

4.11.5.8.4.5 Status of encoder supplies

Name:
PowerSupply01 to PowerSupply02
This register shows the status of the integrated encoder supplies. A faulty encoder power supply is displayed as
a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 PowerSupply01 0 24 VDC encoder power supply OK
1 24 VDC encoder power supply faulty
1 PowerSupply02 0 5 VDC encoder power supply OK
1 5 VDC encoder power supply faulty
2-7 Reserved -

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4.11.5.8.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
128 μs

4.11.5.8.6 Maximum cycle time

The maximum cycle time defines how far the bus cycle can be increased without internal counter overflows causing
module malfunctions.
Minimum cycle time
16 ms

4.11.5.8.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
128 μs

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4.11.6 X20DC1198

4.11.6.1 General information

This module is equipped with one input for SSI absolute encoders with 5 V encoder signal.
• 1 SSI absolute encoder 5 V
• 2 additional inputs
• 5 VDC, 24 VDC and GND for encoder supply

4.11.6.2 Order data

Model number Short description Figure

Counter functions
X20DC1198 X20 digital counter module, 1 SSI absolute encoder, 5 V, 1 MBit/
s, 32-bit
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 231: X20DC1198 - Order data

4.11.6.3 Technical data

Product ID X20DC1198
Brief description
I/O module 1 SSI absolute encoder 5 V
General information
B&R ID code 0x1BB0
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.5 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Encoder - Bus Yes
Channel - Bus Yes
Channel - Encoder No
Channel - Channel No
Type of signal lines Shielded cables must be used for all signal lines.
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Quantity 2
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Approx. 3.3 mA
Input filter
Hardware ≥2 µs
Software -
Connection type 3-wire connections
Input circuit Sink
Input resistance 7.19 kΩ

Table 232: X20DC1198 - Technical data

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Product ID X20DC1198
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
SSI absolute encoder
Encoder inputs 5 V, symmetrical
Counter size 32-bit
Max. transfer rate 1 Mbit/s
Keying Gray/Binary
Isolation voltage between encoder and bus 500 Veff
Overload behavior of the encoder supply Short circuit protection, overload protection
Transfer rate 125 kbit/s / 250 kbit/s / 500 kbit/s / 1 Mbit/s
Encoder supply
5 VDC ±5%, module-internal, max. 300 mA
24 VDC Module-internal, max. 300 mA
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 232: X20DC1198 - Technical data

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4.11.6.4 LED status indicators

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
D1 Green Input status - Data signal
1-2 Green Input state of the corresponding digital input

1) Depending on the configuration, a firmware update can take up to several minutes.

4.11.6.5 Pinout

Shielded cables must be used for all signal lines.

r e

X20 DC 1198
D1
1 2

Data Data\

Clock Clock\

DI 1 DI 2

Encoder 24 V + Encoder 5 V +

GND GND

4.11.6.6 Connection example

DC
Data
Counter 1

Data\
Clock

Clock\
Sensor 1

+24 VDC +24 VDC

GND GND

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4.11.6.7 Input circuit diagram

Counter input

Data
RS485
driver Input status

Recipient I/O status

Data

LED (green)

24 V
PTC
Encoder 24 V

24 V
DC
Encoder 5 V
DC

GND

GND

Standard inputs

Input x

VDR
Input status

I/O status

Led (green)

4.11.6.8 Output circuit diagram

PTC
Clock
RS485
Output status driver
PTC
Transmitter
Clock

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4.11.6.9 Register description

4.11.6.9.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Configuration
7176 ConfigOutput14 UINT ●
7172 ConfigAdvanced UDINT ●
Communication
7184 Encoder01 UDINT ●
264 Input state of digital inputs 1 to 2 USINT ●
DigitalInput01 Bit 4
DigitalInput02 Bit 5
40 Status of encoder supplies USINT ●
PowerSupply01 Bit 0
PowerSupply02 Bit 1

4.11.6.9.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Configuration
7176 - ConfigOutput14 UINT ●
7172 - ConfigAdvanced UDINT ●
Communication
7184 0 Encoder01 UDINT ●
264 4 Input state of digital inputs 1 to 2 USINT ●
DigitalInput01 Bit 4
DigitalInput02 Bit 5
40 5 Status of encoder supplies USINT ●
PowerSupply01 Bit 0
PowerSupply02 Bit 1

1) The offset specifies the position of the register within the CAN object.

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4.11.6.9.3 SSI encoder configuration register

4.11.6.9.3.1 Standard configuration

Name:
ConfigOutput14
This configuration register is used to set the coding, the clock rate and the number of bits. Default = 0. This must
be set once using an acyclic write command.
Data type Value
UINT See bit structure.

Bit structure:
Bit Name Value Information
0-5 SSI value valid bits x
6-7 Clock rate 00 1 MHz
01 500 kHz
10 250 kHz
11 125 kHz
8 - 13 SSI number of bits x Number of bits including leading zeros
14 Reserved 0
15 Keying 0 Binary coding
1 Gray coding

4.11.6.9.3.2 Extended configuration

Name:
ConfigAdvanced
This configuration register is used to set the coding, the clock rate, the number of bits and the monostable multivi-
brator settings. Default = 0. This must be set once using an acyclic write command.
It only differs from ConfigOutput14 by data length and additional monostable multivibrator testing.
Data type Value
UDINT See bit structure.

Bit structure:
Bit Name Value Information
0-5 SSI value valid bits x
6-7 Clock rate 00 1 MHz
01 500 kHz
10 250 kHz
11 125 kHz
8 - 13 SSI number of bits x Number of bits including leading zeros
14 Reserved 0
15 Keying 0 Binary coding
1 Gray coding
16 - 17 Monostable multivibrator testing 00 Check OFF, no additional clock bit
01 Check set to High level
10 Check set to Low level
11 Level is clocked but ignored
18 - 31 Reserved 0 Reserved

Transfer to synchronous serial interface

1 2 3 4

Clock

Data Bit n Bit n - 1 Bit n - 3 Bit 1 Bit 0

Measurement value processing

1 Starting bit ... Stores the measurement value
2 Output of first data bit
3 All data bits are transferred, monostable multivibrator time starts counting down.
4 Monostable multivibrator returns to its initial state. A new transfer can be started.

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4.11.6.9.4 SSI encoder - Configuration registers

4.11.6.9.4.1 SSI position values

Name:
Encoder01
The SSI encoder value is displayed as a 32-bit position value. The SSI position value is generated synchronously
with the X2X cycle.
Data type Value Filter
UDINT 0 to 4,294,967,295 SSI position

4.11.6.9.4.2 Input state of digital inputs 1 to 2

Name:
DigitalInput01 to DigitalInput02
This register is used to indicate the input state of digital inputs 1 to 2.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
4 DigitalInput01 0 or 1 Input state - Digital input 1
5 DigitalInput02 0 or 1 Input state - Digital input 2

4.11.6.9.4.3 Status of encoder supplies

Name:
PowerSupply01 to PowerSupply02
This register shows the status of the integrated encoder supplies. A faulty encoder power supply is displayed as
a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 PowerSupply01 0 24 VDC encoder power supply OK
1 24 VDC encoder power supply faulty
1 PowerSupply02 0 5 VDC encoder power supply OK
1 5 VDC encoder power supply faulty
2-7 Reserved -

4.11.6.9.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
128 μs

4.11.6.9.6 Maximum cycle time

The maximum cycle time defines how far the bus cycle can be increased without internal counter overflows causing
module malfunctions.
Minimum cycle time
16 ms

4.11.6.9.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
128 μs

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4.11.7 X20DC11A6

4.11.7.1 General information

The module is equipped with 1 input for an ABR incremental encoder with 5 V encoder signal. The encoder inputs
are monitored (A, B, R, A\, B\, R\).
• 1 ABR incremental encoder 5 V
• Encoder input monitoring (up to 250 kHz input frequency)
• 2 additional inputs, e.g. for latch input
• 5 VDC, 24 VDC and GND for encoder supply

4.11.7.2 Order data

Model number Short description Figure

Counter functions
X20DC11A6 X20 digital counter module, 1 ABR incremental encoders, 5 V, 5
MHz input frequency, 4x evaluation
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 233: X20DC11A6 - Order data

4.11.7.3 Technical data

Product ID X20DC11A6
Brief description
I/O module 1 ABR incremental encoder 5 V
General information
B&R ID code 0xB76B
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.0 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Type of signal lines Shielded cables must be used for all signal lines
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Quantity 2
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Approx. 3.3 mA
Input filter
Hardware ≤30 ns
Software -
Connection type 3-wire connections
Input circuit Sink
Additional functions Latch input
Input resistance 7.03 kΩ

Table 234: X20DC11A6 - Technical data

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Product ID X20DC11A6
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
ABR incremental encoder
Encoder inputs 5 V, symmetrical
Counter size 16/32-bit
Input frequency Max. 5 MHz
Evaluation 4x
Encoder supply
5 VDC ±5%, module-internal, max. 300 mA
24 VDC Module-internal, max. 300 mA
Input filter
Hardware ≤30 ns
Software -
Common-mode range -10 V ≤ VCM ≤ +13.2 V
Overload behavior of the encoder supply Short circuit protection, overload protection
Isolation voltage between encoder and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 234: X20DC11A6 - Technical data

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4.11.7.4 LED status indicators

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Single flash The encoder monitor has detected a line fault on the encoder inputs. The status
bits must be evaluated in order to provide a more detailed definition of this error.
The following error states are detected:
• Broken connection (up to 250 kHz input frequency)
• Short-circuit or voltage level too low
On Error or reset status
A1 Green Input state of counter input A
B1 Green Input state of counter input B
R1 Green Input state of reference pulse R
1-2 Green Input state of the corresponding digital input

1) Depending on the configuration, a firmware update can take up to several minutes.

4.11.7.5 Pinout

Shielded cables must be used for all signal lines.

r e
X20 DC 11A6

A1
B1
R1
1 2

A A\

B B\

R R\

DI 1 DI 2

Encoder 24 V+ Encoder 5 V+

GND GND

4.11.7.6 Connection example

DC

A
A\
Counter 1

B
B\
R
R\
Sensor 1

+24 VDC +24 VDC

GND GND

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4.11.7.7 Input circuit diagram

Counter inputs

ABR

Recipient Input status

with monitoring

ABR I/O status

LED (green)
24 V
PTC
Encoder 24 V

24 V
DC
Encoder 5 V
DC

GND

GND

Standard inputs

Input x

VDR
Input status

I/O status

Led (green)

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4.11.7.8 Register description

4.11.7.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Encoder - Communication
683 SDCLifeCount SINT ●
6342 Encoder01 INT ●
6340 DINT
6310 Encoder01TimeValid INT ●
6308 DINT
6358 Encoder01Latch INT ●
6356 DINT
6153 Encoder commands USINT ●
Encoder01Reset Bit 0
Encoder01LatchEnable Bit 1
927 Input status of signal lines USINT ●
Encoder01_A Bit 0
Encoder01_B Bit 1
Encoder01_R Bit 2
DigitalInput01 Bit 4
DigitalInput02 Bit 5
847 Status of signal lines USINT ●
BW_Channel_A Bit 0
BW_Channel_B Bit 1
BW_Channel_R Bit 2
811 Acknowledging error status of signal lines USINT ●
BW_QuitChannel_A Bit 0
BW_QuitChannel_B Bit 1
BW_QuitChannel_R Bit 2
6326 Encoder01TimeChanged INT ●
6324 DINT
6303 Encoder01LatchCount SINT ●
843 Status of encoder supplies USINT ●
PowerSupply01 Bit 0
PowerSupply02 Bit 1
Encoder - Configuration
513 CfO_SIframeGenID USINT ●
642 CfO_SystemCycleTime UINT ●
769 CfO_PhyIOConfigCh01 USINT ●
771 CfO_PhyIOConfigCh02 USINT ●
773 CfO_PhyIOConfigCh03 USINT ●
777 CfO_PhyIOConfigCh04 USINT ●
779 CfO_PhyIOConfigCh05 USINT ●
815 CfO_BWQuitTimeSelChannel7_0 USINT ●
820 CfO_BWQuitTime_0 UDINT ●
6145 CfO_CounterCycleSelect USINT ●
6147 CfO_CounterMode USINT ●
6149 CfO_LatchMode USINT ●
6151 CfO_LatchComparator USINT ●
6159 CfO_BWCNTEnableMaskChannel7_0 USINT ●

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4.11.7.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Encoder - Communication
6342 0 Encoder01 INT ●
6310 2 Encoder01TimeValid INT ●
6358 4 Encoder01Latch INT ●
6153 1 Encoder commands USINT ●
Encoder01Reset Bit 0
Encoder01LatchEnable Bit 1
927 7 Input status of signal lines USINT ●
Encoder01_A Bit 0
Encoder01_B Bit 1
Encoder01_R Bit 2
DigitalInput01 Bit 4
DigitalInput02 Bit 5
847 6 Status of signal lines USINT ●
BW_Channel_A Bit 0
BW_Channel_B Bit 1
BW_Channel_R Bit 2
811 0 Acknowledging error status of signal lines USINT ●
BW_QuitChannel_A Bit 0
BW_QuitChannel_B Bit 1
BW_QuitChannel_R Bit 2
6326 - Encoder01TimeChanged INT ●
6303 - Encoder01LatchCount SINT ●
843 - Status of encoder supplies USINT ●
PowerSupply01 Bit 0
PowerSupply02 Bit 1
Encoder - Configuration
513 - CfO_SIframeGenID USINT ●
642 - CfO_SystemCycleTime UINT ●
769 - CfO_PhyIOConfigCh01 USINT ●
771 - CfO_PhyIOConfigCh02 USINT ●
773 - CfO_PhyIOConfigCh03 USINT ●
777 - CfO_PhyIOConfigCh04 USINT ●
779 - CfO_PhyIOConfigCh05 USINT ●
815 - CfO_BWQuitTimeSelChannel7_0 USINT ●
820 - CfO_BWQuitTime_0 UDINT ●
6145 - CfO_CounterCycleSelect USINT ●
6147 - CfO_CounterMode USINT ●
6149 - CfO_LatchMode USINT ●
6151 - CfO_LatchComparator USINT ●
6159 - CfO_BWCNTEnableMaskChannel7_0 USINT ●

1) The offset specifies the position of the register within the CAN object.

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4.11.7.8.3 Encoder - Configuration

The following registers are used for setting functions and configuring the module.

4.11.7.8.3.1 Enabling error monitoring for the signal lines

Name:
CfO_BWCNTEnableMaskChannel7_0
This register requires individually enabling error monitoring for each of the signal channels. "Open line", "short
circuit" and "voltage level too low" are reported as error states. Any errors that occur are reported in the error status
registers BW_Channel_x.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Enable error monitoring for signal A lines 0 Error monitoring - Encoder Signal A disabled
1 Error monitoring - Encoder Signal A enabled - Only default in
bus controller function model
1 Enable error monitoring for signal B lines 0 Error monitoring - Encoder Signal B disabled
1 Error monitoring - Encoder Signal B enabled - Only default in
bus controller function model
2 Enable error monitoring for signal R lines 0 Error monitoring - Encoder Signal R disabled
1 Error monitoring - Encoder Signal R enabled - Only default in
bus controller function model
3-7 Reserved 0

4.11.7.8.3.2 Timing for automatic error acknowledgment

Name:
CfO_BWQuitTime_0
This register can be used to enable an additional automatic acknowledgment of the error status through timing.
If a valid time is set, then the acknowledgment can still be made manually, the only difference is that automatic
acknowledgment will take place on the module after the defined amount of time has passed. If the error state has
not yet been corrected, then the error status remains and the time is reset. Make sure that the time is set long
enough for the higher-level system to reliably detect the status messages.
If the timing = 0, then acknowledgment is only possible using the cyclic acknowledgment registers.
Data type Value Information
UDINT 0 No automatic acknowledgment - Only default in bus controller function model
1 to 2.147.483.647 Time for automatic acknowledgment [μs]

4.11.7.8.3.3 Setting the latch mode

Name:
CfO_LatchMode
This register is used to set the latch mode:
• Single shot latch mode:
The latch function must be enabled/set. After a successful latch procedure, the activation must be reset in
order for a new latch procedure to be activated.
• Continuous latch mode:
The latch function only has to be enabled/set as long as latching is desired.
A changed counter state on Encoder01LatchCount indicates that the latch procedure has been performed. The
counter value is stored in the latch register Encoder01Latch.
Data type Value Information
USINT 0 Single shot latch procedure
1 Continuous latch procedure

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4.11.7.8.3.4 Signal channels for triggering latch procedure

Name:
CfO_LatchComparator
This register defines the signal channels and their level for triggering the latch procedure.
• This mainly configures which channels are linked to generate the latch event. All three signals from the
encoder and digital input 1 can be used for the "AND" operation.
• The "active voltage level" needed for the latch procedure can now be used according to the physical signals.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Defines signal level for encoder signal A 0 Low
1 High
1 Defines signal level for encoder signal B 0 Low
1 High
2 Defines signal level for encoder signal R 0 Low
1 High
3 Defines signal level for digital input 1 0 Low
1 High
4 Use encoder signal A to trigger latch procedure 0 Disabled
1 Latch function linked to encoder signal A
5 Use encoder signal B to trigger latch procedure 0 Disabled
1 Latch function linked to encoder signal B
6 Use encoder signal R to trigger latch procedure 0 Disabled
1 Latch function linked to encoder signal R
7 Use digital input 1 to trigger latch procedure 0 Disabled
1 Latch function linked to digital input 1

4.11.7.8.3.5 Physical configuration

The following registers must be set to the specified constant value for correct physical configuration:

Constant register "CfO_SIframeGenID"

Name:
CfO_SIframeGenID
Data type Value Information
USINT 9 Only default in the bus controller module

Constant register "CfO_SystemCycleTime"

Name:
CfO_SystemCycleTime
Data type Value Information
UINT 800 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh01"

Name:
CfO_PhyIOConfigCh01
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh02"

Name:
CfO_PhyIOConfigCh02
Data type Value Information
USINT 0 Only default in the bus controller module

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Constant register "CfO_PhyIOConfigCh03"

Name:
CfO_PhyIOConfigCh03
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh04"

Name:
CfO_PhyIOConfigCh04
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh05"

Name:
CfO_PhyIOConfigCh05
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_BWQuitTimeSelChannel7_0"

Name:
CfO_BWQuitTimeSelChannel7_0
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_CounterCycleSelect"

Name:
CfO_CounterCycleSelect
Data type Value Information
USINT 2 Only default in the bus controller module

Constant register "CfO_CounterMode"

Name:
CfO_CounterMode
Data type Value Information
USINT 3 Only default in the bus controller module

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4.11.7.8.4 Encoder - Communication

4.11.7.8.4.1 Counter for verifying the data frame

Name:
SDCLifeCount
The 8-bit counter register is needed for the SDC software package. It is incremented with the system clock to allow
the SDC to check the validity of the data frame.
Data type Value
SINT -128 to 127

4.11.7.8.4.2 Display of the counter state

Name:
Encoder01
The counter state of the incremental encoder is displayed as a 16 or 32-bit counter value. Only the 16-bit value
is available in the bus controller function model.
Data type Value
INT -32768 to 32767
DINT1) -2.147.483.648 bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.7.8.4.3 Net time of the last valid counter value

Name:
Encoder01TimeValid
The net time of the last valid counter value is the time of the last valid counter value recorded on the module. The
user is able to determine the validity of the counter value by evaluating its age in the program. This means that the
module and error status bits do not have to be checked additionally to determine the validity of the value.
The net time of the last valid counter value that was read is displayed as a 16 or 32-bit value. Only the 16-bit value
is available in the bus controller function model.
Data type Value Information
INT -32768 to 32767 NetTime in µsec.
DINT1) -2.147.483.648
bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.7.8.4.4 Net time of the last counter value change

Name:
Encoder01TimeChanged
For slow X2X Link cycles, the net time of the last counter value change can be used to more accurately determine
the speed.
The net time of the last counter value change is displayed as 16 or 32-bit value. Only the 16-bit value is available
in the bus controller function model.
Data type Value Information
INT -32768 to 32767 NetTime in µsec.
DINT1) -2.147.483.648
bis 2.147.483.647

1) Can only be configured in the standard function model

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4.11.7.8.4.5 Counter value at the time of the last latch

Name:
Encoder01Latch
The counter value at the time of the last latch is displayed as a 16 or 32-bit value. Only the 16-bit value is available
in the bus controller function model.
Data type Value
INT -32768 to 32767
DINT1) -2.147.483.648 bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.7.8.4.6 Counter value of latch event

Name:
Encoder01LatchCount
The latch events are counted and stored in a cyclic 8-bit counter. This counter is incremented with each latch event,
thereby indicating a new occurrence. The new latched counter value is stored in the respective latch register.
Data type Value
SINT -128 to 127

4.11.7.8.4.7 Encoder commands

Name:
Encoder01Command
This register can be used to
1 reset the counter value. The counter is kept at zero until this command is reset.
2 enable the latch procedure. If the latch configuration is valid and matches the hardware signals, then this
activation causes the counter value to be saved in the latch register.
The two different latch configurations that are possible (see section 4.11.7.8.3.3 "Setting the latch mode") must
be handled as follows:
• Single shot latch mode:
After successful latching, indicated by the latch event counter, activation must be reset before any more
latching is possible. The activation must be set again if additional latching is needed.
• Continuous latch mode:
The latch function only has to be enabled/set as long as latching is desired. The latch event counter is
incremented with each event.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Encoder01Reset 0 Do not reset
1 Set encoder value to 0
1 Encoder01LatchEnable 0 Do not activate latch
1 Latching
2-7 Reserved 0

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4.11.7.8.4.8 Input status of signal lines

Name:
Encoder01_A
Encoder01_B
Encoder01_R
DigitalInput01 to DigitalInput02
This register displays the input status of the signal lines from the encoder and the digital inputs.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Encoder01_A 0/1 Input state of encoder signal A
1 Encoder01_B 0/1 Input state of encoder signal B
2 Encoder01_R 0/1 Input state of encoder signal R
3 Reserved 0
4 DigitalInput01 0/1 Input state - Digital input 1
5 DigitalInput02 0/1 Input state - Digital input 2
6-7 Reserved 0

4.11.7.8.4.9 Error status of signal lines

The error states are latched when they occur and are maintained until acknowledged. The counter and time reg-
isters are not updated if there are pending or unacknowledged errors.

Status of signal lines

Name:
BW_Channel_A
BW_Channel_B
BW_Channel_R
This register displays the error states of the signal lines from the encoder. The error states are latched when they
occur and are maintained until acknowledged. The counter and time registers are not updated if there are pending
or unacknowledged errors.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 BW_Channel_A 0 No error in encoder signal A
1 Open line, short circuit or voltage level too low
1 BW_Channel_B 0 No error in encoder signal B
1 Open line, short circuit or voltage level too low
2 BW_Channel_R 0 No error in encoder signal R
1 Open line, short circuit or voltage level too low
3-7 Reserved 0

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Acknowledging error status of signal lines

Name:
BW_QuitChannel_A
BW_QuitChannel_B
BW_QuitChannel_R
This register can be used to acknowledge the latched error states of the signal lines from the encoder. However,
if there are still pending errors remaining, then the error status remains active. After acknowledging the errors, the
bits must also be reset or else any repetition of the error would be undetected.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 BW_QuitChannel_A 0 No acknowledgment
1 Acknowledgment of error status - Encoder signal A
1 BW_QuitChannel_B 0 No acknowledgment
1 Acknowledgment of error status - Encoder signal B
2 BW_QuitChannel_R 0 No acknowledgment
1 Acknowledgment of error status - Encoder signal R
3-7 Reserved 0

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Manual acknowledgment of latched error states

The latched error states of the signal lines from the encoder can be acknowledged manually. However, if there
are still pending errors remaining, then the error status remains active. After successfully acknowledging the errors
(latched error status = 0), the acknowledge bits must still be reset by the user or else a re-occurrence of an error
could be overlooked by the user.
Example 1: Cause of error corrected before being acknowledged
An error has occurred on a signal line. The error state is detected and latched by the module.
The error is acknowledged by the user after the cause of error has been corrected. The latched
error status changes to zero.
The manual acknowledge must now be reset so that any new errors will be recognized by the
user.

Error on signal line

Latched error state

Manual acknowledgment

Latched error state = 0

⇒ Reset manual acknowledgment

Figure 269: Cause of error corrected before being acknowledged

Example 2: Cause of error not yet corrected before being acknowledged

An error has occurred on a signal line. The error state is detected and latched by the module.
The error is acknowledged by the user before the cause of error has been corrected. The latched
error status remains set because the error is still remaining.
Acknowledgment is only successful after the cause of error has been corrected. The latched
error status changes to zero. The manual acknowledge must now be reset so that any new errors
will be recognized by the user.

Error on signal line

Latched error state

Manual acknowledgment

Latched error state = 0

⇒ Reset manual acknowledgment

Figure 270: Cause of error not yet corrected before being acknowledged

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Automatic acknowledgment of latched error states

In addition to manual acknowledgment, automatic acknowledgment of the latched error states after a specified
amount of time can also be enabled. Make sure that the time is set long enough for the higher-level system to
reliably detect the status messages and for the validity of the counter value to be determined using its age.
If the time specification = 0, then only manual acknowledgment is possible.
Example 1: An error has occurred on a signal line. The error state is detected and latched by the module. The
time for automatic acknowledgment starts counting after the cause of error has been corrected.
The error is acknowledged as soon as the time expires. The latched error status changes to zero.

Error on signal line

Latched error state

Automatic acknowledgment

Time Time
start expired

Figure 271: Latched error state acknowledged automatically

Example 2: Automatic and manual acknowledge used

An error has occurred on a signal line. The error state is detected and latched by the module. The
time for automatic acknowledgment starts counting after the cause of error has been corrected.
The error is acknowledged manually by the user before the time expires. The latched error status
changes to zero. The manual acknowledge must now be reset so that any new errors will be
recognized by the user.

Error on signal line

Latched error state

Automatic acknowledgment

Time Time
start expired here

Manual acknowledgment

After successful error evaluation,

the error is manually acknowledged by the user

Figure 272: Automatic and manual acknowledge used

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4.11.7.8.4.10 Status of encoder supplies

Name:
PowerSupply01 to PowerSupply02
This register shows the status of the integrated encoder supplies. A faulty encoder power supply is displayed as
a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 PowerSupply01 0 24 VDC encoder power supply OK
1 24 VDC encoder power supply faulty
1 PowerSupply02 0 5 VDC encoder power supply OK
1 5 VDC encoder power supply faulty
2-7 Reserved -

4.11.7.8.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without causing a communication error
or impaired functionality. It should be noted that very fast cycles decrease the idle time available for handling
monitoring, diagnostics and acyclic commands.
Minimum cycle time
150 µs

4.11.7.8.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
150 µs

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4.11.8 X20DC1376

4.11.8.1 General information

The module is equipped with 1 input for an ABR incremental encoder with 24 V encoder signal. The encoder inputs
are monitored (A, B, R).
• 1 ABR incremental encoder 24 V, asymmetric
• Encoder input monitoring
• 2 additional inputs, e.g. for latch input
• 24 VDC and GND for encoder supply

4.11.8.2 Order data

Model number Short description Figure

Counter functions
X20DC1376 X20 digital counter module, 1 ABR incremental encoder, 24 V
100 kHz input frequency, 4x evaluation, encoder monitoring,
NetTime module
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 235: X20DC1376 - Order data

4.11.8.3 Technical data

Product ID X20DC1376
Short description
I/O module 1 ABR incremental encoder 24 V
General information
Input voltage 24 VDC (-15% / +20%)
B&R ID code 0xA705
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.3 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Type of signal lines Shielded cables must be used for all signal lines
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Quantity 2
Nominal voltage 24 VDC
Input voltage 24 VDC (-15% / +20%)
Input current at 24 VDC Approx. 3.3 mA
Input filter
Hardware ≤2 µs
Software -
Connection type 3-wire connections
Input circuit Sink
Additional functions Latch input

Table 236: X20DC1376 - Technical data

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Product ID X20DC1376
Input resistance 7.03 kΩ
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
ABR incremental encoder
Encoder inputs 24 V, asymmetrical (single-ended)
Counter size 16/32-bit
Input frequency Max. 100 kHz
Evaluation 4x
Encoder supply Module-internal, max. 600 mA
Input filter
Hardware ≤1 μs
Software -
Isolation voltage between encoder and bus 500 Veff
Operating conditions
mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating When operated at temperatures above 55°C, the power consumption of
the modules to the left and right of this module must not exceed 1.15 W
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 236: X20DC1376 - Technical data

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4.11.8.4 LED status indicators

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Single flash The encoder monitor has detected a line fault on the encoder inputs. The status
bits must be evaluated in order to provide a more detailed definition of this error.
The following error states are detected:
• Open line
• Short-circuit or voltage level too low
On Error or reset status
A1 Green Input state of counter input A
B1 Green Input state of counter input B
R1 Green Input state of reference pulse R
1-2 Green Input status - digital input

1) Depending on the configuration, a firmware update can take up to several minutes.

4.11.8.5 Pinout

Shielded cables must be used for all signal lines.

r e
X20 DC 1376

A1
B1
R1
1 2

DI 1 DI 2

Encoder 24 V+

GND GND

4.11.8.6 Connection example

DC

A
Counter 1

+24 VDC +24 VDC

GND GND

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4.11.8.7 Input circuit diagram

Counter inputs

ABR

VDR Input status

Recipient
with monitoring

I/O status

LED (green)

24 V
PTC
Encoder 24 V

GND

GND

Standard inputs

Input x

VDR
Input status

I/O status

Led (green)

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4.11.8.8 Register description

4.11.8.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Encoder - Communication
683 SDCLifeCount SINT ●
6342 Encoder01 INT ●
6340 DINT
6310 Encoder01TimeValid INT ●
6308 DINT
6358 Encoder01Latch INT ●
6356 DINT
6153 Encoder commands USINT ●
Encoder01Reset Bit 0
Encoder01LatchEnable Bit 1
927 Input status of signal lines USINT ●
Encoder01_A Bit 0
Encoder01_B Bit 1
Encoder01_R Bit 2
DigitalInput01 Bit 4
DigitalInput02 Bit 5
847 Status of signal lines USINT ●
BW_Channel_A Bit 0
BW_Channel_B Bit 1
BW_Channel_R Bit 2
811 Acknowledging error status of signal lines USINT ●
BW_QuitChannel_A Bit 0
BW_QuitChannel_B Bit 1
BW_QuitChannel_R Bit 2
6326 Encoder01TimeChanged INT ●
6324 DINT
6303 Encoder01LatchCount SINT ●
843 Status of encoder supply USINT ●
PowerSupply01 Bit 0
Encoder - Configuration
513 CfO_SIframeGenID USINT ●
642 CfO_SystemCycleTime UINT ●
769 CfO_PhyIOConfigCh01 USINT ●
771 CfO_PhyIOConfigCh02 USINT ●
773 CfO_PhyIOConfigCh03 USINT ●
777 CfO_PhyIOConfigCh04 USINT ●
779 CfO_PhyIOConfigCh05 USINT ●
815 CfO_BWQuitTimeSelChannel7_0 USINT ●
820 CfO_BWQuitTime_0 UDINT ●
6145 CfO_CounterCycleSelect USINT ●
6147 CfO_CounterMode USINT ●
6149 CfO_LatchMode USINT ●
6151 CfO_LatchComparator USINT ●
6159 CfO_BWCNTEnableMaskChannel7_0 USINT ●

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4.11.8.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Encoder - Communication
6342 0 Encoder01 INT ●
6310 2 Encoder01TimeValid INT ●
6358 4 Encoder01Latch INT ●
6153 1 Encoder commands USINT ●
Encoder01Reset Bit 0
Encoder01LatchEnable Bit 1
927 7 Input status of signal lines USINT ●
Encoder01_A Bit 0
Encoder01_B Bit 1
Encoder01_R Bit 2
DigitalInput01 Bit 4
DigitalInput02 Bit 5
847 6 Status of signal lines USINT ●
BW_Channel_A Bit 0
BW_Channel_B Bit 1
BW_Channel_R Bit 2
811 0 Acknowledging error status of signal lines USINT ●
BW_QuitChannel_A Bit 0
BW_QuitChannel_B Bit 1
BW_QuitChannel_R Bit 2
6326 - Encoder01TimeChanged INT ●
6303 - Encoder01LatchCount SINT ●
843 - Status of encoder supply USINT ●
PowerSupply01 Bit 0
Encoder - Configuration
513 - CfO_SIframeGenID USINT ●
642 - CfO_SystemCycleTime UINT ●
769 - CfO_PhyIOConfigCh01 USINT ●
771 - CfO_PhyIOConfigCh02 USINT ●
773 - CfO_PhyIOConfigCh03 USINT ●
777 - CfO_PhyIOConfigCh04 USINT ●
779 - CfO_PhyIOConfigCh05 USINT ●
815 - CfO_BWQuitTimeSelChannel7_0 USINT ●
820 - CfO_BWQuitTime_0 UDINT ●
6145 - CfO_CounterCycleSelect USINT ●
6147 - CfO_CounterMode USINT ●
6149 - CfO_LatchMode USINT ●
6151 - CfO_LatchComparator USINT ●
6159 - CfO_BWCNTEnableMaskChannel7_0 USINT ●

1) The offset specifies the position of the register within the CAN object.

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4.11.8.8.3 Encoder - Configuration

The following registers are used for setting functions and configuring the module.

4.11.8.8.3.1 Enabling error monitoring for the signal lines

Name:
CfO_BWCNTEnableMaskChannel7_0
This register requires individually enabling error monitoring for each of the signal channels. "Open line", "short
circuit" and "voltage level too low" are reported as error states. Any errors that occur are reported in the error status
registers BW_Channel_x.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Enable error monitoring for signal A lines 0 Error monitoring - Encoder Signal A disabled
1 Error monitoring - Encoder Signal A enabled - Only default in
bus controller function model
1 Enable error monitoring for signal B lines 0 Error monitoring - Encoder Signal B disabled
1 Error monitoring - Encoder Signal B enabled - Only default in
bus controller function model
2 Enable error monitoring for signal R lines 0 Error monitoring - Encoder Signal R disabled
1 Error monitoring - Encoder Signal R enabled - Only default in
bus controller function model
3-7 Reserved 0

4.11.8.8.3.2 Timing for automatic error acknowledgment

Name:
CfO_BWQuitTime_0
This register can be used to enable an additional automatic acknowledgment of the error status through timing.
If a valid time is set, then the acknowledgment can still be made manually, the only difference is that automatic
acknowledgment will take place on the module after the defined amount of time has passed. If the error state has
not yet been corrected, then the error status remains and the time is reset. Make sure that the time is set long
enough for the higher-level system to reliably detect the status messages.
If the timing = 0, then acknowledgment is only possible using the cyclic acknowledgment registers.
Data type Value Information
UDINT 0 No automatic acknowledgment - Only default in bus controller function model
1 to 2.147.483.647 Time for automatic acknowledgment [μs]

4.11.8.8.3.3 Setting the latch mode

Name:
CfO_LatchMode
This register is used to set the latch mode:
• Single shot latch mode:
The latch function must be enabled/set. After a successful latch procedure, the activation must be reset in
order for a new latch procedure to be activated.
• Continuous latch mode:
The latch function only has to be enabled/set as long as latching is desired.
A changed counter state on Encoder01LatchCount indicates that the latch procedure has been performed. The
counter value is stored in the latch register Encoder01Latch.
Data type Value Information
USINT 0 Single shot latch procedure
1 Continuous latch procedure

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4.11.8.8.3.4 Signal channels for triggering latch procedure

Name:
CfO_LatchComparator
This register defines the signal channels and their level for triggering the latch procedure.
• This mainly configures which channels are linked to generate the latch event. All three signals from the
encoder and digital input 1 can be used for the "AND" operation.
• The "active voltage level" needed for the latch procedure can now be used according to the physical signals.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Defines signal level for encoder signal A 0 Low
1 High
1 Defines signal level for encoder signal B 0 Low
1 High
2 Defines signal level for encoder signal R 0 Low
1 High
3 Defines signal level for digital input 1 0 Low
1 High
4 Use encoder signal A to trigger latch procedure 0 Disabled
1 Latch function linked to encoder signal A
5 Use encoder signal B to trigger latch procedure 0 Disabled
1 Latch function linked to encoder signal B
6 Use encoder signal R to trigger latch procedure 0 Disabled
1 Latch function linked to encoder signal R
7 Use digital input 1 to trigger latch procedure 0 Disabled
1 Latch function linked to digital input 1

4.11.8.8.3.5 Physical configuration

The following registers must be set to the specified constant value for correct physical configuration:

Constant register "CfO_SIframeGenID"

Name:
CfO_SIframeGenID
Data type Value Information
USINT 9 Only default in the bus controller module

Constant register "CfO_SystemCycleTime"

Name:
CfO_SystemCycleTime
Data type Value Information
UINT 800 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh01"

Name:
CfO_PhyIOConfigCh01
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh02"

Name:
CfO_PhyIOConfigCh02
Data type Value Information
USINT 0 Only default in the bus controller module

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Constant register "CfO_PhyIOConfigCh03"

Name:
CfO_PhyIOConfigCh03
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh04"

Name:
CfO_PhyIOConfigCh04
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh05"

Name:
CfO_PhyIOConfigCh05
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_BWQuitTimeSelChannel7_0"

Name:
CfO_BWQuitTimeSelChannel7_0
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_CounterCycleSelect"

Name:
CfO_CounterCycleSelect
Data type Value Information
USINT 2 Only default in the bus controller module

Constant register "CfO_CounterMode"

Name:
CfO_CounterMode
Data type Value Information
USINT 3 Only default in the bus controller module

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4.11.8.8.4 Encoder - Communication

4.11.8.8.4.1 Counter for verifying the data frame

Name:
SDCLifeCount
The 8-bit counter register is needed for the SDC software package. It is incremented with the system clock to allow
the SDC to check the validity of the data frame.
Data type Value
SINT -128 to 127

4.11.8.8.4.2 Display of the counter state

Name:
Encoder01
The counter state of the incremental encoder is displayed as a 16 or 32-bit counter value. Only the 16-bit value
is available in the bus controller function model.
Data type Value
INT -32768 to 32767
DINT1) -2.147.483.648 bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.8.8.4.3 Net time of the last valid counter value

Name:
Encoder01TimeValid
The net time of the last valid counter value is the time of the last valid counter value recorded on the module. The
user is able to determine the validity of the counter value by evaluating its age in the program. This means that the
module and error status bits do not have to be checked additionally to determine the validity of the value.
The net time of the last valid counter value that was read is displayed as a 16 or 32-bit value. Only the 16-bit value
is available in the bus controller function model.
Data type Value Information
INT -32768 to 32767 NetTime in µsec.
DINT1) -2.147.483.648
bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.8.8.4.4 Net time of the last counter value change

Name:
Encoder01TimeChanged
For slow X2X Link cycles, the net time of the last counter value change can be used to more accurately determine
the speed.
The net time of the last counter value change is displayed as 16 or 32-bit value. Only the 16-bit value is available
in the bus controller function model.
Data type Value Information
INT -32768 to 32767 NetTime in µsec.
DINT1) -2.147.483.648
bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.8.8.4.5 Counter value at the time of the last latch

Name:
Encoder01Latch
The counter value at the time of the last latch is displayed as a 16 or 32-bit value. Only the 16-bit value is available
in the bus controller function model.
Data type Value
INT -32768 to 32767
DINT1) -2.147.483.648 bis 2.147.483.647

1) Can only be configured in the standard function model

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4.11.8.8.4.6 Counter value of latch event

Name:
Encoder01LatchCount
The latch events are counted and stored in a cyclic 8-bit counter. This counter is incremented with each latch event,
thereby indicating a new occurrence. The new latched counter value is stored in the respective latch register.
Data type Value
SINT -128 to 127

4.11.8.8.4.7 Encoder commands

Name:
Encoder01Command
This register can be used to
1 reset the counter value. The counter is kept at zero until this command is reset.
2 enable the latch procedure. If the latch configuration is valid and matches the hardware signals, then this
activation causes the counter value to be saved in the latch register.
The two different latch configurations that are possible (see section 4.11.8.8.3.3 "Setting the latch mode") must
be handled as follows:
• Single shot latch mode:
After successful latching, indicated by the latch event counter, activation must be reset before any more
latching is possible. The activation must be set again if additional latching is needed.
• Continuous latch mode:
The latch function only has to be enabled/set as long as latching is desired. The latch event counter is
incremented with each event.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Encoder01Reset 0 Do not reset
1 Set encoder value to 0
1 Encoder01LatchEnable 0 Do not activate latch
1 Latching
2-7 Reserved 0

4.11.8.8.4.8 Input status of signal lines

Name:
Encoder01_A
Encoder01_B
Encoder01_R
DigitalInput01 to DigitalInput02
This register displays the input status of the signal lines from the encoder and the digital inputs.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Encoder01_A 0/1 Input state of encoder signal A
1 Encoder01_B 0/1 Input state of encoder signal B
2 Encoder01_R 0/1 Input state of encoder signal R
3 Reserved 0
4 DigitalInput01 0/1 Input state - Digital input 1
5 DigitalInput02 0/1 Input state - Digital input 2
6-7 Reserved 0

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4.11.8.8.4.9 Error status of signal lines

The error states are latched when they occur and are maintained until acknowledged. The counter and time reg-
isters are not updated if there are pending or unacknowledged errors.

Status of signal lines

Name:
BW_Channel_A
BW_Channel_B
BW_Channel_R
This register displays the error states of the signal lines from the encoder. The error states are latched when they
occur and are maintained until acknowledged. The counter and time registers are not updated if there are pending
or unacknowledged errors.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 BW_Channel_A 0 No error in encoder signal A
1 Open line, short circuit or voltage level too low
1 BW_Channel_B 0 No error in encoder signal B
1 Open line, short circuit or voltage level too low
2 BW_Channel_R 0 No error in encoder signal R
1 Open line, short circuit or voltage level too low
3-7 Reserved 0

Acknowledging error status of signal lines

Name:
BW_QuitChannel_A
BW_QuitChannel_B
BW_QuitChannel_R
This register can be used to acknowledge the latched error states of the signal lines from the encoder. However,
if there are still pending errors remaining, then the error status remains active. After acknowledging the errors, the
bits must also be reset or else any repetition of the error would be undetected.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 BW_QuitChannel_A 0 No acknowledgment
1 Acknowledgment of error status - Encoder signal A
1 BW_QuitChannel_B 0 No acknowledgment
1 Acknowledgment of error status - Encoder signal B
2 BW_QuitChannel_R 0 No acknowledgment
1 Acknowledgment of error status - Encoder signal R
3-7 Reserved 0

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Manual acknowledgment of latched error states

The latched error states of the signal lines from the encoder can be acknowledged manually. However, if there
are still pending errors remaining, then the error status remains active. After successfully acknowledging the errors
(latched error status = 0), the acknowledge bits must still be reset by the user or else a re-occurrence of an error
could be overlooked by the user.
Example 1: Cause of error corrected before being acknowledged
An error has occurred on a signal line. The error state is detected and latched by the module.
The error is acknowledged by the user after the cause of error has been corrected. The latched
error status changes to zero.
The manual acknowledge must now be reset so that any new errors will be recognized by the
user.

Error on signal line

Latched error state

Manual acknowledgment

Latched error state = 0

⇒ Reset manual acknowledgment

Figure 273: Cause of error corrected before being acknowledged

Example 2: Cause of error not yet corrected before being acknowledged

An error has occurred on a signal line. The error state is detected and latched by the module.
The error is acknowledged by the user before the cause of error has been corrected. The latched
error status remains set because the error is still remaining.
Acknowledgment is only successful after the cause of error has been corrected. The latched
error status changes to zero. The manual acknowledge must now be reset so that any new errors
will be recognized by the user.

Error on signal line

Latched error state

Manual acknowledgment

Latched error state = 0

⇒ Reset manual acknowledgment

Figure 274: Cause of error not yet corrected before being acknowledged

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Automatic acknowledgment of latched error states

In addition to manual acknowledgment, automatic acknowledgment of the latched error states after a specified
amount of time can also be enabled. Make sure that the time is set long enough for the higher-level system to
reliably detect the status messages and for the validity of the counter value to be determined using its age.
If the time specification = 0, then only manual acknowledgment is possible.
Example 1: An error has occurred on a signal line. The error state is detected and latched by the module. The
time for automatic acknowledgment starts counting after the cause of error has been corrected.
The error is acknowledged as soon as the time expires. The latched error status changes to zero.

Error on signal line

Latched error state

Automatic acknowledgment

Time Time
start expired

Figure 275: Latched error state acknowledged automatically

Example 2: Automatic and manual acknowledge used

An error has occurred on a signal line. The error state is detected and latched by the module. The
time for automatic acknowledgment starts counting after the cause of error has been corrected.
The error is acknowledged manually by the user before the time expires. The latched error status
changes to zero. The manual acknowledge must now be reset so that any new errors will be
recognized by the user.

Error on signal line

Latched error state

Automatic acknowledgment

Time Time
start expired here

Manual acknowledgment

After successful error evaluation,

the error is manually acknowledged by the user

Figure 276: Automatic and manual acknowledge used

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4.11.8.8.4.10 Status of encoder supply

Name:
PowerSupply01
This register shows the status of the integrated encoder supply. A faulty encoder power supply is displayed as
a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 PowerSupply01 0 24 VDC encoder power supply OK
1 24 VDC encoder power supply faulty
1-7 Reserved -

4.11.8.8.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without causing a communication error
or impaired functionality. It should be noted that very fast cycles decrease the idle time available for handling
monitoring, diagnostics and acyclic commands.
Minimum cycle time
150 µs

4.11.8.8.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
150 µs

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4.11.9 X20DC137A

4.11.9.1 General information

The module is equipped with 1 input for an ABR incremental encoder with 24 V differential signals. The encoder
inputs are monitored (A, B, R, A\, B\, R\).
• 1 ABR incremental encoder 24 V, differential
• Encoder input monitoring
• 2 additional inputs, e.g. for latch input
• 24 VDC and GND for encoder supply

4.11.9.2 Order data

Model number Short description Figure

Counter functions
X20DC137A X20 digital counter module, 1x ABR incremental encoder, 24 V
(differential), 300 kHz input frequency, 4x evaluation, encoder
monitoring, NetTime module
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 237: X20DC137A - Order data

4.11.9.3 Technical data

Product ID X20DC137A
Brief description
I/O module 1 ABR incremental encoder 24 V, differential
General information
B&R ID code 0xDD28
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.2 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Type of signal lines Shielded cables must be used for all signal lines
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
GL Yes
GOST-R Yes
Digital inputs
Quantity 2
Nominal voltage 24 VDC
Input voltage 24 VDC (-15% / +20%)
Input current at 24 VDC Approx. 3.3 mA
Input filter
Hardware ≤2 µs
Software -
Connection type 3-wire connections
Input circuit Sink
Additional functions Latch input
Input resistance 7.03 kΩ

Table 238: X20DC137A - Technical data

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Product ID X20DC137A
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
ABR incremental encoder
Encoder inputs 24 V, differential
Counter size 16/32-bit
Input frequency Max. 300 kHz
Evaluation 4x
Encoder supply Module-internal, max. 600 mA
Input filter
Hardware ≤0.5 µs
Software -
Common-mode range -10 V ≤ VCM ≤ +13 V
Overload behavior of the encoder supply Short circuit protection, overload protection
Isolation voltage between encoder and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating When operated at temperatures above 55°C, the power consumption of
the modules to the left and right of this module must not exceed 1.15 W
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 238: X20DC137A - Technical data

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4.11.9.4 LED status indicators

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Single flash The encoder monitor has detected a line fault on the encoder inputs. The status
bits must be evaluated in order to provide a more detailed definition of this error.
The following error states are detected:
• Open line
• Short-circuit or voltage level too low
On Error or reset status
A1 Green Input state of counter input A
B1 Green Input state of counter input B
R1 Green Input state of reference pulse R
1-2 Green Input state of the corresponding digital input

1) Depending on the configuration, a firmware update can take up to several minutes.

4.11.9.5 Pinout

Shielded cables must be used for all signal lines.

r e
X20 DC 137A

A1
B1
R1
1 2

A A\

B B\

R R\

DI 1 DI 2

Encoder 24 V+

GND GND

4.11.9.6 Connection example

DC

A
A\
Counter 1

B
B\
R
R\
Sensor 1

+24 VDC +24 VDC

GND GND

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4.11.9.7 Input circuit diagram

Counter inputs

ABR
VDR
Recipient Input status
with monitoring
VDR
ABR\ I/O Status

LED (green)

24 V
PTC
Encoder 24 V

GND

GND

Standard inputs

Input x

VDR
Input status

I/O status

Led (green)

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4.11.9.8 Register description

4.11.9.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Encoder - Communication
683 SDCLifeCount SINT ●
6342 Encoder01 INT ●
6340 DINT
6310 Encoder01TimeValid INT ●
6308 DINT
6358 Encoder01Latch INT ●
6356 DINT
6153 Encoder commands USINT ●
Encoder01Reset Bit 0
Encoder01LatchEnable Bit 1
927 Input status of signal lines USINT ●
Encoder01_A Bit 0
Encoder01_B Bit 1
Encoder01_R Bit 2
DigitalInput01 Bit 4
DigitalInput02 Bit 5
847 Status of signal lines USINT ●
BW_Channel_A Bit 0
BW_Channel_B Bit 1
BW_Channel_R Bit 2
811 Acknowledging error status of signal lines USINT ●
BW_QuitChannel_A Bit 0
BW_QuitChannel_B Bit 1
BW_QuitChannel_R Bit 2
6326 Encoder01TimeChanged INT ●
6324 DINT
6303 Encoder01LatchCount SINT ●
843 Status of encoder supply USINT ●
PowerSupply01 Bit 0
Encoder - Configuration
513 CfO_SIframeGenID USINT ●
642 CfO_SystemCycleTime UINT ●
769 CfO_PhyIOConfigCh01 USINT ●
771 CfO_PhyIOConfigCh02 USINT ●
773 CfO_PhyIOConfigCh03 USINT ●
777 CfO_PhyIOConfigCh04 USINT ●
779 CfO_PhyIOConfigCh05 USINT ●
815 CfO_BWQuitTimeSelChannel7_0 USINT ●
820 CfO_BWQuitTime_0 UDINT ●
6145 CfO_CounterCycleSelect USINT ●
6147 CfO_CounterMode USINT ●
6149 CfO_LatchMode USINT ●
6151 CfO_LatchComparator USINT ●
6159 CfO_BWCNTEnableMaskChannel7_0 USINT ●

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4.11.9.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Encoder - Communication
6342 0 Encoder01 INT ●
6310 2 Encoder01TimeValid INT ●
6358 4 Encoder01Latch INT ●
6153 1 Encoder commands USINT ●
Encoder01Reset Bit 0
Encoder01LatchEnable Bit 1
927 7 Input status of signal lines USINT ●
Encoder01_A Bit 0
Encoder01_B Bit 1
Encoder01_R Bit 2
DigitalInput01 Bit 4
DigitalInput02 Bit 5
847 6 Status of signal lines USINT ●
BW_Channel_A Bit 0
BW_Channel_B Bit 1
BW_Channel_R Bit 2
811 0 Acknowledging error status of signal lines USINT ●
BW_QuitChannel_A Bit 0
BW_QuitChannel_B Bit 1
BW_QuitChannel_R Bit 2
6326 - Encoder01TimeChanged INT ●
6303 - Encoder01LatchCount SINT ●
843 - Status of encoder supply USINT ●
PowerSupply01 Bit 0
Encoder - Configuration
513 - CfO_SIframeGenID USINT ●
642 - CfO_SystemCycleTime UINT ●
769 - CfO_PhyIOConfigCh01 USINT ●
771 - CfO_PhyIOConfigCh02 USINT ●
773 - CfO_PhyIOConfigCh03 USINT ●
777 - CfO_PhyIOConfigCh04 USINT ●
779 - CfO_PhyIOConfigCh05 USINT ●
815 - CfO_BWQuitTimeSelChannel7_0 USINT ●
820 - CfO_BWQuitTime_0 UDINT ●
6145 - CfO_CounterCycleSelect USINT ●
6147 - CfO_CounterMode USINT ●
6149 - CfO_LatchMode USINT ●
6151 - CfO_LatchComparator USINT ●
6159 - CfO_BWCNTEnableMaskChannel7_0 USINT ●

1) The offset specifies the position of the register within the CAN object.

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4.11.9.8.3 Encoder - Configuration

The following registers are used for setting functions and configuring the module.

4.11.9.8.3.1 Enabling error monitoring for the signal lines

Name:
CfO_BWCNTEnableMaskChannel7_0
This register requires individually enabling error monitoring for each of the signal channels. "Open line", "short
circuit" and "voltage level too low" are reported as error states. Any errors that occur are reported in the error status
registers BW_Channel_x.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Enable error monitoring for signal A lines 0 Error monitoring - Encoder Signal A disabled
1 Error monitoring - Encoder Signal A enabled - Only default in
bus controller function model
1 Enable error monitoring for signal B lines 0 Error monitoring - Encoder Signal B disabled
1 Error monitoring - Encoder Signal B enabled - Only default in
bus controller function model
2 Enable error monitoring for signal R lines 0 Error monitoring - Encoder Signal R disabled
1 Error monitoring - Encoder Signal R enabled - Only default in
bus controller function model
3-7 Reserved 0

4.11.9.8.3.2 Timing for automatic error acknowledgment

Name:
CfO_BWQuitTime_0
This register can be used to enable an additional automatic acknowledgment of the error status through timing.
If a valid time is set, then the acknowledgment can still be made manually, the only difference is that automatic
acknowledgment will take place on the module after the defined amount of time has passed. If the error state has
not yet been corrected, then the error status remains and the time is reset. Make sure that the time is set long
enough for the higher-level system to reliably detect the status messages.
If the timing = 0, then acknowledgment is only possible using the cyclic acknowledgment registers.
Data type Value Information
UDINT 0 No automatic acknowledgment - Only default in bus controller function model
1 to 2.147.483.647 Time for automatic acknowledgment [μs]

4.11.9.8.3.3 Setting the latch mode

Name:
CfO_LatchMode
This register is used to set the latch mode:
• Single shot latch mode:
The latch function must be enabled/set. After a successful latch procedure, the activation must be reset in
order for a new latch procedure to be activated.
• Continuous latch mode:
The latch function only has to be enabled/set as long as latching is desired.
A changed counter state on Encoder01LatchCount indicates that the latch procedure has been performed. The
counter value is stored in the latch register Encoder01Latch.
Data type Value Information
USINT 0 Single shot latch procedure
1 Continuous latch procedure

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4.11.9.8.3.4 Signal channels for triggering latch procedure

Name:
CfO_LatchComparator
This register defines the signal channels and their level for triggering the latch procedure.
• This mainly configures which channels are linked to generate the latch event. All three signals from the
encoder and digital input 1 can be used for the "AND" operation.
• The "active voltage level" needed for the latch procedure can now be used according to the physical signals.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Defines signal level for encoder signal A 0 Low
1 High
1 Defines signal level for encoder signal B 0 Low
1 High
2 Defines signal level for encoder signal R 0 Low
1 High
3 Defines signal level for digital input 1 0 Low
1 High
4 Use encoder signal A to trigger latch procedure 0 Disabled
1 Latch function linked to encoder signal A
5 Use encoder signal B to trigger latch procedure 0 Disabled
1 Latch function linked to encoder signal B
6 Use encoder signal R to trigger latch procedure 0 Disabled
1 Latch function linked to encoder signal R
7 Use digital input 1 to trigger latch procedure 0 Disabled
1 Latch function linked to digital input 1

4.11.9.8.3.5 Physical configuration

The following registers must be set to the specified constant value for correct physical configuration:

Constant register "CfO_SIframeGenID"

Name:
CfO_SIframeGenID
Data type Value Information
USINT 9 Only default in the bus controller module

Constant register "CfO_SystemCycleTime"

Name:
CfO_SystemCycleTime
Data type Value Information
UINT 800 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh01"

Name:
CfO_PhyIOConfigCh01
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh02"

Name:
CfO_PhyIOConfigCh02
Data type Value Information
USINT 0 Only default in the bus controller module

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Constant register "CfO_PhyIOConfigCh03"

Name:
CfO_PhyIOConfigCh03
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh04"

Name:
CfO_PhyIOConfigCh04
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh05"

Name:
CfO_PhyIOConfigCh05
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_BWQuitTimeSelChannel7_0"

Name:
CfO_BWQuitTimeSelChannel7_0
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_CounterCycleSelect"

Name:
CfO_CounterCycleSelect
Data type Value Information
USINT 2 Only default in the bus controller module

Constant register "CfO_CounterMode"

Name:
CfO_CounterMode
Data type Value Information
USINT 3 Only default in the bus controller module

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4.11.9.8.4 Encoder - Communication

4.11.9.8.4.1 Counter for verifying the data frame

Name:
SDCLifeCount
The 8-bit counter register is needed for the SDC software package. It is incremented with the system clock to allow
the SDC to check the validity of the data frame.
Data type Value
SINT -128 to 127

4.11.9.8.4.2 Display of the counter state

Name:
Encoder01
The counter state of the incremental encoder is displayed as a 16 or 32-bit counter value. Only the 16-bit value
is available in the bus controller function model.
Data type Value
INT -32768 to 32767
DINT1) -2.147.483.648 bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.9.8.4.3 Net time of the last valid counter value

Name:
Encoder01TimeValid
The net time of the last valid counter value is the time of the last valid counter value recorded on the module. The
user is able to determine the validity of the counter value by evaluating its age in the program. This means that the
module and error status bits do not have to be checked additionally to determine the validity of the value.
The net time of the last valid counter value that was read is displayed as a 16 or 32-bit value. Only the 16-bit value
is available in the bus controller function model.
Data type Value Information
INT -32768 to 32767 NetTime in µsec.
DINT1) -2.147.483.648
bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.9.8.4.4 Net time of the last counter value change

Name:
Encoder01TimeChanged
For slow X2X Link cycles, the net time of the last counter value change can be used to more accurately determine
the speed.
The net time of the last counter value change is displayed as 16 or 32-bit value. Only the 16-bit value is available
in the bus controller function model.
Data type Value Information
INT -32768 to 32767 NetTime in µsec.
DINT1) -2.147.483.648
bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.9.8.4.5 Counter value at the time of the last latch

Name:
Encoder01Latch
The counter value at the time of the last latch is displayed as a 16 or 32-bit value. Only the 16-bit value is available
in the bus controller function model.
Data type Value
INT -32768 to 32767
DINT1) -2.147.483.648 bis 2.147.483.647

1) Can only be configured in the standard function model

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4.11.9.8.4.6 Counter value of latch event

Name:
Encoder01LatchCount
The latch events are counted and stored in a cyclic 8-bit counter. This counter is incremented with each latch event,
thereby indicating a new occurrence. The new latched counter value is stored in the respective latch register.
Data type Value
SINT -128 to 127

4.11.9.8.4.7 Encoder commands

Name:
Encoder01Command
This register can be used to
1 reset the counter value. The counter is kept at zero until this command is reset.
2 enable the latch procedure. If the latch configuration is valid and matches the hardware signals, then this
activation causes the counter value to be saved in the latch register.
The two different latch configurations that are possible (see section 4.11.9.8.3.3 "Setting the latch mode") must
be handled as follows:
• Single shot latch mode:
After successful latching, indicated by the latch event counter, activation must be reset before any more
latching is possible. The activation must be set again if additional latching is needed.
• Continuous latch mode:
The latch function only has to be enabled/set as long as latching is desired. The latch event counter is
incremented with each event.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Encoder01Reset 0 Do not reset
1 Set encoder value to 0
1 Encoder01LatchEnable 0 Do not activate latch
1 Latching
2-7 Reserved 0

4.11.9.8.4.8 Input status of signal lines

Name:
Encoder01_A
Encoder01_B
Encoder01_R
DigitalInput01 to DigitalInput02
This register displays the input status of the signal lines from the encoder and the digital inputs.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Encoder01_A 0/1 Input state of encoder signal A
1 Encoder01_B 0/1 Input state of encoder signal B
2 Encoder01_R 0/1 Input state of encoder signal R
3 Reserved 0
4 DigitalInput01 0/1 Input state - Digital input 1
5 DigitalInput02 0/1 Input state - Digital input 2
6-7 Reserved 0

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4.11.9.8.4.9 Error status of signal lines

The error states are latched when they occur and are maintained until acknowledged. The counter and time reg-
isters are not updated if there are pending or unacknowledged errors.

Status of signal lines

Name:
BW_Channel_A
BW_Channel_B
BW_Channel_R
This register displays the error states of the signal lines from the encoder. The error states are latched when they
occur and are maintained until acknowledged. The counter and time registers are not updated if there are pending
or unacknowledged errors.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 BW_Channel_A 0 No error in encoder signal A
1 Open line, short circuit or voltage level too low
1 BW_Channel_B 0 No error in encoder signal B
1 Open line, short circuit or voltage level too low
2 BW_Channel_R 0 No error in encoder signal R
1 Open line, short circuit or voltage level too low
3-7 Reserved 0

Acknowledging error status of signal lines

Name:
BW_QuitChannel_A
BW_QuitChannel_B
BW_QuitChannel_R
This register can be used to acknowledge the latched error states of the signal lines from the encoder. However,
if there are still pending errors remaining, then the error status remains active. After acknowledging the errors, the
bits must also be reset or else any repetition of the error would be undetected.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 BW_QuitChannel_A 0 No acknowledgment
1 Acknowledgment of error status - Encoder signal A
1 BW_QuitChannel_B 0 No acknowledgment
1 Acknowledgment of error status - Encoder signal B
2 BW_QuitChannel_R 0 No acknowledgment
1 Acknowledgment of error status - Encoder signal R
3-7 Reserved 0

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Manual acknowledgment of latched error states

The latched error states of the signal lines from the encoder can be acknowledged manually. However, if there
are still pending errors remaining, then the error status remains active. After successfully acknowledging the errors
(latched error status = 0), the acknowledge bits must still be reset by the user or else a re-occurrence of an error
could be overlooked by the user.
Example 1: Cause of error corrected before being acknowledged
An error has occurred on a signal line. The error state is detected and latched by the module.
The error is acknowledged by the user after the cause of error has been corrected. The latched
error status changes to zero.
The manual acknowledge must now be reset so that any new errors will be recognized by the
user.

Error on signal line

Latched error state

Manual acknowledgment

Latched error state = 0

⇒ Reset manual acknowledgment

Figure 277: Cause of error corrected before being acknowledged

Example 2: Cause of error not yet corrected before being acknowledged

An error has occurred on a signal line. The error state is detected and latched by the module.
The error is acknowledged by the user before the cause of error has been corrected. The latched
error status remains set because the error is still remaining.
Acknowledgment is only successful after the cause of error has been corrected. The latched
error status changes to zero. The manual acknowledge must now be reset so that any new errors
will be recognized by the user.

Error on signal line

Latched error state

Manual acknowledgment

Latched error state = 0

⇒ Reset manual acknowledgment

Figure 278: Cause of error not yet corrected before being acknowledged

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Automatic acknowledgment of latched error states

In addition to manual acknowledgment, automatic acknowledgment of the latched error states after a specified
amount of time can also be enabled. Make sure that the time is set long enough for the higher-level system to
reliably detect the status messages and for the validity of the counter value to be determined using its age.
If the time specification = 0, then only manual acknowledgment is possible.
Example 1: An error has occurred on a signal line. The error state is detected and latched by the module. The
time for automatic acknowledgment starts counting after the cause of error has been corrected.
The error is acknowledged as soon as the time expires. The latched error status changes to zero.

Error on signal line

Latched error state

Automatic acknowledgment

Time Time
start expired

Figure 279: Latched error state acknowledged automatically

Example 2: Automatic and manual acknowledge used

An error has occurred on a signal line. The error state is detected and latched by the module. The
time for automatic acknowledgment starts counting after the cause of error has been corrected.
The error is acknowledged manually by the user before the time expires. The latched error status
changes to zero. The manual acknowledge must now be reset so that any new errors will be
recognized by the user.

Error on signal line

Latched error state

Automatic acknowledgment

Time Time
start expired here

Manual acknowledgment

After successful error evaluation,

the error is manually acknowledged by the user

Figure 280: Automatic and manual acknowledge used

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4.11.9.8.4.10 Status of encoder supply

Name:
PowerSupply01
This register shows the status of the integrated encoder supply. A faulty encoder power supply is displayed as
a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 PowerSupply01 0 24 VDC encoder power supply OK
1 24 VDC encoder power supply faulty
1-7 Reserved -

4.11.9.8.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without causing a communication error
or impaired functionality. It should be noted that very fast cycles decrease the idle time available for handling
monitoring, diagnostics and acyclic commands.
Minimum cycle time
150 µs

4.11.9.8.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
150 µs

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4.11.10 X20DC1396

4.11.10.1 General information

The module is equipped with 1 input for an ABR incremental encoder with 24 V encoder signal.
• 1 ABR incremental encoder 24 V
• 1 additional input e.g. for home enable switch
• 24 VDC and GND for encoder supply

4.11.10.2 Order data

Model number Short description Figure

Counter functions
X20DC1396 X20 digital counter module, 1 ABR incremental encoders, 24 V,
100 kHz input frequency, 4x evaluation
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 239: X20DC1396 - Order data

4.11.10.3 Technical data

Product ID X20DC1396
Brief description
I/O module 1 ABR incremental encoder 24 V
General information
Input voltage 24 VDC -15% / +20%
B&R ID code 0x1BAC
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.4 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Encoder - Bus Yes
Reference enable switch - Bus Yes
Reference enable switch - Encoder No
Type of signal lines Shielded cables must be used for all signal lines.
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Home enable switch
Quantity 1
Nominal voltage 24 VDC
Input filter
Hardware ≥2 µs
Software -
Connection type 3-wire connections
Input circuit Sink
Input current at 24 VDC Approx. 3.3 mA
Input resistance 7.19 kΩ

Table 240: X20DC1396 - Technical data

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Product ID X20DC1396
Isolation voltage between home enable switch and 500 Veff
bus
Switching threshold
Low <5 VDC
High >15 VDC
ABR incremental encoder
Encoder inputs 24 V, asymmetrical
Counter size 16/32-bit
Input frequency Max. 100 kHz
Evaluation 4x
Encoder supply Module-internal, max. 600 mA
Input filter
Hardware ≥2 µs
Software -
Input current at 24 VDC Approx. 1.3 mA
Input resistance 18.4 kΩ
Switching threshold
Low <5 VDC
High >15 VDC
Overload behavior of the encoder supply Short circuit protection, overload protection
Isolation voltage between encoder and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 240: X20DC1396 - Technical data

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4.11.10.4 LED status indicators

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
A1 Green Input state of counter input A
B1 Green Input state of counter input B
R1 Green Input state of reference pulse R
1 Green Input state - Digital input

1) Depending on the configuration, a firmware update can take up to several minutes.

4.11.10.5 Pinout

Shielded cables must be used for all signal lines.

r e
X20 DC 1396
A1
B1
R1
1

DI 1

Encoder 24 V +

GND

4.11.10.6 Connection example

DC

A
Counter 1

+24 VDC +24 VDC

GND GND

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4.11.10.7 Input circuit diagram

Counter inputs

ABR

VDR
Input status

I/O status

24 V
PTC
Encoder 24 V LED (green)

GND

GND

Standard input

Input x

VDR
Input status

I/O status

Led (green)

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4.11.10.8 Register description

4.11.10.8.1 Function model 0 - Standard and

Function model 1 - Standard with 32-bit encoder counter value

The difference between function model 0 and function model 1 is the size of the data type for some registers.
• Function model 0 uses data type INT
• Function model 1 uses data type DINT (specified in parentheses)
Register Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
Configuration
4104 CfO_EdgeDetectFalling USINT ●
4106 CfO_EdgeDetectRising USINT ●
2064 CfO_PresetABR01_1(_32Bit) (D)INT ●
2068 CfO_PresetABR01_2(_32Bit) (D)INT ●
512 ConfigOutput24 UINT ●
522 ConfigOutput26 USINT ●
520 ConfigOutput27 USINT ●
Communication
2116 ReferenceModeEncoder01 USINT ●
2080 Encoder01 (D)INT ●
264 Input state of the digital input USINT ●
DigitalInput01 Bit 3
2118 StatusInput01 USINT ●
40 Status of encoder supply USINT ●
PowerSupply01 Bit 0

4.11.10.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Configuration
4104 - CfO_EdgeDetectFalling USINT ●
4106 - CfO_EdgeDetectRising USINT ●
2064 - CfO_PresetABR01_1 INT ●
2068 - CfO_PresetABR01_2 INT ●
512 - ConfigOutput24 UINT ●
522 - ConfigOutput26 USINT ●
520 - ConfigOutput27 USINT ●
Communication
2116 0 ReferenceModeEncoder01 USINT ●
2080 0 Encoder01 INT ●
264 2 Input state of the digital input USINT ●
DigitalInput01 Bit 3
2118 4 StatusInput01 USINT ●
40 3 Status of encoder supply USINT ●
PowerSupply01 Bit 0

1) The offset specifies the position of the register within the CAN object.

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4.11.10.8.3 ABR encoder - Configuration registers

4.11.10.8.3.1 Reference pulse

The following registers must be configured by a single acyclic write with the listed values so that the homing
procedure is completed on the edge of the reference pulse.
The homing procedure can take place on:
• Rising edge
• Falling edge (default configuration)

Constant register "CfO_EdgeDetectFalling"

Name:
CfO_EdgeDetectFalling
Data type Value Filter
USINT 0x00 Configuration value for rising edge
0x04 Configuration value for falling edge

Constant register "CfO_EdgeDetectRising"

Name:
CfO_EdgeDetectRising
Data type Value Filter
USINT 0x04 Configuration value for rising edge
0x00 Configuration value for falling edge

Constant register "ConfigOutput24"

Name:
ConfigOutput24
This register contains the value for ABR encoder 1.
Data type Value Filter
UINT 0x1012 Configuration value for rising edge
0x1002 Configuration value for falling edge

4.11.10.8.3.2 Setting the home position

Name:
Cfo_PresetABR01_1 to Cfo_PresetABR01_2
CfO_PresetABR01_1_32Bit to CfO_PresetABR01_2_32Bit (only in function model 1)
It is possible to specify two home positions with these registers through a one-off acyclic write, for example (default
= 0). The configured values are applied to the counter values after a completed homing procedure.
Data type Value
INT -32,768 to 32,767
DINT1) -2,147,483,648 to 2,147,483,647

1) Only in function model 1

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4.11.10.8.3.3 Homing with reference enable input

Regardless of the referencing mode, it is possible using this register to prevent the home position from being
applied when the corresponding reference input voltage level occurs (see 4.11.10.8.4.2 "Input state of the digital
input": bit 3). The desired setting can be configured by a one-off acyclic write.

Voltage level for reference enable activation

Name:
ConfigOutput26
This register is used to configure the active voltage level of the digital input for the reference enable.
Data type Value Filter
USINT 0x00 Reference enable is active at 0 VDC
0x08 Reference enable is active at 24 VDC

Reference enable of the input

Name:
ConfigOutput27
This register can be used to define whether the reference enable is activated.
Data type Value Filter
USINT 0x00 Reference enable input OFF (default)
0x08 Reference enable input activated

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4.11.10.8.4 ABR encoder - Configuration registers

4.11.10.8.4.1 Counter state of the encoder

Name:
Encoder01
The encoder values are represented as 16-bit or 32-bit counter values in this register.
Data type Value
INT -32,768 to 32,767
DINT1) -2,147,483,648 to 2,147,483,647

1) Only in function model 1

4.11.10.8.4.2 Input state of the digital input

Name:
DigitalInput01
This register displays the input status of the encoder and the digital input.
Data type Value
USINT See bit structure.

Bit Name Value Information

0 Encoder A 0 or 1 Input state
1 Encoder B 0 or 1 Input state
2 Encoder A + B 0 or 1 Input state of reference pulse
3 DigitalInput01 0 or 1 Input state - Digital input 1
4-7 Reserved -

4.11.10.8.4.3 Reading the referencing mode

Name:
ReferenceModeEncoder01
This register determines the referencing mode.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-1 00 Referencing OFF
01 Single shot referencing
11 Continuous referencing
2-5 0 Bits permanently set = 0
6-7 00 Referencing OFF
11 Bits permanently set = 1

This results in the following values:

Binary Hex Function
00000000 0x00 Referencing OFF
11000001 0xC1 Single shot referencing
For a new start after the completed homing procedure:
• Write value 0x00
• Wait until bit 0 to bit 3 of the StatusInput01 register takes on the value 0. Counter
bits 4 to 7 are not erased
• Switch homing procedure on again
11000011 0xC3 Continuous referencing
Referencing occurs at every reference pulse.
It is important to know how the optional reference enable is configured. See section 4.11.10.8.3.3 "Homing with
reference enable input"

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4.11.10.8.4.4 Status of the homing procedure

Name:
StatusInput01
This register contains information regarding whether the referencing process is off, active or complete.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Reference pulse without homing1) 0 No reference impulse without homing has occurred yet
1 At least a reference impulse without homing has occurred
1 State change 0 or 1 Changes with each reference pulse without homing
2 Reference pulse with homing1) 0 No homing has occurred yet
1 At least one homing procedure has occurred
3 State change 0 or 1 Changes with each homing procedure that has taken place
4 Reference pulse 0 The last reference pulse didn't bring about a homing procedure
1 The last reference pulse brought about a homing procedure
5-7 Counter x Free-running counter, increased with each reference pulse

1) Always 1 after the first reference pulse that has occurred

Examples of possible values:

Binary Hex Function
0x00000000 0x00 Referencing OFF or homing procedure already active
0x00111100 0x3CE First homing procedure complete Reference value applied in the Encoder01 register
0xxxx11100 0xxB Bits 5 to 7 are changed with each reference pulse
0xxxx1x100 0xxx Continuously changing the bits with the "Continuous referencing" setting. The refer-
ence value is applied to the Encoder01 register on each reference pulse.
It is important to know how the optional reference enable (see section 4.11.10.8.3.3 "Homing with reference enable
input" on page 753) is configured.

4.11.10.8.4.5 Status of encoder supply

Name:
PowerSupply01
This register shows the status of the integrated encoder supply. A faulty encoder power supply is displayed as
a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 PowerSupply01 0 24 VDC encoder power supply OK
1 24 VDC encoder power supply faulty
1-7 Reserved -

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4.11.10.8.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
128 μs

4.11.10.8.6 Maximum cycle time

The maximum cycle time defines how far the bus cycle can be increased without internal counter overflows causing
module malfunctions.
Minimum cycle time
16 ms

4.11.10.8.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
128 μs

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4.11.11 X20DC1398

4.11.11.1 General information

This module is equipped with one input for SSI absolute encoders with 24 V encoder signal.
• 1 SSI absolute encoder 24 V
• 1 additional input
• 24 VDC and GND for encoder supply

4.11.11.2 Order data

Model number Short description Figure

Counter functions
X20DC1398 X20 digital counter module, 1 SSI absolute encoder, 24 V, 125
kbit/s, 32-bit
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 241: X20DC1398 - Order data

4.11.11.3 Technical data

Product ID X20DC1398
Brief description
I/O module 1 SSI absolute encoder 24 V
General information
Input voltage 24 VDC -15% / +20%
B&R ID code 0x1BAE
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.3 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Encoder - Bus Yes
Channel - Bus Yes
Channel - Encoder No
Type of signal lines Shielded cables must be used for all signal lines.
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Quantity 1
Nominal voltage 24 VDC
Input current at 24 VDC Approx. 3.3 mA
Input filter
Hardware ≥2 µs
Software -
Connection type 3-wire connections
Input circuit Sink
Input resistance 7.19 kΩ

Table 242: X20DC1398 - Technical data

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Product ID X20DC1398
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
SSI absolute encoder
Encoder inputs 24 V, asymmetrical
Counter size 32-bit
Max. transfer rate 125 kbit/s
Encoder supply Module-internal, max. 600 mA
Keying Gray/Binary
CLK: Output current Max. 100 mA
DATA: Input resistance 18.4 kΩ
Isolation voltage between encoder and bus 500 Veff
Overload behavior of the encoder supply Short circuit protection, overload protection
Switching threshold
Low <5 VDC
High >15 VDC
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 242: X20DC1398 - Technical data

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4.11.11.4 LED status indicators

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
D1 Green Input status - Data signal
1 Green Input state - Digital input

1) Depending on the configuration, a firmware update can take up to several minutes.

4.11.11.5 Pinout

Shielded cables must be used for all signal lines.

r e

X20 DC 1398
D1
1

Data

Clock

DI 1

Encoder 24 V +

GND

4.11.11.6 Connection example

DC

Data
Counter 1

Clock

+24 VDC +24 VDC

GND GND

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4.11.11.7 Input circuit diagram

Counter input

Data

VDR
Input status

I/O status

24 V
PTC
Encoder 24 V LED (green)

GND

GND

Standard input

Input x

VDR
Input status

I/O status

Led (green)

4.11.11.8 Output circuit diagram

24 V

Output status Push

PTC
Clock

VDR
Output status Pull

GND

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4.11.11.9 Register description

4.11.11.9.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Configuration
7176 ConfigOutput14 UINT ●
7172 ConfigAdvanced UDINT ●
Communication
7184 Encoder01 UDINT ●
264 Input state of the digital input 1 USINT ●
DigitalInput01 Bit 3
40 Status of encoder supply USINT ●
PowerSupply01 Bit 0

4.11.11.9.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Configuration
7176 - ConfigOutput14 UINT ●
7172 - ConfigAdvanced UDINT ●
Communication
7184 0 Encoder01 UDINT ●
264 4 Input state of the digital input 1 USINT ●
DigitalInput01 Bit 3
40 5 Status of encoder supply USINT ●
PowerSupply01 Bit 0

1) The offset specifies the position of the register within the CAN object.

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4.11.11.9.3 SSI encoder configuration register

4.11.11.9.3.1 Standard configuration

Name:
ConfigOutput14
This configuration register is used to set the coding, the clock rate and the number of bits. Default = 0. This must
be set once using an acyclic write command.
Data type Value
UINT See bit structure.

Bit structure:
Bit Name Value Information
0-5 SSI value valid bits x
6-7 Clock rate 11 125 kHz
8 - 13 SSI number of bits Number of bits including leading zeros
14 Reserved 0
15 Keying 0 Binary coding
1 Gray coding

4.11.11.9.3.2 Extended configuration

Name:
ConfigAdvanced
This configuration register is used to set the coding, the clock rate, the number of bits and the monostable multivi-
brator settings. Default = 0. This must be set once using an acyclic write command.
It only differs from ConfigOutput14 by data length and additional monostable multivibrator testing.
Data type Value
UDINT See bit structure.

Bit structure:
Bit Name Value Information
0-5 SSI value valid bits x
6-7 Clock rate 11 125 kHz
8 - 13 SSI number of bits x Number of bits including leading zeros
14 Reserved 0
15 Keying 0 Binary coding
1 Gray coding
16 - 17 Monostable multivibrator check 00 Check OFF, no additional clock bit
01 Check set to High level
10 Check set to Low level
11 Level is clocked but ignored
18 - 31 Reserved 0

Transfer to synchronous serial interface

1 2 3 4

Clock

Data Bit n Bit n - 1 Bit n - 3 Bit 1 Bit 0

Measurement value processing

1 Starting bit ... Stores the measurement value
2 Output of first data bit
3 All data bits are transferred, monostable multivibrator time starts counting down.
4 Monostable multivibrator returns to its initial state. A new transfer can be started.

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4.11.11.9.4 SSI encoder - Configuration registers

4.11.11.9.4.1 SSI position values

Name:
Encoder01
The SSI encoder value is displayed as a 32-bit position value. The SSI position value is generated synchronously
with the X2X cycle.
Data type Value Filter
UDINT 0 to 4,294,967,295 SSI position

4.11.11.9.4.2 Input state of the digital input 1

Name:
DigitalInput01
This register displays the input state of the digital input.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
3 DigitalInput01 0 or 1 Input state - Digital input 1

4.11.11.9.4.3 Status of encoder supply

Name:
PowerSupply01
This register shows the status of the integrated encoder supply. A faulty encoder power supply is displayed as
a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 PowerSupply01 0 24 VDC encoder power supply OK
1 24 VDC encoder power supply faulty
1-7 Reserved -

4.11.11.9.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
128 μs

4.11.11.9.6 Maximum cycle time

The maximum cycle time defines how far the bus cycle can be increased without internal counter overflows causing
module malfunctions.
Minimum cycle time
16 ms

4.11.11.9.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
128 μs

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4.11.12 X20DC1976

4.11.12.1 General information

The module is equipped with 1 input for an ABR incremental encoder with 5 V encoder signal. The encoder inputs
are monitored (A, B, R).
• 1 ABR incremental encoder 5 V, asymmetric
• Encoder input monitoring
• 2 additional inputs, e.g. for latch input
• 5 VDC, 24 VDC and GND for encoder supply

4.11.12.2 Order data

Model number Short description Figure

Counter functions
X20DC1976 X20 digital counter module, 1x ABR incremental encoder, 5 V
(single ended), 250 kHz input frequency, 4x evaluation, encoder
monitoring, NetTime module
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 243: X20DC1976 - Order data

4.11.12.3 Technical data

Product ID X20DC1976
Brief description
I/O module 1 ABR incremental encoder 5 V
General information
B&R ID code 0xA707
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.2 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Type of signal lines Shielded cables must be used for all signal lines
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Quantity 2
Nominal voltage 24 VDC
Input voltage 24 VDC (-15% / +20%)
Input current at 24 VDC Approx. 3.3 mA
Input filter
Hardware <2 µs
Software -
Connection type 3-wire connections
Input circuit Sink
Additional functions Latch input
Input resistance 7.03 kΩ

Table 244: X20DC1976 - Technical data

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Product ID X20DC1976
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
ABR incremental encoder
Encoder inputs 5 V, asymmetrical (single-ended)
Counter size 16/32-bit
Input frequency Max. 250 kHz
Evaluation 4x
Encoder supply
5 VDC ±5%, module-internal, max. 300 mA
24 VDC Module-internal, max. 300 mA
Input filter
Hardware ≤600 ns
Software -
Common-mode range -10 V ≤ VCM ≤ +13.2 V
Overload behavior of the encoder supply Short circuit protection, overload protection
Isolation voltage between encoder and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 244: X20DC1976 - Technical data

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4.11.12.4 LED status indicators

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Single flash The encoder monitor has detected a line fault on the encoder inputs. The status
bits must be evaluated in order to provide a more detailed definition of this error.
The following error states are detected:
• Open line
• Short-circuit or voltage level too low
On Error or reset status
A1 Green Input state of counter input A
B1 Green Input state of counter input B
R1 Green Input state of reference pulse R
1-2 Green Input state of the corresponding digital input

1) Depending on the configuration, a firmware update can take up to several minutes.

4.11.12.5 Pinout

Shielded cables must be used for all signal lines.

r e
X20 DC 1976

A1
B1
R1
1 2

DI 1 DI 2

Encoder 24 V+ Encoder 5 V+

GND GND

4.11.12.6 Connection example

DC

A
Counter 1

R
Sensor 1

+24 VDC +24 VDC

GND GND

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4.11.12.7 Input circuit diagram

Counter inputs

ABR

VDR Input status

Recipient
with monitoring

I/O status

LED (green)

24 V
PTC
Encoder 24 V

24 V
DC
Encoder 5 V
DC

GND

GND

Standard inputs

Input x

VDR
Input status

I/O status

Led (green)

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4.11.12.8 Register description

4.11.12.8.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Encoder - Communication
683 SDCLifeCount SINT ●
6342 Encoder01 INT ●
6340 DINT
6310 Encoder01TimeValid INT ●
6308 DINT
6358 Encoder01Latch INT ●
6356 DINT
6153 Encoder commands USINT ●
Encoder01Reset Bit 0
Encoder01LatchEnable Bit 1
927 Input status of signal lines USINT ●
Encoder01_A Bit 0
Encoder01_B Bit 1
Encoder01_R Bit 2
DigitalInput01 Bit 4
DigitalInput02 Bit 5
847 Status of signal lines USINT ●
BW_Channel_A Bit 0
BW_Channel_B Bit 1
BW_Channel_R Bit 2
811 Acknowledging error status of signal lines USINT ●
BW_QuitChannel_A Bit 0
BW_QuitChannel_B Bit 1
BW_QuitChannel_R Bit 2
6326 Encoder01TimeChanged INT ●
6324 DINT
6303 Encoder01LatchCount SINT ●
843 Status of encoder supplies USINT ●
PowerSupply01 Bit 0
PowerSupply02 Bit 1
Encoder - Configuration
513 CfO_SIframeGenID USINT ●
642 CfO_SystemCycleTime UINT ●
769 CfO_PhyIOConfigCh01 USINT ●
771 CfO_PhyIOConfigCh02 USINT ●
773 CfO_PhyIOConfigCh03 USINT ●
777 CfO_PhyIOConfigCh04 USINT ●
779 CfO_PhyIOConfigCh05 USINT ●
815 CfO_BWQuitTimeSelChannel7_0 USINT ●
820 CfO_BWQuitTime_0 UDINT ●
6145 CfO_CounterCycleSelect USINT ●
6147 CfO_CounterMode USINT ●
6149 CfO_LatchMode USINT ●
6151 CfO_LatchComparator USINT ●
6159 CfO_BWCNTEnableMaskChannel7_0 USINT ●

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4.11.12.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Encoder - Communication
6342 0 Encoder01 INT ●
6310 2 Encoder01TimeValid INT ●
6358 4 Encoder01Latch INT ●
6153 1 Encoder commands USINT ●
Encoder01Reset Bit 0
Encoder01LatchEnable Bit 1
927 7 Input status of signal lines USINT ●
Encoder01_A Bit 0
Encoder01_B Bit 1
Encoder01_R Bit 2
DigitalInput01 Bit 4
DigitalInput02 Bit 5
847 6 Status of signal lines USINT ●
BW_Channel_A Bit 0
BW_Channel_B Bit 1
BW_Channel_R Bit 2
811 0 Acknowledging error status of signal lines USINT ●
BW_QuitChannel_A Bit 0
BW_QuitChannel_B Bit 1
BW_QuitChannel_R Bit 2
6326 - Encoder01TimeChanged INT ●
6303 - Encoder01LatchCount SINT ●
843 - Status of encoder supplies USINT ●
PowerSupply01 Bit 0
PowerSupply02 Bit 1
Encoder - Configuration
513 - CfO_SIframeGenID USINT ●
642 - CfO_SystemCycleTime UINT ●
769 - CfO_PhyIOConfigCh01 USINT ●
771 - CfO_PhyIOConfigCh02 USINT ●
773 - CfO_PhyIOConfigCh03 USINT ●
777 - CfO_PhyIOConfigCh04 USINT ●
779 - CfO_PhyIOConfigCh05 USINT ●
815 - CfO_BWQuitTimeSelChannel7_0 USINT ●
820 - CfO_BWQuitTime_0 UDINT ●
6145 - CfO_CounterCycleSelect USINT ●
6147 - CfO_CounterMode USINT ●
6149 - CfO_LatchMode USINT ●
6151 - CfO_LatchComparator USINT ●
6159 - CfO_BWCNTEnableMaskChannel7_0 USINT ●

1) The offset specifies the position of the register within the CAN object.

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4.11.12.8.3 Encoder - Configuration

The following registers are used for setting functions and configuring the module.

4.11.12.8.3.1 Enabling error monitoring for the signal lines

Name:
CfO_BWCNTEnableMaskChannel7_0
This register requires individually enabling error monitoring for each of the signal channels. "Open line", "short
circuit" and "voltage level too low" are reported as error states. Any errors that occur are reported in the error status
registers BW_Channel_x.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Enable error monitoring for signal A lines 0 Error monitoring - Encoder Signal A disabled
1 Error monitoring - Encoder Signal A enabled - Only default in
bus controller function model
1 Enable error monitoring for signal B lines 0 Error monitoring - Encoder Signal B disabled
1 Error monitoring - Encoder Signal B enabled - Only default in
bus controller function model
2 Enable error monitoring for signal R lines 0 Error monitoring - Encoder Signal R disabled
1 Error monitoring - Encoder Signal R enabled - Only default in
bus controller function model
3-7 Reserved 0

4.11.12.8.3.2 Timing for automatic error acknowledgment

Name:
CfO_BWQuitTime_0
This register can be used to enable an additional automatic acknowledgment of the error status through timing.
If a valid time is set, then the acknowledgment can still be made manually, the only difference is that automatic
acknowledgment will take place on the module after the defined amount of time has passed. If the error state has
not yet been corrected, then the error status remains and the time is reset. Make sure that the time is set long
enough for the higher-level system to reliably detect the status messages.
If the timing = 0, then acknowledgment is only possible using the cyclic acknowledgment registers.
Data type Value Information
UDINT 0 No automatic acknowledgment - Only default in bus controller function model
1 to 2.147.483.647 Time for automatic acknowledgment [μs]

4.11.12.8.3.3 Setting the latch mode

Name:
CfO_LatchMode
This register is used to set the latch mode:
• Single shot latch mode:
The latch function must be enabled/set. After a successful latch procedure, the activation must be reset in
order for a new latch procedure to be activated.
• Continuous latch mode:
The latch function only has to be enabled/set as long as latching is desired.
A changed counter state on Encoder01LatchCount indicates that the latch procedure has been performed. The
counter value is stored in the latch register Encoder01Latch.
Data type Value Information
USINT 0 Single shot latch procedure
1 Continuous latch procedure

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4.11.12.8.3.4 Signal channels for triggering latch procedure

Name:
CfO_LatchComparator
This register defines the signal channels and their level for triggering the latch procedure.
• This mainly configures which channels are linked to generate the latch event. All three signals from the
encoder and digital input 1 can be used for the "AND" operation.
• The "active voltage level" needed for the latch procedure can now be used according to the physical signals.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Defines signal level for encoder signal A 0 Low
1 High
1 Defines signal level for encoder signal B 0 Low
1 High
2 Defines signal level for encoder signal R 0 Low
1 High
3 Defines signal level for digital input 1 0 Low
1 High
4 Use encoder signal A to trigger latch procedure 0 Disabled
1 Latch function linked to encoder signal A
5 Use encoder signal B to trigger latch procedure 0 Disabled
1 Latch function linked to encoder signal B
6 Use encoder signal R to trigger latch procedure 0 Disabled
1 Latch function linked to encoder signal R
7 Use digital input 1 to trigger latch procedure 0 Disabled
1 Latch function linked to digital input 1

4.11.12.8.3.5 Physical configuration

The following registers must be set to the specified constant value for correct physical configuration:

Constant register "CfO_SIframeGenID"

Name:
CfO_SIframeGenID
Data type Value Information
USINT 9 Only default in the bus controller module

Constant register "CfO_SystemCycleTime"

Name:
CfO_SystemCycleTime
Data type Value Information
UINT 800 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh01"

Name:
CfO_PhyIOConfigCh01
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh02"

Name:
CfO_PhyIOConfigCh02
Data type Value Information
USINT 0 Only default in the bus controller module

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Constant register "CfO_PhyIOConfigCh03"

Name:
CfO_PhyIOConfigCh03
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh04"

Name:
CfO_PhyIOConfigCh04
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_PhyIOConfigCh05"

Name:
CfO_PhyIOConfigCh05
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_BWQuitTimeSelChannel7_0"

Name:
CfO_BWQuitTimeSelChannel7_0
Data type Value Information
USINT 0 Only default in the bus controller module

Constant register "CfO_CounterCycleSelect"

Name:
CfO_CounterCycleSelect
Data type Value Information
USINT 2 Only default in the bus controller module

Constant register "CfO_CounterMode"

Name:
CfO_CounterMode
Data type Value Information
USINT 3 Only default in the bus controller module

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4.11.12.8.4 Encoder - Communication

4.11.12.8.4.1 Counter for verifying the data frame

Name:
SDCLifeCount
The 8-bit counter register is needed for the SDC software package. It is incremented with the system clock to allow
the SDC to check the validity of the data frame.
Data type Value
SINT -128 to 127

4.11.12.8.4.2 Display of the counter state

Name:
Encoder01
The counter state of the incremental encoder is displayed as a 16 or 32-bit counter value. Only the 16-bit value
is available in the bus controller function model.
Data type Value
INT -32768 to 32767
DINT1) -2.147.483.648 bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.12.8.4.3 Net time of the last valid counter value

Name:
Encoder01TimeValid
The net time of the last valid counter value is the time of the last valid counter value recorded on the module. The
user is able to determine the validity of the counter value by evaluating its age in the program. This means that the
module and error status bits do not have to be checked additionally to determine the validity of the value.
The net time of the last valid counter value that was read is displayed as a 16 or 32-bit value. Only the 16-bit value
is available in the bus controller function model.
Data type Value Information
INT -32768 to 32767 NetTime in µsec.
DINT1) -2.147.483.648
bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.12.8.4.4 Net time of the last counter value change

Name:
Encoder01TimeChanged
For slow X2X Link cycles, the net time of the last counter value change can be used to more accurately determine
the speed.
The net time of the last counter value change is displayed as 16 or 32-bit value. Only the 16-bit value is available
in the bus controller function model.
Data type Value Information
INT -32768 to 32767 NetTime in µsec.
DINT1) -2.147.483.648
bis 2.147.483.647

1) Can only be configured in the standard function model

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4.11.12.8.4.5 Counter value at the time of the last latch

Name:
Encoder01Latch
The counter value at the time of the last latch is displayed as a 16 or 32-bit value. Only the 16-bit value is available
in the bus controller function model.
Data type Value
INT -32768 to 32767
DINT1) -2.147.483.648 bis 2.147.483.647

1) Can only be configured in the standard function model

4.11.12.8.4.6 Counter value of latch event

Name:
Encoder01LatchCount
The latch events are counted and stored in a cyclic 8-bit counter. This counter is incremented with each latch event,
thereby indicating a new occurrence. The new latched counter value is stored in the respective latch register.
Data type Value
SINT -128 to 127

4.11.12.8.4.7 Encoder commands

Name:
Encoder01Command
This register can be used to
1 reset the counter value. The counter is kept at zero until this command is reset.
2 enable the latch procedure. If the latch configuration is valid and matches the hardware signals, then this
activation causes the counter value to be saved in the latch register.
The two different latch configurations that are possible (see section 4.11.12.8.3.3 "Setting the latch mode") must
be handled as follows:
• Single shot latch mode:
After successful latching, indicated by the latch event counter, activation must be reset before any more
latching is possible. The activation must be set again if additional latching is needed.
• Continuous latch mode:
The latch function only has to be enabled/set as long as latching is desired. The latch event counter is
incremented with each event.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Encoder01Reset 0 Do not reset
1 Set encoder value to 0
1 Encoder01LatchEnable 0 Do not activate latch
1 Latching
2-7 Reserved 0

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4.11.12.8.4.8 Input status of signal lines

Name:
Encoder01_A
Encoder01_B
Encoder01_R
DigitalInput01 to DigitalInput02
This register displays the input status of the signal lines from the encoder and the digital inputs.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Encoder01_A 0/1 Input state of encoder signal A
1 Encoder01_B 0/1 Input state of encoder signal B
2 Encoder01_R 0/1 Input state of encoder signal R
3 Reserved 0
4 DigitalInput01 0/1 Input state - Digital input 1
5 DigitalInput02 0/1 Input state - Digital input 2
6-7 Reserved 0

4.11.12.8.4.9 Error status of signal lines

The error states are latched when they occur and are maintained until acknowledged. The counter and time reg-
isters are not updated if there are pending or unacknowledged errors.

Status of signal lines

Name:
BW_Channel_A
BW_Channel_B
BW_Channel_R
This register displays the error states of the signal lines from the encoder. The error states are latched when they
occur and are maintained until acknowledged. The counter and time registers are not updated if there are pending
or unacknowledged errors.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 BW_Channel_A 0 No error in encoder signal A
1 Open line, short circuit or voltage level too low
1 BW_Channel_B 0 No error in encoder signal B
1 Open line, short circuit or voltage level too low
2 BW_Channel_R 0 No error in encoder signal R
1 Open line, short circuit or voltage level too low
3-7 Reserved 0

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Acknowledging error status of signal lines

Name:
BW_QuitChannel_A
BW_QuitChannel_B
BW_QuitChannel_R
This register can be used to acknowledge the latched error states of the signal lines from the encoder. However,
if there are still pending errors remaining, then the error status remains active. After acknowledging the errors, the
bits must also be reset or else any repetition of the error would be undetected.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 BW_QuitChannel_A 0 No acknowledgment
1 Acknowledgment of error status - Encoder signal A
1 BW_QuitChannel_B 0 No acknowledgment
1 Acknowledgment of error status - Encoder signal B
2 BW_QuitChannel_R 0 No acknowledgment
1 Acknowledgment of error status - Encoder signal R
3-7 Reserved 0

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Manual acknowledgment of latched error states

The latched error states of the signal lines from the encoder can be acknowledged manually. However, if there
are still pending errors remaining, then the error status remains active. After successfully acknowledging the errors
(latched error status = 0), the acknowledge bits must still be reset by the user or else a re-occurrence of an error
could be overlooked by the user.
Example 1: Cause of error corrected before being acknowledged
An error has occurred on a signal line. The error state is detected and latched by the module.
The error is acknowledged by the user after the cause of error has been corrected. The latched
error status changes to zero.
The manual acknowledge must now be reset so that any new errors will be recognized by the
user.

Error on signal line

Latched error state

Manual acknowledgment

Latched error state = 0

⇒ Reset manual acknowledgment

Figure 281: Cause of error corrected before being acknowledged

Example 2: Cause of error not yet corrected before being acknowledged

An error has occurred on a signal line. The error state is detected and latched by the module.
The error is acknowledged by the user before the cause of error has been corrected. The latched
error status remains set because the error is still remaining.
Acknowledgment is only successful after the cause of error has been corrected. The latched
error status changes to zero. The manual acknowledge must now be reset so that any new errors
will be recognized by the user.

Error on signal line

Latched error state

Manual acknowledgment

Latched error state = 0

⇒ Reset manual acknowledgment

Figure 282: Cause of error not yet corrected before being acknowledged

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Automatic acknowledgment of latched error states

In addition to manual acknowledgment, automatic acknowledgment of the latched error states after a specified
amount of time can also be enabled. Make sure that the time is set long enough for the higher-level system to
reliably detect the status messages and for the validity of the counter value to be determined using its age.
If the time specification = 0, then only manual acknowledgment is possible.
Example 1: An error has occurred on a signal line. The error state is detected and latched by the module. The
time for automatic acknowledgment starts counting after the cause of error has been corrected.
The error is acknowledged as soon as the time expires. The latched error status changes to zero.

Error on signal line

Latched error state

Automatic acknowledgment

Time Time
start expired

Figure 283: Latched error state acknowledged automatically

Example 2: Automatic and manual acknowledge used

An error has occurred on a signal line. The error state is detected and latched by the module. The
time for automatic acknowledgment starts counting after the cause of error has been corrected.
The error is acknowledged manually by the user before the time expires. The latched error status
changes to zero. The manual acknowledge must now be reset so that any new errors will be
recognized by the user.

Error on signal line

Latched error state

Automatic acknowledgment

Time Time
start expired here

Manual acknowledgment

After successful error evaluation,

the error is manually acknowledged by the user

Figure 284: Automatic and manual acknowledge used

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4.11.12.8.4.10 Status of encoder supplies

Name:
PowerSupply01 to PowerSupply02
This register shows the status of the integrated encoder supplies. A faulty encoder power supply is displayed as
a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 PowerSupply01 0 24 VDC encoder power supply OK
1 24 VDC encoder power supply faulty
1 PowerSupply02 0 5 VDC encoder power supply OK
1 5 VDC encoder power supply faulty
2-7 Reserved -

4.11.12.8.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without causing a communication error
or impaired functionality. It should be noted that very fast cycles decrease the idle time available for handling
monitoring, diagnostics and acyclic commands.
Minimum cycle time
150 µs

4.11.12.8.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
150 µs

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4.11.13 X20DC2190

4.11.13.1 General information

This module can be used to determine paths and to calculate speeds at the same time. The ultrasonic transducer
rods are connected directly to the RS422 interface. Communication to the transducer rod takes place using start/
stop signals. With the DPI/IP protocol, it is also possible, for example, to read operational properties directly from
the transducer. During service (when a transducer is being exchanged) the machine can be started again quickly
without additional configuration work.
The module is designed for connecting two transducer rods with a total of up to four paths. That means, for example,
that two ultrasonic transducers with two magnets each or one with four magnets can be used. The combination
three/one is also possible. The module provides 24 VDC as an external supply for the sensor.
• Ultrasonic transducer module
• Path measurement (resolution 10 µm)
• Speed measurement (resolution 100 µm/s)
• 1, 2, 3 and 4 magnetic rod measurements possible
• DPI/IP protocol supported

4.11.13.2 Order data

Model number Short description Figure

Counter functions
X20DC2190 X20 digital counter module, ultrasonic transducer module, inter-
faces: EP start/stop, DPI/IP, 2 transducer rods, 4 path evaluation
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 245: X20DC2190 - Order data

4.11.13.3 Technical data

Product ID X20DC2190
Short description
I/O module Ultrasonic transducer module, 2 transducer rods, 4 position detection, speed measurement
General information
B&R ID code 0x2188
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.1 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
KC Yes
GOST-R Yes
Channels for path and speed measurements
Quantity 2
Supported encoder types Start/Stop interface
EP start/stop interface
DPI/IP interface

Table 246: X20DC2190 - Technical data

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Product ID X20DC2190
Encoder supply
Voltage 24 VDC, module-internal, max. 150 mA
Monitoring Configurable overvoltage/undervoltage monitoring (±10%, ±15%, ±20%, ±25%)
Short circuit protection Rev. D0 and higher
Input and output level RS422 differential level
Multi-magnet measurement Yes, in combination per rod, max. 4 magnets total
Outputs 1.6 µs durational initialization pulse
Inputs
Path measurement Resolution = 0.01mm, measurement range = ±5.2m
Speed measurement Resolution = 0.1 mm/s, measurement range = ±3.2 m/s
Accuracy ±50 ppm ±5 ppm/year
Short circuit protection No
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation 0 to 55°C
Vertical installation 0 to 50°C
Storage -25 to 70°C
Transport -25 to 70°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 246: X20DC2190 - Technical data

4.11.13.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash Reset mode
Double flash Boot mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
1-2 Yellow Off No transducer rod connected
On No transducer rod is connected to the respective measurement channel

Table 247: LED status indicators

1) Depending on the configuration, a firmware update can take up to several minutes.

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4.11.13.5 Pinout

r e

X20 DC 2190
1 2

Channel 1 Channel 2

Start + Start +

Start - Start -

Stop + Stop +

Stop - Stop -

+24 VDC +24 VDC

GND GND

Figure 285: Pinout

The ultrasonic transducers should be connected using a shielded cable. The shield of the encoder cable is con-
nected to the ground via the shield connection on the X20 bus module.

4.11.13.6 Connection example

DC
Ultrasonic
Transducer rod

Start +

Start -

Stop +

Stop -

+24 VDC

GND

+24 VDC +24 VDC

GND GND

Figure 286: Connection example

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4.11.13.7 Register description

4.11.13.7.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Synchronous register
0 Position01 DINT ●
4 Position02 DINT ●
8 Position03 DINT ●
12 Position04 DINT ●
16 Speed01 INT ●
18 Speed02 INT ●
20 Speed03 INT ●
22 Speed04 INT ●
24 ErrorStatus01 USINT ●
25 ErrorStatus02 USINT ●
26 ErrorStatus03 USINT ●
27 ErrorStatus04 USINT ●
28 StatusInput01 USINT ●
30 USSpeed01 UDINT ●
34 USSpeed02 UDINT ●
68 StatusOutput01 USINT ●
Configuration registers
38 ConfigOutput01 USINT ●
40 ConfigOutput02 UINT ●
60 ConfigOutput03 UDINT ●
64 ConfigOutput04 UDINT ●
134 ConfigOutput07 DINT ●
72 ConfigOutput08 DINT ●
84 ConfigOutput09 DINT ●
88 ConfigOutput10 DINT ●
92 ConfigOutput11 DINT ●
96 ConfigOutput12 DINT ●
100 ConfigOutput13 UDINT ●
104 ConfigOutput14 UDINT ●
76 ConfigOutput15 DINT ●
80 ConfigOutput16 DINT ●
138 ConfigOutput17 DINT ●
142 ConfigOutput18 DINT ●
146 ConfigOutput19 DINT ●
150 ConfigOutput20 DINT ●
154 ConfigOutput21 UDINT ●
158 ConfigOutput22 UDINT ●
42 ConfigOutput23 USINT ●
44 ConfigOutput24 USINT ●
Read configuration register
38 ConfigOutput01Read USINT ●
40 ConfigOutput02Read UINT ●
60 ConfigOutput03Read UDINT ●
64 ConfigOutput04Read UDINT ●
134 ConfigOutput07Read DINT ●
72 ConfigOutput08Read DINT ●
84 ConfigOutput09Read DINT ●
88 ConfigOutput10Read DINT ●
92 ConfigOutput11Read DINT ●
96 ConfigOutput12Read DINT ●
100 ConfigOutput13Read UDINT ●
104 ConfigOutput14Read UDINT ●
76 ConfigOutput15Read DINT ●
80 ConfigOutput16Read DINT ●
138 ConfigOutput17Read DINT ●
142 ConfigOutput18Read DINT ●
146 ConfigOutput19Read DINT ●
150 ConfigOutput20Read DINT ●
154 ConfigOutput21Read UDINT ●
158 ConfigOutput22Read UDINT ●
42 ConfigOutput23Read USINT ●
44 ConfigOutput24Read USINT ●
Status register
108 StatusInput09 UDINT ●
112 StatusInput10 UDINT ●
116 StatusInput11 UDINT ●
120 StatusInput12 UDINT ●
162 StatusInput13 UDINT ●

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Register Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
166 StatusInput14 UDINT ●
170 StatusInput15 UDINT ●
174 StatusInput16 UDINT ●
178 StatusInput17 UDINT ●
182 StatusInput18 UDINT ●
186 StatusInput19 UDINT ●
190 StatusInput20 UDINT ●
194 StatusInput21 UDINT ●
198 StatusInput22 UDINT ●
202 StatusInput23 UDINT ●
206 StatusInput24 UDINT ●
210 StatusInput25 UDINT ●
214 StatusInput26 UDINT ●
218 StatusInput27 UDINT ●
222 StatusInput28 UDINT ●
226 StatusInput29 UDINT ●
230 StatusInput30 UDINT ●
234 StatusInput31 UDINT ●
238 StatusInput32 UDINT ●
242 StatusInput33 UDINT ●
246 StatusInput34 UDINT ●
250 StatusInput35 UDINT ●
254 StatusInput36 UDINT ●

4.11.13.7.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Synchronous register
0 0 Position01 DINT ●
4 8 Position02 DINT ●
8 16 Position03 DINT ●
12 24 Position04 DINT ●
30 4 Speed01 INT ●
32 12 Speed02 INT ●
34 20 Speed03 INT ●
36 28 Speed04 INT ●
38 - LB: Error status of Magnet 1 UINT ●
HB: Module status
6 ErrorStatus01 USINT ●
7 StatusInput01 USINT ●
40 14 ErrorStatus02 USINT ●
42 22 ErrorStatus03 USINT ●
44 30 ErrorStatus04 USINT ●
100 0 USSpeed01 UDINT ●
109 8 USSpeed02 UDINT ●
150 16 StatusOutput01 USINT ●
Configuration registers
2200 - ConfigOutput01 USINT ●
2100 - ConfigOutput02 UINT ●
2000 - ConfigOutput03 UDINT ●
2004 - ConfigOutput04 UDINT ●
2008 - ConfigOutput07 DINT ●
2012 - ConfigOutput08 DINT ●
2024 - ConfigOutput09 DINT ●
2028 - ConfigOutput10 DINT ●
2040 - ConfigOutput11 DINT ●
2044 - ConfigOutput12 DINT ●
2056 - ConfigOutput13 UDINT ●
2060 - ConfigOutput14 UDINT ●
2016 - ConfigOutput15 DINT ●
2020 - ConfigOutput16 DINT ●
2032 - ConfigOutput17 DINT ●
2036 - ConfigOutput18 DINT ●
2048 - ConfigOutput19 DINT ●
2052 - ConfigOutput20 DINT ●
2064 - ConfigOutput21 UDINT ●
2068 - ConfigOutput22 UDINT ●
2201 - ConfigOutput23 USINT ●
2202 - ConfigOutput24 USINT ●
Read configuration register
2200 - ConfigOutput01Read USINT ●
2100 - ConfigOutput02Read UINT ●

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Register Offset1) Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
2000 - ConfigOutput03Read UDINT ●
2004 - ConfigOutput04Read UDINT ●
2008 - ConfigOutput07Read DINT ●
2012 - ConfigOutput08Read DINT ●
2024 - ConfigOutput09Read DINT ●
2028 - ConfigOutput10Read DINT ●
2040 - ConfigOutput11Read DINT ●
2044 - ConfigOutput12Read DINT ●
2056 - ConfigOutput13Read UDINT ●
2060 - ConfigOutput14Read UDINT ●
2016 - ConfigOutput15Read DINT ●
2020 - ConfigOutput16Read DINT ●
2032 - ConfigOutput17Read DINT ●
2036 - ConfigOutput18Read DINT ●
2048 - ConfigOutput19Read DINT ●
2052 - ConfigOutput20Read DINT ●
2064 - ConfigOutput21Read UDINT ●
2068 - ConfigOutput22Read UDINT ●
2201 - ConfigOutput23Read USINT ●
2202 - ConfigOutput24Read USINT ●
Status register
2500 - StatusInput09 UDINT ●
2556 - StatusInput10 UDINT ●
2504 - StatusInput11 UDINT ●
2560 - StatusInput12 UDINT ●
2508 - StatusInput13 UDINT ●
2564 - StatusInput14 UDINT ●
2512 - StatusInput15 UDINT ●
2568 - StatusInput16 UDINT ●
2516 - StatusInput17 UDINT ●
2572 - StatusInput18 UDINT ●
2520 - StatusInput19 UDINT ●
2524 - StatusInput20 UDINT ●
2528 - StatusInput21 UDINT ●
2532 - StatusInput22 UDINT ●
2536 - StatusInput23 UDINT ●
2540 - StatusInput24 UDINT ●
2576 - StatusInput25 UDINT ●
2580 - StatusInput26 UDINT ●
2584 - StatusInput27 UDINT ●
2588 - StatusInput28 UDINT ●
2592 - StatusInput29 UDINT ●
2596 - StatusInput30 UDINT ●
2544 - StatusInput31 UDINT ●
2548 - StatusInput32 UDINT ●
2552 - StatusInput33 UDINT ●
2600 - StatusInput34 UDINT ●
2604 - StatusInput35 UDINT ●
2608 - StatusInput36 UDINT ●

1) The offset specifies the position of the register within the CAN object.

In the bus controller function model, the measurements made from the module are not synchronized with the X2X
Link. The time between two measurements is defined by the configured recovery time for the rod (see section
4.11.13.7.11 "Channel configuration" on page 789) unlike on the X2X where it is the smallest multiple of the X2X
cycle time that is larger than the configured recovery time.

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4.11.13.7.3 Commissioning a transducer rod

Two registers need to be configured to initialize an ultrasonic transducer rod and receive valid measurements. The
first step is to enter the length of the rod (see section 4.11.13.7.12 "Rod length 1 and 2" on page 789). The wave
propagation speed for the rod must then be defined (see section 4.11.13.7.8 "Ultrasonic speed specification" on
page 787). This information can usually be found directly on the transducer rod itself or in its data sheet.
If the plausibility limits remain set to 0 (default value), one of the respective ErrorStatus registers will now indicate
faulty readings or plausibility errors. If this is the case, plausibility mode can be disabled using the "ConfigOutput01"
register (see section 4.11.13.7.10 "Module configuration" on page 788). This will cause the positions of the mag-
nets to be displayed on the rod.

4.11.13.7.4 Reading the magnet position

Name:
Position01 - Position04
These registers contain the position of the individual magnets on the transducer rods.
Data type Value
DINT -2,147,483,648 to 2,147,483,647: Resolution 1 µm

4.11.13.7.5 Reading the magnet speed

Name:
Speed01 to Speed04
These registers contain the speed of the individual magnets on the transducer rods. A resolution of 0.1 mm/s is
achieved by calculating the speed from 2 position values within a 100 ms interval.
Data type Value
INT -32768 to 32767: Resolution 0.1 mm/s

4.11.13.7.6 Error status

Name:
ErrorStatus01 to ErrorStatus04
These registers can be used to indicate the error status for individual channels.
Data type Value
USINT See bit structure.

Bit structure
Bit Description
0-3 Counter for plausibility errors (cyclic)
4-7 Counter for mis-measurements (cyclic)

Possible reasons for plausibility errors:

• Configured max. or min. path of a magnet was exceeded
• Configured max. speed was exceeded
Possible reasons for faulty measurements:
• Configured rod length was exceeded
• Rod failure
• Missing measurement magnet

Information:
If the registers "USSpeed01" and "USSpeed02" are unequal to 0 after the module starts up, the respec-
tive error counters on slower fieldbus systems (e.g. CAN I/O) may continue to count until the module
configuration is completed. In some cases, this is due problems between the respective rod and the
default configuration.

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4.11.13.7.7 Status information about the transducer rods

Name:
StatusInput01
This register displays the status information for the transducer rods.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Supply voltage too low 0 Supply voltage OK
1 Supply voltage too low
1 Supply voltage too high 0 Supply voltage OK
1 Supply voltage too high
2 Transducer Rod 1 0 Ok
1 Deactivated or not initialized
3 Transducer Rod 2 0 Ok
1 Deactivated or not initialized
4 Transducer Rod 1 0 Protocol error (invalid data)
1 Protocol OK (valid data)
5 Transducer Rod 2 0 Protocol error (invalid data)
1 Protocol OK (valid data)
6-7 Reserved

Comment concerning bits 4 + 5

If this bit is set to "1", configuration data was successfully read from the measurement rod using DPI/IP or EP
protocol. This data can now be read into the application using asynchronous access.

4.11.13.7.8 Ultrasonic speed specification

Name:
USSpeed01 to USSpeed02
The module does not perform any measurements on the respective rod while these registers have the value 0.
Also disabled:
• Automatic check to determine whether a rod is connected
• Parameter upload via DPI/IP or EP protocol
If a value >0 but <1000cm/s is specified here, the module freezes all measurements and error counters of the
corresponding rod, regardless of whether plausibility mode is enabled or not. Based on the default ultrasonic speed
of 280,000 cm/s, however, periodic measurement start pulses continue to be generated according to the formula
in section 4.11.13.7.11 "Channel configuration" on page 789. In this case the rod check (inserted/not inserted
and parameter upload) continues to be active.
As soon as a valid value (≥1000) is specified, the module recalculates the measurement rate (see section
4.11.13.7.11 "Channel configuration" on page 789) and begins the position/speed measurement.
Data type Value
UDINT 0 to 4,294,967,296: Resolution 1 cm/s

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4.11.13.7.9 Applying new magnet offsets

Name:
StatusOutput01
This register makes it easier to more quickly determine new offsets (= zero positions) for the individual magnets.
This approach is an alternative or additional method to determining an offset via configuration registers (see section
4.11.13.7.13 "Offset position on the transducer" on page 790).
If the respective bit changes from 0 to 1 in "StatusOutput01" (see following table) then the current mechanical
position of the respective magnet becomes the calculated zero position (register "Position0x" = 0).
From that moment, the current mechanical position will be subtracted from all future measured positions. This is
essentially a type of referencing. The max. and min. magnet paths (see section 4.11.13.7.14 "Plausibility check
configuration" on page 790) are now based on the new zero position.
This process can be repeated at any time by setting the bit again.

Information:
An offset position determined in this manner CANNOT be read out. The registers
"ConfigOutput07Read", "ConfigOutput08Read", "ConfigOutput15Read" and "ConfigOutput16Read"
can only be used to read the current contents of "ConfigOutput07", "ConfigOutput08", "ConfigOut-
put15" and "ConfigOutput16".
Data type Value
USINT See bit structure.

Bit Name Value Information

0 Magnet 1 0 No effect
1 Apply offset magnet 1
... ...
3 Magnet 4 0 No effect
1 Apply offset magnet 4
4-7 Reserved

4.11.13.7.10 Module configuration

Name:
ConfigOutput01
This register configures the module.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Plausibility mode 0 The plausibility error counter is incremented with each implau-
sible measurement and the last plausible measurement value is
"frozen" (default)
1 The plausibility error counter is incremented with each implau-
sible measurement and the implausible measurement value is
forwarded to the controller
1 Reserved
2-3 Tolerance for monitoring the supply voltage 00 25%
01 20%
10 15%
11 10%
4-7 Magnet number 0000 4 magnets on channel 1, channel 2 not available
0001 3 magnets on channel 1, 1 magnet on channel 2
0010 2 magnets on channel 1, 2 magnets on channel 2
0011 1 magnet on channel 1, 0 magnets on channel 2
0100 2 magnets on channel 1, 0 magnets on channel 2
0101 3 magnets on channel 1, 0 magnets on channel 2
0110 2 magnets on channel 1, 1 magnet on channel 2
0111 1 magnet on channel 1, 1 magnet on channel 2
1xxx Reserved

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4.11.13.7.11 Channel configuration

Name:
ConfigOutput02
This register can be used to configure the individual channels.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-2 Transducer Rod 1 000 User parameter
001 DPI/IP (Balluf)
010 EP Start/Stop (MTS)
011 Reserved
1xx Reserved
3-4 Rod 1: Start/Stop IF type 00 Start/Stop Signal: Rising edge - rising edge
01 Start/Stop Signal: Falling edge - falling edge
10 Start/Stop Signal: Rising edge - falling edge (gate time)
11 Only Stop Signal: Start when signal is triggered (initialization
pulses)
5 Rod 1: Recovery time factor, minimum time between two mea- 0 3 x USW runtime for rod (default)
surements 1 2 x USW runtime for rod
6-7 Reserved
8 - 10 Transducer Rod 2 000 User parameter
001 DPI/IP (Balluf)
010 EP Start/Stop (MTS)
011 Reserved
1xx Reserved
11 - 12 Rod 2: Start/Stop IF type 00 Start/Stop Signal: Rising edge - rising edge
01 Start/Stop Signal: Falling edge - falling edge
10 Start/Stop Signal: Rising edge - falling edge (gate time)
11 Only Stop Signal: Start when signal is triggered (initialization
pulses)
13 Rod 2: Recovery time factor, minimum time between two mea- 0 3 x USW runtime for rod (default)
surements 1 2 x USW runtime for rod
14 - 15 Reserved

Comment concerning bits 5 + 13

USW transducer rods require a certain recovery time between two measurements to allow the ultrasonic wave to
fade. Otherwise there is a risk of interfering with the next measurement (especially when the rod has more than
1 magnet).
Depending on the setting, the module waits at least 2 or 3 times the runtime of the ultrasonic wave for the measure-
ment rod (default = 3x). In the standard function module, the next measurement is then triggered synchronously
with the next X2XLink cycle.
The runtime measurement is based on the settings for the rod length (plus a safety margin of 100mm) and the
ultrasonic speed:
• USW runtime = (rod length + 100mm) / ultrasonic speed.
For their rods, BALLUFF recommends a recovery time equal to 3 times the maximum runtime of the ultrasonic
wave for the measurement rod. This is the default setting for the module.
The setting can be switched to 2 times the runtime if the measurement rate is otherwise too slow. This may only
be done after consulting the manufacturer of the transducer rods!

4.11.13.7.12 Rod length 1 and 2

Name:
ConfigOutput03 to ConfigOutput04
These registers are used to configure the length of the respective rod.
• Rod length 1: ConfigOutput03
• Rod length 2: ConfigOutput04
Data type Value
UDINT 0 to 4,294,967,296: Resolution 1 mm

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4.11.13.7.13 Offset position on the transducer

Name:
ConfigOutput07 to ConfigOutput08
ConfigOutput15 to ConfigOutput16
These registers are used to assign the respective magnet an offset position (= zero position) on the transducer.
The max. and min. magnet paths refer to these specified offsets (see 4.11.13.7.14 "Plausibility check configuration"
on page 790). If the offset is changed using the StatusOutput01 register, this becomes the new zero position.
This does not affect the contents of the offset register.
• Offset magnet 1: ConfigOutput07
• Offset magnet 2: ConfigOutput08
• Offset magnet 3: ConfigOutput15
• Offset magnet 4: ConfigOutput16
Data type Value
DINT -2,147,483,648 to 2,147,483,647: Resolution 1 µm

4.11.13.7.14 Plausibility check configuration

These registers are used to configure the plausibility check (also see section 4.11.13.7.6 "Error status" on page
786).

4.11.13.7.14.1 Min. plausible magnet position

Name:
ConfigOutput09 to ConfigOutput10
ConfigOutput17 to ConfigOutput18
These registers are used to assign the min. plausible magnet position based on the applicable offset.
• Min. path - magnet 1: ConfigOutput09
• Min. path - magnet 2: ConfigOutput10
• Min. path - magnet 3: ConfigOutput17
• Min. path - magnet 4: ConfigOutput18
Data type Value
DINT -2,147,483,648 to 2,147,483,647: Resolution 1 µm

4.11.13.7.14.2 Max. plausible magnet position

Name:
ConfigOutput11 to ConfigOutput12
ConfigOutput19 to ConfigOutput20
These registers are used to assign the max. plausible magnet position based on the applicable offset.
• Max. path - magnet 1: ConfigOutput11
• Max. path - magnet 2: ConfigOutput12
• Max. path - magnet 3: ConfigOutput19
• Max. path - magnet 4: ConfigOutput20
Data type Value
DINT -2,147,483,648 to 2,147,483,647: Resolution 1 µm

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4.11.13.7.14.3 Max. plausible magnet speed

Name:
ConfigOutput13 to ConfigOutput14
ConfigOutput21 to ConfigOutput22
These registers are used to assign the max. plausible magnet speed.
• Max. speed - magnet 1: ConfigOutput13
• Max. speed - magnet 2: ConfigOutput14
• Max. speed - magnet 3: ConfigOutput21
• Max. speed - magnet 4: ConfigOutput22
Data type Value
UDINT 0 to 4,294,967,296: Resolution 0.1 mm/s

4.11.13.7.15 Dead time for rods 1 and 2

Name:
ConfigOutput23 to ConfigOutput24
These registers are used to configure the dead time of the respective rod.
• Dead time for rod 1: ConfigOutput23
• Dead time for rod 2: ConfigOutput24
To prevent the multiple pulses that occur with some encoders from affecting the measurement, all pulses received
within a configurable timespan from the beginning of the measurement are not evaluated. The range for the dead
time lies between 0 and 255 µs. The following figure illustrates the effects of defining a dead time:
Init pulse Init pulse
to the encoder

Start pulse Possible

occurring
Start/Stop multiple pulses
pulses 1st stop pulse 2nd stop pulse
from the encoder

Pulse t
ignored

Measurement time of first counter

Measurement time of second counter

Figure 287: Pulse Ignored after Start Pulse

Data type Value
USINT 0 to 255: Resolution 1 µs (default: 0 µs)

4.11.13.7.16 Read configuration register

Name:
ConfigOutput01Read to ConfigOutput04Read
ConfigOutput07Read to ConfigOutput24Read
These registers are used to read the states of the corresponding configuration registers.

4.11.13.7.17 Status register

Name:
StatusInput09 to StatusInput36
These registers are used to store the data read after a parameter upload from transducer rods with DPI/IP protocol
or EP protocol. The registers "StatusInput19" to "StatusInput36" remain empty (0x0000) on transducer rods with
EP protocol.

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4.11.13.7.17.1 Parameter overview

The following parameters are stored in the status registers:

Register Description Supported by the protocol
DP/IP EP
StatusInput09 Rod length 1 [mm] ● ●
StatusInput10 Rod length 2 [mm] ● ●
StatusInput11 Ultrasonic speed 1 ● ●
StatusInput12 Ultrasonic speed 2 ● ●
StatusInput13 Rod 1: Zero point offset [µm] ● ●
StatusInput14 Rod 2: Zero point offset [µm] ● ●
StatusInput15 Rod 1: Vendor ID (see transducer rod data sheet) ● ●
StatusInput16 Rod 2: Vendor ID (see transducer rod data sheet) ● ●
StatusInput17 Rod 1: Serial number (Hex coded) ● ●
StatusInput18 Rod 2: Serial number (Hex coded) ● ●
StatusInput19 Rod 1: Type ID 1 (MSB = letter 1) ● 0x0000
StatusInput20 Rod 1: Type ID 2 (MSB = letter 5) ● 0x0000
StatusInput21 Rod 1: Type ID 3 (MSB = letter 9) ● 0x0000
StatusInput22 Rod 1: Type ID 4 (MSB = letter 13) ● 0x0000
StatusInput23 Rod 1: Type ID 5 (MSB = letter 17) ● 0x0000
StatusInput24 Rod 1: Type ID 6 (MSB = letter 21) ● 0x0000
StatusInput25 Rod 2: Type ID 1 (MSB = letter 1) ● 0x0000
StatusInput26 Rod 2: Type ID 2 (MSB = letter 5) ● 0x0000
StatusInput27 Rod 2: Type ID 3 (MSB = letter 9) ● 0x0000
StatusInput28 Rod 2: Type ID 4 (MSB = letter 13) ● 0x0000
StatusInput29 Rod 2: Type ID 5 (MSB = letter 17) ● 0x0000
StatusInput30 Rod 2: Type ID 6 (MSB = letter 21) ● 0x0000
StatusInput31 Rod 1: Serial number ASCII 1 (MSB = letter 1) ● 0x0000
StatusInput32 Rod 1: Serial number ASCII 2 (MSB = letter 5) ● 0x0000
StatusInput33 Rod 1: Serial number ASCII 3 (MSB = letter 9) ● 0x0000
StatusInput34 Rod 2: Serial number ASCII 1 (MSB = letter 1) ● 0x0000
StatusInput35 Rod 2: Serial number ASCII 2 (MSB = letter 5) ● 0x0000
StatusInput36 Rod 2: Serial number ASCII 3 (MSB = letter 9) ● 0x0000

4.11.13.7.17.2 DPI/IP protocol (BALLUFF) / EP protocol (MTS)

Requirements for a successful upload of the transducer rod parameters to the module:
1. Selection of the communication protocol (DPI/IP or EP). See section . 4.11.13.7.11 "Channel configuration"
on page 789
2. Transducer rod must support the respective protocol.
3. If the transducer rod does not support the selected protocol, the module will detect this after a timeout of
approx. 300 ms and will treat the rod as a "normal" transducer rod.

After the module is started or after a transducer rod is connected, the parameter upload should be complete within
200 to 400 ms.
A communication error causes the data upload to cancel. A new upload attempt can be initiated by the user by
deactivating and reactivating the communication protocol using asynchronous access.
All rod parameters can be read to the controller using asynchronous access. The read parameters "rod length"
and "ultrasonic speed" are NOT automatically uploaded to the module.
It is left up to the application whether the upload values for rod length 1 and rod length 2 or for ultrasonic speed 1
and ultrasonic speed 2 are uploaded.

Information:
Keep in mind that no position measurements can be performed on a rod while parameters are being
uploaded. The module freezes all existing position/speed data for all magnets on the rod while the
parameters are uploading. Parameters should therefore only be uploaded with the machine stopped,
and this should be ensured by the application.

4.11.13.7.18 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
250 µs

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4.11.14 X20DC2395

4.11.14.1 General information

This module is a multifunctional counter module. It can be connected to one SSI encoder, one ABR encoder, two
AB encoders or four event counters. Two outputs are available for pulse width modulation. The functions can also
be mixed.
• 24 VDC encoder inputs
• SSI, ABR, AB or event counters for inputs
• Pulse width modulation for outputs
• 24 VDC and GND for encoder supply

Information:
This module is a multifunctional module. Some bus controllers only support the default function model.
Default function model:
• 2x event counter (24 V)
• 2x PWM output (24 V)

4.11.14.2 Order data

Model number Short description Figure

Counter functions
X20DC2395 X20 digital counter module, 1 SSI absolute encoder, 24 V, 1 ABR
incremental encoder, 24 V, 2 AB incremental encoders, 24 V, 4
event counters or 2 PWM, local time measurement function
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 248: X20DC2395 - Order data

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4.11.14.3 Technical data

Product ID X20DC2395
Short description
I/O module 1 SSI absolute encoder, 24 V, 1 ABR incremental encoder, 24 V, 2 AB incremental encoders,
24 V, 4x event counters or 2x pulse width modulation, time measurement, relative timestamp
General information
Input voltage 24 VDC -15% / +20%
B&R ID code 0x1CD4
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, using the status LED and software (output error status)
Power consumption
Bus 0.01 W
Internal I/O 1.4 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Output - Output No
Output - Bus Yes
Output - Encoder No
Encoder - Bus Yes
Encoder - Encoder No
Type of signal lines Shielded cables must be used for all signal lines.
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Incremental encoder
Quantity 2
Encoder inputs 24 V, asymmetrical
Counter size 16/32-bit
Input frequency Max. 100 kHz
Evaluation 4x
Encoder supply Module-internal, max. 600 mA
Overload behavior of the encoder supply Short circuit protection, overload protection
SSI absolute encoder
Quantity 1
Encoder inputs 24 V, asymmetrical
Counter size 32-bit
Max. transfer rate 125 kbit/s
Encoder supply Module-internal, max. 600 mA
Keying Gray/Binary
CLK: Output current Max. 100 mA
Overload behavior of the encoder supply Short circuit protection, overload protection
Event counter
Quantity 4
Nominal voltage 24 VDC
Signal form Square wave pulse
Evaluation Each edge, cyclic counter
Input frequency Max. 100 kHz
Input current at 24 VDC Approx. 1.3 mA
Input resistance 18.4 kΩ
Isolation voltage between channel and bus 500 Veff
Counter frequency 200 kHz
Counter size 16/32-bit
Input filter
Hardware ≥2 µs
Software -
Switching threshold
Low <5 VDC
High >15 VDC
Time measurement
Possible measurements Gate time, period duration, edge offset for various channels
Measurements per module Up to 9
Measurements per channel Up to 2
Counter size 16-bit
Counter frequency
Internal 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 62.5 kHz
Signal form Square wave pulse

Table 249: X20DC2395 - Technical data

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Product ID X20DC2395
Measurement type Continuous or triggered
Digital outputs
Design Push / Pull / Push-Pull
Quantity 2
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.1 A
Total nominal current 0.2 A
Output circuit Sink or source
Output protection Thermal cutoff if overcurrent or short circuit occurs, integrated protection for switching inductances
Pulse width modulation 1)
Period duration 41.6 µs to 1.36 s
Factor for period duration n/48000 s, n = 2 to 65535
Pulse duration 0 to 100%
Resolution for pulse duration 0.1%
Actuator supply Module-internal, max. 600 mA
Diagnostic status Output monitoring
Leakage current when switched off Max. 25 µA
Residual voltage <0.9 V at 0.1 A rated current
Peak short circuit current <10 A
Switching on after overload or short circuit cutoff Approx. 10 ms (depends on the module temperature)
Switching delay
0 -> 1 <2 µs
1 -> 0 <2 µs
Switching frequency
Resistive load Max. 24 kHz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Switching voltage + 0.6 VDC
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 249: X20DC2395 - Technical data

1) Dead time when switching between push and pull: max. 1.5 µs.

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4.11.14.4 LED status indicators

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
1-4 Green Status of the corresponding digital signal

1) Depending on the configuration, a firmware update can take up to several minutes.

4.11.14.5 Pinout

Shielded cables must be used for all signal lines.

r e

X20 DC 2395
1
2
3
4

Channel 1

Channel 2

Channel 3

Channel 4

Encoder 24 V +

GND

4.11.14.6 Connection example

DC

Data

Cycle
Counter 1

A
B
R
PWM

+24 VDC +24 VDC

GND GND

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4.11.14.7 Function overview

The following functions can be configured on the module. They cannot all be used at the same time due to the
multiple use of the hardware channels and the limited cyclic data length.
• 4 digital channels, 2 of which can be configured as outputs
• 4 event counters with configurable counting direction and optional referencing via digital input
• 2 PWM outputs
• 2 up/down counters, each with optional latch inputs and comparator output
• 2 AB counters, each with optional latch inputs and comparator output
• 1 ABR encoder with configurable reference pulse edge and reference position, optional reference enable
input, latch input and comparator output
• 1 SSI counter with optional latch input and comparator output
• 2 edge-triggered time measurement functions with configurable start edge based on current configuration
settings

4.11.14.7.1 Description of channel assignments

The functions listed here are directly assigned to the respective hardware channels and cannot be changed:
Channel Signal connections
1 • Digital input 1
• Event counter 1
• AB encoder 1 - signal line A
• Up/down counter 1 - frequency
• SSI encoder 1 - data line
• ABR encoder 1 - signal line A
2 • Digital input 2
• Digital output 2
• Event counter 2
• PWM output 2
• AB encoder 1 - signal line B
• Up/down counter 1 - direction
• SSI encoder 1 - clock line
• ABR encoder 1 - signal line B
3 • Digital input 3
• Event counter 3
• AB encoder 2 - signal line A
• Up/down counter 2 - frequency
• ABR encoder 1 - signal line R
4 • Digital input 4
• Digital output 4
• Event counter 4
• PWM output 4
• AB encoder 2 - signal line B
• Up/down counter 2 - direction
• ABR encoder 1 - reference enable input

Options available in addition to these basic functions, such as comparator outputs or latch inputs, can be configured
freely to unused input/output channels.

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4.11.14.7.2 Connection options

Channels 1 to 4 can be connected as follows:

Channel Function
1 I Event counter A A SSI data
2 I/O Event counter B B SSI cycle PWM
3 I Event counter A R
4 I/O Event counter B Enable reference PWM

The functions can also be mixed. For example:

Example 1 Example 2 Example 3
Channel Function Channel Function Channel Function
1 SSI data 1 SSI data 1 Event counter
2 SSI cycle 2 SSI cycle 2 PWM
3 Event counter 3 A 3 Event counter
4 PWM 4 B 4 PWM

Example 4 Example 5 Example 6

Channel Function Channel Function Channel Function
1 A 1 A 1 Event counter
2 B 2 B 2 PWM
3 R 3 Event counter 3 A
4 Enable reference 4 PWM 4 B

4.11.14.8 Input circuit diagram

Input x

VDR
Input status

I/O status

24 V
PTC
Encoder 24 V LED (green)

GND

GND

4.11.14.9 Output circuit diagram

24 V

Output status Push

PTC
Output x

VDR
Output status Pull

GND
Output
monitoring

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4.11.14.10 Switching inductive loads

100 H 10 H 1H
1000
0.1 H

Coil resistance
Coil inductance
[Ω]

0.01 H
240 Ω ≙ 100 mA
0.1 1 10 100 1000 10000

Max. switching cycles / second

(with 90% duty cycle)

4.11.14.11 Calculating the period duration

The outputs of the module can be operated as PWM outputs. The period duration is calculated using the following
formula:
n
Period duration = s
48000
A value of 2 to 65535 can be defined for n.

Example
n Period duration Frequency
2 416 μs 24 kHz
24000 500 ms 2 Hz
48000 1s 1 Hz
65535 1.36 s 0.73 Hz

Table 250: Calculating the period duration

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4.11.14.12 Register description

4.11.14.12.1 Function model 0 - Standard and Function model 1 - 32-bit counter

The following 2 models can be selected:

• 16-bit counter, Function model 0
• 32-bit counter, Function model 1 (identified in the table with a "(D)" in the data type and "(_32Bit)" in the
name.)
The only difference between these two models is that they use either 16-bit or 32-bit registers for incremental
counter functions. These include:
• ABR encoders
• AB encoders
• Up/down counters
• Event counters
All other module functions e.g. SSI, PWM and time measurement, as well as their data types, are identical for
the two models.
Register Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
Module configuration - General
(N-1) * 2 CfO_CFGchannel0N (Index N = 1 to 4) USINT ●
64 + N * 2 CfO_LEDNsource (Index N = 0 to 3) USINT ●
Configuration - Input for ABR encoders
512 CfO_DIREKTIOevent0IDwr UINT ●
516 CfO_DIREKTIOevent0mode USINT ●
522 CfO_DIREKTIOevent0compState UINT ●
520 CfO_Ev0CompMask USINT ●
2,064 CfO_Counter1PresetValue1(_32Bit) U(D)INT ●
2,068 CfO_Counter1PresetValue2(_32Bit) U(D)INT ●
2,320 CfO_Counter2PresetValue1(_32Bit) U(D)INT ●
2,324 CfO_Counter2PresetValue2(_32Bit) U(D)INT ●
2,048 CfO_Counter1config USINT ●
2,056 CfO_Counter1configReg0 USINT ●
2,058 CfO_Counter1configReg1 USINT ●
2,112 CfO_Counter1event0IDwr UDINT ●
2,120 CfO_Counter1event0config UINT ●
2,144 CfO_Counter1event1IDwr UINT ●
2,152 CfO_Counter1event1config UINT ●
2,148 CfO_Counter1event1mode USINT ●
Configuration - Inputs for AB, up/down and event counters
2,048 CfO_Counter1config USINT ●
2,056 CfO_Counter1configReg0 USINT ●
2,058 CfO_Counter1configReg1 USINT ●
2,112 CfO_Counter1event0IDwr UDINT ●
2,120 CfO_Counter1event0config UINT ●
2,116 CfO_Counter1event0mode USINT ●
2,144 CfO_Counter1event1IDwr UINT ●
2,152 CfO_Counter1event1config UINT ●
2,148 CfO_Counter1event1mode USINT ●
2,304 CfO_Counter2config USINT ●
2,312 CfO_Counter2configReg0 USINT ●
2,314 CfO_Counter2configReg1 USINT ●
2,368 CfO_Counter2event0IDwr UINT ●
2,376 CfO_Counter2event0config UINT ●
2,372 CfO_Counter2event0mode USINT ●
2,400 CfO_Counter2event1IDwr UINT ●
2,408 CfO_Counter2event1config UINT ●
2,404 CfO_Counter2event1mode USINT ●
Configuration - Inputs for SSI encoders
7,176 CfO_SSI1cfg UINT ●
7,180 CfO_SSI1control USINT ●
7,168 CfO_SSI1eventIDwr UINT ●
7,232 CfO_SSI1event0IDwr UINT ●
7,240 CfO_SSI1event0config UINT ●
7,236 CfO_SSI1event0mode USINT ●
7,172 ConfigAdvanced01 UDINT ●
Configuration - Comparator function for ABR, AB, SSI encoders and up/down counters
256 CfO_OutClearMask USINT ●
258 CfO_OutSetMask USINT ●

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Register Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
1,024 CfO_DIREKTIOoutevent0IDwr UINT ●
1,034 CfO_DIREKTIOoutsetmask0 USINT ●
1,032 CfO_DIREKTIOoutclearmask0 USINT ●
1,066 CfO_DIREKTIOoutsetmask1 USINT ●
1,064 CfO_DIREKTIOoutclearmask1 USINT ●
1,056 CfO_DIREKTIOoutevent1IDwr UINT ●
Configuration - Outputs for PWM (pulse width modulation)
6,144 CfO_PWM0prescaler UINT ●
6,160 CfO_PWM1prescaler UINT ●
Module communication - General
40 Status of encoder supply USINT ●
PowerSupply01 Bit 0
Communication - Digital inputs
264 Input states of the channels USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput04 Bit 3
Communication - Event counters
2,080 EventCounter01 U(D)INT ●
2,084 EventCounter02 U(D)INT ●
2,336 EventCounter03 U(D)INT ●
2,340 EventCounter04 U(D)INT ●
Communication - Input for ABR encoders (optionally with comparator)
2,080 ABREncoder01 (D)INT ●
2,116 ReferenceModeABR01 USINT ●
2,160 OriginComparator01 (D)INT ●
2,164 MarginComparator01 U(D)INT ●
264 Input states of the channels USINT ●
ReferenceEnableSwitch01 (without comparator) Bit 3
ComparatorActualValue01 (with comparator)
2,172 Latch01ABR01 (D)INT ●
2,118 StatusABR01 USINT ●
Communication - Input for AB
2,080 ABEncoder01 (D)INT ●
2,336 ABEncoder02 (D)INT ●
2,160 OriginComparator01 (D)INT ●
2,164 MarginComparator01 U(D)INT ●
264 Input states of the channels USINT ●
ComparatorActualValue01 Bit 3
2,140 Latch01AB01 (D)INT ●
2,172 Latch02AB01 (D)INT ●
2,396 Latch01AB02 (D)INT ●
2,428 Latch02AB02 (D)INT ●
Communication - Up/down counters
2,080 Counter01 U(D)INT ●
2,336 Counter02 U(D)INT ●
2,160 OriginComparator01 U(D)INT ●
2,164 MarginComparator01 U(D)INT ●
264 Input states of the channels USINT ●
ComparatorActualValue01 Bit 3
2,140 Latch01Counter01 U(D)INT ●
2,172 Latch02Counter01 U(D)INT ●
2,396 Latch01Counter02 U(D)INT ●
2,428 Latch02Counter02 U(D)INT ●
Communication - Input for SSI encoders
7,184 SSIEncoder01 UDINT ●
7,248 OriginComparator01 UDINT ●
7,252 MarginComparator01 UDINT ●
264 Input states of the channels USINT ●
ComparatorActualValue01 Bit 3
7,260 Latch01SSI01 UDINT ●
Communication - Digital outputs
260 Output states of the channels USINT ●
DigitalOutput02 Bit 1
DigitalOutput04 Bit 3
264 Input states of the channels USINT ●
StatusDigitalOutput02 Bit 1
StatusDigitalOutput04 Bit 3
Communication - Outputs for PWM (pulse width modulation)
6,146 PWMOutput02 UINT ●
6,162 PWMOutput04 UINT ●
Configuration - Edge detection
4,104 CfO_EdgeDetectFalling USINT ●
4,106 CfO_EdeDetectRising USINT ●

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Register Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
4,108 CfO_FallingDisProtection USINT ●
4,110 CfO_RisingDisProtection USINT ●
Configuration - Time measurement
4,336 CfO_EdgeTimeglobalenable USINT ●
4344 + N * 8 CfO_EdgeTimeFallingMode0N (Index N = 1 to 4) UINT ●
4472 + N * 8 CfO_EdgeTimeRisingMode0N (Index N = 1 to 4) UINT ●
Communication - Time measurement
4,342 Trigger rising edge detection USINT ●
TriggerRisingCH01 Bit 0
... ...
TriggerRisingCH04 Bit 3
4,350 Show first rising trigger edge USINT ●
BusyTriggerRisingCH01 Bit 0
... ...
BusyTriggerRisingCH04 Bit 3
4,340 Trigger falling edge detection USINT ●
TriggerFallingCH01 Bit 0
... ...
TriggerFallingCH04 Bit 3
4,348 Show first falling trigger edge USINT ●
BusyTriggerFallingCH01 Bit 0
... ...
BusyTriggerFallingCH04 Bit 3
4474 + N * 8 CountRisingCH0N (Index N = 1 to 4) USINT ●
4476 + N * 8 TimeStampRisingCH0N (Index N = 1 to 4) UINT ●
4478 + N * 8 TimeDiffRisingCH0N (Index N = 1 to 4) UINT ●
4346 + N * 8 CountFallingCH0N (Index N = 1 to 4) USINT ●
4348 + N * 8 TimeStampFallingCH0N (Index N = 1 to 4) UINT ●
4350 + N * 8 TimeDiffFallingCH0N (Index N = 1 to 4) UINT ●

4.11.14.12.2 Function model 254 - Bus controller

Unlike the function models 0 and 1, this model only offers a selection of functions with a limited scope of config-
uration on the module.
The following functions are provided and can be run at the same time:
• 2 event counter with configurable counting direction
• 2 PWM outputs
Register Offset1) Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
Configuration
(N-1) * 2 - CfO_CFGchannel0N (Index N = 1 to 4) USINT ●
64 + N * 2 - CfO_LEDNsource (Index N = 0 to 3) USINT ●
2,056 - CfO_Counter1configReg0 USINT ●
2,312 - CfO_Counter2configReg0 USINT ●
Communication
2,080 0 EventCounter01 UINT ●
2,336 2 EventCounter03 UINT ●
6,146 0 PWMOutput02 UINT ●
6,162 2 PWMOutput04 UINT ●
40 4 Status of encoder supply USINT ●
PowerSupply01 Bit 0

1) The offset specifies the position of the register within the CAN object.

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4.11.14.12.3 General module registers

4.11.14.12.3.1 Configuring LED status indicators

Name:
CfO_LED0source to CfO_LED3source
These registers can be used to define how the module's LED status indicators are used. Blinking patterns can be
generated from the application, and the status of the physical inputs and outputs can be indicated.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-3 MODE = 0 0 LED off
1 Blinking quickly
2 Blinking
3 Blinking slowly
4 Single flash
5 Double flash
6 to 15 Reserved
MODE = 1 (inverted) 0 LED on
1 Blinking quickly
2 Blinking
3 Blinking slowly
4 Single flash
5 Double flash
6 to 15 Reserved
MODE = 2 0 to 3 Number of the physical input channel
4 to 15 Reserved
MODE = 3 0 to 3 Number of the physical output channel
4 to 15 Reserved
4-7 Selection of the mode for the LED status indicator 0 LED blinking pattern
1 Inverted LED blinking pattern
2 Displays a channel's physical input status
3 Displays a channel's physical output status
4 to 15 Reserved

4.11.14.12.3.2 Status of encoder supply

Name:
PowerSupply01
This register shows the status of the integrated encoder supply. A faulty encoder power supply is displayed as
a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 PowerSupply01 0 24 VDC encoder power supply OK
1 24 VDC encoder power supply faulty
1-7 Reserved -

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4.11.14.12.4 Digital inputs and outputs

4.11.14.12.4.1 Configure physical channels

Name:
CfO_CFGchannel01 to CfO_CFGchannel04
This register can be used to configure physical I/O channels 1 to 4.

Information:
Except for bit 2 (inverted input), all other bits are only available for channels 2 and 4.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Push1) 0 Disabled
1 Enabled
1 Pull1) 0 Disabled
1 Enabled
2 Inverted input 0 Disabled
1 Enabled
3 Inverted output 0 Disabled
1 Enabled
4-7 Output type 0 Direct I/O
1 to 5 Reserved
6 PWM (channel-specific)
7 SSI clock (channel-specific)

1) To configure a channel as an output, Push and/or Pull must be enabled.

4.11.14.12.4.2 Reset mask of the digital channels

Name:
CfO_OutClearMask
The settings in this register only affect the values written to registers 4.11.14.12.4.5 "DigitalOutput02 and 04".
• 0 allows manual reset of digital outputs using registers DigitalOutput02 and 04
• 1 prevents manual reset of digital outputs using registers DigitalOutput02 and 04
When "1" is used, the "output event function" can be used to reset the outputs.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Reserved -
1 DigitalOutput02 0 Writing 0 to the DigitalOutput02 register resets the output
1 Writing 0 from the DigitalOutput02 register does not reset the
output
2 Reserved -
3 DigitalOutput04 0 Writing 0 to the DigitalOutput04 register resets the output
1 Writing 0 from the DigitalOutput04 register does not reset the
output
4-7 Reserved -

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4.11.14.12.4.3 Set mask of the digital channels

Name:
CfO_OutSetMask
The settings in this register only affect the values written to registers 4.11.14.12.4.5 "DigitalOutput02 and 04".
• 0 allows manual setting of digital outputs using registers DigitalOutput02 and 04
• 1 prevents manual setting of digital outputs using registers DigitalOutput02 and 04
When "1" is used, the "output event function" can be used to set the outputs.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Reserved -
1 DigitalOutput02 0 Writing 1 to the DigitalOutput02 register sets the output
1 Writing 1 from the DigitalOutput02 register does not set the out-
put
2 Reserved -
3 DigitalOutput04 0 Writing 1 to the DigitalOutput04 register sets the output
1 Writing 1 from the DigitalOutput04 register does not set the out-
put
4-7 Reserved -

4.11.14.12.4.4 Input states of the channels

Name:
see "Name in the AS I/O configuration"
This register reads the input status of a physical channel. The polarity settings are accounted for in the value (bit
2 in 4.11.14.12.4.1 "CfO_CFGchannel[x]" register).
The bits in this register are shown in the AS I/O mapping table under different names based on the function used
in order to improve readability.
Data type Value
USINT See bit structure.

Bit structure:
Bit Physical input channel Value Name in the AS I/O configuration
0 Channel 1 0 or 1 DigitalInput01
1 Channel 2 0 or 1 DigitalInput02
StatusDigitalOutput02
2 Channel 3 0 or 1 DigitalInput03
3 Channel 4 0 or 1 DigitalInput04
StatusDigitalOutput04
ReferenceEnableSwitch01
ComparatorActualValue01
4-7 Reserved -

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4.11.14.12.4.5 Output states of the channels

Name:
DigitalOutput02 and DigitalOutput04
The output status of a physical channel can be written using this register. In order to configure a channel as an
output:
1 Bit 0 "Push" and/or bit 1 "Pull" must be enabled in the 4.11.14.12.4.1 "CfO_CFGchannel[x]" register.
2 Bits 4 to 7 in the 4.11.14.12.4.1 "CfO_CFGchannel[x]" register must be set to Direct I/O.
3 0 must be set for the respective channel in the 4.11.14.12.4.2 "CfO_OutClearMask" and 4.11.14.12.4.3
"CfO_OutSetMask" registers.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Reserved -
1 DigitalOutput02 0 or 1 Output status of channel 2
2 Reserved -
3 DigitalOutput04 0 or 1 Output status of channel 4
4-7 Reserved -

4.11.14.12.5 Event functions

The module provides configurable event functions. An event function can be connected to physical I/O and the
values derived from them (e.g. counters) or be purely used for internal processing.
Every event function has event inputs and outputs. Event functions can also have only inputs or only outputs. Each
event output has a unique event ID. It is possible to configure when an event should be generated on an event
output. The effect of an event is determined by the respective event function.
Event functions can also be linked to one another. The link takes place using the event input. Every event input
has a 16-bit register to which the event number of the linked event output is written.

Information:
The module functions that can be configured in the AS I/O configuration are primarily based on these
event functions and their links. Changes in the AS I/O configuration have multiple effects on event
functions and their links.

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4.11.14.12.5.1 List of event IDs

Various hardware and software functions send event IDs or require event IDs in order to start. The following table
shows all of the IDs available to configure the module.
Event ID Description
Direct event inputs
512 Comparator condition FALSE
513 Comparator condition TRUE
Counter comparator function
2,112 Counter function 1 Event function 1; FALSE
2,113 Event function 1; TRUE
2,144 Event function 2; FALSE
2,145 Event function 2; TRUE
2,368 Counter function 2 Event function 1; FALSE
2,369 Event function 1; TRUE
2,400 Event function 2; FALSE
2,401 Event function 2; TRUE
Edge events
4,096 Falling edge on I/O channel Channel 1
... ...
4,099 Channel 4
4,112 Rising edge on I/O channel Channel 1
... ...
4,115 Channel 4
4,128 Rising or falling edge on I/O channel Channel 1
... ...
4,131 Channel 4
SSI counter events
7,168 SSI valid
7,169 SSI ready
SSI comparator events
7,232 SSI 1 comparator condition FALSE
7,233 TRUE
Timerevents
208 Timer1 50 μs
209 Timer2 100 μs
210 Timer3 200 μs
211 Timer4 400 μs
212 Timer5 800 μs
213 Timer6 1600 μs
214 Timer7 3200 μs
215 Timer8 3200 μs (time offset to timer 7)
Network functions
224 SOAISOP (synchronous out asynchronous in start of protocol)
225 AOSISOP (asynchronous out synchronous in start of protocol)
226 SOAIEOP (synchronous out asynchronous in end of protocol)
227 AOSIEOP (asynchronous out synchronous in end of protocol)
Idle event
192 No-load operation

Timer
There are 8 timer events that the module can generate.

Information:
The timers have the highest event priority. All other system functions are interrupted when a timer
event occurs, and jitter for the amount of time it takes to process the event.

Idle event
Idle time is the time that remains after the system has processed all higher priority events and operations. The
module performs the following functions during idle time:
• Handling of the asynchronous protocol
• Mechanism for (re-)linking events
• Operation of LEDs
• Execution of event event functions linked to the idle function

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4.11.14.12.5.2 Edge events

For each physical input channel there are 3 event functions

• Falling edge
• Rising edge
• Falling and rising edge
The respective event is triggered when an edge is detected on the hardware input and the "CfO_EdgeDetectRising"
and/or "CfO_EdgeDetectFalling" register has been configured for the respective channel.
Edges are detected by the hardware and processed for each interrupt. The interrupt handler uses an event distrib-
utor, which requires a specific amount of time for each edge to operate the hardware and execute linked event
functions. To reduce this time, edge detection can be enabled/disabled individually for each channel. To optimize
system load and I/O jitter, it is important to only enable edge detection where it is actually needed.

Information:
Edge detection can also be used for channels that are configured as outputs.

Event frequency limitation

To stabilize the system, there is a mechanism that limits the number of events created through edge recognition.
At least one idle event must occur between two edge events for the same edge.
The "CfO_FallingDisProtection" and "CfO_RisingDisProtection" registers can be used to disable this limitation for
each edge, and then an event will be generated for every edge. However, this can cause a system overload, i.e.
I/O operation can fail for up to 100 ms before the module changes to the reset state.

Generate event on falling edge

Name:
CfO_EdgeDetectFalling
This register defines whether an event is generated on a falling edge.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Channel 1 0 No event generated on falling edge.
1 Events 4096 and 4128 are generated on falling edge.
... ...
3 Channel 4 0 No event generated on falling edge.
1 Events 4099 and 4131 are generated on falling edge.
4-7 Reserved -

Generate event on rising edge

Name:
CfO_EdgeDetectRising
This register defines whether an event is generated on a rising edge.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Channel 1 0 No event generated on rising edge.
1 Events 4112 and 4128 are generated on rising edge.
... ...
3 Channel 4 0 No event generated on rising edge.
1 Events 4115 and 4131 are generated on rising edge.
4-7 Reserved -

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Enable limit for falling edges

Name:
CfO_FallingDisProtection
This register can be used to enable/disable the event frequency limit for falling edges on the respective channel.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Channel 1 0 Event frequency limit enabled.
1 Event frequency limit disabled.
... ...
3 Channel 4 0 Event frequency limit enabled.
1 Event frequency limit disabled.
4-7 Reserved -

Enable limit for rising edges

Name:
CfO_RisingDisProtection
This register can be used to enable/disable the event frequency limit for rising edges on the respective channel.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Channel 1 0 Event frequency limit enabled.
1 Event frequency limit disabled.
... ...
3 Channel 4 0 Event frequency limit enabled.
1 Event frequency limit disabled.
4-7 Reserved -

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4.11.14.12.5.3 Direct input function

The module features a direct input function.

This event function is based on comparator functionality. If the event configured in the "CfO_DIREKTIOevent0IDwr"
register occurs, the event function compares the status of all Direct I/O channels enabled in the
"CfO_EvCompMask" register to a status defined in the "CfO_DIREKTIOeventcompState" register. The event that
is generated depends on the results of this comparison.
• If the respective bits are the same, then event number 513 is generated
• If the respective bits are different, then event number 512 is generated

Configure event ID for input function

Name:
CfO_DIREKTIOevent0IDwr
This register holds the event ID generated by the direct input function. For a list of all possible event IDs, see
4.11.14.12.5.1 "List of event IDs"
Data type Value Information
INT 192 to 7,233 ID of event function

Configure the mode of the input function

Name:
CfO_DIREKTIOevent0mode
The mode in which the direct input function operates can be set in this register.
Comparator functions can be operated in 4 different modes. For a description, see "Comparator modes".
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Comparator mode 0 Off
1 Single
2 State change
3 Continuous
2-7 Reserved -

Comparator status for comparator mask

Name:
CfO_DIREKTIOevent0compState
This register contains the status bits that are compared with the bits specified in the "CfO_Ev0CompMask" register,
which contain the I/O input status, when an event is received.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Comparator status of channel 1 0 or 1
... ...
3 Comparator status of channel 4 0 or 1
4-7 Reserved -

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Configure the comparator mask for the input function

Name:
CfO_Ev0CompMask
If a bit is set, then the input status of the respective channel is compared with that bit in the
"CfO_DIREKTIOeventcompState" register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Channel 1 0 Do not compare bit
1 Compare bit in register
... ...
3 Channel 4 0 Do not compare bit
1 Compare bit in register
4-7 Reserved 0

4.11.14.12.5.4 Direct output functions

The module has 2 of these event functions

The effect of executing this event function is similar to writing to the 4.11.14.12.4.5 "DigitalOutput02 and 04" reg-
isters. When this event function is triggered, however, the changed output states are passed on to the hardware
immediately, regardless of the X2X cycle.
When this event function is used, the masks of the respective outputs (see 4.11.14.12.4.2 "CfO_OutClearMask"
and 4.11.14.12.4.3 "CfO_OutSetMask" registers) must be set to 1. Otherwise the output status would constantly
be overwritten by the values in the 4.11.14.12.4.5 "DigitalOutput02 and 04" registers.

Configure event ID for output function

Name:
CfO_DIREKTIOevent0IDwr to CfO_DIREKTIOevent1IDwr
These registers hold the event IDs that trigger the direct output function. For a list of all possible event IDs, see
4.11.14.12.5.1 "List of event IDs"
Data type Value Information
INT 192 to 7,233 ID of event function

Configure channels for resetting

Name:
CfO_DIREKTIOoutclearmask0 to CfO_DIREKTIOoutclearmask1
Writing "1" to the bit position that corresponds to a channel resets the output if the output event function is being
executed. This corresponds to writing "0" to the 4.11.14.12.4.5 "DigitalOutput 02 and 04" registers.
The bit that corresponds to channels that should be reset should be set to "1" in the 4.11.14.12.4.2
"CfO_OutClearMask" register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Reserved -
1 Channel 2 0 Reset channel 2
1 Do not reset channel 2
2 Reserved -
3 Channel 4 0 Reset channel 4
1 Do not reset channel 4
4-7 Reserved -

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Configure channels for setting

Name:
CfO_DIREKTIOoutsetmask0 to CfO_DIREKTIOoutsetmask1
Writing "1" to the bit position that corresponds to a channel sets the output if the output event function is being
executed. This corresponds to writing "1" to the 4.11.14.12.4.5 "DigitalOutput 02 and 04" registers.
The bit that corresponds to channels that should be reset should be set to "1" in the 4.11.14.12.4.3
"CfO_OutSetMask" register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Reserved -
1 Channel 2 0 Set channel 2
1 Do not set channel 2
2 Reserved -
3 Channel 4 0 Set channel 4
1 Do not set channel 4
4 Reserved -

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4.11.14.12.6 Counters and encoders

The module has 2 internal counter functions, each with 2 event counter registers. Each of these 2 counters is
permanently assigned to 2 physical inputs. This assignment cannot be changed.
The counter registers perform different functions based on how the event functions are connected. The counter
registers can be configured in the following ways:
• ABR counter
• AB counter
• Up/down counters
• Event counters
Different names are used for them in Automation Studio and in the register description to improve clarity.
Channel Counter function Counter register Name in AS

1 1 1 ABEncoder01
ABREncoder01
Counter01
EventCounter01
2 2 EventCounter02
3 2 1 ABEncoder02
Counter02
EventCounter03
4 2 EventCounter04

4.11.14.12.6.1 Counter value calculation

There are 3 steps for calculating the state of any counter function
1. The counter value is based on the 2 absolute value counters "abs1" and "abs2". They are only used internally in
the module and cannot be read. Depending on the mode, these registers show the respective physical input signals.
Mode
Edge counters AB encoders Up/down counter
abs1 Edges of counter channel 1 Increments in positive direction Counter channel 2 = 0:
Edges of counter channel 1
in up direction
abs2 Edges of counter channel 2 Increments in negative direction Counter channel 2 = 1
Edges of counter channel 1
in down direction

2. From the absolute value registers "abs1" and "abs2", 2 more counters are formed: "counter 1" and "counter 2".
These are only used internally in the module and cannot be read. The following values are used for the calculation:
• Absolute value registers "abs1" and "abs2"
• SW_reference_counter 1 and 2: This reference value can be defined by the "CfO_CounterPresetValue"
register to allow referencing <> 0.
• HW_reference_counter 1 and 2: In the "CfO_CounterEventMode" register, you can configure whether
latched values should be copied to these registers when counter events occur.
counter1 = abs1 + SW_reference_counter1 - HW_reference_counter1
counter2 = abs2 + SW_reference_counter2 - HW_reference_counter2
3. The counter registers contain the sum of the two internal counters "counter 1" and "counter 2". The
"CfO_CounterConfigReg" register allows you to define a sign for each "counter" register and define whether or
not it should be used.
Counter register = counter1 + counter2

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4.11.14.12.6.2 Sample configurations

All of the settings available in Automation Studio for AB encoders, ABR encoders, up/down counters and event
counters are based on the two counter functions.
The following configuration examples show the values with which Automation Studio initializes the module registers
in order to implement these functions.

I/O configuration - AB encoder

The following table shows how the module's various event functions can be linked in order to configure an AB
encoder.
[x] stands for the respective counter function, either 1 or 2
Register Value Comment
For the function
CfO_Counter[x]config 0x01 Mode = Up/down counter
CfO_Counter[x]configReg0 0x0D Configure the calculation of the internal "counter1" and "counter2" registers
(see 4.11.14.12.6.1 "Counter value calculation" and "Examples of calculation
configurations")
For the latch
CfO_Counter[x]event0config 0x000D Configuration of the calculation of the first value used for the latch
CfO_Counter[x]event0mode 0x03 Mode of the first counter event function - Continuous
CfO_Counter[x]event0IDwr (any) Number of the event that should trigger Latch 1 ("Latch 01 - Channel" in the AS
I/O configuration).
CfO_Counter[x]event1config 0x0D Configuration of the calculation of the second value used for the latch
CfO_Counter[x]event1mode 0x03 Mode of the second counter event function - Continuous
CfO_Counter[x]event1IDwr (any) Number of the event that should trigger Latch 2
For the comparator
CfO_Counter1event1IDwr 0x00D0 Event number of Timer 1 (50 μs)

Information:
The latch and comparator must not have the same event number!

CfO_Counter1event1config 0x900D or 0xA00D Configuration of the comparator for the second counter event
CfO_Counter1event1mode 0x03 Mode of the second counter event function - Continuous
CfO_DIREKTIOoutevent0IDwr 0x0861 TRUE event output of the second counter to trigger the direct output function
(set outputs).
CfO_DIREKTIOoutsetmask0 0x08, 0x20, 0x80 Outputs that should be set when comparator condition = TRUE
CfO_DIREKTIOoutevent1IDwr 0x0860 FALSE event output of the second counter to trigger the direct output function
(reset outputs).
CfO_DIREKTIOoutclearmask1 0x08, 0x20, 0x80 Outputs that should be reset when comparator condition = FALSE

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I/O configuration - ABR encoder

The following table shows how the module's various event functions can be linked in order to configure an ABR
encoder.
Register Value Comment
For the function
CfO_Counter1PresetValue1 (any) Desired offset value for referencing
CfO_Counter1event0IDwr 0x0201 Link between the first counter event and the "direct input" comparator condition
TRUE
CfO_Counter1config 0x01 Mode = AB encoder
CfO_Counter1configReg0 0x0D Configure the calculation of the internal "counter1" and "counter2" registers
(see 4.11.14.12.6.1 "Counter value calculation" and "Examples of calculation
configurations")
CfO_DIREKTIOevent0IDwr 0x1002 or 0x1012 Selection of the desired input edge as trigger for the ABR encoder function
CfO_Counter1event0config 0x0000 Configuration of the first counter event (for referencing)
CfO_DIREKTIOevent0mode 0x03 Mode of the "direct input function" - Continuous
CfO_DIREKTIOevent0compState 0x00 or 0x08 Comparator status for the "direct input function"
CfO_Ev0CompMask 0x08 Comparator mask for the "direct input function"
For the latch
CfO_Counter1event0config 0x000D Configuration of the calculation of the value used for the latch
CfO_Counter1event0mode 0x03 Mode of the first counter event function - Continuous
CfO_Counter1event0IDwr (any) Number of the event that should trigger the latch
For the comparator
CfO_Counter1event1IDwr 0x00D0 Event number of Timer 1 (50 μs)

Information:
The latch and comparator must not have the same event number!

CfO_Counter1event1config 0x900D or 0xA00D Configuration of the comparator for the second counter event
CfO_Counter1event1mode 0x03 Mode of the second counter event function - Continuous
CfO_DIREKTIOoutevent0IDwr 0x0861 TRUE event output of the second counter to trigger the direct output function
(set outputs).
CfO_DIREKTIOoutsetmask0 0x08, 0x20, 0x80 Outputs that should be set when comparator condition = TRUE
CfO_DIREKTIOoutevent1IDwr 0x0860 FALSE event output of the second counter to trigger the direct output function
(reset outputs).
CfO_DIREKTIOoutclearmask1 0x08, 0x20, 0x80 Outputs that should be reset when comparator condition = FALSE

I/O configuration - Up/down counter

The following table shows how the module's various event functions can be linked in order to configure an up/
down counter.
[x] stands for the respective counter function, either 1 or 2
Register Value Comment
For the function
CfO_Counter[x]config 0x03 Counter mode = Up/down counter
CfO_Counter[x]configReg0 0x0D, 0x07 Configure the calculation of the internal "counter1" and "counter2" registers
(see 4.11.14.12.6.1 "Counter value calculation" and "Examples of calculation
configurations")
For the latch
CfO_Counter[x]event0config 0x0D, 0x07 Configuration of the calculation of the first value used for the latch
CfO_Counter[x]event0mode 0x03 Mode of the first counter function - Continuous
CfO_Counter[x]event0IDwr (any) Number of the event that should trigger Latch 1
CfO_Counter[x]event1config 0x0D, 0x07 Configuration of the calculation of the second value used for the latch
CfO_Counter[x]event1mode 0x03 Mode of the second counter function - Continuous
CfO_Counter[x]event1IDwr (any) Number of the event that should trigger Latch 2
For the comparator
CfO_Counter1event1IDwr 0x00D0 Event number of Timer 1 (50 μs)

Information:
The latch and comparator must not have the same event number!

CfO_Counter1event1config 0x900D, 0xA00D or 0x9007, 0xA007 Configuration of the comparator for the second counter event
CfO_Counter1event1mode 0x03 Mode of the second counter event function - Continuous
CfO_DIREKTIOoutevent0IDwr 0x0861 TRUE event output of the second counter to trigger the direct output function
(set outputs).
CfO_DIREKTIOoutsetmask0 0x08, 0x20, 0x80 Outputs that should be set when comparator condition = TRUE
CfO_DIREKTIOoutevent1IDwr 0x0860 FALSE event output of the second counter to trigger the direct output function
(reset outputs).
CfO_DIREKTIOoutclearmask1 0x08, 0x20, 0x80 Outputs that should be reset when comparator condition = FALSE

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I/O configuration - Event counter

The following table shows how the module's various event functions can be linked in order to configure an event
counter.
[x] stands for the respective counter function, either 1 or 2
Register Value Comment
For event counters on channels 1 and 3
CfO_Counter[x]configReg0 0x01 or 0x03 Configure the calculation of the internal "counter1" and "counter2" registers
(see 4.11.14.12.6.1 "Counter value calculation" and "Examples of calculation
configurations")
CfO_Counter[x]event0mode 0x43 Mode of the first counter event function and referencing configuration
CfO_Counter[x]event0IDwr (any) Number of the event that should trigger referencing
For event counters on channels 2 and 4
CfO_Counter[x]configReg1 0x04 or 0x08 Configure the calculation of the internal "counter1" and "counter2" registers
(see 4.11.14.12.6.1 "Counter value calculation" and "Examples of calculation
configurations")
CfO_Counter[x]event1mode 0x83 Mode of the second counter event function and referencing configuration
CfO_Counter[x]event1IDwr (any) Number of the event that should trigger referencing

4.11.14.12.6.3 General event functions

Each of the 2 counter functions has 2 counter event functions. These consist of:
• Event ID that triggers the counter event function
• A window comparator
• Latch register for saving the counter value
When the counter event function is complete, a combined event ID in the range 2112 to 2401 (see 4.11.14.12.5.1
"List of event IDs") is sent.
Each counter event function also has the option to copy the current counter value to the "HW reference counter"
when an event occurs (see 4.11.14.12.6.1 "Counter value calculation").
Event input
E

True event False event

Comparator window
Logic

Latch True

CfO_Counter(x)event(y) False CfO_Counter(x)event(y) False

mode.Bit6 = 1 ? mode.Bit4 = 1 ?

True True
Hardware reference Hardware reference
Counter 1 = abs 1 Counter 1 = abs 1

CfO_Counter(x)event(y) False CfO_Counter(x)event(y) False

mode.Bit7 = 1 ? mode.Bit5 = 1 ?

True True
Hardware reference Hardware reference
Counter 2 = abs 2 Counter 2 = abs 2

E E
Event output Event output
True False

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Configure counter mode

Name:
Counter function 1: CfO_Counter1config
Counter function 2: CfO_Counter2config
These registers are used to configure the mode of the counter function. Each counter function can be operated
in 3 different modes.
Counter function mode
Edge counters AB encoder Up/down counter
Counter channel 11) Counting pulses, edge counter 1 A Metering pulses
Counter channel 21) Counting pulses, edge counter 2 B Counting direction (0 =
positive, 1 = negative)
Counter register 1 Counter value 1 Position Counter value
Counter register 2 Counter value 2

1) Corresponds to the physical channels of the counter functions. See 4.11.14.7.1 "Description of channel assignments".

Data type Value

USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Counter mode 00 Edge counters
01 AB encoder
11 Up/down counter
2-7 Reserved -

Configure calculation of internal counters

Name:
Counter function 1: CfO_Counter1configReg0 to CfO_Counter2configReg0
Counter function 2: CfO_Counter1configReg1 to CfO_Counter2configReg1
The calculation of the internal "counter1" and "counter2" registers can be configured in these registers. For infor-
mation on using these internal registers, see 4.11.14.12.6.1 "Counter value calculation".
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 counter 1 - use 0 0 is added instead of "counter 1"
1 "counter 1" is used for addition
1 counter 1 - sign 0 The sign of the "counter 1" register is not changed for addition
1 The sign of the "counter 1" register is reversed for addition
2 counter 2 - use 0 0 is added instead of "counter 2"
1 "counter 2" is used for addition
3 counter 2 - sign 0 The sign of the "counter 2" register is not changed for addition
1 The sign of the "counter 2" register is reversed for addition
4-7 Reserved -

Examples of calculation configurations

0b00000001 = 0x01 Only the "counter1 - use" bit is set, entering the contents of the "counter" (edge of counter event channel 1)
directly in the counter register.
0b00000011 = 0x03 "counter 1 - use" and "counter1 - sign" bits are set. The sign is changed so that the counter register counts in
the negative direction.
0b00001101 = 0x0d Edges on counter input channel 1 increase the value in the counter register. Edges on counter input channel 2
decrease the value in the counter register. This value is the best setting for the modes "AB encoder" and "Up/
down counter".

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Offset value for referencing

Name:
Counter function 1: CfO_Counter1PresetValue1 to CfO_Counter2PresetValue1
Counter function 1: CfO_Counter1PresetValue1_32Bit to CfO_Counter2PresetValue1_32Bit
Counter function 2: CfO_Counter1PresetValue2 to CfO_Counter1PresetValue2
Counter function 2: CfO_Counter1PresetValue2_32Bit to CfO_Counter1PresetValue2_32Bit
"Preset value" in the AS I/O configuration.
These registers can be used to define an offset value for referencing. This value is copied to the internal
SW_reference_counter register of the respective counter register.
Data type Value
INT -32,768 to 32,767
DINT -2,147,483,648 to 2,147,483,647

Counter register

Name:
Different names are used for these 4 registers depending on their function.
These 4 registers show the results of the counter value calculation for the respective register. Depending on the
function, this corresponds to either the encoder position or the counter value.
For information on the relationship between physical channels and counter registers, see 4.11.14.12.6 "Counters
and encoders" and 4.11.14.7.1 "Description of channel assignments"
Counter function 1
Counter register Function Name
1 AB encoders ABEncoder01
ABR encoders ABREncoder01
Up/down counters Counter01
Event counters EventCounter01
2 Event counters EventCounter02

Counter function 2
Counter register Function Name
1 AB encoders ABEncoder02
Up/down counters Counter02
Event counters EventCounter03
2 Event counters EventCounter04

Data type Value Information

INT -32,768 to 32,767 Encoder position or counter value
DINT1) -2,147,483,648 Encoder position or counter value
to 2,147,483,647

1) Only in function model 1

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Status of the ABR encoder

Name:
StatusABR01
The referencing status of the ABR encoder is shown in this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Reserved 0
2 Bit is always 1 after the first reference pulse. 0 No reference pulses have occurred since the start of referenc-
ing.
1 The first reference pulse has occurred.
3 State change when referencing is complete 0 or 1
4 Bit is always 1 after the first reference pulse. 0 No reference pulses have occurred since the start of referenc-
ing.
1 The first reference pulse has occurred.
5-7 Continuous counter xxx Increased with each reference pulse

Examples of possible values

0b00000000 = 0x00 Referencing OFF or homing procedure already active
0b00111100 = 0x3C First reference complete, reference value applied in the "ABREncoder0" register
0bxxx11100 = 0xxB Bits 5 to 7 are changed with each reference pulse
0bxxx1x100 = 0xxx Bits changed continuously with the setting continuous referencing. With every reference pulse, the reference
value is applied to the "ABREncoder0" register

Configure ABR referencing mode

Name:
ReferenceModeABR01
The bits in this register are used to configure the reaction to the configured reference pulse.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Sets the referencing mode 00 Referencing OFF
01 Single shot referencing
10 Reserved
11 Continuous referencing
2-5 Reserved -
6-7 Reserved 11 Must always be 11!

This results in the following values:

0b00000000 = 0x00 Referencing OFF
0b11000001 = 0xC1 Single shot referencing → When starting over after the referencing process is complete, the value 0x00 must
be written to start again. Wait until the "StatusABR" register also takes on the value 0x00, then the value 0xC1
can be written again.
0b11000011 = 0xC3 Continuous referencing → Referencing takes place automatically with every reference pulse

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4.11.14.12.6.4 Comparator functions

The ABR and AB encoders and the up/down counter have a comparator function. It always works the same and
is described here globally for all three.
The comparators are implemented in software form. They do not work actively but rather passively, i.e. the com-
parison is only carried out when an event is received. The event received is forwarded along the TRUE or FALSE
branch depending on the status of the comparator condition. An event function like this generally also offers a latch
for the TRUE and FALSE branch to save the value used for the comparator at the time of the event.

Comparator modes

Comparator functions can be operated in 4 different modes.

• Off
Events are ignored.
• Single
The event function is executed once and then disables itself automatically. To re-enable it, the "event
function mode" must be changed, preferably to "off" and then to the desired mode. This setting allows a
hardware latch to be simulated.
• State change
The event function only responds when the comparator status has changed, i.e. from false to true (or vice
versa). Only the first event for each status is processed, e.g. the first "true" of a sequence of events with the
comparator condition "true". After the event function is enabled, the first incoming event is used to determine
the starting status and therefore not forwarded. This setting allows a hardware comparator to be simulated.
• Continuous
Each incoming event is forwarded to the true or false branch depending on the comparator condition. This
setting allows event filters to be created.

Configure event ID for comparator

Name:
Counter function 1: CfO_Counter1event0IDwr to CfO_Counter1event1IDwr
Counter function 2: CfO_Counter2event0IDwr to CfO_Counter2event1IDwr
This register holds the event ID that should trigger the counter event function. For a list of all possible event IDs,
see 4.11.14.12.5.1 "List of event IDs"
Data type Value Information
INT 192 to 7,233 ID of counter event function

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Configure calculation of comparator

Name:
Counter function 1: CfO_Counter1event0config to CfO_Counter1event1config
Counter function 2: CfO_Counter2event0config to CfO_Counter2event1config
These registers are used to configure the counter event function for the respective counter function.
Bits 0 to 3 configure the calculation of the comparison or to latch the value. This calculation is similar to the calcu-
lation of the counter register (see 4.11.14.12.6.1 "Counter value calculation")
Bits 8 to 13 can be used to limit the number of bits used for the comparison. A mask is calculated as 2n - 1 and
linked with an "AND" operation. This makes it possible to generate a comparator pulse every 2n increments.
Data type Value
UINT See bit structure.

Bit structure:
Bit Description Value Information
0 counter 1 - use 0 0 is added instead of "counter 1"
1 "counter 1" is used for addition
1 counter 1 - sign 0 The sign of the "counter 1" register is not changed for addition
1 The sign of the "counter 1" register is reversed for addition
2 counter 2 - use 0 0 is added instead of "counter 2"
1 "counter 2" is used for addition
3 counter 1 - sign 0 The sign of the "counter 2" register is not changed for addition
1 The sign of the "counter 2" register is reversed for addition
4-7 Reserved -
8 - 13 Number of bits for comparator mask x The mask value is calculated as 2n-1, where n is value set in
these bits. Default: 0
14 Reserved -
15 Margin comparator mode 0 MarginComparator01 >= (Current position - OriginCompara-
tor01)
1 MarginComparator01 > (Current position - OriginComparator01)

Configure mode and latching of comparator function

Name:
Counter function 1: CfO_Counter1event0mode to CfO_Counter1event1mode
Counter function 2: CfO_Counter2event0mode to CfO_Counter2event1mode
In these registers you can set the mode for the comparator function and optional copying of the latched registers.
Comparator functions can be operated in 4 different modes. For a description, see "Comparator modes".
Bits 4 to 7 can be used to define hardware referencing actions.
Based on these bits, the values of the internal absolute value counters "abs1" and "abs2" can be copied to the re-
spective "HW_reference_counter" register at every counter event (see 4.11.14.12.6.1 "Counter value calculation").
This function can be used to reference the counter values directly in the hardware.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Comparator mode 0 Off
1 Single
2 State change
3 Continuous
2-3 Reserved -
4 Copy abs1 counter value 0 No action
1 When event is FALSE → hardware reference counter 1 = abs1
5 Copy abs2 counter value 0 No action
1 When event is FALSE → hardware reference counter 2 = abs2
6 Copy abs1 counter value 0 No action
1 When event is TRUE → hardware reference counter 1 = abs1
7 Copy abs2 counter value 0 No action
1 When event is TRUE → hardware reference counter 2 = abs2

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Comparator origin

Name:
OriginComparator01
This register is available for the AB and ABR encoders and the up/down counters.
It defines the position value at which the respective configured comparator output channel is set.
Data type Value Information
INT -32,768 to 32,767 Comparator window origin, 16-bit
DINT -2,147,483,648 Comparator window origin, 32-bit
to 2,147,483,647

Width of the comparator

Name:
MarginComparator01
This register is available for the AB and ABR encoders and the up/down counters.
It defines the width of the comparator window in the positive direction.
Data type Value Information
INT -32,768 to 32,767 Width of comparator window, 16-bit
DINT -2,147,483,648 to 2,147,483,647 Width of comparator window, 32-bit

Read latch position or counter value

Name:
Different names are used for these 4 registers depending on their function.
If the comparator returns "TRUE", then the current counter value is latched and copied to these registers. The
calculation of the comparator value used for the latch can be configured in the "Configure calculation of comparator"
register.
Counter function 1
Event function Function Name
1 AB encoders Latch01AB01
Up/down counters Latch01Counter01
2 ABR encoders Latch01ABR01
AB encoders Latch02AB01
Up/down counters Latch02Counter01

Counter function 2
Event function Function Name
1 AB encoders Latch01AB02
Up/down counters Latch01Counter02
Event counters Latch02AB02
2 Event counters Latch02Counter02

Data type Value Information

INT -32,768 to 32,767 Latched encoder position or counter value
DINT1) -2,147,483,648 Latched encoder position or counter value
to 2,147,483,647

1) Only in function model 1

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4.11.14.12.7 SSI encoder interface

The module has 1 SSI encoders available, supported directly in the hardware. Two 24 V output channels are set
for the SSI encoder and cannot be changed. (See also 4.11.14.7.1 "Description of channel assignments")
When using the SSI encoder, the corresponding clock channel can be configured in the 4.11.14.12.4.1
"CfO_CFGchannel" register as "Channel-specific" and "Push/Pull".
SSI encoders Channel number
Data channel 1
Clock channel 2

4.11.14.12.7.1 SSI event functions

The SSI encoder consists of an event function and an event input. The SSI cycle is started when an event is
received on this input.

Information:
The SSI event function is not linked to an event by default, i.e. SSI functions are disabled.
Two events are sent from the SSI encoder interface..
• An "SSI valid" event is triggered immediately after the end of the SSI cycle if a new counter value is available.
• The "SSI ready" event then shows when the monoflop time has expired (tp in SSI encoder timing diagram).
This is the earliest that the next SSI cycle can be started.
SSI encoder - Timing diagram
SSI cycle

Clock 1 2 3 4 5 6 n

Data

MSB LSB MSB

0
tp

SSI valid
SSI start event SSI ready

Configure event ID for SSI

Name:
CfO_SSI1eventIDwr
This register holds the event ID that should start the SSI cycle. For a list of all possible event IDs, see 4.11.14.12.5.1
"List of event IDs"
Normally this register is set to network event 225 "AOSISOP"- This ensures that the new encoder position is
available at the next "I/O → Synchronous Frame" transfer. Check the SSI transfer time and the X2X cycle time,
because the SSI cycle must be completed within this time.
Data type Value Information
INT 192 to 7,233 ID of event function

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Configure SSI

Name:
CfO_SSI1cfg
This configuration register is used to set the coding, the clock rate and the number of bits. Default = 0. This must
be set once using an acyclic write command.
Data type Value
UINT See bit structure.

Bit structure:
Bit Name Value Information
0-5 SSI value valid bits x
6-7 Clock rate 00 1 MHz
01 500 kHz
10 250 kHz
11 125 kHz
8 - 13 SSI number of bits x Number of bits including leading zeros
14 Reserved 0
15 Keying 0 Binary coding
1 Gray coding

SSI advanced configuration

Name:
ConfigAdvanced
This configuration register is used to set the coding, the clock rate, the number of bits and the monostable multivi-
brator settings. Default = 0. This must be set once using an acyclic write command.
It only differs from "CfO_SSI1cfg" by data length and additional monostable multivibrator testing.
Data type Value
UDINT See bit structure.

Bit structure:
Bit Name Value Information
0-5 SSI value valid bits x
6-7 Clock rate 00 1 MHz
01 500 kHz
10 250 kHz
11 125 kHz
8 - 13 SSI number of bits x Number of bits including leading zeros
14 Reserved 0
15 Keying 0 Binary coding
1 Gray coding
16 - 17 Monostable multivibrator check 00 Check OFF, no additional clock bit
01 Check set to High level
10 Check set to Low level
11 Level is clocked but ignored
18 - 31 Reserved 0

Enable SSI event function

Name:
CfO_SSI1control
The two SSI encoder events can be enabled/disabled using this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Event: SSI valid 0 Not sent
1 Sent
1 Event: SSI ready 0 Not sent
1 Sent
2-7 Reserved -

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Read SSI position

Name:
SSIEncoder01
The last transferred SSI position can be read out from this register. The SSI encoder value is displayed as a 32-
bit position value. This position value is generated synchronously with the X2X cycle.
Data type Value Information
UDINT 0 to 4,294,967,295 Last SSI position transferred

4.11.14.12.7.2 SSI comparator condition

The module has an assigned comparator function for the SSI function. These consist of:
• Event ID that triggers the comparator function
• The window comparator
• Latch register for saving the counter value
When the comparator function is complete, event ID 7232 or 7233 (see 4.11.14.12.5.1 "List of event IDs") is sent.

Configure event ID for SSI comparator

Name:
CfO_SSI1event0IDwr
This register holds the event ID that should start the SSI comparator function. For a list of all possible event IDs,
see 4.11.14.12.5.1 "List of event IDs"
Data type Value Information
INT 192 to 7,233 ID of comparator function

Configure the mode of the SSI comparator function

Name:
CfO_SSI1event0mode
This register can be used to configure the mode of the comparator function.
Comparator functions can be operated in 4 different modes. For a description, see "Comparator modes".
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Comparator mode 0 Off
1 Single
2 State change
3 Continuous
2-7 Reserved -

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Configure calculation of SSI comparator

Name:
CfO_SSI1event0config
The calculation of the position value used for the comparator can be configured in this register.
The window comparator condition is calculated as follows:
counter_window_value = ssi_counter & (2^ssi_data_bits - 1)
diff = counter_window_value – origin_comparator
if ((diff & (2^(comparator_mask)-1)) <= margin_comparator)
condition = True;
else
condition = False;
Data type Value
UINT See bit structure.

Bit structure:
Bit Description Value Information
0-5 SSI data bits x Number of data bits used for masking
6-7 Reserved -
8 - 13 Comparator mask x The mask value is calculated from 2n-1, where n is the value
configured in SSI data bits. Default: 0
14 Comparator mode 0 MarginComparator >= SSI position - OriginComparator
1 MarginComparator > SSI position - OriginComparator

Origin of the SSI comparator

Name:
OriginComparator01_SSI
This register contains the origin of the window comparator.
Data type Value Information
UDINT 0 to 4,294,967,295 Origin of the window comparator.

Width of the SSI comparator

Name:
MarginComparator01_SSI
This register provides the width of the window comparator.
Data type Value Information
UDINT 0 to 4,294,967,295 Width of the SSI window comparator

Read SSI latch position

Name:
Latch01SSI01
If the SSI window comparator returns "True", then the current SSI position is latched and saved in this register.
Data type Value Information
UDINT 0 to 4,294,967,295 Latched SSI position

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4.11.14.12.8 PWM - Pulse width modulation

The module has 2 PWM functions available, supported directly by the hardware. A 24 V output channel is set for
each PWM encoder and cannot be changed. (See also 4.11.14.7.1 "Description of channel assignments")
When using the PWM function, the corresponding channel can be configured in the 4.11.14.12.4.1
"CfO_CFGchannel" register as "Channel-specific".
PWM function Channel
PWM1 2
PWM2 4

4.11.14.12.8.1 Configure PWM prescaler

Name:
CfO_PWM0prescaler to CfO_PWM1prescaler
The length of the PWM cycle is configured using this register. The base is a 48 MHz clock, which can be changed
(divided) using the setting in this register. One PWM cycle consists of 1,000 of the resulting clocks after they have
been divided. The period length of the PWM cycle is calculated as follows:
prescale
PWM_cycle = 1000 [s]
48,000,000
Data type Value Information
UINT 2 to 65,535 Prescaler for PWM cycle

4.11.14.12.8.2 Output PWM values

Name:
PWMOutput02 and PWMOutput04
In this register, a configuration is made for the percentage of the PWM cycle (in 1/10 % steps) that the PWM output
is logical 1, i.e. ON.
Data type Value Information
UINT 0 to 1,000 PWM output always off
2 to 999 Turn on time in 1/10% steps
1,000 PWM output always on

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4.11.14.12.9 Time measurement function

The module has a time measurement function for each I/O channel. It can be configured separately for rising and
falling edges on each channel.
A starting edge can be configured for each time measurement function. When a configured starting edge occurs,
the value of the internal timer is saved in a FIFO. This FIFO holds up to 16 elements. When the actual trigger edge
occurs, the difference in time between the starting edge and the triggered edge is copied to the respective register.
Bits 8 to 11 "Previous start edge" of the 4.11.14.12.9.2 "CfO_EdgeTimeFallingMode" and 4.11.14.12.9.3
"CfO_EdgeTimeRisingMode" registers can be used to define which detected starting edge from the FIFO should
be used to calculate the difference. Additionally, when the trigger edge occurs, the counter clocked internally us-
ing bits 12 to 15 "Time measurement resolution are copied to the 4.11.14.12.9.10 "TimeStampFallingCH" and
4.11.14.12.9.11 "TimeStampRisingCH" registers.

Information:
The time measurement function is an extension of edge detection, so all of the channels used must
be configured there.

4.11.14.12.9.1 Enable time measurement function

Name:
CfO_EdgeTimeglobalenable
This register enables/disables the time measurement function for the entire module.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Time measurement function 0 Disabled for entire module
1 Enabled for entire module
1-7 Reserved -

4.11.14.12.9.2 Configure time measurement function for the falling edge

Name:
CfO_EdgeTimeFallingMode01 to CfO_EdgeTimeFallingMode04
These registers can be used to configure the time measurement function for the falling edge of the respective
channel.
Data type Value
UINT See bit structure.

Bit structure:
Bit Description Value Information
0-3 Selects the channel for the starting edge 0 Channel 1
...
3 Channel 4
4 Selects the edge for the starting edge 0 The falling edge of the channel configured in bits 0 to 3 serves
as the starting edge.
1 The rising edge of the channel configured in bits 0 to 3 serves
as the starting edge.
5-6 Reserved -
7 Trigger 0 Triggered1)
1 Continuous2)
8 - 11 Previous start edge 0 to 15 The value determines which entry in the starting edge FIFO
should be used to calculate the time difference.
12 - 15 Time measurement resolution 0 8 Mhz
1 4 Mhz
2 2 Mhz
3 1 Mhz
4 500 kHz
5 250 kHz
6 125 kHz
7 625 kHz

1) The time measurement is triggered by the corresponding bit in the 4.11.14.12.9.5 "TriggerRisingCH" register.
2) Time measurement runs continuously and is triggered at every edge.

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4.11.14.12.9.3 Configure time measurement function for the rising edge

Name:
CfO_EdgeTimeRisingMode01 to CfO_EdgeTimeRisingMode04
These registers can be used to configure the time measurement function for the rising edge of the respective
channel.
Data type Value
UINT See bit structure.

Bit structure:
Bit Description Value Information
0-3 Selects the channel for the starting edge 0 Channel 1
...
3 Channel 4
4 Selects the edge for the starting edge 0 The falling edge of the channel configured in bits 0 to 3 serves
as the starting edge.
1 The rising edge of the channel configured in bits 0 to 3 serves
as the starting edge.
5-6 Reserved -
7 Trigger 0 Triggered1)
1 Continuous2)
8 - 11 Previous start edge 0 to 15 The value determines which entry in the starting edge FIFO
should be used to calculate the time difference.
12 - 15 Time measurement resolution 0 8 Mhz
1 4 Mhz
2 2 Mhz
3 1 Mhz
4 500 kHz
5 250 kHz
6 125 kHz
7 625 kHz

1) The time measurement is triggered by the corresponding bit in the 4.11.14.12.9.4 "TriggerRisingCH" register.
2) Time measurement runs continuously and is triggered at every edge.

4.11.14.12.9.4 Trigger falling edge detection

Name:
TriggerFallingCH01 to TriggerFallingCH04
If bit 7 "Trigger" is cleared in the 4.11.14.12.9.2 "CfO_EdgeTimeFallingMode" register, then detection of a falling
edge on the respective input can be triggered using the respective bit in this register. After a bit has been set, the
next falling edge on the corresponding channel is detected.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 TriggerFallingCH01 0 Falling edges on channel 1 are not detected
1 The next falling edge on channel 1 will be detected
... ...
3 TriggerFallingCH04 0 Falling edges on channel 4 are not detected
1 The next falling edge on channel 4 will be detected
4-7 Reserved -

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4.11.14.12.9.5 Trigger rising edge detection

Name:
TriggerRisingCH01 to TriggerRisingCH04
If bit 7 "Trigger" is cleared in the 4.11.14.12.9.3 "CfO_EdgeTimeRisingMode" register, then detection of a rising
edge on the respective input can be triggered using the respective bit in this register. After a bit has been set, the
next rising edge on the corresponding channel is detected.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 TriggerRisingCH01 0 Rising edges on channel 1 are not detected
1 The next rising edge on channel 1 will be detected
... ...
3 TriggerRisingCH04 0 Rising edges on channel 4 are not detected
1 The next rising edge on channel 4 will be detected
4-7 Reserved -

4.11.14.12.9.6 Show first falling trigger edge

Name:
BusyTriggerFallingCH01 to BusyTriggerFallingCH04
If edges are triggered via the bits in the 4.11.14.12.9.4 "TriggerFallingCH" register, then a set bit in this register
indicates that no falling edges have been detected on the respective channel since the corresponding bit was
set in the "TriggerFallingCH" register. If a falling edge occurs on the respective channel, then the corresponding
BusyTriggerFalling bit is cleared.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 BusyTriggerFallingCH01 0 Falling edge detected on channel 1
1 Module waiting for a falling edge on channel 1
... ...
3 BusyTriggerFallingCH04 0 Falling edge detected on channel 4
1 Module waiting for a falling edge on channel 4
4-7 Reserved -

4.11.14.12.9.7 Show first rising trigger edge

Name:
BusyTriggerRisingCH01 to BusyTriggerRisingCH04
If edges are triggered via the bits in the 4.11.14.12.9.5 "TriggerRisingCH" register, then a set bit in this register
indicates that no rising edges have been detected on the respective channel since the corresponding bit was
set in the "TriggerRisingCH" register. If a rising edge occurs on the respective channel, then the corresponding
BusyTriggerRising bit is cleared.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 BusyTriggerRisingCH01 0 Rising edge detected on channel 1
1 Module waiting for a rising edge on channel 1
... ...
3 BusyTriggerRisingCH04 0 Rising edge detected on channel 4
1 Module waiting for a rising edge on channel 4
4-7 Reserved -

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4.11.14.12.9.8 Count falling trigger edges

Name:
CountFallingCH01 to CountFallingCH04
These registers contain cyclic counters that are incremented with every detected falling edge on the respective
channel.
Data type Value Information
USINT 0 to 255 Counter for falling edges

4.11.14.12.9.9 Count rising trigger edges

Name:
CountRisingCH01 to CountRisingCH04
These registers contain cyclic counters that are incremented with every detected rising edge on the respective
channel.
Data type Value Information
USINT 0 to 255 Counter for rising edges

4.11.14.12.9.10 Time stamp of falling edge

Name:
TimeStampFallingCH01 to TimeStampFallingCH04
When a falling edge occurs on the respective channel, the current counter value of the module timer is copied
to these registers.
Data type Value Information
UINT 0 to 65,535 Time stamp for rising edges

4.11.14.12.9.11 Time stamp of the rising edge

Name:
TimeStampRisingCH01 to TimeStampRisingCH04
When a rising edge occurs on the respective channel, the current counter value of the module timer is copied to
these registers.
Data type Value Information
UINT 0 to 65,535 Time stamp for rising edges

4.11.14.12.9.12 Time difference of falling edge

Name:
TimeDiffFallingCH01 to TimeDiffFallingCH04
When a falling edge occurs on the respective channel, the time difference compared to the starting edge configured
in bit 4 of the 4.11.14.12.9.2 "CfO_EdgeTimeFallingMode" register is copied to this register.
Data type Value Information
UINT 0 to 65,535 Time difference from starting edge

4.11.14.12.9.13 Time difference of rising edge

Name:
TimeDiffRisingCH01 to TimeDiffRisingCH04
When a rising edge occurs on the respective channel, the time difference compared to the starting edge configured
in bit 4 of the 4.11.14.12.9.3 "CfO_EdgeTimeRisingMode" register is copied to this register.
Data type Value Information
UINT 0 to 65,535 Time difference from starting edge

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4.11.14.12.10 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
128 μs

4.11.14.12.11 Maximum cycle time

The maximum cycle time defines how far the bus cycle can be increased without internal counter overflows causing
module malfunctions.
Minimum cycle time
16 ms

4.11.14.12.12 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
128 μs

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4.11.15 X20DC2396

4.11.15.1 General information

The module is equipped with two inputs for an ABR incremental encoder with 24 V encoder signal.
• 2 ABR incremental encoder 24 V
• 2 additional inputs e.g. for home enable switch
• 24 VDC and GND for encoder supply

4.11.15.2 Order data

Model number Short description Figure

Counter functions
X20DC2396 X20 digital counter module, 2 ABR incremental encoders, 24 V,
100 kHz input frequency, 4x evaluation
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 251: X20DC2396 - Order data

4.11.15.3 Technical data

Product ID X20DC2396
Brief description
I/O module 2 ABR incremental encoder 24 V
General information
Input voltage 24 VDC -15% / +20%
B&R ID code 0x1BAB
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.5 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Encoder - Bus Yes
Encoder - Encoder No
Reference enable switch - Bus Yes
Reference enable switch - Encoder No
Reference switch - Reference switch No
Type of signal lines Shielded cables must be used for all signal lines.
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Home enable switch
Quantity 2
Nominal voltage 24 VDC
Input filter
Hardware ≤2 μs
Software -
Connection type 3-wire connections
Input circuit Sink
Input current at 24 VDC Approx. 3.3 mA

Table 252: X20DC2396 - Technical data

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Product ID X20DC2396
Input resistance 7.19 kΩ
Isolation voltage between home enable switch and 500 Veff
bus
Switching threshold
Low <5 VDC
High >15 VDC
ABR incremental encoder
Encoder inputs 24 V, asymmetrical
Counter size 16/32-bit
Input frequency Max. 100 kHz
Evaluation 4x
Encoder supply Module-internal, max. 600 mA
Input filter
Hardware ≥2 µs
Software -
Input current at 24 VDC Approx. 1.3 mA
Input resistance 18.4 kΩ
Switching threshold
Low <5 VDC
High >15 VDC
Overload behavior of the encoder supply Short circuit protection, overload protection
Isolation voltage between encoder and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 252: X20DC2396 - Technical data

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4.11.15.4 LED status indicators

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
A1, A2 Green Input state of counter input A1 or A2
B1, B2 Green Input state of counter input B1 or B2
R1, R2 Green Input state of reference pulse R1 or R2
1-2 Green Input state of the corresponding digital input

1) Depending on the configuration, a firmware update can take up to several minutes.

4.11.15.5 Pinout

Shielded cables must be used for all signal lines.

r e
X20 DC 2396
A1 A2
B1 B2
R1 R2
1 2

A1 A2

B1 B2

R1 R2

DI 1 DI 2

Encoder 1 24 V+ Encoder 2 24 V+

GND GND

4.11.15.6 Connection example

DC

A1 A2
Counter 1

Counter 2

B1 B2

R1 R2

+24 VDC +24 VDC

GND GND

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4.11.15.7 Input circuit diagram

Counter inputs

ABR x

VDR
Input status

I/O status

24 V
PTC
Encoder x 24 V LED (green)

GND

GND

Standard inputs

Input x

VDR
Input status

I/O status

Led (green)

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4.11.15.8 Register description

4.11.15.8.1 Function model 0 - Standard and

Function model 1 - Standard with 32-bit encoder counter value

The difference between function model 0 and function model 1 is the size of the data type for some registers.
• Function model 0 uses data type INT
• Function model 1 uses data type DINT (specified in parentheses)
Register Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
Configuration
4104 CfO_EdgeDetectFalling USINT ●
4106 CfO_EdgeDetectRising USINT ●
2064 CfO_PresetABR01_1(_32Bit) (D)INT ●
2068 CfO_PresetABR01_2(_32Bit) (D)INT ●
2576 CfO_PresetABR02_1(_32Bit) (D)INT ●
2580 CfO_PresetABR02_2(_32Bit) (D)INT ●
512 ConfigOutput24 UINT ●
522 ConfigOutput26 USINT ●
520 ConfigOutput27 USINT ●
544 ConfigOutput32 UINT ●
554 ConfigOutput34 USINT ●
552 ConfigOutput35 USINT ●
Communication
2116 ReferenceModeEncoder01 USINT ●
2628 ReferenceModeEncoder02 USINT ●
2080 Encoder01 (D)INT ●
2592 Encoder02 (D)INT ●
264 Input state of digital inputs 1 to 2 USINT ●
DigitalInput01 Bit 3
DigitalInput02 Bit 7
2118 StatusInput01 USINT ●
2630 StatusInput02 USINT ●
40 Status of encoder supply USINT ●
PowerSupply01 Bit 0

4.11.15.8.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Configuration
4104 - CfO_EdgeDetectFalling USINT ●
4106 - CfO_EdgeDetectRising USINT ●
2064 - CfO_PresetABR01_1 INT ●
2068 - CfO_PresetABR01_2 INT ●
2576 - CfO_PresetABR02_1 INT ●
2580 - CfO_PresetABR02_2 INT ●
512 - ConfigOutput24 UINT ●
522 - ConfigOutput26 USINT ●
520 - ConfigOutput27 USINT ●
544 - Constant register "ConfigOutput32" UINT ●
554 - ConfigOutput34 USINT ●
552 - ConfigOutput35 USINT ●
Communication
2116 0 ReferenceModeEncoder01 USINT ●
2628 1 ReferenceModeEncoder02 USINT ●
2080 0 Encoder01 INT ●
2592 4 Encoder02 INT ●
264 2 Input state of digital inputs 1 to 2 USINT ●
DigitalInput01 Bit 3
DigitalInput02 Bit 7
2118 6 StatusInput01 USINT ●
2630 7 StatusInput02 USINT ●
40 3 Status of encoder supply USINT ●
PowerSupply01 Bit 0

1) The offset specifies the position of the register within the CAN object.

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4.11.15.8.3 ABR encoder - Configuration registers

4.11.15.8.3.1 Reference pulse

The following registers must be configured by a single acyclic write with the listed values so that the homing
procedure is completed on the edge of the reference pulse.
The homing procedure can take place on:
• Rising edge
• Falling edge (default configuration)

Constant register "CfO_EdgeDetectFalling"

Name:
CfO_EdgeDetectFalling
Data type Value Filter
USINT 0x00 Configuration value for rising edge
0x04 Encoder 1 - Configuration value for falling edge
0x40 Encoder 2 - Configuration value for falling edge
0x44 Encoders 1 and 2 - Configuration value for falling edge

Constant register "CfO_EdgeDetectRising"

Name:
CfO_EdgeDetectRising
Data type Value Filter
USINT 0x00 Configuration value for falling edge (default 0x00)
0x04 Encoder 1 - Configuration value for rising edge
0x40 Encoder 2 - Configuration value for rising edge
0x44 Encoders 1 and 2 - Configuration value for rising edge

Constant register "ConfigOutput24"

Name:
ConfigOutput24
This register contains the value for ABR encoder 1.
Data type Value Filter
UINT 0x1012 Configuration value for rising edge
0x1002 Configuration value for falling edge

Constant register "ConfigOutput32"

Name:
ConfigOutput32
This register contains the value for ABR encoder 2.
Data type Value Filter
UINT 0x1016 Configuration value for rising edge
0x1006 Configuration value for falling edge

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4.11.15.8.3.2 Setting the home position

Name:
CfO_PresetABR01_1 to CfO_PresetABR01_2
CfO_PresetABR02_1 to CfO_PresetABR02_2
CfO_PresetABR01_1_32Bit to CfO_PresetABR01_2_32Bit
CfO_PresetABR02_1_32Bit to CfO_PresetABR02_2_32Bit (only in function model 1)
It is possible to specify two home positions for each encoder with these registers through a one-off acyclic write, for
example (default = 0). The configured values are applied to the counter values after a completed homing procedure.
Data type Value
INT -32,768 to 32,767
DINT1) -2,147,483,648 to 2,147,483,647

1) Only in function model 1

4.11.15.8.3.3 Homing with reference enable input

Regardless of the referencing mode, it is possible using this register to prevent the home position from being
applied when the corresponding reference input voltage level occurs (see 4.11.15.8.4.2 "Input state of digital inputs
1 to 2": bit 7). The desired setting can be configured by a one-off acyclic write.

Voltage level for reference enable activation - ABR encoder 1

Name:
ConfigOutput26
The voltage level of the digital input 1 to activate reference enable is configured with this register.
Data type Value Filter
USINT 0x00 Reference enable is active at 0 VDC
0x08 Reference enable is active at 24 VDC

Reference enable of the input - ABR encoder 1

Name:
ConfigOutput27
This register can be used to define whether the reference enable is activated.
Data type Value Filter
USINT 0x00 Reference enable input OFF (default)
0x08 Reference enable input activated

Voltage level for reference enable activation - ABR encoder 2

Name:
ConfigOutput34
The voltage level of the digital input 2 to activate reference enable is configured with this register.
Data type Value Filter
USINT 0x00 Reference enable is active at 0 VDC
0x80 Reference enable is active at 24 VDC

Reference enable of the input - ABR encoder 2

Name:
ConfigOutput35
This register can be used to define whether the reference enable is activated.
Data type Value Filter
USINT 0x00 Reference enable input OFF (default)
0x80 Reference enable input activated

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4.11.15.8.4 ABR encoder - Configuration registers

4.11.15.8.4.1 Counter state of the encoders

Name:
Encoder01 to Encoder02
The encoder values are displayed in this register.
Data type Value
INT -32,768 to 32,767
DINT1) -2,147,483,648 to 2,147,483,647

1) Only in function model 1

4.11.15.8.4.2 Input state of digital inputs 1 to 2

Name:
DigitalInput01 to DigitalInput02.
This register displays the input status of the encoders and the digital inputs.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Encoder 1 0 or 1 Input state - Signal A
1 0 or 1 Input state - Signal B
2 0 or 1 Input state of reference pulse
3 DigitalInput01 0 or 1 Input state - Digital input 1
4 Encoder 2 0 or 1 Input state - Signal A
5 0 or 1 Input state - Signal B
6 0 or 1 Input state of reference pulse
7 DigitalInput02 0 or 1 Input state - Digital input 2

4.11.15.8.4.3 Reading the referencing mode

Name:
ReferenceModeEncoder01 to ReferenceModeEncoder02
This register determines the referencing mode.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-1 00 Referencing OFF
01 Single shot referencing
11 Continuous referencing
2-5 0 Bits permanently set = 0
6-7 00 Referencing OFF
11 Bits permanently set = 1

This results in the following values:

Binary Hex Function
00000000 0x00 Referencing OFF
11000001 0xC1 Single shot referencing
For a new start after the completed homing procedure:
• Write value 0x00
• Wait until bit 0 to bit 3 of the StatusInput01 register takes on the value 0. Counter
bits 4 to 7 are not erased
• Switch homing procedure on again
11000011 0xC3 Continuous referencing
Referencing occurs at every reference pulse.

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4.11.15.8.4.4 Status of the homing procedure

Name:
StatusInput01 (for encoder 1) to StatusInput02 (for encoder 2)
This register contains information regarding whether the referencing process is off, active or complete.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Reference pulse without homing1) 0 No reference impulse without homing has occurred yet
1 At least a reference impulse without homing has occurred
1 State change 0 or 1 Changes with each reference pulse without homing
2 Reference pulse with homing1) 0 No homing has occurred yet
1 At least one homing procedure has occurred
3 State change 0 or 1 Changes with each homing procedure that has taken place
4 Reference pulse 0 The last reference pulse didn't bring about a homing procedure
1 The last reference pulse brought about a homing procedure
5-7 Counter x Free-running counter, increased with each reference pulse

1) Always 1 after the first reference pulse that has occurred

Examples of possible values:

Binary Hex Function
0x00000000 0x00 Referencing OFF or homing procedure already active
0x00111100 0x3CE First homing procedure complete Reference value applied in the Encoder01 register
0xxxx11100 0xxB Bits 5 to 7 are changed with each reference pulse
0xxxx1x100 0xxx Continuously changing the bits with the "Continuous referencing" setting. The refer-
ence value is applied to the Encoder01 register on each reference pulse.

4.11.15.8.4.5 Status of encoder supply

Name:
PowerSupply01
This register shows the status of the integrated encoder supply. A faulty encoder power supply is displayed as
a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 PowerSupply01 0 24 VDC encoder power supply OK
1 24 VDC encoder power supply faulty
1-7 Reserved -

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4.11.15.8.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
128 μs

4.11.15.8.6 Maximum cycle time

The maximum cycle time defines how far the bus cycle can be increased without internal counter overflows causing
module malfunctions.
Minimum cycle time
16 ms

4.11.15.8.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
128 μs

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4.11.16 X20DC2398

4.11.16.1 General information

This module is equipped with two inputs for SSI absolute encoders with 24 V encoder signal.
• 2 SSI absolute encoder 24 V
• 2 additional inputs
• 24 VDC and GND for encoder supply

4.11.16.2 Order data

Model number Short description Figure

Counter functions
X20DC2398 X20 digital counter module, 2 SSI absolute encoder, 24 V, 125
kbit/s, 32-bit
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 253: X20DC2398 - Order data

4.11.16.3 Technical data

Product ID X20DC2398
Brief description
I/O module 2 SSI absolute encoder 24 V
General information
Input voltage 24 VDC -15% / +20%
B&R ID code 0x1BAD
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.4 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Encoder - Bus Yes
Encoder - Encoder No
Channel - Bus Yes
Channel - Encoder No
Channel - Channel No
Type of signal lines Shielded cables must be used for all signal lines.
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Quantity 2
Nominal voltage 24 VDC
Input current at 24 VDC Approx. 3.3 mA
Input filter
Hardware ≥2 µs
Software -
Connection type 3-wire connections
Input circuit Sink

Table 254: X20DC2398 - Technical data

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Product ID X20DC2398
Input resistance 7.19 kΩ
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
SSI absolute encoder
Encoder inputs 24 V, asymmetrical
Counter size 32-bit
Max. transfer rate 125 kbit/s
Encoder supply Module-internal, max. 600 mA
Keying Gray/Binary
CLK: Output current Max. 100 mA
DATA: Input resistance 18.4 kΩ
Isolation voltage between encoder and bus 500 Veff
Overload behavior of the encoder supply Short circuit protection, overload protection
Switching threshold
Low <5 VDC
High >15 VDC
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 254: X20DC2398 - Technical data

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4.11.16.4 LED status indicators

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
D1, D2 Green Input state of data signal 1 or 2
1-2 Green Input state of the corresponding digital input

1) Depending on the configuration, a firmware update can take up to several minutes.

4.11.16.5 Pinout

Shielded cables must be used for all signal lines.

r e

X20 DC 2398
D1 D2
1 2

Data 1 Data 2

Clock 1 Clock 2

DI 1 DI 2

Encoder 1 24 V+ Encoder 2 24 V+

GND GND

4.11.16.6 Connection example

DC

Data 1 Data 2
Counter 1

Counter 2

Clock 1 Clock 2

+24 VDC +24 VDC

GND GND

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4.11.16.7 Input circuit diagram

Counter inputs

Data x

VDR
Input status

I/O status

24 V
PTC
Encoder x 24 V LED (green)

GND

GND

Standard inputs

Input x

VDR
Input status

I/O status

Led (green)

4.11.16.8 Output circuit diagram

24 V

Output status Push

PTC
Clock x

VDR
Output status Pull

GND

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4.11.16.9 Register description

4.11.16.9.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Configuration
7176 ConfigOutput15 UINT ●
7432 ConfigOutput16 UINT ●
7172 ConfigAdvanced01 UDINT ●
7428 ConfigAdvanced02 UDINT ●
Communication
7184 Encoder01 UDINT ●
7440 Encoder02 UDINT ●
264 Input state of digital inputs 1 to 2 USINT ●
DigitalInput01 Bit 3
DigitalInput02 Bit 7
40 Status of encoder supply USINT ●
PowerSupply01 Bit 0

4.11.16.9.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Configuration
7176 - ConfigOutput15 UINT ●
7432 - ConfigOutput16 UINT ●
7172 - ConfigAdvanced01 UDINT ●
7428 - ConfigAdvanced02 UDINT ●
Communication
7184 0 Encoder01 UDINT ●
7440 8 Encoder02 UDINT ●
264 4 Input state of digital inputs 1 to 2 USINT ●
DigitalInput01 Bit 3
DigitalInput02 Bit 7
40 5 Status of encoder supply USINT ●
PowerSupply01 Bit 0

1) The offset specifies the position of the register within the CAN object.

4.11.16.9.3 SSI encoder configuration register

4.11.16.9.3.1 Standard configuration

Name:
ConfigOutput15 to ConfigOutput 16
This configuration register is used to set the coding, the clock rate and the number of bits. Default = 0. This must
be set once using an acyclic write command.
"ConfigOutput15": Configuration register for SSI encoder01 and
"ConfigOutput16": Configuration register for SSI encoder02
Data type Value
UINT See bit structure.

Bit structure:
Bit Name Value Information
0-5 SSI value valid bits
6-7 Clock rate 11 125 kHz
8 - 13 SSI number of bits x Number of bits including leading zeros
14 Reserved 0
15 Keying 0 Binary coding
1 Gray coding

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4.11.16.9.3.2 Extended configuration

Name:
ConfigAdvanced01 to ConfigAdvanced02
This configuration register is used to set the coding, the clock rate, the number of bits and the monostable multivi-
brator settings. Default = 0. This must be set once using an acyclic write command.
It only differs from register ConfigOutput15 + 16 by data length and additional monostable multivibrator testing.
"ConfigAdvanced01": Configuration register for SSI encoder01 and
"ConfigAdvanced02": Configuration register for SSI encoder02
Data type Value
UDINT See bit structure.

Bit structure:
Bit Name Value Information
0-5 SSI value valid bits x
6-7 Clock rate 11 125 kHz
8 - 13 SSI number of bits x Number of bits including leading zeros
14 Reserved 0
15 Keying 0 Binary coding
1 Gray coding
16 - 17 Monostable multivibrator 00 Check OFF, no additional clock bit
01 Check set to High level
10 Check set to Low level
11 Level is clocked but ignored
18 - 31 Reserved 0

Transfer to synchronous serial interface

1 2 3 4

Clock

Data Bit n Bit n - 1 Bit n - 3 Bit 1 Bit 0

Measurement value processing

1 Starting bit ... Stores the measurement value
2 Output of first data bit
3 All data bits are transferred, monostable multivibrator time starts counting down.
4 Monostable multivibrator returns to its initial state. A new transfer can be started.

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4.11.16.9.4 SSI encoder - Configuration registers

4.11.16.9.4.1 SSI position values

Name:
Encoder01 to Encoder02
The two SSI encoder values are displayed as 32-bit position values. The SSI position values are generated syn-
chronously with the X2X cycle.
Data type Value Filter
UDINT 0 to 4,294,967,729 SSI position

4.11.16.9.4.2 Input state of digital inputs 1 to 2

Name:
DigitalInput01 to DigitalInput02
This register is used to indicate the input state of digital inputs 1 to 2.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
3 DigitalInput01 0 or 1 Input state - Digital input 1
7 DigitalInput02 0 or 1 Input state - Digital input 2

4.11.16.9.4.3 Status of encoder supply

Name:
PowerSupply01
This register shows the status of the integrated encoder supply. A faulty encoder power supply is displayed as
a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 PowerSupply01 0 24 VDC encoder power supply OK
1 24 VDC encoder power supply faulty
1-7 Reserved -

4.11.16.9.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
128 μs

4.11.16.9.6 Maximum cycle time

The maximum cycle time defines how far the bus cycle can be increased without internal counter overflows causing
module malfunctions.
Minimum cycle time
16 ms

4.11.16.9.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
128 μs

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X20 system modules • Counter modules • X20DC4395

4.11.17 X20DC4395

4.11.17.1 General information

This module is a multifunctional counter module. It can be connected to two SSI encoders, two ABR encoders,
four AB encoders or eight event counters. Four outputs are available for pulse width modulation. The functions
can also be mixed.
• 24 VDC encoder inputs
• SSI, ABR, AB or event counters for inputs
• Pulse width modulation for outputs
• 24 VDC and GND for encoder supply

Information:
This module is a multifunctional module. Some bus controllers only support the default function model.
Default function model:
• 1x ABR incremental encoder (24 V)
• 1x SSI absolute encoder (24 V)
• 1x event counter (24 V)
• 2x PWM output (24 V)

4.11.17.2 Order data

Model number Short description Figure

Counter functions
X20DC4395 X20 digital counter module, 2 SSI absolute encoder, 24 V, 2 ABR
incremental encoder, 24 V, 4 AB incremental encoders, 24 V, 8
event counters or 4 PWM, local time measurement function
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 255: X20DC4395 - Order data

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4.11.17.3 Technical data

Product ID X20DC4395
Short description
I/O module 2 SSI absolute encoder, 24 V, 2 ABR incremental encoder, 24 V, 4 AB incremental encoders,
24 V, 8x event counters or 4x pulse width modulation, time measurement, relative timestamp
General information
Input voltage 24 VDC -15% / +20%
B&R ID code 0x1CC5
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, using the status LED and software (output error status)
Power consumption
Bus 0.01 W
Internal I/O 1.5 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Output - Output No
Output - Bus Yes
Output - Encoder No
Encoder - Bus Yes
Encoder - Encoder No
Type of signal lines Shielded cables must be used for all signal lines.
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Incremental encoder
Quantity 4
Encoder inputs 24 V, asymmetrical
Counter size 16/32-bit
Input frequency Max. 100 kHz
Evaluation 4x
Encoder supply Module-internal, max. 600 mA
Overload behavior of the encoder supply Short circuit protection, overload protection
SSI absolute encoder
Quantity 2
Encoder inputs 24 V, asymmetrical
Counter size 32-bit
Max. transfer rate 125 kbit/s
Encoder supply Module-internal, max. 600 mA
Keying Gray/Binary
CLK: Output current Max. 100 mA
Overload behavior of the encoder supply Short circuit protection, overload protection
Event counter
Quantity 8
Nominal voltage 24 VDC
Signal form Square wave pulse
Evaluation Each edge, cyclic counter
Input frequency Max. 100 kHz
Input current at 24 VDC Approx. 1.3 mA
Input resistance 18.4 kΩ
Isolation voltage between channel and bus 500 Veff
Counter frequency 200 kHz
Counter size 16/32-bit
Input filter
Hardware ≥2 µs
Software -
Switching threshold
Low <5 VDC
High >15 VDC
Time measurement
Possible measurements Gate time, period duration, edge offset for various channels
Measurements per module Up to 9
Measurements per channel Up to 2
Counter size 16-bit
Counter frequency
Internal 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 62.5 kHz
Signal form Square wave pulse

Table 256: X20DC4395 - Technical data

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Product ID X20DC4395
Measurement type Continuous or triggered
Digital outputs
Design Push / Pull / Push-Pull
Quantity 4
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.1 A
Total nominal current 0.4 A
Output circuit Sink or source
Output protection Thermal cutoff if overcurrent or short circuit occurs, integrated protection for switching inductances
Pulse width modulation 1)
Period duration 41.6 µs to 1.36 s
Factor for period duration n/48000 s, n = 2 to 65535
Pulse duration 0 to 100%
Resolution for pulse duration 0.1%
Actuator supply Module-internal, max. 600 mA
Diagnostic status Output monitoring
Leakage current when switched off Max. 25 µA
Residual voltage <0.9 V at 0.1 A rated current
Peak short circuit current <10 A
Switching on after overload or short circuit cutoff Approx. 10 ms (depends on the module temperature)
Switching delay
0 -> 1 <2 µs
1 -> 0 <2 µs
Switching frequency
Resistive load Max. 24 kHz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Switching voltage + 0.6 VDC
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 256: X20DC4395 - Technical data

1) Dead time when switching between push and pull: max. 1.5 µs.

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4.11.17.4 LED status indicators

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
1-8 Green Status of the corresponding digital signal

1) Depending on the configuration, a firmware update can take up to several minutes.

4.11.17.5 Pinout

Shielded cables must be used for all signal lines.

r e

X20 DC 4395
1 5
2 6
3 7
4 8

Channel 1 Channel 5

Channel 2 Channel 6

Channel 3 Channel 7

Channel 4 Channel 8

Encoder 1 24 V+ Encoder 2 24 V+

GND GND

4.11.17.6 Connection example

DC

Data Data

Cycle Cycle
Counter 1

Counter 2

A A
B B
R R
PWM PWM

+24 VDC +24 VDC

GND GND

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4.11.17.7 Function overview

The following functions can be configured on the module. They cannot all be used at the same time due to the
multiple use of the hardware channels and the limited cyclic data length.
• 8 digital channels, 4 of which can be configured as outputs
• 8 event counters with configurable counting direction and optional referencing via digital input
• 4 PWM outputs
• 4 up/down counters, each with optional latch inputs and comparator output
• 4 AB counters, each with optional latch inputs and comparator output
• 2 ABR encoder with configurable reference pulse edge and reference position, optional reference enable
input, latch input and comparator output
• 2 SSI counter with optional latch input and comparator output
• 2 edge-triggered time measurement functions with configurable start edge based on current configuration
settings

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4.11.17.7.1 Description of channel assignments

The functions listed here are directly assigned to the respective hardware channels and cannot be changed:
Channel Signal connections
1 • Digital input 1
• Event counter 1
• AB encoder 1 - signal line A
• Up/down counter 1 - frequency
• SSI encoder 1 - data line
• ABR encoder 1 - signal line A
2 • Digital input 2
• Digital output 2
• Event counter 2
• PWM output 2
• AB encoder 1 - signal line B
• Up/down counter 1 - direction
• SSI encoder 1 - clock line
• ABR encoder 1 - signal line B
3 • Digital input 3
• Event counter 3
• AB encoder 2 - signal line A
• Up/down counter 2 - frequency
• ABR encoder 1 - signal line R
4 • Digital input 4
• Digital output 4
• Event counter 4
• PWM output 4
• AB encoder 2 - signal line B
• Up/down counter 2 - direction
• ABR encoder 1 - reference enable input
5 • Digital input 5
• Event counter 5
• AB encoder 3 - signal line A
• Up/down counter 3 - frequency
• SSI encoder 2 - data line
• ABR encoder 2 - signal line A
6 • Digital input 6
• Digital output 6
• Event counter 6
• PWM output 6
• AB encoder 3 - signal line B
• Up/down counter 3 - direction
• SSI encoder 2 - clock line
• ABR encoder 2 - signal line B
7 • Digital input 7
• Event counter 7
• AB encoder 4 - signal line A
• Up/down counter 4 - frequency
• ABR encoder 2 - signal line R
8 • Digital input 8
• Digital output 8
• Event counter 8
• PWM output 8
• AB encoder 4 - signal line B
• Up/down counter 4 - direction
• ABR encoder 2 - reference enable input

Options available in addition to these basic functions, such as comparator outputs or latch inputs, can be configured
freely to unused input/output channels.

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4.11.17.7.2 Connection options

Channels 1 to 8 can be connected as follows:

Channel Function
1 I Event counter A A SSI data
2 I/O Event counter B B SSI cycle PWM
3 I Event counter A R
4 I/O Event counter B Enable reference PWM
5 I Event counter A A SSI data
6 I/O Event counter B B SSI cycle PWM
7 I Event counter A R
8 I/O Event counter B Enable reference PWM

The functions can also be mixed. For example:

Example 1 Example 2 Example 3
Channel Function Channel Function Channel Function
1 SSI data 1 SSI data 1 Event counter
2 SSI cycle 2 SSI cycle 2 PWM
3 Event counter 3 A 3 Event counter
4 PWM 4 B 4 PWM
5 A 5 Event counter 5 SSI data
6 B 6 Event counter 6 SSI cycle
7 Event counter 7 Event counter 7 A
8 PWM 8 Event counter 8 B

Example 4 Example 5 Example 6

Channel Function Channel Function Channel Function
1 A 1 A 1 Event counter
2 B 2 B 2 Event counter
3 R 3 Event counter 3 Event counter
4 Enable reference 4 PWM 4 PWM
5 A 5 A 5 SSI data
6 B 6 B 6 SSI cycle
7 R 7 Event counter 7 A
8 Enable reference 8 Event counter 8 B

4.11.17.8 Input circuit diagram

Input x

VDR
Input status

I/O status

24 V
PTC
Encoder 24 V LED (green)

GND

GND

4.11.17.9 Output circuit diagram

24 V

Output status Push

PTC
Output x

VDR
Output status Pull

GND
Output
monitoring

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4.11.17.10 Switching inductive loads

100 H 10 H 1H
1000
0.1 H

Coil resistance
Coil inductance
[Ω]

0.01 H
240 Ω ≙ 100 mA
0.1 1 10 100 1000 10000

Max. switching cycles / second

(with 90% duty cycle)

4.11.17.11 Calculating the period duration

The outputs of the module can be operated as PWM outputs. The period duration is calculated using the following
formula:
n
Period duration = s
48000
A value of 2 to 65535 can be defined for n.

Example
n Period duration Frequency
2 416 μs 24 kHz
24000 500 ms 2 Hz
48000 1s 1 Hz
65535 1.36 s 0.73 Hz

Table 257: Calculating the period duration

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4.11.17.12 Register description

4.11.17.12.1 Function model 0 - Standard and Function model 1 - 32-bit counter

The following 2 models can be selected:

• 16-bit counter, Function model 0
• 32-bit counter, Function model 1 (identified in the table with a "(D)" in the data type and "(_32Bit)" in the
name.)
The only difference between these two models is that they use either 16-bit or 32-bit registers for incremental
counter functions. These include:
• ABR encoders
• AB encoders
• Up/down counters
• Event counters
All other module functions e.g. SSI, PWM and time measurement, as well as their data types, are identical for
the two models.
Register Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
Module configuration - General
(N-1) * 2 CfO_CFGchannel0N (Index N = 1 to 8) USINT ●
64 + N * 2 CfO_LEDNsource (Index N = 0 to 7) USINT ●
Configuration - Input for ABR encoders
512 CfO_DIREKTIOevent0IDwr UINT ●
544 CfO_DIREKTIOevent1IDwr UINT ●
516 CfO_DIREKTIOevent0mode USINT ●
548 CfO_DIREKTIOevent1mode USINT ●
522 CfO_DIREKTIOevent0compState UINT ●
544 CfO_DIREKTIOevent1compState UINT ●
520 CfO_Ev0CompMask USINT ●
552 CfO_Ev1CompMask USINT ●
2064 + (N-1) * 256 CfO_CounterNPresetValue1(_32Bit) (Index N = 1 to 4) U(D)INT ●
2068 + (N-1) * 256 CfO_CounterNPresetValue2(_32Bit) (Index N = 1 to 4) U(D)INT ●
2048 + (N-1) * 256 CfO_CounterNconfig (Index N = 1 to 4) USINT ●
2056 + (N-1) * 256 CfO_CounterNconfigReg0 (Index N = 1 to 4) USINT ●
2058 + (N-1) * 256 CfO_CounterNconfigReg1 (Index N = 1 to 4) USINT ●
2112 + (N-1) * 256 CfO_CounterNevent0IDwr (Index N = 1 to 4) UDINT ●
2120 + (N-1) * 256 CfO_CounterNevent0config (Index N = 1 to 4) UINT ●
2144 + (N-1) * 256 CfO_CounterNevent1IDwr (Index N = 1 to 4) UINT ●
2152 + (N-1) * 256 CfO_CounterNevent1config (Index N = 1 to 4) UINT ●
2148 + (N-1) * 256 CfO_CounterNevent1mode (Index N = 1 to 4) USINT ●
Configuration - Inputs for AB, up/down and event counters
2048 + (N-1) * 256 CfO_CounterNconfig (Index N = 1 to 4) USINT ●
2056 + (N-1) * 256 CfO_CounterNconfigReg0 (Index N = 1 to 4) USINT ●
2058 + (N-1) * 256 CfO_CounterNconfigReg1 (Index N = 1 to 4) USINT ●
2112 + (N-1) * 256 CfO_CounterNevent0IDwr (Index N = 1 to 4) UDINT ●
2120 + (N-1) * 256 CfO_CounterNevent0config (Index N = 1 to 4) UINT ●
2116 + (N-1) * 256 CfO_CounterNevent0mode (Index N = 1 to 4) USINT ●
2144 + (N-1) * 256 CfO_CounterNevent1IDwr (Index N = 1 to 4) UINT ●
2152 + (N-1) * 256 CfO_CounterNevent1config (Index N = 1 to 4) UINT ●
2148 + (N-1) * 256 CfO_CounterNevent1mode (Index N = 1 to 4) USINT ●
Configuration - Inputs for SSI encoders
7,176 CfO_SSI1cfg UINT ●
7,432 CfO_SSI2cfg UINT ●
7,180 CfO_SSI1control USINT ●
7,436 CfO_SSI2control USINT ●
7,168 CfO_SSI1eventIDwr UINT ●
7,424 CfO_SSI2eventIDwr UINT ●
7,232 CfO_SSI1event0IDwr UINT ●
7,488 CfO_SSI2event0IDwr UINT ●
7,240 CfO_SSI1event0config UINT ●
7,496 CfO_SSI2event0config UINT ●
7,236 CfO_SSI1event0mode USINT ●
7,492 CfO_SSI2event0mode USINT ●
7,172 ConfigAdvanced01 UDINT ●
7,428 ConfigAdvanced02 UDINT ●
Configuration - Comparator function for ABR, AB, SSI encoders and up/down counters
256 CfO_OutClearMask USINT ●
258 CfO_OutSetMask USINT ●

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Register Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
1,024 CfO_DIREKTIOoutevent0IDwr UINT ●
1034 + N * 32 CfO_DIREKTIOoutsetmaskN (Index N = 0 to 3) USINT ●
1032 + N * 32 CfO_DIREKTIOoutclearmaskN (Index N = 0 to 3) USINT ●
1,066 CfO_DIREKTIOoutsetmask1 USINT ●
1,064 CfO_DIREKTIOoutclearmask1 USINT ●
1024 + N * 32 CfO_DIREKTIOouteventNIDwr (Index N = 0 to 3) UINT ●
Configuration - Outputs for PWM (pulse width modulation)
6144 + N * 16 CfO_PWMNprescaler (Index N = 0 to 3) UINT ●
Module communication - General
40 Status of encoder supply USINT ●
PowerSupply01 Bit 0
Communication - Digital inputs
264 Input states of the channels USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
Communication - Event counters
2,080 EventCounter01 U(D)INT ●
2,084 EventCounter02 U(D)INT ●
2,336 EventCounter03 U(D)INT ●
2,340 EventCounter04 U(D)INT ●
2,592 EventCounter05 U(D)INT ●
2,596 EventCounter06 U(D)INT ●
2,848 EventCounter07 U(D)INT ●
2,852 EventCounter08 U(D)INT ●
Communication - Input for ABR encoders (optionally with comparator)
2,080 ABREncoder01 (D)INT ●
2,592 ABREncoder02 (D)INT ●
2,116 ReferenceModeABR01 USINT ●
2,628 ReferenceModeABR02 USINT ●
2,160 OriginComparator01 (D)INT ●
2,164 MarginComparator01 U(D)INT ●
264 Input states of the channels USINT ●
ComparatorActualValue02 Bit 1
ReferenceEnableSwitch01 (without comparator) Bit3
ComparatorActualValue01 (with comparator)
ComparatorActualValue02 (with comparator)
ComparatorActualValue01 Bit 5
ReferenceEnableSwitch02 (without comparator) Bit 7
ComparatorActualValue01 (with comparator)
ComparatorActualValue02 (with comparator)
2,172 Latch01ABR01 (D)INT ●
2,684 Latch01ABR02 (D)INT ●
2,118 StatusABR01 USINT ●
2,630 StatusABR02 USINT ●
Communication - Input for AB
2080 + (N-1) * 256 ABEncoder0N (Index N = 1 to 4) (D)INT ●
2,336 ABEncoder02 (D)INT ●
2,160 OriginComparator01 (D)INT ●
2,164 MarginComparator01 U(D)INT ●
264 Input states of the channels USINT ●
ComparatorActualValue03 Bit 1
ComparatorActualValue01 Bit 3
ComparatorActualValue03
ComparatorActualValue01 Bit 5
ComparatorActualValue01 Bit 7
ComparatorActualValue03
2140 + (N-1) * 256 Latch01AB0N (Index N = 1 to 4) (D)INT ●
2172 + (N-1) * 256 Latch02AB0N (Index N = 1 to 4) (D)INT ●
Communication - Up/down counters
2080 + (N-1) * 256 Counter0N (Index N = 1 to 4) U(D)INT ●
2,160 OriginComparator01 U(D)INT ●
2,164 MarginComparator01 U(D)INT ●
264 Input states of the channels USINT ●
ComparatorActualValue03 Bit 1
ComparatorActualValue01 Bit 3
ComparatorActualValue03
ComparatorActualValue01 Bit 5
ComparatorActualValue01 Bit 7
ComparatorActualValue03
2140 + (N-1) * 256 Latch01Counter0N (Index N = 1 to 4) U(D)INT ●
2172 + (N-1) * 256 Latch02Counter0N (Index N = 1 to 4) U(D)INT ●
Communication - Input for SSI encoders
7,184 SSIEncoder01 UDINT ●
7,440 SSIEncoder02 UDINT ●

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Register Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
7,248 OriginComparator01 UDINT ●
7,504 OriginComparator02 UDINT ●
7,252 MarginComparator01 UDINT ●
7,508 MarginComparator02 UDINT ●
264 Input states of the channels USINT ●
ComparatorActualValue02 Bit 1
ComparatorActualValue01 Bit 3
ComparatorActualValue02
ComparatorActualValue01 Bit 5
ComparatorActualValue01 Bit 7
ComparatorActualValue02
7,260 Latch01SSI01 UDINT ●
7,516 Latch01SSI02 UDINT ●
Communication - Digital outputs
260 Output states of the channels USINT ●
DigitalOutput02 Bit 1
DigitalOutput04 Bit 3
DigitalOutput06 Bit 5
DigitalOutput08 Bit 7
264 Input states of the channels USINT ●
StatusDigitalOutput02 Bit 1
StatusDigitalOutput04 Bit 3
StatusDigitalOutput06 Bit 5
StatusDigitalOutput08 Bit 7
Communication - Outputs for PWM (pulse width modulation)
6130 + N * 8 PWMOutput0N (Index N = 2,4,6,8) UINT ●
Configuration - Edge detection
4,104 CfO_EdgeDetectFalling USINT ●
4,106 CfO_EdgeDetectRising USINT ●
4,108 CfO_FallingDisProtection USINT ●
4,110 CfO_RisingDisProtection USINT ●
Configuration - Time measurement
4,336 CfO_EdgeTimeglobalenable USINT ●
4344 + N * 8 CfO_EdgeTimeFallingMode0N (Index N = 1 to 8) UINT ●
4472 + N * 8 CfO_EdgeTimeRisingMode0N (Index N = 1 to 8) UINT ●
Communication - Time measurement
4,342 Trigger rising edge detection USINT ●
TriggerRisingCH01 Bit 0
... ...
TriggerRisingCH08 Bit 7
4,350 Show first rising trigger edge USINT ●
BusyTriggerRisingCH01 Bit 0
... ...
BusyTriggerRisingCH08 Bit 7
4,340 Trigger falling edge detection USINT ●
TriggerFallingCH01 Bit 0
... ...
TriggerFallingCH08 Bit 7
4,348 Show first falling trigger edge USINT ●
BusyTriggerFallingCH01 Bit 0
... ...
BusyTriggerFallingCH08 Bit 7
4474 + N * 8 CountRisingCH0N (Index N = 1 to 8) USINT ●
4476 + N * 8 TimeStampRisingCH0N (Index N = 1 to 8) UINT ●
4478 + N * 8 TimeDiffRisingCH0N (Index N = 1 to 8) UINT ●
4346 + N * 8 CountFallingCH0N (Index N = 1 to 8) USINT ●
4348 + N * 8 TimeStampFallingCH0N (Index N = 1 to 8) UINT ●
4350 + N * 8 TimeDiffFallingCH0N (Index N = 1 to 8) UINT ●

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4.11.17.12.2 Function model 254 - Bus controller

Unlike the function models 0 and 1, this model only offers a selection of functions with a limited scope of config-
uration on the module.
The following functions are provided and can be run at the same time:
• SSI encoders
• ABR encoder with configurable reference pulse edge and reference position
• 1 event counter with configurable counting direction
• 2 PWM outputs
Register Offset1) Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
Module configuration - General
N*2-2 - CfO_CFGchannel0N (Index N = 1 to 8) USINT ●
N * 2 + 64 - CfO_LEDNsource (Index N = 0 to 7) USINT ●
Configuration - ABR encoder
512 - CfO_DIREKTIOevent0IDwr UINT ●
544 - CfO_DIREKTIOevent1IDwr UINT ●
2,560 - CfO_Counter3config USINT ●
2,568 - CfO_Counter3configReg0 USINT ●
2,570 - CfO_Counter3configReg1 USINT ●
2,576 - CfO_Counter3PresetValue1 UINT ●
2,580 CfO_Counter3PresetValue2 UINT ●
2,624 - CfO_Counter3event0IDwr UINT ●
2,632 - CfO_Counter3event0config UINT ●
2,628 - CfO_Counter3event0mode USINT ●
2,656 - CfO_Counter3event1IDwr UINT ●
2,664 - CfO_Counter3event1config UINT ●
2,660 - CfO_Counter3event1mode USINT ●
4,104 - CfO_EdgeDetectFalling USINT ●
4,106 - CfO_EdgeDetectRising USINT ●
Configuration - Event counter
2,304 - CfO_Counter2config USINT ●
2,312 - CfO_Counter2configReg0 USINT ●
2,314 - CfO_Counter2configReg1 USINT ●
2,368 - CfO_Counter2event0IDwr UINT ●
2,376 - CfO_Counter2event0config UINT ●
2,372 - CfO_Counter2event0mode USINT ●
2,400 - CfO_Counter2event1IDwr UINT ●
2,408 - CfO_Counter2event1config UINT ●
2,404 - CfO_Counter2event1mode USINT ●
Configuration - SSI encoder
7,176 - CfO_SSI1cfg UINT ●
7,180 - CfO_SSI1control USINT ●
7,168 - CfO_SSI1eventIDwr UINT ●
7,232 - CfO_SSI1event0IDwr UINT ●
7,240 - CfO_SSI1event0config UINT ●
7,236 - CfO_SSI1event0mode USINT ●
7,172 - ConfigAdvanced01 UDINT ●
Configuration - PWM (pulse width modulation)
6,160 - CfO_PWM1prescaler UINT ●
6,192 - CfO_PWM3prescaler UINT ●
Module communication - General
40 6 Status of encoder supply USINT ●
PowerSupply01 Bit 0
Communication - Counters and encoders
2,336 4 EventCounter03 UINT ●
2,592 8 ABREncoder02 INT ●
2,628 10 ReferenceModeABR02 USINT ●
2,630 10 StatusABR02 USINT ●
7,184 0 SSIEncoder01 UDINT ●
Communication - PWM (pulse width modulation)
6,162 0 PWMOutput04 UINT ●
6,194 8 PWMOutput08 UINT ●

1) The offset specifies the position of the register within the CAN object.

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4.11.17.12.3 General module registers

4.11.17.12.3.1 Configuring LED status indicators

Name:
CfO_LED0source to CfO_LED7source
These registers can be used to define how the module's LED status indicators are used. Blinking patterns can be
generated from the application, and the status of the physical inputs and outputs can be indicated.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-3 MODE = 0 0 LED off
1 Blinking quickly
2 Blinking
3 Blinking slowly
4 Single flash
5 Double flash
6 to 15 Reserved
MODE = 1 (inverted) 0 LED on
1 Blinking quickly
2 Blinking
3 Blinking slowly
4 Single flash
5 Double flash
6 to 15 Reserved
MODE = 2 0 to 7 Number of the physical input channel
8 to 15 Reserved
MODE = 3 0 to 7 Number of the physical output channel
8 to 15 Reserved
4-7 Selection of the mode for the LED status indicator 0 LED blinking pattern
1 Inverted LED blinking pattern
2 Displays a channel's physical input status
3 Displays a channel's physical output status
4 to 15 Reserved

4.11.17.12.3.2 Status of encoder supply

Name:
PowerSupply01
This register shows the status of the integrated encoder supply. A faulty encoder power supply is displayed as
a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 PowerSupply01 0 24 VDC encoder power supply OK
1 24 VDC encoder power supply faulty
1-7 Reserved -

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4.11.17.12.4 Digital inputs and outputs

4.11.17.12.4.1 Configure physical channels

Name:
CfO_CFGchannel01 to CfO_CFGchannel08
This register can be used to configure physical I/O channels 1 to 8.

Information:
Except for bit 2 (inverted input), all other bits are only available for channels 2, 4, 6 and 8.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Push1) 0 Disabled
1 Enabled
1 Pull1) 0 Disabled
1 Enabled
2 Inverted input 0 Disabled
1 Enabled
3 Inverted output 0 Disabled
1 Enabled
4-7 Output type 0 Direct I/O
1 to 5 Reserved
6 PWM (channel-specific)
7 SSI clock (channel-specific)

1) To configure a channel as an output, Push and/or Pull must be enabled.

4.11.17.12.4.2 Reset mask of the digital channels

Name:
CfO_OutClearMask
The settings in this register only affect the values written to registers 4.11.17.12.4.5 "DigitalOutput02 to 08".
• 0 allows manual reset of digital outputs using registers DigitalOutput02 to 08
• 1 prevents manual reset of digital outputs using registers DigitalOutput02 to 08
When "1" is used, the "output event function" can be used to reset the outputs.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Reserved -
1 DigitalOutput02 0 Writing 0 to the DigitalOutput02 register resets the output
1 Writing 0 from the DigitalOutput02 register does not reset the
output
2 Reserved -
3 DigitalOutput04 0 Writing 0 to the DigitalOutput04 register resets the output
1 Writing 0 from the DigitalOutput04 register does not reset the
output
4 Reserved -
5 DigitalOutput06 0 Writing 0 to the DigitalOutput06 register resets the output
1 Writing 0 from the DigitalOutput06 register does not reset the
output
6 Reserved -
7 DigitalOutput08 0 Writing 0 to the DigitalOutput08 register resets the output
1 Writing 0 from the DigitalOutput08 register does not reset the
output

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4.11.17.12.4.3 Set mask of the digital channels

Name:
CfO_OutSetMask
The settings in this register only affect the values written to registers 4.11.17.12.4.5 "DigitalOutput02 to 08".
• 0 allows manual setting of digital outputs using registers DigitalOutput02 to 04
• 1 prevents manual setting of digital outputs using registers DigitalOutput02 to 04
When "1" is used, the "output event function" can be used to reset the outputs.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Reserved -
1 DigitalOutput02 0 Writing 1 to the DigitalOutput02 register sets the output
1 Writing 1 from the DigitalOutput02 register does not set the out-
put
2 Reserved -
3 DigitalOutput04 0 Writing 1 to the DigitalOutput04 register sets the output
1 Writing 1 from the DigitalOutput04 register does not set the out-
put
4 Reserved -
5 DigitalOutput06 0 Writing 1 to the DigitalOutput06 register sets the output
1 Writing 1 from the DigitalOutput06 register does not set the out-
put
6 Reserved -
7 DigitalOutput08 0 Writing 1 to the DigitalOutput08 register sets the output
1 Writing 1 from the DigitalOutput08 register does not set the out-
put

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4.11.17.12.4.4 Input states of the channels

Name:
see "Name in the AS I/O configuration"
This register reads the input status of a physical channel. The polarity settings are accounted for in the value (bit
2 in 4.11.17.12.4.1 "CfO_CFGchannel[x]" register).
The bits in this register are shown in the AS I/O mapping table under different names based on the function used
in order to improve readability.
Data type Value
USINT See bit structure.

Bit structure:
Bit Physical input channel Value Name in the AS I/O configuration
0 Channel 1 0 or 1 DigitalInput01
1 Channel 2 0 or 1 DigitalInput02
StatusDigitalOutput02
ComparatorActualValue02
ComparatorActualValue03
2 Channel 3 0 or 1 DigitalInput03
3 Channel 4 0 or 1 DigitalInput04
StatusDigitalOutput04
ReferenceEnableSwitch01
ComparatorActualValue01
ComparatorActualValue02
ComparatorActualValue03
4 Channel 5 0 or 1 DigitalInput05
5 Channel 6 0 or 1 DigitalInput06
StatusDigitalOutput06
ComparatorActualValue01
6 Channel 7 0 or 1 DigitalInput07
7 Channel 8 0 or 1 DigitalInput08
StatusDigitalOutput08
ReferenceEnableSwitch02
ComparatorActualValue01
ComparatorActualValue02
ComparatorActualValue03

4.11.17.12.4.5 Output states of the channels

Name:
DigitalOutput02 to DigitalOutput08
The output status of a physical channel can be written using this register. In order to configure a channel as an
output:
1 Bit 0 "Push" and/or bit 1 "Pull" must be enabled in the 4.11.17.12.4.1 "CfO_CFGchannel[x]" register.
2 Bits 4 to 7 in the 4.11.17.12.4.1 "CfO_CFGchannel[x]" register must be set to Direct I/O.
3 0 must be set for the respective channel in the 4.11.17.12.4.2 "CfO_OutClearMask" and 4.11.17.12.4.3
"CfO_OutSetMask" registers.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Reserved -
1 DigitalOutput02 0 or 1 Output status of channel 2
2 Reserved -
3 DigitalOutput04 0 or 1 Output status of channel 4
4 Reserved -
5 DigitalOutput06 0 or 1 Output status of channel 6
6 Reserved -
7 DigitalOutput08 0 or 1 Output status of channel 8

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4.11.17.12.5 Event functions

The module provides configurable event functions. An event function can be connected to physical I/O and the
values derived from them (e.g. counters) or be purely used for internal processing.
Every event function has event inputs and outputs. Event functions can also have only inputs or only outputs. Each
event output has a unique event ID. It is possible to configure when an event should be generated on an event
output. The effect of an event is determined by the respective event function.
Event functions can also be linked to one another. The link takes place using the event input. Every event input
has a 16-bit register to which the event number of the linked event output is written.

Information:
The module functions that can be configured in the AS I/O configuration are primarily based on these
event functions and their links. Changes in the AS I/O configuration have multiple effects on event
functions and their links.

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4.11.17.12.5.1 List of event IDs

Various hardware and software functions send event IDs or require event IDs in order to start. The following table
shows all of the IDs available to configure the module.
Event ID Description
Direct event inputs
512 Comparator condition 1 FALSE
513 TRUE
544 Comparator condition 2 FALSE
545 TRUE
576 Comparator condition 3 FALSE
577 TRUE
608 Comparator condition 4 FALSE
609 TRUE
Counter comparator function
2,112 Counter function 1 Event function 1; FALSE
2,113 Event function 1; TRUE
2,144 Event function 2; FALSE
2,145 Event function 2; TRUE
2,368 Counter function 2 Event function 1; FALSE
2,369 Event function 1; TRUE
2,400 Event function 2; FALSE
2,401 Event function 2; TRUE
2,624 Counter function 3 Event function 1; FALSE
2,625 Event function 1; TRUE
2,656 Event function 2; FALSE
2,657 Event function 2; TRUE
2,880 Counter function 4 Event function 1; FALSE
2,881 Event function 1; TRUE
2,912 Event function 2; FALSE
2,913 Event function 2; TRUE
Edge events
4,096 Falling edge on I/O channel Channel 1
... ...
4,103 Channel 8
4,112 Rising edge on I/O channel Channel 1
... ...
4,119 Channel 8
4,128 Rising or falling edge on I/O channel Channel 1
... ...
4,135 Channel 8
SSI counter events
7,168 SSI 1 SSI valid
7,169 SSI ready
7,424 SSI 2 SSI valid
7,425 SSI ready
SSI comparator events
7,232 SSI 1 comparator condition FALSE
7,233 TRUE
7,488 SSI 2 comparator condition FALSE
7,489 TRUE
Timerevents
208 Timer1 50 μs
209 Timer2 100 μs
210 Timer3 200 μs
211 Timer4 400 μs
212 Timer5 800 μs
213 Timer6 1600 μs
214 Timer7 3200 μs
215 Timer8 3200 μs (time offset to timer 7)
Network functions
224 SOAISOP (synchronous out asynchronous in start of protocol)
225 AOSISOP (asynchronous out synchronous in start of protocol)
226 SOAIEOP (synchronous out asynchronous in end of protocol)
227 AOSIEOP (asynchronous out synchronous in end of protocol)
Idle event
192 No-load operation

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Timer
There are 8 timer events that the module can generate.

Information:
The timers have the highest event priority. All other system functions are interrupted when a timer
event occurs, and jitter for the amount of time it takes to process the event.

Idle event
Idle time is the time that remains after the system has processed all higher priority events and operations. The
module performs the following functions during idle time:
• Handling of the asynchronous protocol
• Mechanism for (re-)linking events
• Operation of LEDs
• Execution of event event functions linked to the idle function

4.11.17.12.5.2 Edge events

For each physical channel there are 3 event functions

• Falling edge
• Rising edge
• Falling and rising edge
The respective event is triggered when an edge is detected on the hardware input and the "CfO_EdgeDetectRising"
and/or "CfO_EdgeDetectFalling" register has been configured for the respective channel.
Edges are detected by the hardware and processed for each interrupt. The interrupt handler uses an event distrib-
utor, which requires a specific amount of time for each edge to operate the hardware and execute linked event
functions. To reduce this time, edge detection can be enabled/disabled individually for each channel. To optimize
system load and I/O jitter, it is important to only enable edge detection where it is actually needed.

Information:
Edge detection can also be used for channels that are configured as outputs.

Event frequency limitation

To stabilize the system, there is a mechanism that limits the number of events created through edge recognition.
At least one idle event must occur between two edge events for the same edge.
The "CfO_FallingDisProtection" and "CfO_RisingDisProtection" registers can be used to disable this limitation for
each edge, and then an event will be generated for every edge. However, this can cause a system overload, i.e.
I/O operation can fail for up to 100 ms before the module changes to the reset state.

Generate event on falling edge

Name:
CfO_EdgeDetectFalling
This register defines whether an event is generated on a falling edge.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Channel 1 0 No event generated on falling edge.
1 Events 4096 and 4128 are generated on falling edge.
... ...
7 Channel 8 0 No event generated on falling edge.
1 Events 4103 and 4135 are generated on falling edge.

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Generate event on rising edge

Name:
CfO_EdgeDetectRising
This register defines whether an event is generated on a rising edge.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Channel 1 0 No event generated on rising edge.
1 Events 4112 and 4128 are generated on rising edge.
... ...
7 Channel 8 0 No event generated on rising edge.
1 Events 4119 and 4135 are generated on rising edge.

Enable limit for falling edges

Name:
CfO_FallingDisProtection
This register can be used to enable/disable the event frequency limit for falling edges on the respective channel.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Channel 1 0 Event frequency limit enabled.
1 Event frequency limit disabled.
... ...
7 Channel 7 0 Event frequency limit enabled.
1 Event frequency limit disabled.

Enable limit for rising edges

Name:
CfO_RisingDisProtection
This register can be used to enable/disable the event frequency limit for rising edges on the respective channel.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Channel 1 0 Event frequency limit enabled.
1 Event frequency limit disabled.
... ...
7 Channel 8 0 Event frequency limit enabled.
1 Event frequency limit disabled.

4.11.17.12.5.3 Direct input functions

The module has 2 "direct input functions"

These event functions are based on comparator functionality. If the event configured in the
"CfO_DIREKTIOevent0IDwr" register occurs, the event function compares the status of all Direct I/O channels
enabled in the "CfO_EvCompMask" register to a status defined in the "CfO_DIREKTIOeventcompState" register.
The event that is generated depends on the results of this comparison.
• If the respective bits are the same, then event number 513 or 545 is generated
• If the respective bits are different, then event number 512 or 544 is generated

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Configure event ID for input function

Name:
CfO_DIREKTIOevent0IDwr to CfO_DIREKTIOevent1IDwr
This register holds the event ID generated by the direct input function. For a list of all possible event IDs, see
4.11.17.12.5.1 "List of event IDs"
Data type Value Information
INT 192 to 7,289 ID of event function

Configure the mode of the input function

Name:
CfO_DIREKTIOevent0mode to CfO_DIREKTIOevent1mode
The mode in which the direct input function operates can be set in this register.
Comparator functions can be operated in 4 different modes. For a description, see "Comparator modes".
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Comparator mode 0 Off
1 Single
2 State change
3 Continuous
2-7 Reserved -

Comparator status for comparator mask

Name:
CfO_DIREKTIOevent0compState to CfO_DIREKTIOevent1compState
This register contains the status bits that are compared with the bits specified in the "CfO_Ev0CompMask" register,
which contain the I/O input status, when an event is received.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Comparator status of channel 1 0 or 1
... ...
7 Comparator status of channel 8 0 or 1

Configure the comparator mask for the input function

Name:
CfO_Ev0CompMask to CfO_Ev1CompMask
If a bit is set, then the input status of the respective channel is compared with that bit in the
"CfO_DIREKTIOeventcompState" register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Channel 1 0 Do not compare bit
1 Compare bit in register
... ...
7 Channel 8 0 Do not compare bit
1 Compare bit in register

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4.11.17.12.5.4 Direct output functions

The module has 4 of these event functions

The effect of executing this event function is similar to writing to the 4.11.17.12.4.5 "DigitalOutput02 to 08" regis-
ters. When this event function is triggered, however, the changed output states are passed on to the hardware
immediately, regardless of the X2X cycle.
When this event function is used, the masks of the respective outputs (see 4.11.17.12.4.2 "CfO_OutClearMask"
and 4.11.17.12.4.3 "CfO_OutSetMask" registers) must be set to 1. Otherwise the output status would constantly
be overwritten by the values in the 4.11.17.12.4.5 "DigitalOutput02 to 08" registers.

Configure event ID for output function

Name:
CfO_DIREKTIOevent0IDwr to CfO_DIREKTIOevent3IDwr
These registers hold the event IDs that trigger the direct output function. For a list of all possible event IDs, see
4.11.17.12.5.1 "List of event IDs"
Data type Value Information
INT 192 to 7,489 ID of event function

Configure channels for resetting

Name:
CfO_DIREKTIOoutclearmask0 to CfO_DIREKTIOoutclearmask3
Writing "1" to the bit position that corresponds to a channel resets the output if the output event function is being
executed. This corresponds to writing "0" to the 4.11.17.12.4.5 "DigitalOutput 02 to 08" registers.
The bit that corresponds to channels that should be reset should be set to "1" in the 4.11.17.12.4.2
"CfO_OutClearMask" register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Reserved -
1 Channel 2 0 Reset channel 2
1 Do not reset channel 2
2 Reserved -
3 Channel 4 0 Reset channel 4
1 Do not reset channel 4
4 Reserved -
5 Channel 6 0 Reset channel 6
1 Do not reset channel 6
6 Reserved -
7 Channel 8 0 Reset channel 8
1 Do not reset channel 8

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Configure channels for setting

Name:
CfO_DIREKTIOoutsetmask0 to CfO_DIREKTIOoutsetmask3
Writing "1" to the bit position that corresponds to a channel sets the output if the output event function is being
executed. This corresponds to writing "1" to the 4.11.17.12.4.5 "DigitalOutput 02 to 08" registers.
The bit that corresponds to channels that should be reset should be set to "1" in the 4.11.17.12.4.3
"CfO_OutSetMask" register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Reserved -
1 Channel 2 0 Set channel 2
1 Do not set channel 2
2 Reserved -
3 Channel 4 0 Set channel 4
1 Do not set channel 4
4 Reserved -
5 Channel 6 0 Set channel 6
1 Do not set channel 6
6 Reserved -
7 Channel 8 0 Set channel 8
1 Do not set channel 8

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4.11.17.12.6 Counters and encoders

The module has 4 internal counter functions, each with 2 event counter registers. Each of these 4 counters is
permanently assigned to 2 physical inputs. This assignment cannot be changed.
The counter registers perform different functions based on how the event functions are connected. The counter
registers can be configured in the following ways:
• ABR counter
• AB counter
• Up/down counters
• Event counters
Different names are used for them in Automation Studio and in the register description to improve clarity.
Channel Counter function Counter register Name in AS

1 1 1 ABEncoder01
ABREncoder01
Counter01
EventCounter01
2 2 EventCounter02
3 2 1 ABEncoder02
Counter02
EventCounter03
4 2 EventCounter04
5 3 1 ABEncoder03
ABREncoder02
Counter03
EventCounter05
6 2 EventCounter06
7 4 1 ABEncoder04
Counter04
EventCounter07
8 2 EventCounter08

4.11.17.12.6.1 Counter value calculation

There are 3 steps for calculating the state of any counter function
1. The counter value is based on the 2 absolute value counters "abs1" and "abs2". These are only used internally in
the module and cannot be read. Depending on the mode, these registers show the respective physical input signals.
Mode
Edge counters AB encoders Up/down counter
abs1 Edges of counter channel 1 Increments in positive direction Counter channel 2 = 0:
Edges of counter channel 1
in up direction
abs2 Edges of counter channel 2 Increments in negative direction Counter channel 2 = 1
Edges of counter channel 1
in down direction

2. From the absolute value registers "abs1" and "abs2", 2 more counters are formed: "counter 1" and "counter 2".
They are only used internally in the module and cannot be read. The following values are used for the calculation:
• Absolute value registers "abs1" and "abs2"
• SW_reference_counter 1 and 2: This reference value can be defined by the "CfO_CounterPresetValue"
register to allow referencing <> 0.
• HW_reference_counter 1 and 2: In the "CfO_CounterEventMode" register, you can configure whether
latched values should be copied to these registers when counter events occur.
counter1 = abs1 + SW_reference_counter1 - HW_reference_counter1
counter2 = abs2 + SW_reference_counter2 - HW_reference_counter2
3. The counter registers contain the sum of the two internal counters "counter 1" and "counter 2". The
"CfO_CounterConfigReg" register allows you to define a sign for each "counter" register and define whether or
not it should be used.
Counter register = counter1 + counter2

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4.11.17.12.6.2 Sample configurations

All of the settings available in Automation Studio for AB encoders, ABR encoders, up/down counters and event
counters are based on the two counter functions.
The following configuration examples show the values with which Automation Studio initializes the module registers
in order to implement these functions.

I/O configuration - AB encoder

The following table shows how the module's various event functions can be linked in order to configure an AB
encoder.
[x] stands for the respective counter function, from 1 to 4
Register Value Comment
For the function
CfO_Counter[x]config 0x01 Mode = Up/down counter
CfO_Counter[x]configReg0 0x0D Configure the calculation of the internal "counter1" and "counter2" registers
(see 4.11.17.12.6.1 "Counter value calculation" and "Examples of calculation
configurations")
For the latch
CfO_Counter[x]event0config 0x000D Configuration of the calculation of the first value used for the latch
CfO_Counter[x]event0mode 0x03 Mode of the first counter event function - Continuous
CfO_Counter[x]event0IDwr (any) Number of the event that should trigger Latch 1 ("Latch 01 - Channel" in the AS
I/O configuration).
CfO_Counter[x]event1config 0x0D Configuration of the calculation of the second value used for the latch
CfO_Counter[x]event1mode 0x03 Mode of the second counter event function - Continuous
CfO_Counter[x]event1IDwr (any) Number of the event that should trigger Latch 2
For the comparator
CfO_Counter1event1IDwr 0x00D0 Event number of Timer 1 (50 μs)
CfO_Counter3event1IDwr
Information:
The latch and comparator must not have the same event number!

CfO_Counter1event1config 0x900D or 0xA00D Configuration of the comparator for the second counter event
CfO_Counter3event1config
CfO_Counter1event1mode 0x03 Mode of the second counter event function - Continuous
CfO_Counter3event1mode
CfO_DIREKTIOoutevent0IDwr 0x0861 TRUE event output of the second counter to trigger the direct output function
CfO_DIREKTIOoutevent2IDwr 0x0A61 (set outputs).
CfO_DIREKTIOoutsetmask0 0x08, 0x20, 0x80 Outputs that should be set when comparator condition = TRUE
CfO_DIREKTIOoutsetmask2 0x02, 0x08, 0x80
CfO_DIREKTIOoutevent1IDwr 0x0860 FALSE event output of the second counter to trigger the direct output function
CfO_DIREKTIOoutevent3IDwr 0x0A60 (reset outputs).
CfO_DIREKTIOoutclearmask1 0x08, 0x20, 0x80 Outputs that should be reset when comparator condition = FALSE
CfO_DIREKTIOoutclearmask3 0x02, 0x08, 0x80

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I/O configuration - ABR encoder

The following table shows how the module's various event functions can be linked in order to configure an ABR
encoder.
Register Value Comment
For the function
CfO_Counter1PresetValue1 (any) Desired offset value for referencing
CfO_Counter3PresetValue1
CfO_Counter1event0IDwr 0x0201 Link between the first counter event and the "direct input" comparator condition
CfO_Counter3event0IDwr TRUE
CfO_Counter1config 0x01 Mode = AB encoder
CfO_Counter3config
CfO_Counter1configReg0 0x0D Configure the calculation of the internal "counter1" and "counter2" registers
CfO_Counter3configReg0 (see 4.11.17.12.6.1 "Counter value calculation" and "Examples of calculation
configurations")
CfO_DIREKTIOevent0IDwr 0x1002 or 0x1012 Selection of the desired input edge as trigger for the ABR encoder function
CfO_DIREKTIOevent1IDwr
CfO_Counter1event0config 0x0000 Configuration of the first counter event (for referencing)
CfO_Counter3event0config
CfO_DIREKTIOevent0mode 0x03 Mode of the "direct input function" - Continuous
CfO_DIREKTIOevent1mode
CfO_DIREKTIOevent0compState 0x00 or 0x08 Comparator status for the "direct input function"
CfO_DIREKTIOevent1compState
CfO_Ev0CompMask 0x08 Comparator mask for the "direct input function"
CfO_Ev1CompMask
For the latch
CfO_Counter1event0config 0x000D Configuration of the calculation of the value used for the latch
CfO_Counter3event1config
CfO_Counter1event0mode 0x03 Mode of the first counter event function - Continuous
CfO_Counter3event1mode
CfO_Counter1event0IDwr (any) Number of the event that should trigger the latch
CfO_Counter3event1IDwr
For the comparator
CfO_Counter1event1IDwr 0x00D0 Event number of Timer 1 (50 μs)
CfO_Counter3event1IDwr
Information:
The latch and comparator must not have the same event number!

CfO_Counter1event1config 0x900D or 0xA00D Configuration of the comparator for the second counter event
CfO_Counter3event1config
CfO_DIREKTIOoutevent0IDwr 0x0861 TRUE event output of the second counter to trigger the direct output function
CfO_DIREKTIOoutevent2IDwr 0x0A61 (set outputs).
CfO_DIREKTIOoutsetmask0 0x08, 0x20, 0x80 Outputs that should be set when comparator condition = TRUE
CfO_DIREKTIOoutsetmask2 0x02, 0x08, 0x80
CfO_DIREKTIOoutevent1IDwr 0x0860 FALSE event output of the second counter to trigger the direct output function
CfO_DIREKTIOoutevent3IDwr 0x0A60 (reset outputs).
CfO_DIREKTIOoutclearmask1 0x08, 0x20, 0x80 Outputs that should be reset when comparator condition = FALSE
CfO_DIREKTIOoutclearmask3 0x02, 0x08, 0x80

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I/O configuration - Up/down counter

The following table shows how the module's various event functions can be linked in order to configure an up/
down counter.
[x] stands for the respective counter function, from 1 to 4
Register Value Comment
For the function
CfO_Counter[x]config 0x03 Counter mode = Up/down counter
CfO_Counter[x]configReg0 0x0D, 0x07 Configure the calculation of the internal "counter1" and "counter2" registers
(see 4.11.17.12.6.1 "Counter value calculation" and "Examples of calculation
configurations")
For the latch
CfO_Counter[x]event0config 0x0D, 0x07 Configuration of the calculation of the first value used for the latch
CfO_Counter[x]event0mode 0x03 Mode of the first counter function - Continuous
CfO_Counter[x]event0IDwr (any) Number of the event that should trigger Latch 1
CfO_Counter[x]event1config 0x0D, 0x07 Configuration of the calculation of the second value used for the latch
CfO_Counter[x]event1mode 0x03 Mode of the second counter function - Continuous
CfO_Counter[x]event1IDwr (any) Number of the event that should trigger Latch 2
For the comparator
CfO_Counter1event1IDwr 0x00D0 Event number of Timer 1 (50 μs)
CfO_Counter3event1lDwr
Information:
The latch and comparator must not have the same event number!

CfO_Counter1event1config 0x900D, 0xA00d or 0x9007, 0xA007 Configuration of the comparator for the second counter event
CfO_Counter3event1config
CfO_Counter1event1mode 0x03 Mode of the second counter event function - Continuous
CfO_Counter3event1lmode
CfO_DIREKTIOoutevent0IDwr 0x0861 TRUE event output of the second counter to trigger the direct output function
CfO_DIREKTIOoutevent2lDwr (set outputs).
CfO_DIREKTIOoutsetmask0 0x08, 0x20, 0x80 Outputs that should be set when comparator condition = TRUE
CfO_DIREKTIOoutsetmask2 0x02, 0x08, 0x80
CfO_DIREKTIOoutevent1IDwr 0x0860 FALSE event output of the second counter to trigger the direct output function
CfO_DIREKTIOoutevent3lDwr 0x0A60 (reset outputs).
CfO_DIREKTIOoutclearmask1 0x08, 0x20, 0x80 Outputs that should be reset when comparator condition = FALSE
CfO_DIREKTIOoutclearmask3 0x02, 0x08, 0x80

I/O configuration - Event counter

The following table shows how the module's various event functions can be linked in order to configure an event
counter.
[x] stands for the respective counter function, from 1 to 4
Register Value Comment
For event counters on channels 1, 3, 5 and 7
CfO_Counter[x]configReg0 0x01 or 0x03 Configure the calculation of the internal "counter1" and "counter2" registers
(see 4.11.17.12.6.1 "Counter value calculation" and "Examples of calculation
configurations")
CfO_Counter[x]event0mode 0x43 Mode of the first counter event function and referencing configuration
CfO_Counter[x]event0IDwr (any) Number of the event that should trigger referencing
For event counters on channels 2, 4, 6 and 8
CfO_Counter[x]configReg1 0x04 or 0x08 Configure the calculation of the internal "counter1" and "counter2" registers
(see 4.11.17.12.6.1 "Counter value calculation" and "Examples of calculation
configurations")
CfO_Counter[x]event1mode 0x83 Mode of the second counter event function and referencing configuration
CfO_Counter[x]event1IDwr (any) Number of the event that should trigger referencing

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4.11.17.12.6.3 General event functions

Each of the 4 counter functions has 2 counter event functions. These consist of:
• Event ID that triggers the counter event function
• A window comparator
• Latch register for saving the counter value
When the counter event function is complete, a combined event ID in the range 2112 to 2913 (see 4.11.17.12.5.1
"List of event IDs") is sent.
Each counter event function also has the option to copy the current counter value to the "HW reference counter"
when an event occurs (see 4.11.17.12.6.1 "Counter value calculation").
Event input
E

True event False event

Comparator window
Logic

Latch True

CfO_Counter(x)event(y) False CfO_Counter(x)event(y) False

mode.Bit6 = 1 ? mode.Bit4 = 1 ?

True True
Hardware reference Hardware reference
Counter 1 = abs 1 Counter 1 = abs 1

CfO_Counter(x)event(y) False CfO_Counter(x)event(y) False

mode.Bit7 = 1 ? mode.Bit5 = 1 ?

True True
Hardware reference Hardware reference
Counter 2 = abs 2 Counter 2 = abs 2

E E
Event output Event output
True False

Configure counter mode

Name:
CfO_Counter1config to CfO_Counter4config
These registers are used to configure the mode of the counter function. Each counter function can be operated
in 3 different modes.
Counter function mode
Edge counters AB encoder Up/down counter
Counter channel 11) Counting pulses, edge counter 1 A Metering pulses
Counter channel 21) Counting pulses, edge counter 2 B Counting direction (0 =
positive, 1 = negative)
Counter register 1 Counter value 1 Position Counter value
Counter register 2 Counter value 2

1) Corresponds to the physical channels of the counter functions. See 4.11.17.7.1 "Description of channel assignments".

Data type Value

USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Counter mode 00 Edge counters
01 AB encoder
11 Up/down counter
2-7 Reserved -

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Configure calculation of internal counters

Name:
CfO_Counter1configReg0 to CfO_Counter4configReg0 ("counter 1")
CfO_Counter1configReg1 to CfO_Counter4configReg1 ("counter 2")
The calculation of the internal "counter1" and "counter2" registers can be configured in these registers. For infor-
mation on using these internal registers, see 4.11.17.12.6.1 "Counter value calculation".
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 counter 1 - use 0 0 is added instead of "counter 1"
1 "counter 1" is used for addition
1 counter 1 - sign 0 The sign of the "counter 1" register is not changed for addition
1 The sign of the "counter 1" register is reversed for addition
2 counter 2 - use 0 0 is added instead of "counter 2"
1 "counter 2" is used for addition
3 counter 2 - sign 0 The sign of the "counter 2" register is not changed for addition
1 The sign of the "counter 2" register is reversed for addition
4-7 Reserved -

Examples of calculation configurations

0b00000001 = 0x01 Only the "counter1 - use" bit is set, entering the contents of the "counter" (edge of counter event channel 1)
directly in the counter register.
0b00000011 = 0x03 "counter 1 - use" and "counter1 - sign" bits are set. The sign is changed so that the counter register counts in
the negative direction.
0b00001101 = 0x0d Edges on counter input channel 1 increase the value in the counter register. Edges on counter input channel 2
decrease the value in the counter register. This value is the best setting for the modes "AB encoder" and "Up/
down counter".

Offset value for referencing

Name:
CfO_Counter1PresetValue1 to CfO_Counter4PresetValue1
CfO_Counter1PresetValue1_32Bit to CfO_Counter4PresetValue1_32Bit (SW_reference_counter1)
CfO_Counter1PresetValue2 to CfO_Counter4PresetValue2
CfO_Counter1PresetValue2_32Bit to CfO_Counter4PresetValue2_32Bit (SW_reference_counter2)
These registers can be used to define an offset value for referencing. This value is copied to the internal
SW_reference_counter register of the respective counter register.
Data type Value
INT -32,768 to 32,767
DINT -2,147,483,648 to 2,147,483,647

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Counter register

Name:
Different names are used for these 8 registers depending on their function.
These 8 registers show the results of the counter value calculation for the respective register. Depending on the
function, this corresponds to either the encoder position or the counter value.
For information on the relationship between physical channels and counter registers, see 4.11.17.12.6 "Counters
and encoders" and 4.11.17.7.1 "Description of channel assignments"
Counter 1 - Counter channel 1
Counter register Function Name
1 AB encoders ABEncoder01
ABR encoders ABREncoder01
Up/down counters Counter01
Event counters EventCounter01
2 Event counters EventCounter02

Counter 1 - Counter channel 2

Counter register Function Name
1 AB encoders ABEncoder02
Up/down counters Counter02
Event counters EventCounter03
2 Event counters EventCounter04

Counter 2 - Counter channel 1

Counter register Function Name
1 AB encoders ABEncoder03
ABR encoders ABREncoder02
Up/down counters Counter03
Event counters EventCounter05
2 Event counters EventCounter06

Counter 2 - Counter channel 2

Counter register Function Name
1 AB encoders ABEncoder04
Up/down counters Counter04
Event counters EventCounter07
2 Event counters EventCounter08

Data type Value Information

INT -32,768 to 32,767 Encoder position or counter value
DINT1) -2,147,483,648 Encoder position or counter value
to 2,147,483,647

1) Only in function model 1

Status of the ABR encoder

Name:
StatusABR01 to StatusABR02
The referencing status of the ABR encoder is shown in this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Reserved 0
2 Bit is always 1 after the first reference pulse. 0 No reference pulses have occurred since the start of referenc-
ing.
1 The first reference pulse has occurred.
3 State change when referencing is complete 0 or 1 State change when referencing is complete
4 Bit is always 1 after the first reference pulse. 0 No reference pulses have occurred since the start of referenc-
ing.
1 The first reference pulse has occurred.
5-7 Continuous counter xxx Increased with each reference pulse

Examples of possible values

0b00000000 = 0x00 Referencing OFF or homing procedure already active
0b00111100 = 0x3C First reference complete, reference value applied in the "ABREncoder0" register
0bxxx11100 = 0xxB Bits 5 to 7 are changed with each reference pulse
0bxxx1x100 = 0xxx Bits changed continuously with the setting continuous referencing. With every reference pulse, the reference
value is applied to the "ABREncoder0" register

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Configure ABR referencing mode

Name:
ReferenceModeABR01 to ReferenceModeABR02
The bits in this register are used to configure the reaction to the configured reference pulse.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Sets the referencing mode 00 Referencing OFF
01 Single shot referencing
10 Reserved
11 Continuous referencing
2-5 Reserved -
6-7 Reserved 11 Must always be 11!

This results in the following values:

0b00000000 = 0x00 Referencing OFF
0b11000001 = 0xC1 Single shot referencing → When starting over after the referencing process is complete, the value 0x00 must
be written to start again. Wait until the "StatusABR" register also takes on the value 0x00, then the value 0xC1
can be written again.
0b11000011 = 0xC3 Continuous referencing → Referencing takes place automatically with every reference pulse

4.11.17.12.6.4 Comparator functions

The ABR and AB encoders and the up/down counter have a comparator function. It always works the same and
is described here globally for all three.
The comparators are implemented in software form. They do not work actively but rather passively, i.e. the com-
parison is only carried out when an event is received. The event received is forwarded along the TRUE or FALSE
branch depending on the status of the comparator condition. An event function like this generally also offers a latch
for the TRUE and FALSE branch to save the value used for the comparator at the time of the event.

Comparator modes

Comparator functions can be operated in 4 different modes.

• Off
Events are ignored.
• Single
The event function is executed once and then disables itself automatically. To re-enable it, the "event
function mode" must be changed, preferably to "off" and then to the desired mode. This setting allows a
hardware latch to be simulated.
• State change
The event function only responds when the comparator status has changed, i.e. from false to true (or vice
versa). Only the first event for each status is processed, e.g. the first "true" of a sequence of events with the
comparator condition "true". After the event function is enabled, the first incoming event is used to determine
the starting status and therefore not forwarded. This setting allows a hardware comparator to be simulated.
• Continuous
Each incoming event is forwarded to the true or false branch depending on the comparator condition. This
setting allows event filters to be created.

Configure event ID for comparator

Name:
CfO_Counter1event0IDwr to CfO_Counter4event0IDwr (event function 1)
CfO_Counter1event1IDwr to CfO_Counter4event1IDwr (event function 2)
This register holds the event ID that should trigger the counter event function. For a list of all possible event IDs,
see 4.11.17.12.5.1 "List of event IDs"
Data type Value Information
INT 192 to 7,489 ID of counter event function

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Configure calculation of comparator

Name:
CfO_Counter1event0config to CfO_Counter4event0config (event function 1)
CfO_Counter1event1config to CfO_Counter4event1config (event function 2)
These registers are used to configure the counter event function for the respective counter function.
Bits 0 to 3 configure the calculation of the comparison or to latch the value. This calculation is similar to the calcu-
lation of the counter register (see 4.11.17.12.6.1 "Counter value calculation")
Bits 8 to 13 can be used to limit the number of bits used for the comparison. A mask is calculated as 2n - 1 and
linked with an "AND" operation. This makes it possible to generate a comparator pulse every 2n increments.
Data type Value
UINT See bit structure.

Bit structure:
Bit Description Value Information
0 counter 1 - use 0 0 is added instead of "counter 1"
1 "counter 1" is used for addition
1 counter 1 - sign 0 The sign of the "counter 1" register is not changed for addition
1 The sign of the "counter 1" register is reversed for addition
2 counter 2 - use 0 0 is added instead of "counter 2"
1 "counter 2" is used for addition
3 counter 1 - sign 0 The sign of the "counter 2" register is not changed for addition
1 The sign of the "counter 2" register is reversed for addition
4-7 Reserved -
8 - 13 Number of bits for comparator mask x The mask value is calculated as 2n-1, where n is value set in
these bits. Default: 0
14 Reserved -
15 Margin comparator mode 0 MarginComparator >= (Current position - OriginComparator)
1 MarginComparator > (Current position - OriginComparator)

Configure mode and latching of comparator function

Name:
CfO_Counter1event0mode to CfO_Counter4event0mode (event function 1)
CfO_Counter1event1mode to CfO_Counter4event1mode (event function 2)
In these registers you can set the mode for the comparator function and optional copying of the latched registers.
Comparator functions can be operated in 4 different modes. For a description, see "Comparator modes".
Bits 4 to 7 can be used to define hardware referencing actions.
Based on these bits, the values of the internal absolute value counters "abs1" and "abs2" can be copied to the re-
spective "HW_reference_counter" register at every counter event (see 4.11.17.12.6.1 "Counter value calculation").
This function can be used to reference the counter values directly in the hardware.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Comparator mode 0 Off
1 Single
2 State change
3 Continuous
2-3 Reserved -
4 Copy abs1 counter value 0 No action
1 When event is FALSE → hardware reference counter 1 = abs1
5 Copy abs2 counter value 0 No action
1 When event is FALSE → hardware reference counter 2 = abs2
6 Copy abs1 counter value 0 No action
1 When event is TRUE → hardware reference counter 1 = abs1
7 Copy abs2 counter value 0 No action
1 When event is TRUE → hardware reference counter 2 = abs2

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Comparator origin

Name:
OriginComparator01 to OriginComparator02 (ABR encoder)
OriginComparator01 and OriginComparator03 (AB encoder and up/down counter)
This register is available for the AB and ABR encoders and the up/down counters.
It defines the position value at which the respective configured comparator output channel is set.
Data type Value Information
INT -32,768 to 32,767 Comparator window origin, 16-bit
DINT -2,147,483,648 Comparator window origin, 32-bit
to 2,147,483,647

Width of the comparator

Name:
MarginComparator01 to MarginComparator02 (ABR encoder)
MarginComparator01 and MarginComparator03 (AB encoder and up/down counter)
This register is available for the AB and ABR encoders and the up/down counters.
It defines the width of the comparator window in the positive direction.
Data type Value Information
INT -32,768 to 32,767 Width of comparator window, 16-bit
DINT -2,147,483,648 to 2,147,483,647 Width of comparator window, 32-bit

Read latch position or counter value

Name:
Different names are used for these 4 registers depending on their function.
If the comparator returns "TRUE", then the current counter value is latched and copied to these registers. The
calculation of the comparator value used for the latch can be configured in the "CfO_Counter[x]event[y]config"
register.
Counter 1 - Latch 1
Event function Function Name
1 AB encoders Latch01AB01
Up/down counters Latch01Counter01
2 AB encoders Latch02AB01
ABR encoders Latch01ABR01
Up/down counters Latch02Counter01

Counter 1 - Latch 2
Event function Function Name
1 AB encoders Latch01AB02
Up/down counters Latch01Counter02
2 AB encoders Latch02AB02
Up/down counters Latch02Counter02

Counter 2 - Latch 1
Event function Function Name
1 AB encoders Latch01AB03
Up/down counters Latch01Counter03
2 AB encoders Latch02AB03
ABR encoders Latch01ABR02
Up/down counters Latch02Counter03

Counter 2 - Latch 2
Event function Function Name
1 AB encoders Latch01AB04
Up/down counters Latch01Counter04
2 AB encoders Latch02AB04
Up/down counters Latch02Counter04

Data type Value Information

INT -32,768 to 32,767 Latched encoder position or counter value
DINT1) -2,147,483,648 Latched encoder position or counter value
to 2,147,483,647

1) Only in function model 1

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4.11.17.12.7 SSI encoder interface

The module has 2 SSI encoders available, supported directly in the hardware. Two 24 V output channels are set
for each SSI encoder and cannot be changed. (See also 4.11.17.7.1 "Description of channel assignments")
When using the SSI encoder, the corresponding clock channel can be configured in the 4.11.17.12.4.1
"CfO_CFGchannel" register as "Channel-specific" and "Push/Pull".
Encoder Data channel Clock channel
SSI1 1 2
SSI2 5 6

4.11.17.12.7.1 SSI event functions

Each of the two SSI encoders consists of an event function and an event input. The SSI cycle is started when an
event is received on this input.

Information:
The SSI event function is not linked to an event by default, i.e. SSI functions are disabled.
Two events are sent from the SSI encoder interface..
• An "SSI valid" event is triggered immediately after the end of the SSI cycle if a new counter value is available.
• The "SSI ready" event then shows when the monoflop time has expired (tp in SSI encoder timing diagram).
This is the earliest that the next SSI cycle can be started.
SSI encoder - Timing diagram
SSI cycle

Clock 1 2 3 4 5 6 n

Data

MSB LSB MSB

0
tp

SSI valid
SSI start event SSI ready

Configure event ID for SSI

Name:
CfO_SSI1event0IDwr to CfO_SSI2event0IDwr
This register holds the event ID that should start the SSI cycle. For a list of all possible event IDs, see 4.11.17.12.5.1
"List of event IDs"
Normally this register is set to network event 225 "AOSISOP"- This ensures that the new encoder position is
available at the next "I/O → Synchronous Frame" transfer. Check the SSI transfer time and the X2X cycle time,
because the SSI cycle must be completed within this time.
Data type Value Information
INT 192 to 7,233 ID of event function

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Configure SSI

Name:
CfO_SSI1cfg to CfO_SSI2cfg
This configuration register is used to set the coding, the clock rate and the number of bits. Default = 0. This must
be set once using an acyclic write command.
Data type Value
UINT See bit structure.

Bit structure:
Bit Name Value Information
0-5 SSI value valid bits x
6-7 Clock rate 00 1 MHz
01 500 kHz
10 250 kHz
11 125 kHz
8 - 13 SSI number of bits x Number of bits including leading zeros
14 Reserved 0
15 Keying 0 Binary coding
1 Gray coding

SSI advanced configuration

Name:
ConfigAdvanced01 to ConfigAdvanced02
This configuration register is used to set the coding, the clock rate, the number of bits and the monostable multivi-
brator settings. Default = 0. This must be set once using an acyclic write command.
It only differs from "CfO_SSI1cfg" by data length and additional monostable multivibrator testing.
Data type Value
UDINT See bit structure.

Bit structure:
Bit Name Value Information
0-5 SSI value valid bits x
6-7 Clock rate 00 1 MHz
01 500 kHz
10 250 kHz
11 125 kHz
8 - 13 SSI number of bits x Number of bits including leading zeros
14 Reserved 0
15 Keying 0 Binary coding
1 Gray coding
16 - 17 Monostable multivibrator check 00 Check OFF, no additional clock bit
01 Check set to High level
10 Check set to Low level
11 Level is clocked but ignored
18 - 31 Reserved 0

Enable SSI event function

Name:
CfO_SSI1control to CfO_SSI2control
The two SSI encoder events can be enabled/disabled using this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Event: SSI valid 0 Not sent
1 Sent
1 Event: SSI ready 0 Not sent
1 Sent
2-7 Reserved -

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Read SSI position

Name:
SSIEncoder01 to SSIEncoder02
The last transferred SSI position can be read out from this register. The SSI encoder value is displayed as a 32-
bit position value. This position value is generated synchronously with the X2X cycle.
Data type Value Information
UDINT 0 to 4,294,967,295 Last SSI position transferred

4.11.17.12.7.2 SSI comparator condition

The module has an assigned comparator function for the SSI function. These consist of:
• Event ID that triggers the comparator function
• The window comparator
• Latch register for saving the counter value
When the comparator function is complete, event ID 7232 to7489 (see 4.11.17.12.5.1 "List of event IDs") is sent.

Configure event ID for SSI comparator

Name:
CfO_SSI1eventIDwr to CfO_SSI2eventIDwr
This register holds the event ID that should start the SSI comparator function. For a list of all possible event IDs,
see 4.11.17.12.5.1 "List of event IDs"
Data type Value Information
INT 192 to 7,233 ID of comparator function

Configure the mode of the SSI comparator function

Name:
CfO_SSI1event0mode to CfO_SSI2event0mode
This register can be used to configure the mode of the comparator function.
Comparator functions can be operated in 4 different modes. For a description, see "Comparator modes".
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Comparator mode 0 Off
1 Single
2 State change
3 Continuous
2-7 Reserved -

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Configure calculation of SSI comparator

Name:
CfO_SSI1event0config and CfO_SSI2event0config
The calculation of the position value used for the comparator can be configured in this register.
The window comparator condition is calculated as follows:
counter_window_value = ssi_counter & (2^ssi_data_bits - 1)
diff = counter_window_value – origin_comparator
if ((diff & (2^(comparator_mask)-1)) <= margin_comparator)
condition = True;
else
condition = False;
Data type Value
UINT See bit structure.

Bit structure:
Bit Description Value Information
0-5 SSI data bits x Number of data bits used for masking
6-7 Reserved -
8 - 13 Comparator mask x The mask value is calculated from 2n-1, where n is the value
configured in SSI data bits. Default: 0
14 Comparator mode 0 MarginComparator >= SSI position - OriginComparator
1 MarginComparator > SSI position - OriginComparator

Origin of the SSI comparator

Name:
OriginComparator01_SSI to OriginComparator02_SSI
This register contains the origin of the window comparator.
Data type Value Information
UDINT 0 to 4,294,967,295 Origin of the window comparator.

Width of the SSI comparator

Name:
MarginComparator01_SSI to MarginComparator02_SSI
This register provides the width of the window comparator.
Data type Value Information
UDINT 0 to 4,294,967,295 Width of the SSI window comparator

Read SSI latch position

Name:
Latch01SSI01 to Latch01SSI02
If the SSI window comparator returns "True", then the current SSI position is latched and saved in this register.
Data type Value Information
UDINT 0 to 4,294,967,295 Latched SSI position

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4.11.17.12.8 PWM - Pulse width modulation

The module has 4 PWM functions available, supported directly by the hardware. A 24 V output channel is set for
each PWM encoder and cannot be changed. (See also 4.11.17.7.1 "Description of channel assignments")
When using the PWM function, the corresponding channel can be configured in the 4.11.17.12.4.1
"CfO_CFGchannel" register as "Channel-specific".
PWM function Channel
PWM1 2
PWM2 4
PWM3 6
PWM4 8

4.11.17.12.8.1 Configure PWM prescaler

Name:
CfO_PWM0prescaler to CfO_PWM3prescaler
The length of the PWM cycle is configured using this register. The base is a 48 MHz clock, which can be changed
(divided) using the setting in this register. One PWM cycle consists of 1,000 of the resulting clocks after they have
been divided. The period length of the PWM cycle is calculated as follows:
prescale
PWM_cycle = 1000 [s]
48,000,000
Data type Value Information
UINT 2 to 65,535 Prescaler for PWM cycle

4.11.17.12.8.2 Output PWM values

Name:
PWMOutput02, PWMOutput04, PWMOutput06, PWMOutput08
In this register, a configuration is made for the percentage of the PWM cycle (in 1/10 % steps) that the PWM output
is logical 1, i.e. ON.
Data type Value Information
UINT 0 to 1,000 PWM output always off
2 to 999 Turn on time in 1/10% steps
1,000 PWM output always on

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4.11.17.12.9 Time measurement function

The module has a time measurement function for each I/O channel. It can be configured separately for rising and
falling edges on each channel.
A starting edge can be configured for each time measurement function. When a configured starting edge occurs,
the value of the internal timer is saved in a FIFO. This FIFO holds up to 16 elements. When the actual trigger edge
occurs, the difference in time between the starting edge and the triggered edge is copied to the respective register.
Bits 8 to 11 "Previous start edge" of the 4.11.17.12.9.2 "CfO_EdgeTimeFallingMode" and 4.11.17.12.9.3
"CfO_EdgeTimeRisingMode" registers can be used to define which detected starting edge from the FIFO should
be used to calculate the difference. Additionally, when the trigger edge occurs, the counter clocked internally us-
ing bits 12 to 15 "Time measurement resolution are copied to the 4.11.17.12.9.10 "TimeStampFallingCH" and
4.11.17.12.9.11 "TimeStampRisingCH" registers.

Information:
The time measurement function is an extension of edge detection, so all of the channels used must
be configured there.

4.11.17.12.9.1 Enable time measurement function

Name:
CfO_EdgeTimeglobalenable
This register enables/disables the time measurement function for the entire module.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Time measurement function 0 Disabled for entire module
1 Enabled for entire module
1-7 Reserved -

4.11.17.12.9.2 Configure time measurement function for the falling edge

Name:
CfO_EdgeTimeFallingMode01 to CfO_EdgeTimeFallingMode08
These registers can be used to configure the time measurement function for the falling edge of the respective
channel.
Data type Value
UINT See bit structure.

Bit structure:
Bit Description Value Information
0-3 Selects the channel for the starting edge 0 Channel 1
...
7 Channel 8
4 Selects the edge for the starting edge 0 The falling edge of the channel configured in bits 0 to 3 serves
as the starting edge.
1 The rising edge of the channel configured in bits 0 to 3 serves
as the starting edge.
5-6 Reserved -
7 Trigger 0 Triggered1)
1 Continuous2)
8 - 11 Previous start edge 0 to 15 The value determines which entry in the starting edge FIFO
should be used to calculate the time difference.
12 - 15 Time measurement resolution 0 8 Mhz
1 4 Mhz
2 2 Mhz
3 1 Mhz
4 500 kHz
5 250 kHz
6 125 kHz
7 625 kHz

1) The time measurement is triggered by the corresponding bit in the 4.11.17.12.9.5 "TriggerRisingCH" register.
2) Time measurement runs continuously and is triggered at every edge.

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4.11.17.12.9.3 Configure time measurement function for the rising edge

Name:
CfO_EdgeTimeRisingMode01 to CfO_EdgeTimeRisingMode08
These registers can be used to configure the time measurement function for the rising edge of the respective
channel.
Data type Value
UINT See bit structure.

Bit structure:
Bit Description Value Information
0-3 Selects the channel for the starting edge 0 Channel 1
...
7 Channel 8
4 Selects the edge for the starting edge 0 The falling edge of the channel configured in bits 0 to 3 serves
as the starting edge.
1 The rising edge of the channel configured in bits 0 to 3 serves
as the starting edge.
5-6 Reserved -
7 Trigger 0 Triggered1)
1 Continuous2)
8 - 11 Previous start edge 0 to 15 The value determines which entry in the starting edge FIFO
should be used to calculate the time difference.
12 - 15 Time measurement resolution 0 8 Mhz
1 4 Mhz
2 2 Mhz
3 1 Mhz
4 500 kHz
5 250 kHz
6 125 kHz
7 625 kHz

1) The time measurement is triggered by the corresponding bit in the 4.11.17.12.9.5 "TriggerRisingCH" register.
2) Time measurement runs continuously and is triggered at every edge.

4.11.17.12.9.4 Trigger falling edge detection

Name:
TriggerFallingCH01 to TriggerFallingCH08
If bit 7 "Trigger" is cleared in the 4.11.17.12.9.2 "CfO_EdgeTimeFallingMode" register, then detection of a falling
edge on the respective input can be triggered using the respective bit in this register. After a bit has been set, the
next falling edge on the corresponding channel is detected.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 TriggerFallingCH01 0 Falling edges on channel 1 are not detected
1 The next falling edge on channel 1 will be detected
... ...
7 TriggerFallingCH08 0 Falling edges on channel 8 are not detected
1 The next falling edge on channel 8 will be detected

4.11.17.12.9.5 Trigger rising edge detection

Name:
TriggerRisingCH01 to TriggerRisingCH08
If the "Continued/triggered" bit is cleared in the 4.11.17.12.9.3 "CfO_EdgeTimeRisingMode" register, then detection
of a rising edge on the respective input can be triggered using the respective bit in this register. After a bit has been
set, the next rising edge on the corresponding channel is detected.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 Trigger rising edge - Channel 1 0 Rising edges on channel 1 are not detected
1 The next rising edge on channel 1 will be detected
... -
7 Trigger rising edge - Channel 8 0 Rising edges on channel 8 are not detected
1 The next rising edge on channel 8 will be detected

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4.11.17.12.9.6 Show first falling trigger edge

Name:
BusyTriggerFallingCH01 to BusyTriggerFallingCH08
If edges are triggered via the bits in the 4.11.17.12.9.4 "TriggerFallingCH" register, then a set bit in this register
indicates that no falling edges have been detected on the respective channel since the corresponding bit was
set in the "TriggerFallingCH" register. If a falling edge occurs on the respective channel, then the corresponding
BusyTriggerFalling bit is cleared.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 BusyTriggerFallingCH01 0 Falling edge detected on channel 1
1 Module waiting for a falling edge on channel 1
... ...
7 BusyTriggerFallingCH08 0 Falling edge detected on channel 8
1 Module waiting for a falling edge on channel 8

4.11.17.12.9.7 Show first rising trigger edge

Name:
BusyTriggerRisingCH01 to BusyTriggerRisingCH08
If edges are triggered via the bits in the 4.11.17.12.9.5 "TriggerRisingCH" register, then a set bit in this register
indicates that no rising edges have been detected on the respective channel since the corresponding bit was
set in the "TriggerRisingCH" register. If a rising edge occurs on the respective channel, then the corresponding
BusyTriggerRising bit is cleared.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 BusyTriggerRisingCH01 0 Rising edge detected on channel 1
1 Module waiting for a rising edge on channel 1
... ...
7 BusyTriggerRisingCH08 0 Rising edge detected on channel 8
1 Module waiting for a rising edge on channel 8

4.11.17.12.9.8 Count falling trigger edges

Name:
CountFallingCH01 to CountFallingCH08
These registers contain cyclic counters that are incremented with every detected falling edge on the respective
channel.
Data type Value Information
USINT 0 to 255 Counter for falling edges

4.11.17.12.9.9 Count rising trigger edges

Name:
CountRisingCH01 to CountRisingCH08
These registers contain cyclic counters that are incremented with every detected rising edge on the respective
channel.
Data type Value Information
USINT 0 to 255 Counter for rising edges

4.11.17.12.9.10 Time stamp of falling edge

Name:
TimeStampFallingCH01 to TimeStampFallingCH08
When a falling edge occurs on the respective channel, the current counter value of the module timer is copied
to these registers.
Data type Value Information
UINT 0 to 65,535 Time stamp for rising edges

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 X20 system modules • Counter modules • X20DC4395

4.11.17.12.9.11 Time stamp of the rising edge

Name:
TimeStampRisingCH01 to TimeStampRisingCH08
When a rising edge occurs on the respective channel, the current counter value of the module timer is copied to
these registers.
Data type Value Information
UINT 0 to 65,535 Time stamp for rising edges

4.11.17.12.9.12 Time difference of falling edge

Name:
TimeDiffFallingCH01 to TimeDiffFallingCH08
When a falling edge occurs on the respective channel, the time difference compared to the starting edge configured
in bit 4 of the 4.11.17.12.9.2 "CfO_EdgeTimeFallingMode" register is copied to this register.
Data type Value Information
UINT 0 to 65,535 Time difference from starting edge

4.11.17.12.9.13 Time difference of rising edge

Name:
TimeD-iffRisingCH01 to TimeDiffRisingCH08
When a rising edge occurs on the respective channel, the time difference compared to the starting edge configured
in bit 4 of the 4.11.17.12.9.3 "CfO_EdgeTimeRisingMode" register is copied to this register.
Data type Value Information
UINT 0 to 65,535 Time difference from starting edge

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X20 system modules • Counter modules • X20DC4395

4.11.17.12.10 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
128 μs

4.11.17.12.11 Maximum cycle time

The maximum cycle time defines how far the bus cycle can be increased without internal counter overflows causing
module malfunctions.
Minimum cycle time
16 ms

4.11.17.12.12 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
128 μs

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 X20 system modules • X20 CPUs

4.12 X20 CPUs

The X20 CPUs are a powerful addition to the X20 system. With the exception of the entry level model, all CPUs are
based on Intel ATOM™ processors, which are available in various performance classes. Each CPU is available
with either one or three slots for interface modules.

Flexible communication options onboard

In addition to one CompactFlash, two USB and two RS232 interfaces, there are also two independent Ethernet
interfaces. One of them is a standard gigabit Ethernet interface for TCP/IP data traffic.
Behind the second female RJ45 connector, there is a pure Fast Ethernet interface (100 Mbit/s) that serves as a
POWERLINK interface. This means that no additional POWERLINK interface is needed to operate a POWERLINK
network.
Easy maintenance
A special feature of the CPU modules is that they are operated fan-free. The CPU can be operated throughout
the full temperature range of the X20 system (-25 to 60°C). Depending on the model, derating may be required
over 55°C.
The built-in SRAM buffer battery can be exchanged during operation as long as local regulations allow it. When the
battery is exchanged with the power off, the SRAM is buffered for approximately 1 minute. This makes maintenance
work very simple.

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X20 system modules • X20 CPUs • Brief information

4.12.1 Brief information

Product ID Short description on page
X20CP1483 X20 CPU, x86 100 MHz Intel compatible, 32 MB DRAM, 128 kB SRAM, removable application memory: Com- 896
pactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20
locking plate (right) X20AC0SR1 included, order application memory separately.
X20CP1483-1 X20 CPU, x86 100 MHz Intel compatible, 64 MB DRAM, 128 kB SRAM, removable application memory: Com- 896
pactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20
locking plate (right) X20AC0SR1 included, order application memory separately.
X20CP1583 X20 CPU, ATOM 333 MHz compatible, 128 MB DDR2 RAM, 1 MB SRAM, removable application memory: 913
CompactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and
X20 locking plate (right) X20AC0SR1 included, order application memory separately.
X20CP1584 X20 CPU, ATOM 0.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: CompactFlash, 913
1 insert slot for X20 interface modules, 2 USB ports, 1 RS232 interface, 1 Ethernet interface 10/100/1000 Base-
T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20 locking plate
(right) X20AC0SR1 included, order application memory separately.
X20CP1585 X20 CPU, ATOM 1.0 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: CompactFlash, 913
1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface 10/100/1000
Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20 locking
plate (right) X20AC0SR1 included, order application memory separately.
X20CP1586 X20 CPU, ATOM 1.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: CompactFlash, 913
1 insert slot for X20 interface modules, 2 USB ports, 1 RS232 interface, 1 Ethernet interface 10/100/1000 Base-
T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot cover and X20 locking plate
(right) X20AC0SR1 included, order application memory separately.
X20CP3583 X20 CPU, ATOM 333 MHz compatible, 128 MB DDR2 RAM, 1 MB SRAM, removable application memory: 917
CompactFlash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet inter-
face 10/100/1000 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal block, slot covers
and X20 locking plate (right) X20AC0SR1 included, order application memory separately.
X20CP3584 X20 CPU, ATOM 0.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: Compact- 917
Flash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000BASE-T, 1 POWERLINK interface, incl. supply module, 1 terminal block, slot cover and X20 locking
plate (right) included, order application memory separately.
X20CP3585 X20 CPU, ATOM 1.0 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: Compact- 917
Flash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000BASE-T, 1 POWERLINK interface, incl. supply module, 1 terminal block, slot cover and X20 locking
plate (right) included, order application memory separately.
X20CP3586 X20 CPU, ATOM 1.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory: Compact- 917
Flash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 Ethernet interface
10/100/1000BASE-T, 1 POWERLINK interface, incl. supply module, 1 terminal block, slot cover and X20 locking
plate (right) included, order application memory separately.

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4.12.2 X20CP1483 and X20CP1483-1

4.12.2.1 General information

The x86 100 MHz-compatible X20CP1483 is the entry-level X20 CPU. With an optimal price/performance ratio, it
has the same basic features as the larger CPUs and offers sufficient performance for most standard applications.
USB and Ethernet are included in every CPU. In addition, every CPU has a POWERLINK connection for real-time
communication.
In addition, a multi-purpose slot is provided for an additional interface module.
• Intel x86 100 MHz-compatible with additional I/O processor
• Ethernet, POWERLINK V1/V2 and USB onboard
• Modular expansion of interfaces
• CompactFlash as removable application memory
• Fanless
• Extremely compact

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4.12.2.2 Order data - X20CP148x

Model number Short description

X20 CPUs
X20CP1483 X20 CPU, x86 100 MHz Intel compatible, 32 MB DRAM, 128 kB SRAM, removable application
memory: CompactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232
interface, 1 Ethernet interface 10/100 Base-T, 1 POWERLINK interface, incl. supply module, 1
X20TB12 terminal block, slot cover and X20 locking plate (right) X20AC0SR1 included, order
application memory separately.
X20CP1483-1 X20 CPU, x86 100 MHz Intel compatible, 64 MB DRAM, 128 kB SRAM, removable application
memory: CompactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232
interface, 1 Ethernet interface 10/100 Base-T, 1 POWERLINK interface, incl. supply module, 1
X20TB12 terminal block, slot cover and X20 locking plate (right) X20AC0SR1 included, order
application memory separately.
Required accessories
CompactFlash-cards
0CFCRD.0128E.01 CompactFlash 128 MB WD extended temp.
0CFCRD.0512E.01 CompactFlash 512 MB WD extended temp.
0SDMIC.0512E.01 Micro SD Card 512MB extended Temp.
5CFCRD.016G-06 CompactFlash 16 GB B&R (SLC)
5CFCRD.0512-06 CompactFlash 512 MB B&R (SLC)
5CFCRD.1024-06 CompactFlash 1 GB B&R (SLC)
5CFCRD.2048-06 CompactFlash 2 GB B&R (SLC)
5CFCRD.4096-06 CompactFlash 4 GB B&R (SLC)
5CFCRD.8192-06 CompactFlash 8 GB B&R (SLC)
Optional accessories
Batteries
0AC201.91 Lithium batteries 4 pcs., 3 V / 950 mAh button cell We hereby state that the lithium cells contained
in this shipment qualify as "partly regulated". Handle with care. If the package is damaged, inspect
the cells, repack intact cells and protect the cells against short circuit. For emergency information,
call RENATA SA at +41 61 319 28 27.
4A0006.00-000 Lithium battery, 3 V / 950 mAh, button cell

Table 258: X20CP1483, X20CP1483-1 - Order data

Included in delivery
Model number Short description
4A0006.00-000 Backup battery (see also section 4.12.2.18 "Exchanging the lithium battery")
- Interface module slot covers
X20AC0SR1 X20 locking plate, right
X20TB12 X20 terminal block, 12-pin, 24 V keyed

Table 259: X20 CPUs - Contents of delivery

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4.12.2.3 Technical data - X20CP148x

Product ID X20CP1483 X20CP1483-1

Short description
Interfaces 1x RS232, 1x Ethernet, 1x POWERLINK (V1/V2), 2x USB, 1x X2X Link
System module CPU
General information
Cooling Fanless
B&R ID code 0xA239 0xAEC5
Status indicators CPU function, overtemperature, Ethernet, POWERLINK, CompactFlash, battery
Diagnostics
Battery Yes, using status LED and software
CPU function Yes, using status LED
CompactFlash Yes, using status LED
Ethernet Yes, using status LED
POWERLINK Yes, using status LED
Overtemperature Yes, using status LED
ACOPOS capability Yes
Visual Components support Yes
Power consumption without memory card, interface 6.0 W
module and USB
Internal power consumption of the X2X Link and I/
O supply 1)
Bus 1.42 W
Internal I/O 0.6 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
IF1 - IF2 Yes
IF1 - IF3 Yes
IF1 - IF4 No
IF1 - IF5 No
IF1 - IF6 Yes
IF2 - IF3 Yes
IF2 - IF4 Yes
IF2 - IF5 Yes
IF2 - IF6 Yes
IF3 - IF4 Yes
IF3 - IF5 Yes
IF3 - IF6 Yes
IF4 - IF5 No
IF4 - IF6 Yes
IF5 - IF6 Yes
PLC - IF1 No
PLC - IF2 Yes
PLC - IF3 Yes
PLC - IF4 No
PLC - IF5 No
PLC - IF6 Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes -
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
CPU and X2X Link supply
Input voltage 24 VDC -15% / +20%
Input current Max. 2.2 A
Fuse Integrated, cannot be replaced
Reverse polarity protection Yes
X2X Link supply output
Nominal output power 7.0 W
Parallel operation Yes 2)
Redundant operation Yes
Input I/O supply
Input voltage 24 VDC -15% / +20%
Fuse Required line fuse: Max. 10 A, slow-blow
Output I/O supply
Rated output voltage 24 VDC
Permitted contact load 10.0 A
Supply - General information
Status indicators Overload, operating status, module status, RS232 data transfer

Table 260: X20CP1483, X20CP1483-1 - Technical data

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Product ID X20CP1483 X20CP1483-1
Diagnostics
RS232 data transfer Yes, using status LED
Module run/error Yes, using status LED and software
Overload Yes, using status LED and software
Electrical isolation
I/O feed - I/O supply No
CPU/X2X Link feed - CPU/X2X Link supply Yes
Controller
CompactFlash slot 1
Real-time clock Nonvolatile, 1 s resolution, -10 to 10 ppm accuracy at 25°C
FPU Yes
Processor
Type x86 100 comp.
Clock frequency 100 MHz
L2 cache -
L1 cache for data and program code 16 kB
Integrated I/O processor Processes I/O data points in the background
Modular interface slots 1
Remanent variables Max. 32 kB 3)
Shortest task class cycle time 1 ms
Typical instruction cycle time 0.09 μs
Data buffering
Battery monitoring Yes
Lithium battery At least 3 years
Standard memory
RAM 32 MB SDRAM 64 MB SDRAM
User RAM 128 kB SRAM 4)
Interfaces
IF1 interface
Signal RS232
Design Connection made using 12-pin X20TB12 terminal block
Max. distance 900 m
Transfer rate Max. 115.2 kbit/s
IF2 interface
Signal Ethernet
Design 1x shielded RJ45 port
Cable length Max. 100 m between two stations (segment length)
Transfer rate 10/100 Mbit/s
Transmission
Physical interfaces 10 BASE-T/100 BASE-TX
Half-duplex Yes
Full-duplex Yes
Autonegotiation Yes
Auto-MDI / MDIX Yes
IF3 interface
Fieldbus POWERLINK (V1/V2) managing or controlled node
Type Type 4 5)
Design 1x shielded RJ45 port
Cable length Max. 100 m between two stations (segment length)
Transfer rate 100 Mbit/s
Transmission
Physical interfaces 100 BASE-TX
Half-duplex Yes
Full-duplex No
Autonegotiation Yes
Auto-MDI / MDIX Yes
IF4 interface
Type USB 1.1
Design Type A
IF5 interface
Type USB 1.1
Design Type A
IF6 interface
Fieldbus X2X Link master
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20

Table 260: X20CP1483, X20CP1483-1 - Technical data

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Product ID X20CP1483 X20CP1483-1
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order application memory (CompactFlash) separately
Backup battery included in delivery
X20 locking plate (right) included in delivery
X20 terminal block (12-pin) included in delivery
Interface module slot covers included in delivery
Dimensions
Width 150 mm
Height 99 mm
Depth 85 mm
Weight 300 g

Table 260: X20CP1483, X20CP1483-1 - Technical data

1) The specified values are maximum values. The exact calculation is included as a data sheet in the module documentation and can be downloaded from
the B&R website.
2) In parallel operation, only 75% of the rated power can be assumed. It is important to make sure that all power supplies operating in parallel are switched
on and off at the same time.
3) Can be configured in Automation Studio.
4) Minus configured remanent variables.
5) See the POWERLINK help system under "General information, Hardware - IF/LS".

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4.12.2.4 X20 CPUs - Status LEDs

Figure LED Color Status Description

R/E Green On Application running
Blinking Boot mode system start:
CPU initializing the application, all bus systems and I/O modules1)
Red On SERVICE mode
Blinking The "R/E" LED blinks red and the "RDY/F" LED blinks yellow when there is a
license violation.
Double flash BOOT mode (during firmware update)1)
RDY/F Yellow On SERVICE or BOOT mode
Blinking The "RDY/F" LED blinks yellow and the "R/E" LED blinks red when there is a
license violation.
S/E Green/Red Status/Error LED. The statuses of this LED are described in section 4.12.2.4.1
""S/E" LED".
PLK Green On A link to the POWERLINK peer station has been established.
Blinking A link to the POWERLINK peer station has been established. The LED blinks
when Ethernet activity is taking place on the bus.
ETH Green On A link to the peer station has been established.
Blinking A link to the peer station has been established. Indicates Ethernet activity is
taking place on the bus.
CF Green On CompactFlash inserted and detected
Yellow On CompactFlash read/write access
DC Yellow On CPU power supply OK
Red On Backup battery empty

Table 261: X20 CPUs - CPU status indicators

1) The process can take several minutes depending on the configuration.

4.12.2.4.1 "S/E" LED

The Status/Error LED is a green/red dual LED. The LED status can have different meanings depending on the
operating mode.

4.12.2.4.1.1 Ethernet mode

In this mode, the interface is operated as an Ethernet interface.

Green - Status Description
On Operates the interface as an Ethernet interface

Table 262: Status/Error LED - Ethernet operating mode

4.12.2.4.1.2 POWERLINK V1
Status LED Status of the POWERLINK node
Green Red
On Off The POWERLINK node is running with no errors.
Off On A system error has occurred. The error type can be read using the PLC logbook. An irreparable problem has occurred. The system
cannot properly carry out its tasks. This state can only be changed by resetting the module.
Blinking alternately The POWERLINK managing node has failed. This error code can only occur when operated as a controlled node. This means
that the configured node number lies within the range 0x01 - 0xFD.
Off Blinking System failure. The red blinking LED signals an error code (see section 4.12.2.4.2 "System failure error codes").
Off Off Module is:
• Off
• Starting up
• Not configured correctly in Automation Studio
• Defective

Table 263: Status/Error LED - POWERLINK V1 operating mode

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4.12.2.4.1.3 POWERLINK V2
Red - Error Description
On The module is in an error mode (failed Ethernet frames, increased number of collisions on the network, etc.).
If an error occurs in the following states, then the green LED blinks over the red LED:
• PRE_OPERATIONAL_1
• PRE_OPERATIONAL_2
• READY_TO_OPERATE

Status
Green
t
Error
Red
t
"S/E" LED

t
Note:
The LED blinks red several times immediately after startup. This is not an error.

Table 264: Status/Error LED as Error LED - POWERLINK operating mode

Green - Status Description
Off Mode
The module is in NOT_ACTIVE mode or:
• Switched off
• Starting up
• Not configured correctly in Automation Studio
• Defective

Managing node (MN)

The bus is monitored for POWERLINK frames. If a corresponding frame is not received within the defined time frame
(timeout), then the module will immediately enter PRE_OPERATIONAL_1 mode.
If POWERLINK communication is detected before the time expires, however, then the MN will not be started.

Controlled node (CN)

The bus is monitored for POWERLINK frames. If a corresponding frame is not received within the defined time frame
(timeout), then the module will immediately enter BASIC_ETHERNET mode. If POWERLINK communication is detected
before this time passes, however, then the module will immediately go into PRE_OPERATIONAL_1 mode.
Green flickering (approx. 10 Hz) Mode
The module is in BASIC_ETHERNET mode. The interface is being operated as an Ethernet TCP/IP interface.

Managing node (MN)

This state can only be changed by resetting the module.

Controlled node (CN)

If POWERLINK communication is detected while in this state, the module will transition to the PRE_OPERATIONAL_1
state.
Single flash (approx. 1 Hz) Mode
The module is in PRE_OPERATIONAL_1 mode.

Managing node (MN)

The MN starts "reduced cycle" operation. Cyclic communication is not yet taking place.

Controlled node (CN)

The module can be configured by the MN in this state. The CN waits until it receives an SoC frame and then transitions
to the PRE_OPERATIONAL_2 state.
An LED lit red in this state indicates a failure of the MN.
Double flash (approx. 1 Hz) Mode
The module is in PRE_OPERATIONAL_2 mode.

Managing node (MN)

The MN begins cyclic communication (cyclic input data is not yet evaluated).
The CNs are configured in this state.

Controlled node (CN)

The module can be configured by the MN in this state. A command then changes the state to READY_TO_OPERATE.
An LED lit red in this mode indicates a failure of the MN.
Triple flash (approx. 1 Hz) Mode
The module is in the READY_TO_OPERATE state.

Managing node (MN)

Cyclic and asynchronous communication. The received PDO data is ignored.

Controlled node (CN)

The module configuration is complete. Normal cyclic and asynchronous communication. The PDO data sent corresponds
to the PDO mapping. Cyclic data is not yet evaluated, however.
An LED lit red in this mode indicates a failure of the MN.

Table 265: Status/Error LED as Status LED - POWERLINK operating mode

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Green - Status Description
On Mode
The module is in PRE_OPERATIONAL_2 mode. PDO mapping is active and cyclic data is being evaluated.
Blinking (approx. 2.5 Hz) Mode
The module is in STOPPED mode.

Managing node (MN)

This status is not possible for the MN.

Controlled node (CN)

No output data is produced or input data supplied. It is only possible to enter or leave this mode after the MN has given
the appropriate command.

Table 265: Status/Error LED as Status LED - POWERLINK operating mode

Triple flash
200 200 200 200 200 1000

Double flash
200 200 200 1000

Single flash
200 1000

Blinking
200 200

Flickering
All times in ms

Figure 288: LED status indicators - Blinking patterns

4.12.2.4.2 System failure error codes

Incorrect configuration or defective hardware can cause a system failure error code.
The error code is indicated by the red Error LED using four switch-on phases. The switch-on phases have a duration
of either 150 ms or 600 ms. The error code is output cyclically every 2 seconds.
Error description Error code indicated by red status LED
RAM error: ● ● ● - Pause ● ● ● - Pause
The module is defective and must be replaced.
Hardware error: - ● ● - Pause - ● ● - Pause
The module or a system component is defective and must be replaced.

Table 266: Status/Error ("S/E") LED - System failure error codes

Key: ● ... 150 ms
- ... 600 ms
Pause ... 2 second delay

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4.12.2.5 LED status indicators for the integrated power supply

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Double flash LED indicates one of the following states:
• The X2X Link supply for the power supply is overloaded
• I/O supply too low
• Input voltage for X2X Link supply too low
e+r Red on / Green single flash Invalid firmware
S Yellow Off No RS232 activity
On The LED lights up when data is being sent or received via the RS232 interface.
l Red Off The X2X Link supply is within the valid limits
On The X2X Link supply for the power supply is overloaded

Table 267: X20 CPUs - LED status indicators for the integrated power supply

4.12.2.6 Operating and connection elements

Mounting rail Operating mode-

lock switch CompactFlash LED status indicators

IF6 - X2X Link

IF1 - RS232

Terminal block for CPU

and I/O supply,
RS232 interface

Ethernet IF2 - Ethernet Battery IF4 - USB Slot for

Station address IF5 - USB Interface
IF3 - POWERLINK modules
Reset button

Figure 289: X20 CPUs - Operating elements for X20CP1483 and X20CP1483-1

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4.12.2.7 Slot for application memory

These CPUs require application memory in order to operate. The application memory is provided in the form of a
CompactFlash card. It is not included with the CPUs, but must be ordered separately as an accessory.

Information:
The CompactFlash card must not be removed during operation.

4.12.2.8 Operating mode switch

The operating mode switch is used to set the operating mode.

Figure 290: X20 CPUs - Operating mode switch

Switch position Operating mode Description
BOOT BOOT When the switch is in this position, the default B&R Automation Runtime (AR) system is started
and the runtime system can be installed via the online interface (B&R Automation Studio). User
flash memory is deleted only after the download begins.
RUN RUN RUN mode
DIAG DIAGNOSE Boots the CPU in diagnostic mode. Program sections in User RAM and User FlashPROM are
not initialized. After diagnostic mode, the CPU always boots with a cold restart.

Table 268: X20 CPUs - Operating modes

4.12.2.9 Reset button

Reset button

Figure 291: X20CPUs - Reset button

The reset button is located below the USB interfaces on the bottom of the housing. It can be pressed with any
small pointed object (e.g. paper clip). Pressing the reset button triggers a hardware reset, which means:
• All application programs are stopped.
• All outputs are set to zero.
The PLC then boots into Service mode by default. The boot mode that follows after pressing the reset button can
be defined in Automation Studio.

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 X20 system modules • X20 CPUs • X20CP1483 and X20CP1483-1

4.12.2.10 CPU supply

A power supply is integrated in the X20 CPUs. It has a feed for the CPU, the X2X Link and the internal I/O supply.
Supply for the CPU and X2X Link is electrically isolated.

Pinout

r e
SI

Reserved

Reserved Reserved

+24 V CP/X2X L. +24 V I/O

+24 V CP/X2X L. +24 V I/O

GND GND

Figure 292: X20 CPUs - Pinout of the integrated power supply

Connection examples

PS

10 A slow-blow
CPU / X2X Link + + I/O
supply _ _ supply

+24 VDC
GND

Figure 293: Connection example with 2 separate supplies

PS

Jumper

10 A slow-blow
+ I/O
_ supply

+24 VDC
GND

Figure 294: Connection example with a supply and jumper

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4.12.2.11 RS232 interface (IF1)

The non-electrically isolated RS232 interface is primarily intended to serve as an online interface for communication
with the programming device.

r e
SI

TX RX

GND

Figure 295: X20 CPUs - Pinout of the RS232 interface (IF1)

4.12.2.12 Ethernet interface (IF2)

Figure 296: X20 CPUs - Ethernet interface (IF2)

The IF2 is executed as the10 BASE-T / 100 BASE-TX interface.
The INA2000 station number of the Ethernet interface is set using the two hex switches.
Information about cabling X20 modules with an Ethernet interface can be found on the B&R website in the module's
download section at www.br-automation.com.

Information:
The Ethernet interface (IF2) is not suited for POWERLINK (see 4.12.2.13 "POWERLINK interface (IF3)").

Pinout
Interface Pinout
Pin Ethernet
1 TXD Transmit data
2 TXD\ Transmit data\
1
3 RXD Receive data
4 Termination
5 Termination
6 RXD\ Receive data\
Shielded RJ45 7 Termination
8 Termination

Table 269: Pinout

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4.12.2.13 POWERLINK interface (IF3)

POWERLINK V1
Switch position Description
0x00 Operation as managing node.
0x01 - 0xFD Node number of the POWERLINK node. Operation as controlled node.
0xFE - 0xFF Reserved, switch position not permitted

Table 270: POWERLINK V1 - Node numbers

POWERLINK V2
Switch position Description
0x00 Reserved, switch position not permitted
0x01 - 0xEF Node number of the POWERLINK node. Operation as a controlled node.
0xF0 Operation as a managing node.
0xF1 - 0xFF Reserved, switch position not permitted

Table 271: POWERLINK node number

Ethernet mode
Starting with Automation Studio Version V2.5.3 and with Automation Runtime V2.90, the interface can be operated
as an Ethernet interface.
The INA2000 station number can be set using the B&R Automation Studio software.

Pinout

Figure 297: X20 CPUs - POWERLINK interface (IF3)

Information about cabling X20 modules with an Ethernet interface can be found on the B&R website in the module's
download section at www.br-automation.com.
Interface Pinout
Pin Ethernet
1 RXD Receive data
2 RXD\ Receive data\
1
3 TXD Transmit data
4 Termination
5 Termination
6 TXD\ Transmit data\
Shielded RJ45 7 Termination
8 Termination

Table 272: Pinout

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4.12.2.14 USB interfaces (IF4 and IF5)

Figure 298: X20 CPUs - USB interfaces (IF4 and IF5)

IF4 and IF5 are USB interfaces. The connection is made using a USB 1.1 interface.
The USB interfaces can only be used for devices approved by B&R (e.g. floppy disk drive, DiskOnKey or dongle).

Information:
USB interfaces cannot be used for online communication with a programming device.

4.12.2.15 Slots for interface modules

The CPUs have one or three slots for interface modules.

Various bus and network systems can easily be integrated into the X20 system by selecting the corresponding
interface module.

4.12.2.16 Overtemperature cutoff

To prevent damage, a shut-off/reset is triggered on the CPU when the processor reaches 100°C.
The following errors are entered in the logbook:
Error number Error description
9204 WARNING: System halted because of temperature check
9210 WARNING: Boot by watchdog or manual reset

Table 273: X20 CPUs - Logbook entries after overtemperature cutoff

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4.12.2.17 Data / Real-time clock buffering

The CPUs are buffered by a backup battery. The following areas are buffered:
• Remanent variables
• User RAM
• System RAM
• Real-time clock

Battery monitoring
The battery voltage is checked cyclically. The cyclic load test of the battery does not considerably shorten the
battery life, instead it gives an early warning of weakened buffer capacity.
The status information "Battery OK" is available from the system library function "BatteryInfo" and the CPU's I/
O mapping.

Replacement interval for battery

The battery should be replaced every 4 years. The replacement intervals recommended by B&R reflect the batter-
ies' average service life and operating conditions. It does not represent the maximum buffer duration.

4.12.2.18 Exchanging the lithium battery

The CPUs have a lithium battery. The lithium battery is found in a separate compartment on the bottom of the
module and protected by a cover.
Backup battery data
Model number
4A0006.00-000 1 pcs.
0AC201.91 4 pcs.
Short description Lithium battery, 3 V / 950 mAh, button cell
Storage temperature -20 to 60°C
Storage time Max. 3 years at 30°C
Relative humidity 0 to 95%, non-condensing

Table 274: X20 CPUs - Backup battery data

Important information about the battery exchange

The product design allows the battery to be changed with the PLC switched either on or off. In some countries,
safety regulations do not allow batteries to be changed while the module is switched on. To prevent data loss, the
battery must be changed within 1 min. with the power off.

Warning!
The battery must be replaced by a Typ CR2477N Renata battery only. The use of another battery may
present a risk of fire or explosion.
The battery may explode if handled improperly. Do not recharge, disassemble or dispose of in fire.

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X20 system modules • X20 CPUs • X20CP1483 and X20CP1483-1

Procedure for exreplacing the battery

1. Touch the mounting rail or ground connection (not the power supply!) in order to discharge any electrostatic
charge from your body.
2. Remove the cover for the lithium battery. Do this by sliding it down and away from the CPU.

Figure 299: X20 CPUs - Remove lithium battery cover

3. Remove the battery from the holder (do not use pliers or uninsulated tweezers -> risk of short circuiting). The
battery should not be held by its edges. Insulated tweezers may also be used to remove the battery.
Correct: Incorrect:

Figure 300: X20 CPUs - Correct grip for the battery

4. Insert the new battery with the correct polarity. To do this, lay the battery with the "+" side up on the right part
of the battery holder under the USB interface IF4. Then secure the battery in the holder by pressing above
the left part of the battery holder.
5. Replace the cover.

Information:
Lithium batteries are considered hazardous waste. Used batteries should be disposed of in accordance
with applicable local regulations.

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4.12.2.19 Programming the system flash memory

General information
In order for the application project to be executed on the CPU, the Automation Runtime operating system, the
system components and the application project must be installed on the CompactFlash card.

Creating a CompactFlash using a USB card reader

The easiest way to perform an initial installation is by creating a fully programmed CompactFlash card using a
USB card reader.
1. Creating and configuring a project in Automation Studio
2. In Automation Studio, select Tools / Create CompactFlash
3. In the dialog box that opens, select a CompactFlash card and then generate it
4. Insert the finished CompactFlash into the CPU and turn on the CPU's supply voltage
5. CPU booting

For details about commissioning: See help system under "Automation Software / Getting Started"

Installation over an online connection

The CPUs are delivered with a default B&R Automation Runtime system (with limited functions) already installed.
This runtime system is started in Boot mode (operating mode switch in the BOOT position or no CompactFlash /
invalid CompactFlash inserted). It initializes the Ethernet interface and onboard serial RS232 interface, making it
possible to download a new runtime system.
1. Insert the CompactFlash card and switch on the power to the CPU. When the switch is in the BOOT position,
a new or invalid CompactFlash card starts the CPU with the default B&R Automation Runtime system.
2. Establish a physical online connection between the programming device (PC or industrial PC) and the CPU
(e.g. over an Ethernet network or the RS232 interface).
3. Before you can establish an online connection via Ethernet, the CPU must be assigned an IP address. In
Automation Studio, select Settings from the Online menu and then click on the Browse targets button to
search for B&R target systems on the local network. The CPU should appear in the list. If the CPU has not
already received an IP address from a DHCP server, right-click on it and select Set IP parameters from the
shortcut menu. All necessary network configurations can be made on a temporary basis in this dialog box
(should be identical to the settings defined in the project).
4. Configure online connection in B&R Automation Studio. For details about the configuration: See help system
under "Automation Software / Communication / Online communication"
5. Start the download procedure by selecting the Services command from the Project menu. Then select Trans-
fer Automation Runtime from the pop-up menu. Now follow the instructions provided by B&R Automation
Studio.

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4.12.3 X20CP158x and X20CP358x

4.12.3.1 General information

Based on state-of-the-art Intel® ATOM™ processor technology, X20 CPUs cover a wide spectrum of requirements.
They can be implemented in solutions ranging from standard applications to those requiring the highest levels of
performance.
The series starts with Intel® ATOM™ processor 333 MHz compatible models – X20CP1583 and X20CP3583. With
an optimum price/performance ratio, it has the same basic features as all of the larger CPUs.
The basic model includes USB, Ethernet, POWERLINK V1/V2 and replaceable CompactFlash card. The standard
Ethernet interface is capable of handling communication in the gigabit range. For improved real-time network
performance, the onboard POWERLINK interface supports poll response chaining mode (PRC).
In addition, there are up to three multi-purpose slots for additional interface modules.
• Intel® ATOM™ 1600/1000/600 Performance with integrated I/O processor
• Entry-level CPU is Intel® ATOM™ 333 MHz-compatible with integrated I/O processor
• Ethernet, POWERLINK V1/V2 with poll response chaining and onboard USB
• 1 or 3 slots for modular interface expansion
• CompactFlash as removable application memory
• Up to 512 MB DDR2-SRAM according to performance requirements
• CPU redundancy possible
• Fanless
• Extremely compact

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4.12.3.2 Order data - X20CP158x

Model number Short description

X20 CPUs
X20CP1583 X20 CPU, ATOM 333 MHz compatible, 128 MB DDR2 RAM, 1 MB SRAM, removable application
memory: CompactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 in-
terface, 1 Ethernet interface 10/100/1000 Base-T, 1 POWERLINK interface, incl. supply module,
1 X20TB12 terminal block, slot cover and X20 locking plate (right) X20AC0SR1 included, order
application memory separately.
X20CP1584 X20 CPU, ATOM 0.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory:
CompactFlash, 1 insert slot for X20 interface modules, 2 USB ports, 1 RS232 interface, 1 Ethernet
interface 10/100/1000 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal
block, slot cover and X20 locking plate (right) X20AC0SR1 included, order application memory
separately.
X20CP1585 X20 CPU, ATOM 1.0 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memo-
ry: CompactFlash, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 inter-
face, 1 Ethernet interface 10/100/1000 Base-T, 1 POWERLINK interface, incl. supply module,
1 X20TB12 terminal block, slot cover and X20 locking plate (right) X20AC0SR1 included, order
application memory separately.
X20CP1586 X20 CPU, ATOM 1.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory:
CompactFlash, 1 insert slot for X20 interface modules, 2 USB ports, 1 RS232 interface, 1 Ethernet
interface 10/100/1000 Base-T, 1 POWERLINK interface, incl. supply module, 1 X20TB12 terminal
block, slot cover and X20 locking plate (right) X20AC0SR1 included, order application memory
separately.
Required accessories
CompactFlash-cards
0CFCRD.0128E.01 CompactFlash 128 MB WD extended temp.
0CFCRD.0512E.01 CompactFlash 512 MB WD extended temp.
0SDMIC.0512E.01 Micro SD Card 512MB extended Temp.
5CFCRD.016G-06 CompactFlash 16 GB B&R (SLC)
5CFCRD.0512-06 CompactFlash 512 MB B&R (SLC)
5CFCRD.1024-06 CompactFlash 1 GB B&R (SLC)
5CFCRD.2048-06 CompactFlash 2 GB B&R (SLC)
5CFCRD.4096-06 CompactFlash 4 GB B&R (SLC)
5CFCRD.8192-06 CompactFlash 8 GB B&R (SLC)
Optional accessories
Batteries
0AC201.91 Lithium batteries 4 pcs., 3 V / 950 mAh button cell We hereby state that the lithium cells contained
in this shipment qualify as "partly regulated". Handle with care. If the package is damaged, inspect
the cells, repack intact cells and protect the cells against short circuit. For emergency information,
call RENATA SA at +41 61 319 28 27.
4A0006.00-000 Lithium battery, 3 V / 950 mAh, button cell

Table 275: X20CP1583, X20CP1584, X20CP1585, X20CP1586 - Order data

Included in delivery
Model number Short description
4A0006.00-000 Backup battery (see also section 4.12.3.20 "Exchanging the lithium battery")
- Interface module slot covers
X20AC0SR1 X20 locking plate, right
X20TB12 X20 terminal block, 12-pin, 24 V keyed

Table 276: X20 CPUs - Contents of delivery

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4.12.3.3 Technical data - X20CP158x

Product ID X20CP1583 X20CP1584 X20CP1585 X20CP1586

Short description
Interfaces 1x RS232, 1x Ethernet, 1x POWERLINK (V1/V2), 2x USB, 1x X2X Link
System module CPU
General information
Cooling Fanless
B&R ID code 0xD45B 0xC370 0xC3AE 0xC3B0
Status indicators CPU function, overtemperature, Ethernet, POWERLINK, CompactFlash, battery
Diagnostics
Battery Yes, using status Yes, with status LED Yes, using status Yes, with status LED
LED and software and software status LED and software and software status
CPU function Yes, using status LED
CompactFlash Yes, using status LED
Ethernet Yes, using status LED
POWERLINK Yes, using status LED
Overtemperature Yes, using status LED
CPU redundancy possible No
ACOPOS capability Yes
Visual Components support Yes
Power consumption without interface 8.2 W 8.6 W 8.8 W 9.7 W
module and USB
Internal power consumption of the
X2X Link and I/O supply 1)
Bus 1.42 W
Internal I/O 0.6 W
Additional power dissipation caused -
by the actuators (resistive) [W]
Electrical isolation
IF1 - IF2 Yes
IF1 - IF3 Yes
IF1 - IF4 No
IF1 - IF5 No
IF1 - IF6 Yes
IF2 - IF3 Yes
IF2 - IF4 Yes
IF2 - IF5 Yes
IF2 - IF6 Yes
IF3 - IF4 Yes
IF3 - IF5 Yes
IF3 - IF6 Yes
IF4 - IF5 No
IF4 - IF6 Yes
IF5 - IF6 Yes
PLC - IF1 No
PLC - IF2 Yes
PLC - IF3 Yes
PLC - IF4 No
PLC - IF5 No
PLC - IF6 Yes
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC - Yes
GL Yes
GOST-R Yes
CPU and X2X Link supply
Input voltage 24 VDC -15% / +20%
Input current Max. 1.5 A
Fuse Integrated, cannot be replaced
Reverse polarity protection Yes
X2X Link supply output
Nominal output power 7.0 W 2)
Parallel operation Yes 3)
Redundant operation Yes
Input I/O supply
Input voltage 24 VDC -15% / +20%
Fuse Required line fuse: Max. 10 A, slow-blow
Output I/O supply
Rated output voltage 24 VDC
Permitted contact load 10.0 A
Supply - General information
Status indicators Overload, operating status, module status, RS232 data transfer

Table 277: X20CP1583, X20CP1584, X20CP1585, X20CP1586 - Technical data

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 X20 system modules • X20 CPUs • X20CP158x and X20CP358x
Product ID X20CP1583 X20CP1584 X20CP1585 X20CP1586
Diagnostics
RS232 data transfer Yes, using status LED
Module run/error Yes, using status Yes, with status LED Yes, using status Yes, with status LED
LED and software and software status LED and software and software status
Overload Yes, using status Yes, with status LED Yes, using status Yes, with status LED
LED and software and software status LED and software and software status
Electrical isolation
I/O feed - I/O supply No
CPU/X2X Link feed - CPU/X2X Link Yes
supply
Controller
CompactFlash slot 1
Real-time clock Nonvolatile, 1 s resolution, -10 to 10 ppm accuracy at 25°C
FPU Yes
Processor
Type ATOM™ E620T ATOM™ E640T Atom™ E680T
Clock frequency 333 MHz 0.6 GHz 1.0 GHz 1.6 GHz
L1 cache
Data code 24 kB
Program code 32 kB
L2 cache - 512 kB
Integrated I/O processor Processes I/O data points in the background
Modular interface slots 1
Remanent variables Max. 64 kB 4) Max. 256 kB 4) Max. 1 MB 4)
Shortest task class cycle time 800 µs 400 µs 200 µs 100 µs
Typical instruction cycle time 001 µs 0.0075 µs 00044 µs 0.0027 µs
Data buffering
Battery monitoring Yes
Lithium battery Min. 2 years at 23°C ambient temperature
Standard memory
RAM 128 MB DDR2 SDRAM 256 MB DDR2 SDRAM 512 MB DDR2 SDRAM
User RAM 1 MB SRAM 5)
Interfaces
IF1 interface
Signal RS232
Design Connection made using 12-pin X20TB12 terminal block
Max. distance 900 m
Transfer rate Max. 115.2 kbit/s
IF2 interface
Signal Ethernet
Design 1x shielded RJ45 port
Cable length Max. 100 m between two stations (segment length)
Transfer rate 10/100/1000 Mbit/s
Transmission
Physical interfaces 10 BASE-T/100 BASE-TX/1000 BASE-T
Half-duplex Yes
Full-duplex Yes
Autonegotiation Yes
Auto-MDI / MDIX Yes
IF3 interface
Fieldbus POWERLINK (V1/V2) managing or controlled node
Type Type 4 6) Type 4 7) Type 4 6) Type 4 7)
Design 1x shielded RJ45 port
Cable length Max. 100 m between two stations (segment length)
Transfer rate 100 Mbit/s
Transmission
Physical interfaces 100 BASE-TX
Half-duplex Yes
Full-duplex No
Autonegotiation Yes
Auto-MDI / MDIX Yes
IF4 interface
Type USB 1.1/2.0
Design Type A
IF5 interface
Type USB 1.1/2.0
Design Type A
IF6 interface
Fieldbus X2X Link master
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes

Table 277: X20CP1583, X20CP1584, X20CP1585, X20CP1586 - Technical data

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X20 system modules • X20 CPUs • X20CP158x and X20CP358x
Product ID X20CP1583 X20CP1584 X20CP1585 X20CP1586
Installation at elevations above sea
level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order application memory Order application memory Order application memory Order application memory
(CompactFlash) separately (CompactFlash) separately (CompactFlash) separately (CompactFlash) separately
Backup battery in- Backup battery in- Backup battery in- Backup battery in-
cluded in delivery cluded in delivery cluded in delivery cluded in delivery
X20 locking plate (right) X20 locking plate (right) X20 locking plate (right) X20 locking plate (right)
included in delivery included in delivery included in delivery included in delivery
X20 terminal block (12- X20 terminal block (12- X20 terminal block (12- X20 terminal block (12-
pin) included in delivery pin) included in delivery pin) included in delivery pin) included in delivery
Interface module slot cov- Interface module slot cov- Interface module slot cov- Interface module slot cov-
ers included in delivery ers included in delivery ers included in delivery ers included in delivery
Dimensions
Width 150 mm
Height 99 mm
Depth 85 mm
Weight 400 g

Table 277: X20CP1583, X20CP1584, X20CP1585, X20CP1586 - Technical data

1) The specified values are maximum values. The exact calculation is included as a data sheet in the module documentation and can be downloaded from
the B&R website.
2) When operated at temperatures above 55°C, a derating of the rated output current to 5 W for the X2X Link supply must be taken into consideration.
3) In parallel operation, only 75% of the rated power can be assumed. It is important to make sure that all power supplies operating in parallel are switched
on and off at the same time.
4) Can be configured in Automation Studio.
5) 1 MB SRAM minus the configured remanent variables.
6) See the POWERLINK help system under "General information, Hardware - IF/LS".
7) See the POWERLINK online help documentation under "General information, Hardware - IF/LS".

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4.12.3.4 Order data - X20CP358x

Model number Short description

X20 CPUs
X20CP3583 X20 CPU, ATOM 333 MHz compatible, 128 MB DDR2 RAM, 1 MB SRAM, removable application
memory: CompactFlash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 in-
terface, 1 Ethernet interface 10/100/1000 Base-T, 1 POWERLINK interface, incl. supply module,
1 X20TB12 terminal block, slot covers and X20 locking plate (right) X20AC0SR1 included, order
application memory separately.
X20CP3584 X20 CPU, ATOM 0.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory:
CompactFlash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1
Ethernet interface 10/100/1000BASE-T, 1 POWERLINK interface, incl. supply module, 1 terminal
block, slot cover and X20 locking plate (right) included, order application memory separately.
X20CP3585 X20 CPU, ATOM 1.0 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory:
CompactFlash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1
Ethernet interface 10/100/1000BASE-T, 1 POWERLINK interface, incl. supply module, 1 terminal
block, slot cover and X20 locking plate (right) included, order application memory separately.
X20CP3586 X20 CPU, ATOM 1.6 GHz, 512 MB DDR2 RAM, 1 MB SRAM, removable application memory:
CompactFlash, 3 insert slots for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1
Ethernet interface 10/100/1000BASE-T, 1 POWERLINK interface, incl. supply module, 1 terminal
block, slot cover and X20 locking plate (right) included, order application memory separately.
Required accessories
CompactFlash-cards
0CFCRD.0128E.01 CompactFlash 128 MB WD extended temp.
0CFCRD.0512E.01 CompactFlash 512 MB WD extended temp.
0SDMIC.0512E.01 Micro SD Card 512MB extended Temp.
5CFCRD.016G-06 CompactFlash 16 GB B&R (SLC)
5CFCRD.0512-06 CompactFlash 512 MB B&R (SLC)
5CFCRD.1024-06 CompactFlash 1 GB B&R (SLC)
5CFCRD.2048-06 CompactFlash 2 GB B&R (SLC)
5CFCRD.4096-06 CompactFlash 4 GB B&R (SLC)
5CFCRD.8192-06 CompactFlash 8 GB B&R (SLC)
Optional accessories
Batteries
0AC201.91 Lithium batteries 4 pcs., 3 V / 950 mAh button cell We hereby state that the lithium cells contained
in this shipment qualify as "partly regulated". Handle with care. If the package is damaged, inspect
the cells, repack intact cells and protect the cells against short circuit. For emergency information,
call RENATA SA at +41 61 319 28 27.
4A0006.00-000 Lithium battery, 3 V / 950 mAh, button cell

Table 278: X20CP3583, X20CP3584, X20CP3585, X20CP3586 - Order data

Included in delivery
Model number Short description
4A0006.00-000 Backup battery (see also section 4.12.3.20 "Exchanging the lithium battery")
- Interface module slot covers
X20AC0SR1 X20 locking plate, right
X20TB12 X20 terminal block, 12-pin, 24 V keyed

Table 279: X20 CPUs - Contents of delivery

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4.12.3.5 X20CP358x - Technical data

Product ID X20CP3583 X20CP3584 X20CP3585 X20CP3586

Short description
Interfaces 1x RS232, 1x Ethernet, 1x POWERLINK (V1/V2), 2x USB, 1x X2X Link
System module CPU
General information
Cooling Fanless
B&R ID code 0xD45C 0xC3AD 0xC3AF 0xBF2B
Status indicators CPU function, overtemperature, Ethernet, POWERLINK, CompactFlash, battery
Diagnostics
Battery Yes, using status LED and software
CPU function Yes, using status LED
CompactFlash Yes, using status LED
Ethernet Yes, using status LED
POWERLINK Yes, using status LED
Overtemperature Yes, using status LED
CPU redundancy possible No Yes
ACOPOS capability Yes
Visual Components support Yes
Power consumption without interface 8.2 W 8.6 W 8.8 W 9.7 W
module and USB
Internal power consumption of the
X2X Link and I/O supply 1)
Bus 1.42 W
Internal I/O 0.6 W
Additional power dissipation caused -
by the actuators (resistive) [W]
Electrical isolation
IF1 - IF2 Yes
IF1 - IF3 Yes
IF1 - IF4 No
IF1 - IF5 No
IF1 - IF6 Yes
IF2 - IF3 Yes
IF2 - IF4 Yes
IF2 - IF5 Yes
IF2 - IF6 Yes
IF3 - IF4 Yes
IF3 - IF5 Yes
IF3 - IF6 Yes
IF4 - IF5 No
IF4 - IF6 Yes
IF5 - IF6 Yes
PLC - IF1 No
PLC - IF2 Yes
PLC - IF3 Yes
PLC - IF4 No
PLC - IF5 No
PLC - IF6 Yes
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC - Yes
GL Yes
GOST-R Yes
CPU and X2X Link supply
Input voltage 24 VDC -15% / +20%
Input current Max. 1.5 A
Fuse Integrated, cannot be replaced
Reverse polarity protection Yes
X2X Link supply output
Nominal output power 7.0 W 2)
Parallel operation Yes 3)
Redundant operation Yes
Input I/O supply
Input voltage 24 VDC -15% / +20%
Fuse Required line fuse: Max. 10 A, slow-blow
Output I/O supply
Rated output voltage 24 VDC
Permitted contact load 10.0 A
Supply - General information
Status indicators Overload, operating status, module status, RS232 data transfer

Table 280: X20CP3583, X20CP3584, X20CP3585, X20CP3586 - Technical data

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Product ID X20CP3583 X20CP3584 X20CP3585 X20CP3586
Diagnostics
RS232 data transfer Yes, using status LED
Module run/error Yes, using status LED and software
Overload Yes, using status LED and software
Electrical isolation
I/O feed - I/O supply No
CPU/X2X Link feed - CPU/X2X Link Yes
supply
Controller
CompactFlash slot 1
Real-time clock Nonvolatile, 1 s resolution, -10 to 10 ppm accuracy at 25°C
FPU Yes
Processor
Type ATOM™ E620T ATOM™ E640T Atom™ E680T
Clock frequency 333 MHz 0.6 GHz 1 GHz 1.6 GHz
L1 cache
Data code 24 kB
Program code 32 kB
L2 cache - 512 kB
Integrated I/O processor Processes I/O data points in the background
Modular interface slots 3
Remanent variables Max. 64 kB 4) Max. 256 kB 4) Max. 1 MB 4)
Shortest task class cycle time 800 µs 400 µs 200 µs 100 µs
Typical instruction cycle time 001 µs 0.0075 µs 0.0044 µs 0.0027 µs
Data buffering
Battery monitoring Yes
Lithium battery Min. 2 years at 23°C ambient temperature
Standard memory
RAM 128 MB DDR2 SDRAM 256 MB DDR2 SDRAM 512 MB DDR2 SDRAM
User RAM 1 MB SRAM 5)
Interfaces
IF1 interface
Signal RS232
Design Connection made using 12-pin X20TB12 terminal block
Max. distance 900 m
Transfer rate Max. 115.2 kbit/s Max. 1152 kbit/s
IF2 interface
Signal Ethernet
Design 1x shielded RJ45 port
Cable length Max. 100 m between two stations (segment length)
Transfer rate 10/100/1000 Mbit/s
Transmission
Physical interfaces 10 BASE-T/100 BASE-TX/1000 BASE-T
Half-duplex Yes
Full-duplex Yes
Autonegotiation Yes
Auto-MDI / MDIX Yes
IF3 interface
Fieldbus POWERLINK (V1/V2) managing or controlled node
Type Type 4 6)
Design 1x shielded RJ45 port
Cable length Max. 100 m between two stations (segment length)
Transfer rate 100 Mbit/s
Transmission
Physical interfaces 100 BASE-TX
Half-duplex Yes
Full-duplex No
Autonegotiation Yes
Auto-MDI / MDIX Yes
IF4 interface
Type USB 1.1/2.0
Design Type A
IF5 interface
Type USB 1.1/2.0
Design Type A
IF6 interface
Fieldbus X2X Link master
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea
level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m

Table 280: X20CP3583, X20CP3584, X20CP3585, X20CP3586 - Technical data

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Product ID X20CP3583 X20CP3584 X20CP3585 X20CP3586
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order application memory Order application memory (CompactFlash) separately
(CompactFlash) separately Backup battery included in delivery
Backup battery in- X20 locking plate (right) included in delivery
cluded in delivery X20 terminal block (12-pin) included in delivery
X20 locking plate (right) Interface module slot covers included in delivery
included in delivery
X20 terminal block (12-
pin) included in delivery
Interface module slot cov-
ers included in delivery
Dimensions
Width 200 mm
Height 99 mm
Depth 85 mm
Weight 470 g

Table 280: X20CP3583, X20CP3584, X20CP3585, X20CP3586 - Technical data

1) The specified values are maximum values. The exact calculation is included as a data sheet in the module documentation and can be downloaded from
the B&R website.
2) When operated at temperatures above 55°C, a derating of the rated output current to 5 W for the X2X Link supply must be taken into consideration.
3) In parallel operation, only 75% of the rated power can be assumed. It is important to make sure that all power supplies operating in parallel are switched
on and off at the same time.
4) Can be configured in Automation Studio.
5) 1 MB SRAM minus the configured remanent variables.
6) See the POWERLINK help system under "General information, Hardware - IF/LS".

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4.12.3.6 X20 CPUs - Status LEDs

Figure LED Color Status Description

R/E Green On Application running
Blinking Boot mode system start:
CPU initializing the application, all bus systems and I/O modules1)
Red On SERVICE mode
Blinking The "R/E" LED blinks red and the "RDY/F" LED blinks yellow when there is a
license violation.
Double flash BOOT mode (during firmware update)1)
RDY/F Yellow On SERVICE or BOOT mode
Blinking The "RDY/F" LED blinks yellow and the "R/E" LED blinks red when there is a
license violation.
S/E Green/Red Status/Error LED. The statuses of this LED are described in section 4.12.3.6.1
""S/E" LED".
PLK Green On A link to the POWERLINK peer station has been established.
Blinking A link to the POWERLINK peer station has been established. The LED blinks
when Ethernet activity is taking place on the bus.
ETH Green On A link to the peer station has been established.
Blinking A link to the peer station has been established. Indicates Ethernet activity is
taking place on the bus.
CF Green On CompactFlash inserted and detected
Yellow On CompactFlash read/write access
DC Yellow On CPU power supply OK
Red On Backup battery empty

Table 281: X20 CPUs - CPU status indicators

1) The process can take several minutes depending on the configuration.

4.12.3.6.1 "S/E" LED

The Status/Error LED is a green/red dual LED. The LED status can have different meanings depending on the
operating mode.

4.12.3.6.1.1 Ethernet mode

In this mode, the interface is operated as an Ethernet interface.

Green - Status Description
On Operates the interface as an Ethernet interface

Table 282: Status/Error LED - Ethernet operating mode

4.12.3.6.1.2 POWERLINK V1
Status LED Status of the POWERLINK node
Green Red
On Off The POWERLINK node is running with no errors.
Off On A system error has occurred. The error type can be read using the PLC logbook. An irreparable problem has occurred. The system
cannot properly carry out its tasks. This state can only be changed by resetting the module.
Blinking alternately The POWERLINK managing node has failed. This error code can only occur when operated as a controlled node. This means
that the configured node number lies within the range 0x01 - 0xFD.
Off Blinking System failure. The red blinking LED signals an error code (see section 4.12.3.6.2 "System failure error codes").
Off Off Module is:
• Off
• Starting up
• Not configured correctly in Automation Studio
• Defective

Table 283: Status/Error LED - POWERLINK V1 operating mode

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4.12.3.6.1.3 POWERLINK V2
Red - Error Description
On The module is in an error mode (failed Ethernet frames, increased number of collisions on the network, etc.).
If an error occurs in the following states, then the green LED blinks over the red LED:
• PRE_OPERATIONAL_1
• PRE_OPERATIONAL_2
• READY_TO_OPERATE

Status
Green
t
Error
Red
t
"S/E" LED

t
Note:
The LED blinks red several times immediately after startup. This is not an error.

Table 284: Status/Error LED as Error LED - POWERLINK operating mode

Green - Status Description
Off Mode
The module is in NOT_ACTIVE mode or:
• Switched off
• Starting up
• Not configured correctly in Automation Studio
• Defective

Managing node (MN)

The bus is monitored for POWERLINK frames. If a corresponding frame is not received within the defined time frame
(timeout), then the module will immediately enter PRE_OPERATIONAL_1 mode.
If POWERLINK communication is detected before the time expires, however, then the MN will not be started.

Controlled node (CN)

The bus is monitored for POWERLINK frames. If a corresponding frame is not received within the defined time frame
(timeout), then the module will immediately enter BASIC_ETHERNET mode. If POWERLINK communication is detected
before this time passes, however, then the module will immediately go into PRE_OPERATIONAL_1 mode.
Green flickering (approx. 10 Hz) Mode
The module is in BASIC_ETHERNET mode. The interface is being operated as an Ethernet TCP/IP interface.

Managing node (MN)

This state can only be changed by resetting the module.

Controlled node (CN)

If POWERLINK communication is detected while in this state, the module will transition to the PRE_OPERATIONAL_1
state.
Single flash (approx. 1 Hz) Mode
The module is in PRE_OPERATIONAL_1 mode.

Managing node (MN)

The MN starts "reduced cycle" operation. Cyclic communication is not yet taking place.

Controlled node (CN)

The module can be configured by the MN in this state. The CN waits until it receives an SoC frame and then transitions
to the PRE_OPERATIONAL_2 state.
An LED lit red in this state indicates a failure of the MN.
Double flash (approx. 1 Hz) Mode
The module is in PRE_OPERATIONAL_2 mode.

Managing node (MN)

The MN begins cyclic communication (cyclic input data is not yet evaluated).
The CNs are configured in this state.

Controlled node (CN)

The module can be configured by the MN in this state. A command then changes the state to READY_TO_OPERATE.
An LED lit red in this mode indicates a failure of the MN.
Triple flash (approx. 1 Hz) Mode
The module is in the READY_TO_OPERATE state.

Managing node (MN)

Cyclic and asynchronous communication. The received PDO data is ignored.

Controlled node (CN)

The module configuration is complete. Normal cyclic and asynchronous communication. The PDO data sent corresponds
to the PDO mapping. Cyclic data is not yet evaluated, however.
An LED lit red in this mode indicates a failure of the MN.

Table 285: Status/Error LED as Status LED - POWERLINK operating mode

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Green - Status Description
On Mode
The module is in PRE_OPERATIONAL_2 mode. PDO mapping is active and cyclic data is being evaluated.
Blinking (approx. 2.5 Hz) Mode
The module is in STOPPED mode.

Managing node (MN)

This status is not possible for the MN.

Controlled node (CN)

No output data is produced or input data supplied. It is only possible to enter or leave this mode after the MN has given
the appropriate command.

Table 285: Status/Error LED as Status LED - POWERLINK operating mode

Triple flash
200 200 200 200 200 1000

Double flash
200 200 200 1000

Single flash
200 1000

Blinking
200 200

Flickering
All times in ms

Figure 301: LED status indicators - Blinking patterns

4.12.3.6.2 System failure error codes

Incorrect configuration or defective hardware can cause a system failure error code.
The error code is indicated by the red Error LED using four switch-on phases. The switch-on phases have a duration
of either 150 ms or 600 ms. The error code is output cyclically every 2 seconds.
Error description Error code indicated by red status LED
RAM error: ● ● ● - Pause ● ● ● - Pause
The module is defective and must be replaced.
Hardware error: - ● ● - Pause - ● ● - Pause
The module or a system component is defective and must be replaced.

Table 286: Status/Error ("S/E") LED - System failure error codes

Key: ● ... 150 ms
- ... 600 ms
Pause ... 2 second delay

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4.12.3.7 LED status indicators for the integrated power supply

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Double flash LED indicates one of the following states:
• The X2X Link supply for the power supply is overloaded
• I/O supply too low
• Input voltage for X2X Link supply too low
e+r Red on / Green single flash Invalid firmware
S Yellow Off No RS232 activity
On The LED lights up when data is being sent or received via the RS232 interface.
l Red Off The X2X Link supply is within the valid limits
On The X2X Link supply for the power supply is overloaded

Table 287: X20 CPUs - LED status indicators for the integrated power supply

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4.12.3.8 Operating and connection elements

X20CP158x
Mounting rail Operating mode-
lock switch CompactFlash LED status indicators

IF6 - X2X Link

IF1 - RS232

Terminal block for CPU

and I/O supply,
RS232 interface

Ethernet IF2 - Ethernet Battery IF4 - USB Slot for

Station address IF5 - USB Interface
IF3 - POWERLINK modules
Reset button

Figure 302: X20 CPUs - Operating elements for X20CP158x

X20CP358x
Mounting rail Operating mode-
lock switch CompactFlash LED status indicators

IF6 - X2X Link

IF1 - RS232

Ethernet IF2 - Ethernet Battery IF4 - USB Slots for Terminal block for CPU
Station address IF5 - USB interface and I/O supply,
IF3 - POWERLINK modules RS232 interface
Reset button

Figure 303: X20 CPUs - Operating elements for X20CP358x

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4.12.3.9 Slot for application memory

These CPUs require application memory in order to operate. The application memory is provided in the form of a
CompactFlash card. It is not included with the CPUs, but must be ordered separately as an accessory.

Information:
The CompactFlash card must not be removed during operation.

4.12.3.10 Operating mode switch

The operating mode switch is used to set the operating mode.

Figure 304: X20 CPUs - Operating mode switch

Switch position Operating mode Description
BOOT BOOT When the switch is in this position, the default B&R Automation Runtime (AR) system is started
and the runtime system can be installed via the online interface (B&R Automation Studio). User
flash memory is deleted only after the download begins.
RUN RUN RUN mode
DIAG DIAGNOSE Boots the CPU in diagnostic mode. Program sections in User RAM and User FlashPROM are
not initialized. After diagnostic mode, the CPU always boots with a cold restart.

Table 288: X20 CPUs - Operating modes

4.12.3.11 Reset button

Reset button

Figure 305: X20CPUs - Reset button

The reset button is located below the USB interfaces on the bottom of the housing. It can be pressed with any
small pointed object (e.g. paper clip). Pressing the reset button triggers a hardware reset, which means:
• All application programs are stopped.
• All outputs are set to zero.
The PLC then boots into Service mode by default. The boot mode that follows after pressing the reset button can
be defined in Automation Studio.

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4.12.3.12 CPU supply

A power supply is integrated in the X20 CPUs. It has a feed for the CPU, the X2X Link and the internal I/O supply.
Supply for the CPU and X2X Link is electrically isolated.

Pinout

r e
SI

Reserved

Reserved Reserved

+24 V CP/X2X L. +24 V I/O

+24 V CP/X2X L. +24 V I/O

GND GND

Figure 306: X20 CPUs - Pinout of the integrated power supply

Connection examples

PS

10 A slow-blow
CPU / X2X Link + + I/O
supply _ _ supply

+24 VDC
GND

Figure 307: Connection example with 2 separate supplies

PS

Jumper

10 A slow-blow
+ I/O
_ supply

+24 VDC
GND

Figure 308: Connection example with a supply and jumper

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4.12.3.13 RS232 interface (IF1)

The non-electrically isolated RS232 interface is primarily intended to serve as an online interface for communication
with the programming device.

r e
SI

TX RX

GND

Figure 309: X20 CPUs - Pinout of the RS232 interface (IF1)

4.12.3.14 Ethernet interface (IF2)

Figure 310: X20 CPUs - Ethernet interface (IF2)

The IF2 is executed as the10 BASE-T / 100 BASE-TX / 1000 BASE-T gigabit Ethernet interface.
The INA2000 station number of the Ethernet interface is set using the two hex switches.
Information about cabling X20 modules with an Ethernet interface can be found on the B&R website in the module's
download section at www.br-automation.com.

Information:
The Ethernet interface (IF2) is not suitable for POWERLINK (see 4.12.3.15 "POWERLINK interface
(IF3)").

Pinout
Interface Pinout
Pin Ethernet
1 D1+ Data 1+
2 D1- Data 1-
1
3 D2+ Data 2+
4 D3+ Data 3+
5 D3- Data 3-
6 D2- Data 2-
Shielded RJ45 port 7 D4+ Data 4+
8 D4- Data 4-

Table 289: Pinout for RJ45 port

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4.12.3.15 POWERLINK interface (IF3)

POWERLINK V1
Switch position Description
0x00 Operation as managing node.
0x01 - 0xFD Node number of the POWERLINK node. Operation as controlled node.
0xFE - 0xFF Reserved, switch position not permitted

Table 290: POWERLINK V1 - Node numbers

POWERLINK V2
Switch position Description
0x00 Reserved, switch position not permitted
0x01 - 0xEF Node number of the POWERLINK node. Operation as a controlled node.
0xF0 Operation as a managing node.
0xF1 - 0xFF Reserved, switch position not permitted

Table 291: POWERLINK node number

Ethernet mode
In this mode, the interface is operated as an Ethernet interface. The INA2000 station number can be set using the
B&R Automation Studio software.

Pinout

Information about cabling X20 modules with an Ethernet interface can be found on the B&R website in the module's
download section at www.br-automation.com.
Pin Assignment
1 RxD Receive data
2 RxD\ Receive data\
3 TxD Transmit data
4 Termination
5 Termination
6 TxD\ Transmit data\
7 Termination
8 Termination

Table 292: X20 CPUs - Pinout for POWERLINK interface (IF3)

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4.12.3.16 USB interfaces (IF4 and IF5)

Figure 311: X20 CPUs - USB interfaces (IF4 and IF5)

IF4 and IF5 are USB interfaces. The connection is made using a USB 1.1/2.0 interface.
The USB interfaces can only be used for devices approved by B&R (e.g. floppy disk drive, DiskOnKey or dongle).

Information:
USB interfaces cannot be used for online communication with a programming device.

4.12.3.17 Slots for interface modules

The CPUs have one or three slots for interface modules.

Various bus and network systems can easily be integrated into the X20 system by selecting the corresponding
interface module.

4.12.3.18 Overtemperature cutoff

To prevent damage, the CPU is cut off and reset when the processor reaches 110°C or the circuit board reaches
95°C.
The following errors are entered in the logbook:
Error number Error description
9204 WARNING: System halted because of temperature check
9210 WARNING: Boot by watchdog or manual reset

Table 293: X20 CPUs - Logbook entries after overtemperature cutoff

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4.12.3.19 Data / Real-time clock buffering

The CPUs are buffered by a backup battery. The following areas are buffered:
• Remanent variables
• User RAM
• System RAM
• Real-time clock

Battery monitoring
The battery voltage is checked cyclically. The cyclic load test of the battery does not considerably shorten the
battery life, instead it gives an early warning of weakened buffer capacity.
The status information "Battery OK" is available from the system library function "BatteryInfo" and the CPU's I/
O mapping.

Replacement interval for battery

The battery should be replaced every 4 years. The replacement intervals recommended by B&R reflect the batter-
ies' average service life and operating conditions. It does not represent the maximum buffer duration.

4.12.3.20 Exchanging the lithium battery

The CPUs have a lithium battery. The lithium battery is found in a separate compartment on the bottom of the
module and protected by a cover.
Backup battery data
Model number
4A0006.00-000 1 pcs.
0AC201.91 4 pcs.
Short description Lithium battery, 3 V / 950 mAh, button cell
Storage temperature -20 to 60°C
Storage time Max. 3 years at 30°C
Relative humidity 0 to 95%, non-condensing

Table 294: X20 CPUs - Backup battery data

Important information about the battery exchange

The product design allows the battery to be changed with the PLC switched either on or off. In some countries,
safety regulations do not allow batteries to be changed while the module is switched on. To prevent data loss, the
battery must be changed within 1 min. with the power off.

Warning!
The battery must be replaced by a Typ CR2477N Renata battery only. The use of another battery may
present a risk of fire or explosion.
The battery may explode if handled improperly. Do not recharge, disassemble or dispose of in fire.

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Procedure for exreplacing the battery

1. Touch the mounting rail or ground connection (not the power supply!) in order to discharge any electrostatic
charge from your body.
2. Remove the cover for the lithium battery. Do this by sliding it down and away from the CPU.

Figure 312: X20 CPUs - Remove lithium battery cover

3. Remove the battery from the holder (do not use pliers or uninsulated tweezers -> risk of short circuiting). The
battery should not be held by its edges. Insulated tweezers may also be used to remove the battery.
Correct: Incorrect:

Figure 313: X20 CPUs - Correct grip for the battery

4. Insert the new battery with the correct polarity. To do this, lay the battery with the "+" side up on the right part
of the battery holder under the USB interface IF4. Then secure the battery in the holder by pressing above
the left part of the battery holder.
5. Replace the cover.

Information:
Lithium batteries are considered hazardous waste. Used batteries should be disposed of in accordance
with applicable local regulations.

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4.12.3.21 Programming the system flash memory

General information
In order for the application project to be executed on the CPU, the Automation Runtime operating system, the
system components and the application project must be installed on the CompactFlash card.

Creating a CompactFlash using a USB card reader

The easiest way to perform an initial installation is by creating a fully programmed CompactFlash card using a
USB card reader.
1. Creating and configuring a project in Automation Studio
2. In Automation Studio, select Tools / Create CompactFlash
3. In the dialog box that opens, select a CompactFlash card and then generate it
4. Insert the finished CompactFlash into the CPU and turn on the CPU's supply voltage
5. CPU booting

For details about commissioning: See help system under "Automation Software / Getting Started"

Installation over an online connection

The CPUs are delivered with a default B&R Automation Runtime system (with limited functions) already installed.
This runtime system is started in Boot mode (operating mode switch in the BOOT position or no CompactFlash /
invalid CompactFlash inserted). It initializes the Ethernet interface and onboard serial RS232 interface, making it
possible to download a new runtime system.
1. Insert the CompactFlash card and switch on the power to the CPU. When the switch is in the BOOT position,
a new or invalid CompactFlash card starts the CPU with the default B&R Automation Runtime system.
2. Establish a physical online connection between the programming device (PC or industrial PC) and the CPU
(e.g. over an Ethernet network or the RS232 interface).
3. Before you can establish an online connection via Ethernet, the CPU must be assigned an IP address. In
Automation Studio, select Settings from the Online menu and then click on the Browse targets button to
search for B&R target systems on the local network. The CPU should appear in the list. If the CPU has not
already received an IP address from a DHCP server, right-click on it and select Set IP parameters from the
shortcut menu. All necessary network configurations can be made on a temporary basis in this dialog box
(should be identical to the settings defined in the project).
4. Configure online connection in B&R Automation Studio. For details about the configuration: See help system
under "Automation Software / Communication / Online communication"
5. Start the download procedure by selecting the Services command from the Project menu. Then select Trans-
fer Automation Runtime from the pop-up menu. Now follow the instructions provided by B&R Automation
Studio.

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4.12.3.22 Information regarding switching from X20CPx48x to X20CPx58x

• A hardware upgrade is required for some X20 IFxxxx interface modules. This can be installed from Au-
tomation Studio by selecting Tools/Upgrades from the menu.
In addition, some modules specify a specific hardware revision. The following table provides an overview:
Model number Minimum upgrade version Minimum hardware revision
X20IF1020 1.1.5.1 H0
X20IF1030 1.1.5.1 I0
X20IF1041-1 - -
X20IF1043-1 - -
X20IF1051-1 - -
X20IF1053-1 - -
X20IF1061 - E0
X20IF1061-1 - -
X20IF1063 1.1.5.0 -
X20IF1063-1 - -
X20IF1065 - -
X20IF1072 1.0.5.1 -
X20IF1082 1.2.2.0 -
X20IF1082-2 1.2.1.0 -
X20IF1086-2 1.1.1.0 -
X20IF1091 1.0.5.1 -
X20IF10A1-1 - -
X20IF10D1-1 - -
X20IF10D3-1 - -
X20IF10E1-1 - -
X20IF10E3-1 - -
X20IF10G3-1 - -
X20IF10H3-1 - -
X20IF2772 1.0.6.1 -
X20IF2792 1.0.5.1 -

Table 295: X20 CPUs - Minimum upgrade version and minimum hardware revision for X20 IFxxxx interface modules
• The X20CPx58x CPUs are supported by B&R Automation Studio V3.0.90.20 and higher.
• If an X20CPx48x is to be replaced by an X20CPx58x in an existing Automation Studio configuration, the
X20CPx58x may not be listed as one of the available options even though the upgrade for the CPU has
already been installed. If this is the case, it is necessary to upgrade the X20CPx48x.
• Starting with Automation Runtime 4.x, USB devices are integrated in Automation Runtime dynamically so
that they no longer need to be configured in Automation Studio. In order to use a USB device, its internal
device name needs to be obtained at runtime. For an example, see the Automation Studio help system
for the library "AsUSB / Examples".

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 X20 system modules • Digital input modules • Brief information

4.13 Digital input modules

Digital input modules convert binary process signals into the internal signal level required by the PLC. The states
of the digital inputs are indicated with status LEDs.

4.13.1 Brief information

Product ID Short description on page
X20DI2371 X20 digital input module, 2 inputs, 24 VDC, sink, configurable input filter, 3-wire connections 936
X20DI2372 X20 digital input module, 2 inputs, 24 VDC, source, configurable input filter, 3-wire connections 942
X20DI2377 X20 digital input module, 2 inputs, 24 VDC, sink, configurable input filter, 2 event counters 50 kHz, 3-wire 948
connections
X20DI2653 X20 digital input module, 2 inputs, 100 to 240 VAC, 240 V keyed, 3-wire connections 956
X20DI4371 X20 digital input module, 4 inputs, 24 VDC, sink, configurable input filter, 3-wire connections 962
X20DI4372 X20 digital input module, 4 inputs, 24 VDC, source, configurable input filter, 3-wire connections 969
X20DI4375 X20 digital input module, 4 inputs, 24 VDC, sink, configurable input filter, open line and short circuit detection, 975
3-wire connections
X20DI4653 X20 digital input module, 4 inputs, 100 to 240 VAC, 240 V keyed, 2-wire connections 986
X20DI4760 X20 digital input module, 4 NAMUR inputs, 8.05 V 992
X20DI6371 X20 digital input module, 6 inputs, 24 VDC, sink, configurable input filter, 2-wire connections 1001
X20DI6372 X20 digital input module, 6 inputs, 24 VDC, source, configurable input filter, 2-wire connections 1007
X20DI6373 X20 digital input module, 6 inputs, 24 VDC, sink/source, all inputs floating, configurable input filter, 2-wire con- 1013
nections
X20DI6553 X20 digital input module, 6 inputs, 100 to 120 VAC, 240 V keyed, 1-wire connections 1019
X20DI8371 X20 digital input module, 8 inputs, 24 VDC, sink, configurable input filter, 1-wire connections 1025
X20DI9371 X20 digital input module, 12 inputs, 24 VDC, sink, configurable input filter, 1-wire connections 1031
X20DI9372 X20 digital input module, 12 inputs, 24 VDC, source, configurable input filter, 1-wire connections 1037
X20DID371 X20 digital input module, 8 inputs, 24 VDC, sink, configurable input filter, 2-wire connections 1043
X20DIF371 X20 digital input module, 16 inputs, 24 VDC, sink, configurable input filter, 1-wire connections 1049

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4.13.2 X20DI2371

4.13.2.1 General Information

The module is equipped with 2 inputs for 3-wire connections.

This module is designed for X20 6-pin terminal blocks. If needed (e.g. for logistical reasons), the 12-pin terminal
block can also be used.
• 2 digital inputs
• Sink connection
• 3-wire connections
• 24 VDC and GND for sensor supply
• Software input filter can be configured for entire module

4.13.2.2 Order data

Model number Short description Figure

Digital input modules
X20DI2371 X20 digital input module, 2 inputs, 24 VDC, sink, configurable
input filter, 3-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 296: X20DI2371 - Order data

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4.13.2.3 Technical data

Product ID X20DI2371
Short description
I/O module 2 digital inputs 24 VDC for 3-wire connections
General information
B&R ID code 0x1B8D
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.12 W
Internal I/O 0.29 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Typ. 3.75 mA
Input filter
Hardware ≤100 μs
Software Default 1 ms, configurable between 0 and 25 ms in 0.2 ms intervals
Connection type 3-wire connections
Input circuit Sink
Input resistance Typ. 6.4 kΩ
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
Sensor supply
Power consumption Max. 12.0 W 1)
Voltage Module supply minus voltage drop for short circuit protection
Voltage drop for short circuit protection at 500 mA Max. 2 VDC
Summation current 0.5 A
Short circuit protection Yes
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 297: X20DI2371 - Technical data

1) The power consumption of the sensors connected to the module may not exceed 12 W.

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4.13.2.4 Status LEDs

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
e+r Red on / Green single flash Invalid firmware
1-2 Green Input status of the corresponding digital input

4.13.2.5 Pinout

r e

X20 DI 2371
1 2

DI 1 DI 2

+24 VDC +24 VDC

GND GND

4.13.2.6 Connection example

DI
Sensor 1

Sensor 2

+24 VDC +24 VDC

GND GND

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4.13.2.7 Input circuit diagram

Input x

VDR

GND

I/O status
LED (green)
Input status

24 V
PTC
24 V

GND

GND

4.13.2.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.2.9.3.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

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4.13.2.9 Register description

4.13.2.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 DigitalInput USINT ●
DigitalInput01 Bit 0
DigitalInput02 Bit 1
18 - ConfigOutput01 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.2.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 Input status of digital inputs 1 to 2 USINT ●
DigitalInput01 Bit 0
DigitalInput02 Bit 1
18 - ConfigOutput01 USINT ●

1) The offset specifies where the register is within the CAN object.

4.13.2.9.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.2.9.3.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

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4.13.2.9.3.2 Input status of digital inputs 1 to 2

Name:
DigitalInput or
DigitalInput01 to DigitalInput02
The input status of digital inputs 1 to 2 is mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput02") or whether
this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 3 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
1 DigitalInput02 0 or 1 Input status - Digital input 2

4.13.2.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.2.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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4.13.3 X20DI2372

4.13.3.1 General Information

The module is equipped with 2 inputs for 3-wire connections.

This module is designed for X20 6-pin terminal blocks. If needed (e.g. for logistical reasons), the 12-pin terminal
block can also be used.
• 2 digital inputs
• Source connection
• 3-wire connections
• 24 VDC and GND for sensor supply
• Software input filter can be configured for entire module

4.13.3.2 Order data

Model number Short description Figure

Digital input modules
X20DI2372 X20 digital input module, 2 inputs, 24 VDC, source, configurable
input filter, 3-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 298: X20DI2372 - Order data

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4.13.3.3 Technical data

Product ID X20DI2372
Short description
I/O module 2 digital inputs 24 VDC for 3-wire connections
General information
B&R ID code 0x22A7
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.12 W
Internal I/O 0.29 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Typ. 3.75 mA
Input filter
Hardware ≤100 μs
Software Default 1 ms, configurable between 0 and 25 ms in 0.2 ms intervals
Connection type 3-wire connections
Input circuit Source
Input resistance Typ. 6.4 kΩ
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
Sensor supply
Power consumption Max. 12.0 W 1)
Voltage Module supply minus voltage drop for short circuit protection
Voltage drop for short circuit protection at 500 mA Max. 2 VDC
Summation current 0.5 A
Short circuit protection Yes
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 299: X20DI2372 - Technical data

1) The power consumption of the sensors connected to the module may not exceed 12 W.

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4.13.3.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
e+r Red on / Green single flash Invalid firmware
1-2 Green Input status of the corresponding digital input

4.13.3.5 Pinout

r e

X20 DI 2372
1 2

DI 1 DI 2

+24 VDC +24 VDC

GND GND

4.13.3.6 Connection example

DI
Sensor 1

Sensor 2

+24 VDC +24 VDC

GND GND

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4.13.3.7 Input circuit diagram

Input x

VDR

GND

I/O status
LED (green)
Input status

24 V

24 V
PTC

GND

GND

4.13.3.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.3.9.3.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

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4.13.3.9 Register description

4.13.3.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 DigitalInput USINT ●
DigitalInput01 Bit 0
DigitalInput02 Bit 1
18 - ConfigOutput01 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.3.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 Input status of digital inputs 1 to 2 USINT ●
DigitalInput01 Bit 0
DigitalInput02 Bit 1
18 - ConfigOutput01 USINT ●

1) The offset specifies where the register is within the CAN object.

4.13.3.9.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.3.9.3.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

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4.13.3.9.3.2 Input status of digital inputs 1 to 2

Name:
DigitalInput or
DigitalInput01 to DigitalInput02
The input status of digital inputs 1 to 2 is mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput02") or whether
this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 3 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
1 DigitalInput02 0 or 1 Input status - Digital input 2

4.13.3.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.3.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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4.13.4 X20DI2377

4.13.4.1 General Information

The module is equipped with two inputs for 3-wire connections. Both inputs can be configured as event counters.
Gate measurement is only ever possible on one channel.
This module is designed for X20 6-pin terminal blocks. If needed (e.g. for logistical reasons), the 12-pin terminal
block can also be used.
• 2 digital inputs
• Sink connection
• 3-wire connections
• 2 counter inputs with 50 kHz counter frequency
• Gate measurement
• 24 VDC and GND for sensor supply
• Software input filter can be configured for entire module

4.13.4.2 Order data

Model number Short description Figure

Digital input modules
X20DI2377 X20 digital input module, 2 inputs, 24 VDC, sink, configurable
input filter, 2 event counters 50 kHz, 3-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 300: X20DI2377 - Order data

4.13.4.3 Technical data

Product ID X20DI2377
Short description
I/O module 2 digital inputs 24 VDC for 3-wire connections, special functions
General information
B&R ID code 0x1B8E
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.15 W
Internal I/O 0.82 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Typ. 10.5 mA

Table 301: X20DI2377 - Technical data

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Product ID X20DI2377
Input filter
Hardware ≤10 μs
Software Default 0 ms, can be configured between 0 and 25 ms in 0.2 ms intervals
Connection type 3-wire connections
Input circuit Sink
Additional functions 50 kHz event counting, gate measurement
Input resistance Typ. 2.23 kΩ
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
Event counter
Quantity 2
Signal form Square wave pulse
Evaluation Every positive edge, cyclic counter
Input frequency Max. 50 kHz
Counter 1 Input 1
Counter 2 Input 2
Counter frequency Max. 50 kHz
Counter size 16-bit
Gate measurement
Number of gate measurements 1
Signal form Square wave pulse
Evaluation Rising edge - Falling edge
Counter frequency
Internal 48 MHz, 24 MHz, 12 MHz, 6 MHz, 3 MHz, 1.5 MHz, 750 kHz, 375 kHz, 187.5 kHz
Counter size 16-bit
Length of pause between pulses ≥100 µs
Pulse length ≥20 µs
Supported inputs Input 1 or Input 2
Sensor supply
Power consumption Max. 12.0 W 1)
Voltage Module supply minus voltage drop for short circuit protection
Voltage drop for short circuit protection at 500 mA Max. 2 VDC
Summation current 0.5 A
Short circuit protection Yes
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 301: X20DI2377 - Technical data

1) The power consumption of the sensors connected to the module may not exceed 12 W.

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4.13.4.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
e+r Red on / Green single flash Invalid firmware
1-2 Green Input status of the corresponding digital input

4.13.4.5 Pinout

r e

X20 DI 2377
1 2

DI 1 DI 2

+24 VDC +24 VDC

GND GND

4.13.4.6 Connection example

DI
Counter/sensor

Counter/sensor

+24 VDC +24 VDC

GND GND

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4.13.4.7 Input circuit diagram

Input x

VDR

GND
24 V
PTC
24 V
Input status

I/O status
LED (green)
GND

GND

4.13.4.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.4.9.4.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

Information:
The input filter is applied to digital inputs in event counter mode with software
The input filter is NOT applied in event counter mode without software.

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4.13.4.9 Register description

4.13.4.9.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 DigitalInput USINT ●
DigitalInput01 Bit 0
DigitalInput02 Bit 1
4 Counter01 USINT ●
6 Counter02 USINT ●
20 Counter configuration USINT ●
ResetCounter01 Bit 5
22 Counter configuration USINT ●
ResetCounter02 Bit 5
18 ConfigOutput01 USINT ●
20 ConfigOutput02 USINT ●
22 ConfigOutput03 USINT ●

4.13.4.9.2 Function model 1 - Input latch

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
26 Input status of digital latch inputs 1 - 2 USINT ●
DigitalInputLatch01 Bit 0
DigitalInputLatch02 Bit 1
28 Acknowledge digital inputs USINT ●
DigitalInput01LatchQuitt Bit 0
DigitalInput02LatchQuitt Bit 1
4 Counter01 USINT ●
6 Counter02 USINT ●
20 Counter configuration USINT ●
ResetCounter01 Bit 5
22 Counter configuration USINT ●
ResetCounter02 Bit 5
18 ConfigOutput01 USINT ●
20 ConfigOutput02 USINT ●
22 ConfigOutput03 USINT ●

4.13.4.9.3 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
4 0 Counter01 USINT ●
6 2 Counter02 USINT ●
20 - Counter configuration USINT ●
ResetCounter01 Bit 5
22 - Counter configuration USINT ●
ResetCounter02 Bit 5
18 - ConfigOutput01 USINT ●
20 - ConfigOutput02 USINT ●
22 - ConfigOutput03 USINT ●

1) The offset specifies where the register is within the CAN object.

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4.13.4.9.4 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.4.9.4.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

4.13.4.9.4.2 Input status of digital inputs 1 to 2

Name:
DigitalInput or
DigitalInput01 to DigitalInput02
The input status of digital inputs 1 to 2 is mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput02") or whether
this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 3 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
1 DigitalInput02 0 or 1 Input status - Digital input 2

4.13.4.9.4.3 Input status of digital latch inputs 1 - 2

Name:
DigitalInputLatch01 to DigitalInputLatch02
The input status of digital inputs 1 to 2 after expiration of the input filter time is mapped in this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 DigitalInputLatch01 0 or 1 Input status of digital input 1 after expiration of the delay time
1 DigitalInputLatch02 0 or 1 Input status of digital input 2 after expiration of the delay time

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4.13.4.9.5 Counter operation

The following operation modes can be selected:

• Event counter mode
• Event counter mode with software (processed after the input filter)
• Gate measurement
Event counter mode
The rising (positive) edges are registered on the counter input.
The counter state is registered with a fixed offset with respect to the network cycle and transferred in the same cycle.
Event counter mode with software
The rising (positive) edges are registered on the counter input. But the edges are first processed through the
configured software filter.
The counter state is registered with a fixed offset with respect to the network cycle and transferred in the same cycle.
Gate measurement
The time of rising to falling edges for the gate input is registered using an internal frequency. The result is checked
for overflow (0xFFFF) and corrected with the adjustable prescaler.
The recovery time between measurements must be >100 µs.
The measurement result is transferred with the falling edge to the result memory.

Information:
Only one of the counter channels at a time can be used for gate measurement.

4.13.4.9.5.1 Event or gate counter

Name:
Counter01 to Counter02
This register displays the results of the individual counters.
Event counter or gate measurement (16-bit counter value) depending on operating mode.
Data type Value
USINT Counter value

4.13.4.9.5.2 Counter configuration

Name:
ConfigOutput02 to ConfigOutput03
The individual counters can be configured in this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-3 Counter frequency 0 48MHz (only with gate measurement)
1 3MHz (only with gate measurement)
1 Event counter mode with software (only with event counter
measurement)
2 187.5kHz (only with gate measurement)
3 24MHz (only with gate measurement)
4 12MHz (only with gate measurement)
5 6MHz (only with gate measurement)
6 1.5MHz (only with gate measurement)
7 750kHz (only with gate measurement)
8 375kHz (only with gate measurement)
4 Reserved 0
5 ResetCounter01 or ResetCounter02 0 No influence on the counter
1 Clear counter (at positive edge)
6-7 0 Event counter measurement
1 Gate measurement

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4.13.4.9.6 Positive edge input latch

Using this function, the positive edges of the input signal can be latched with a resolution of 200 µs. With the
"Acknowledge - input latch" function, the input latch is either reset or prevented from latching.
It works in the same way as a dominant reset RS flip-flop.
Reset x

R
R S Q Status
0 0 x Do not change
S Q Latch x 0 1 1 Set
Input x
1 0 0 Reset
Pos. edge 1 1 0 Reset

4.13.4.9.6.1 Acknowledge digital inputs

Name:
DigitalInput01LatchQuitt to DigitalInput02LatchQuitt
This register is used to reset the input latches channel by channel.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 DigitalInput01LatchQuitt 0 No influence on the latch status
1 Resets the latch status
1 DigitalInput02LatchQuitt 0 No influence on the latch status
1 Resets the latch status
2-7 Reserved -

4.13.4.9.7 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.4.9.8 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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4.13.5 X20DI2653

4.13.5.1 General Information

The module is equipped with 2 inputs for 3-wire connections. It is designed for an input voltage of 100 to 240 VAC.
• 2 digital inputs
• 100 to 240 VAC inputs
• 50 Hz or 60 Hz
• 3-wire connections
• 240 V coded

Danger!
Risk of electric shock!
The terminal block must only be allowed to conduct voltage when it is inserted. It must not under any
circumstances be removed or inserted when voltage is applied or have voltage applied to it when it
is removed.

4.13.5.2 Order data

Model number Short description Figure

Digital input modules
X20DI2653 X20 digital input module, 2 inputs, 100 to 240 VAC, 240 V keyed,
3-wire connections
Required accessories
Bus modules
X20BM12 Bus module, 240 VAC keyed, internal I/O supply continuous
Terminal blocks
X20TB32 X20 terminal block, 12-pin, 240 VAC keyed

Table 302: X20DI2653 - Order data

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4.13.5.3 Technical data

Product ID X20DI2653
Short description
I/O module 2 digital inputs 100 to 240 VAC for 3-wire connections
General information
B&R ID code 0x2544
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
External I/O supply Yes, using software (typical threshold 85 VAC)
Power consumption
Bus 0.14 W
Internal I/O -
External I/O 0.55 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital inputs
Nominal voltage 100 to 240 VAC
Input filter
Software Default 1 ms, configurable between 0 and 25 ms in 0.2 ms intervals
Hardware
1 -> 0 ≤30 ms
0 -> 1 ≤40 ms
Connection type 3-wire connections
Rated frequency 47 to 63 Hz
Switching threshold
Low <40 VAC
High >79 VAC
Isolation voltage between channel and bus 1 minute 2500 VAC
Input voltage
Maximum 264 VAC
Input current
100 VAC / 60 Hz 5.0 mA
240 VAC / 50 Hz 11 mA
Sensor supply
Voltage Equal to the module supply
Summation current 2 Aeff
Short circuit protection No
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB32 terminal block separately
Order 1x X20BM12 bus module separately
Spacing 12.5 +0.2 mm

Table 303: X20DI2653 - Technical data

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4.13.5.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
Double flash External supply is too low or not connected
e+r Red on / Green single flash Invalid firmware
1-2 Green Input status of the corresponding digital input

4.13.5.5 Pinout

r e

X20 DI 2653
1 2

DI 1 DI 2

L L

N N

L L

N N

4.13.5.6 Connection example

DI
Sensor 1

Sensor 2

L L

N N

L L

N N

+24 VDC +24 VDC

GND GND

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4.13.5.7 Input circuit diagram

Input status
Input x

Diagnostics status
L U ok

Voltage
monitoring

4.13.5.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.5.9.3.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

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4.13.5.9 Register description

4.13.5.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 DigitalInput USINT ●
DigitalInput01 Bit 0
DigitalInput02 Bit 1
PowerSupply Bit 7
18 - ConfigOutput01 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.5.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 Input status of digital inputs 1 to 2 USINT ●
DigitalInput01 Bit 0
DigitalInput02 Bit 1
PowerSupply Bit 7
18 - ConfigOutput01 USINT ●

1) The offset specifies where the register is within the CAN object.

4.13.5.9.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.5.9.3.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

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4.13.5.9.3.2 Input status of digital inputs 1 to 2

Name:
DigitalInput or
DigitalInput01 to DigitalInput02
PowerSupply
The input status of digital inputs 1 to 2 is mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("DigitalInput01", "DigitalInput02" and "PowerSupply")
or whether this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 255 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
1 DigitalInput02 0 or 1 Input status - Digital input 2
2-6 Reserved 0
7 PowerSupply 0 Supply voltage too low
1 Supply voltage >80 VAC

4.13.5.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.5.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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4.13.6 X20DI4371

4.13.6.1 General Information

The module is equipped with four inputs for 3-wire connections.

• 4 digital inputs
• Sink connection
• 3-wire connections
• 4 counter inputs with 1 kHz counter frequency
• 24 VDC and GND for sensor supply
• Software input filter can be configured for entire module

4.13.6.2 Order data

Model number Short description Figure

Digital input modules
X20DI4371 X20 digital input module, 4 inputs, 24 VDC, sink, configurable
input filter, 3-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 304: X20DI4371 - Order data

4.13.6.3 Technical data

Product ID X20DI4371
Short description
I/O module 4 digital inputs 24 VDC for 3-wire connections
General information
B&R ID code 0x1B92
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.14 W
Internal I/O 0.59 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Typ. 3.75 mA
Input filter
Hardware ≤100 μs
Software Default 1 ms, configurable between 0 and 25 ms in 0.2 ms intervals
Connection type 3-wire connections
Input circuit Sink
Input resistance Typ. 6.4 kΩ

Table 305: X20DI4371 - Technical data

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Product ID X20DI4371
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
Event counter
Quantity 4
Signal form Square wave pulse
Evaluation Configurable edge event, cyclic counter
Input frequency Max. 1 kHz
Counter 1 Input 1
Counter 2 Input 2
Counter 3 Input 3
Counter 4 Input 4
Counter frequency Max. 1 kHz (with input filter switched off)
Counter size 16-bit
Sensor supply
Power consumption Max. 12.0 W 1)
Voltage Module supply minus voltage drop for short circuit protection
Voltage drop for short circuit protection at 500 mA Max. 2 VDC
Summation current 0.5 A
Short circuit protection Yes
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 305: X20DI4371 - Technical data

1) The power consumption of the sensors connected to the module may not exceed 12 W.

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4.13.6.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
e+r Red on / Green single flash Invalid firmware
1-4 Green Input status of the corresponding digital input

4.13.6.5 Pinout

r e

X20 DI 4371
1 2
3 4

DI 1 DI 2

+24 VDC +24 VDC

GND GND

DI 3 DI 4

+24 VDC +24 VDC

GND GND

4.13.6.6 Connection example

DI
Sensor 1

Sensor 2
Sensor 3

Sensor 4

+24 VDC +24 VDC

GND GND

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4.13.6.7 Input circuit diagram

Input x

VDR

GND

I/O status
LED (green)
Input status

24 V
PTC
24 V

GND

GND

4.13.6.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.6.9.4.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

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4.13.6.9 Register description

4.13.6.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 DigitalInput USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput04 Bit 3
18 - ConfigOutput01 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.6.9.2 Function model 1 - Event counter

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 Input status of digital inputs 1 to 4 USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput04 Bit 3
4 2 Counter01 UINT ●
6 4 Counter02 UINT ●
8 6 Counter03 UINT ●
10 8 Counter04 UINT ●
12 0 Resets the counter registers USINT ●
ResetCounter01 Bit 0
... ...
ResetCounter04 Bit 3
18 - ConfigOutput01 USINT ●
14 - ConfigOutput02 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.6.9.3 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 Input status of digital inputs 1 to 4 USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput04 Bit 3
18 - ConfigOutput01 USINT ●

1) The offset specifies where the register is within the CAN object.

4.13.6.9.4 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

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4.13.6.9.4.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

4.13.6.9.4.2 Input status of digital inputs 1 to 4

Name:
DigitalInput or
DigitalInput01 to DigitalInput04
The input status of digital inputs 1 to 4 is mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput04") or whether
this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 15 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
... ...
3 DigitalInput04 0 or 1 Input status - Digital input 4

4.13.6.9.5 The event counter function model

Starting with hardware variant F0 and firmware version 801, the module has four software counters for signal
edges. Each counter register can be configured individually for falling, rising or both edges.

4.13.6.9.5.1 Counter register

Name:
Counter01 to Counter04
These registers provide the current counter value for the configured events.
Data type Value
UINT 0 to 65535

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4.13.6.9.5.2 Resets the counter registers

Name:
ResetCounter01 to ResetCounter04
Using these data points, the corresponding counter registers can be reset to 0.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 ResetCounter01 0 No change
1 Counter register 1 is reset
... ...
3 ResetCounter04 0 No change
1 Counter register 4 is reset

Information:
A counter is only reset if a positive edge is detected on the reset bit.
A continually set reset bit does not prevent counting in the counter register.

4.13.6.9.5.3 Configuration of the edges

Name:
ConfigOutput02
This register is used to configure which event will be assessed on the channel input for the respective counter.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Rising edge on input 1 0 Event is not counted
1 Event increments Counter01
... ...
3 Rising edge on input 4 0 Event is not counted
1 Event increments Counter04
4 Falling edge on input 1 0 Event is not counted
1 Event increments Counter01
... ...
7 Falling edge on input 4 0 Event is not counted
1 Event increments Counter04

4.13.6.9.6 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.6.9.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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4.13.7 X20DI4372

4.13.7.1 General Information

The module is equipped with 4 inputs for 3-wire connections.

• 4 digital inputs
• Source connection
• 3-wire connections
• 24 VDC and GND for sensor supply
• Software input filter can be configured for entire module

4.13.7.2 Order data

Model number Short description Figure

Digital input modules
X20DI4372 X20 digital input module, 4 inputs, 24 VDC, source, configurable
input filter, 3-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 306: X20DI4372 - Order data

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4.13.7.3 Technical data

Product ID X20DI4372
Short description
I/O module 4 digital inputs 24 VDC for 3-wire connections
General information
B&R ID code 0x22A8
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.14 W
Internal I/O 0.59 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Typ. 3.75 mA
Input filter
Hardware ≤100 μs
Software Default 1 ms, configurable between 0 and 25 ms in 0.2 ms intervals
Connection type 3-wire connections
Input circuit Source
Input resistance Typ. 6.4 kΩ
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
Sensor supply
Power consumption Max. 12.0 W 1)
Voltage Module supply minus voltage drop for short circuit protection
Voltage drop for short circuit protection at 500 mA Max. 2 VDC
Summation current 0.5 A
Short circuit protection Yes
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 307: X20DI4372 - Technical data

1) The power consumption of the sensors connected to the module may not exceed 12 W.

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4.13.7.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
e+r Red on / Green single flash Invalid firmware
1-4 Green Input status of the corresponding digital input

4.13.7.5 Pinout

r e

X20 DI 4372
1 2
3 4

DI 1 DI 2

+24 VDC +24 VDC

GND GND

DI 3 DI 4

+24 VDC +24 VDC

GND GND

4.13.7.6 Connection example

DI
Sensor 1

Sensor 2
Sensor 3

Sensor 4

+24 VDC +24 VDC

GND GND

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4.13.7.7 Input circuit diagram

Input x

VDR

GND

I/O status
LED (green)
Input status

24 V

24 V
PTC

GND

GND

4.13.7.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.7.9.3.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

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4.13.7.9 Register description

4.13.7.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 DigitalInput USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput04 Bit 3
18 - ConfigOutput01 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.7.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 Input status of digital inputs 1 to 4 USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput04 Bit 3
18 - ConfigOutput01 USINT ●

1) The offset specifies where the register is within the CAN object.

4.13.7.9.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.7.9.3.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

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4.13.7.9.3.2 Input status of digital inputs 1 to 4

Name:
DigitalInput or
DigitalInput01 to DigitalInput04
The input status of digital inputs 1 to 4 is mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput04") or whether
this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 15 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
... ...
3 DigitalInput04 0 or 1 Input status - Digital input 4

4.13.7.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.7.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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4.13.8 X20DI4375

4.13.8.1 General Information

The module is equipped with four inputs for 3-wire connections. It has open circuit and short circuit detection. This
detection can be switched off individually for each channel.
• 4 digital inputs
• Sink connection
• 3-wire connections
• 24 VDC and GND for sensor supply
• Open circuit and short circuit detection, can be switched off individually for each channel
• Software input filter can be configured for entire module

4.13.8.2 Order data

Model number Short description Figure

Digital input modules
X20DI4375 X20 digital input module, 4 inputs, 24 VDC, sink, configurable
input filter, open line and short circuit detection, 3-wire connec-
tions
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 308: X20DI4375 - Order data

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4.13.8.3 Technical data

Product ID X20DI4375
Short description
I/O module 4 digital inputs 24 VDC for 3-line connections, open line and short cir-
cuit detection, detection can be switched off individually for each channel
General information
B&R ID code 0xA911
Status indicators I/O function per channel, operating state, module status, sensor line, sensor supply
Diagnostics
Module run/error Yes, using status LED and software
Open line Yes, using status LED and software
Short circuit Yes, using status LED and software
Sensor supply Yes, using status LED and software
Other channel errors Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.1 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Nominal voltage 24 VDC
Input filter
Hardware 0.8 ms
Software Default 1 ms, configurable between 0 and 25 ms in 0.2 ms intervals
Connection type 3-wire connections
Input circuit Sink
Sensor supply 4 x 50mA
Open circuit and short circuit detection Yes, can be switched off individually for each channel
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 309: X20DI4375 - Technical data

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4.13.8.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during update)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
Single flash Summary status for channel error → Check the red channel LEDs 1 - 4
Double flash Module supply below lower limit
Triple flash Converter error (or transition between single and double flash)
1-4 Green Input status of the corresponding digital input
1-4 Red Off No error detected
Single flash Short circuit of respective digital input with +24 VDC
Blinking Open circuit or the measured value is below the lower switch off threshold
Single flash, Other channel error
inverse
S1 - S4 Red Off Sensor supply OK
On Sensor supply monitor has detected something

4.13.8.5 Pinout

Shielded cables should be used for all connections.

r e
X20 DI 4375

1 2
3 4
1 2
3 4
S1 S2
S3 S4

DI 1 DI 2

+24 VDC +24 VDC

GND GND

DI 3 DI 4

+24 VDC +24 VDC

GND GND

4.13.8.6 Connection example

DI
Sensor 1

Sensor 2
Sensor 3

Sensor 4

+24 VDC +24 VDC

GND GND

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4.13.8.7 Input circuit diagram

A/D Input value

Input x
Converter

VDR Ri

I/O status
GND GND GND

24 V LED (green)
PTC
24 V GND

VDC Monitoring the 24 VDC

Sensor supply voltage

Sensor supply status (S1 - S4)

Sensor supply status (S1 - S4)
GND GND

GND LED (red)

GND GND

4.13.8.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.8.13.3.1 "ConfigOutput02"
on page 981. Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

4.13.8.9 Open circuit and short circuit detection

General Information
The X20DI4375 digital input module is equipped with open line and short circuit detection. To do this the sensor
needs to be connected to the necessary resistances.

Sensor connections
The resistances are connected to the sensor parallel or in series. The following values are defined for the resis-
tances:
Resistance Range
Serial 1 - 2 kΩ (10%)
Parallel 10 - 20 kΩ (10%)

Table 310: Value range for sensor connections

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Connection options
To guarantee error-free functionality of the open circuit and short circuit detection, the +24 VDC sensor supply from
the module must absolutely be used.
Sensor connections Description Detection Setting in configuration register
+24 V

Standard connection - 0

Input x
Sensor

RS
+24 V

Series and parallel resistance Open circuit and short circuit 1

RP

Input x

Sensor

RS
+24 V

Parallel and series resistor Open circuit and short circuit 2

RP

Input x

Sensor

+24 V

RP
Parallel resistance Open line 3

Input x

Sensor

RS
+24 V

Series resistor Short circuit 4

Input x

Table 311: Connection options for sensor

4.13.8.10 Error status

The following errors are detected by the module and can be evaluated separately for each channel:
• Sensor line short circuit
• Sensor line open circuit
• Sensor supply
• Other channel error

4.13.8.11 Timestamp

Each converted value is given a timestamp. The time of the last conversion can be read.

4.13.8.12 Configuration

The sensor connections and therefore the sensor monitoring are set in the configuration register. Sensor monitor-
ing and the settings in the configuration register are described in section 4.13.8.9 "Open circuit and short circuit
detection" on page 978.

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4.13.8.13 Register description

4.13.8.13.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2305 DigitalInput USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput04 Bit 3
StateDigitalInput01 Bit 4
... ...
StateDigitalInput04 Bit 7
2307 StatusInput01 USINT ●
SC_DigitalInput01 Bit 0
... ...
SC_DigitalInput04 Bit 3
2309 StatusInput02 USINT ●
WB_DigitalInput01 Bit 0
... ...
WB_DigitalInput04 Bit 3
2311 StatusInput03 USINT ●
SM_DigitalInput01 Bit 0
... ...
SM_DigitalInput04 Bit 3
2313 StatusInput04 ●
IE_DigitalInput01 Bit 0
... ...
IE_DigitalInput01 Bit 3
2324 SampleTimeStamp UDINT ●
2050 ConfigOutput01 UINT ●
2053 ConfigOutput02 USINT ●

4.13.8.13.2 Function model 254 - Bus Controller

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2305 Input status of digital inputs 1 to 4 USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput04 Bit 3
StateDigitalInput01 Bit 4
... ...
StateDigitalInput04 Bit 7
2307 Short circuit monitoring of channels 1 to 4 USINT ●
SC_DigitalInput01 Bit 0
... ...
SC_DigitalInput04 Bit 3
2309 Open line monitoring on channels 1 to 4 USINT ●
WB_DigitalInput01 Bit 0
... ...
WB_DigitalInput04 Bit 3
2311 Voltage monitoring on channels 1 to 4 USINT ●
SM_DigitalInput01 Bit 0
... ...
SM_DigitalInput04 Bit 3
2313 Error monitoring on channels 1 to 4 ●
IE_DigitalInput01 Bit 0
... ...
IE_DigitalInput01 Bit 3
2324 SampleTimeStamp UDINT ●
2050 ConfigOutput01 UINT ●
2053 ConfigOutput02 USINT ●

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4.13.8.13.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.8.13.3.1 Digital input filter

Name:
ConfigOutput02
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

4.13.8.13.3.2 Input status of digital inputs 1 to 4

Name:
DigitalInput or
DigitalInput01 to DigitalInput04
StateDigitalInput01 to StateDigitalInput04
The input status and status of digital inputs 1 to 4 are mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits
should be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput04" and
"StateDigitalInput01" through "StateDigitalInput04") or whether this register should be displayed as an individual
USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 255 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
... ...
3 DigitalInput04 0 or 1 Input status - Digital input 4
0 No error
4 StateDigitalInput01 Short-circuit, open line, sensor monitoring error or other channel
1
error
... ...
0 No error
7 StateDigitalInput04 Short-circuit, open line, sensor monitoring error or other channel
1
error

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4.13.8.13.4 Short circuit monitoring of channels 1 to 4

Name:
StatusInput01 or
SC_DigitalInput01 to SC_DigitalInput04
This register indicates whether a short circuit has occurred on the individual channels.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("SC_DigitalInput01" through "SC_DigitalInput04") or
whether this register should be displayed as an individual USINT data point ("StatusInput01").
Data type Value Information
USINT 0 to 15 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 SC_DigitalInput01 0 No error
1 Short circuit on channel 1
... ...
3 SC_DigitalInput04 0 No error
1 Short circuit on channel 4
4-7 Reserved

4.13.8.13.5 Open line monitoring on channels 1 to 4

Name:
StatusInput02 or
WB_DigitalInput01 to WB_DigitalInput04
This register indicates whether an open line has occurred on the individual channels.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("WB_DigitalInput01" through "WB_DigitalInput04") or
whether this register should be displayed as an individual USINT data point ("StatusInput02").
Data type Value Information
USINT 0 to 15 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 WB_DigitalInput01 0 No error
1 Open line on channel 1
... ...
3 WB_DigitalInput04 0 No error
1 Open line on channel 4
4-7 Reserved -

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4.13.8.13.6 Voltage monitoring on channels 1 to 4

Name:
StatusInput03 or
SM_DigitalInput01 to SM_DigitalInput04
This register monitors the voltage supply on the individual channels.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("SM_DigitalInput01" through "SM_DigitalInput04") or
whether this register should be displayed as an individual USINT data point ("StatusInput03").
Data type Value Information
USINT 0 to 15 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 SM_DigitalInput01 0 No error
1 Sensor supply error on channel 1
... ...
3 SM_DigitalInput04 0 No error
1 Sensor supply error on channel 4
4-7 Reserved -

4.13.8.13.7 Error monitoring on channels 1 to 4

Name:
StatusInput04 or
IE_DigitalInput01 to IE_DigitalInput04
This register indicates whether any other errors have occurred on the individual channels.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("IE_DigitalInput01" through "IE_DigitalInput04") or
whether this register should be displayed as an individual USINT data point ("StatusInput04").
Data type Value Information
USINT 0 to 15 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 IE_DigitalInput01 0 No error
1 Other error on channel 1
... ...
3 IE_DigitalInput04 0 No error
1 Other error on channel 4
4-7 Reserved -

4.13.8.13.8 Timestamp of last conversion

Name:
SampleTimeStamp
This register shows the timestamp of the last conversion in μs.
Data type Value
UDINT Timestamp of the last conversion in μs

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4.13.8.13.9 Configuration of line status monitoring

Name:
ConfigOutput01
This register is used to configure short circuit monitoring and line status monitoring on the inputs.
Data type Value
UINT See bit structure

Bit structure:
Bit Name Value Information
0-3 Channel configuration - Channel 1 0 Standard
1 Serial/Parallel: R-1k in series with (R-10k parallel to the switch)
2 Parallel/Serial: R-10k parallel to (R-1k in series with switch)
3 Parallel: R-10k parallel to switch
4 Serial: R-1k in series with switch
5 to 15 Inactive
4-7 Channel configuration - Channel 2 0 to 15 See Channel configuration - Channel 1
8 - 11 Channel configuration - Channel 3 0 to 15 See Channel configuration - Channel 1
12 - 15 Channel configuration - Channel 4 0 to 15 See Channel configuration - Channel 1

The name R-1k indicates a resistance in the permitted range of 1000 Ohm to 2000 Ohm with an accuracy of 10%.
The name R-10k indicates a resistance in the permitted range of 10000 Ohm to 20000 Ohm with an accuracy
of 10%.

Information:
Inputs that are not being used should be set to the type "Standard" or "Serial" to prevent mistakes.
Configuration Possibilities:
Value Configuration Diagram Information
0 Standard +24 V Short-circuit detection and line break monitoring is not possible when using this
configuration.

Input x
1 Serial/parallel Sensor Short-circuit detection and line break monitoring is possible with this configura-
tion.
RS
+24 V

RP

Input x

2 Parallel/serial Sensor Short-circuit detection and line break monitoring is possible with this configura-
tion.
RS
+24 V

RP

Input x

3 Parallel Sensor This configuration allows line break monitoring. Short-circuit detection is not pos-
sible when using this configuration.
+24 V

RP

Input x

4 Serial Sensor This configuration allows short circuit detection. Line break monitoring is not pos-
sible when using this configuration.
RS
+24 V

Input x

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4.13.8.13.10 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
All channels 150 μs

4.13.8.13.11 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
All channels 150 μs

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4.13.9 X20DI4653

4.13.9.1 General Information

The module is equipped with 4 inputs for 2-wire connections. It is designed for an input voltage of 100 to 240 VAC.
• 4 digital inputs
• 100 to 240 VAC inputs
• 50 Hz or 60 Hz
• 2-wire connections
• 240 V coded

Danger!
Risk of electric shock!
The terminal block must only be allowed to conduct voltage when it is inserted. It must not under any
circumstances be removed or inserted when voltage is applied or have voltage applied to it when it
is removed.

4.13.9.2 Order data

Model number Short description Figure

Digital input modules
X20DI4653 X20 digital input module, 4 inputs, 100 to 240 VAC, 240 V keyed,
2-wire connections
Required accessories
Bus modules
X20BM12 Bus module, 240 VAC keyed, internal I/O supply continuous
Terminal blocks
X20TB32 X20 terminal block, 12-pin, 240 VAC keyed

Table 312: X20DI4653 - Order data

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4.13.9.3 Technical data

Product ID X20DI4653
Short description
I/O module 4 digital inputs 100 to 240 VAC for 2-wire connections
General information
B&R ID code 0x2545
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
External I/O supply Yes, using software (typical threshold 85 VAC)
Power consumption
Bus 0.17 W
Internal I/O -
External I/O 0.91 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital inputs
Nominal voltage 100 to 240 VAC
Input filter
Software Default 1 ms, configurable between 0 and 25 ms in 0.2 ms intervals
Hardware
1 -> 0 ≤30 ms
0 -> 1 ≤40 ms
Connection type 2-wire connections
Rated frequency 47 to 63 Hz
Switching threshold
Low <40 VAC
High >79 VAC
Isolation voltage between channel and bus 1 minute 2500 VAC
Input voltage
Maximum 264 VAC
Input current
100 VAC / 60 Hz 5.0 mA
240 VAC / 50 Hz 11 mA
Sensor supply
Voltage Equal to the module supply
Short circuit protection No
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB32 terminal block separately
Order 1x X20BM12 bus module separately
Spacing 12.5 +0.2 mm

Table 313: X20DI4653 - Technical data

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4.13.9.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
Double flash External supply is too low or not connected
e+r Red on / Green single flash Invalid firmware
1-4 Green Input status of the corresponding digital input

4.13.9.5 Pinout

r e

X20 DI 4653
1 2
3 4

DI 1 DI 2

DI 3 DI 4

L L

L L

L L

N N

4.13.9.6 Connection example

DI

Sensor 1 Sensor 2

Sensor 3 Sensor 4

L L

N N

+24 VDC +24 VDC

GND GND

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4.13.9.7 Input circuit diagram

Input status
Input x

Diagnostics status
L U ok

Voltage
monitoring

4.13.9.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.9.9.3.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

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4.13.9.9 Register description

4.13.9.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 DigitalInput USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput04 Bit 3
PowerSupply Bit 7
18 - ConfigOutput01 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.9.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 Input status of digital inputs 1 to 4 USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput04 Bit 3
PowerSupply Bit 7
18 - ConfigOutput01 USINT ●

1) The offset specifies where the register is within the CAN object.

4.13.9.9.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.9.9.3.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

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4.13.9.9.3.2 Input status of digital inputs 1 to 4

Name:
DigitalInput or
DigitalInput01 to DigitalInput04
PowerSupply
The input status of digital inputs 1 to 4 is mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits
should be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput02" and
"PowerSupply") or whether this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 15 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
... ...
3 DigitalInput04 0 or 1 Input status - Digital input 4
4-6 Reserved 0
7 PowerSupply 0 Supply voltage too low
1 Supply voltage >80 VAC

4.13.9.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.9.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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4.13.10 X20DI4760

4.13.10.1 General Information

The module is used to transfer digital signals from NAMUR encoders according to EN 60947-5-6. In addition to
NAMUR encoders, normal switches can also be used.
• 4 digital inputs
• Input module for NAMUR encoders
• Open line and short circuit detection
• Each input can be used as a counter input

4.13.10.2 Order data

Model number Short description Figure

Digital input modules
X20DI4760 X20 digital input module, 4 NAMUR inputs, 8.05 V
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 314: X20DI4760 - Order data

4.13.10.3 Technical data

Product ID X20DI4760
Short description
I/O module 4 NAMUR inputs, special function
General information
B&R ID code 0x2105
Status indicators I/O function by channel, open line and short circuit detection by channel, operating status, module status
Diagnostics
Module run/error Yes, using status LED and software
Short circuit Yes, using status LED and software
Open line Yes, using status LED and software
Power consumption
Bus 0.01 W
Internal I/O 1.5 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Event counter
Quantity 4
Signal form Symmetric square wave pulse or corresponding minimum pulse duration 1)
Evaluation Every positive edge, cyclic counter
Counter size 8-bit
Input frequency
1 input active Max. 1600 Hz
2 inputs active Max. 1100 Hz
3 inputs active Max. 870 Hz
4 inputs active Max. 680 Hz

Table 315: X20DI4760 - Technical data

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Product ID X20DI4760
NAMUR inputs
Open line detection <350 µA
Input circuit For NAMUR encoders in accordance with EN 60947-5-6
Isolation voltage between channel and bus 500 Veff
Short circuit detection >7 mA
No load voltage 8.05 V ±0.33%
Switching amplifier internal resistance 1 kΩ ±1%
Max. short circuit current 8.2 mA
Input delay
1 input active ≤310 µs
2 inputs active ≤450 µs
3 inputs active ≤570 µs
4 inputs active ≤735 µs
Switching threshold
Range 1.2 mA to 2.1 mA
Switching hysteresis Typ. 300 µA
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 315: X20DI4760 - Technical data

1) Minimum pulse duration: t[s] ≥ 1/(2 x fmax[Hz])

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4.13.10.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
On Error or reset status
Single flash Error on at least one channel
e+r Red on / Green single flash Invalid firmware
1-4 Green Off Open line or input status log. 0
On Short circuit or input status log. 1
1-4 Red Off The sensor is ready for operation
Blinking 1Hz Open line on corresponding channel
On Short circuit on corresponding channel

4.13.10.5 Pinout

r e

X20 DI 4760
1 2
3 4
1 2
3 4

K1 + K2 +

K1 - K2 -

K3 + K4 +

K3 - K4 -

4.13.10.6 Connection example

DI
NAMUR NAMUR
Sensor Sensor

+24 VDC +24 VDC

GND GND

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4.13.10.7 Input circuit diagram

Signal-
evaluation

PTC
Kx +

I/O status Line state Kx -

LED (green) LED (red)

4.13.10.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.10.10.3.1 "ConfigOutput03"
on page 998. Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

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4.13.10.9 Examples of possible signal generators

Proximity switch
+ input x

Switch in accordance with EN 60947-5-6 (NAMUR)

- input x

Mechanical contacts (instead of NAMUR encoders)

+ input x

Without open line detection and without short circuit detection

- input x

+ input x

Without open line detection and with short circuit detection

1 kΩ - input x

+ input x

With open line detection and without short circuit detection 10 kΩ

- input x

+ input x

With open line detection and with short circuit detection 10 kΩ

1 kΩ - input x

Table 316: X20DI4760 - Examples of possible signal generators

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4.13.10.10 Register description

4.13.10.10.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 DigitalInput USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput04 Bit 3
4 Counter01 USINT ●
6 Counter02 USINT ●
8 Counter03 USINT ●
10 Counter04 USINT ●
30 StatusInput USINT ●
ShortCircuit01 Bit 0
... ...
ShortCircuit04 Bit 3
OpenLine01 Bit 4
... ...
OpenLine04 Bit 7
16 OutputConfig01 USINT ●
18 OutputConfig02 USINT ●
20 OutputConfig03 USINT ●

4.13.10.10.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 Input status of digital inputs 1 to 4 USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput04 Bit 3
4 - Counter01 USINT ●

6 - Counter02 USINT ●
8 - Counter03 USINT ●
10 - Counter04 USINT ●
30 - Status of channels 1 to 4 USINT ●
ShortCircuit01 Bit 0
... ...
ShortCircuit04 Bit 3
OpenLine01 Bit 4
... ...
OpenLine04 Bit 7
16 - ConfigOutput01 USINT ●
18 - ConfigOutput02 USINT ●
20 - ConfigOutput03 USINT ●

1) The offset specifies where the register is within the CAN object.

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4.13.10.10.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.10.10.3.1 Digital input filter

Name:
ConfigOutput03
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

4.13.10.10.3.2 Input status of digital inputs 1 to 4

Name:
DigitalInput or
DigitalInput01 to DigitalInput04
PowerSupply
The input status of digital inputs 1 to 4 is mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits
should be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput02" and
"PowerSupply") or whether this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 15 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
... ...
3 DigitalInput04 0 or 1 Input status - Digital input 4
4-6 Reserved 0
7 PowerSupply 0 Supply voltage too low
1 Supply voltage >80 VAC

4.13.10.10.4 Positive edge counter on digital inputs

Name:
Counter01 to Counter04
These registers cyclically count the positive edges on the individual channels.
Data type Value
USINT Positive edge counter on channel, cyclic

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4.13.10.10.5 Status of channels 1 to 4

Name:
StatusInput01 or
ShortCircuit01 to ShortCircuit04
OpenLine01 to OpenLine04
This register indicates whether an open line or overflow has occurred on the individual channels.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits
should be set up individually as data points in the AS I/O mapping ("ShortCircuit01" through "ShortCircuit02" and
"OpenLine01" through "OpenLine02") or whether this register should be displayed as an individual USINT data
point ("DigitalInput").
Data type Value Information
USINT 0 to 3 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 ShortCircuit01 0 No error
1 Overload on channel 1
... ...
3 ShortCircuit04 0 No error
1 Overload on channel 4
4 OpenLine01 0 No error
1 Open line on channel 1
... ...
7 OpenLine04 0 No error
1 Open line on channel 4

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4.13.10.10.6 Function expansion

Firmware version 802 is offered for hardware variant 7 or higher of the module. This and subsequent firmware
versions provide the user with new configuration possibilities.

4.13.10.10.6.1 Disabling channels and status messages

Name:
OutputConfig01
This register can be used to (de)activate individual channels or just their status responses.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Channel 1 0 Channel enabled
1 Channel disabled
... ...
3 Channel 4 0 Channel enabled
1 Channel disabled
4 Status message - Channel 1 0 Status message activated
1 Status message deactivated
... ...
7 Status message - Channel 4 0 Status message activated
1 Status message deactivated

4.13.10.10.6.2 Replacement values during overload

Name:
OutputConfig02
This register can be used to specify defined replacement values for the individual channels according to the error
situation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Overload - Channel 1 0 Replacement value when overload is FALSE
1 Replacement value when overload is TRUE
... ...
3 Overload - Channel 4 0 Replacement value when overload is FALSE
1 Replacement value when overload is TRUE
4 Open line - Channel 1 0 Replacement value when open line is FALSE
1 Replacement value when open line is TRUE
... ...
7 Open line - Channel 4 0 Replacement value when open line is FALSE
1 Replacement value when open line is TRUE

4.13.10.10.7 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.10.10.8 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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4.13.11 X20DI6371

4.13.11.1 General Information

The module is equipped with six inputs for 1 or 2-wire connections. The X20 6-pin terminal block can be used
for universal 1-line wiring. Two-line wiring can be implemented using the 12-pin terminal block. The inputs on the
module are designed for sink connections.
• 6 digital inputs
• Sink connection
• 2-wire connections
• 24 VDC for sensor supply
• Software input filter can be configured for entire module
• 1-wire connection type with 6-pin terminal block

4.13.11.2 Order data

Model number Short description Figure

Digital input modules
X20DI6371 X20 digital input module, 6 inputs, 24 VDC, sink, configurable
input filter, 2-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 317: X20DI6371 - Order data

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4.13.11.3 Technical data

Product ID X20DI6371
Short description
I/O module 6 digital inputs 24 VDC for 1- or 2-wire connections
General information
B&R ID code 0x1B93
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.15 W
Internal I/O 0.88 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Typ. 3.75 mA
Input filter
Hardware ≤100 μs
Software Default 1 ms, can be configured between 0 and 25 ms in 0.2 ms intervals
Connection type 1- or 2-wire connections
Input circuit Sink
Input resistance Typ. 6.4 kΩ
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
Sensor supply
Voltage Module supply minus voltage drop for short circuit protection
Voltage drop for short circuit protection at 500 mA Max. 2 VDC
Summation current 0.5 A
Short circuit protection Yes
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 318: X20DI6371 - Technical data

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4.13.11.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
e+r Red on / Green single flash Invalid firmware
1-6 Green Input status of the corresponding digital input

4.13.11.5 Pinout

r e

X20 DI 6371
1 2
3 4
5 6

DI 1 DI 2

DI 3 DI 4

DI 5 DI 6

+24 VDC +24 VDC

+24 VDC +24 VDC

+24 VDC +24 VDC

4.13.11.6 Connection example

DI

Sensor 1 Sensor 2

Sensor 3 Sensor 4

Sensor 5 Sensor 6

+24 VDC +24 VDC

GND GND

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4.13.11.7 Input circuit diagram

Input x

VDR

GND

I/O status
LED (green)
Input status

24 V
PTC GND
24 V

4.13.11.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.11.9.3.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

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4.13.11.9 Register description

4.13.11.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 DigitalInput USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput06 Bit 5
18 - ConfigOutput01 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.11.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 Input status of digital inputs 1 to 6 USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput06 Bit 5
18 - ConfigOutput01 USINT ●

1) The offset specifies where the register is within the CAN object.

4.13.11.9.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.11.9.3.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

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4.13.11.9.3.2 Input status of digital inputs 1 to 6

Name:
DigitalInput or
DigitalInput01 to DigitalInput06
The input status of digital inputs 1 to 6 is mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput06") or whether
this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 63 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
... ...
5 DigitalInput06 0 or 1 Input status - Digital input 6

4.13.11.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.11.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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4.13.12 X20DI6372

4.13.12.1 General Information

The module is equipped with six inputs for 1 or 2-wire connections. The X20 6-pin terminal block can be used
for universal 1-line wiring. Two-line wiring can be implemented using the 12-pin terminal block. The inputs on the
module are designed for source connections.
• 6 digital inputs
• Source connection
• 2-wire connections
• 24 VDC for sensor supply
• Software input filter can be configured for entire module
• 1-wire connection type with 6-pin terminal block

4.13.12.2 Order data

Model number Short description Figure

Digital input modules
X20DI6372 X20 digital input module, 6 inputs, 24 VDC, source, configurable
input filter, 2-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 319: X20DI6372 - Order data

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4.13.12.3 Technical data

Product ID X20DI6372
Short description
I/O module 6 digital inputs 24 VDC for 1- or 2-wire connections
General information
B&R ID code 0x1B94
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.15 W
Internal I/O 0.88 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Typ. 3.75 mA
Input filter
Hardware ≤100 μs
Software Default 1 ms, configurable between 0 and 25 ms in 0.2 ms intervals
Connection type 1- or 2-wire connections
Input circuit Source
Input resistance Typ. 6.4 kΩ
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 320: X20DI6372 - Technical data

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4.13.12.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
e+r Red on / Green single flash Invalid firmware
1-6 Green Input status of the corresponding digital input

4.13.12.5 Pinout

r e

X20 DI 6372
1 2
3 4
5 6

DI 1 DI 2

DI 3 DI 4

DI 5 DI 6

GND GND

GND GND

GND GND

4.13.12.6 Connection example

DI

Sensor 1 Sensor 2

Sensor 3 Sensor 4

Sensor 5 Sensor 6

+24 VDC +24 VDC

GND GND

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4.13.12.7 Input circuit diagram

24 V

I/O status
LED (green)
Input status

Input x

VDR

GND

GND

GND

4.13.12.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.12.9.3.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

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4.13.12.9 Register description

4.13.12.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 DigitalInput USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput06 Bit 5
18 - ConfigOutput01 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.12.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 Input status of digital inputs 1 to 6 USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput06 Bit 5
18 - ConfigOutput01 USINT ●

1) The offset specifies where the register is within the CAN object.

4.13.12.9.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.12.9.3.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

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4.13.12.9.3.2 Input status of digital inputs 1 to 6

Name:
DigitalInput or
DigitalInput01 to DigitalInput06
The input status of digital inputs 1 to 6 is mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput06") or whether
this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 63 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
... ...
5 DigitalInput06 0 or 1 Input status - Digital input 6

4.13.12.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.12.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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4.13.13 X20DI6373

4.13.13.1 General Information

The module has 6 inputs. The input circuit can be sink or source thanks to the potential-free design of the inputs.
• 6 digital inputs
• Sink/Source connection
• Software input filter can be configured for entire module

4.13.13.2 Order data

Model number Short description Figure

Digital input modules
X20DI6373 X20 digital input module, 6 inputs, 24 VDC, sink/source, all in-
puts floating, configurable input filter, 2-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 321: X20DI6373 - Order data

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4.13.13.3 Technical data

Product ID X20DI6373
Short description
I/O module 6 digital floating inputs 24 VDC
General information
B&R ID code 0xA7A2
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.15 W
Internal I/O 0.88 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel Yes
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Nominal voltage 24 VDC
Input filter
Hardware ≤100 μs
Software Default 1 ms, can be configured between 0 and 25 ms in 0.2 ms intervals
Input circuit Sink or source
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 322: X20DI6373 - Technical data

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 X20 system modules • Digital input modules • X20DI6373

4.13.13.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
e+r Red on / Green single flash Invalid firmware
1-6 Green Input status of the corresponding digital input

4.13.13.5 Pinout

r e

X20 DI 6373
1 2
3 4
5 6

DI 1+ DI 1-

DI 2+ DI 2-

DI 3+ DI 3-

DI 4+ DI 4-

DI 5+ DI 5-

DI 6+ DI 6-

4.13.13.6 Connection example

+24 VDC1 GND1

DI

Sensor 1

Sensor 2

Sensor 3

Sensor 4

+24 VDC +24 VDC

GND GND

+24 VDC2 GND2

X20 system User's Manual 3.10 1015

X20 system modules • Digital input modules • X20DI6373

4.13.13.7 Input circuit diagram

Input x+

I/O status
LED (green)
VDR
Input status

Input x-

4.13.13.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.13.9.3.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

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 X20 system modules • Digital input modules • X20DI6373

4.13.13.9 Register description

4.13.13.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 DigitalInput USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput06 Bit 5
18 - ConfigOutput01 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.13.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 Input status of digital inputs 1 to 6 USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput06 Bit 5
18 - ConfigOutput01 USINT ●

1) The offset specifies where the register is within the CAN object.

4.13.13.9.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.13.9.3.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

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X20 system modules • Digital input modules • X20DI6373

4.13.13.9.3.2 Input status of digital inputs 1 to 6

Name:
DigitalInput or
DigitalInput01 to DigitalInput06
The input status of digital inputs 1 to 6 is mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput06") or whether
this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 63 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
... ...
5 DigitalInput06 0 or 1 Input status - Digital input 6

4.13.13.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.13.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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 X20 system modules • Digital input modules • X20DI6553

4.13.14 X20DI6553

4.13.14.1 General Information

The module is equipped with 6 inputs for 1-wire connections. It is designed for an input voltage of 100 to 120 VAC.
• 6 digital inputs
• 100 to 120 VAC inputs
• 50 Hz or 60 Hz
• 1-wire connections
• 240 V coded

Danger!
Risk of electric shock!
The terminal block must only be allowed to conduct voltage when it is inserted. It must not under any
circumstances be removed or inserted when voltage is applied or have voltage applied to it when it
is removed.

4.13.14.2 Order data

Model number Short description Figure

Digital input modules
X20DI6553 X20 digital input module, 6 inputs, 100 to 120 VAC, 240 V keyed,
1-wire connections
Required accessories
Bus modules
X20BM12 Bus module, 240 VAC keyed, internal I/O supply continuous
Terminal blocks
X20TB32 X20 terminal block, 12-pin, 240 VAC keyed

Table 323: X20DI6553 - Order data

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X20 system modules • Digital input modules • X20DI6553

4.13.14.3 Technical data

Product ID X20DI6553
Short description
I/O module 6 digital inputs 100 to 120 VAC for 1-wire connections
General information
B&R ID code 0x256F
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
External I/O supply Yes, using software (typical threshold 85 VAC)
Power consumption
Bus 0.21 W
Internal I/O -
External I/O 0.68 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital inputs
Nominal voltage 100 to 120 VAC
Input filter
Software Default 1 ms, can be configured between 0 and 25 ms in 0.2 ms intervals
Hardware
1 -> 0 ≤30 ms
0 -> 1 ≤15 ms
Connection type 1-wire connection
Rated frequency 47 to 63 Hz
Switching threshold
Low <20 VAC
High >79 VAC
Isolation voltage between channel and bus 1 minute 1500 VAC
Input voltage
Maximum 132 VAC
Input current
120 VAC / 50 Hz 8.5 mA
120 VAC / 60 Hz 10 mA
Sensor supply
Voltage Equal to the module supply
Short circuit protection No
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB32 terminal block separately
Order 1x X20BM12 bus module separately
Spacing 12.5 +0.2 mm

Table 324: X20DI6553 - Technical data

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 X20 system modules • Digital input modules • X20DI6553

4.13.14.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
Double flash External supply is too low or not connected
e+r Red on / Green single flash Invalid firmware
1-6 Green Input status of the corresponding digital input

4.13.14.5 Pinout

r e

X20 DI 6553
1 2
3 4
5 6

DI 1 DI 2

DI 3 DI 4

DI 5 DI 6

L L

L L

N N

4.13.14.6 Connection example

DI

Sensor 1 Sensor 2

Sensor 3 Sensor 4

Sensor 5 Sensor 6

L L

N N

+24 VDC +24 VDC

GND GND

X20 system User's Manual 3.10 1021

X20 system modules • Digital input modules • X20DI6553

4.13.14.7 Input circuit diagram

Input status
Input x

Diagnostics status
L U ok

Voltage
monitoring

4.13.14.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.14.9.3.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

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 X20 system modules • Digital input modules • X20DI6553

4.13.14.9 Register description

4.13.14.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 DigitalInput USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput06 Bit 5
PowerSupply Bit 7
18 - ConfigOutput01 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.14.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 Input status of digital inputs 1 to 6 USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput06 Bit 5
PowerSupply Bit 7
18 - ConfigOutput01 USINT ●

1) The offset specifies where the register is within the CAN object.

4.13.14.9.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.14.9.3.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

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X20 system modules • Digital input modules • X20DI6553

4.13.14.9.3.2 Input status of digital inputs 1 to 6

Name:
DigitalInput or
DigitalInput01 to DigitalInput06
PowerSupply
The input status of digital inputs 1 to 6 is mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits
should be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput02" and
"PowerSupply") or whether this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 63 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
... ...
5 DigitalInput04 0 or 1 Input status - Digital input 6
6 Reserved 0
7 PowerSupply 0 Supply voltage too low
1 Supply voltage >80 VAC

4.13.14.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.14.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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 X20 system modules • Digital input modules • X20DI8371

4.13.15 X20DI8371

4.13.15.1 General Information

The module is equipped with eight inputs for 1-wire connections. The module is designed for sink input wiring.
• 8 digital inputs
• Sink connection
• 1-wire connections
• Software input filter can be configured for entire module

4.13.15.2 Order data

Model number Short description Figure

Digital input modules
X20DI8371 X20 digital input module, 8 inputs, 24 VDC, sink, configurable
input filter, 1-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 325: X20DI8371 - Order data

X20 system User's Manual 3.10 1025

X20 system modules • Digital input modules • X20DI8371

4.13.15.3 Technical data

Product ID X20DI8371
Short description
I/O module 8 digital inputs 24 VDC for 1-wire connections
General information
B&R ID code 0xA4AB
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.18 W
Internal I/O -
External I/O 1.2 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Typ. 3.75 mA
Input filter
Hardware ≤100 μs
Software Default 1 ms, configurable between 0 and 25 ms in 0.2 ms intervals
Connection type 1-wire connections
Input circuit Sink
Input resistance Typ. 6.4 kΩ
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 326: X20DI8371 - Technical data

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 X20 system modules • Digital input modules • X20DI8371

4.13.15.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
e+r Red on / Green single flash Invalid firmware
1-8 Green Input status of the corresponding digital input

4.13.15.5 Pinout

r e

X20 DI 8371
1 2
3 4
5 6
7 8

DI 1 DI 2

DI 3 DI 4

DI 5 DI 6

DI 7 DI 8

4.13.15.6 Connection example

DI

Sensor 1 Sensor 2

Sensor 3 Sensor 4

Sensor 5 Sensor 6

Sensor 7 Sensor 8

+24 VDC +24 VDC

GND GND

+24 VDC +24 VDC

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X20 system modules • Digital input modules • X20DI8371

4.13.15.7 Input circuit diagram

Input x

VDR

GND

I/O status
LED (green)
Input status

GND

4.13.15.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.15.9.3.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

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 X20 system modules • Digital input modules • X20DI8371

4.13.15.9 Register description

4.13.15.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 DigitalInput USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
18 - ConfigOutput01 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.15.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 DigitalInput USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
18 - ConfigOutput01 USINT ●

1) The offset specifies where the register is within the CAN object.

4.13.15.9.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.15.9.3.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

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X20 system modules • Digital input modules • X20DI8371

4.13.15.9.3.2 Input state of digital inputs 1 to 8

Name:
DigitalInput or
DigitalInput01 to DigitalInput08
This register is used to indicate the input state of digital inputs 1 to 8.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput08") or whether
this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 255 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input state - Digital input 1
... ...
7 DigitalInput08 0 or 1 Input state - Digital input 8

4.13.15.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.15.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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 X20 system modules • Digital input modules • X20DI9371

4.13.16 X20DI9371

4.13.16.1 General Information

The module is equipped with 12 inputs for 1-wire connections. The module is designed for sink input wiring.
• 12 digital inputs
• Sink connection
• 1-wire connections
• Software input filter can be configured for entire module

4.13.16.2 Order data

Model number Short description Figure

Digital input modules
X20DI9371 X20 digital input module, 12 inputs, 24 VDC, sink, configurable
input filter, 1-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 327: X20DI9371 - Order data

4.13.16.3 Technical data

Product ID X20DI9371
Short description
I/O module 12 digital inputs 24 VDC for 1-wire connections
General information
B&R ID code 0x1B95
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.18 W
Internal I/O -
External I/O 1.75 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Typ. 3.75 mA
Input filter
Hardware ≤100 μs
Software Default 1 ms, configurable between 0 and 25 ms in 0.2 ms intervals
Connection type 1-wire connections
Input circuit Sink
Input resistance Typ. 6.4 kΩ

Table 328: X20DI9371 - Technical data

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X20 system modules • Digital input modules • X20DI9371
Product ID X20DI9371
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 328: X20DI9371 - Technical data

4.13.16.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
e+r Red on / Green single flash Invalid firmware
1 - 12 Green Input status of the corresponding digital input

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4.13.16.5 Pinout

r e

X20 DI 9371
1 2
3 4
5 6
7 8
9 10
11 12

DI 1 DI 2

DI 3 DI 4

DI 5 DI 6

DI 7 DI 8

DI 9 DI 10

DI 11 DI 12

4.13.16.6 Connection example

DI

Sensor 1 Sensor 2

Sensor 3 Sensor 4

Sensor 5 Sensor 6

Sensor 7 Sensor 8

Sensor 9 Sensor 10

Sensor 11 Sensor 12

+24 VDC +24 VDC

GND GND

+24 VDC +24 VDC

4.13.16.7 Input circuit diagram

Input x

VDR

GND

I/O status
LED (green)
Input status

GND

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X20 system modules • Digital input modules • X20DI9371

4.13.16.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.16.10.3.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

4.13.16.9 Derating for the simultaneity factor

Be aware of the derating values below for the simultaneity factor.

Derating of simultaneity factor at 24 VDC input voltage
Horizontal installation
Vertical installation

100

80
Simultaneity factor [%]

0
-25 50 55 60
Ambient temperature [°C]

Derating of simultaneity factor at 28.8 VDC input voltage

Horizontal installation
Vertical installation

100

75
Simultaneity factor [%]

60

0
-25 35 40 50 60
Ambient temperature [°C]

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4.13.16.10 Register description

4.13.16.10.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
- 1 DigitalInput UINT ●
0 1 Input status of digital inputs 1 to 8 USINT
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
1 2 Input status of digital inputs 9 to 12 USINT ●
DigitalInput09 Bit 0
... ...
DigitalInput12 Bit 3
18 - ConfigOutput01 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.16.10.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 Input status of digital inputs 1 to 8 USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
1 1 Input status of digital inputs 9 to 12 USINT ●
DigitalInput09 Bit 0
... ...
DigitalInput12 Bit 3
18 - ConfigOutput01 USINT ●

1) The offset specifies where the register is within the CAN object.

4.13.16.10.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.16.10.3.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

X20 system User's Manual 3.10 1035

X20 system modules • Digital input modules • X20DI9371

4.13.16.10.3.2 Input status of digital inputs 1 to 12

Name:
DigitalInput or
DigitalInput01 to DigitalInput12
The input status of digital inputs 1 to 12 is mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput12") or whether
this register should be displayed as an individual UINT data point ("DigitalInput").
Data type Value Information
UINT 0 to 4095 Packed inputs = on
USINT See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Register 0:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
... ...
7 DigitalInput08 0 or 1 Input status - Digital input 8

Register 1:
Bit Name Value Information
0 DigitalOutput09 0 or 1 Input status - Digital input 9
... ...
3 DigitalOutput12 0 or 1 Input status - Digital input 12

4.13.16.10.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.16.10.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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 X20 system modules • Digital input modules • X20DI9372

4.13.17 X20DI9372

4.13.17.1 General Information

The module is equipped with 12 inputs for 1-wire connections. The module is designed for source input wiring.
• 12 digital inputs
• Source connection
• 1-wire connections
• Software input filter can be configured for entire module

4.13.17.2 Order data

Model number Short description Figure

Digital input modules
X20DI9372 X20 digital input module, 12 inputs, 24 VDC, source, config-
urable input filter, 1-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 329: X20DI9372 - Order data

4.13.17.3 Technical data

Product ID X20DI9372
Short description
I/O module 12 digital inputs 24 VDC for 1-wire connections
General information
B&R ID code 0x1D28
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.18 W
Internal I/O 1.75 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Typ. 3.75 mA
Input filter
Hardware ≤100 μs
Software Default 1 ms, configurable between 0 and 25 ms in 0.2 ms intervals
Connection type 1-wire connections
Input circuit Source
Input resistance Typ. 6.4 kΩ
Switching threshold
Low <5 VDC
High >15 VDC

Table 330: X20DI9372 - Technical data

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X20 system modules • Digital input modules • X20DI9372
Product ID X20DI9372
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 330: X20DI9372 - Technical data

4.13.17.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
e+r Red on / Green single flash Invalid firmware
1 - 12 Green Input status of the corresponding digital input

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 X20 system modules • Digital input modules • X20DI9372

4.13.17.5 Pinout

r e

X20 DI 9372
1 2
3 4
5 6
7 8
9 10
11 12

DI 1 DI 2

DI 3 DI 4

DI 5 DI 6

DI 7 DI 8

DI 9 DI 10

DI 11 DI 12

4.13.17.6 Connection example

DI

Sensor 1 Sensor 2

Sensor 3 Sensor 4

Sensor 5 Sensor 6

Sensor 7 Sensor 8

Sensor 9 Sensor 10

Sensor 11 Sensor 12

+24 VDC +24 VDC

GND GND

GND GND

4.13.17.7 Input circuit diagram

24 V

I/O status
LED (green)
Input status

Input x

VDR

GND

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X20 system modules • Digital input modules • X20DI9372

4.13.17.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.17.10.3.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

4.13.17.9 Derating for the simultaneity factor

Be aware of the derating values below for the simultaneity factor.

Derating of simultaneity factor at 24 VDC input voltage
Horizontal installation
Vertical installation

100

80
Simultaneity factor [%]

0
-25 50 55 60
Ambient temperature [°C]

Derating of simultaneity factor at 28.8 VDC input voltage

Horizontal installation
Vertical installation

100

75
Simultaneity factor [%]

60

0
-25 35 40 50 60
Ambient temperature [°C]

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 X20 system modules • Digital input modules • X20DI9372

4.13.17.10 Register description

4.13.17.10.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
- 1 DigitalInput UINT ●
0 1 Input status of digital inputs 1 to 8 USINT
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
1 2 Input status of digital inputs 9 to 12 USINT ●
DigitalInput09 Bit 0
... ...
DigitalInput12 Bit 3
18 - ConfigOutput01 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.17.10.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 Input status of digital inputs 1 to 8 USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
1 1 Input status of digital inputs 9 to 12 USINT ●
DigitalInput09 Bit 0
... ...
DigitalInput12 Bit 3
18 - ConfigOutput01 USINT ●

1) The offset specifies where the register is within the CAN object.

4.13.17.10.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.17.10.3.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

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X20 system modules • Digital input modules • X20DI9372

4.13.17.10.3.2 Input status of digital inputs 1 to 12

Name:
DigitalInput or
DigitalInput01 to DigitalInput12
The input status of digital inputs 1 to 12 is mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput12") or whether
this register should be displayed as an individual UINT data point ("DigitalInput").
Data type Value Information
UINT 0 to 4095 Packed inputs = on
USINT See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Register 0:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
... ...
7 DigitalInput08 0 or 1 Input status - Digital input 8

Register 1:
Bit Name Value Information
0 DigitalOutput09 0 or 1 Input status - Digital input 9
... ...
3 DigitalOutput12 0 or 1 Input status - Digital input 12

4.13.17.10.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.17.10.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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 X20 system modules • Digital input modules • X20DID371

4.13.18 X20DID371

4.13.18.1 General Information

The module is equipped with 8 inputs for 1-wire or 2-wire connections. The module is designed for sink input wiring.
• 8 digital inputs
• Sink connection
• 2-wire connections
• 24 VDC for sensor supply
• Software input filter can be configured for entire module

4.13.18.2 Order data

Model number Short description Figure

Digital input modules
X20DID371 X20 digital input module, 8 inputs, 24 VDC, sink, configurable
input filter, 2-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB1F X20 terminal block, 16-pin, 24 VDC keyed

Table 331: X20DID371 - Order data

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X20 system modules • Digital input modules • X20DID371

4.13.18.3 Technical data

Product ID X20DID371
Short description
I/O module 8 digital inputs 24 VDC for 1- or 2-wire connections
General information
B&R ID code 0xC0E7
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.13 W
Internal I/O 1.2 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Typ. 3.75 mA
Input filter
Hardware ≤100 μs
Software Default 1 ms, can be configured between 0 and 25 ms in 0.2 ms intervals
Connection type 1- or 2-wire connections
Input circuit Sink
Input resistance Typ. 6.4 kΩ
Sensor supply 0.5 A total current
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB1F terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 332: X20DID371 - Technical data

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 X20 system modules • Digital input modules • X20DID371

4.13.18.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
S Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
Red Off Module supply not connected or everything OK
Red on / Green single flash Invalid firmware
1-8 Green Input status of the corresponding digital input

4.13.18.5 Pinout

S 1 2
3 4

X20 DI D371
5 6
7 8

DI 1 DI 2
DI 3 DI 4
DI 5 DI 6
DI 7 DI 8
+24 VDC +24 VDC
+24 VDC +24 VDC
+24 VDC +24 VDC
+24 VDC +24 VDC

4.13.18.6 Connection example

DI

Sensor 1 Sensor 2

Sensor 3 Sensor 4

Sensor 5 Sensor 6

Sensor 7 Sensor 8

+24 VDC +24 VDC

GND GND

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X20 system modules • Digital input modules • X20DID371

4.13.18.7 Input circuit diagram

Input x

I/O status
LED (green)
Input status

GND

24 V
PTC
24 V

4.13.18.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.18.9.3.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

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 X20 system modules • Digital input modules • X20DID371

4.13.18.9 Register description

4.13.18.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 DigitalInput USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
18 - ConfigOutput01 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.18.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 Input state of digital inputs 1 to 8 USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
18 - ConfigOutput01 USINT ●

1) The offset specifies where the register is within the CAN object.

4.13.18.9.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.18.9.3.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

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X20 system modules • Digital input modules • X20DID371

4.13.18.9.3.2 Input state of digital inputs 1 to 8

Name:
DigitalInput or
DigitalInput01 to DigitalInput08
This register is used to indicate the input state of digital inputs 1 to 8.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput08") or whether
this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 255 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input state - Digital input 1
... ...
7 DigitalInput08 0 or 1 Input state - Digital input 8

4.13.18.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.18.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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 X20 system modules • Digital input modules • X20DIF371

4.13.19 X20DIF371

4.13.19.1 General Information

The module is equipped with 16 inputs for 1-wire connections. The module is designed for sink input wiring.
• 16 digital inputs
• Sink connection
• 1-wire connections
• Software input filter can be configured for entire module

4.13.19.2 Order data

Model number Short description Figure

Digital input modules
X20DIF371 X20 digital input module, 16 inputs, 24 VDC, sink, configurable
input filter, 1-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB1F X20 terminal block, 16-pin, 24 VDC keyed

Table 333: X20DIF371 - Order data

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X20 system modules • Digital input modules • X20DIF371

4.13.19.3 Technical data

Product ID X20DIF371
Short description
I/O module 16 digital inputs 24 VDC for 1-wire connections
General information
B&R ID code 0xC0E8
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Power consumption
Bus 0.18 W
Internal I/O -
External I/O 1.47 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital inputs
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Typ. 2.68 mA
Input filter
Hardware ≤100 μs
Software Default 1 ms, configurable between 0 and 25 ms in 0.2 ms intervals
Connection type 1-wire connections
Input circuit Sink
Input resistance Typ. 8.9 kΩ
Simultaneousness
With 24 V I/O supply 100% 1)
With 28.8 V I/O supply 75% 1)
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB1F terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 334: X20DIF371 - Technical data

1) Derating must be taken into consideration.

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 X20 system modules • Digital input modules • X20DIF371

4.13.19.4 Status LEDs

For a description of the various operating modes, see section 2.11.1 "re LEDs".
Image LED Color Status Description
S Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
Red Off Module supply not connected or everything OK
Red on / Green single flash Invalid firmware
1 - 16 Green Input status of the corresponding digital input

4.13.19.5 Pinout

S 1 2
3 4

X20 DI F371
5 6
7 8
9 10
11 12
13 14
15 16

DI 1 DI 2
DI 3 DI 4
DI 5 DI 6
DI 7 DI 8
DI 9 DI 10
DI 11 DI 12
DI 13 DI 14
DI 15 DI 16

4.13.19.6 Connection example

DI

Sensor 1 Sensor 2

Sensor 3 Sensor 4

Sensor 5 Sensor 6

Sensor 7 Sensor 8

Sensor 9 Sensor 10

Sensor 11 Sensor 12

Sensor 13 Sensor 14

Sensor 15 Sensor 16

+24 VDC +24 VDC

GND GND

+24 VDC +24 VDC

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X20 system modules • Digital input modules • X20DIF371

4.13.19.7 Input circuit diagram

Input x

GND
Input status

I/O status
LED (green)

GND GND

4.13.19.8 Input filter

An input filter is available for each input. The input delay can be set using register 4.13.19.9.3.1 "ConfigOutput01".
Disturbance pulses which are shorter than the input delay are suppressed by the input filter.
Input
signal

Time

Signal after tDelay tDelay tDelay

the filter

Time

tDelay ⇒ Input delay

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 X20 system modules • Digital input modules • X20DIF371

4.13.19.9 Register description

4.13.19.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
- 1 DigitalInput UINT ●
0 1 Input status of digital inputs 1 to 8 USINT
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
1 2 Input status of digital inputs 9 to 16 USINT ●
DigitalInput09 Bit 0
... ...
DigitalInput16 Bit 7
18 - ConfigOutput01 USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.13.19.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 Input status of digital inputs 1 to 8 USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
1 1 Input status of digital inputs 9 to 16 USINT ●
DigitalInput09 Bit 0
... ...
DigitalInput16 Bit 7
18 - ConfigOutput01 USINT ●

1) The offset specifies where the register is within the CAN object.

4.13.19.9.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

4.13.19.9.3.1 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

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X20 system modules • Digital input modules • X20DIF371

4.13.19.9.3.2 Input status of digital inputs 1 to 16

Name:
DigitalInput or
DigitalInput01 to DigitalInput16
The input status of digital inputs 9 to 16 is mapped in this register.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput16") or whether
this register should be displayed as an individual UINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 65535 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Register 0:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
... ...
7 DigitalInput08 0 or 1 Input status - Digital input 8

Register 1:
Bit Name Value Information
0 DigitalInput09 0 or 1 Input status - Digital input 9
... ...
7 DigitalInput16 0 or 1 Input status - Digital input 16

4.13.19.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.13.19.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

1054 X20 system User's Manual 3.10

 X20 system modules • Digital mixed modules • Brief information

4.14 Digital mixed modules

Digital mixed modules are a combination of digital input and output modules. The states of the digital inputs or
outputs are shown by the status LEDs.

4.14.1 Brief information

Product ID Short description on page
X20DM9324 X20 digital mixed module, 8 inputs, 24 VDC, sink, configurable input filter, 4 outputs, 24 VDC, 0.5 A, source, 1056
1-wire connections

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X20 system modules • Digital mixed modules • X20DM9324

4.14.2 X20DM9324

4.14.2.1 General information

This module is equipped with 8 inputs and 4 outputs for 1-wire connections. The inputs are designed for sink
connections, the outputs for source connections.
• 8 digital inputs, sink connections
• 4 digital outputs, source connections
• 1-wire connections
• Configurable software input filter for entire module
• Integrated output protection

4.14.2.2 Order data

Model number Short description Figure

Digital input/output modules
X20DM9324 X20 digital mixed module, 8 inputs, 24 VDC, sink, configurable
input filter, 4 outputs, 24 VDC, 0.5 A, source, 1-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 335: X20DM9324 - Order data

4.14.2.3 Technical data

Product ID X20DM9324
Short description
I/O module 8 digital inputs 24 VDC for 1-wire connections, 4 digital outputs 24 VDC for 1-wire connections
General information
Nominal voltage 24 VDC
B&R ID code 0x20B9
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, using status LED and software (output error status)
Power consumption
Bus 0.21 W
Internal I/O 0.5 W
External I/O 1.17 W
Additional power dissipation caused by the actua- +0.21
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital inputs
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Typ. 3.75 mA
Input filter
Hardware ≤100 µs
Software Default 1 ms, configurable between 0 and 25 ms in 0.2 ms intervals
Connection type 1-wire connections
Input circuit Sink

Table 336: X20DM9324 - Technical data

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 X20 system modules • Digital mixed modules • X20DM9324
Product ID X20DM9324
Input resistance Typ. 6.4 kΩ
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
Digital outputs
Design FET positive switching
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.5 A
Total nominal current 2.0 A
Connection type 1-wire connections
Output circuit Source
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching inductive loads (see section "Switching inductive loads")
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 5 µA
RDS(on) 210 mΩ
Residual voltage <0.3 V at 0.5 A rated current
Max. continuous current 6.0 A
Peak short circuit current <12 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay
0 -> 1 <300 µs
1 -> 0 <300 µs
Switching frequency
Resistive load Max. 500 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Typ. 50 VDC
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 336: X20DM9324 - Technical data

1) Number of outputs x RDS(on) x nominal output current2.

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4.14.2.4 Status LEDs

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
e+r Red on / Green single flash Invalid firmware
1-8 Green Input status of the corresponding digital input
1-4 Orange Output status of the corresponding digital output

4.14.2.5 Pinout

r e

X20 DM 9324
1 2
3 4
5 6
7 8
1 2
3 4

DI 1 DI 2

DI 3 DI 4

DI 5 DI 6

DI 7 DI 8

DO 1 DO 2

DO 3 DO 4

4.14.2.6 Connection example

DM

Sensor 1 Sensor 2

Sensor 3 Sensor 4

Sensor 5 Sensor 6

Sensor 7 Sensor 8

Actuator 1 Actuator 2

Actuator 3 Actuator 4

+24 VDC +24 VDC

GND GND

+24 VDC GND GND +24 VDC

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4.14.2.7 Input circuit diagram

Input x

VDR

GND

I/O status
LED (green)
Input status

GND

4.14.2.8 Output circuit diagram

24 V

High-side
Output status
Logic
Output x

VDR

GND

I/O status
Output LED (orange)
monitoring

GND

4.14.2.9 Switching inductive loads

100 H 10 H
1000

1H

Coil resistance
Coil inductance
[Ω] 100 mH

100

10 mH

50
0.1 1 10 100

Max. switching cycles / second

(with 90% duty cycle)

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4.14.2.10 Register description

4.14.2.10.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 DigitalInput USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
2 0 DigitalOutput ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
18 - ConfigOutput01 USINT ●
30 2 StatusInput01 USINT ●
StatusDigitalOutput01 Bit 0
...
StatusDigitalOutput04 Bit 3

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.14.2.10.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 Input state of digital inputs 1 to 8 USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
2 0 Switching state of digital outputs 1 to 4 ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
18 - ConfigOutput01 USINT ●
30 - Status of digital outputs 1 to 4 USINT ●
StatusDigitalOutput01 Bit 0
...
StatusDigitalOutput04 Bit 3

1) The offset specifies where the register is within the CAN object.

4.14.2.10.3 Digital inputs

Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.

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4.14.2.10.3.1 Input state of digital inputs 1 to 8

Name:
DigitalInput or
DigitalInput01 to DigitalInput08
This register is used to indicate the input state of digital inputs 1 to 8.
Function model 0 - Standard only:
The "packed inputs" setting in the AS I/O configuration is used to determine whether all of this register's bits should
be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput08") or whether
this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 255 Packed inputs = on
See bit structure Packed inputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input state - Digital input 1
... ...
7 DigitalInput08 0 or 1 Input state - Digital input 8

4.14.2.10.3.2 Digital input filter

Name:
ConfigOutput01
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs. It makes sense to enter values in steps of 2, however, since
the input signals are sampled every 200 μs.
Data type Value Filters
USINT 0 No software filter
2 0.2 ms
... ...
250 25 ms - Higher values are limited to this value

4.14.2.10.4 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.14.2.10.4.1 Switching state of digital outputs 1 to 4

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput04
The switching state of digital outputs 1 to 4 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 15 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
3 DigitalOutput04 0 Digital output 04 reset
1 Digital output 04 set

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4.14.2.10.5 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

4.14.2.10.5.1 Status of digital outputs 1 to 4

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput04
The status of digital outputs 1 to 4 is mapped in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through
"StatusDigitalOutput0x") or whether this register should be displayed as an individual USINT data point
("StatusInput01").
Data type Value Information
USINT 0 to 15 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Value Information
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
... ...
3 StatusDigitalOutput04 0 Channel 04: No error
1 Channel 04: Short circuit or overload

4.14.2.10.6 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Without filtering 100 μs
With filtering 150 μs

4.14.2.10.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Without filtering 100 μs
With filtering 200 μs

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 X20 system modules • Digital output modules • Brief information

4.15 Digital output modules

Digital output modules are used to control external loads (relays, motors, solenoids). The states of the digital
outputs are indicated by status LEDs.

4.15.1 Brief information

Product ID Short description on page
X20DO2321 X20 digital output module, 2 outputs, 24 VDC, 0.5 A, sink, 3-wire connections 1066
X20DO2322 X20 digital output module, 2 outputs, 24 VDC, 0.5 A, source, 3-wire connections 1074
X20DO2623 X20 digital output module, 2 outputs, 100-240 VAC, 1 A, source, 240 V keyed, 3-wire connections 1082
X20DO2633 X20 digital output module, 2 triac outputs, 12 to 240 VAC, 2 A, L switching, phase angle control, 240 V keyed 1091
X20DO2649 X20 digital output module, 2 relays, changeover contacts, 230 VAC / 5 A, 24 VDC / 5 A 1106
X20DO4321 X20 digital output module, 4 outputs, 24 VDC, 0.5 A, sink, 3-wire connections 1112
X20DO4322 X20 digital output module, 4 outputs, 24 VDC, 0.5 A, source, 3-wire connections 1120
X20DO4331 X20 digital output module, 4 outputs, 24 VDC, 2 A, sink, 3-wire connections 1128
X20DO4332 X20 digital output module, 4 outputs, 24 VDC, 2 A, source, 3-wire connections 1138
X20DO4529 X20 digital output module, 4 relays, changeover contacts, 115 VAC / 0.5 A, 24 VDC / 1 A 1148
X20DO4613 X20 digital output module, 4 triac coupler outputs, 12 to 240 VAC, 50 mA, zero-crossing detection, 240 V keyed,... 1154
X20DO4623 X20 digital output module, 4 outputs, 100-240 VAC, 0.5 A, source, 240 V keyed, 2-wire connections 1167
X20DO4633 X20 digital output module, 4 triac outputs, 12 to 240 VAC, 1 A, L switching, phase angle control, 240 V keyed 1175
X20DO4649 X20 digital output module, 4 relays, N.O. contacts, 240 VAC / 5 A 1190
X20DO6321 X20 digital output module, 6 outputs, 24 VDC, 0.5 A, sink, 2-wire connections 1196
X20DO6322 X20 digital output module, 6 outputs, 24 VDC, 0.5 A, source, 2-wire connections 1202
X20DO6325 X20 digital output module, 6 outputs, 24 VDC, 0.5 A, source, open line and overload detection, 2-wire connec- 1210
tions
X20DO6529 X20 digital output module, 6 relays, normally open contacts, 115 VAC / 0.5 A, 30 VDC / 1 A 1222
X20DO6639 X20 digital output module, 6 relays, normally open contacts, 240 VAC / 2 A, 30 VDC / 2 A 1228
X20DO8232 X20 digital output module, 8 outputs, 12 VDC, 2.0 A, source, supply directly on module, 1 wire technology 1234
X20DO8322 X20 digital output module, 8 outputs, 24 VDC, 0.5 A, source, 1-wire connections 1245
X20DO8323 X20 digital output module, 8 outputs, 12 to 24 V, 0.5 A, sink/source, 1-wire connections, full bridge, half bridge, 1252
thermal overload protection
X20DO8331 X20 digital output module, 8 outputs, 24 VDC, 2 A, sink, supply directly on module, 1-wire connections 1260
X20DO8332 X20 digital output module, 8 outputs, 24 VDC, 2 A, source, supply directly on module, 1-wire connections 1271
X20DO9321 X20 digital output module, 12 outputs, 24 VDC, 0.5 A, sink, 1-wire connections 1282
X20DO9322 X20 digital output module, 12 outputs, 24 VDC, 0.5 A, source, 1-wire connections 1289
X20DOD322 X20 digital output module, 8 outputs, 24 VDC, 0.5 A, source, 2-wire connections 1297
X20DOF322 X20 digital output module, 16 outputs, 24 VDC, 0.5 A, source, 1-wire connections 1303

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X20 system modules • Digital output modules • Calculation of the additional power dissipation resulting from
actuators
4.15.2 Calculation of the additional power dissipation resulting from actuators

Calculation of power dissipation when specifying RDS(on)

Explaining output load with an X20DO4332 example

DO

1A 0.6 A

Actuator 2
Actuator 1
1.2 A 1A

Actuator 4
Actuator 3

+24 VDC +24 VDC

GND GND

Figure 314: Calculation of power dissipation when specifying RDS(on)

Theoretically highest power dissipation resulting from actuators:

Number of outputs * RDSon * nominal output current2 = power dissipation
4 * 140 mΩ * 2 A2 = 2.24 W
Power dissipation resulting from actuators in this example:
140 mΩ * (1 A2 + 0.6 A2 + 1.2 A2 + 1 A2) = 0.532 W

Power dissipation calculation when specifying the residual voltage

Explaining output load with an X20DO4623 example

DO

0.5 A 0.2 A

0.3 A 0.4 A
Actuator 1

Actuator 2
Actuator 4
Actuator 3

L L

N N

+24 VDC +24 VDC

GND GND

Figure 315: Power dissipation calculation when specifying the residual voltage
Theoretically highest power dissipation resulting from actuators:
Number of outputs * residual voltage * nominal output current = power dissipation
4 * 1.6 V * 0.5 A = 3.2 W
Power dissipation resulting from actuators in this example:
1.6 V * (0.5 A + 0.2 A + 0.3 A + 0.4 A) = 2.24 W

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actuators
Power dissipation calculation when specifying the contact resistance
Explaining output load with an X20DO4649 example

DO

3A

3A

230 VAC

+24 VDC +24 VDC

GND GND

Figure 316: Power dissipation calculation when specifying the contact resistance
Theoretically highest power dissipation resulting from actuators:
Number of outputs * contact resistance * nominal output current2 = power dissipation
4 * 15 mΩ * 5 A2 = 1.5 W
Power dissipation resulting from actuators in this example:
15 mΩ * (3 A2 + 3 A2 ) = 0.27 W

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X20 system modules • Digital output modules • X20DO2321

4.15.3 X20DO2321

4.15.3.1 General information

The module is equipped with 2 outputs for 3-wire connections. It is designed for X20 6-pin terminal blocks. If needed
(e.g. for logistical reasons), the 12-pin terminal block can also be used.
• 2 digital outputs
• Sink connection
• 3-wire connections
• 24 VDC and GND for actuator supply
• Integrated output protection
• OSP mode

4.15.3.2 Order data

Model number Short description Figure

Digital output modules
X20DO2321 X20 digital output module, 2 outputs, 24 VDC, 0.5 A, sink, 3-wire
connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 337: X20DO2321 - Order data

4.15.3.3 Technical data

Product ID X20DO2321
Short description
I/O module 2 digital outputs 24 VDC for 3-wire connections
General information
B&R ID code 0x22B3
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, with status LED and software status (output error status)
Power consumption
Bus 0.13 W
Internal I/O 0.3 W
Additional power dissipation caused by the actua- +0.06
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital outputs
Design FET negative switching
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.5 A
Total nominal current 1.0 A
Connection type 3-wire connections
Output circuit Sink

Table 338: X20DO2321 - Technical data

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Product ID X20DO2321
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")
Actuator supply 0.5 A in total for output-independent actuator supply
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 75 µA
RDS(on) 120 mΩ
Residual voltage <0.15 V at 0.5 A rated current
Peak short circuit current <7 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay
0 -> 1 <300 µs
1 -> 0 <300 µs
Switching frequency
Resistive load Max. 500 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Typ. 50 VDC
Isolation voltage between channel and bus 500 Veff
Actuator supply
Voltage Module supply minus voltage drop for short circuit protection
Voltage drop for short circuit protection at 500 mA Max. 2 V
Short circuit protection Yes
Power consumption
Actuator supply Max. 12.0 W 2)
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 338: X20DO2321 - Technical data

1) Number of outputs x RDS(on) x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the module.)
2) The power consumption of the sensors connected to the module may not exceed 12 W.

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4.15.3.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
Flickering (ap- Module is in OSP state
prox. 10 Hz)
e Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
e+r Red on / Green single flash Invalid firmware
1-2 Orange Output status of the corresponding digital output

Table 339: Status LEDs

4.15.3.5 Pinout

r e

X20 DO 2321
1 2

DO 1 DO 2

+24 VDC +24 VDC

GND GND

Figure 317: Pinout

4.15.3.6 Connection example

DO
Actuator 1

Actuator 2

+24 VDC +24 VDC

GND GND

Figure 318: Connection example

4.15.3.7 OSP hardware requirements

In order to best use OSP mode, make sure when creating the application that the output module and CPU have
separate power supplies.

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4.15.3.8 Output circuit diagram

24 V

I/O status
LED (orange)
Low-side
Output status Output x
Logic

VDR
GND
Output
monitoring GND

24 V

GND 24 V

PTC
GND

GND

Figure 319: Output circuit diagram

4.15.3.9 Switching inductive loads

Environmental temperature: 60°C, all outputs with the same load

100 H 10 H
1000
Switching voltage:

28.8 V
1H
24.0 V

Coil resistance Coil inductance

[Ω] 100 mH

100

10 mH
50
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.3.10 Register description

4.15.3.10.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
DigitalOutput02 Bit 1
30 1 StatusInput01 USINT ●
StatusDigitalOutput01 Bit 0
StatusDigitalOutput02 Bit 1

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.3.10.2 Function model 1 - OSP

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 2 USINT ●
DigitalOutput01 Bit 0
DigitalOutput02 Bit 1
30 1 Status of digital outputs 1 to 2 USINT ●
StatusDigitalOutput01 Bit 0
StatusDigitalOutput02 Bit 1
34 1 Activating the OSP output in the module USINT ●
OSPValid Bit 0
32 - CfgOSPMode USINT ●
36 - CfgOSPValue USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.3.10.3 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 2 USINT ●
DigitalOutput01 Bit 0
DigitalOutput02 Bit 1
30 - Status of digital outputs 1 to 2 USINT ●
StatusDigitalOutput01 Bit 0
StatusDigitalOutput02 Bit 1

1) The offset specifies where the register is within the CAN object.

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4.15.3.10.4 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.3.10.4.1 Switching state of digital outputs 1 to 2

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput02
This register is used to store the switching state of digital outputs 1 to 2.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 3 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
1 DigitalOutput02 0 Digital output 02 reset
1 Digital output 02 set

4.15.3.10.5 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

4.15.3.10.5.1 Status of digital outputs 1 to 2

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput02
The status of digital outputs 1 to 2 is mapped in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through
"StatusDigitalOutput0x") or whether this register should be displayed as an individual USINT data point
("StatusInput01").
Data type Value Information
USINT 0 to 3 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
1 StatusDigitalOutput02 0 Channel 02: No error
1 Channel 02: Short circuit or overload

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4.15.3.10.6 "OSP" function model

In the "OSP" function model (Operator Set Predefined), the user defines an analog value or digital pattern. This
OSP value is output as soon as communication between the module and master is interrupted.
Functionality
The user can choose between two OSP modes:
• Retain last valid value
• Replace with static value
In the first case, the module retains the last value as validly recognized output state.
When selecting the mode, "Replace with static value" a plausible output value must be entered in the corresponding
value register. If an OSP event occurs, this value will be output instead of the value currently requested by the task.

4.15.3.10.6.1 Activating the OSP output in the module

Name:
OSPValid
This data point offers the possibility to start module output and request OSP operation during running operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Request OSP operation (after initial start or module in Standby)
0 OSPValid
1 Request normal operation
1-7 0 Reserved

There is one OSPValid bit on the module, which is managed by the user task. It must be set when the enabled
channels are started. As long as the OSPValid bit remains set in the module, the module behaves the same as
the "Standard" function model.
If an OSP event occurs (e.g. communication between the module and master CPU interrupted) then the OSPValid
bit will be reset on the module. The module enters OSP mode and the output occurs in the "OSPMode" register
according to the configuration.
The following applies:
The OSP replacement value remains even after the communication channel has recovered. OSP mode
is only exited when a set OSPValid bit is transferred.
When the master CPU is restarted, the OSPValid bit is re-initialized on the master CPU. It must once
more be set by the application and transferred via the bus.
When temporary communication errors occur between the module and master CPU (e.g. due to EMC),
a few bus cycles will pass without refreshing the cyclic registers. The OSPValid bit is reset internally in
the module - the bit in the CPU however remains set. Upon the next successful transfer, the OSPValid
bit in the module is set again and the module returns to normal operation.
The ModulOK bit can be evaluated if the task in the master CPU needs to know which output mode the module
is currently in.

Warning!
If the OSPValid bit is reset to "0" on the module, then the output state no longer depends on the
responsible task in the master CPU. However, output still occurs according to the configuration of the
OSP replacement value.

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4.15.3.10.6.2 Setting the OSP mode

Name:
CfgOSPMode
This register essentially controls a channel's behavior when OSP is being used.
Data type Value Description
USINT 0 Replace with static value
1 Retain last valid value

4.15.3.10.6.3 Define the OSP digital output value

Name:
CfgOSPValue
This register contains the digital output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 0 or 1 OSP output value for channel DigitalOutput00
... ...
x 0 or 1 OSP output value for channel DigitalOutput0x

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.15.3.10.7 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.3.10.8 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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4.15.4 X20DO2322

4.15.4.1 General information

The module is equipped with 2 outputs for 3-wire connections. It is designed for X20 6-pin terminal blocks. If needed
(e.g. for logistical reasons), the 12-pin terminal block can also be used.
• 2 digital outputs
• Source connection
• 3-wire connections
• 24 VDC and GND for actuator supply
• Integrated output protection
• OSP mode

4.15.4.2 Order data

Model number Short description Figure

Digital output modules
X20DO2322 X20 digital output module, 2 outputs, 24 VDC, 0.5 A, source, 3-
wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 340: X20DO2322 - Order data

4.15.4.3 Technical data

Product ID X20DO2322
Brief description
I/O module 2 digital outputs 24 VDC for 3-wire connections
General information
B&R ID code 0x1B96
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, with status LED and software status (output error status)
Power consumption
Bus 0.13 W
Internal I/O 0.33 W
Additional power dissipation caused by the actua- +0.1
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital outputs
Design FET positive switching
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.5 A
Total nominal current 1.0 A
Connection type 3-wire connections
Output circuit Source

Table 341: X20DO2322 - Technical data

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Product ID X20DO2322
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")
Actuator supply 0.5 A in total for output-independent actuator supply
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 5 µA
RDS(on) 210 mΩ
Max. continuous current 6.0 A
Peak short circuit current <12 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay 2)
0 -> 1 <300 µs
1 -> 0 <300 µs
Switching frequency
Resistive load 2) Max. 500 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Typ. 50 VDC
Isolation voltage between channel and bus 500 Veff
Actuator supply
Voltage Module supply minus voltage drop for short circuit protection
Voltage drop for short circuit protection at 500 mA Max. 2 V
Short circuit protection Yes
Power consumption
Actuator supply Max. 12.0 W 3)
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 341: X20DO2322 - Technical data

1) Number of outputs x RDS(on) x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the module.)
2) At loads ≤ 1 kΩ
3) The power consumption of the sensors connected to the module may not exceed 12 W.

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4.15.4.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
Flickering (ap- Module is in OSP state
prox. 10 Hz)
e Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
e+r Red on / Green single flash Invalid firmware
1-2 Orange Output status of the corresponding digital output

Table 342: Status LEDs

4.15.4.5 Pinout

r e

X20 DO 2322
1 2

DO 1 DO 2

+24 VDC +24 VDC

GND GND

Figure 320: Pinout

4.15.4.6 Connection example

DO
Actuator 1

Actuator 2

+24 VDC +24 VDC

GND GND

Figure 321: Connection example

Caution!
If the module is operated outside of specifications, the output current can increase above the maximum
permissible nominal current. This applies to individual channels and also to the summation current
for the module.
Therefore sufficient cable cross sections or external safety measures must be used.

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4.15.4.7 OSP hardware requirements

In order to best use OSP mode, make sure when creating the application that the output module and CPU have
separate power supplies.

4.15.4.8 Output circuit diagram

24 V

High-side
Output status
Logic
Output x

GND

I/O status
Output LED (orange) 24 V
PTC
monitoring
24 V

GND
GND

Figure 322: Output circuit diagram

4.15.4.9 Switching inductive loads

Environmental temperature: 60°C, all outputs with the same load

100 H 10 H
1000
Switching voltage:
1H
28.8 V
24.0 V

100 mH
Coil resistance Coil inductance
[Ω]

100
10 mH

50
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.4.10 Register description

4.15.4.10.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
DigitalOutput02 Bit 1
30 1 StatusInput01 USINT ●
StatusDigitalOutput01 Bit 0
StatusDigitalOutput02 Bit 1

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.4.10.2 Function model 1 - OSP

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 2 USINT ●
DigitalOutput01 Bit 0
DigitalOutput02 Bit 1
30 1 Status of digital outputs 1 to 2 USINT ●
StatusDigitalOutput01 Bit 0
StatusDigitalOutput02 Bit 1
34 1 Activating the OSP output in the module USINT ●
OSPValid Bit 0
32 - CfgOSPMode USINT ●
36 - CfgOSPValue USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.4.10.3 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 2 USINT ●
DigitalOutput01 Bit 0
DigitalOutput02 Bit 1
30 - Status of digital outputs 1 to 2 USINT ●
StatusDigitalOutput01 Bit 0
StatusDigitalOutput02 Bit 1

1) The offset specifies where the register is within the CAN object.

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4.15.4.10.4 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.4.10.4.1 Switching state of digital outputs 1 to 2

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput02
This register is used to store the switching state of digital outputs 1 to 2.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 3 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
1 DigitalOutput02 0 Digital output 02 reset
1 Digital output 02 set

4.15.4.10.5 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

4.15.4.10.5.1 Status of digital outputs 1 to 2

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput02
The status of digital outputs 1 to 2 is mapped in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through
"StatusDigitalOutput0x") or whether this register should be displayed as an individual USINT data point
("StatusInput01").
Data type Value Information
USINT 0 to 3 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
1 StatusDigitalOutput02 0 Channel 02: No error
1 Channel 02: Short circuit or overload

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4.15.4.10.6 "OSP" function model

In the "OSP" function model (Operator Set Predefined), the user defines an analog value or digital pattern. This
OSP value is output as soon as communication between the module and master is interrupted.
Functionality
The user can choose between two OSP modes:
• Retain last valid value
• Replace with static value
In the first case, the module retains the last value as validly recognized output state.
When selecting the mode, "Replace with static value" a plausible output value must be entered in the corresponding
value register. If an OSP event occurs, this value will be output instead of the value currently requested by the task.

4.15.4.10.6.1 Activating the OSP output in the module

Name:
OSPValid
This data point offers the possibility to start module output and request OSP operation during running operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Request OSP operation (after initial start or module in Standby)
0 OSPValid
1 Request normal operation
1-7 0 Reserved

There is one OSPValid bit on the module, which is managed by the user task. It must be set when the enabled
channels are started. As long as the OSPValid bit remains set in the module, the module behaves the same as
the "Standard" function model.
If an OSP event occurs (e.g. communication between the module and master CPU interrupted) then the OSPValid
bit will be reset on the module. The module enters OSP mode and the output occurs in the "OSPMode" register
according to the configuration.
The following applies:
The OSP replacement value remains even after the communication channel has recovered. OSP mode
is only exited when a set OSPValid bit is transferred.
When the master CPU is restarted, the OSPValid bit is re-initialized on the master CPU. It must once
more be set by the application and transferred via the bus.
When temporary communication errors occur between the module and master CPU (e.g. due to EMC),
a few bus cycles will pass without refreshing the cyclic registers. The OSPValid bit is reset internally in
the module - the bit in the CPU however remains set. Upon the next successful transfer, the OSPValid
bit in the module is set again and the module returns to normal operation.
The ModulOK bit can be evaluated if the task in the master CPU needs to know which output mode the module
is currently in.

Warning!
If the OSPValid bit is reset to "0" on the module, then the output state no longer depends on the
responsible task in the master CPU. However, output still occurs according to the configuration of the
OSP replacement value.

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4.15.4.10.6.2 Setting the OSP mode

Name:
CfgOSPMode
This register essentially controls a channel's behavior when OSP is being used.
Data type Value Description
USINT 0 Replace with static value
1 Retain last valid value

4.15.4.10.6.3 Define the OSP digital output value

Name:
CfgOSPValue
This register contains the digital output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 0 or 1 OSP output value for channel DigitalOutput00
... ...
x 0 or 1 OSP output value for channel DigitalOutput0x

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.15.4.10.7 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.4.10.8 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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4.15.5 X20DO2623

4.15.5.1 General information

The module is a digital output module that is equipped with 2 SSR outputs with zero cross-over switches and uses
3-line connections. The module is also equipped with integrated full-wave control. The supply (L and N) is fed
directly to the module.
• 2 digital outputs
• Outputs with integrated snubber circuit
• Outputs with 100 to 240 VAC
• L switching
• 50 Hz or 60 Hz
• 3-wire connections
• Integrated full-wave control
• 240 V coding

Danger!
Risk of electric shock!
The terminal block must only be allowed to conduct voltage when it is inserted. It must not under any
circumstances be removed or inserted when voltage is applied or have voltage applied to it when it
is removed.

4.15.5.2 Order data

Model number Short description Figure

Digital output modules
X20DO2623 X20 digital output module, 2 outputs, 100-240 VAC, 1 A, source,
240 V keyed, 3-wire connections
Required accessories
Bus modules
X20BM12 Bus module, 240 VAC keyed, internal I/O supply continuous
Terminal blocks
X20TB32 X20 terminal block, 12-pin, 240 VAC keyed

Table 343: X20DO2623 - Order data

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4.15.5.3 Technical data

Product ID X20DO2623
Brief description
I/O module 2 digital SSR outputs 100 - 240 VAC, 3-wire connections
General information
B&R ID code 0x267B
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software status
Outputs Yes, with status LED
Power consumption
Bus 0.35 W
Internal I/O -
External I/O 0.38 W
Additional power dissipation caused by the actua- +3.0
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital outputs
Design SSR
Wiring L switching
Nominal voltage 100 to 240 VAC
Rated frequency 47 to 63 Hz
Nominal output current 1.0 A
Total nominal current 1.0 A
Surge current 40 A (20 ms), 10 A (1 s)
Connection type 3-wire connections
Zero crossover switches Yes
Leakage current Max. 10 mA at 240 V
Residual voltage (on-state voltage) 1.5 V
Switching delay
At 50 Hz
0 -> 1 ≤ 11 ms
1 -> 0 ≤ 11 ms
At 60 Hz
0 -> 1 ≤ 9.3 ms
1 -> 0 ≤ 9.3 ms
Isolation voltage between channel and bus Tested at 2500 VAC
Voltage monitoring L - N No
Overvoltage protection between L and N Yes
Output voltage
Minimum 80 VAC
Maximum 264 VAC
Protective circuit
External Generally a varistor or fuse
Internal Snubber circuit (RC element)
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0,5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing

Table 344: X20DO2623 - Technical data

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Product ID X20DO2623
Mechanical characteristics
Note Order 1x X20TB32 terminal block separately
Order 1x X20BM12 bus module separately
Spacing 12.5 +0.2 mm

Table 344: X20DO2623 - Technical data

1) Number of outputs x residual voltage (on-state voltage) x nominal output current (A calculation example can be found on the B&R website in the download
area for the module.)

4.15.5.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
On Error or reset status
Single flash Zero cross-over signal has dropped out
e+r Red on / Green single flash Invalid firmware
1-2 Orange Control status of the corresponding digital output

Table 345: Status LEDs

4.15.5.5 Pinout

r e
X20 DO 2623

1 2

DO 1 DO 2

L L

N N

L L

N N

Figure 323: Pinout

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4.15.5.6 Connection example

DO

L L

N N

Actuator Actuator

L L

N N

+24 VDC +24 VDC

GND GND

Figure 324: Connection example

4.15.5.7 Output circuit diagram

SSR
Output x
Output status
zc

I/O status
(LED orange) electrical
separation

L
Zero External
power supply
N

Figure 325: Output circuit diagram

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4.15.5.8 Integrated full-wave control

Full-wave control is used to control power for electrical power consumers that are operated with AC voltage. Tem-
perature control is a typical application
Unlike phase-angle control, the sine wave oscillation form of the mains voltage is not changed during full-wave
control. This significantly reduces system perturbation.
The output voltage (channel) is switched on and off at a certain ratio. This switches the multi-cycle packets. A
multi-cycle packet consists of a number of complete sine waves throughout a cycle. The relationship between
the power-on duration and the cycle duration results in the desired effect of reduced power consumption by the
connected power consumer.
With the full-wave control that is integrated in the module, a maximum of 24 full waves can be provided on the
outputs per cycle. Control takes place in 4% steps.
Settings Full waves
SW% % 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0 0
4 ●
8 ● ●
12 ● ● ●
16 ● ● ● ●
20 ● ● ● ● ●
24 25 ● ● ● ● ● ●
28 ● ● ● ● ● ● ●
32 ● ● ● ● ● ● ● ●
36 ● ● ● ● ● ● ● ● ●
40 ● ● ● ● ● ● ● ● ● ●
44 ● ● ● ● ● ● ● ● ● ● ●
48 50 ● ● ● ● ● ● ● ● ● ● ● ●
52 ● ● ● ● ● ● ● ● ● ● ● ● ●
56 ● ● ● ● ● ● ● ● ● ● ● ● ● ●
60 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
64 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
68 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
72 75 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
76 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
80 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
84 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
88 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
92 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
96 100 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●

Table 346: - Full-wave control in 4% steps

Example of full-wave control (8%):

UChannel

1 cycle
(24 full waves)

Figure 326: Example of full-wave control (8%)

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4.15.5.9 Register description

4.15.5.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
DigitalOutput02 Bit 1
4 1 AnalogOutput01 USINT ●
6 2 AnalogOutput02 USINT ●
12 3 ShiftOutput011) USINT ●
14 4 ShiftOutput021) USINT ●
28 - Output configuration 1 - 2 ConfigOutput01 USINT ●
30 1 StatusInput01 USINT ●
ZeroCrossingInput Bit 0
ZeroCrossingStatus Bit 4

1) Firmware version 816 and up.

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.5.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
4 0 AnalogOutput01 USINT ●
6 2 AnalogOutput02 USINT ●
12 - ShiftOutput012) USINT ●
14 - ShiftOutput022) USINT ●
30 0 Zero crossing status USINT ●
ZeroCrossingInput Bit 0
ZeroCrossingStatus Bit 4

1) The offset specifies where the register is within the CAN object.
2) Firmware version 816 and up.

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4.15.5.9.3 Digital outputs

The output status is transferred to the control switch asynchronously to the connected network. The outputs switch
on when the voltage crosses zero and switch off when the current crosses zero.

4.15.5.9.3.1 Switching state of digital outputs 1 to 2

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput02
This register is used to store the switching state of digital outputs 1 to 2.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 3 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
1 DigitalOutput02 0 Digital output 02 reset
1 Digital output 02 set

Information:
The states in this register are only applied when the channels are set to DIGITAL in "Setting the output
configuration ".
When using the setting "packed outputs" ALL channels must be set to DIGITAL. Mixed operation is
not possible.

4.15.5.9.4 Analog outputs

The output value is transferred to the control circuit in sync with the connected power mains according to the
firing pattern table (see "Integrated full-wave control"). The analog value is output with a resolution of ~4% over a
duration of 24 complete waves. Values > 96% result in full control. Changes to the output value within an interval
are applied after the next zero crossover.

4.15.5.9.4.1 Setting the output value from the firing pattern table

Name:
AnalogOutput01 to AnalogOutput02
These registers are used to set the output value from the firing pattern table.
Values between 0 and 100 correspond to the output value for the respective channel in percent. Values above
100 correspond to 100%.
Data type Value
USINT 0 to 100

Information:
The states in these registers are only applied when the channels are set to ANALOG in Setting the
output configuration .

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4.15.5.9.4.2 Setting the output configuration

Name:
Output configuration 1 - 2 ConfigOutput01
Each channel can be configured for either "digital" or "analog" operation in this register. The corresponding
DigitalOutput or AnalogOutput registers must be written depending on the setting.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Digital register is used
0 Channel 1
1 Analog register is used
0 Digital register is used
1 Channel 2
1 Analog register is used
2-7 0

4.15.5.9.4.3 Shift switching pattern

Name:
ShiftOutput01 to ShiftOutput02
To prevent load peaks due to simultaneous switching of outputs, this register can be used to shift the switching
pattern by a number of full waves. Due to the hardware used, it is not possible to shift by less than a full wave.
Values higher than 23 are limited to 23.
Data type Value Information
USINT 0 No shift
1 to 23 Size of the shift in number of full waves

Example
Set 0 on Channel 1 and 1 on Channel 2. With the same control value (see "Integrated full-wave control") this delays
the switching pattern of Channel 2 by one full wave.

4.15.5.9.5 Zero crossing status

Name:
ZeroCrossingInput
ZeroCrossingStatus
StatusInput01
Zero crossing detection uses a fixed filter time of 1 ms and a scanning frequency of 10 kHz. When a missing or too
short period is detected, control is switched off until at least 2 periods are detected correctly, and the status flag
is set accordingly. Control is offset by 2 ms from the negative half-wave until the next zero crossover is detected
correctly or another error occurs. This is normally at least one complete wave.
Monitoring is activated at the first zero crossover after being switched on.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits should
be set up individually as data points in the AS I/O mapping ("ZeroCrossingInput" through "ZeroCrossingStatus") or
whether this register should be displayed as an individual USINT data point ("StatusInput01").
Data type Value Information
USINT 0 to 17 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 ZeroCrossingInput1) 0 Signal during the negative half-wave
1 Signal during the positive half-wave
1-3 0
4 ZeroCrossingStatus 0 No error
1 Zero crossover failed
5-7 0

1) Value is valid if no error has occurred (ZeroCrossingStatus= 0)

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4.15.5.9.6 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Digital mode 100 μs
Digital and analog mode 150 μs

4.15.5.9.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Digital mode 100 μs
Digital and analog mode 150 μs

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4.15.6 X20DO2633

4.15.6.1 General information

The module is a digital output module with phase-angle control that is equipped with 2 Triac outputs using 3-line
connections. The supply (L and N) is fed directly to the module.
• 2 digital outputs
• Outputs with integrated snubber circuit
• Outputs with 12 to 240 VAC
• L switching
• Zero-crossing detection
• Phase-angle control
• Open-circuit detection for each channel
• Negative half-waves can be switched off
• 50 Hz or 60 Hz
• 3-wire connections
• 240 V coding
• OSP mode
• Frequency mode

Danger!
Risk of electric shock!
The terminal block must only be allowed to conduct voltage when it is inserted. It must not under any
circumstances be removed or inserted when voltage is applied or have voltage applied to it when it
is removed.

4.15.6.2 Order data

Model number Short description Figure

Digital output modules
X20DO2633 X20 digital output module, 2 triac outputs, 12 to 240 VAC, 2 A,
L switching, phase angle control, 240 V keyed
Required accessories
Bus modules
X20BM32 X20 bus module for double-width modules, 240 VAC keyed, in-
ternal I/O supply continuous
Terminal blocks
X20TB32 X20 terminal block, 12-pin, 240 VAC keyed

Table 347: X20DO2633 - Order data

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4.15.6.3 Technical data

Product ID X20DO2633
Brief description
I/O module 2 digital outputs 12-240 VAC for 3-wire connections
General information
B&R ID code 0xAC39
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, using status LED and software
Power consumption
Bus 0.6 W
Internal I/O -
External I/O -
Additional power dissipation caused by the actua- +6 W
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital outputs
Design Triac
Wiring L switching
Nominal voltage 12 to 240 VAC
Rated frequency 47 to 63 Hz
Nominal output current 2.0 A
Total nominal current 4.0 A
Maximum current
Output current 2.5 A
Summation current 5.0 A
Connection type 3-wire connections
Zero-crossing detection Yes
Minimum holding current IH 15 mA
Leakage current 50 Hz: Max. 2.0 mA at 240 V
60 Hz: Max. 2.4 mA at 240 V

Residual voltage (on-state voltage) 1.5 V

Phase-angle control
Range 5 to 95%
Resolution 1%
Accuracy (60 to 240 VAC) <100 μs
Voltage monitoring L - N Yes
Additional functions Open line detection
Overvoltage protection between L and N Yes, Varistor
Output voltage
Minimum 10 VAC
Maximum 253 VAC
Isolation voltage
Terminal block - Bus Tested at 2300 VAC (Rev. <E0 1500 VAC)
Terminal block - 24 V Tested at 2300 VAC (Rev. <E0 2000 VAC)
Terminal block - PE Tested at 2300 VAC (Rev. <E0 1500 VAC)
Protective circuit
External See section "External fuses"
Internal Snubber circuit (RC element) and varistor
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20

Table 348: X20DO2633 - Technical data

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Product ID X20DO2633
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB32 terminal block separately
Order 1x X20BM32 bus module separately
Spacing 25 +0.2 mm

Table 348: X20DO2633 - Technical data

1) Number of outputs x residual voltage (on-state voltage) x nominal output current (A calculation example can be found on the B&R website in the download
area for the module.)

4.15.6.4 Status LEDs

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off Module supply not connected
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
Flickering (ap- Module is in OSP state
prox. 10 Hz)
e Red Off Module supply not connected or everything OK
On Error or reset status
Single flash Zero cross-over signal has dropped out
e+r Red on / Green single flash Invalid firmware
1-2 Orange Control status of the corresponding digital output

4.15.6.5 Pinout

The following points must be taken into consideration when wiring the module:
• For thermal reasons, wires with a cross-section ≥1.5 mm² must be used to wire the module.
• The neutral return lines for the outputs must be wired to the terminal block separately for each channel
and must not be bypassed in the field.
• A line filter must be used for the 240 V supply that provides ≥40 dB attenuation at 150 kHz and works
up to 5 MHz.

r e
X20 DO 2633

1 2

DO 1 DO 2

L L

N N

L L

N N

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4.15.6.6 Connection example

2-wire connections

DO

Actuator Actuator

T 10 A
L L

N N

+24 VDC +24 VDC

GND GND

3-wire connections

DO

L L

N N

Actuator Actuator

T 10 A
L L

N N

+24 VDC +24 VDC

GND GND

4.15.6.7 OSP hardware requirements

In order to best use OSP mode, make sure when creating the application that the output module and CPU have
separate power supplies.

4.15.6.8 Output circuit diagram

DO 1
Output status 1
VDR

N
I/O status
(LED orange)

DO 2
Output status 2
VDR

N
I/O status
(LED orange)

Null Zero cross

N
detection
External
VDR
Power supply
L

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4.15.6.9 External fuses

The following protective circuit must be used for safe operation:

Protective circuit Value
For the supply lines Fuse T 10 A
For the outputs Fuse Melting integral I2t ≤ 78 A2s when tp = 10 ms
With an inductive load Varistor1) e.g. varistor with 275 VRMS at 240 VAC
For the supply voltage Line filter2) Attenuation ≥40 dB at 150 kHz, effective range up to 5 MHz

1) See also section 4.15.6.13 "Operation with inductive loads" on page 1096
2) Meeting the limit values specified in the standards EN 61131, EN 55011 and EN 55022 (each Class A) requires installation of a line filter in the 240 V supply
line. Line filters such as the Schaffner FN 2412‐8‐44 can be used.
If periodic ground transients occur on the supply lines (as can occur with upstream inverters), it is necessary to use an asymmetric filter that keeps these
types of changes in potential below a few volts (e.g. "Sinus Plus" from Schaffner) in addition to the symmetric filter.

4.15.6.10 Derating

The derating listed below must be applied for the current:

Legend: Horizontal installation
Vertical installation

2.5

1.875
Output current [A]

0
-25 25 35 50 60
Ambient temperature [°C]

4.15.6.11 Operating principle

The digital output module was designed for phase control of resistive and and inductive loads. The triac outputs
do not have short circuit protection. The integrated open-circuit detection makes it possible to recognize defects
on the load or the cabling (see 4.15.6.12 "Open line detection" on page 1095).
The module is equipped with internal zero-crossing detection. Zero-crossing detection is the basis for a software
PLL that generates 200 times the zero-crossing frequency. The output signal of the PLL is the base timer for the
PWM outputs in both digital and analog mode.
Upon detection of lost periods or periods that are too short, control to the outputs is cut until the PLL is tuned
correctly. The tuning procedure can take several seconds. In addition, the "ZeroCrossingStatus" bit is set and the
error LED enabled (valid frequency range for the supply is 45 to 65 Hz).

Information:
The jitter of the output signals generated by the PLL and communication can reach 0.5%.

4.15.6.12 Open line detection

The module is equipped with open-circuit detection. Note that open-circuit detection only works when the output
is enabled. An open-circuit will not be detected if the output is turned off.
In addition, open-circuit detection is restricted or doesn't work at all for inductive loads. This depends on the induc-
tance of the load and should be determined beforehand, if necessary.

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4.15.6.13 Operation with inductive loads

As inherent to its functional principal, the triac output is cleared when the current crosses zero. Because zero
crossing for current is delayed with inductive loads, it is possible that the triac will be fired again even though it is
not completely cleared at higher output values (between 50 and 100% depending on the inductance of the load).
In this case, a full-wave is output. This causes the available control range (0 to 95%) to be changed.
For open line detection (LowCurrentStatus), a pause in control is required where the triac is not permitted to be
fired. The full wave that is created with inductive loads causes open line detection to be triggered even though
the load on the output is sufficient.
This behavior can be used to detect the full wave and properly adjust the control range (Example: If open line
detection is triggered at a control value of 70%, that means that 0-70% corresponds to 0-100% output).

Switch-off delay caused by

Inductive load

Zero crossing: Voltage

Zero crossing: Current

Input voltage
Output voltage
Output current
Internal firing signal for the triac

CfO_SwitchOffValue in %

With inductive loads, a suitable varistor must be provided between the output DO x and the phase L (e.g. a varistor
with 275 VRMS at 240 VAC).

DO
Actuator

VDR

L L

N N

+24 VDC +24 VDC

GND GND

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4.15.6.14 Register description

4.15.6.14.1 Function model 0 - Standard and Function model 2 - Frequency mode

The only difference between function model 2 and function model 0 is the possibility of generating half-wave pat-
terns in various frequencies. Register 18 "CfO_Frequency" is an additional register for this.
Register Name Data type Read Write
Cyclic Non-cyclic Cyclic Non-cyclic
Configuration - General
4 AnalogOutput01 USINT ●
6 AnalogOutput02 USINT ●
18 CfO-Frequency UINT ●
20 CfO_SwitchOffValue1 USINT ●
22 CfO_SwitchOffValue2 USINT ●
28 CfO_OutputConfig USINT ●
29 CfO_OutputTolerance USINT ●
Communication
2 DigitalOutput USINT ●
DigitalOutput01 Bit 0
DigitalOutput02 Bit 2
30 StatusInput01 USINT ●
LowCurrentStatus1 Bit 0
LowCurrentStatus2 Bit 1
ZeroCrossingInput Bit 4
ZeroCrossingStatus Bit 7

4.15.6.14.2 Function model 1 - OSP

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Configuration - General
4 AnalogOutput01 USINT ●
6 AnalogOutput02 USINT ●
20 CfO_SwitchOffValue1 USINT ●
22 CfO_SwitchOffValue2 USINT ●
28 CfO_OutputConfig USINT ●
29 CfO_OutputTolerance USINT ●
Configuration - OSP
34 Activating the OSP output in the module USINT ●
OSPValid Bit 0
32 CfgOSPMode USINT ●
36 CfgOSPValue USINT ●
38 CfgOSPValue01 USINT ●
40 CfgOSPValue02 USINT ●
Communication
2 Switching state of digital outputs 1 to 2 USINT ●
DigitalOutput01 Bit 0
DigitalOutput02 Bit 1
30 Status of the outputs USINT ●
LowCurrentStatus1 Bit 0
LowCurrentStatus2 Bit 1
ZeroCrossingInput Bit 4
ZeroCrossingStatus Bit 7

4.15.6.14.3 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Configuration - General
4 0 AnalogOutput01 USINT ●
6 2 AnalogOutput02 USINT ●
20 - CfO_SwitchOffValue1 USINT ●
22 - CfO_SwitchOffValue2 USINT ●
28 - CfO_OutputConfig USINT ●
29 - CfO_OutputTolerance USINT ●
Communication
30 0 Status of the outputs USINT ●
LowCurrentStatus1 Bit 0
LowCurrentStatus2 Bit 1
ZeroCrossingInput Bit 4
ZeroCrossingStatus Bit 7

1) The offset specifies the position of the register within the CAN object.

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4.15.6.14.4 General information

The digital output module was designed for phase control of resistive and inductive loads. The triac outputs do
not have short circuit protection, but have open line detection that can be used to find defects in the consumer
or the wiring.
The module is equipped with internal zero-crossing detection. Zero crossing detection is the basis for a software
PLL that generates 200 times the zero crossing frequency. The output signal of the PLL is the base timer for the
2 PWM outputs in both digital and analog mode.
Upon detection of lost periods or periods that are too short, control of the outputs is cut until the PLL is tuned
correctly (can take several seconds). In addition, the "ZeroCrossingStatus" bit is set and the Error LED is enabled
(valid frequency range for the supply is 45 to 65 Hz).

Information:
The jitter of the output signals generated by the PLL and communication can reach 0.5%.

4.15.6.14.5 Digital outputs

The output state of the outputs defined as digital is transferred to the output ports of the control switch in sync with
the connected power mains. The switch-on state is applied when the voltage crosses zero on the positive half-
wave and the switch-off state at the zero crossing for current in each half wave.

4.15.6.14.5.1 Switching state of digital outputs 1 to 2

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput02
This register is used to store the switching state of digital outputs 1 to 2.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 3 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
1 DigitalOutput02 0 Digital output 02 reset
1 Digital output 02 set

Information:
The states in these registers are only applied when the channels are set to DIGITAL in "Configuration
of the output channels".
When using the setting "packed outputs" ALL channels must be set to DIGITAL. Mixed operation is
not possible.

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4.15.6.14.6 Analog outputs

The output value of the outputs defined as analog outputs (unit percent) is switched through to the control ports in
sync with power mains. The analog value is output to the TRIAC control port in the range between (output value
> SwitchOffValue) and (output value <= 95%) with a resolution of 1%.
A short triac switch-on delay is required for open line detection. Therefore even with output values >= 96%, there
is a a small pause in control.
Changes to the output value are applied at the next positive half-wave
Triac switch-on delay
for open line detection
U

1/f

4.15.6.14.6.1 Commutation angle for analog outputs 1 - 2

Name:
AnalogOutput01 to AnalogOutput02
These registers are used to set the commutation angle for phase angle control.
Values between 0 and 100 correspond to the output value for the respective channel in percent. Values above
100 correspond to 100%.
Data type Value
USINT 0 to 100

Information:
The commutation angle for phase angle control set in these registers are only applied when the chan-
nels are set to ANALOG in "Configuration of the output channels".

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4.15.6.14.7 Output configuration

4.15.6.14.7.1 Configuring the half-wave pattern

Name:
CfO_Frequency
This register can only be used in function model 2 - Frequency mode and makes it possible to configure the output
of half-wave patterns in various frequencies. The commutation angle of the outputs is not affected by this. The
following frequency patterns can be configured:
• 100 half-waves

100 half-waves

• 50 half-waves

50 half-waves

• 33 half-waves

33 half-waves

• 25 half-waves

25 half-waves

With multichannel operation, the second channels should be operated with delayed half-waves in order to ensure
that the load is placed evenly on the module.
Data type Value
UINT See bit structure.

Bit structure:
Bit Description Value Information
0-3 Channel 1 0000 100 half-waves/second
0001 50 half-waves/second
0010 25 half-waves/second
0011 33 half-waves/second
0101 50 half-waves/second delayed by 1 half-wave
0110 25 half-waves/second delayed by 2 half-waves
0111 33 half-waves/second delayed by 1 half-wave
4-7 Channel 2 0000 to 0111 See channel 1
8 - 15 Reserved -

Information:
This function is available beginning with firmware version 940. This can be included beginning with
hardware variant 8.

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4.15.6.14.7.2 Setting the switch-off time

Name:
Cfo_SwitchOffValue1 and Cfo_SwitchOffValue2
This register defines how far in front of the zero cross-over the internal control signal for the TRIAC is switched off.
Increasing this value may be necessary in order to prevent unwanted firing of the TRIAC in the event of a slight
disturbance in the mains frequency.
With smaller loads, it is important to ensure that this switch off value is not set to large (too early) to prevent
switching off prematurely.
The triac can of course only be fired before the set switch-off time.
"SwitchOffValue" in the AS I/O configuration.

1/f

Triac
Control signal

Switch-off value
5 to 50%

Data type Value Description

USINT 5 to 50 Switch-off time in %

4.15.6.14.7.3 Configuration of the output channels

Name:
Cfo_OutputConfig
The configuration of the output channels are stored in this register.
"Output type digital/analog" and "Output type full/half wave" in the AS I/O configuration
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Channel 1: Digital / Analog output 0 Output channel 1 is defined as a digital output. The output status
is defined using bit 0 in the DigitalOutput 1 - 2 register.
1 Output channel 1 is defined as an analog output. The output
status is defined using the AnalogOutput01 register.
1 Channel 2: Digital / Analog output 0 Output channel 2 is defined as a digital output. The output status
is defined using bit 0 in the DigitalOutput 1 - 2 register.
1 Output channel 2 is defined as an analog output. The output
status is defined using the AnalogOutput02 register.
2-3 Reserved -
4 Channel 1: Full-wave / half-wave control1) 0 Full-wave control on output channel 1
1 Negative half-wave on output channel 1 is suppressed.
5 Channel 2: Full-wave / half-wave control1) 0 Full-wave control on output channel 2
1 Negative half-wave on output channel 2 is suppressed.
6-7 Reserved -

1) Not available in function model 2 - Frequency mode.

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4.15.6.14.7.4 Switching behavior for zero-crossing errors

Name:
CfO_OutputTolerance
This register can be used to set the switching behavior of the trigger. After the number of zero-crossing errors
configured in Bit 0 to 4, the output is switched off for at least 3 periods. This is followed by synchronization with
the zero signal according to Bit 7.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-4 Trigger for Resync 0 to 30 Number of zero-crossover errors
5-6 Reserved -
7 Fast settling 0 Fast synchronization
1 PLL synchronization

Fast synchronization
With this option, the trigger point is closed-loop controlled after each individual zero-crossover and input jitter.
• Advantage: Increased tolerance and faster response to deviations in mains frequency
• Disadvantage: Increased switch-on jitter for firing signal by zero cross signal ±100 µSec
PLL synchronization
With this option the intervals between zero cross-overs are measured and the PLL frequency is updated accord-
ingly.
• Advantage: Jitter-free firing signal
• Disadvantage: When the output is switched off, additional measurement phases are required before it can
be switched back on.

Information:
This function is available starting with Firmware version 928. This can be installed with hardware ver-
sion 8 and hardware revision B4 or higher.

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4.15.6.14.8 Status of the outputs

Name:
LowCurrentStatus1 through LowCurrentStatus2
ZeroCrossingInput
ZeroCrossingStatus
StatusInput01
The operating status of the outputs is mapped in this register.
In order to do determine the "LowCurrentStatus", the system checks if there is a neutral connection from the output
via the consumer shortly before each triac firing.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits should
be set up individually as data points in the AS I/O mapping ("LowCurrentStatus1" through "ZeroCrossingStatus")
or whether this register should be displayed as an individual USINT data point ("StatusInput01").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 LowCurrentStatus1 0 Current flow on activated output 1
1 No current flow on activated output 1
1 LowCurrentStatus2 0 Current flow on activated output 2
1 No current flow on activated output 2
2-3 Reserved -
4 ZeroCrossingInput 0 Zero cross signal during the negative half-wave
1 Zero cross signal during the positive half-wave
5-6 Reserved -
7 ZeroCrossingStatus 0 Zero cross signal OK
1 Zero cross signal has dropped out

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4.15.6.14.9 "OSP" function model

In the "OSP" function model (Operator Set Predefined), the user defines an analog value or digital pattern. This
OSP value is output as soon as communication between the module and master is interrupted.
Functionality
The user can choose between two OSP modes:
• Retain last valid value
• Replace with static value
In the first case, the module retains the last value as validly recognized output state.
When selecting the mode, "Replace with static value" a plausible output value must be entered in the corresponding
value register. If an OSP event occurs, this value will be output instead of the value currently requested by the task.

4.15.6.14.9.1 Activating the OSP output in the module

Name:
OSPValid
This data point offers the possibility to start module output and request OSP operation during running operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 OSPValid 0 Request OSP operation (after initial start or module in Standby)
1 Request normal operation
1-7 Reserved 0

There is one OSPValid bit on the module, which is managed by the user task. It must be set when the enabled
channels are started. As long as the OSPValid bit remains set in the module, the module behaves the same as
the "Standard" function model.
If an OSP event occurs (e.g. communication between the module and master CPU interrupted) then the OSPValid
bit will be reset on the module. The module enters OSP mode and the output occurs in the "OSPMode" register
according to the configuration.
The following applies:
The OSP replacement value remains even after the communication channel has recovered. OSP mode
is only exited when a set OSPValid bit is transferred.
When the master CPU is restarted, the OSPValid bit is re-initialized on the master CPU. It must once
more be set by the application and transferred via the bus.
When temporary communication errors occur between the module and master CPU (e.g. due to EMC),
a few bus cycles will pass without refreshing the cyclic registers. The OSPValid bit is reset internally in
the module - the bit in the CPU however remains set. Upon the next successful transfer, the OSPValid
bit in the module is set again and the module returns to normal operation.
The ModulOK bit can be evaluated if the task in the master CPU needs to know which output mode the module
is currently in.

Warning!
If the OSPValid bit is reset to "0" on the module, then the output state no longer depends on the
responsible task in the master CPU. However, output still occurs according to the configuration of the
OSP replacement value.

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4.15.6.14.9.2 Setting the OSP mode

Name:
CfgOSPMode
This register essentially controls a channel's behavior when OSP is being used.
Data type Value Description
USINT 0 Replace with static value
1 Retain last valid value

4.15.6.14.9.3 Define the OSP digital output value

Name:
CfgOSPValue
This register contains the digital output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 0 or 1 OSP output value for channel DigitalOutput00
... ...
x 0 or 1 OSP output value for channel DigitalOutput0x

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.15.6.14.9.4 Define the OSP analog output value

Name:
CfgOSPValue01 to CfgOSPValue02
This register contains the analog output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
USINT 0 to 100

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.15.6.14.10 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
All channels 150 μs

4.15.6.14.11 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
All channels 150 μs

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X20 system modules • Digital output modules • X20DO2649

4.15.7 X20DO2649

4.15.7.1 General information

The module has 2 relay outputs.

• 2 digital outputs
• Relay module for 230 VAC / 30 VDC
• 2 change over contacts
• Single-channel isolated outputs

Danger!
Risk of electric shock!
The terminal block must only be allowed to conduct voltage when it is inserted. It must not under any
circumstances be removed or inserted when voltage is applied or have voltage applied to it when it
is removed.

4.15.7.2 Order data

Model number Short description Figure

Digital output modules
X20DO2649 X20 digital output module, 2 relays, changeover contacts, 230
VAC / 5 A, 24 VDC / 5 A
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 349: X20DO2649 - Order data

4.15.7.3 Technical data

Product ID X20DO2649
Brief description
I/O module 2 digital outputs 30 VDC / 230 VAC, outputs are single-channel isolated
General information
B&R ID code 0x20DA
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, using status LED
Power consumption
Bus 0.45 W
Internal I/O -
Additional power dissipation caused by the actua- +2.5
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital outputs
Design Relay / Changeover contact
Channels are single-channel isolated

Table 350: X20DO2649 - Technical data

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Product ID X20DO2649
Nominal voltage 30 VDC / 230 VAC
Switching voltage Max. 110 VDC / 250 VAC
Rated frequency DC / 45 to 63 Hz
Nominal output current 5.0 A at 30 VDC / 5.0 A at 230 VAC
Total nominal current 10.0 A at 30 VDC / 10.0 A at 230 VAC
Actuator supply External
Starting current Max. 6 A (per channel)
Contact resistance 50 mΩ
Switching delay
0 -> 1 ≤10 ms
1 -> 0 ≤10 ms
Isolation voltage
Contact - Contact Tested at 1000 VAC
Contact - Coil Tested at 4000 VAC
Service life
Electrical 2) Min. 60 x 10³ ops. (NC) at 6 A
Min. 30 x 30³ ops. (NO) at 6 A
Mechanical Min. 10 x 106 ops.
Switching capacity
Minimum 10 mA / 5 VDC
Maximum 180 W / 1500 VA
Protective circuit
Internal None
External
AC RC combination or VDR
DC Inverse diode, RC combination or VDR
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 350: X20DO2649 - Technical data

1) Number of outputs x Contact resistance x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the
module.)
2) With a resistive load. See also section "Electrical service life"

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4.15.7.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
On Error or reset status
e+r Red on / Green single flash Invalid firmware
1-2 Orange Output status of the corresponding digital output

Table 351: Status LEDs

4.15.7.5 Pinout

r e

X20 DO 2649
1
2

NC 1 NC 1

COM 1 COM 1

NO 1 NO 1

NC 2 NC 2

COM 2 COM 2

NO 2 NO 2

Figure 327: Pinout

4.15.7.6 Connection example

DO

230 VAC

+24 VDC +24 VDC

GND GND

Figure 328: Connection example

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 X20 system modules • Digital output modules • X20DO2649

4.15.7.7 Output circuit diagram

NC x

COM x

NO x

Output status

I/O status
LED (orange)

Figure 329: Output circuit diagram

4.15.7.8 Electrical service life

Electrical service life

100

50
250 VAC / 30 VDC resistive (cos ɸ = 1)
Switching operations (x10⁴)

20
250 VAC cos ɸ = 0.7

10
30 VDC τ = 7 ms

250 VAC cos ɸ = 0.4

5
30 VDC τ = 15 ms

1
0 2 4 6 8 10 12 14

Switching current [A]

Figure 330: Electrical service life

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4.15.7.9 Register description

4.15.7.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
DigitalOutput02 Bit 1

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.7.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 2 USINT ●
DigitalOutput01 Bit 0
DigitalOutput02 Bit 1

1) The offset specifies where the register is within the CAN object.

4.15.7.9.3 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.7.9.3.1 Switching state of digital outputs 1 to 2

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput02
This register is used to store the switching state of digital outputs 1 to 2.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 3 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
1 DigitalOutput02 0 Digital output 02 reset
1 Digital output 02 set

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4.15.7.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.7.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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4.15.8 X20DO4321

4.15.8.1 General information

The module is equipped with 4 outputs for 3-wire connections.

• 4 digital outputs
• Sink connection
• 3-wire connections
• 24 VDC and GND for actuator supply
• Integrated output protection
• OSP mode

4.15.8.2 Order data

Model number Short description Figure

Digital output modules
X20DO4321 X20 digital output module, 4 outputs, 24 VDC, 0.5 A, sink, 3-wire
connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 352: X20DO4321 - Order data

4.15.8.3 Technical data

Product ID X20DO4321
Brief description
I/O module 4 digital outputs 24 VDC for 3-wire connections
General information
B&R ID code 0x22B4
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, with status LED and software status (output error status)
Power consumption
Bus 0.16 W
Internal I/O 0.49 W
Additional power dissipation caused by the actua- +0.12
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital outputs
Design FET negative switching
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.5 A
Total nominal current 2.0 A
Connection type 3-wire connections
Output circuit Sink
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")

Table 353: X20DO4321 - Technical data

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Product ID X20DO4321
Actuator supply 0.5 A in total for output-independent actuator supply
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 75 µA
RDS(on) 120 mΩ
Peak short circuit current <7 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay
0 -> 1 <300 µs
1 -> 0 <300 µs
Switching frequency
Resistive load Max. 500 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Typ. 50 VDC
Isolation voltage between channel and bus 500 Veff
Actuator supply
Voltage Module supply minus voltage drop for short circuit protection
Voltage drop for short circuit protection at 500 mA Max. 2 V
Short circuit protection Yes
Power consumption
Actuator supply Max. 12.0 W 2)
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 353: X20DO4321 - Technical data

1) Number of outputs x RDS(on) x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the module.)
2) The power consumption of the sensors connected to the module may not exceed 12 W.

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4.15.8.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
Flickering (ap- Module is in OSP state
prox. 10 Hz)
e Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
e+r Red on / Green single flash Invalid firmware
1-4 Orange Output status of the corresponding digital output

Table 354: Status LEDs

4.15.8.5 Pinout

r e

X20 DO 4321
1 2
3 4

DO 1 DO 2

+24 VDC +24 VDC

GND GND

DO 3 DO 4

+24 VDC +24 VDC

GND GND

Figure 331: Pinout

4.15.8.6 Connection example

DO
Actuator 1

Actuator 2
Actuator 4
Actuator 3

+24 VDC +24 VDC

GND GND

Figure 332: Connection example

4.15.8.7 OSP hardware requirements

In order to best use OSP mode, make sure when creating the application that the output module and CPU have
separate power supplies.

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4.15.8.8 Output circuit diagram

24 V

I/O status
LED (orange)
Low-side
Output status Output x
Logic

VDR
GND
Output
monitoring GND

24 V

GND 24 V

PTC
GND

GND

Figure 333: Output circuit diagram

4.15.8.9 Switching inductive loads

Environmental temperature: 60°C, all outputs with the same load

100 H 10 H
1000
Switching voltage:

28.8 V
1H
24.0 V

Coil resistance Coil inductance

[Ω] 100 mH

100

10 mH
50
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.8.10 Register description

4.15.8.10.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 1 StatusInput01 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput04 Bit 3

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.8.10.2 Function model 1 - OSP

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 4 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 1 Status of digital outputs 1 to 4 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput04 Bit 3
34 1 Activating the OSP output in the module USINT ●
OSPValid Bit 0
32 - CfgOSPMode USINT ●
36 - CfgOSPValue USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.8.10.3 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 4 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 - Status of digital outputs 1 to 4 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput04 Bit 3

1) The offset specifies where the register is within the CAN object.

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4.15.8.10.4 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.8.10.4.1 Switching state of digital outputs 1 to 4

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput04
The switching state of digital outputs 1 to 4 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 15 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
3 DigitalOutput04 0 Digital output 04 reset
1 Digital output 04 set

4.15.8.10.5 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

4.15.8.10.5.1 Status of digital outputs 1 to 4

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput04
The status of digital outputs 1 to 4 is mapped in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through
"StatusDigitalOutput0x") or whether this register should be displayed as an individual USINT data point
("StatusInput01").
Data type Value Information
USINT 0 to 15 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Value Information
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
... ...
3 StatusDigitalOutput04 0 Channel 04: No error
1 Channel 04: Short circuit or overload

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4.15.8.10.6 "OSP" function model

In the "OSP" function model (Operator Set Predefined), the user defines an analog value or digital pattern. This
OSP value is output as soon as communication between the module and master is interrupted.
Functionality
The user can choose between two OSP modes:
• Retain last valid value
• Replace with static value
In the first case, the module retains the last value as validly recognized output state.
When selecting the mode, "Replace with static value" a plausible output value must be entered in the corresponding
value register. If an OSP event occurs, this value will be output instead of the value currently requested by the task.

4.15.8.10.6.1 Activating the OSP output in the module

Name:
OSPValid
This data point offers the possibility to start module output and request OSP operation during running operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Request OSP operation (after initial start or module in Standby)
0 OSPValid
1 Request normal operation
1-7 0 Reserved

There is one OSPValid bit on the module, which is managed by the user task. It must be set when the enabled
channels are started. As long as the OSPValid bit remains set in the module, the module behaves the same as
the "Standard" function model.
If an OSP event occurs (e.g. communication between the module and master CPU interrupted) then the OSPValid
bit will be reset on the module. The module enters OSP mode and the output occurs in the "OSPMode" register
according to the configuration.
The following applies:
The OSP replacement value remains even after the communication channel has recovered. OSP mode
is only exited when a set OSPValid bit is transferred.
When the master CPU is restarted, the OSPValid bit is re-initialized on the master CPU. It must once
more be set by the application and transferred via the bus.
When temporary communication errors occur between the module and master CPU (e.g. due to EMC),
a few bus cycles will pass without refreshing the cyclic registers. The OSPValid bit is reset internally in
the module - the bit in the CPU however remains set. Upon the next successful transfer, the OSPValid
bit in the module is set again and the module returns to normal operation.
The ModulOK bit can be evaluated if the task in the master CPU needs to know which output mode the module
is currently in.

Warning!
If the OSPValid bit is reset to "0" on the module, then the output state no longer depends on the
responsible task in the master CPU. However, output still occurs according to the configuration of the
OSP replacement value.

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4.15.8.10.6.2 Setting the OSP mode

Name:
CfgOSPMode
This register essentially controls a channel's behavior when OSP is being used.
Data type Value Description
USINT 0 Replace with static value
1 Retain last valid value

4.15.8.10.6.3 Define the OSP digital output value

Name:
CfgOSPValue
This register contains the digital output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 0 or 1 OSP output value for channel DigitalOutput00
... ...
x 0 or 1 OSP output value for channel DigitalOutput0x

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.15.8.10.7 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.8.10.8 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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4.15.9 X20DO4322

4.15.9.1 General information

The module is equipped with 4 outputs for 3-wire connections.

• 4 digital outputs
• Source connection
• 3-wire connections
• 24 VDC and GND for actuator supply
• Integrated output protection
• OSP mode

4.15.9.2 Order data

Model number Short description Figure

Digital output modules
X20DO4322 X20 digital output module, 4 outputs, 24 VDC, 0.5 A, source, 3-
wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 355: X20DO4322 - Order data

4.15.9.3 Technical data

Product ID X20DO4322
Brief description
I/O module 4 digital outputs 24 VDC for 3-wire connections
General information
B&R ID code 0x1B97
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, with status LED and software status (output error status)
Power consumption
Bus 0.16 W
Internal I/O 0.49 W
Additional power dissipation caused by the actua- +0.21
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital outputs
Design FET positive switching
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.5 A
Total nominal current 2.0 A
Connection type 3-wire connections
Output circuit Source

Table 356: X20DO4322 - Technical data

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Product ID X20DO4322
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")
Actuator supply 0.5 A in total for output-independent actuator supply
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 5 µA
RDS(on) 210 mΩ
Max. continuous current 6.0 A
Peak short circuit current <12 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay 2)
0 -> 1 <300 µs
1 -> 0 <300 µs
Switching frequency
Resistive load 2) Max. 500 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Typ. 50 VDC
Isolation voltage between channel and bus 500 Veff
Actuator supply
Voltage Module supply minus voltage drop for short circuit protection
Voltage drop for short circuit protection at 500 mA Max. 2 V
Short circuit protection Yes
Power consumption
Actuator supply Max. 12.0 W 3)
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 356: X20DO4322 - Technical data

1) Number of outputs x RDS(on) x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the module.)
2) At loads ≤ 1 kΩ
3) The power consumption of the sensors connected to the module may not exceed 12 W.

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4.15.9.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
Flickering (ap- Module is in OSP state
prox. 10 Hz)
e Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
e+r Red on / Green single flash Invalid firmware
1-4 Orange Output status of the corresponding digital output

Table 357: Status LEDs

4.15.9.5 Pinout

r e

X20 DO 4322
1 2
3 4

DO 1 DO 2

+24 VDC +24 VDC

GND GND

DO 3 DO 4

+24 VDC +24 VDC

GND GND

Figure 334: Pinout

4.15.9.6 Connection example

DO
Actuator 1

Actuator 2
Actuator 4
Actuator 3

+24 VDC +24 VDC

GND GND

Figure 335: Connection example

Caution!
If the module is operated outside of specifications, the output current can increase above the maximum
permissible nominal current. This applies to individual channels and also to the summation current
for the module.
Therefore sufficient cable cross sections or external safety measures must be used.

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4.15.9.7 OSP hardware requirements

In order to best use OSP mode, make sure when creating the application that the output module and CPU have
separate power supplies.

4.15.9.8 Output circuit diagram

24 V

High-side
Output status
Logic
Output x

GND

I/O status
Output LED (orange) 24 V
PTC
monitoring
24 V

GND
GND

Figure 336: Output circuit diagram

4.15.9.9 Switching inductive loads

Environmental temperature: 60°C, all outputs with the same load

100 H 10 H
1000
Switching voltage:
1H
28.8 V
24.0 V

100 mH
Coil resistance Coil inductance
[Ω]

100
10 mH

50
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.9.10 Register description

4.15.9.10.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 1 StatusInput01 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput04 Bit 3

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.9.10.2 Function model 1 - OSP

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 4 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 1 Status of digital outputs 1 to 4 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput04 Bit 3
34 1 Activating the OSP output in the module USINT ●
OSPValid Bit 0
32 - CfgOSPMode USINT ●
36 - CfgOSPValue USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.9.10.3 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 4 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 - Status of digital outputs 1 to 4 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput04 Bit 3

1) The offset specifies where the register is within the CAN object.

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4.15.9.10.4 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.9.10.4.1 Switching state of digital outputs 1 to 4

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput04
The switching state of digital outputs 1 to 4 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 15 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
3 DigitalOutput04 0 Digital output 04 reset
1 Digital output 04 set

4.15.9.10.5 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

4.15.9.10.5.1 Status of digital outputs 1 to 4

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput04
The status of digital outputs 1 to 4 is mapped in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through
"StatusDigitalOutput0x") or whether this register should be displayed as an individual USINT data point
("StatusInput01").
Data type Value Information
USINT 0 to 15 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Value Information
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
... ...
3 StatusDigitalOutput04 0 Channel 04: No error
1 Channel 04: Short circuit or overload

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4.15.9.10.6 "OSP" function model

In the "OSP" function model (Operator Set Predefined), the user defines an analog value or digital pattern. This
OSP value is output as soon as communication between the module and master is interrupted.
Functionality
The user can choose between two OSP modes:
• Retain last valid value
• Replace with static value
In the first case, the module retains the last value as validly recognized output state.
When selecting the mode, "Replace with static value" a plausible output value must be entered in the corresponding
value register. If an OSP event occurs, this value will be output instead of the value currently requested by the task.

4.15.9.10.6.1 Activating the OSP output in the module

Name:
OSPValid
This data point offers the possibility to start module output and request OSP operation during running operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Request OSP operation (after initial start or module in Standby)
0 OSPValid
1 Request normal operation
1-7 0 Reserved

There is one OSPValid bit on the module, which is managed by the user task. It must be set when the enabled
channels are started. As long as the OSPValid bit remains set in the module, the module behaves the same as
the "Standard" function model.
If an OSP event occurs (e.g. communication between the module and master CPU interrupted) then the OSPValid
bit will be reset on the module. The module enters OSP mode and the output occurs in the "OSPMode" register
according to the configuration.
The following applies:
The OSP replacement value remains even after the communication channel has recovered. OSP mode
is only exited when a set OSPValid bit is transferred.
When the master CPU is restarted, the OSPValid bit is re-initialized on the master CPU. It must once
more be set by the application and transferred via the bus.
When temporary communication errors occur between the module and master CPU (e.g. due to EMC),
a few bus cycles will pass without refreshing the cyclic registers. The OSPValid bit is reset internally in
the module - the bit in the CPU however remains set. Upon the next successful transfer, the OSPValid
bit in the module is set again and the module returns to normal operation.
The ModulOK bit can be evaluated if the task in the master CPU needs to know which output mode the module
is currently in.

Warning!
If the OSPValid bit is reset to "0" on the module, then the output state no longer depends on the
responsible task in the master CPU. However, output still occurs according to the configuration of the
OSP replacement value.

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4.15.9.10.6.2 Setting the OSP mode

Name:
CfgOSPMode
This register essentially controls a channel's behavior when OSP is being used.
Data type Value Description
USINT 0 Replace with static value
1 Retain last valid value

4.15.9.10.6.3 Define the OSP digital output value

Name:
CfgOSPValue
This register contains the digital output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 0 or 1 OSP output value for channel DigitalOutput00
... ...
x 0 or 1 OSP output value for channel DigitalOutput0x

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.15.9.10.7 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.9.10.8 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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X20 system modules • Digital output modules • X20DO4331

4.15.10 X20DO4331

4.15.10.1 General information

The module is equipped with 4 outputs for 3-wire connections. The rated output current is 2 A.
• 4 digital outputs with 2 A
• Sink connection
• 3-wire connections
• 24 VDC and GND for actuator supply
• Integrated output protection
• OSP mode

4.15.10.2 Order data

Model number Short description Figure

Digital output modules
X20DO4331 X20 digital output module, 4 outputs, 24 VDC, 2 A, sink, 3-wire
connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 358: X20DO4331 - Order data

4.15.10.3 Technical data

Product ID X20DO4331
Brief description
I/O module 4 digital outputs 24 VDC for 3-wire connections
General information
B&R ID code 0x22B5
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, with status LED and software status (output error status)
Power consumption
Bus 0.16 W
Internal I/O 0.49 W
Additional power dissipation caused by the actua- +0.56
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital outputs
Design FET negative switching
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 2.0 A
Total nominal current 8.0 A
Connection type 3-wire connections
Output circuit Sink
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")

Table 359: X20DO4331 - Technical data

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 X20 system modules • Digital output modules • X20DO4331
Product ID X20DO4331
Actuator supply 0.5 A in total for output-independent actuator supply
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 75 µA
RDS(on) 35 mΩ
Peak short circuit current <24 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay
0 -> 1 <300 µs
1 -> 0 <500 µs
Switching frequency
Resistive load Max. 500 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Typ. 50 VDC
Isolation voltage between channel and bus 500 Veff
Additional functions To increase the output current, outputs can be switched in parallel
Actuator supply
Voltage Module supply minus voltage drop for short circuit protection
Voltage drop for short circuit protection at 500 mA Max. 2 V
Short circuit protection Yes
Power consumption
Actuator supply Max. 12.0 W 2)
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 359: X20DO4331 - Technical data

1) Number of outputs x RDS(on) x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the module.)
2) The power consumption of the sensors connected to the module may not exceed 12 W.

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4.15.10.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
Flickering (ap- Module is in OSP state
prox. 10 Hz)
e Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
e+r Red on / Green single flash Invalid firmware
1-4 Orange Output status of the corresponding digital output

Table 360: Status LEDs

4.15.10.5 Pinout

r e

X20 DO 4331
1 2
3 4

DO 1 DO 2

+24 VDC +24 VDC

GND GND

DO 3 DO 4

+24 VDC +24 VDC

GND GND

Figure 337: Pinout

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4.15.10.6 Connection example

DO

Actuator 1

Actuator 2
Actuator 4
Actuator 3
+24 VDC +24 VDC
GND GND

Figure 338: Connection example

4.15.10.7 OSP hardware requirements

In order to best use OSP mode, make sure when creating the application that the output module and CPU have
separate power supplies.

4.15.10.8 Output circuit diagram

24 V

I/O status
LED (orange)
Low-side
Output status Output x
Logic

VDR
GND
Output
monitoring GND

24 V

GND 24 V

PTC
GND

GND

Figure 339: Output circuit diagram

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4.15.10.9 Switching inductive loads

Environmental temperature: 40°C, all outputs with the same load.

100 H 10 H
500
Switching voltage:
1H
28.8 V
24.0 V

100 100 mH

Coil resistance Coil inductance

[Ω]

10 mH

10
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Environmental temperature: 60°C, all outputs with the same load.

100 H 10 H 1H
500
Switching voltage:

28.8 V
24.0 V
100 mH

100

Coil resistance Coil inductance

[Ω] 10 mH

10
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.10.10 Operation with 2 A

The outputs of the X20DO4331 can handle up to 2A. To ensure optimal use of the module, it is important to assign
the channels properly, and to keep in mind a potential derating.
The following table provides an overview of the number of fully used channels, the resulting best distribution, and
a potential derating.
Number of channels using 2A Division Derating
1 Any No
2 Possible divisions: No
1, 3
2, 4
3 Possible divisions: No
1, 2, 4
1, 3, 4
4 1-4 All channels

Table 361: Operation with 2 A

2

1.34
Output current [A]

0
-25 35 60

Ambient temperature [°C]

Figure 340: Derating when 4 channels are operated with 2 A

Modules next to the X20DO4331 can have a maximum power consumption of 1.5 W.

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X20 system modules • Digital output modules • X20DO4331

4.15.10.11 Register description

4.15.10.11.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 1 StatusInput01 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput04 Bit 3

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.10.11.2 Function model 1 - OSP

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 4 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 1 Status of digital outputs 1 to 4 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput04 Bit 3
34 1 Activating the OSP output in the module USINT ●
OSPValid Bit 0
32 - CfgOSPMode USINT ●
36 - CfgOSPValue USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.10.11.3 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 4 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 - Status of digital outputs 1 to 4 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput04 Bit 3

1) The offset specifies where the register is within the CAN object.

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4.15.10.11.4 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.10.11.4.1 Switching state of digital outputs 1 to 4

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput04
The switching state of digital outputs 1 to 4 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 15 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
3 DigitalOutput04 0 Digital output 04 reset
1 Digital output 04 set

4.15.10.11.5 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

4.15.10.11.5.1 Status of digital outputs 1 to 4

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput04
The status of digital outputs 1 to 4 is mapped in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through
"StatusDigitalOutput0x") or whether this register should be displayed as an individual USINT data point
("StatusInput01").
Data type Value Information
USINT 0 to 15 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Value Information
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
... ...
3 StatusDigitalOutput04 0 Channel 04: No error
1 Channel 04: Short circuit or overload

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4.15.10.11.6 "OSP" function model

In the "OSP" function model (Operator Set Predefined), the user defines an analog value or digital pattern. This
OSP value is output as soon as communication between the module and master is interrupted.
Functionality
The user can choose between two OSP modes:
• Retain last valid value
• Replace with static value
In the first case, the module retains the last value as validly recognized output state.
When selecting the mode, "Replace with static value" a plausible output value must be entered in the corresponding
value register. If an OSP event occurs, this value will be output instead of the value currently requested by the task.

4.15.10.11.6.1 Activating the OSP output in the module

Name:
OSPValid
This data point offers the possibility to start module output and request OSP operation during running operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Request OSP operation (after initial start or module in Standby)
0 OSPValid
1 Request normal operation
1-7 0 Reserved

There is one OSPValid bit on the module, which is managed by the user task. It must be set when the enabled
channels are started. As long as the OSPValid bit remains set in the module, the module behaves the same as
the "Standard" function model.
If an OSP event occurs (e.g. communication between the module and master CPU interrupted) then the OSPValid
bit will be reset on the module. The module enters OSP mode and the output occurs in the "OSPMode" register
according to the configuration.
The following applies:
The OSP replacement value remains even after the communication channel has recovered. OSP mode
is only exited when a set OSPValid bit is transferred.
When the master CPU is restarted, the OSPValid bit is re-initialized on the master CPU. It must once
more be set by the application and transferred via the bus.
When temporary communication errors occur between the module and master CPU (e.g. due to EMC),
a few bus cycles will pass without refreshing the cyclic registers. The OSPValid bit is reset internally in
the module - the bit in the CPU however remains set. Upon the next successful transfer, the OSPValid
bit in the module is set again and the module returns to normal operation.
The ModulOK bit can be evaluated if the task in the master CPU needs to know which output mode the module
is currently in.

Warning!
If the OSPValid bit is reset to "0" on the module, then the output state no longer depends on the
responsible task in the master CPU. However, output still occurs according to the configuration of the
OSP replacement value.

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4.15.10.11.6.2 Setting the OSP mode

Name:
CfgOSPMode
This register essentially controls a channel's behavior when OSP is being used.
Data type Value Description
USINT 0 Replace with static value
1 Retain last valid value

4.15.10.11.6.3 Define the OSP digital output value

Name:
CfgOSPValue
This register contains the digital output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 0 or 1 OSP output value for channel DigitalOutput00
... ...
x 0 or 1 OSP output value for channel DigitalOutput0x

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.15.10.11.7 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.10.11.8 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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X20 system modules • Digital output modules • X20DO4332

4.15.11 X20DO4332

4.15.11.1 General information

The module is equipped with 4 outputs for 3-wire connections. The rated output current is 2 A.
• 4 digital outputs with 2 A
• Source connection
• 3-wire connections
• 24 VDC and GND for actuator supply
• Integrated output protection
• OSP mode

4.15.11.2 Order data

Model number Short description Figure

Digital output modules
X20DO4332 X20 digital output module, 4 outputs, 24 VDC, 2 A, source, 3-
wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 362: X20DO4332 - Order data

4.15.11.3 Technical data

Product ID X20DO4332
Brief description
I/O module 4 digital outputs 24 VDC for 3-wire connections
General information
B&R ID code 0x1B9C
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, with status LED and software status (output error status)
Power consumption
Bus 0.16 W
Internal I/O 0.49 W
Additional power dissipation caused by the actua- +1.60 (Rev. <H0: +2.24)
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital outputs
Design FET positive switching
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 2.0 A
Total nominal current 8.0 A (Rev. <H0: 4.0 A)
Connection type 3-wire connections
Output circuit Source
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")

Table 363: X20DO4332 - Technical data

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Product ID X20DO4332
Actuator supply 0.5 A in total for output-independent actuator supply
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 5 µA
RDS(on) 100 mΩ (Rev. <H0: 140 mΩ)
Max. continuous current 8.0 A
Peak short circuit current <4 A (Rev. <H0: <12 A)
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay 2)
0 -> 1 <300 µs
1 -> 0 <300 µs
Switching frequency
Resistive load 2) Max. 500 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Typ. 50 VDC
Isolation voltage between channel and bus 500 Veff
Additional functions To increase the output current, outputs can be switched in parallel
Actuator supply
Voltage Module supply minus voltage drop for short circuit protection
Voltage drop for short circuit protection at 500 mA Max. 2 V
Short circuit protection Yes
Power consumption
Actuator supply Max. 12.0 W 3)
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 363: X20DO4332 - Technical data

1) Number of outputs x RDS(on) x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the module.)
2) At loads ≤ 1 kΩ
3) The power consumption of the sensors connected to the module may not exceed 12 W.

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4.15.11.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
Flickering (ap- Module is in OSP state
prox. 10 Hz)
e Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
e+r Red on / Green single flash Invalid firmware
1-4 Orange Output status of the corresponding digital output

Table 364: Status LEDs

4.15.11.5 Pinout

r e

X20 DO 4332
1 2
3 4

DO 1 DO 2

+24 VDC +24 VDC

GND GND

DO 3 DO 4

+24 VDC +24 VDC

GND GND

Figure 341: Pinout

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 X20 system modules • Digital output modules • X20DO4332

4.15.11.6 Connection example

DO

Actuator 1

Actuator 2
Actuator 4
Actuator 3
+24 VDC +24 VDC
GND GND

Figure 342: Connection example

4.15.11.7 OSP hardware requirements

In order to best use OSP mode, make sure when creating the application that the output module and CPU have
separate power supplies.

4.15.11.8 Output circuit diagram

24 V

High-side
Output status
Logic
Output x

GND

I/O status
Output LED (orange) 24 V
PTC
monitoring
24 V

GND
GND

Figure 343: Output circuit diagram

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4.15.11.9 Switching inductive loads (Rev. H0 and higher)

Environmental temperature: 50°C, all outputs with the same load.

100 H 10 H
500
1H
Switching voltage:

28.8 V
24.0 V

100 mH
100
Coil resistance Coil inductance
[Ω]
10 mH

10
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Environmental temperature: 60°C, all outputs with the same load.

100 H 10 H
500 1H
Switching voltage:

28.8 V
24.0 V
100 mH

100
Coil resistance Coil inductance
[Ω]
10 mH

10
0.1 1 10 100
max. Schaltspiele / Sekunde
(with 90% duty cycle)

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.11.10 Operation with 2 A

The outputs of the module can handle up to 2 A. With a total current of 4 A, no more than 2 channels are operable
at full load. Correct channel assignments are important for achieving optimal use of the module.
The following table provides an overview of the number of fully used channels and the resulting best distribution.
Number of channels using 2A Division
1 Any
2 The following channel numbers can be assigned:
1, 3
1, 4
2, 4

Table 365: Operation with 2 A

Information:
This section is only valid up to Rev. H0.

4.15.11.11 Derating

When operated at temperatures above 55°C, the power consumption of the modules to the left and right of this
module must not exceed 1.15 W.
8

6
Total current [A]

0
-25 50 60

Ambient temperature [°C]

Information:
This section is only valid for Rev. H0 and higher.

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4.15.11.12 Register description

4.15.11.12.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 1 StatusInput01 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput04 Bit 3

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.11.12.2 Function model 1 - OSP

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 4 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 1 Status of digital outputs 1 to 4 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput04 Bit 3
34 1 Activating the OSP output in the module USINT ●
OSPValid Bit 0
32 - CfgOSPMode USINT ●
36 - CfgOSPValue USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.11.12.3 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 4 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 - Status of digital outputs 1 to 4 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput04 Bit 3

1) The offset specifies where the register is within the CAN object.

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4.15.11.12.4 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.11.12.4.1 Switching state of digital outputs 1 to 4

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput04
The switching state of digital outputs 1 to 4 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 15 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
3 DigitalOutput04 0 Digital output 04 reset
1 Digital output 04 set

4.15.11.12.5 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

4.15.11.12.5.1 Status of digital outputs 1 to 4

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput04
The status of digital outputs 1 to 4 is mapped in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through
"StatusDigitalOutput0x") or whether this register should be displayed as an individual USINT data point
("StatusInput01").
Data type Value Information
USINT 0 to 15 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Value Information
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
... ...
3 StatusDigitalOutput04 0 Channel 04: No error
1 Channel 04: Short circuit or overload

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4.15.11.12.6 "OSP" function model

In the "OSP" function model (Operator Set Predefined), the user defines an analog value or digital pattern. This
OSP value is output as soon as communication between the module and master is interrupted.
Functionality
The user can choose between two OSP modes:
• Retain last valid value
• Replace with static value
In the first case, the module retains the last value as validly recognized output state.
When selecting the mode, "Replace with static value" a plausible output value must be entered in the corresponding
value register. If an OSP event occurs, this value will be output instead of the value currently requested by the task.

4.15.11.12.6.1 Activating the OSP output in the module

Name:
OSPValid
This data point offers the possibility to start module output and request OSP operation during running operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Request OSP operation (after initial start or module in Standby)
0 OSPValid
1 Request normal operation
1-7 0 Reserved

There is one OSPValid bit on the module, which is managed by the user task. It must be set when the enabled
channels are started. As long as the OSPValid bit remains set in the module, the module behaves the same as
the "Standard" function model.
If an OSP event occurs (e.g. communication between the module and master CPU interrupted) then the OSPValid
bit will be reset on the module. The module enters OSP mode and the output occurs in the "OSPMode" register
according to the configuration.
The following applies:
The OSP replacement value remains even after the communication channel has recovered. OSP mode
is only exited when a set OSPValid bit is transferred.
When the master CPU is restarted, the OSPValid bit is re-initialized on the master CPU. It must once
more be set by the application and transferred via the bus.
When temporary communication errors occur between the module and master CPU (e.g. due to EMC),
a few bus cycles will pass without refreshing the cyclic registers. The OSPValid bit is reset internally in
the module - the bit in the CPU however remains set. Upon the next successful transfer, the OSPValid
bit in the module is set again and the module returns to normal operation.
The ModulOK bit can be evaluated if the task in the master CPU needs to know which output mode the module
is currently in.

Warning!
If the OSPValid bit is reset to "0" on the module, then the output state no longer depends on the
responsible task in the master CPU. However, output still occurs according to the configuration of the
OSP replacement value.

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4.15.11.12.6.2 Setting the OSP mode

Name:
CfgOSPMode
This register essentially controls a channel's behavior when OSP is being used.
Data type Value Description
USINT 0 Replace with static value
1 Retain last valid value

4.15.11.12.6.3 Define the OSP digital output value

Name:
CfgOSPValue
This register contains the digital output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 0 or 1 OSP output value for channel DigitalOutput00
... ...
x 0 or 1 OSP output value for channel DigitalOutput0x

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.15.11.12.7 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.11.12.8 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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4.15.12 X20DO4529

4.15.12.1 General information

The module is equipped with 4 relay outputs.

• 4 digital outputs
• Relay module for 115 VAC
• 4 change over contacts
• Single-channel isolated outputs

Danger!
Risk of electric shock!
The terminal block must only be allowed to conduct voltage when it is inserted. It must not under any
circumstances be removed or inserted when voltage is applied or have voltage applied to it when it
is removed.

4.15.12.2 Order data

Model number Short description Figure

Digital output modules
X20DO4529 X20 digital output module, 4 relays, changeover contacts, 115
VAC / 0.5 A, 24 VDC / 1 A
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 366: X20DO4529 - Order data

4.15.12.3 Technical data

Product ID X20DO4529
Brief description
I/O module 4 digital outputs 30 VDC / 115 VAC, outputs are single-channel isolated
General information
B&R ID code 0x20D9
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, using status LED
Power consumption
Bus 0.8 W
Internal I/O -
Additional power dissipation caused by the actua- +0.3
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital outputs
Design Relay / Changeover contact
Channels are single-channel isolated

Table 367: X20DO4529 - Technical data

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 X20 system modules • Digital output modules • X20DO4529
Product ID X20DO4529
Nominal voltage 30 VDC / 115 VAC
Switching voltage Max. 110 VDC / 125 VAC
Rated frequency DC / 45 to 63 Hz
Nominal output current 1.0 A at 30 VDC / 0.5 A at 115 VAC
Total nominal current 4.0 A at 30 VDC / 2.0 A at 115 VAC
Actuator supply External
Starting current Max. 2 A (per channel)
Contact resistance 75 mΩ at 6 VDC / 1A
Switching delay
0 -> 1 ≤4 ms
1 -> 0 ≤4 ms
Isolation voltage
Contact - Contact Tested at 1000 VAC
Contact - Coil Tested at 1500 VAC
Service life
Electrical 2) Min. 100 x 10³ ops.
Mechanical Min. 50 x 106 ops. (3 Hz)
Switching capacity
Minimum 0.01 mA / 10 mV DC
Maximum 30 W / 62.5 VA
Protective circuit
Internal None
External
AC RC combination or VDR
DC Inverse diode, RC combination or VDR
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 367: X20DO4529 - Technical data

1) Number of outputs x Contact resistance x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the
module.)
2) With a resistive load. See also section "Electrical service life"

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4.15.12.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
On Error or reset status
e+r Red on / Green single flash Invalid firmware
1-4 Orange Output status of the corresponding digital output

Table 368: Status LEDs

4.15.12.5 Pinout

r e

X20 DO 4529
1 2
34

NC 1 NC 2

COM 1 COM 2

NO 1 NO 2

NC 3 NC 4

COM 3 COM 4

NO 3 NO4

Figure 344: Pinout

4.15.12.6 Connection example

DO

115 VAC 24 VDC

+24 VDC +24 VDC

GND GND

Figure 345: Connection example

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4.15.12.7 Output circuit diagram

NC x

COM x

NO x

Output status

I/O status
LED (orange)

Figure 346: Output circuit diagram

4.15.12.8 Maximum switching power

Maximum switching power

2
AC resistive
Switching current [A]

0.5
DC resistive
0.3

0.2

0.1
1 2 5 10 20 30 50 100 200

Switching voltage [V]

Figure 347: Maximum switching power

4.15.12.9 Electrical service life

Electrical service life

100
Switching operations (x10⁴)

70
50
40
30
30 VD
C
re
si s
20
12

t iv
e
5V
DC
re

10
si s
t iv
e

0 0.2 0.4 0.6 0.8 1.0 1.2

Switching current [A]

Figure 348: Electrical service life

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4.15.12.10 Register description

4.15.12.10.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.12.10.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 4 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3

1) The offset specifies where the register is within the CAN object.

4.15.12.10.3 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.12.10.3.1 Switching state of digital outputs 1 to 4

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput04
The switching state of digital outputs 1 to 4 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 15 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
3 DigitalOutput04 0 Digital output 04 reset
1 Digital output 04 set

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4.15.12.10.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.12.10.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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4.15.13 X20DO4613

4.15.13.1 General information

The module is a digital output module that is equipped with 4 opto-triac outputs using phase-angle control. L and
N are fed to the module for zero-crossing detection.
The 4 outputs are electrically isolated from one another and are used for controlling external power triacs or non-
parallel thyristors.
• 4 digital outputs
• Controls external power triacs or non-parallel thyristors
• Outputs with 48 - 240 VAC
• 50 Hz or 60 Hz
• Outputs electrically isolated from one another
• Phase-angle control
• Zero-crossing detection
• Negative half-waves can be switched off
• 2-wire connections
• 240 V coding
• OSP mode
• Frequency mode

Danger!
Risk of electric shock!
The terminal block must only be allowed to conduct voltage when it is inserted. It must not under any
circumstances be removed or inserted when voltage is applied or have voltage applied to it when it
is removed.

4.15.13.2 Order data

Model number Short description Figure

Digital output modules
X20DO4613 X20 digital output module, 4 triac coupler outputs, 12 to 240
VAC, 50 mA, zero-crossing detection, 240 V keyed,...
Required accessories
Bus modules
X20BM12 Bus module, 240 VAC keyed, internal I/O supply continuous
Terminal blocks
X20TB32 X20 terminal block, 12-pin, 240 VAC keyed

Table 369: X20DO4613 - Order data

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4.15.13.3 Technical data

Product ID X20DO4613
Short description
I/O module 4 digital outputs for controlling external power triacs or non-parallel thyristors
General information
B&R ID code 0xAD05
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, using status LED
Power consumption
Bus 0.8 W
Internal I/O -
External I/O -
Additional power dissipation caused by the actua- +1 W
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel Yes
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital outputs
Design Opto-triac
Wiring N.O. contact
Nominal voltage 48 to 240 VAC
Rated frequency 47 to 63 Hz
Rated current at 25°C
Nominal output current 80 mA
Total nominal current 320 mA
Current over entire temperature range
Output current 50 mA
Summation current 200 mA
Connection type 2-wire connections
Zero-crossing detection Yes
Holding current Max. 3.5mA
Leakage current Max. 1.5 mA (per channel)
Residual voltage (on-state voltage) Max. 3V
Phase-angle control
Range 5 to 95%
Resolution 1%
Accuracy (60 to 240 VAC) <100 μs
Voltage monitoring L - N No
Recommended cabling Twisted pair cabling to the terminal pairs
Cable length Max. 10 m
Overvoltage protection between L and N Yes
Isolation voltage
Channel - Bus Tested at 2300 VAC
Channel - Channel Tested at 2300 VAC
Protective circuit
External General protection
Internal Snubber circuit (RC element) and varistor
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C

Table 370: X20DO4613 - Technical data

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Product ID X20DO4613
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB32 terminal block separately
Order 1x X20BM12 bus module separately
Spacing 12.5 +0.2 mm

Table 370: X20DO4613 - Technical data

1) Number of outputs x residual voltage (on-state voltage) x nominal output current (A calculation example can be found on the B&R website in the download
area for the module.)

4.15.13.4 Status LEDs

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off Module supply not connected
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
Flickering (ap- Module is in OSP state
prox. 10 Hz)
e Red Off Module supply not connected or everything OK
On Error or reset status
Single flash Loss of zero-crossing signal (input voltage absent or too low)
e+r Red on / Green single flash Invalid firmware
1-4 Orange Control status of the corresponding digital output

4.15.13.5 Pinout

r e
X20 DO 4613

1 2
3 4

DO 11 DO 12

DO 21 DO 22

DO 31 DO 32

DO 41 DO 42

L L

N N

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4.15.13.6 Connection example

Power triac Power thyristor

48 - 240 VAC
L

Line filter

Load
N DO

Twisted pair lines T 0.5 A

L L

N N

+24 VDC +24 VDC

GND GND

4.15.13.7 Output circuit diagram

Triac Coupler
Output status 1
DO 11
VDR
DO 12
I/O status
(LED orange)

Triac Coupler
Output status 2
DO 21
VDR
DO 22
I/O status
(LED orange)

Triac Coupler
Output status 3
DO 31
VDR
DO 32
I/O status
(LED orange)

Triac Coupler
Output status 4
DO 41
VDR
DO 42
I/O status
(LED orange)

N
Zero-crossing detection
VDR

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4.15.13.8 Operating principle

The digital output module DO4613 was designed to control external triacs and thyristors.
The module is equipped with internal zero-crossing detection. Zero-crossing detection is the basis for a software
PLL that generates 200 times the zero-crossing frequency. The output signal of the PLL is the base timer for the
4 PWM outputs in both digital and analog mode.
Upon detection of lost periods or periods that are too short, control to the outputs is cut until the PLL is tuned
correctly. The tuning procedure can take several seconds. In addition, the "ZeroCrossingStatus" bit is set and the
error LED enabled (valid frequency range for the supply is 47 to 63 Hz).

Information:
The jitter of the output signals generated by the PLL and communication can reach 0.5%.

4.15.13.9 Operation with inductive loads

As inherent to its functional principal, the triac output is cleared when the current crosses zero. Because zero
crossing for current is delayed with inductive loads, it is possible that the triac will be fired again even though it is
not completely cleared at higher output values (between 50 and 100% depending on the inductance of the load).
In this case, a full-wave is output. This causes the available control range to be reduced (0 to 100%).
For control beyond the point of full-wave control (up to 100%), the value that is physically output no longer changes.
However, this does not cause damage to the module.

Switch-off delay caused by

Inductive load

Zero crossing: Voltage

Zero crossing: Current

Input voltage
Output voltage
Output current
Internal firing signal for the triac

CfO_SwitchOffValue in %

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4.15.13.10 Register description

4.15.13.10.1 Function model 0 - Standard and Function model 2 - Frequency mode

The only difference between function model 2 and function model 0 is the possibility of generating half-wave pat-
terns in various frequencies. Register 18 "CfO_Frequency" is an additional register for this.
Register Name Data type Read Write
Cyclic Non-cyclic Cyclic Non-cyclic
Configuration - General
2+N*2 AnalogOutput0N (Index N = 1 to 4) USINT ●
18 CfO_Frequency UINT ●
18 + N * 2 ConfigOutput0N (Index N = 1 to 4) USINT ●
28 ConfigOutput05 USINT ●
29 CfO_OutputTolerance USINT ●
Communication
2 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 StatusInput01 USINT ●
ZeroCrossingInput Bit 4
ZeroCrossingStatus Bit 7

4.15.13.10.2 Function model 1 - OSP

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Configuration - General
2+N*2 AnalogOutput0N (Index N = 1 to 4) USINT ●
18 + N * 2 ConfigOutput0N (Index N = 1 to 4) USINT ●
28 ConfigOutput05 USINT ●
29 CfO_OutputTolerance USINT ●
Configuration - OSP
34 Activating the OSP output in the module USINT ●
OSPValid Bit 0
32 CfgOSPMode USINT ●
36 CfgOSPValue USINT ●
36 + N * 2 CfgOSPValue0N (Index N = 1 to 4) USINT ●
Communication
2 Switching state of digital outputs 1 to 4 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 Status of the outputs USINT ●
ZeroCrossingInput Bit 4
ZeroCrossingStatus Bit 7

4.15.13.10.3 Function model 254 - Bus controller

Register Offset Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Configuration - General
2+N*2 (N-1) * 2 AnalogOutput0N (Index N = 1 to 4) USINT ●
18 + N * 2 - ConfigOutput0N (Index N = 1 to 4) USINT ●
28 - ConfigOutput05 USINT ●
29 - CfO_OutputTolerance USINT ●
Communication
30 0 Status of the outputs USINT ●
ZeroCrossingInput Bit 4
ZeroCrossingStatus Bit 7

1) The offset specifies the position of the register within the CAN object.

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4.15.13.10.4 General information

The digital output module was designed for phase control of resistive and inductive loads.
The module is equipped with internal zero-crossing detection. Zero crossing detection is the basis for a software
PLL that generates 200 times the zero crossing frequency. The output signal of the PLL is the base timer for the
2 PWM outputs in both digital and analog mode.
Upon detection of lost periods or periods that are too short, control of the outputs is cut until the PLL is tuned
correctly (can take several seconds). In addition, the "ZeroCrossingStatus" bit is set and the Error LED is enabled
(valid frequency range for the supply is 45 to 65 Hz).

Information:
The jitter of the output signals generated by the PLL and communication can reach 0.5%.

4.15.13.10.5 Digital outputs

The output state of the outputs defined as digital is transferred to the output ports of the control switch in sync with
the connected power mains. The switch-on state is applied when the voltage crosses zero on the positive half-
wave and the switch-off state at the zero crossing for current in each half wave.

4.15.13.10.5.1 Switching state of digital outputs 1 to 4

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput04
The switching state of digital outputs 1 to 4 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 15 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
3 DigitalOutput04 0 Digital output 04 reset
1 Digital output 04 set

Information:
The states in these registers are only applied when the channels are set to DIGITAL in register
4.15.13.10.7.3 "ConfigOutput05".
When using the setting "packed outputs" ALL channels must be set to DIGITAL. Mixed operation is
not possible.

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4.15.13.10.6 Analog outputs

The output value of the outputs defined as analog outputs (unit percent) is switched through to the control ports in
sync with power mains. The analog value is output to the TRIAC control port in the range between (output value
> SwitchOffValue) and (output value <= 95%) with a resolution of 1%.
Changes to the output value are applied at the next positive half-wave.

4.15.13.10.6.1 Commutation angle for analog outputs 1 - 4

Name:
AnalogOutput01 to AnalogOutput04
These registers are used to set the commutation angle for phase angle control.
Values between 0 and 100 correspond to the output value for the respective channel in percent. Values above
100 correspond to 100%.
Data type Value
USINT 0 to 100

Information:
The commutation angle for phase angle control set in these registers are only applied when the chan-
nels are set to ANALOG in register 4.15.13.10.7.3 "ConfigOutput05".

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4.15.13.10.7 Output configuration

4.15.13.10.7.1 Configuring the half-wave pattern

Name:
CfO_Frequency
This register can only be used in function model 2 - Frequency mode and makes it possible to configure the output
of half-wave patterns in various frequencies. The commutation angle of the outputs is not affected by this. The
following frequency patterns can be configured:
• 100 half-waves

100 half-waves

• 50 half-waves

50 half-waves

• 33 half-waves

33 half-waves

• 25 half-waves

25 half-waves

With multichannel operation, the different channels should be operated with delayed half-waves in order to ensure
that the load is placed evenly on the module.
Data type Value
UINT See bit structure.

Bit structure:
Bit Description Value Information
0-3 Channel 1 0000 100 half-waves/second
0001 50 half-waves/second
0010 25 half-waves/second
0011 33 half-waves/second
0101 50 half-waves/second delayed by 1 half-wave
0110 25 half-waves/second delayed by 2 half-waves
0111 33 half-waves/second delayed by 1 half-wave
4-7 Channel 2 0000 to 0111 See channel 1
8 - 11 Channel 3 0000 to 0111 See channel 1
12 - 15 Channel 4 0000 to 0111 See channel 1

Information:
This function is available beginning with firmware version 940. This can be included beginning with
hardware variant 8.

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4.15.13.10.7.2 Setting the switch-off time

Name:
ConfigOutput01 to ConfigOutput04
This register defines how far in front of the zero cross-over the internal control signal for the TRIAC is switched off.
Increasing this value may be necessary in order to prevent unwanted firing of the TRIAC in the event of a slight
disturbance in the mains frequency.
With smaller loads, it is important to ensure that this switch off value is not set to large (too early) to prevent
switching off prematurely.
The triac can of course only be fired before the set switch-off time.
"SwitchOffValue" in the AS I/O configuration.

1/f

Triac
Control signal

Switch-off value
5 to 50%

Data type Value Description

USINT 5 to 50 Switch-off time in %

4.15.13.10.7.3 Configuration of the output channels

Name:
ConfigOutput05
The configuration of the output channels are stored in this register.
"Output type digital/analog" and "Output type full/half wave" in the AS I/O configuration
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Channel 1: Digital / Analog output 0 Output channel 1 is defined as a digital output. The output sta-
tus is defined using bit 0 in the register DigitalOutput 1 - 4
1 Output channel 1 is defined as an analog output. The output
status is defined in the register AnalogOutput01
... ...
3 Channel 4: Digital / Analog output 0 Output channel 4 is defined as a digital output. The output sta-
tus is defined using bit 1 in the register DigitalOutput 1 - 4
1 Output channel 2 is defined as an analog output. The output
status is defined in the register AnalogOutput04
4 Channel 1: Full-wave / half-wave control1) 0 Full-wave control on output channel 1
1 Negative half-wave on output channel 1 is suppressed.
... ...
7 Channel 4: Full-wave / half-wave control1) 0 Full-wave control on output channel 4
1 Negative half-wave on output channel 4 is suppressed.

1) Not available in function model 2 - Frequency mode.

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4.15.13.10.7.4 Switching behavior for zero-crossing errors

Name:
CfO_OutputTolerance
This register can be used to set the switching behavior of the trigger. After the number of zero-crossing errors
configured in Bit 0 to 4, the output is switched off for at least 3 periods. This is followed by synchronization with
the zero signal according to Bit 7.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-4 Trigger for Resync 0 to 30 Number of zero-crossover errors
5-6 Reserved -
7 Fast settling 0 Fast synchronization
1 PLL synchronization

Fast synchronization
With this option, the trigger point is closed-loop controlled after each individual zero-crossover and input jitter.
• Advantage: Increased tolerance and faster response to deviations in mains frequency
• Disadvantage: Increased switch-on jitter for firing signal by zero cross signal ±100 µSec
PLL synchronization
With this option the intervals between zero cross-overs are measured and the PLL frequency is updated accord-
ingly.
• Advantage: Jitter-free firing signal
• Disadvantage: When the output is switched off, additional measurement phases are required before it can
be switched back on.

Information:
This function is available starting with Firmware version 928. This can be installed with hardware ver-
sion 7 and hardware revision B4 or higher.

4.15.13.10.8 Status of the outputs

Name:
ZeroCrossingInput
ZeroCrossingStatus
StatusInput01
The operating status of the outputs is mapped in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits should
be set up individually as data points in the AS I/O mapping ("ZeroCrossingInput" through "ZeroCrossingStatus") or
whether this register should be displayed as an individual USINT data point ("StatusInput01").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0-3 Reserved -
4 ZeroCrossingInput 0 Zero cross signal during the negative half-wave
1 Zero cross signal during the positive half-wave
5-6 Reserved -
7 ZeroCrossingStatus 0 Zero cross signal OK
1 Zero cross signal has dropped out

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4.15.13.10.9 "OSP" function model

In the "OSP" function model (Operator Set Predefined), the user defines an analog value or digital pattern. This
OSP value is output as soon as communication between the module and master is interrupted.
Functionality
The user can choose between two OSP modes:
• Retain last valid value
• Replace with static value
In the first case, the module retains the last value as validly recognized output state.
When selecting the mode, "Replace with static value" a plausible output value must be entered in the corresponding
value register. If an OSP event occurs, this value will be output instead of the value currently requested by the task.

4.15.13.10.9.1 Activating the OSP output in the module

Name:
OSPValid
This data point offers the possibility to start module output and request OSP operation during running operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 OSPValid 0 Request OSP operation (after initial start or module in Standby)
1 Request normal operation
1-7 Reserved 0

There is one OSPValid bit on the module, which is managed by the user task. It must be set when the enabled
channels are started. As long as the OSPValid bit remains set in the module, the module behaves the same as
the "Standard" function model.
If an OSP event occurs (e.g. communication between the module and master CPU interrupted) then the OSPValid
bit will be reset on the module. The module enters OSP mode and the output occurs in the "OSPMode" register
according to the configuration.
The following applies:
The OSP replacement value remains even after the communication channel has recovered. OSP mode
is only exited when a set OSPValid bit is transferred.
When the master CPU is restarted, the OSPValid bit is re-initialized on the master CPU. It must once
more be set by the application and transferred via the bus.
When temporary communication errors occur between the module and master CPU (e.g. due to EMC),
a few bus cycles will pass without refreshing the cyclic registers. The OSPValid bit is reset internally in
the module - the bit in the CPU however remains set. Upon the next successful transfer, the OSPValid
bit in the module is set again and the module returns to normal operation.
The ModulOK bit can be evaluated if the task in the master CPU needs to know which output mode the module
is currently in.

Warning!
If the OSPValid bit is reset to "0" on the module, then the output state no longer depends on the
responsible task in the master CPU. However, output still occurs according to the configuration of the
OSP replacement value.

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4.15.13.10.9.2 Setting the OSP mode

Name:
CfgOSPMode
This register essentially controls a channel's behavior when OSP is being used.
Data type Value Description
USINT 0 Replace with static value
1 Retain last valid value

4.15.13.10.9.3 Define the OSP digital output value

Name:
CfgOSPValue
This register contains the digital output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 0 or 1 OSP output value for channel DigitalOutput00
... ...
x 0 or 1 OSP output value for channel DigitalOutput0x

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.15.13.10.9.4 Define the OSP analog output value

Name:
CfgOSPValue01 to CfgOSPValue04
This register contains the analog output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
USINT 0 to 100

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.15.13.10.10 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
All channels 150 μs

4.15.13.10.11 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
All channels 150 μs

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4.15.14 X20DO4623

4.15.14.1 General information

The module is a digital output module that is equipped with 4 SSR outputs with zero cross-over switches and uses
2-line connections. The module is also equipped with integrated full-wave control. The supply (L and N) is fed
directly to the module.
• 4 digital outputs
• Outputs with integrated snubber circuit
• Outputs with 100 to 240 VAC
• L switching
• 50 Hz or 60 Hz
• 2-wire connections
• Integrated full-wave control
• 240 V coding

Danger!
Risk of electric shock!
The terminal block must only be allowed to conduct voltage when it is inserted. It must not under any
circumstances be removed or inserted when voltage is applied or have voltage applied to it when it
is removed.

4.15.14.2 Order data

Model number Short description Figure

Digital output modules
X20DO4623 X20 digital output module, 4 outputs, 100-240 VAC, 0.5 A,
source, 240 V keyed, 2-wire connections
Required accessories
Bus modules
X20BM12 Bus module, 240 VAC keyed, internal I/O supply continuous
Terminal blocks
X20TB32 X20 terminal block, 12-pin, 240 VAC keyed

Table 371: X20DO4623 - Order data

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4.15.14.3 Technical data

Product ID X20DO4623
Brief description
I/O module 4 digital SSR outputs 100 - 240 VAC, 2-wire connections
General information
B&R ID code 0x267C
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software status
Outputs Yes, with status LED
Power consumption
Bus 0.52 W
Internal I/O -
External I/O 0.38 W
Additional power dissipation caused by the actua- +3.2
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital outputs
Design SSR
Wiring L switching
Nominal voltage 100 to 240 VAC
Rated frequency 47 to 63 Hz
Nominal output current 0.5 A
Total nominal current 1.0 A
Surge current 7 A (20 ms), 2 A (1 s)
Connection type 2-wire connections
Zero crossover switches Yes
Leakage current Max. 1.5 mA at 240 V
Residual voltage (on-state voltage) 1.6 V
Switching delay
At 50 Hz
0 -> 1 ≤ 11 ms
1 -> 0 ≤ 11 ms
At 60 Hz
0 -> 1 ≤ 9.3 ms
1 -> 0 ≤ 9.3 ms
Isolation voltage between channel and bus Tested at 2500 VAC
Voltage monitoring L - N No
Overvoltage protection between L and N Yes
Output voltage
Minimum 75 VAC
Maximum 264 VAC
Protective circuit
External Generally a varistor or fuse
Internal Snubber circuit (RC element)
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0,5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing

Table 372: X20DO4623 - Technical data

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Product ID X20DO4623
Mechanical characteristics
Note Order 1x X20TB32 terminal block separately
Order 1x X20BM12 bus module separately
Spacing 12.5 +0.2 mm

Table 372: X20DO4623 - Technical data

1) Number of outputs x residual voltage (on-state voltage) x nominal output current (A calculation example can be found on the B&R website in the download
area for the module.)

4.15.14.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
On Error or reset status
Single flash Zero cross-over signal has dropped out
e+r Red on / Green single flash Invalid firmware
1-4 Orange Control status of the corresponding digital output

Table 373: Status LEDs

4.15.14.5 Pinout

r e
X20 DO 4623

1 2
3 4

DO 1 DO 2

DO 3 DO 4

N N

N N

L L

N N

Figure 349: Pinout

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4.15.14.6 Connection example

DO

Actuator
Actuator
T 10 A
L L

N N

+24 VDC +24 VDC

GND GND

4.15.14.7 Output circuit diagram

SSR
Output x
Output status
zc

I/O status
(LED orange) electrical
separation

L
Zero External
power supply
N

Figure 350: Output circuit diagram

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4.15.14.8 Integrated full-wave control

Full-wave control is used to control power for electrical power consumers that are operated with AC voltage. Tem-
perature control is a typical application
Unlike phase-angle control, the sine wave oscillation form of the mains voltage is not changed during full-wave
control. This significantly reduces system perturbation.
The output voltage (channel) is switched on and off at a certain ratio. This switches the multi-cycle packets. A
multi-cycle packet consists of a number of complete sine waves throughout a cycle. The relationship between
the power-on duration and the cycle duration results in the desired effect of reduced power consumption by the
connected power consumer.
With the full-wave control that is integrated in the module, a maximum of 24 full waves can be provided on the
outputs per cycle. Control takes place in 4% steps.
Settings Full waves
SW% % 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0 0
4 ●
8 ● ●
12 ● ● ●
16 ● ● ● ●
20 ● ● ● ● ●
24 25 ● ● ● ● ● ●
28 ● ● ● ● ● ● ●
32 ● ● ● ● ● ● ● ●
36 ● ● ● ● ● ● ● ● ●
40 ● ● ● ● ● ● ● ● ● ●
44 ● ● ● ● ● ● ● ● ● ● ●
48 50 ● ● ● ● ● ● ● ● ● ● ● ●
52 ● ● ● ● ● ● ● ● ● ● ● ● ●
56 ● ● ● ● ● ● ● ● ● ● ● ● ● ●
60 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
64 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
68 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
72 75 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
76 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
80 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
84 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
88 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
92 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
96 100 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●

Table 374: - Full-wave control in 4% steps

Example of full-wave control (8%):

UChannel

1 cycle
(24 full waves)

Figure 351: Example of full-wave control (8%)

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4.15.14.9 Register description

4.15.14.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
4 1 AnalogOutput01 USINT ●
6 2 AnalogOutput02 USINT ●
8 3 AnalogOutput03 USINT ●
10 4 AnalogOutput04 USINT ●
28 - Output configuration 1 - 4 ConfigOutput01 USINT ●
30 1 StatusInput01 USINT ●
ZeroCrossingInput Bit 0
ZeroCrossingStatus Bit 4

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.14.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
4 0 AnalogOutput01 USINT ●
6 2 AnalogOutput02 USINT ●
8 4 AnalogOutput03 USINT ●
10 6 AnalogOutput04 USINT ●
28 - Output configuration 1 - 4 ConfigOutput01 USINT ●
30 0 Zero crossing status USINT ●
ZeroCrossingInput Bit 0
ZeroCrossingStatus Bit 4

1) The offset specifies where the register is within the CAN object.

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4.15.14.9.3 Digital outputs

The output status is transferred to the control switch asynchronously to the connected network. The outputs switch
on when the voltage crosses zero and switch off when the current crosses zero.

4.15.14.9.3.1 Switching state of digital outputs 1 to 4

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput04
The switching state of digital outputs 1 to 4 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 15 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
3 DigitalOutput04 0 Digital output 04 reset
1 Digital output 04 set

Information:
The states are only applied when the channels are set to DIGITAL in Setting the output configuration.
When using the setting "packed outputs" ALL channels must be set to DIGITAL. Mixed operation is
not possible.

4.15.14.9.4 Analog outputs

The output value is transferred to the control circuit in sync with the connected power mains according to the
firing pattern table (see "Integrated full-wave control"). The analog value is output with a resolution of ~4% over a
duration of 24 complete waves. Values > 96% result in full control. Changes to the output value within an interval
are applied after the next zero crossover.

4.15.14.9.4.1 Setting the output value from the firing pattern table

Name:
AnalogOutput01 to AnalogOutput04
These registers are used to set the output value from the firing pattern table.
Values between 0 and 100 correspond to the output value for the respective channel in percent. Values above
100 correspond to 100%.
Data type Value
USINT 0 to 100

Information:
The states in these registers are only applied when the channels are set to ANALOG in Setting the
output configuration.

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4.15.14.9.4.2 Setting the output configuration

Name:
Output configuration 1 - 4
ConfigOutput01
Each channel can be configured for either "digital" or "analog" operation in this register. Depending on the setting,
the corresponding DigitalOutput or AnalogOutput registers must be written.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Description
0 Channel 1 0 Digital register is used
1 1 Analog register is used
... ...
3 Channel 4 0 Digital register is used
1 Analog register is used
4-7 0

4.15.14.9.5 Zero crossing status

Name:
ZeroCrossingInput
ZeroCrossingStatus
StatusInput01
Zero crossing detection uses a fixed filter time of 1 ms and a scanning frequency of 10 kHz. When a missing or too
short period is detected, control is switched off until at least 2 periods are detected correctly, and the status flag
is set accordingly. Control is offset by 2 ms from the negative half-wave until the next zero crossover is detected
correctly or another error occurs. This is normally at least one complete wave.
Monitoring is activated at the first zero crossover after being switched on.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits should
be set up individually as data points in the AS I/O mapping ("ZeroCrossingInput" through "ZeroCrossingStatus") or
whether this register should be displayed as an individual USINT data point ("StatusInput01").
Data type Value Information
USINT 0 to 17 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 ZeroCrossingInput1) 0 Signal during the negative half-wave
1 Signal during the positive half-wave
1-3 0
4 ZeroCrossingStatus 0 No error
1 Zero crossover failed
5-7 0

1) Value is valid if no error has occurred (ZeroCrossingStatus= 0)

4.15.14.9.6 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Standard function model 100 μs
Bus controller function model 150 μs

4.15.14.9.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Function model 0 Equal to the minimum cycle time
Function model 1 Equal to the minimum cycle time

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4.15.15 X20DO4633

4.15.15.1 General information

The module is a digital output module with phase-angle control that is equipped with 4 Triac outputs using 2-line
connections. The supply (L and N) is fed directly to the module.
• 4 digital outputs
• Outputs with integrated snubber circuit
• Outputs with 12 to 240 VAC
• L switching
• Zero-crossing detection
• Phase-angle control
• Open-circuit detection for each channel
• Negative half-waves can be switched off
• 50 Hz or 60 Hz
• 2-wire connections
• 240 V coding
• OSP mode
• Frequency mode

Danger!
Risk of electric shock!
The terminal block must only be allowed to conduct voltage when it is inserted. It must not under any
circumstances be removed or inserted when voltage is applied or have voltage applied to it when it
is removed.

4.15.15.2 Order data

Model number Short description Figure

Digital output modules
X20DO4633 X20 digital output module, 4 triac outputs, 12 to 240 VAC, 1 A,
L switching, phase angle control, 240 V keyed
Required accessories
Bus modules
X20BM32 X20 bus module for double-width modules, 240 VAC keyed, in-
ternal I/O supply continuous
Terminal blocks
X20TB32 X20 terminal block, 12-pin, 240 VAC keyed

Table 375: X20DO4633 - Order data

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4.15.15.3 Technical data

Product ID X20DO4633
Short description
I/O module 4 digital outputs 12 to 240 VAC for 2-wire connections
General information
B&R ID code 0xAC3A
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, using status LED
Power consumption
Bus 0.6 W
Internal I/O -
External I/O -
Additional power dissipation caused by the actua- +6.4 W
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital outputs
Design Triac
Wiring L switching
Nominal voltage 12 to 240 VAC
Rated frequency 47 to 63 Hz
Nominal output current 1A
Total nominal current 4A
Maximum current
Output current 1.25 A
Summation current 5A
Connection type 2-wire connections
Zero-crossing detection Yes
Minimum holding current IH 15 mA
Leakage current Max. 2 mA at 240 V and 50 Hz
Max. 2.4 mA at 240 V and 60 Hz
Residual voltage (on-state voltage) 1.6 V
Phase-angle control
Range 5 to 95%
Resolution 1%
Accuracy (60 to 240 VAC) <100 μs
Voltage monitoring L - N No
Additional functions Open line detection
Overvoltage protection between L and N Yes
Isolation voltage
Terminal block - Bus Tested at 2300 VAC (Rev. <E0 1500 VAC)
Terminal block - 24 V Tested at 2300 VAC (Rev. <E0 2000 VAC)
Terminal block - PE Tested at 2300 VAC (Rev. <E0 1500 VAC)
Protective circuit
External See section "External fuses"
Internal Snubber circuit (RC element) and varistor
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C

Table 376: X20DO4633 - Technical data

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Product ID X20DO4633
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB32 terminal block separately
Order 1x X20BM32 bus module separately
Spacing 25 +0.2 mm

Table 376: X20DO4633 - Technical data

1) Number of outputs x residual voltage (on-state voltage) x nominal output current (A calculation example can be found on the B&R website in the download
area for the module.)

4.15.15.4 Status LEDs

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off Module supply not connected
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
Flickering (ap- Module is in OSP state
prox. 10 Hz)
e Red Off Module supply not connected or everything OK
On Error or reset status
Single flash Loss of zero-crossing signal (I/O supply voltage not applied or too low)
e+r Red on / Green single flash Invalid firmware
1-4 Orange Control status of the corresponding digital output

4.15.15.5 Pinout

The following points must be taken into consideration when wiring the module:
• For thermal reasons, wires with a cross-section ≥1.5 mm² must be used to wire the module.
• The neutral return lines for the outputs must be wired to the terminal block separately for each channel
and must not be bypassed in the field.
• A line filter must be used for the 240 V supply that provides ≥40 dB attenuation at 150 kHz and works
up to 5 MHz.

r e
X20 DO 4633

1 2
3 4

DO 1 DO 2

DO 3 DO 4

N N

N N

L L

N N

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4.15.15.6 Connection example

DO

Actuator
Actuator
T 10 A
L L

N N

+24 VDC +24 VDC

GND GND

4.15.15.7 OSP hardware requirements

In order to best use OSP mode, make sure when creating the application that the output module and CPU have
separate power supplies.

4.15.15.8 Output circuit diagram

DO 1
Output status 1
VDR

N
I/O status
(LED orange)

DO 4
Output status 4
VDR

N
I/O status
(LED orange)

Null Zero cross

N
detection
External
VDR
Power supply
L

4.15.15.9 External fuses

The following protective circuit must be used for safe operation:

Protective circuit Value
For the supply lines Fuse T 10 A
For the outputs Fuse Melting integral I2t ≤ 36 A2s when tp = 10 ms
With an inductive load Varistor1) e.g. varistor with 275 VRMS at 240 VAC
For the supply voltage Line filter2) Attenuation ≥40 dB at 150 kHz, effective range up to 5 MHz

1) See also section 4.15.15.13 "Operation with inductive loads" on page 1180
2) Meeting the limit values specified in the standards EN 61131, EN 55011 and EN 55022 (each Class A) requires installation of a line filter in the 240 V supply
line. Line filters such as the Schaffner FN 2412‐8‐44 can be used.
If periodic ground transients occur on the supply lines (as can occur with upstream inverters), it is necessary to use an asymmetric filter that keeps these
types of changes in potential below a few volts (e.g. "Sinus Plus" from Schaffner) in addition to the symmetric filter.

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4.15.15.10 Derating

The derating listed below must be applied for the current:

Legend: Horizontal installation
Vertical installation

1.25

0.938

Output current [A]

0
-25 25 35 50 60
Ambient temperature [°C]

4.15.15.11 Operating principle

The digital output module was designed for phase control of resistive and and inductive loads. The triac outputs
do not have short circuit protection. The integrated open-circuit detection makes it possible to recognize defects
on the load or the cabling (see 4.15.15.12 "Open line detection" on page 1179).
The module is equipped with internal zero-crossing detection. Zero-crossing detection is the basis for a software
PLL that generates 200 times the zero-crossing frequency. The output signal of the PLL is the base timer for the
PWM outputs in both digital and analog mode.
Upon detection of lost periods or periods that are too short, control to the outputs is cut until the PLL is tuned
correctly. The tuning procedure can take several seconds. In addition, the "ZeroCrossingStatus" bit is set and the
error LED enabled (valid frequency range for the supply is 45 to 65 Hz).

Information:
The jitter of the output signals generated by the PLL and communication can reach 0.5%.

4.15.15.12 Open line detection

The module is equipped with open-circuit detection. Note that open-circuit detection only works when the output
is enabled. An open-circuit will not be detected if the output is turned off.
In addition, open-circuit detection is restricted or doesn't work at all for inductive loads. This depends on the induc-
tance of the load and should be determined beforehand, if necessary.

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4.15.15.13 Operation with inductive loads

As inherent to its functional principal, the triac output is cleared when the current crosses zero. Because zero
crossing for current is delayed with inductive loads, it is possible that the triac will be fired again even though it is
not completely cleared at higher output values (between 50 and 100% depending on the inductance of the load).
In this case, a full-wave is output. This causes the available control range (0 to 95%) to be changed.
For open line detection (LowCurrentStatus), a pause in control is required where the triac is not permitted to be
fired. The full wave that is created with inductive loads causes open line detection to be triggered even though
the load on the output is sufficient.
This behavior can be used to detect the full wave and properly adjust the control range (Example: If open line
detection is triggered at a control value of 70%, that means that 0-70% corresponds to 0-100% output).

Switch-off delay caused by

Inductive load

Zero crossing: Voltage

Zero crossing: Current

Input voltage
Output voltage
Output current
Internal firing signal for the triac

CfO_SwitchOffValue in %

With inductive loads, a suitable varistor must be provided between the output DO x and the phase L (e.g. a varistor
with 275 VRMS at 240 VAC).

DO
Actuator

VDR

L L

N N

+24 VDC +24 VDC

GND GND

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4.15.15.14 Register description

4.15.15.14.1 Function model 0 - Standard and Function model 2 - Frequency mode

The only difference between function model 2 and function model 0 is the possibility of generating half-wave pat-
terns in various frequencies. Register 18 "CfO_Frequency" is an additional register for this.
Register Name Data type Read Write
Cyclic Non-cyclic Cyclic Non-cyclic
Configuration - General
2+N*2 AnalogOutput0N (Index N = 1 to 4) USINT ●
18 CfO_Frequency UINT ●
18 + N * 2 CfO_SwitchOffValueN (Index N = 1 to 4) USINT ●
28 CfO_OutputConfig USINT ●
29 CfO_OutputTolerance USINT ●
Communication
2 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 StatusInput01 USINT ●
LowCurrentStatus1 Bit 0
... ...
LowCurrentStatus4 Bit 3
ZeroCrossingInput Bit 4
ZeroCrossingStatus Bit 7

4.15.15.14.2 Function model 1 - OSP

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Configuration - General
2+N*2 AnalogOutput0N (Index N = 1 to 4) USINT ●
18 + N * 2 CfO_SwitchOffValueN (Index N = 1 to 4) USINT ●
28 CfO_OutputConfig USINT ●
29 CfO_OutputTolerance USINT ●
Configuration - OSP
34 Activating the OSP output in the module USINT ●
OSPValid Bit 0
32 Setting the OSP mode USINT ●
36 CfgOSPValue USINT ●
36 + N * 2 CfgOSPValue0N (Index N = 1 to 4) USINT ●
Communication
2 Switching state of digital outputs 1 to 4 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3
30 Status of the outputs USINT ●
LowCurrentStatus1 Bit 0
... ...
LowCurrentStatus4 Bit 3
ZeroCrossingInput Bit 4
ZeroCrossingStatus Bit 7

4.15.15.14.3 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
Configuration - General
2+N*2 (N-1) * 2 AnalogOutput0N (Index N = 1 to 4) USINT ●
18 + N * 2 - CfO_SwitchOffValueN (Index N = 1 to 4) USINT ●
28 - CfO_OutputConfig USINT ●
29 - CfO_OutputTolerance USINT ●
Communication
30 0 Status of the outputs USINT ●
LowCurrentStatus1 Bit 0
... ...
LowCurrentStatus4 Bit 3
ZeroCrossingInput Bit 4
ZeroCrossingStatus Bit 7

1) The offset specifies the position of the register within the CAN object.

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4.15.15.14.4 General information

The digital output module was designed for phase control of resistive and inductive loads. The triac outputs do
not have short circuit protection, but have open line detection that can be used to find defects in the consumer
or the wiring.
The module is equipped with internal zero-crossing detection. Zero crossing detection is the basis for a software
PLL that generates 200 times the zero crossing frequency. The output signal of the PLL is the base timer for the
2 PWM outputs in both digital and analog mode.
Upon detection of lost periods or periods that are too short, control of the outputs is cut until the PLL is tuned
correctly (can take several seconds). In addition, the "ZeroCrossingStatus" bit is set and the Error LED is enabled
(valid frequency range for the supply is 45 to 65 Hz).

Information:
The jitter of the output signals generated by the PLL and communication can reach 0.5%.

4.15.15.14.5 Digital outputs

The output state of the outputs defined as digital is transferred to the output ports of the control switch in sync with
the connected power mains. The switch-on state is applied when the voltage crosses zero on the positive half-
wave and the switch-off state at the zero crossing for current in each half wave.

4.15.15.14.5.1 Switching state of digital outputs 1 to 4

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput04
The switching state of digital outputs 1 to 4 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 15 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
3 DigitalOutput04 0 Digital output 04 reset
1 Digital output 04 set

Information:
The states in these registers are only applied when the channels are set to DIGITAL in "Configuration
of the output channels".
When using the setting "packed outputs" ALL channels must be set to DIGITAL. Mixed operation is
not possible.

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4.15.15.14.6 Analog outputs

The output value of the outputs defined as analog outputs (unit percent) is switched through to the control ports in
sync with power mains. The analog value is output to the TRIAC control port in the range between (output value
> SwitchOffValue) and (output value <= 95%) with a resolution of 1%.
A short triac switch-on delay is required for open line detection. Therefore even with output values >= 96%, there
is a a small pause in control.
Changes to the output value are applied at the next positive half-wave
Triac switch-on delay
for open line detection
U

1/f

4.15.15.14.6.1 Commutation angle for analog outputs 1 - 4

Name:
AnalogOutput01 and AnalogOutput04
These registers are used to set the commutation angle for phase angle control.
Values between 0 and 100 correspond to the output value for the respective channel in percent. Values above
100 correspond to 100%.
Data type Value
USINT 0 to 100

Information:
The commutation angle for phase angle control set in these registers are only applied when the chan-
nels are set to ANALOG in Configuration of the output channels.

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4.15.15.14.7 Output configuration

4.15.15.14.7.1 Configuring the half-wave pattern

Name:
CfO_Frequency
This register can only be used in function model 2 - Frequency mode and makes it possible to configure the output
of half-wave patterns in various frequencies. The commutation angle of the outputs is not affected by this. The
following frequency patterns can be configured:
• 100 half-waves

100 half-waves

• 50 half-waves

50 half-waves

• 33 half-waves

33 half-waves

• 25 half-waves

25 half-waves

With multichannel operation, the different channels should be operated with delayed half-waves in order to ensure
that the load is placed evenly on the module.
Data type Value
UINT See bit structure.

Bit structure:
Bit Description Value Information
0-3 Channel 1 0000 100 half-waves/second
0001 50 half-waves/second
0010 25 half-waves/second
0011 33 half-waves/second
0101 50 half-waves/second delayed by 1 half-wave
0110 25 half-waves/second delayed by 2 half-waves
0111 33 half-waves/second delayed by 1 half-wave
4-7 Channel 2 0000 to 0111 See channel 1
8 - 11 Channel 3 0000 to 0111 See channel 1
12 - 15 Channel 4 0000 to 0111 See channel 1

Information:
This function is available beginning with firmware version 940. This can be included beginning with
hardware variant 8.

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4.15.15.14.7.2 Setting the switch-off time

Name:
CfO_SwitchOffValue1 to CfO_SwitchOffValue4
This register defines how far in front of the zero cross-over the internal control signal for the TRIAC is switched off.
Increasing this value may be necessary in order to prevent unwanted firing of the TRIAC in the event of a slight
disturbance in the mains frequency.
With smaller loads, it is important to ensure that this switch off value is not set to large (too early) to prevent
switching off prematurely.
The triac can of course only be fired before the set switch-off time.
"SwitchOffValue" in the AS I/O configuration.

1/f

Triac
Control signal

Switch-off value
5 to 50%

Data type Value Description

USINT 5 to 50 Switch-off time in %

4.15.15.14.7.3 Configuration of the output channels

Name:
Cfo_OutputConfig
The configuration of the output channels are stored in this register.
"Output type digital/analog" and "Output type full/half wave" in the AS I/O configuration
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Channel 1: Digital / Analog output 0 Output channel 1 is defined as a digital output. The output sta-
tus is defined using bit 0 in the register DigitalOutput 1 - 4
1 Output channel 1 is defined as an analog output. The output
status is defined in the register AnalogOutput01
... ...
3 Channel 4: Digital / Analog output 0 Output channel 4 is defined as a digital output. The output sta-
tus is defined using bit 1 in the register DigitalOutput 1 - 4
1 Output channel 2 is defined as an analog output. The output
status is defined in the register AnalogOutput04
4 Channel 1: Full-wave / half-wave control1) 0 Full-wave control on output channel 1
1 Negative half-wave on output channel 1 is suppressed.
... ...
7 Channel 4: Full-wave / half-wave control1) 0 Full-wave control on output channel 4
1 Negative half-wave on output channel 4 is suppressed.

1) Not available in function model 2 - Frequency mode.

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4.15.15.14.7.4 Switching behavior for zero-crossing errors

Name:
CfO_OutputTolerance
This register can be used to set the switching behavior of the trigger. After the number of zero-crossing errors
configured in Bit 0 to 4, the output is switched off for at least 3 periods. This is followed by synchronization with
the zero signal according to Bit 7.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-4 Trigger for Resync 0 to 30 Number of zero-crossover errors
5-6 Reserved -
7 Fast settling 0 Fast synchronization
1 PLL synchronization

Fast synchronization
With this option, the trigger point is closed-loop controlled after each individual zero-crossover and input jitter.
• Advantage: Increased tolerance and faster response to deviations in mains frequency
• Disadvantage: Increased switch-on jitter for firing signal by zero cross signal ±100 µSec
PLL synchronization
With this option the intervals between zero cross-overs are measured and the PLL frequency is updated accord-
ingly.
• Advantage: Jitter-free firing signal
• Disadvantage: When the output is switched off, additional measurement phases are required before it can
be switched back on.

Information:
This function is available starting with Firmware version 928. This can be installed with hardware ver-
sion 8 and hardware revision B2 or higher.

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4.15.15.14.8 Status of the outputs

Name:
LowCurrentStatus1 through LowCurrentStatus4
ZeroCrossingInput
ZeroCrossingStatus
StatusInput01
The operating status of the outputs is mapped in this register.
In order to do determine the "LowCurrentStatus", the system checks if there is a neutral connection from the output
via the consumer shortly before each triac firing.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits should
be set up individually as data points in the AS I/O mapping ("LowCurrentStatus1" through "ZeroCrossingStatus")
or whether this register should be displayed as an individual USINT data point ("StatusInput01").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 LowCurrentStatus1 0 0 = No current flow on activated output 1
1 No current flow on activated output 1
... ...
3 LowCurrentStatus4 0 Current flow on activated output 4
1 No current flow on activated output 4
4 ZeroCrossingInput 0 Zero cross signal during the negative half-wave
1 Zero cross signal during the positive half-wave
5-6 Reserved -
7 ZeroCrossingStatus 0 Zero cross signal OK
1 Zero cross signal has dropped out

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4.15.15.14.9 "OSP" function model

In the "OSP" function model (Operator Set Predefined), the user defines an analog value or digital pattern. This
OSP value is output as soon as communication between the module and master is interrupted.
Functionality
The user can choose between two OSP modes:
• Retain last valid value
• Replace with static value
In the first case, the module retains the last value as validly recognized output state.
When selecting the mode, "Replace with static value" a plausible output value must be entered in the corresponding
value register. If an OSP event occurs, this value will be output instead of the value currently requested by the task.

4.15.15.14.9.1 Activating the OSP output in the module

Name:
OSPValid
This data point offers the possibility to start module output and request OSP operation during running operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 OSPValid 0 Request OSP operation (after initial start or module in Standby)
1 Request normal operation
1-7 Reserved 0

There is one OSPValid bit on the module, which is managed by the user task. It must be set when the enabled
channels are started. As long as the OSPValid bit remains set in the module, the module behaves the same as
the "Standard" function model.
If an OSP event occurs (e.g. communication between the module and master CPU interrupted) then the OSPValid
bit will be reset on the module. The module enters OSP mode and the output occurs in the "OSPMode" register
according to the configuration.
The following applies:
The OSP replacement value remains even after the communication channel has recovered. OSP mode
is only exited when a set OSPValid bit is transferred.
When the master CPU is restarted, the OSPValid bit is re-initialized on the master CPU. It must once
more be set by the application and transferred via the bus.
When temporary communication errors occur between the module and master CPU (e.g. due to EMC),
a few bus cycles will pass without refreshing the cyclic registers. The OSPValid bit is reset internally in
the module - the bit in the CPU however remains set. Upon the next successful transfer, the OSPValid
bit in the module is set again and the module returns to normal operation.
The ModulOK bit can be evaluated if the task in the master CPU needs to know which output mode the module
is currently in.

Warning!
If the OSPValid bit is reset to "0" on the module, then the output state no longer depends on the
responsible task in the master CPU. However, output still occurs according to the configuration of the
OSP replacement value.

4.15.15.14.9.2 Setting the OSP mode

Name:
CfgOSPMode
This register essentially controls a channel's behavior when OSP is being used.
Data type Value Description
USINT 0 Replace with static value
1 Retain last valid value

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4.15.15.14.9.3 Define the OSP digital output value

Name:
CfgOSPValue
This register contains the digital output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 0 or 1 OSP output value for channel DigitalOutput00
... ...
x 0 or 1 OSP output value for channel DigitalOutput0x

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.15.15.14.9.4 Define the OSP analog output value

Name:
CfgOSPValue01 to CfgOSPValue04
This register contains the analog output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
USINT 0 to 100

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.15.15.14.10 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
All channels 150 μs

4.15.15.14.11 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
All channels 150 μs

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4.15.16 X20DO4649

4.15.16.1 General information

The module is equipped with 4 relay outputs.

• 4 digital outputs
• Relay module for 240 VAC / 30 VDC
• 4 normally open contacts
• Single-channel isolated outputs

Danger!
Risk of electric shock!
The terminal block must only be allowed to conduct voltage when it is inserted. It must not under any
circumstances be removed or inserted when voltage is applied or have voltage applied to it when it
is removed.

4.15.16.2 Order data

Model number Short description Figure

Digital output modules
X20DO4649 X20 digital output module, 4 relays, N.O. contacts, 240 VAC / 5 A
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 377: X20DO4649 - Order data

4.15.16.3 Technical data

Product ID X20DO4649
Brief description
I/O module 4 digital outputs 30 VDC / 240 VAC, outputs are single-channel isolated
General information
B&R ID code 0xA704
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, using status LED
Power consumption
Bus 0.8 W
Internal I/O -
Additional power dissipation caused by the actua- +1.5
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital outputs
Design Relay / Normally open contact
Channels are single-channel isolated
Nominal voltage 30 VDC / 240 VAC

Table 378: X20DO4649 - Technical data

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Product ID X20DO4649
Switching voltage Max. 110 VDC / 250 VAC
Rated frequency DC / 45 to 63 Hz
Nominal output current 5.0 A at 30 VDC / 5.0 A at 240 VAC
Total nominal current 10.0 A at 30 VDC / 10.0 A at 240 VAC
Actuator supply External
Contact resistance 15 mΩ at 6 VDC / 1A
Switching delay
0 -> 1 ≤10 ms
1 -> 0 ≤10 ms
Isolation voltage
Contact - Contact Tested at 750 VAC
Contact - Coil Tested at 2300 VAC
Service life
Electrical 2) Min. 5 x 104 ops. (NO) at 5 A
Mechanical Min. 2 x 107 ops
Switching capacity
Minimum 0.05 W / 2.4 VA
Maximum 150 W / 1250 VA
Protective circuit
Internal None
External
AC RC combination or VDR
DC Inverse diode, RC combination or VDR
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating When operated at temperatures above 55°C, the maximum current
per channel is reduced to 4 A and the maximum total current to 8 A.
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 378: X20DO4649 - Technical data

1) Number of outputs x Contact resistance x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the
module.)
2) With a resistive load. See also section "Electrical service life"

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4.15.16.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
On Error or reset status
e+r Red on / Green single flash Invalid firmware
1-4 Orange Output status of the corresponding digital output

Table 379: Status LEDs

4.15.16.5 Pinout

For easy wiring, 4 auxiliary contacts are available on the module starting with revision E0. They are connected
together internally and can be loaded with a total of 10 A (see also section "Connection example").

r e

X20 DO 4649
1
2
3
4

NO 1 COM 1

NO 2 COM 2

NO 3 COM 3

NO 4 COM 4

AUX AUX

AUX AUX

Figure 352: Pinout

4.15.16.6 Connection example

DO

240 VAC

+24 VDC +24 VDC

GND GND

Figure 353: Connection example

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4.15.16.7 Output circuit diagram

COM x

NO x

Output status
AUX
AUX
AUX
I/O status
AUX
LED (orange)

Figure 354: Output circuit diagram

4.15.16.8 Electrical service life

Electrical service life

5000
3000
2000
Switching operations (x10³)

DC 30 V / AC 250 V resistive
1000
DC 30 V τ = 7 ms
500
300
200

100

50
AC 250 V cosφ = 0.4
30
20

10
0.1 0.2 0.3 0.5 1 2 3 5 10

Switching current [A]

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4.15.16.9 Register description

4.15.16.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.16.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 4 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput04 Bit 3

1) The offset specifies where the register is within the CAN object.

4.15.16.9.3 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.16.9.3.1 Switching state of digital outputs 1 to 4

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput04
The switching state of digital outputs 1 to 4 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 15 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
3 DigitalOutput04 0 Digital output 04 reset
1 Digital output 04 set

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4.15.16.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.16.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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4.15.17 X20DO6321

4.15.17.1 General information

The module is equipped with 6 outputs for 1 or 2-wire connections. The X20 6-pin terminal block can be used
for universal 1-line wiring. 2-line wiring can be implemented using the 12-pin terminal block. The X20DO6321 is
designed for sink output wiring.
• 6 digital outputs
• Sink connection
• 2-wire connections
• 24 VDC for signal supply
• Integrated output protection
• 1-wire connection type with 6-pin terminal block

4.15.17.2 Order data

Model number Short description Figure

Digital output modules
X20DO6321 X20 digital output module, 6 outputs, 24 VDC, 0.5 A, sink, 2-wire
connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 380: X20DO6321 - Order data

4.15.17.3 Technical data

Product ID X20DO6321
Brief description
I/O module 6 digital outputs 24 VDC for 1- or 2-wire connections
General information
B&R ID code 0x1B99
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, with status LED and software status (output error status)
Power consumption
Bus 0.2 W
Internal I/O 0.59 W
Additional power dissipation caused by the actua- +0.18
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital outputs
Design FET negative switching
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.5 A
Total nominal current 3.0 A
Connection type 1- or 2-wire connections

Table 381: X20DO6321 - Technical data

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Product ID X20DO6321
Output circuit Sink
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 75 µA
RDS(on) 120 mΩ
Peak short circuit current <7 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay
0 -> 1 <300 µs
1 -> 0 <300 µs
Switching frequency
Resistive load Max. 500 Hz
Braking voltage when switching off inductive loads Typ. 50 VDC
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 381: X20DO6321 - Technical data

1) Number of outputs x RDS(on) x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the module.)

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4.15.17.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
e+r Red on / Green single flash Invalid firmware
1-6 Orange Output status of the corresponding digital output

Table 382: Status LEDs

4.15.17.5 Pinout

r e

X20 DO 6321
1 2
3 4
5 6

DO 1 DO 2

DO 3 DO 4

DO 5 DO 6

+24 VDC +24 VDC

+24 VDC +24 VDC

+24 VDC +24 VDC

Figure 355: Pinout

4.15.17.6 Connection example

DO

Actuator 1 Actuator 2

Actuator 3 Actuator 4

Actuator 5 Actuator 6

+24 VDC +24 VDC

GND GND

Figure 356: Connection example

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4.15.17.7 Output circuit diagram

24 V

I/O status
LED (orange)
Low-side
Output status Output x
Logic

VDR
GND
Output
monitoring GND

24 V
GND
24 V

Figure 357: Output circuit diagram

4.15.17.8 Switching inductive loads

Environmental temperature: 60°C, all outputs with the same load

100 H 10 H
1000
Switching voltage:

28.8 V
1H
24.0 V

Coil resistance Coil inductance

[Ω] 100 mH

100

10 mH
50
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.17.9 Register description

4.15.17.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput06 Bit 5
30 1 StatusInput01 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput06 Bit 5

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.17.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 6 USINT ●
DigitalOutput01 Bit 0
...
DigitalOutput06 Bit 5
30 - Status of digital outputs 1 to 6 USINT ●
StatusDigitalOutput01 Bit 0
...
StatusDigitalOutput06 Bit 5

1) The offset specifies where the register is within the CAN object.

4.15.17.9.3 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.17.9.3.1 Switching state of digital outputs 1 to 6

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput06
The switching state of digital outputs 1 to 6 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 63 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
5 DigitalOutput06 0 Digital output 06 reset
1 Digital output 06 set

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4.15.17.9.4 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

4.15.17.9.4.1 Status of digital outputs 1 to 6

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput06
The status of digital outputs 1 to 6 is mapped in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through
"StatusDigitalOutput0x") or whether this register should be displayed as an individual USINT data point
("StatusInput01").
Data type Value Information
USINT 0 to 63 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
... ...
5 StatusDigitalOutput06 0 Channel 06: No error
1 Channel 06: Short circuit or overload

4.15.17.9.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.17.9.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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4.15.18 X20DO6322

4.15.18.1 General information

The module is equipped with 6 outputs for 1 or 2-wire connections. The X20 6-pin terminal block can be used for
universal 1-line wiring. 2-line wiring can be implemented using the 12-pin terminal block. The module is designed
for source output wiring.
• 6 digital outputs
• Source connection
• 2-wire connections
• GND for signal supply
• Integrated output protection
• 1-wire connection type with 6-pin terminal block
• OSP mode

4.15.18.2 Order data

Model number Short description Figure

Digital output modules
X20DO6322 X20 digital output module, 6 outputs, 24 VDC, 0.5 A, source, 2-
wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 383: X20DO6322 - Order data

4.15.18.3 Technical data

Product ID X20DO6322
Brief description
I/O module 6 digital outputs 24 VDC for 1- or 2-wire connections
General information
B&R ID code 0x1B98
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, with status LED and software status (output error status)
Power consumption
Bus 0.18 W
Internal I/O 0.71 W
Additional power dissipation caused by the actua- +0.31
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital outputs
Design FET positive switching
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.5 A

Table 384: X20DO6322 - Technical data

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Product ID X20DO6322
Total nominal current 3.0 A
Connection type 1- or 2-wire connections
Output circuit Source
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 5 µA
RDS(on) 210 mΩ
Max. continuous current 6.0 A
Peak short circuit current <12 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay 2)
0 -> 1 <300 µs
1 -> 0 <300 µs
Switching frequency
Resistive load 2) Max. 500 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Typ. 50 VDC
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 384: X20DO6322 - Technical data

1) Number of outputs x RDS(on) x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the module.)
2) At loads ≤ 1 kΩ

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4.15.18.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
Flickering (ap- Module is in OSP state
prox. 10 Hz)
e Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
e+r Red on / Green single flash Invalid firmware
1-6 Orange Output status of the corresponding digital output

Table 385: Status LEDs

4.15.18.5 Pinout

r e

X20 DO 6322
1 2
3 4
5 6

DO 1 DO 2

DO 3 DO 4

DO 5 DO 6

GND GND

GND GND

GND GND

Figure 358: Pinout

4.15.18.6 Connection example

DO

Actuator 1 Actuator 2

Actuator 3 Actuator 4

Actuator 5 Actuator 6

+24 VDC +24 VDC

GND GND

Figure 359: Connection example

Caution!
If the module is operated outside of specifications, the output current can increase above the maximum
permissible nominal current. This applies to individual channels and also to the summation current
for the module.
Therefore sufficient cable cross sections or external safety measures must be used.

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4.15.18.7 OSP hardware requirements

In order to best use OSP mode, make sure when creating the application that the output module and CPU have
separate power supplies.

4.15.18.8 Output circuit diagram

24 V

High-side
Output status
Logic
Output x

GND

I/O status
Output LED (orange)
monitoring

GND
GND

Figure 360: Output circuit diagram

4.15.18.9 Switching inductive loads

Environmental temperature: 60°C, all outputs with the same load

100 H 10 H
1000
Switching voltage:
1H
28.8 V
24.0 V

100 mH
Coil resistance Coil inductance
[Ω]

100
10 mH

50
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.18.10 Register description

4.15.18.10.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput06 Bit 5
30 1 StatusInput01 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput06 Bit 5

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.18.10.2 Function model 1 - OSP

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 6 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput06 Bit 5
30 1 Status of digital outputs 1 to 6 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput06 Bit 5
34 1 Activating the OSP output in the module USINT ●
OSPValid Bit 0
32 - CfgOSPMode USINT ●
36 - CfgOSPValue USINT ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.18.10.3 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 6 USINT ●
DigitalOutput01 Bit 0
...
DigitalOutput06 Bit 5
30 - Status of digital outputs 1 to 6 USINT ●
StatusDigitalOutput01 Bit 0
...
StatusDigitalOutput06 Bit 5

1) The offset specifies where the register is within the CAN object.

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4.15.18.10.4 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.18.10.4.1 Switching state of digital outputs 1 to 6

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput06
The switching state of digital outputs 1 to 6 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 63 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
5 DigitalOutput06 0 Digital output 06 reset
1 Digital output 06 set

4.15.18.10.5 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

4.15.18.10.5.1 Status of digital outputs 1 to 6

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput06
The status of digital outputs 1 to 6 is mapped in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through
"StatusDigitalOutput0x") or whether this register should be displayed as an individual USINT data point
("StatusInput01").
Data type Value Information
USINT 0 to 63 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
... ...
5 StatusDigitalOutput06 0 Channel 06: No error
1 Channel 06: Short circuit or overload

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4.15.18.10.6 "OSP" function model

In the "OSP" function model (Operator Set Predefined), the user defines an analog value or digital pattern. This
OSP value is output as soon as communication between the module and master is interrupted.
Functionality
The user can choose between two OSP modes:
• Retain last valid value
• Replace with static value
In the first case, the module retains the last value as validly recognized output state.
When selecting the mode, "Replace with static value" a plausible output value must be entered in the corresponding
value register. If an OSP event occurs, this value will be output instead of the value currently requested by the task.

4.15.18.10.6.1 Activating the OSP output in the module

Name:
OSPValid
This data point offers the possibility to start module output and request OSP operation during running operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Request OSP operation (after initial start or module in Standby)
0 OSPValid
1 Request normal operation
1-7 0 Reserved

There is one OSPValid bit on the module, which is managed by the user task. It must be set when the enabled
channels are started. As long as the OSPValid bit remains set in the module, the module behaves the same as
the "Standard" function model.
If an OSP event occurs (e.g. communication between the module and master CPU interrupted) then the OSPValid
bit will be reset on the module. The module enters OSP mode and the output occurs in the "OSPMode" register
according to the configuration.
The following applies:
The OSP replacement value remains even after the communication channel has recovered. OSP mode
is only exited when a set OSPValid bit is transferred.
When the master CPU is restarted, the OSPValid bit is re-initialized on the master CPU. It must once
more be set by the application and transferred via the bus.
When temporary communication errors occur between the module and master CPU (e.g. due to EMC),
a few bus cycles will pass without refreshing the cyclic registers. The OSPValid bit is reset internally in
the module - the bit in the CPU however remains set. Upon the next successful transfer, the OSPValid
bit in the module is set again and the module returns to normal operation.
The ModulOK bit can be evaluated if the task in the master CPU needs to know which output mode the module
is currently in.

Warning!
If the OSPValid bit is reset to "0" on the module, then the output state no longer depends on the
responsible task in the master CPU. However, output still occurs according to the configuration of the
OSP replacement value.

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4.15.18.10.6.2 Setting the OSP mode

Name:
CfgOSPMode
This register essentially controls a channel's behavior when OSP is being used.
Data type Value Description
USINT 0 Replace with static value
1 Retain last valid value

4.15.18.10.6.3 Define the OSP digital output value

Name:
CfgOSPValue
This register contains the digital output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 0 or 1 OSP output value for channel DigitalOutput00
... ...
x 0 or 1 OSP output value for channel DigitalOutput0x

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.15.18.10.7 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.18.10.8 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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4.15.19 X20DO6325

4.15.19.1 General information

The module is equipped with six outputs for 1 or 2-wire connections with diagnostic functions. The X20 6-pin
terminal block can be used for universal 1-line wiring. Two-line wiring can be implemented using the 12-pin terminal
block. The outputs on the module are designed for source connections.
• 6 digital outputs
• Source connection
• 2-wire connections
• GND for signal supply
• Integrated output protection
• 1-wire connection type with 6-pin terminal block
• Diagnostic functions (open line, short circuit and overload/overtemperature)
• OSP mode

4.15.19.2 Order data

Model number Short description Figure

X20DO6325 X20 digital output module, 6 outputs, 24 VDC, 0.5 A, source,

open line and overload detection, 2-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 386: X20DO6325 - Order data

4.15.19.3 Technical data

Product ID X20DO6325
Brief description
I/O module 6 digital outputs 24 VDC for 1- or 2-wire connections with a diagnostics function
General information
B&R ID code 0xE284
Status indicators I/O function by channel, diagnostics by channel, operating status, module status
Diagnostics
Module run/error Yes, using status LED and software
Status - Outputs Yes, using status LED and software
Diagnostics - Outputs Yes, using status LED and software
Power consumption
Bus 0.15 W
Internal I/O 0.4 W
Additional power dissipation caused by the actua- Max. 0.225 W
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
GOST-R In preparation
Digital outputs
Design FET positive switching
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.5 A
Total nominal current 3.0 A
Connection type 1- or 2-wire connections
Output circuit Source

Table 387: X20DO6325 - Technical data

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 X20 system modules • Digital output modules • X20DO6325
Product ID X20DO6325
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching inductive loads (see section "Switching inductive loads")
Diagnostic status
Open line Current is <1 mA (typ.): Detected if the output is OFF, delay approx. 10 ms
Short circuit to 24 VDC Detected if the output is OFF, delay approx. 10 ms
Short circuit to GND Detected if the output is ON, delay approx. 10 ms
Overload/overtemperature Detected if the output is ON, delay approx. 10 ms
Leakage current when switched off <160 μA
RDS(on) 150 mΩ
Peak short circuit current <40 A
Switching on after overload or short circuit cutoff Depends on the module temperature
Switching delay 2)
0 -> 1 <100 μs
1 -> 0 <300 μs
Switching frequency
Resistive load 2) Max. 2000 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads 45 to 52 VDC
Isolation voltage between channel and bus 510 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 387: X20DO6325 - Technical data

1) Number of outputs x RDS(on) x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the module.)
2) At loads ≤ 1 kΩ

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4.15.19.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash RESET mode
Blinking PREOPERATIONAL mode
On RUN mode
Flickering Module is in OSP mode
(approx. 10 Hz)
e Red Off No power to module or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
Double flash I/O supply is outside valid range.
e+r Red on / Green single flash Invalid firmware
Channel 1 - 6 Orange Output status of the corresponding digital output
Diagnostics 1 - Red Monitoring of the corresponding digital output was tripped (short circuit, open line
6 or overload)

Table 388: LED status indicators

4.15.19.5 Pinout

r e
X20 DO 6325

1 2
3 4
5 6
1 2
3 4
5 6

DO 1 DO 2

DO 3 DO 4

DO 5 DO 6

GND GND

GND GND

GND GND

Figure 361: Pinout

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4.15.19.6 Connection example

DO

Actuator 1 Actuator 2

Actuator 3 Actuator 4

Actuator 5 Actuator 6

+24 VDC +24 VDC

GND GND

Figure 362: Connection example

Caution!
If the module is operated outside of specifications, the output current can increase above the maximum
permissible nominal current. This applies to individual channels and also to the summation current
for the module.
Therefore sufficient cable cross sections or external safety measures must be used.

4.15.19.7 OSP hardware requirements

In order to best use OSP mode, make sure when creating the application that the output module and CPU have
separate power supplies.

4.15.19.8 Output circuit diagram

24 V

High-side 200 kOhm for open line monitoring

Output status
Logic
Output x

GND
I/O status
Output LED (orange)
monitoring

GND

Figure 363: Output circuit diagram

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4.15.19.9 Open line detection

Each output is equipped with an internal 200 kOhm resistor to 24 V for open line detection.
If the charging resistance at the terminal is greater than 25 to 100 kOhm (tolerance range) an open line is therefore
detected at 24 V. When switched on, this corresponds to a current of 0.2 to 1 mA with all tolerances taken into
consideration.
Supply voltage Min. load Max. load Corresponds to load current when ON
24 V 100 kOhm 25 kOhm 0.2 to 1 mA

4.15.19.10 Switching inductive loads

Environmental temperature: 60°C, all outputs with the same load

100 H 10 H 1H 100 mH 10 mH
1000

Coil resistance Coil inductance

[Ω]

100
Switching voltage:
28.8 V
24.0 V
10
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.19.11 Register description

4.15.19.11.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
2 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput06 Bit 5
4 CfgBwStatus USINT ●
28 StatusInput01 USINT ●
DigitalStatusGnd01 Bit 0
... ...
DigitalStatusGnd06 Bit 5
29 StatusInput02 USINT ●
DigitalStatusVcc01 Bit 0
... ...
DigitalStatusVcc06 Bit 5
30 StatusInput03 USINT ●
DigitalStatusBw01 Bit 0
... ...
DigitalStatusBw06 Bit 5
31 StatusInput04 USINT ●
DigitalStatusSum01 Bit 0
... ...
DigitalStatusSum06 Bit 5
PowerSupply01 Bit 7

4.15.19.11.2 Function model 1 - OSP

Register Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
2 Switching state of digital outputs 1 to 6 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput06 Bit 5
4 CfgBwStatus USINT ●
28 Short circuit to GND and overtemperature USINT ●
DigitalStatusGnd01 Bit 0
... ...
DigitalStatusGnd06 Bit 5
29 Short circuit to voltage USINT ●
DigitalStatusVcc01 Bit 0
... ...
DigitalStatusVcc06 Bit 5
30 Open line USINT ●
DigitalStatusBw01 Bit 0
... ...
DigitalStatusBw06 Bit 5
31 Cumulative status USINT ●
DigitalStatusSum01 Bit 0
... ...
DigitalStatusSum06 Bit 5
PowerSupply01 Bit 7
34 Activating the OSP output in the module USINT ●
OSPValid Bit 0
32 CfgOSPMode USINT ●
36 CfgOSPValue USINT ●

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4.15.19.11.3 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Non-cyclic Cyclic Non-cyclic
2 2 Switching state of digital outputs 1 to 6 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput06 Bit 5
4 4 CfgBwStatus USINT ●
28 28 Short circuit to GND and overtemperature USINT ●
DigitalStatusGnd01 Bit 0
... ...
DigitalStatusGnd06 Bit 5
29 29 Short circuit to voltage USINT ●
DigitalStatusVcc01 Bit 0
... ...
DigitalStatusVcc06 Bit 5
30 30 Open line USINT ●
DigitalStatusBw01 Bit 0
... ...
DigitalStatusBw06 Bit 5
31 31 Cumulative status USINT ●
DigitalStatusSum01 Bit 0
... ...
DigitalStatusSum06 Bit 5
PowerSupply01 Bit 7

1) The offset specifies the position of the register within the CAN object.

4.15.19.11.4 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.19.11.4.1 Switching state of digital outputs 1 to 6

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput06
The switching state of digital outputs 1 to 6 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 63 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
5 DigitalOutput06 0 Digital output 06 reset
1 Digital output 06 set

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4.15.19.11.5 Digital output status

The status of the outputs is checked every 4 ms. To suppress disturbances on the feedback inputs, two readings
are compared.
The hardware diagnostics recognize the following states:
• Short circuit to ground GND (when output is ON)
• Short circuit to 24 VDC (when output is OFF)
• Open line (when output is OFF)
• Overtemperature / overload
The error is logged in the corresponding status registers and in the cumulative status register.
An open line error is also indicated by the corresponding LED. The LED indicator can be disabled so that an open
(unused) channel does not constantly indicate an error.

4.15.19.11.5.1 Enabling the status LED

Name:
CfgBwStatus
For each output there is a corresponding enable bit. In this register, the bit can be set to define whether or not the
status LED should be used to indicate an open line error. This allows the LED to be disabled for unused channels.
In the bus controller function model the default value is 0xBF.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Channel 01 0 Open line indicator 01 disabled
1 Open line indicator 01 enabled
... ...
5 Channel 06 0 Open line indicator 06 disabled
1 Open line indicator 06 enabled
6 Reserved 0
7 PowerSupply01 0 No error status indicators
1 Monitor supply voltage

4.15.19.11.5.2 Short circuit to GND and overtemperature

Name:
StatusInput01
DigitalStatusGnd01 to DigitalStatusGnd06
In this register, a short circuit or overtemperature error can be indicated by setting the corresponding channel bit.
It is not possible to differentiate between short circuit to GND and overload/overtemperature.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits should
be set up individually as data points in the AS I/O mapping ("DigitalStatusGnd01" through "DigitalStatusGnd06")
or whether this register should be displayed as an individual USINT data point ("StatusInput01").
Data type Value Information
USINT 0 to 63 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalStatusGnd01 0 No error
1 Channel 1: Short circuit or overload
... ...
5 DigitalStatusGnd06 0 No error
1 Channel 6: Short circuit or overload
6-7 Reserved 0

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4.15.19.11.5.3 Short circuit to voltage

Name:
StatusInput02
DigitalStatusVcc01 to DigitalStatusVcc06
In this register, a short circuit can be indicated by setting the corresponding channel bit.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits should
be set up individually as data points in the AS I/O mapping ("DigitalStatusVcc01" through "DigitalStatusVcc06") or
whether this register should be displayed as an individual USINT data point ("StatusInput02").
Data type Value Information
USINT 0 to 63 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalStatusVcc01 0 No error
1 Channel 1: Short circuit to voltage
... ...
5 DigitalStatusVcc06 0 No error
1 Channel 6: Short circuit to voltage
6-7 Reserved 0

4.15.19.11.5.4 Open line

Name:
StatusInput03
DigitalStatusBw01 to DigitalStatusBw06
In this register, an open line can be indicated by setting the corresponding channel bit.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits should
be set up individually as data points in the AS I/O mapping ("DigitalStatusBw01" through "DigitalStatusBw06") or
whether this register should be displayed as an individual USINT data point ("StatusInput03").
Data type Value Information
USINT 0 to 63 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalStatusBw01 0 No error
1 Channel 1: Open line
... ...
5 DigitalStatusBw06 0 No error
1 Channel 6: Open line
6-7 Reserved 0

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4.15.19.11.5.5 Cumulative status

Name:
StatusInput04
DigitalStatusSum01 to DigitalStatusSum06
PowerSupply01
Every error found in the other status registers is also shown in this register. This provides an easy way to check
whether any errors have occurred.
If the I/O supply fails, Bit 7 is set and all status bits in the other status registers are reset to 0.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits should
be set up individually as data points ("DigitalStatusSum01 through DigitalStatusSum06","PowerSupply01") in the
AS I/O mapping or whether this register should be displayed as an individual USINT data point ("StatusInput04").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalStatusSum01 0 No error
1 Channel 1: Error occurred
... ...
5 DigitalStatusSum06 0 No error
1 Channel 6: Error occurred
6 Reserved 0
7 PowerSupply01 0 No error
1 Pending supply voltage error

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4.15.19.11.6 "OSP" function model

In the "OSP" function model (Operator Set Predefined), the user defines an analog value or digital pattern. This
OSP value is output as soon as communication between the module and master is interrupted.
Functionality
The user can choose between two OSP modes:
• Retain last valid value
• Replace with static value
In the first case, the module retains the last value as validly recognized output state.
When selecting the mode, "Replace with static value" a plausible output value must be entered in the corresponding
value register. If an OSP event occurs, this value will be output instead of the value currently requested by the task.

4.15.19.11.6.1 Activating the OSP output in the module

Name:
OSPValid
This data point offers the possibility to start module output and request OSP operation during running operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Request OSP operation (after initial start or module in Standby)
0 OSPValid
1 Request normal operation
1-7 0 Reserved

There is one OSPValid bit on the module, which is managed by the user task. It must be set when the enabled
channels are started. As long as the OSPValid bit remains set in the module, the module behaves the same as
the "Standard" function model.
If an OSP event occurs (e.g. communication between the module and master CPU interrupted) then the OSPValid
bit will be reset on the module. The module enters OSP mode and the output occurs in the "OSPMode" register
according to the configuration.
The following applies:
The OSP replacement value remains even after the communication channel has recovered. OSP mode
is only exited when a set OSPValid bit is transferred.
When the master CPU is restarted, the OSPValid bit is re-initialized on the master CPU. It must once
more be set by the application and transferred via the bus.
When temporary communication errors occur between the module and master CPU (e.g. due to EMC),
a few bus cycles will pass without refreshing the cyclic registers. The OSPValid bit is reset internally in
the module - the bit in the CPU however remains set. Upon the next successful transfer, the OSPValid
bit in the module is set again and the module returns to normal operation.
The ModulOK bit can be evaluated if the task in the master CPU needs to know which output mode the module
is currently in.

Warning!
If the OSPValid bit is reset to "0" on the module, then the output state no longer depends on the
responsible task in the master CPU. However, output still occurs according to the configuration of the
OSP replacement value.

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4.15.19.11.6.2 Setting the OSP mode

Name:
CfgOSPMode
This register essentially controls a channel's behavior when OSP is being used.
Data type Value Description
USINT 0 Replace with static value
1 Retain last valid value

4.15.19.11.6.3 Define the OSP digital output value

Name:
CfgOSPValue
This register contains the digital output value, which is output in "Replace with static value" mode during OSP
operation.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 0 or 1 OSP output value for channel DigitalOutput00
... ...
x 0 or 1 OSP output value for channel DigitalOutput0x

Warning!
The "OSPValue" is not accepted by the module until the "OSPValid" bit has been set in the module.

4.15.19.11.7 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
150 μs

4.15.19.11.8 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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4.15.20 X20DO6529

4.15.20.1 General information

The module is equipped with 6 relay outputs.

• 6 digital outputs
• Relay module for 115 VAC
• 6 normally open contacts
• Single-channel isolated outputs

Danger!
Risk of electric shock!
The terminal block must only be allowed to conduct voltage when it is inserted. It must not under any
circumstances be removed or inserted when voltage is applied or have voltage applied to it when it
is removed.

4.15.20.2 Order data

Model number Short description Figure

Digital output modules
X20DO6529 X20 digital output module, 6 relays, normally open contacts, 115
VAC / 0.5 A, 30 VDC / 1 A
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 389: X20DO6529 - Order data

4.15.20.3 Technical data

Product ID X20DO6529
Brief description
I/O module 6 digital outputs 30 VDC / 115 VAC, outputs are single-channel isolated
General information
B&R ID code 0x2019
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, using status LED
Power consumption
Bus 1.1 W
Internal I/O -
Additional power dissipation caused by the actua- +0.45
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel Yes
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital outputs
Design Relay / Normally open contact
Channels are single-channel isolated

Table 390: X20DO6529 - Technical data

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Product ID X20DO6529
Nominal voltage 30 VDC / 115 VAC
Switching voltage Max. 110 VDC / 125 VAC
Rated frequency DC / 45 to 63 Hz
Nominal output current 1.0 A at 30 VDC / 0.5 A at 115 VAC
Total nominal current 6.0 A at 30 VDC / 3.0 A at 115 VAC
Actuator supply External
Starting current Max. 2 A (per channel)
Contact resistance 75 mΩ at 6 VDC / 1A
Switching delay
0 -> 1 ≤4 ms
1 -> 0 ≤4 ms
Isolation voltage
Contact - Contact Tested at 1000 VAC
Contact - Coil Tested at 1500 VAC
Service life
Electrical 2) Min. 100 x 10³ ops.
Mechanical Min. 50 x 106 ops. (3 Hz)
Switching capacity
Minimum 0.01 mA / 10 mV DC
Maximum 30 W / 62.5 VA
Protective circuit
Internal None
External
AC RC combination or VDR
DC Inverse diode, RC combination or VDR
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 390: X20DO6529 - Technical data

1) Number of outputs x Contact resistance x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the
module.)
2) With a resistive load. See also section "Electrical service life"

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4.15.20.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
On Error or reset status
e+r Red on / Green single flash Invalid firmware
1-6 Orange Output status of the corresponding digital output

Table 391: Status LEDs

4.15.20.5 Pinout

r e

X20 DO 6529
1 2
3 4
5 6

NO 1 NO 2

COM 1 COM 2

NO 3 NO 4

COM 3 COM 4

NO 5 NO 6

COM 5 COM 6

Figure 364: Pinout

4.15.20.6 Connection example

DO

115 VAC 24 VDC

+24 VDC +24 VDC

GND GND

Figure 365: Connection example

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4.15.20.7 Output circuit diagram

NO x

COM x

Output status

I/O status
LED (orange)

Figure 366: Output circuit diagram

4.15.20.8 Maximum switching power

Maximum switching power

2
AC resistive
Switching current [A]

0.5
DC resistive
0.3

0.2

0.1
1 2 5 10 20 30 50 100 200

Switching voltage [V]

Figure 367: Maximum switching power

4.15.20.9 Electrical service life

Electrical service life

100
Switching operations (x10⁴)

70
50
40
30
30 VD
C
re
si s
20
12

t iv
e
5V
DC
re

10
si s
t iv
e

0 0.2 0.4 0.6 0.8 1.0 1.2

Switching current [A]

Figure 368: Electrical service life

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4.15.20.10 Register description

4.15.20.10.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput06 Bit 5

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.20.10.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 6 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput06 Bit 5

1) The offset specifies where the register is within the CAN object.

4.15.20.10.3 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.20.10.3.1 Switching state of digital outputs 1 to 6

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput06
The switching state of digital outputs 1 to 6 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 63 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
5 DigitalOutput06 0 Digital output 06 reset
1 Digital output 06 set

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4.15.20.10.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.20.10.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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4.15.21 X20DO6639

4.15.21.1 General information

The module is equipped with 6 relay outputs.

• 6 digital outputs
• Relay module for 240 VAC / 30 VDC
• Switching current 2 A
• 6 normally open contacts
• Single-channel isolated outputs

Danger!
Risk of electric shock!
The terminal block must only be allowed to conduct voltage when it is inserted. It must not under any
circumstances be removed or inserted when voltage is applied or have voltage applied to it when it
is removed.

4.15.21.2 Order data

Model number Short description Figure

Digital output modules
X20DO6639 X20 digital output module, 6 relays, normally open contacts, 240
VAC / 2 A, 30 VDC / 2 A
Erforderliches Zubehör
Bus modules
X20BM12 X20 bus module, 240 V keyed, internal I/O supply continuous
Terminal blocks
X20TB32 X20 terminal block, 12-pin, 240 VAC keyed

Table 392: X20DO6639 - Order data

4.15.21.3 Technical data

Product ID X20DO6639
Short description
I/O module 6 digital outputs 30 VDC / 240 VAC, outputs are single-channel isolated
General information
B&R ID code 0xDF50
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED
Outputs Yes, using status LED
Power consumption
Bus 1W
Internal I/O -
Additional power dissipation caused by the actua- +0.36
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel -
Certification
CE Yes
ATEX Zone 2 Yes
GOST-R Yes
Digital outputs
Nominal voltage 30 VDC / 240 VAC
Switching voltage max. 110 VDC / 250 VAC
Rated frequency DC / 45 to 63 Hz
Nominal output current 2 A at 30 VDC / 2 A at 240 VAC
Total nominal current 10 A at 30 VDC / 10 A at 240 VAC

Table 393: X20DO6639 - Technical data

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 X20 system modules • Digital output modules • X20DO6639
Product ID X20DO6639
Design Relay / N.O.
Channels are single-channel isolated
Actuator supply External
Contact resistance 15 mΩ at 6 VDC / 1A
Switching delay
0 -> 1 ≤10 ms
1 -> 0 ≤10 ms
Isolation voltage
Contact - Contact Tested at 750 VAC
Contact - Coil Tested at 2300 VAC
Service life
Electrical 2) Min. 120 x 103 ops. (at 2 A / 240 VAC)
Mechanical Min. 2 x 107 ops
Switching capacity
Minimum 0.05 W DC / 2.4 W AC
Maximum 60 W DC / 480 W AC
Total power of all channels
AC 3000 W
DC 360 W
Protective circuit
Internal None
External
AC RC combination or VDR
DC Inverse diode, RC combination or VDR
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB32 terminal block separately,
Order 1x X20BM12 bus module separately
Spacing 12.5 +0.2 mm

Table 393: X20DO6639 - Technical data

1) Number of outputs x Contact resistance x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the
module.)
2) With a resistive load. See also section "Electrical service life"

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4.15.21.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
On Error or reset status
e+r Red on / Green single flash Invalid firmware
1-6 Orange Output status of the corresponding digital output

Table 394: Status LEDs

4.15.21.5 Pinout

r e

X20 DO 6639
1
2
3
4
5
6

NO 1 COM 1

NO 2 COM 2

NO 3 COM 3

NO 4 COM 4

NO 5 COM 5

NO 6 COM 6

Figure 369: Pinout

4.15.21.6 Connection example

DO

240 VAC

+24 VDC +24 VDC

GND GND

Figure 370: Connection example

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 X20 system modules • Digital output modules • X20DO6639

4.15.21.7 Output circuit diagram

COM x

NO x

Output status

I/O status
LED (orange)

Figure 371: Output circuit diagram

4.15.21.8 Electrical service life

Electrical service life

5000
3000
2000
DC 30 V / AC 250 V resistive
Switching operations (x10³)

1000
DC 30 V τ = 7 ms
500
300
200

100

50
AC 250 V cosφ = 0.4
30
20

10
0.1 0.2 0.3 0.5 1 2 3 5

Switching current [A]

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4.15.21.9 Register description

4.15.21.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput06 Bit 5

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.21.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 6 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput06 Bit 5

1) The offset specifies where the register is within the CAN object.

4.15.21.9.3 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.21.9.3.1 Switching state of digital outputs 1 to 6

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput06
The switching state of digital outputs 1 to 6 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 63 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
5 DigitalOutput06 0 Digital output 06 reset
1 Digital output 06 set

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4.15.21.9.4 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.21.9.5 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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4.15.22 X20DO8232

4.15.22.1 General information

The module is equipped with 8 outputs for 1-wire connections. The nominal output current is 2 A and the nominal
voltage is 12 VDC.
The output supply is fed directly to the module. An additional supply module is not needed. There is no connection
between the module and the I/O supply potential on the bus module.
• 8 digital outputs with 2 A
• Rated voltage 12 VDC
• Source connection
• 1-wire connection
• Power feed integrated in the module
• Integrated output protection

4.15.22.2 Order data

Model number Short description Figure

Digital output modules
X20DO8232 X20 digital output module, 8 outputs, 12 VDC, 2.0 A, source,
supply directly on module, 1 wire technology
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 395: X20DO8232 - Order data

4.15.22.3 Technical data

Product ID X20DO8232
Brief description
I/O module Eight 12 VDC digital outputs for 1-wire connections
General information
B&R ID code 0xA4AD
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software status
Outputs Yes, with status LED and software status (output error status)
Supply voltage monitoring Yes, with software status
Power consumption
Bus 0.22 W
Internal I/O -
External I/O 0.82 W
Additional power dissipation caused by the actua- +4.48
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital outputs
Design FET positive switching
Nominal voltage 12 VDC

Table 396: X20DO8232 - Technical data

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Product ID X20DO8232
Switching voltage 12 VDC (-15% / +20%)
Nominal output current 2.0 A
Total nominal current 8.0 A
Connection type 1-wire connections
Output circuit Source
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")
Reverse polarity protection for supply voltage
Actuator supply
Feed External
Fuse Required line fuse max. 10 A (slow blow)
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 5 μA
RDS(on) 140 mΩ
Max. continuous current 8.0 A
Peak short circuit current <12 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay 2)
0 -> 1 <300 μs
1 -> 0 <300 μs
Switching frequency
Resistive load 2) Max. 500 Hz; 600 Hz with max. 250 mA load
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Type 50 VDC
Isolation voltage between channel and bus 500 Veff
Additional functions To increase the output current, outputs can be switched in parallel
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0,5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5+0.2 mm

Table 396: X20DO8232 - Technical data

1) Number of outputs x RDS(on) x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the module.)
2) At loads ≤ 1 kΩ

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4.15.22.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
Double flash External I/O supply is outside the valid range: 12 VDC (-15% / +20%)
e+r Red on / Green single flash Invalid firmware
1-8 Orange Output status of the corresponding digital output

Table 397: Status LEDs

4.15.22.5 Pinout

r e

X20 DO 8232
1 2
3 4
5 6
7 8

DO 1 DO 2

DO 3 DO 4

DO 5 DO 6

DO
DI 17 DO 8

+12 VDC +12 VDC

GND GND

Figure 372: Pinout

4.15.22.6 Connection example

DO

Actuator 1 Actuator 2

Actuator 3 Actuator 4

Actuator 5 Actuator 6

Actuator 7 Actuator 8

_
+
+12 V ext. GND

Figure 373: Connection example

Caution!
If the module is operated outside of specifications, the output current can increase above the maximum
permissible nominal current. This applies to individual channels and also to the summation current
for the module.
Therefore sufficient cable cross sections or external safety measures must be used.

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4.15.22.7 Output circuit diagram

External Supply
12 V GND

12 V
External Supply Reverse polarity
protection
High-side
Output status 1 GND
Logic
Output x

I/O status GND

LED (orange)
Output monitoring

12 V
External
Power supply
GND
1 12 V
External Supply

12 V monitoring

Figure 374: Output circuit diagram

4.15.22.8 Switching inductive loads

Environmental temperature: 35°C, 4 outputs (1,3,5,7 or 2,4,6,8) with the same load.
100 H
500 10 H
Switching voltage:
14.4 V
12.0 V
1H

100

100 mH
Coil resistance Coil inductance
[Ω]
10 mH

10

5
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Figure 375: Switching inductive loads

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Environmental temperature: 60°C, 4 outputs (1,3,5,7 or 2,4,6,8) with the same load.
100 H 10 H
500
Switching voltage:
14.4 V
1H 12.0 V

100
100 mH
Coil resistance Coil inductance
[Ω]

10 mH

10

5
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Figure 376: Switching inductive loads

Environmental temperature: 60°C, all outputs with the same load.
100 H 10 H
500
Switching voltage:
1H 14.4 V
12.0 V

100 100 mH

Coil resistance Coil inductance

[Ω]
10 mH

10

5
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Figure 377: Switching inductive loads

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.22.9 Operation with 2 A

The outputs of the module can handle up to 2 A. With a total current of 8 A, no more than 4 channels are operable
at full load. To ensure optimal use of the module, it is important to assign the channels properly, and to keep in
mind a potential derating.
Correct channel assignment is important, since the eight outputs are divided between two output drivers. The
channels operated with 2A must therefore be evenly divided between both output drivers.
Output driver 1: Channels 1 - 4
Output driver 2: Channels 5 - 8
The following table provides an overview of the number of fully used channels, the resulting best distribution, and
a potential derating.
Number of channels using 2A Division Derating
1 Any No
2 1st channel with 2 A ... channel no. 1 - 4 No
2nd channel with 2 A ... channel no. 5 - 8
3 Assign all even or all odd channel numbers. Exam-
ples:
1, 3, 5 Channels 1 and 3
2, 4, 6 Channels 2 and 4
3, 5, 7 Channels 5 and 7
4, 6, 8 Channels 6 and 8
4 Assign all even or all odd channel numbers. Possible
distributions:
1, 3, 5, 7 All channels
2, 4, 6, 8 All channels

Derating when 3 or 4 channels are operated with 2 A:

2

1.375
Output current [A]

0
-25 35 60

Ambient temperature [°C]

Information:
Modules next to this module can have a maximum power consumption of 1.0 W.

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4.15.22.10 Register description

4.15.22.10.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
30 1 StatusInput01 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
8192 - Reading the module ID UINT ●
8196 - Status of the supply voltage USINT ●
PowerSupply01 Bit 2 ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.22.10.2 Function model 1 - Output switching

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 8 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
4 1 Switching state of delayed digital outputs 1 to 8 USINT ●
DigitalOutput01Delayed Bit 0
... ...
DigitalOutput08Delayed Bit 7
6 2 Switching mask after the delay time has expired USINT ●
DigitalOutput01DelayEnable Bit 0
... ...
DigitalOutput08DelayEnable Bit 7
8 3 Setting the delay USINT ●
(OutputDelayTime)
30 1 Status of digital outputs 1 to 8 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
8192 - Reading the module ID UINT ●
8196 - Status of the supply voltage USINT ●
PowerSupply01 Bit 2 ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.22.10.3 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 - Switching state of digital outputs 1 to 8 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
30 - Status of digital outputs 1 to 8 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
8192 - Reading the module ID UINT ●
8196 - Status of the supply voltage USINT ●
PowerSupply01 Bit 2 ●

1) The offset specifies where the register is within the CAN object.

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4.15.22.10.4 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.22.10.4.1 Switching state of digital outputs 1 to 8

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput08
The switching state of digital outputs 1 to 8 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
7 DigitalOutput08 0 Digital output 08 reset
1 Digital output 08 set

4.15.22.10.5 Reading the module ID

Name:
asy_ModulID
This register offers another possibility for reading the module ID.
Data type Value
UINT Module ID

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4.15.22.10.6 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

4.15.22.10.6.1 Status of digital outputs 1 to 8

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput08
This register is used to indicate the status of digital outputs 1 to 8.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through
"StatusDigitalOutput0x") or whether this register should be displayed as an individual USINT data point
("StatusInput01").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
... ...
8 StatusDigitalOutput08 0 Channel 08: No error
1 Channel 08: Short circuit or overload

4.15.22.10.7 Operating limit monitoring

The module's output supply is monitored. An I/O supply voltage of <10.2 V is displayed as a warning.

4.15.22.10.7.1 Status of the supply voltage

Name:
asy_SupplyStatus
The status of the I/O supply voltage is mapped in this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-1 0 0
2 PowerSupply01 0 I/O supply above the warning level of 10.2 V
1 I/O supply below the warning level of 10.2 V
3-7 0 0

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4.15.22.10.8 Additional function - switch digital outputs w/ delay using switching mask

In function model 1 - Output switching, it is possible to control the digital outputs with a delay.
The OutputDelay mask can be used to activate the delay for each channel individually. The module is controlled
here using a 100 μs-based timer and the Output or OutputDelayed register.
Behavior of function model 1 - Output switching
With a timer delay of 0:
Output: DigitalOutput0x bits
When the delay is changed:
The bit string for DigitalOutput0x bits is output. The timer restarts.
Output: DigitalOutput0x bits
After delay time has expired:
The channels with bits set in the OutputDelay mask are adapted to the respective OutputDelayed bits.
Output: DigitalOutput0x bits (if Enable bit = FALSE)
OutputDelayed bits (if Enable bit = TRUE)

Information:
Adjusting the output and restarting the timer take place immediately after transferring the new delay,
even if the previous time has not yet passed.

4.15.22.10.8.1 Switching state of delayed digital outputs 1 to 8

Name:
DigitalOutput01Delayed to Digital08Delayed
According to the corresponding bit in the OutputDelay mask, the switching state of all digital outputs 1 to 8 are
stored in the OutputDelayed bits after the delay time has expired.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Digital output 01 reset
0 DigitalOutput01Delayed
1 Digital output 01 set
... ...
0 Digital output 08 reset
7 DigitalOutput08Delayed
1 Digital output 08 set

Information:
After the delay time has expired, only the channels with a bit set in the OutputDelay mask are adjusted
to the OutputDelayed bits.

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4.15.22.10.8.2 Switching mask after the delay time has expired

Name:
DigitalOutput01DelayEnable to DigitalOutput08DelayEnable
These registers create the mask for OutputDelay. They define which outputs are switched to the bit string for the
OutputDelayed register after the delay time has expired.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Digital output 01 remains unchanged
0 DigitalOutput01DelayEnable
1 Digital output 01 is toggled
... ...
0 Digital output 08 remains unchanged
7 DigitalOutput08DelayEnable
1 Digital output 08 is toggled

4.15.22.10.8.3 Setting the delay

Name:
OutputDelayTime
This register can be used to set the delay in 100 μs steps.
After the delay time has expired, the digital outputs are adjusted according to the switching mask (register 6) and
the delayed output pattern (register 4).
Data type Value
USINT 0 to 255 (in 100 μs steps)1)

1) The value 0 disables processing

4.15.22.10.9 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Standard function model 100 μs
Bus controller function model 150 μs

4.15.22.10.10 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Function model 0 Equal to the minimum cycle time
Function model 1 Equal to the minimum cycle time

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4.15.23 X20DO8322

4.15.23.1 General information

The module is equipped with 8 outputs for 1-wire connections and designed for source output wiring.
• 8 digital outputs
• Source connection
• 1-wire connections
• Integrated output protection

4.15.23.2 Order data

Model number Short description Figure

Digital output modules
X20DO8322 X20 digital output module, 8 outputs, 24 VDC, 0.5 A, source, 1-
wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 398: X20DO8322 - Order data

4.15.23.3 Technical data

Product ID X20DO8322
Brief description
I/O module 8 digital outputs 24 VDC for 1-wire connections
General information
B&R ID code 0xA4AC
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, with status LED and software status (output error status)
Power consumption
Bus 0.26 W
Internal I/O 0.8 W
Additional power dissipation caused by the actua- +0.42
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital outputs
Design FET positive switching
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.5 A
Total nominal current 4.0 A
Connection type 1-wire connections
Output circuit Source
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 5 µA

Table 399: X20DO8322 - Technical data

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Product ID X20DO8322
RDS(on) 210 mΩ
Max. continuous current 6.0 A
Peak short circuit current <12 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay
0 -> 1 <300 µs
1 -> 0 <300 µs
Switching frequency
Resistive load Max. 500 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Typ. 50 VDC
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 399: X20DO8322 - Technical data

1) Number of outputs x RDS(on) x nominal output current2

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4.15.23.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
e+r Red on / Green single flash Invalid firmware
1-8 Orange Output status of the corresponding digital output

Table 400: Status LEDs

4.15.23.5 Pinout

r e

X20 DO 8322
1 2
3 4
5 6
7 8

DO 1 DO 2

DO 3 DO 4

DO 5 DO 6

DO 7 DO 8

Figure 378: Pinout

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4.15.23.6 Connection example

DO

Actuator 1 Actuator 2

Actuator 3 Actuator 4

Actuator 5 Actuator 6

Actuator 7 Actuator 8

+24 VDC +24 VDC

GND GND

GND GND

Figure 379: Connection example

Caution!
If the module is operated outside of specifications, the output current can increase above the maximum
permissible nominal current. This applies to individual channels and also to the summation current
for the module.
Therefore sufficient cable cross sections or external safety measures must be used.

4.15.23.7 Output circuit diagram

External Supply
24 V GND

Reverse polarity
protection
24 V

High-side 1 GND
Output status
Logic
Output x

I/O status GND

Output
LED (orange)
monitoring

Figure 380: Output circuit diagram

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4.15.23.8 Switching inductive loads

Environmental temperature: 55°C, all outputs with the same load

100 H 10 H
1000
Switching voltage:
1H
28.8 V
24.0 V

Coil resistance Coil inductance

[Ω]
100 mH

100
10 mH

50
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Figure 381: Switching inductive loads

Environmental temperature: 60°C, all outputs with the same load
100 H 10 H
1000
1 H Switching voltage:

28.8 V
24.0 V

100 mH

Coil resistance Coil inductance

[Ω]

100
10 mH

50
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Figure 382: Switching inductive loads

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.23.9 Register description

4.15.23.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
30 1 StatusInput01 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.23.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 8 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
30 - Status of digital outputs 1 to 8 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7

1) The offset specifies where the register is within the CAN object.

4.15.23.9.3 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.23.9.3.1 Switching state of digital outputs 1 to 8

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput08
The switching state of digital outputs 1 to 8 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
7 DigitalOutput08 0 Digital output 08 reset
1 Digital output 08 set

4.15.23.9.4 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

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4.15.23.9.4.1 Status of digital outputs 1 to 8

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput08
This register is used to indicate the status of digital outputs 1 to 8.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through
"StatusDigitalOutput0x") or whether this register should be displayed as an individual USINT data point
("StatusInput01").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
... ...
8 StatusDigitalOutput08 0 Channel 08: No error
1 Channel 08: Short circuit or overload

4.15.23.9.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.23.9.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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4.15.24 X20DO8323

4.15.24.1 General Information

The module is an electrically isolated 8-channel digital output module. It can be configured as high-side or low-side
or as a push/pull output for controlling 12 to 24 VDC DC motors.
• 8 digital outputs
• High-side or low-side connection
• Push/pull outputs
• 1-wire connections
• Integrated output protection

4.15.24.2 Order data

Model number Short description Figure

Digital output modules
X20DO8323 X20 digital output module, 8 outputs, 12 to 24 V, 0.5 A, sink/
source, 1-wire connections, full bridge, half bridge, thermal over-
load protection
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 401: X20DO8323 - Order data

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4.15.24.3 Technical data

Product ID X20DO8323
General information
Module type B&R X20 digital output module
B&R ID code 0xDF4E
Status indicators Operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, using software
Power consumption
Bus 160 mW
Internal I/O 200 mW (without load)
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
Digital outputs
Design FET push/pull (high resistance)
Nominal voltage 11.5 to 30 V
Nominal output current 0.5 A
Total nominal current 4.0 A
Connection type Sink / source
Output circuit 1-wire connections
Diagnostic status
Voltage monitoring 1) 11.5 V < supply voltage < 30 V
Output monitoring Output OK
Leakage current when switched off 5 μA per channel
RDS(on) 120 mΩ (low-side), 140 mΩ (high-side)
Switching delay
0 -> 1 Max. 450 μs
1 -> 0 Max. 450 μs
Switching frequency
Resistive load Max. 100 Hz
Isolation voltage between channel and bus 500 V
Reverse polarity protection Yes
Switching voltage
Minimum 11.5 VDC
Nominal 12 – 24 VDC
Maximum 30 VDC
Protective circuit
External 24 VDC supply voltage – Maximum current 5A (blow-out fuse)
Internal Thermal cutoff, integrated protection for switching inductances
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 402: X20DO8323 - Technical data

1) If the voltage is too low, the outputs are switched off.

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4.15.24.4 Status LEDs

Image LED Color Status Description

r Green Off No power to module
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
On Error or reset status
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
Double flash I/O supply too low

Table 403: Status LEDs

4.15.24.5 Pinout

r e

X20 DO 8323

DO 1 DO 2

DO 3 DO 4

DO 5 DO 6

DO
DI 17 DO 8

+24 VDC +24 VDC

GND GND

Figure 383: Pinout

4.15.24.6 Connection example

Half bridge connection:

+ +
M1 DO M2

+ +
M7 M8
+

+12 VDC
+

+12 VDC
+24 VDC +24 VDC
GND GND

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Full bridge connection:

DO

+ +
M1 M2

+ +
M3 M4

+24 VDC
+
+24 VDC +24 VDC
GND GND

Use as high-side or low-side:

DO

Actuator 1 Actuator 2

Actuator 3 Actuator 4

Actuator 5 Actuator 6

Actuator 7 Actuator 8
+

+24 VDC

+24 VDC +24 VDC

GND GND

4.15.24.7 Output circuit diagram

24 V

AH x

Output x

Output status AL x

GND

GND
FB x

GND

GND GND

Figure 384: Output circuit diagram

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4.15.24.8 Register description

4.15.24.8.1 Function model 0 - Default

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 1 DigitalInput USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
4 1 EnableDigitalOutput USINT ●
EnabDigitalOutput01 Bit 0
... ...
EnabDigitalOutput08 Bit 7
30 2 StatusInput01 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
31 3 Cumulative status USINT ●
StatusDigitalOutputs Bit 0
StatusSupplyLO Bit 4
StatusSupplyHI Bit 5

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.24.8.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 0 Digital inputs USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
2 0 Switching state of digital outputs 1 to 8 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
4 - Switching between inputs and outputs USINT ●
EnabDigitalOutput01 Bit 0
... ...
EnabDigitalOutput08 Bit 7
30 - Status of digital outputs 1 to 8 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
31 - Cumulative status USINT ●
StatusDigitalOutputs Bit 0
StatusSupplyLO Bit 4
StatusSupplyHI Bit 5

1) The offset specifies where the register is within the CAN object.

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4.15.24.8.3 Digital outputs

The output state is sent to the output ports acyclically to the network in the system timer (100 μsec). (max. switch
off jitter: 50 µsec, max. switch on jitter: 150 µsec)
The output state must be switched with at least a 300 µsec delay in order to prevent the high-side and low-side
drivers from switching together.

4.15.24.8.3.1 Switching state of digital outputs 1 to 8

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput08
The switching state of digital outputs 1 to 8 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
7 DigitalOutput08 0 Digital output 08 reset
1 Digital output 08 set

4.15.24.8.3.2 Status of digital outputs 1 to 8

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput08
This register is used to indicate the status of digital outputs 1 to 8.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through
"StatusDigitalOutput0x") or whether this register should be displayed as an individual USINT data point
("StatusInput01").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
... ...
8 StatusDigitalOutput08 0 Channel 08: No error
1 Channel 08: Short circuit or overload

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4.15.24.8.3.3 Switching between inputs and outputs

Name:
EnableDigitalOutput
EnabDigitalOutput01 through EnabDigitalOutput08
In this register, all channels can be connected as inputs or outputs. For each output there is a corresponding
switching bit. Clearing this bit switches to tristate mode.
In function model 254 the initial value is 255.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits should
be set up individually as data points in the AS I/O mapping ("EnabDigitalOutput01" through "EnabDigitalOutput08")
or whether this register should be displayed as an individual USINT data point ("EnableDigitalOutput").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 EnabDigitalOutput01 0 Channel 1 used as input
1 Channel 1 used as output
... ...
7 EnabDigitalOutput08 0 Channel 8 used as input
1 Channel 8 used as output

4.15.24.8.4 Digital inputs

Name:
DigitalInput
DigitalInput01 through DigitalInput08
The status of digital inputs 1 to 8 is mapped in this register.
The status of the digital inputs is read with a minimum update rate of 5 to 8 msec. according to the digital output
status sample rate.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalInput01" through "DigitalInput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalInput").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalInput01 0 or 1 Input status - Digital input 1
... ...
7 DigitalInput08 0 or 1 Input status - Digital input 8

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4.15.24.8.5 Cumulative status

Name:
StatusDigitalOutputs
StatusSupplyLO
StatusSupplyHI
The state of output monitoring and the supply voltage for all outputs are collected and mapped to this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 StatusDigitalOutputs 0 No output monitoring
1 Output monitoring active for at least one channel
1-3 Reserved 0
4 StatusSupplyLO 0 No error
1 Supply voltage too low (<= 11.5 VDC)
5 StatusSupplyHI 0 No error
1 Supply voltage too high (> 30 VDC)
6-7 Reserved 0

4.15.24.8.6 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.24.8.7 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
All channels 400 μs

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4.15.25 X20DO8331

4.15.25.1 General information

The module is equipped with 8 outputs for 1-wire connections. The rated output current is 2 A.
The output supply is fed directly to the module. An additional supply module is not needed. There is no connection
between the module and the I/O supply potential on the bus module.
• 8 digital outputs with 2 A
• Sink connection
• 1-wire connections
• Power feed integrated in the module
• Integrated output protection

4.15.25.2 Order data

Model number Short description Figure

Digital output modules
X20DO8331 X20 digital output module, 8 outputs, 24 VDC, 2 A, sink, supply
directly on module, 1-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 404: X20DO8331 - Order data

4.15.25.3 Technical data

Product ID X20DO8331
Brief description
I/O module 8 digital outputs 24 VDC for 1-wire connections
General information
B&R ID code 0x22EB
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, with status LED and software status (output error status)
Supply voltage monitoring Yes, using software
Power consumption
Bus 0.22 W
Internal I/O -
External I/O 0.9 W
Additional power dissipation caused by the actua- +0.56
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital outputs
Design FET negative switching
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 2.0 A
Total nominal current 8.0 A
Connection type 1-wire connections

Table 405: X20DO8331 - Technical data

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Product ID X20DO8331
Output circuit Sink
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")
Reverse polarity protection for supply voltage
Actuator supply
Feed External
Fuse Required line fuse: Max. 10 A, slow-blow
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 75 µA
RDS(on) 35 mΩ
Peak short circuit current <24 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay
0 -> 1 <300 µs
1 -> 0 <500 µs
Switching frequency
Resistive load Max. 500 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Typ. 50 VDC
Isolation voltage between channel and bus 500 Veff
Additional functions To increase the output current, outputs can be switched in parallel
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 405: X20DO8331 - Technical data

1) Number of outputs x RDS(on) x nominal output current2

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4.15.25.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
Double flash I/O supply too low
e+r Red on / Green single flash Invalid firmware
1-8 Orange Output status of the corresponding digital output

Table 406: Status LEDs

4.15.25.5 Pinout

r e

X20 DO 8331
1 2
3 4
5 6
7 8

DO 1 DO 2

DO 3 DO 4

DO 5 DO 6

DO 7 DO 8

+24 VDC +24 VDC

GND GND

Figure 385: Pinout

4.15.25.6 Connection example

DO

Actuator 1 Actuator 2

Actuator 3 Actuator 4

Actuator 5 Actuator 6

Actuator 7 Actuator 8

+24 VDC +24 VDC

GND GND

T 10 A _
+
+24 V ext.

Figure 386: Connection example

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4.15.25.7 Output circuit diagram

External Supply
24 V 24 V GND

Reverse polarity
protection

I/O status
LED (orange) GND 24 VInternal
Low-side
Output status Output x
Logic

VDR
GND
Output
monitoring GND

24 V

GND 24 V
External
Power supply
24 VInternal GND

GND
24 V monitoring

GND

Figure 387: Output circuit diagram

4.15.25.8 Switching inductive loads

Environmental temperature: 35°C, 4 outputs (1,3,5,7 or 2,4,6,8) with the same load.
100 H 10 H
500

1H

100 100 mH

Coil resistance Coil inductance

[Ω]

10 mH

Switching voltage:
28.8 V
24.0 V
10
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Figure 388: Switching inductive loads

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Environmental temperature: 60°C, 4 outputs (1,3,5,7 or 2,4,6,8) with the same load.
100 H 10 H
500
1H

100 mH

100

Coil resistance Coil inductance

[Ω] 10 mH

Switching voltage:
28.8 V
24.0 V
10
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Figure 389: Switching inductive loads

Environmental temperature: 60°C, all outputs with the same load.
100 H 10 H 1H
500

100 mH

100

10 mH
Coil resistance Coil inductance
[Ω]

Switching voltage:
28.8 V
24.0 V
10
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Figure 390: Switching inductive loads

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.25.9 Operation with 2 A

The outputs of the module can handle up to 2 A. With a total current of 8 A, no more than 4 channels are operable
at full load. To ensure optimal use of the module, it is important to assign the channels properly, and to keep in
mind a potential derating.
Correct channel assignment is important, since the eight outputs are divided between two output drivers. The
channels operated with 2A must therefore be evenly divided between both output drivers.
Output driver 1: Channels 1 - 4
Output driver 2: Channels 5 - 8
The following table provides an overview of the number of fully used channels, the resulting best distribution, and
a potential derating.
Number of channels using 2A Division Derating
1 Any No
2 1st channel with 2 A ... channel no. 1 - 4 No
2nd channel with 2 A ... channel no. 5 - 8
3 Assign all even or all odd channel numbers. Exam-
ples:
1, 3, 5 Channels 1 and 3
2, 4, 6 Channels 2 and 4
3, 5, 7 Channels 5 and 7
4, 6, 8 Channels 6 and 8
4 Assign all even or all odd channel numbers. Possible
distributions:
1, 3, 5, 7 All channels
2, 4, 6, 8 All channels

Derating when 3 or 4 channels are operated with 2 A:

2

1.375
Output current [A]

0
-25 35 60

Ambient temperature [°C]

Figure 391: Derating when 3 or 4 channels are operated with 2 A

Information:
Modules next to this module can have a maximum power consumption of 1.5 W.

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4.15.25.10 Register description

4.15.25.10.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
30 1 StatusInput01 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
8192 - Reading the module ID UINT ●
8196 - Status of the supply voltage USINT ●
PowerSupply01 Bit 2 ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.25.10.2 Function model 1 - Output switching

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 8 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
4 1 Switching state of delayed digital outputs 1 to 8 USINT ●
DigitalOutput01Delayed Bit 0
... ...
DigitalOutput08Delayed Bit 7
6 2 Switching mask after the delay time has expired USINT ●
DigitalOutput01DelayEnable Bit 0
... ...
DigitalOutput08DelayEnable Bit 7
8 3 Setting the delay USINT ●
(OutputDelayTime)
30 1 Status of digital outputs 1 to 8 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
8192 - Reading the module ID UINT ●
8196 - Status of the supply voltage USINT ●
PowerSupply01 Bit 2 ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.25.10.3 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 8 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
30 - Status of digital outputs 1 to 8 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
8192 - Reading the module ID UINT ●
8196 - Status of the supply voltage USINT ●
Power Supply01 Bit 2 ●

1) The offset specifies where the register is within the CAN object.

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4.15.25.10.4 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.25.10.4.1 Switching state of digital outputs 1 to 8

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput08
The switching state of digital outputs 1 to 8 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
7 DigitalOutput08 0 Digital output 08 reset
1 Digital output 08 set

4.15.25.10.5 Reading the module ID

Name:
asy_ModulID
This register offers another possibility for reading the module ID.
Data type Value
UINT Module ID

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4.15.25.10.6 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

4.15.25.10.6.1 Status of digital outputs 1 to 8

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput08
This register is used to indicate the status of digital outputs 1 to 8.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through
"StatusDigitalOutput0x") or whether this register should be displayed as an individual USINT data point
("StatusInput01").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
... ...
8 StatusDigitalOutput08 0 Channel 08: No error
1 Channel 08: Short circuit or overload

4.15.25.10.7 Operating limit monitoring

The module's output supply is monitored. An I/O supply voltage of <20.4 V is displayed as a warning.

4.15.25.10.7.1 Status of the supply voltage

Name:
asy_SupplyStatus
The status of the I/O supply voltage is mapped in this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-1 0
2 PowerSupply01 0 I/O supply above the warning level of 20.4V
1 I/O supply below the warning level of 20.4V
3-7 0

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4.15.25.10.8 Additional function - switch digital outputs w/ delay using switching mask

In function model 1 - Output switching, it is possible to control the digital outputs with a delay.
The OutputDelay mask can be used to activate the delay for each channel individually. The module is controlled
here using a 100 μs-based timer and the Output or OutputDelayed register.
Behavior of function model 1 - Output switching
With a timer delay of 0:
Output: DigitalOutput0x bits
When the delay is changed:
The bit string for DigitalOutput0x bits is output. The timer restarts.
Output: DigitalOutput0x bits
After delay time has expired:
The channels with bits set in the OutputDelay mask are adapted to the respective OutputDelayed bits.
Output: DigitalOutput0x bits (if Enable bit = FALSE)
OutputDelayed bits (if Enable bit = TRUE)

Information:
Adjusting the output and restarting the timer take place immediately after transferring the new delay,
even if the previous time has not yet passed.

4.15.25.10.8.1 Switching state of delayed digital outputs 1 to 8

Name:
DigitalOutput01Delayed to Digital08Delayed
According to the corresponding bit in the OutputDelay mask, the switching state of all digital outputs 1 to 8 are
stored in the OutputDelayed bits after the delay time has expired.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Digital output 01 reset
0 DigitalOutput01Delayed
1 Digital output 01 set
... ...
0 Digital output 08 reset
7 DigitalOutput08Delayed
1 Digital output 08 set

Information:
After the delay time has expired, only the channels with a bit set in the OutputDelay mask are adjusted
to the OutputDelayed bits.

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4.15.25.10.8.2 Switching mask after the delay time has expired

Name:
DigitalOutput01DelayEnable to DigitalOutput08DelayEnable
These registers create the mask for OutputDelay. They define which outputs are switched to the bit string for the
OutputDelayed register after the delay time has expired.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Digital output 01 remains unchanged
0 DigitalOutput01DelayEnable
1 Digital output 01 is toggled
... ...
0 Digital output 08 remains unchanged
7 DigitalOutput08DelayEnable
1 Digital output 08 is toggled

4.15.25.10.8.3 Setting the delay

Name:
OutputDelayTime
This register can be used to set the delay in 100 μs steps.
After the delay time has expired, the digital outputs are adjusted according to the switching mask (register 6) and
the delayed output pattern (register 4).
Data type Value
USINT 0 to 255 (in 100 μs steps)1)

1) The value 0 disables processing

4.15.25.10.9 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Standard function model 100 μs
Bus controller function model 150 μs

4.15.25.10.10 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Function model 0 Equal to the minimum cycle time
Function model 1 Equal to the minimum cycle time

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4.15.26 X20DO8332

4.15.26.1 General information

The module is equipped with 8 outputs for 1-wire connections. The rated output current is 2 A.
The output supply is fed directly to the module. An additional supply module is not needed. There is no connection
between the module and the I/O supply potential on the bus module.
• 8 digital outputs with 2 A
• Source connection
• 1-wire connections
• Power feed integrated in the module
• Integrated output protection

4.15.26.2 Order data

Model number Short description Figure

Digital output modules
X20DO8332 X20 digital output module, 8 outputs, 24 VDC, 2 A, source, sup-
ply directly on module, 1-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 407: X20DO8332 - Order data

4.15.26.3 Technical data

Product ID X20DO8332
Brief description
I/O module 8 digital outputs 24 VDC for 1-wire connections
General information
B&R ID code 0x1B9D
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, with status LED and software status (output error status)
Supply voltage monitoring Yes, using software
Power consumption
Bus 0.22 W
Internal I/O -
External I/O 0.92 W
Additional power dissipation caused by the actua- +2.24
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital outputs
Design FET positive switching
Number of output groups 2
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 2.0 A

Table 408: X20DO8332 - Technical data

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Product ID X20DO8332
Total nominal current
Per group 4.0 A
Per module 8.0 A 2)
Connection type 1-wire connections
Output circuit Source
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")
Reverse polarity protection for supply voltage
Actuator supply
Feed External
Fuse Required line fuse: Max. 10 A, slow-blow
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 5 µA
RDS(on) 140 mΩ
Max. continuous current 8.0 A
Peak short circuit current <12 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay
0 -> 1 <300 µs
1 -> 0 <300 µs
Switching frequency
Resistive load Max. 500 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Typ. 50 VDC
Isolation voltage between channel and bus 500 Veff
Additional functions To increase the output current, outputs can be switched in parallel
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 408: X20DO8332 - Technical data

1) Number of outputs x RDS(on) x nominal output current2
2) Derating may be necessary with more than 6 A total current.

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4.15.26.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
Double flash I/O supply too low
e+r Red on / Green single flash Invalid firmware
1-8 Orange Output status of the corresponding digital output

Table 409: Status LEDs

4.15.26.5 Pinout

r e

X20 DO 8332
1 2
3 4
5 6
7 8

DO 1 DO 2

DO 3 DO 4

DO 5 DO 6

DO 7 DO 8

+24 VDC +24 VDC

GND GND

Figure 392: Pinout

4.15.26.6 Connection example

DO

Actuator 1 Actuator 2

Actuator 3 Actuator 4

Actuator 5 Actuator 6

Actuator 7 Actuator 8

+24 VDC +24 VDC

GND GND

T 10 A _
+
+24 V ext.

Figure 393: Connection example

Caution!
If the module is operated outside of specifications, the output current can increase above the maximum
permissible nominal current. This applies to individual channels and also to the summation current
for the module.
Therefore sufficient cable cross sections or external safety measures must be used.

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4.15.26.7 Output circuit diagram

External Supply
24 V GND

Reverse polarity
24 V
protection
External Supply

High-side 1 GND
Output status
Logic
Output x

I/O status GND

Output
LED (orange)
monitoring

24 V
External
Power supply
GND
1 24 V
External Supply

24 V monitoring

Figure 394: Output circuit diagram

4.15.26.8 Switching inductive loads

Environmental temperature: 35°C, 4 outputs (1,3,5,7 or 2,4,6,8) with the same load.
100 H 10 H
500

1H

100 100 mH

Coil resistance Coil inductance

[Ω]
10 mH

Switching voltage:
28.8 V
24.0 V
10
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Figure 395: Switching inductive loads

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Environmental temperature: 60°C, 4 outputs (1,3,5,7 or 2,4,6,8) with the same load.
100 H 10 H
500
1H

100 mH

100

Coil resistance Coil inductance

[Ω] 10 mH

Switching voltage:
28.8 V
24.0 V
10
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Figure 396: Switching inductive loads

Environmental temperature: 60°C, all outputs with the same load.
100 H 10 H 1H
500

100 mH

100
10 mH
Coil resistance Coil inductance
[Ω]

Switching voltage:
28.8 V
24.0 V
10
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Figure 397: Switching inductive loads

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.26.9 Operation with 2 A

The outputs of the module can handle up to 2 A. With a total current of 8 A, no more than 4 channels are operable
at full load. To ensure optimal use of the module, it is important to assign the channels properly, and to keep in
mind a potential derating.
Correct channel assignment is important, since the eight outputs are divided between two output drivers. The
channels operated with 2A must therefore be evenly divided between both output drivers.
Output driver 1: Channels 1 - 4
Output driver 2: Channels 5 - 8
The following table provides an overview of the number of fully used channels, the resulting best distribution, and
a potential derating.
Number of channels using 2A Division Derating
1 Any No
2 1st channel with 2 A ... channel no. 1 - 4 No
2nd channel with 2 A ... channel no. 5 - 8
3 Assign all even or all odd channel numbers. Exam-
ples:
1, 3, 5 Channels 1 and 3
2, 4, 6 Channels 2 and 4
3, 5, 7 Channels 5 and 7
4, 6, 8 Channels 6 and 8
4 Assign all even or all odd channel numbers. Possible
distributions:
1, 3, 5, 7 All channels
2, 4, 6, 8 All channels

Derating when 3 or 4 channels are operated with 2 A:

2

1.375
Output current [A]

0
-25 35 60

Ambient temperature [°C]

Figure 398: Derating when 3 or 4 channels are operated with 2 A

Information:
Modules next to this module can have a maximum power consumption of 1.5 W.

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4.15.26.10 Register description

4.15.26.10.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
30 1 StatusInput01 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
8192 - Reading the module ID UINT ●
8196 - Status of the supply voltage USINT ●
PowerSupply01 Bit 2 ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.26.10.2 Function model 1 - Output switching

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 8 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
4 1 Switching state of delayed digital outputs 1 to 8 USINT ●
DigitalOutput01Delayed Bit 0
... ...
DigitalOutput08Delayed Bit 7
6 2 Switching mask after the delay time has expired USINT ●
DigitalOutput01DelayEnable Bit 0
... ...
DigitalOutput08DelayEnable Bit 7
8 3 Setting the delay USINT ●
(OutputDelayTime)
30 1 Status of digital outputs 1 to 8 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
8192 - Reading the module ID UINT ●
8196 - Status of the supply voltage USINT ●
PowerSupply01 Bit 2 ●

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.26.10.3 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 8 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
30 - Status of digital outputs 1 to 8 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
8192 - Reading the module ID UINT ●
8196 - Status of the supply voltage USINT ●
Power Supply01 Bit 2 ●

1) The offset specifies where the register is within the CAN object.

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4.15.26.10.4 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.26.10.4.1 Switching state of digital outputs 1 to 8

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput08
The switching state of digital outputs 1 to 8 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput0x") or
whether this register should be displayed as an individual USINT data point ("DigitalOutput").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
7 DigitalOutput08 0 Digital output 08 reset
1 Digital output 08 set

4.15.26.10.5 Reading the module ID

Name:
asy_ModulID
This register offers another possibility for reading the module ID.
Data type Value
UINT Module ID

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4.15.26.10.6 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

4.15.26.10.6.1 Status of digital outputs 1 to 8

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput08
This register is used to indicate the status of digital outputs 1 to 8.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of this registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through
"StatusDigitalOutput0x") or whether this register should be displayed as an individual USINT data point
("StatusInput01").
Data type Value Information
USINT 0 to 255 Packed outputs = on
See bit structure Packed outputs = off or function model <> 0 - Standard

Bit structure:
Bit Name Value Information
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
... ...
8 StatusDigitalOutput08 0 Channel 08: No error
1 Channel 08: Short circuit or overload

4.15.26.10.7 Operating limit monitoring

The module's output supply is monitored. An I/O supply voltage of <20.4 V is displayed as a warning.

4.15.26.10.7.1 Status of the supply voltage

Name:
asy_SupplyStatus
The status of the I/O supply voltage is mapped in this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-1 0
2 PowerSupply01 0 I/O supply above the warning level of 20.4V
1 I/O supply below the warning level of 20.4V
3-7 0

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4.15.26.10.8 Additional function - switch digital outputs w/ delay using switching mask

In function model 1 - Output switching, it is possible to control the digital outputs with a delay.
The OutputDelay mask can be used to activate the delay for each channel individually. The module is controlled
here using a 100 μs-based timer and the Output or OutputDelayed register.
Behavior of function model 1 - Output switching
With a timer delay of 0:
Output: DigitalOutput0x bits
When the delay is changed:
The bit string for DigitalOutput0x bits is output. The timer restarts.
Output: DigitalOutput0x bits
After delay time has expired:
The channels with bits set in the OutputDelay mask are adapted to the respective OutputDelayed bits.
Output: DigitalOutput0x bits (if Enable bit = FALSE)
OutputDelayed bits (if Enable bit = TRUE)

Information:
Adjusting the output and restarting the timer take place immediately after transferring the new delay,
even if the previous time has not yet passed.

4.15.26.10.8.1 Switching state of delayed digital outputs 1 to 8

Name:
DigitalOutput01Delayed to Digital08Delayed
According to the corresponding bit in the OutputDelay mask, the switching state of all digital outputs 1 to 8 are
stored in the OutputDelayed bits after the delay time has expired.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Digital output 01 reset
0 DigitalOutput01Delayed
1 Digital output 01 set
... ...
0 Digital output 08 reset
7 DigitalOutput08Delayed
1 Digital output 08 set

Information:
After the delay time has expired, only the channels with a bit set in the OutputDelay mask are adjusted
to the OutputDelayed bits.

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4.15.26.10.8.2 Switching mask after the delay time has expired

Name:
DigitalOutput01DelayEnable to DigitalOutput08DelayEnable
These registers create the mask for OutputDelay. They define which outputs are switched to the bit string for the
OutputDelayed register after the delay time has expired.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Digital output 01 remains unchanged
0 DigitalOutput01DelayEnable
1 Digital output 01 is toggled
... ...
0 Digital output 08 remains unchanged
7 DigitalOutput08DelayEnable
1 Digital output 08 is toggled

4.15.26.10.8.3 Setting the delay

Name:
OutputDelayTime
This register can be used to set the delay in 100 μs steps.
After the delay time has expired, the digital outputs are adjusted according to the switching mask (register 6) and
the delayed output pattern (register 4).
Data type Value
USINT 0 to 255 (in 100 μs steps)1)

1) The value 0 disables processing

4.15.26.10.9 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
Standard function model 100 μs
Bus controller function model 150 μs

4.15.26.10.10 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Function model 0 Equal to the minimum cycle time
Function model 1 Equal to the minimum cycle time

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4.15.27 X20DO9321

4.15.27.1 General information

The module is equipped with 12 outputs for 1-wire connections. The module is designed for sink output wiring.
• 12 digital outputs
• Sink connection
• 1-wire connections
• Integrated output protection

4.15.27.2 Order data

Model number Short description Figure

Digital output modules
X20DO9321 X20 digital output module, 12 outputs, 24 VDC, 0.5 A, sink, 1-
wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 410: X20DO9321 - Order data

4.15.27.3 Technical data

Product ID X20DO9321
Short description
I/O module 12 digital outputs 24 VDC for 1-wire connections
General information
B&R ID code 0x1B9B
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, with status LED and software status (output error status)
Power consumption
Bus 0.26 W
Internal I/O 0.99 W
Additional power dissipation caused by the actua- +0.36
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital outputs
Design FET negative switching
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.5 A
Total nominal current 6.0 A
Connection type 1-wire connections
Output circuit Sink
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 75 µA
RDS(on) 120 mΩ

Table 411: X20DO9321 - Technical data

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Product ID X20DO9321
Peak short circuit current <7 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay
0 -> 1 <300 µs
1 -> 0 <300 µs
Switching frequency
Resistive load Max. 500 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Typ. 50 VDC
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 411: X20DO9321 - Technical data

1) Number of outputs x RDS(on) x nominal output current2

4.15.27.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
e+r Red on / Green single flash Invalid firmware
1 - 12 Orange Output status of the corresponding digital output

Table 412: Status LEDs

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4.15.27.5 Pinout

r e

X20 DO 9321
1 2
3 4
5 6
7 8
9 10
11 12

DO 1 DO 2

DO 3 DO 4

DO 5 DO 6

DO 7 DO 8

DO 9 DO 10

DO 11 DO 12

Figure 399: Pinout

4.15.27.6 Connection example

DO

Actuator 1 Actuator 2

Actuator 3 Actuator 4

Actuator 5 Actuator 6

Actuator 7 Actuator 8

Actuator 9 Actuator 10

Actuator 11 Actuator 12

+24 VDC +24 VDC

GND GND

+24 VDC +24 VDC

Figure 400: Connection example

4.15.27.7 Output circuit diagram

24 V

I/O status
LED (orange)
Low-side
Output status Output x
Logic

VDR
GND
Output
monitoring GND

GND

Figure 401: Output circuit diagram

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4.15.27.8 Switching inductive loads

Environmental temperature: 55°C, all outputs with the same load

100 H 10 H
1000
1H
Switching voltage:

28.8 V
24.0 V

100 mH
Coil resistance Coil inductance
[Ω]

100 10 mH

50
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Environmental temperature: 60°C, all outputs with the same load

100 H 10 H 1H
1000
Switching voltage:

28.8 V
24.0 V

100 mH

Coil resistance Coil inductance

[Ω]

10 mH
100

50
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.27.9 Register description

4.15.27.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
1 DigitalOutput UINT ●
2 0 Switching state of digital outputs 1 to 8 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
3 1 Switching state of digital outputs 9 to 12 USINT ●
DigitalOutput09 Bit 0
... ...
DigitalOutput12 Bit 3
1 StatusInput01 UINT ●
30 1 Status of digital outputs 1 to 8 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
31 2 Status of digital outputs 9 to 12 USINT ●
StatusDigitalOutput09 Bit 0
... ...
StatusDigitalOutput12 Bit 3

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.27.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 8 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
3 1 Switching state of digital outputs 9 to 12 USINT ●
DigitalOutput09 Bit 0
... ...
DigitalOutput12 Bit 3
30 - Status of digital outputs 1 to 8 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
31 - Status of digital outputs 9 to 12 USINT ●
StatusDigitalOutput09 Bit 0
... ...
StatusDigitalOutput12 Bit 3

1) The offset specifies where the register is within the CAN object.

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4.15.27.9.3 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.27.9.3.1 Switching state of digital outputs 1 to 12

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput12
The switching state of digital outputs 1 to 12 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of these registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput12") or
whether these registers should be displayed as an individual UINT data point ("DigitalOutput").
Data type Value
UINT Packed "DigitalOutput" values
USINT See bit structure

Bit structure:
Register 2, Offset 0:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
7 DigitalOutput08 0 Digital output 08 reset
1 Digital output 08 set

Register 3, Offset 1:
Bit Name Value Information
0 DigitalOutput09 0 Digital output 09 reset
1 Digital output 09 set
... ...
3 DigitalOutput12 0 Digital output 12 reset
1 Digital output 12 set

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4.15.27.9.4 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

4.15.27.9.4.1 Status of digital outputs 1 to 12

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput12
The status of digital outputs 1 to 12 is mapped in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of these registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through "Status-
DigitalOutput12") or whether these registers should be displayed as an individual UINT data point ("StatusDigi-
talOutput").
Data type Value
UINT Packed "StatusDigitalOutput" values
USINT See bit structure

Bit structure:
Register 30, (Offset 1):
Bit Name Value Description
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
... ...
7 StatusDigitalOutput08 0 Channel 08: No error
1 Channel 08: Short circuit or overload

Register 31, (Offset 2):

Bit Name Value Information
0 StatusDigitalOutput09 0 Channel 09: No error
1 Channel 09: Short circuit or overload
... ...
3 StatusDigitalOutput12 0 Channel 12: No error
1 Channel 12: Short circuit or overload

4.15.27.9.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.27.9.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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4.15.28 X20DO9322

4.15.28.1 General information

The module is equipped with 12 outputs for 1-wire connections. The module is designed for source output wiring.
• 12 digital outputs
• Source connection
• 1-wire connections
• Integrated output protection

4.15.28.2 Order data

Model number Short description Figure

Digital output modules
X20DO9322 X20 digital output module, 12 outputs, 24 VDC, 0.5 A, source,
1-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 413: X20DO9322 - Order data

4.15.28.3 Technical data

Product ID X20DO9322
Short description
I/O module 12 digital outputs 24 VDC for 1-wire connections
General information
B&R ID code 0x1B9A
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, with status LED and software status (output error status)
Power consumption
Bus 0.26 W
Internal I/O 1.15 W
Additional power dissipation caused by the actua- +0.63
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GL Yes
GOST-R Yes
Digital outputs
Design FET positive switching
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.5 A
Total nominal current 6.0 A
Connection type 1-wire connections
Output circuit Source
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 5 µA

Table 414: X20DO9322 - Technical data

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Product ID X20DO9322
RDS(on) 210 mΩ
Max. continuous current 6.0 A
Peak short circuit current <12 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay 2)
0 -> 1 <300 µs
1 -> 0 <300 µs
Switching frequency
Resistive load 2) Max. 500 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Typ. 50 VDC
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 414: X20DO9322 - Technical data

1) Number of outputs x RDS(on) x nominal output current2
2) @ ≤ 1 kΩ

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4.15.28.4 Status LEDs

Figure LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
e+r Red on / Green single flash Invalid firmware
1 - 12 Orange Output status of the corresponding digital output

Table 415: Status LEDs

4.15.28.5 Pinout

r e

X20 DO 9322
1 2
3 4
5 6
7 8
9 10
11 12

DO 1 DO 2

DO 3 DO 4

DO 5 DO 6

DO 7 DO 8

DO 9 DO 10

DO 11 DO 12

Figure 402: Pinout

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4.15.28.6 Connection example

DO

Actuator 1 Actuator 2

Actuator 3 Actuator 4

Actuator 5 Actuator 6

Actuator 7 Actuator 8

Actuator 9 Actuator 10

Actuator 11 Actuator 12

+24 VDC +24 VDC

GND GND

GND GND

Figure 403: Connection example

Caution!
If the module is operated outside of specifications, the output current can increase above the maximum
permissible nominal current. This applies to individual channels and also to the summation current
for the module.
Therefore sufficient cable cross sections or external safety measures must be used.

4.15.28.7 Output circuit diagram

24 V GND

Reverse polarity
protection
24 V

High-side 1 GND
Output status
Logic
Output x

I/O status GND

Output
LED (orange)
monitoring

Figure 404: Output circuit diagram

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4.15.28.8 Switching inductive loads

Environmental temperature: 55°C, all outputs with the same load

100 H 10 H
1000
1H Switching voltage:

28.8 V
24.0 V

100 mH

Coil resistance Coil inductance

[Ω]

100 10 mH

50
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Figure 405: Switching inductive loads

Environmental temperature: 60°C, all outputs with the same load
100 H 10 H 1H
1000
Switching voltage:
28.8 V
24.0 V
100 mH

Coil resistance Coil inductance

[Ω]
10 mH

100

50
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Figure 406: Switching inductive loads

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.28.9 Register description

4.15.28.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
1 DigitalOutput UINT ●
2 0 Switching state of digital outputs 1 to 8 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
3 1 Switching state of digital outputs 9 to 12 USINT ●
DigitalOutput09 Bit 0
... ...
DigitalOutput12 Bit 3
1 StatusInput01 UINT ●
30 1 Status of digital outputs 1 to 8 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
31 2 Status of digital outputs 9 to 12 USINT ●
StatusDigitalOutput09 Bit 0
... ...
StatusDigitalOutput12 Bit 3

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.28.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 8 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
3 1 Switching state of digital outputs 9 to 12 USINT ●
DigitalOutput09 Bit 0
... ...
DigitalOutput12 Bit 3
30 - Status of digital outputs 1 to 8 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
31 - Status of digital outputs 9 to 12 USINT ●
StatusDigitalOutput09 Bit 0
... ...
StatusDigitalOutput12 Bit 3

1) The offset specifies where the register is within the CAN object.

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4.15.28.9.3 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.28.9.3.1 Switching state of digital outputs 1 to 12

Name:
DigitalOutput
DigitalOutput01 to DigitalOutput12
The switching state of digital outputs 1 to 12 are stored in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of these registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput12") or
whether these registers should be displayed as an individual UINT data point ("DigitalOutput").
Data type Value
UINT Packed "DigitalOutput" values
USINT See bit structure

Bit structure:
Register 2, Offset 0:
Bit Name Value Information
0 DigitalOutput01 0 Digital output 01 reset
1 Digital output 01 set
... ...
7 DigitalOutput08 0 Digital output 08 reset
1 Digital output 08 set

Register 3, Offset 1:
Bit Name Value Information
0 DigitalOutput09 0 Digital output 09 reset
1 Digital output 09 set
... ...
3 DigitalOutput12 0 Digital output 12 reset
1 Digital output 12 set

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4.15.28.9.4 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

4.15.28.9.4.1 Status of digital outputs 1 to 12

Name:
StatusInput01
StatusDigitalOutput01 to StatusDigitalOutput12
The status of digital outputs 1 to 12 is mapped in this register.
Function model 0 - Standard only:
The "packed outputs" setting in the AS I/O configuration is used to determine whether all of these registers'
bits should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through "Status-
DigitalOutput12") or whether these registers should be displayed as an individual UINT data point ("StatusDigi-
talOutput").
Data type Value
UINT Packed "StatusDigitalOutput" values
USINT See bit structure

Bit structure:
Register 30, (Offset 1):
Bit Name Value Description
0 StatusDigitalOutput01 0 Channel 01: No error
1 Channel 01: Short circuit or overload
... ...
7 StatusDigitalOutput08 0 Channel 08: No error
1 Channel 08: Short circuit or overload

Register 31, (Offset 2):

Bit Name Value Information
0 StatusDigitalOutput09 0 Channel 09: No error
1 Channel 09: Short circuit or overload
... ...
3 StatusDigitalOutput12 0 Channel 12: No error
1 Channel 12: Short circuit or overload

4.15.28.9.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.28.9.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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4.15.29 X20DOD322

4.15.29.1 General information

The X20DOD322 module is equipped with eight outputs for 1-wire or 2-wire connections. The X20DOD322 is
designed for source output wiring.
• 8 digital outputs
• Source connection
• 2-wire connections
• GND for signal supply
• Integrated output protection

4.15.29.2 Order data

Model number Short description Figure

Digital output modules
X20DOD322 X20 digital output module, 8 outputs, 24 VDC, 0.5 A, source, 2-
wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB1F X20 terminal block, 16-pin, 24 VDC keyed

Table 416: X20DOD322 - Order data

4.15.29.3 Technical data

Product ID X20DOD322
Short description
I/O module 8 digital outputs 24 VDC for 1- or 2-wire connections
General information
B&R ID code 0xC0E9
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, with status LED and software status (output error status)
Power consumption
Bus 0.19 W
Internal I/O 0.8 W
Additional power dissipation caused by the actua- 0.28 W
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GOST-R In preparation
Digital outputs
Design FET positive switching
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.5 A
Total nominal current 4.0 A
Connection type 1- or 2-wire connections
Output circuit Source
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")
Diagnostic status Output monitoring with 10 ms delay

Table 417: X20DOD322 - Technical data

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Product ID X20DOD322
Leakage current when switched off 5 µA
RDS(on) 140 mΩ
Max. continuous current 6.0 A
Peak short circuit current <3 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay 2)
0 -> 1 <300 µs
1 -> 0 <300 µs
Switching frequency
Resistive load 2) Max. 500 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Typ. 45 VDC
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB1F terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 417: X20DOD322 - Technical data

1) Number of outputs x RDS(on) x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the module.)
2) At loads ≤ 1 kΩ

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4.15.29.4 Status LEDs

Figure LED Color Status Description

S Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
Red on / Green single flash Invalid firmware
1-8 Orange Output status of the corresponding digital output

Table 418: Status LEDs

4.15.29.5 Pinout

S 1 2
3 4

X20 DO D322
5 6
7 8

DO 1 DO 2
DO 3 DO 4
DO 5 DO 6
DO 7 DO 8
GND GND
GND GND
GND GND
GND GND

Figure 407: Pinout

4.15.29.6 Connection example

DO

Actuator 1 Actuator 2

Actuator 3 Actuator 4

Actuator 5 Actuator 6

Actuator 7 Actuator 8

+24 VDC +24 VDC

GND GND

Figure 408: Connection example

Caution!
If the module is operated outside of specifications, the output current can increase above the maximum
permissible nominal current. This applies to individual channels and also to the summation current
for the module.
Therefore sufficient cable cross sections or external safety measures must be used.

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4.15.29.7 Output circuit diagram

24 V

High-side
Output status
Logic
Output x

GND
I/O status
LED (orange)
Output
monitoring

GND
GND

Figure 409: Output circuit diagram

4.15.29.8 Switching inductive loads

Environmental temperature: 60°C, all outputs with the same load

100 H 10 H 1H
1000
Switching voltage:

28.8 V
24.0 V

100 mH

Coil resistance Coil inductance

[Ω]

100 10 mH

50
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.29.9 Register description

4.15.29.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 DigitalOutput USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
30 1 StatusDigitalOutput USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7

Table 419: Overview of registers

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.29.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 8 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
30 - Status of digital outputs 1 to 8 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7

1) The offset specifies where the register is within the CAN object.

4.15.29.9.3 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.29.9.3.1 Switching state of digital outputs 1 to 8

Name:
DigitalOutput or
DigitalOutput01 to DigitalOutput08
The switching state of digital outputs 1 to 8 are stored in this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Digital output 01 reset
0 DigitalOutput01
1 Digital output 01 set
... ...
0 Digital output 08 reset
7 DigitalOutput08
1 Digital output 08 set

The "packed outputs" setting in the AS I/O configuration is used to determine whether all of these registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput16") or
whether these registers should be displayed as an individual UINT data point ("DigitalOutput").

4.15.29.9.4 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

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4.15.29.9.4.1 Status of digital outputs 1 to 8

Name:
StatusDigitalOutput or
StatusDigitalOutput01 to StatusDigitalOutput08
The status of digital outputs 1 to 8 is mapped in this register.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 Channel 01: No error
0 StatusDigitalOutput01
1 Channel 01: Short circuit or overload
... ...
0 Channel 08: No error
8 StatusDigitalOutput08
1 Channel 08: Short circuit or overload

The "packed outputs" setting in the AS I/O configuration is used to determine whether all of these registers' bits
should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through "StatusDigi-
talOutput16") or whether these registers should be displayed as an individual UINT data point ("StatusDigitalOut-
put").

4.15.29.9.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.29.9.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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 X20 system modules • Digital output modules • X20DOF322

4.15.30 X20DOF322

4.15.30.1 General information

The X20DOF322 module is equipped with 16 outputs for 1-wire connections. The X20DOF322 is designed for
source output wiring.
• 16 digital outputs
• Source connection
• 1-wire connections
• Integrated output protection

4.15.30.2 Order data

Model number Short description Figure

Digital output modules
X20DOF322 X20 digital output module, 16 outputs, 24 VDC, 0.5 A, source,
1-wire connections
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB1F X20 terminal block, 16-pin, 24 VDC keyed

Table 420: X20DOF322 - Order data

4.15.30.3 Technical data

Product ID X20DOF322
Short description
I/O module 16 digital outputs 24 VDC for 1-wire connections
General information
B&R ID code 0xC0EA
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, with status LED and software status (output error status)
Power consumption
Bus 0.28 W
Internal I/O 0.95 W
Additional power dissipation caused by the actua- 0.56 W
tors (resistive) [W] 1)
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GOST-R In preparation
Digital outputs
Design FET positive switching
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.5 A
Total nominal current 8.0 A
Connection type 1-wire connections
Output circuit Source
Output protection Thermal cutoff for overcurrent or short circuit (see value "Peak short circuit current")
Internal inverse diode for switching ind. loads (see section "Switching inductive loads")
Diagnostic status Output monitoring with 10 ms delay
Leakage current when switched off 5 µA
RDS(on) 140 mΩ

Table 421: X20DOF322 - Technical data

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X20 system modules • Digital output modules • X20DOF322
Product ID X20DOF322
Max. continuous current 6.0 A
Peak short circuit current <3 A
Switching on after overload or short circuit cutoff Ca. 10 ms (depends on the module temperature)
Switching delay 2)
0 -> 1 <300 µs
1 -> 0 <300 µs
Switching frequency
Resistive load 2) Max. 500 Hz
Inductive load See section "Switching inductive loads"
Braking voltage when switching off inductive loads Typ. 45 VDC
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB1F terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5 +0.2 mm

Table 421: X20DOF322 - Technical data

1) Number of outputs x RDS(on) x Nominal output current2 (A calculation example can be found on the B&R website in the download area for the module.)
2) At loads ≤ 1 kΩ

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 X20 system modules • Digital output modules • X20DOF322

4.15.30.4 Status LEDs

Figure LED Color Status Description

S Green Off Module supply not connected
Single flash Reset mode
Blinking PREOPERATIONAL mode
On RUN mode
Red Off Module supply not connected or everything OK
Single flash Warning/Error on an I/O channel. Level monitoring for digital outputs has been
triggered.
Red on / Green single flash Invalid firmware
1 - 16 Orange Output status of the corresponding digital output

Table 422: Status LEDs

4.15.30.5 Pinout

S 1 2
3 4

X20 DO F322
5 6
7 8
9 10
11 12
13 14
15 16

DO 1 DO 2
DO 3 DO 4
DO 5 DO 6
DO 7 DO 8
DO 9 DO 10
DO 11 DO 12
DO 13 DO 14
DO 15 DO 16

Figure 410: Pinout

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4.15.30.6 Connection example

DO

Actuator 1 Actuator 2

Actuator 3 Actuator 4

Actuator 5 Actuator 6

Actuator 7 Actuator 8

Actuator 9 Actuator 10

Actuator 11 Actuator 12

Actuator 13 Actuator 14

Actuator 15 Actuator 16

+24 VDC +24 VDC

GND GND

GND GND

Figure 411: Connection example

Caution!
If the module is operated outside of specifications, the output current can increase above the maximum
permissible nominal current. This applies to individual channels and also to the summation current
for the module.
Therefore sufficient cable cross sections or external safety measures must be used.

4.15.30.7 Output circuit diagram

24 V GND

Reverse polarity
protection
24 V

High-side 1 GND
Output status
Logic
Output x

GND

Output I/O status

monitoring LED (orange)

Figure 412: Output circuit diagram

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 X20 system modules • Digital output modules • X20DOF322

4.15.30.8 Switching inductive loads

Environmental temperature: 55°C, all outputs with the same load

100 H 10 H 1H
1000
Switching voltage:

28.8 V
24.0 V

100 mH

Coil resistance Coil inductance

[Ω]

10 mH
100

50
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Environmental temperature: 60°C, all outputs with the same load

100 H 10 H 1H
1000
Switching voltage:

28.8 V
24.0 V
100 mH

Coil resistance Coil inductance

[Ω]
10 mH

100

50
0.1 1 10 100
Max. switching cycles / second
(with 90% duty cycle)

Information:
If the maximum number of operating cycles per second is exceeded, an external inverse diode must
be used.
Operating conditions outside of the area in the diagram are not permitted!

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4.15.30.9 Register description

4.15.30.9.1 Function model 0 - Standard

Register Fixed offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
0 DigitalOutput UINT ●
2 0 Switching state of digital outputs 1 to 8 USINT
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
3 1 Switching state of digital outputs 9 to 16 USINT
DigitalOutput09 Bit 0
... ...
DigitalOutput16 Bit 7
2 StatusDigitalOutput UINT ●
30 2 Status of digital outputs 1 to 8 USINT
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
31 3 Status of digital outputs 9 to 16 USINT
StatusDigitalOutput09 Bit 0
... ...
StatusDigitalOutput16 Bit 7

Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.

4.15.30.9.2 Function model 254 - Bus Controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
2 0 Switching state of digital outputs 1 to 8 USINT ●
DigitalOutput01 Bit 0
... ...
DigitalOutput08 Bit 7
3 1 Switching state of digital outputs 9 to 16 USINT
DigitalOutput09 Bit 0
... ...
DigitalOutput16 Bit 7
30 - Status of digital outputs 1 to 8 USINT ●
StatusDigitalOutput01 Bit 0
... ...
StatusDigitalOutput08 Bit 7
31 - Status of digital outputs 9 to 16 USINT
StatusDigitalOutput09 Bit 0
... ...
StatusDigitalOutput16 Bit 7

1) The offset specifies where the register is within the CAN object.

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4.15.30.9.3 Digital outputs

The output status is transferred to the output channels with a fixed offset (<60 µs) in relation to the network cycle
(SyncOut).

4.15.30.9.3.1 Switching state of digital outputs 1 to 16

Name:
DigitalOutput or
DigitalOutput01 to DigitalOutput16
The switching state of digital outputs 1 to 16 are stored in this register.
Data type Value
UINT Packed "DigitalOutput" values
USINT See bit structure

Bit structure:
Register 2, Offset 0:
Bit Name Value Information
0 Digital output 01 reset
0 DigitalOutput01
1 Digital output 01 set
... ...
0 Digital output 08 reset
7 DigitalOutput08
1 Digital output 08 set

Register 3, Offset 1:
Bit Name Value Information
0 Digital output 09 reset
0 DigitalOutput09
1 Digital output 09 set
... ...
0 Digital output 16 reset
7 DigitalOutput16
1 Digital output 16 set

The "packed outputs" setting in the AS I/O configuration is used to determine whether all of these registers' bits
should be set up individually as data points in the AS I/O mapping ("DigitalOutput01" through "DigitalOutput16") or
whether these registers should be displayed as an individual UINT data point ("DigitalOutput").

4.15.30.9.4 Monitoring status of the digital outputs

On the module, the output states of the outputs are compared to the setpoint states. The control of the output
driver is used for the setpoint states.
A change in the output state resets monitoring for that output. The status of each individual channel can be read.
A change in the monitoring status generates an error message.

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4.15.30.9.4.1 Status of digital outputs 1 to 16

Name:
StatusDigitalOutput or
StatusDigitalOutput01 to StatusDigitalOutput16
The status of digital outputs 1 to 16 is mapped in this register.
Data type Value
UINT Packed "StatusDigitalOutput" values
USINT See bit structure

Bit structure:
Register 30, Offset 1:
Bit Name Value Description
0 Channel 01: No error
0 StatusDigitalOutput01
1 Channel 01: Short circuit or overload
... ...
0 Channel 08: No error
7 StatusDigitalOutput08
1 Channel 08: Short circuit or overload

Register 31, Offset 2:

Bit Name Value Information
0 Channel 09: No error
0 StatusDigitalOutput09
1 Channel 09: Short circuit or overload
... ...
0 Channel 16: No error
7 StatusDigitalOutput16
1 Channel 16: Short circuit or overload

The "packed outputs" setting in the AS I/O configuration is used to determine whether all of these registers' bits
should be set up individually as data points in the AS I/O mapping ("StatusDigitalOutput01" through "StatusDigi-
talOutput16") or whether these registers should be displayed as an individual UINT data point ("StatusDigitalOut-
put").

4.15.30.9.5 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

4.15.30.9.6 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
Equal to the minimum cycle time

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 X20 system modules • Digital signal processing modules • Brief information

4.16 Digital signal processing modules

The highly flexible digital signal processor modules can be implemented for a wide range of tasks involving the
creation or processing of digital signals.

4.16.1 Brief information

Product ID Short description on page
X20CM1201 X20 combination module, 1 AB incremental encoder, 24 V, 4 digital inputs 24 V, 4 channels 24 V configurable 1312
as inputs or outputs, flexible digital controller logic
X20DC1073 X20 digital counter module, 1x SinCos, 1 Vss, 400 kHz input frequency, encoder monitoring, NetTime module 1332
X20DS1828 X20 digital signal module, 1x HIPERFACE, NetTime module 1337
X20DS1928 X20 digital signal module, 1x EnDat 2.1/2.2, NetTime module 1399

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X20 system modules • Digital signal processing modules • X20CM1201

4.16.2 X20CM1201

4.16.2.1 General information

The module can be used to configure and carry out simple movements. For this purpose, the module has one AB
encoder input and a total of 8 digital channels. Four of them are inputs, and the other 4 can be set as either an
input or an output. Various output bit patterns are stored directly in the module.
The module is perfectly suited for easy to create drive control tasks for program and event controlled motor move-
ments. Feed movements using drives with 2 speeds and forward/reverse movement are created easily and effi-
ciently.
• Command-dependent digital pattern output
• Counter-dependent output circuit
• Event-controlled abort criteria
• 4 digital inputs
• 4 digital channels, configurable as inputs or outputs

4.16.2.2 Order data

Model number Short description Figure

Digital signal processing and preparation
X20CM1201 X20 combination module, 1 AB incremental encoder, 24 V, 4
digital inputs 24 V, 4 channels 24 V configurable as inputs or
outputs, flexible digital controller logic
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 423: X20CM1201 - Order data

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 X20 system modules • Digital signal processing modules • X20CM1201

4.16.2.3 Technical data

Product ID X20CM1201
Short description
I/O module 1 AB incremental encoder, 24 V, 4 digital inputs, 4 channels configurable as inputs or outputs
General information
Input voltage 24 VDC -15% / +20%
B&R ID code 0x21EF
Status indicators I/O function per channel, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
Outputs Yes, using the status LED and software (output error status)
Power consumption
Bus 0.01 W
Internal I/O 1.5 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Type of signal lines Shielded cables must be used for all signal lines.
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Digital inputs
Quantity 4 + 4 additional channels, configurable as inputs or outputs
Nominal voltage 24 VDC
Input voltage 24 VDC -15% / +20%
Input current at 24 VDC Approx. 1.3 mA
Input filter
Hardware ≤2 μs
Software -
Connection type 1-wire connections
Input circuit Sink
Input resistance 18.4 kΩ
Switching threshold
Low <5 VDC
High >15 VDC
Isolation voltage between channel and bus 500 Veff
AB incremental encoder
Quantity 1
Encoder inputs 24 V, asymmetrical
Counter size 32-bit
Input frequency Max. 100 kHz
Evaluation 4x
Encoder supply Module-internal, max. 600 mA
Overload behavior of the encoder supply Short circuit protection, overload protection
Digital outputs
Design Push / Pull / Push-Pull
Quantity Up to 4, configurable as inputs or outputs using software
Nominal voltage 24 VDC
Switching voltage 24 VDC -15% / +20%
Nominal output current 0.1 A
Total nominal current 0.4 A
Connection type 1-wire connections
Output circuit Sink or source
Output protection Thermal cutoff if overcurrent or short circuit occurs, integrated protection for switching inductances
Actuator supply Module-internal, max. 600 mA
Diagnostic status Output monitoring
Leakage current when switched off Max. 25 µA
Residual voltage <0.9 V at 0.1 A rated current
Peak short circuit current <10 A
Switching on after overload or short circuit cutoff Approx. 10 ms (depends on the module temperature)
Switching delay
0 -> 1 <2 µs
1 -> 0 <2 µs
Switching frequency
Resistive load Max. 24 kHz
Inductive load See section "Switching inductive loads" (at 90% duty cycle).
Braking voltage when switching off inductive loads Switching voltage + 0.6 VDC

Table 424: X20CM1201 - Technical data

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X20 system modules • Digital signal processing modules • X20CM1201
Product ID X20CM1201
Isolation voltage between channel and bus 500 Veff
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5+0.2 mm

Table 424: X20CM1201 - Technical data

4.16.2.4 LED status indicators

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset status
1-8 Green Status of the corresponding digital signal

1) Depending on the configuration, a firmware update can take up to several minutes.

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 X20 system modules • Digital signal processing modules • X20CM1201

4.16.2.5 Pinout

Shielded cables must be used for all signal lines.

r e

X20 CM 1201
1 5
2 6
3 7
4 8

Channel 1 Channel 5

Channel 2 Channel 6

Channel 3 Channel 7

Channel 4 Channel 8

Encoder 24 V + Encoder 24 V +

GND GND

4.16.2.6 Connection example

CM

End neg
A +24 VDC
Motion neg
B GND
End pos
R +24 VDC
Fast/Slow Motion pos
GND
GND

+24 VDC +24 VDC

GND GND

4.16.2.7 Input circuit diagram

Input x

VDR
Input status

I/O status

24 V
PTC
Encoder 24 V LED (green)

GND

GND

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4.16.2.8 Output circuit diagram

24 V

Output status Push

PTC
Output x

VDR
Output status Pull

GND
Output
monitoring

4.16.2.9 Switching inductive loads

100 H 10 H 1H
1000
0.1 H

Coil resistance
Coil inductance
[Ω]

0.01 H
240 Ω ≙ 100 mA
0.1 1 10 100 1000 10000

Max. switching cycles / second

(with 90% duty cycle)

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4.16.2.10 Register description

4.16.2.10.1 Function model 0 - Standard

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Configuration
130 CycleTimeCff ●
Communication - Command interface
1 SendCommand USINT ●
3 SendCommandParam USINT ●
12 SendData DINT ●
1 ReadStatus USINT ●
3 ReadIndex USINT ●
12 ReadData DINT ●
Communication - Display register
20 ABRposition DINT ●
28 TargetARBposition DINT ●
36 ErrorInfo UDINT ●
47 Status of the digital inputs USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
55 Status of encoder supply USINT ●
PowerSupply01 Bit 0

4.16.2.10.2 Function model 254 - Bus controller

Register Offset1) Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Configuration
130 - CycleTimeCff ●
Communication - Command interface
1 1 SendCommand USINT ●
3 0 SendCommandParam USINT ●
12 4 SendData DINT ●
1 1 ReadStatus USINT ●
3 0 ReadIndex USINT ●
12 4 ReadData DINT ●
Communication - Display register
20 - ABRposition DINT ●
28 - TargetABRposition DINT ●
36 - ErrorInfo UDINT ●
47 - Status of the digital inputs USINT ●
DigitalInput01 Bit 0
... ...
DigitalInput08 Bit 7
55 - Status of encoder supply USINT ●
PowerSupply01 Bit 0

1) The offset specifies the position of the register within the CAN object.

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4.16.2.10.3 General

This is a low-end positioning module that supports 2 speed movements in positive and negative directions. No
active position check is performed. The movements are started using a command interface and stopped by the
position comparator (target position) or user-defined trigger conditions (input edge/ comparison). Every movement
step is time-monitored. Up to 8 movement steps can be linked to form one continuous movement.
Position, input states and timeout periods are checked during each system cycle.

4.16.2.10.3.1 Types of movement

The module supports the following types of movement:

• Negative direction - fast
• Negative direction - slow
• Stop
• Positive direction - slow
• Positive direction - fast
The initial state of each type of movement is defined by the user. In order to avoid false input levels on the motor
(caused by signal runtimes), and ensure timing (e.g. during direction change), there are additional command pa-
rameters to describe a operating mode change:
• 0x93 Negative directional setup state
• 0x88 Negative directional setup time
• 0x8A Negative directional stop time
• 0x95 Positive direction setup state
• 0x89 Positive direction setup time
• 0x8B Positive direction stop time
• 0x94 Stop state

Information:
No directional stop state is defined. To allow error handling, the directional stop state must be the
same as STOP. Speed changes in the same direction of movement are not evaluated as changes in the
operating mode of the movement.

4.16.2.10.3.2 Movement blocks

The module supports 4 movement blocks: Each movement block contains up to 8 movement steps. Each step is
comprised of the following parameters:
• Target position - relative or absolute
• Timeout or delay
• Trigger condition - edge or comparator value (signal level)
A block's movement steps can be executed as one continuous movement. The following parameters must be
configured before the movement start command is issued:
• Step activation
• Step target position interpolation - relative or absolute
• Step speed - slow or fast
• Trigger mode - off or "Comparator value = true" or "Comparator value = false"

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4.16.2.10.3.3 Movement generator

When a movement start command is issued, the mode of the active movement step is calculated based on the
preceding target position. Step parameters may also be changed after the start as long as the step direction is
not changed. Otherwise a movement error occurs. To ensure correct directional interpretation, the movement step
position/range is limited to ±1073741824.
The target position of a step configured with a trigger is evaluated as the end position (error position). This means
the position at the time of the trigger condition becomes the effective target position. Because this position is
unknown when the calculation is made by the movement generator, the set end position is used for calculating the
next absolute movement step. As a result, it is recommended to proceed with a relative movement step following a
triggered step. A successive absolute movement step must be outside the positioning range of the triggered step.
If a movement step is configured as a standstill, i.e. relative position = 0, or the new absolute position = previous
target position, a delay has occurred. If no trigger is configured, the parameter step timeout is evaluated as a simple
delay time and not as an error state.

4.16.2.10.3.4 Tolerance monitoring

The module constantly monitors the position tolerance, even when no movements are active. Jitter and overshoot
tolerances must be configured for both directions. Depending on the previous movement direction, a tolerance
window is calculated based on the current target position. Because the movement generator uses the last target
position, movements within the tolerance window must be avoided to prevent errors from occurring.

4.16.2.10.3.5 Homing

Homing is not implemented in this module as a movement function. The target position of a completed movement
can be applied as the home position via command.

4.16.2.10.3.6 Safety monitoring

A safe input status (masks and comparator values) for positive and negative movements must be configured.
Software end positions – minimum and maximum positions – can also be configured for both directions.
The module monitors these two positions from the time the parameter 0x93 or 0x95 "Positive directional setup
state" is set. Monitoring is ended when the parameter 0x94 "Stop state" is set.
Because a trigger condition aborts the movement step before a safety check, a hardware limit switch can also be
used as a trigger condition without generating an error.

4.16.2.10.4 Command description

4.16.2.10.4.1 No action

This command can be used as a placeholder during development or to separate 2 identical commands.
Code 0x00
Parameter 0
Data 0 to 3 0

4.16.2.10.4.2 Configure display mode

This command can be used to configure how the values in the 4.16.2.10.5.6 "Read parameter number" and
4.16.2.10.5.7 "Read parameter data" registers are displayed. Up to 4 display values can be displayed simultane-
ously. Possible selections include the command parameters 0xC0 = current position, to 0xC3 = I/O states.
Code 0x01
Parameter Display control:
0 Scheduler off; Data 0 used for display
1 Scheduler cycle = X2X cycle; The next display cycle starts with each X2X cycle
2 Scheduler cycle = Command cycle; The next display cycle starts with each completed command
Data 0 Parameter number of display cycle 1 (Default: 0xC0 = current position)
... ...
Data 3 Parameter number of display cycle 4 (Default: 0xC0 = current position)

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4.16.2.10.4.3 Enables the interface

This command activates the movement interface. The status of the interface is displayed in the 4.16.2.10.5.5
"Read status" register (bit 5). The interface is disabled following a reset. This is necessary to ensure a consistent
parameter field.
Code 0x02
Parameter 0
Data 0 to 3 0

4.16.2.10.4.4 Configure parameters

Code 0x03
Parameter See parameter list
Data 0 to 3 Parameter data

Parameter list
Parameter Description Parameter format
Movement blocks
Calculating the address: Addr = (BlockN - 1) * 32 + (StepN - 1) * 8
BlockN = 1 to 4
StepN = 1 to 8
Addr Movement BlockN StepN: Position (relative or absolute) DINT value
Addr + 1 Movement BlockN StepN: Timeout or delay Time format
Addr + 2 Movement BlockN StepN: Trigger condition (edge or comparator value) Trigger condition
Addr + 3 Movement BlockN StepN: Debug information (read only) 0
Configuration
0x80 Jitter tolerance negative (must be a negative value) Time format
0x81 Jitter tolerance positive (must be a positive value) Time format
0x82 Overshoot tolerance negative (must be a negative value) Time format
0x83 Overshoot tolerance positive (must be a positive value) Time format
0x84 - 0x87 Reserved
0x88 Setup time - negative direction Time format
0x89 Setup time - positive direction Time format
0x8a Stop time - negative direction Time format
0x8b Stop time - positive direction Time format
0x8C - 0x8F Reserved
0x90 Output configuration (push/pull) Output configuration
0x91 Output state - negative direction, high speed Output states
0x92 Output state - negative direction, low speed Output states
0x93 Output state, negative direction - setup Output states
0x94 Output state - stop Output states
0x95 Output state, positive direction - setup Output states
0x96 Output state - positive direction, low speed Output states
0x97 Output state - positive direction, high speed Output states
0x98 Safe input state - negative direction Safe input states
0x99 Safe input state - positive direction Safe input states
0x9A - 0x9B Reserved
0x9C Safe minimum position - negative direction DINT value
0x9D Safe maximum position - negative direction DINT value
0x9E Safe minimum position - positive direction DINT value
0x9F Safe maximum position - positive direction DINT value
0xA0 - 0xBF Reserved
Status indicators
0xC0 Current position 0
0xC1 Target position 0
0xC2 Error information 0; Error information
0xC3 I/O states 0; I/O states
0xC4 - 0xFF Reserved

Parameter formats used

DINT value
The possible values depend on the respective command.
Data type Value
DINT -2,147,483,648 to 2,147,483,647

Time format
Time in microseconds. System resolution is a result of the system cycle time (default: 50 μs).

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Trigger condition
Depending on bits 2 and 3 in the data structure of each movement block, either the "edge" or "comparator value"
structure is selected as the trigger condition.
Edge
Bit Description Value Information
0 Falling edge - channel 01 0 Disabled
1 Enabled
... ...
7 Falling edge - channel 08 0 Disabled
1 Enabled
8 - 15 Reserved 0
16 Rising edge - channel 01 0 Disabled
1 Enabled
.. ...
23 Rising edge - channel 08 0 Disabled
1 Enabled
24 - 31 Reserved 0

Comparator value
Bit Description Value Information
0 Activation mask - channel 01 0 Disabled
1 Enabled
... ...
7 Activation mask - channel 08 0 Disabled
1 Enabled
8 - 15 Reserved 0
15 Comparative state - channel 01 0 or 1
...
23 Comparative state - channel 08 0 or 1
24 - 31 Reserved 0

Output configuration
Bit Description Value Information
0-1 Reserved 0
2 Push driver - channel 02 0 Disabled
1 Enabled
3 Push driver - channel 02 0 Disabled
1 Enabled
4-5 Reserved 0
6 Push driver - channel 04 0 Disabled
1 Enabled
7 Pull driver - channel 04 0 Disabled
1 Enabled
8-9 Reserved 0
10 Push driver - channel 06 0 Disabled
1 Enabled
11 Pull driver - channel 06 0 Disabled
1 Enabled
12 - 13 Reserved 0
14 Push driver - channel 08 0 Disabled
1 Enabled
15 Pull driver - channel 08 0 Disabled
1 Enabled
16 - 31 Reserved 0

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Output states
Bit Description Value Information
0 Reserved 0
1 Channel 02 0 No action
1 Clear channel
2 Reserved 0
3 Channel 04 0 No action
1 Clear channel
4 Reserved 0
5 Channel 06 0 No action
1 Clear channel
6 Reserved 0
7 Channel 08 0 No action
1 Clear channel
8 - 16 Reserved 0
17 Channel 02 0 No action
1 Set channel
18 Reserved 0
19 Channel 04 0 No action
1 Set channel
20 Reserved 0
21 Channel 06 0 No action
1 Set channel
22 Reserved 0
23 Channel 08 0 No action
1 Set channel
24 - 31 Reserved 0

Safe input states

Bit Description Value Information
0 Activation mask - channel 01 0 Disabled
1 Enabled
... ...
7 Activation mask - channel 08 0 Disabled
1 Enabled
8 - 15 Reserved 0
15 Comparative state - channel 01 0 or 1
...
23 Comparative state - channel 08 0 or 1
24 - 31 Reserved 0

Error information
This table shows the read display value. The parameter for the display command is 0.
Bit Description Value Information
0 Tolerance error - negative 0 No error
1 Error occurred
1 Tolerance error - positive 0 No error
1 Error occurred
2 Timeout 0 No timeout
1 Timeout
3-7 Reserved 0
8 Safety monitoring error Inputs (hardwire limit switch) 0 No error
1 Error occurred
9 Safety monitoring error Position (software end position) 0 No error
1 Error occurred
10 - 15 Reserved 0
16 - 18 Error status information 000 Reserved
001 Negative directional stop state
010 Negative movement
011 Negative directional setup state
100 Stop state
101 Positive directional setup state
110 Positive movement
111 Positive directional stop state
19 Reserved 0
20 - 24 Invalid step number 000 to 111 Number of the step that does not contain any movement infor-
mation.
1000 Inactive movement step (tolerance check)
25 - 31 Reserved 0

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I/O states
This table shows the read display value. The parameter for the display command is 0.
Bit Description Value Information
0 Input state - channel 01 0 or 1
... ...
7 Input state - channel 08 0 or 1
8 - 16 Reserved 0
17 Output state - channel 02 0 or 1
18 Reserved 0
19 Output state - channel 04 0 or 1
20 Reserved 0
21 Output state - channel 06 0 or 1
22 Reserved 0
23 Output state - channel 08 0 or 1
24 - 31 Reserved 0

4.16.2.10.4.5 Configure counters

This command can be used to assign the hardware channels to the AB counter. With an ABR counter, the R input
can be connected to any hardware channel as the trigger signal.
Code 0x04
Parameter See parameter structure
Data 0 See data structure
Data 1 to 3 0

Parameter structure:
Bit Description Value Information
0-1 Counter connection pair 00 Pair 1 (A: channel 01, B: channel 02)
01 Pair 2 (A: channel 03, B: channel 04)
10 Pair 3 (A: channel 05, B: channel 06)
11 Pair 4 (A: channel 07, B: channel 08)
2-7 Reserved 0

Data structure:
Bit Description Value Information
0-1 Counter mode 00 AB encoder: Up/down counter (A: timing, B: up/down signal)
01 Edge counter - channel A
10 Reserved
11 Edge counter - channel B
2 Counting direction 0 Positive
1 Negative
3-7 Reserved 0

4.16.2.10.4.6 Homing

Assumes the target position of the last successful movement step as a reference position.
Code 0x05
Parameter 0
Data 0 to 3 Home position

4.16.2.10.4.7 Stops the movement.

The movement step in progress is stopped. This command always results in a movement error.
Code 0x06
Parameter 0
Data 0 to 3 0

4.16.2.10.4.8 Acknowledge movement error

The movement error is is cleared. If this command is executed when the error is still present, the current position
is assumed as the target position. The basis of the relative position becomes unclear.
Code 0x07
Parameter 0
Data 0 to 3 0

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4.16.2.10.4.9 Start a movement block

This command starts a movement block consisting of up to 8 steps.

Code 0x08 (Block 1)
0x09 (Block 2)
0x0A (Block 3)
0x0B (Block 4)
Parameter See parameter structure
Data 0 to 3 See data structure

Parameter structure:
Bit Description Value Information
0 Step 1 0 No movement.
1 Perform movement step.
... ...
7 Step 8 0 No movement.
1 Perform movement step.

Data structure:
Bit Description Value Information
0 Step 1 position setting: 0 Relative
1 Absolute
1 Step 1 speed: 0 Slow
1 Fast
2-3 Step 1 trigger mode: 00 No trigger
01 Edge trigger
10 Comparator value "true"
11 Comparator value "false"
4-7 Step 2 x Like step 1 / Bits 0 to 2
...
28 - 31 Step 8 x Like step 1 / Bits 0 to 2

4.16.2.10.4.10 Selecting the debug information

At the end of each movement step, the command parameter "Addr + 3" (see 4.16.2.10.4.4 "Movement blocks -
Calculating the address" can be used to read the debug information selected in this register. This debug information
is shown in the 4.16.2.10.5.6 "Read parameter number" and 4.16.2.10.5.7 "Read parameter data" registers.
Code 0x00
Parameter 0 Error information (default)
1 Timestamp
2 Current position
3 Target position
Data 0 to 3 0

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4.16.2.10.5 Command interface

A command interface is available to the user. A command consists of:

• 4.16.2.10.5.2 "Command" (in the command description: code)
• 4.16.2.10.5.3 "Command parameter" (in the command description: parameters)
• 4.16.2.10.5.4 "Command data" (in the command description: Data 0 to 3)
The following commands can be executed:
• 4.16.2.10.4.1 "No action"
• 4.16.2.10.4.2 "Configure display mode"
• 4.16.2.10.4.3 "Enable the interface"
• 4.16.2.10.4.4 "Configure parameters"
• 4.16.2.10.4.5 "Configure counters"
• 4.16.2.10.4.6 "Perform homing"
• 4.16.2.10.4.7 "Stop the movement"
• 4.16.2.10.4.8 "Acknowledge movement error"
• 4.16.2.10.4.9 "Start a movement block"
• 4.16.2.10.4.10 "Select debug information"
The module returns:
• 4.16.2.10.5.5 "System status"
• 4.16.2.10.5.6 "Displays parameter number"
• 4.16.2.10.5.7 "Displays data content"
The module detects a new command through a change in the command register. The toggle bit must be changed
in order to detect when the command issued in the 4.16.2.10.5.5 "System status" register is applied. Identical
commands can be executed immediately following one another simply by changing the toggle bit.

4.16.2.10.5.1 Execution of a command

Commands must be sent by the application using the command interface. Due to the simple structure of the
command interface, it is also possible to send them via CAN.
All commands are executed as follows:
1 Write command parameters and command data to the respective register.
2 Write command with changed toggle bit.
When bit 7 in the command register is toggled, the module executes the comand with the command para-
meters and command data.
3 Wait until bit 7 in the response register (System Status) matches bit 7 in the command register.
4 Read additional status information from the response register if necessary.
5 If additional commands should be sent, proceed with step 1.

4.16.2.10.5.2 Send command

Name:
SendCommand
The commands described under 4.16.2.10.4 "Command description" can be sent from this register. Bit 7 must be
toggled to apply the commands.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-6 Command code x
7 Toggle bit for applying a new command x

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4.16.2.10.5.3 Send command parameters

Name:
SendCommandParam
Specific parameters for the command to be sent must be entered in this register. The required parameters are
listed under 4.16.2.10.4 "Command description" for the respective commands.
Data type Value Information
USINT x Command parameter

4.16.2.10.5.4 Send command data

Name:
SendData
Specific parameters for the command to be sent must be entered in this register. The required data is listed under
4.16.2.10.4 "Command description" for the respective commands.
Data 0 to 3 are sent as a single DINT value. The following structure is used:

Data 3 Data 2 Data 1 Data 0

Bit 31 24 16 8 0

Data type Value Information

DINT x Command data 0 to 3

4.16.2.10.5.5 Read status

Name:
ReadStatus
The commands and the current status can be checked in this register. Bit 7 can be used to check whether an
issued command has been applied.
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0-1 Reserved 0
2 Position 0 Not yet reached
1 Reached
3 Motion 0 In motion
1 completed
4 Numerator 0 Not yet configured
1 Configured
5 Interface 0 Not enabled
1 Enabled
6 Command 0 No error
1 Error occurred
7 Command toggle bit x Value that was read

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4.16.2.10.5.6 Read parameter number

Name:
ReadIndex
The parameter number returned for a display command is shown in this register. See 4.16.2.10.4.2 "Configure
display mode" and 4.16.2.10.4.10 "Selecting the debug information"
Data type Value Information
USINT x Parameter numbers

4.16.2.10.5.7 Read parameter data

Name:
ReadData
The parameter data returned for a display command is shown in this register. See 4.16.2.10.4.2 "Configure display
mode" and 4.16.2.10.4.10 "Selecting the debug information"
Data type Value Information
DINT x Parameter data

4.16.2.10.5.8 Special display parameters

The following 4 registers correspond to display parameters 0xC0 to 0xC3 in the command description 4.16.2.10.4.4
"Configure parameters". This frees up the 4.16.2.10.5.7 "ReadData" register for other data.

Indicates the current position.

Name:
ABRPosition
This register shows the current position in the current step. It corresponds with the parameter 0xC0 in section
4.16.2.10.4.4 "Configure parameters".
Data type Value
DINT -2,147,483,648 to 2,147,483,647

Indicates the current target position

Name:
TargetABRposition
This register shows the target position of the current step. It corresponds with the parameter 0xC1 in section
4.16.2.10.4.4 "Configure parameters".
Data type Value
DINT -2,147,483,648 to 2,147,483,647

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Displays the error information

Name:
ErrorInfo
The error information is shown in this register. It corresponds with the parameter 0xC2 in section 4.16.2.10.4.4
"Configure parameters".
Data type Value
UDINT See bit structure.

Bit structure:
Bit Description Value Information
0 Tolerance error - negative 0 No error
1 Error occurred
1 Tolerance error - positive 0 No error
1 Error occurred
2 Timeout 0 No timeout
1 Timeout
3-7 Reserved 0
8 Safety monitoring error Inputs (hardwire limit switch) 0 No error
1 Error occurred
9 Safety monitoring error Position (software end position) 0 No error
1 Error occurred
10 - 15 Reserved 0
16 - 18 Error status information 000 Reserved
001 Negative directional stop state
010 Negative movement
011 Negative directional setup state
100 Stop state
101 Positive directional setup state
110 Positive movement
111 Positive directional stop state
19 Reserved 0
20 - 24 Invalid step number 000 to 111 Number of the step that does not contain any movement infor-
mation.
1000 Inactive movement step (tolerance check)
25 - 31 Reserved 0

Status of the digital inputs

Name:
DigitalInput01 to DigitalInput08
The status of the digital inputs or read outputs are shown in this register. It corresponds with the parameter 0xC3
in section 4.16.2.10.4.4 "Configure parameters".
Data type Value
USINT See bit structure.

Bit structure:
Bit Description Value Information
0 DigitalInput01 0 or 1 Input status - channel 1
... ...
7 DigitalInput08 0 or 1 Input status - channel 8

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4.16.2.10.6 Sample configurations

4.16.2.10.6.1 Movement example

The channels have been set as follows for this example:

Hardware channel Direction Function assignment
1 Input ABR encoder - signal A
2 Input ABR encoder - signal B
3 Input ABR encoder - signal R
4 Output Fast speed
5 Input Negative limit switch
6 Output Negative direction
7 Input Positive limit switch
8 Output Positive direction

Enable interface
Value Description
Code 0x02
Parameter 0
Data 0 to 3 0

Configure parameters
Value
Code 0x03
Parameter Parameter numbers
Data 0 to 3 Parameter data

The following parameters must be configured:

Parameter Data Description
0x80 APPL Negative jitter tolerance [µs] (application-specific)
0x81 APPL Positive jitter tolerance [µs] (application-specific)
0x82 APPL Negative overshoot tolerance [µs] (application-specific)
0x83 APPL Positive overshoot tolerance [µs] (application-specific)

0x88 APPL Negative setup time [µs] (application-specific)

0x89 APPL Positive setup time [µs] (application-specific)
0x8A APPL Negative stop time [µs] (application-specific)
0x8B APPL Positive stop time [µs] (application-specific)

0x90 0x0000CCC0 Output configuration: Channel 04, channel 06, channel 08 as push/pull outputs
0x91 0x00280080 Output states - fast negative movement: Set channels 04 and 06, clear channel 08
0x92 0x00200088 Output states - slow negative movement: Set channel 06, clear channels 04 and 08
0x93 0x000000A8 Output states - negative setup: Clear channels 04, 06 and 08
0x94 0x000000A8 Output states - stop: Clear channels 04, 06 and 08
0x95 0x000000A8 Output states - positive setup: Clear channels 04, 06 and 08
0x96 0x00800028 Output states - slow positive movement: Set channel 08, clear channels 04 and 06
0x97 0x00880020 Output states - fast positive movement: Set channels 04 and 08, clear channel 06

0x98 0x00100010 Safe input state - negative: Channel 05 active, status of channel 05 (level) = 1
0x99 0x00400040 Safe input state - positive: Channel 07 active, status of channel 05 (level) = 1 Code 0x04

Configure counters
Value Description
Code 0x04
Parameter 0x03 Counter pair 1
Data 0 0 AB encoder, positive direction
Data 1 to 3 0

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4.16.2.10.6.2 Homing example

Configure parameters
Value
Code 0x03
Parameter Parameter numbers
Data 0 to 3 Parameter data

The following parameters must be configured:

Parameter Data Description
0x00 0x3FFFFFFF Relative positive position maximum
0x02 0x00000040 Trigger on input state of channel 07 = 0
0x04 0xC0000001 Relative negative position maximum
0x06 0x00400040 Trigger on input state of channel 07 == 1
0x08 0xC0000001 Relative negative position maximum
0x0A 0x00000004 Trigger on falling edge of channel 03

Start movement
Value Description
Code 0x08 Block 1
Parameter 0x07 Activate steps 1 to 3
Data 0 to 3 0x00000411 Step 1: absolute, slow, trigger off
Step 2: absolute, slow, trigger off
Step 3: relative, slow, trigger on edge

Wait until the movement is complete.

Homing
Value Description
Code 0x05
Parameter 0
Data 0 to 3 x Home position

4.16.2.10.6.3 Standard positioning example

Configure parameters
Value
Code 0x03
Parameter Parameter numbers
Data 0 to 3 Parameter data

The following parameters must be configured:

Parameter Data Description
0x00 X1 Pre-stop position
0x04 X2 Stop position

Start movement
Value Description
Code 0x08 Block 1
Parameter 0x03 Activate steps 1 and 2
Data 0 to 3 0x00000011 Step 1: absolute, slow, trigger off
Step 2: absolute, slow, trigger off

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4.16.2.10.6.4 Standard positioning example with stop

Configure parameters
Value
Code 0x03
Parameter Parameter numbers
Data 0 to 3 Parameter data

The following parameters must be configured:

Parameter Data Description
0x00 X1 Pre-stop position
0x04 X2 Stop position
0x08 0 Relative movement
0x09 T_STOP Stop delay [µs]

Start movement
Value Description
Code 0x08 Block 1
Parameter 0x07 Activate steps 1 to 3
Data 0 to 3 0x00000011 Step 1: absolute, slow, trigger off
Step 2: absolute, slow, trigger off
Step 3: relative, trigger off

4.16.2.10.7 General module register

4.16.2.10.7.1 Configures the system cycle time

Name:
CycleTimeCff
This register configures the module's system cycle time.
Data type Value Information
UINT 25 to 255 System cycle time in µs (default = 50 µs)

4.16.2.10.7.2 Status of encoder supply

Name:
PowerSupply01
This register shows the status of the integrated encoder supply. A faulty encoder power supply is displayed as
a warning.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0 PowerSupply01 0 24 VDC encoder power supply OK
1 24 VDC encoder power supply faulty
1-7 Reserved -

4.16.2.10.8 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
100 µs

4.16.2.10.9 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without communication errors occurring.
It should be noted that very fast cycles decrease the idle time available for handling monitoring, diagnostics and
acyclic commands.
Minimum cycle time
100 μs

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4.16.3 X20DC1073

4.16.3.1 General information

The module is equipped with a SinCos encoder interface. The input signals are monitored. This makes it possible
to detect open or shorted lines as well as encoder supply failures.
• SinCos encoder interface
• Encoder input monitoring
• 5 VDC and GND for encoder supply
• NetTime function: Timestamp for position
SinCos encoders
SinCos encoders with 1 Vss are mostly used in linear drives and systems with high-resolution optical or magnetic
position measurement systems. The module can process input signals with a frequency of up to 400 kHz.
NetTime position timestamp
Highly dynamic positioning tasks require not only the position value, but also the exact time at which the position
was determined. The module has a NetTime function for this, which adds a timestamp to the recorded position
with microsecond accuracy.
The module provides the PLC with the position value and timestamp as absolute time value. The NetTime mech-
anisms ensure that the PLC NetTime clock and the local NetTime clock on the module have exactly the same
absolute time at all times.

4.16.3.2 Order data

Model number Short description Figure

Digital signal processing and preparation
X20DC1073 X20 digital counter module, 1x SinCos, 1 Vss, 400 kHz input
frequency, encoder monitoring, NetTime module
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 425: X20DC1073 - Order data

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4.16.3.3 Technical data

Product ID X20DC1073
Short description
I/O module 1x SinCos input
General information
B&R ID code 0xAEC6
Status indicators Counting direction, operating status, module status
Diagnostics
Module run/error Yes, using status LED and software
Counting direction Yes, using status LED
Power consumption
Bus 0.01 W
Internal I/O 1.3 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Type of signal lines Shielded cables must be used for all signal lines
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Encoder inputs
Type SinCos
Angular position resolution 13-bit, with a 1 VSS signal
Encoder monitoring Yes
Max. encoder cable length Max. 20 m, see "Calculation of the maximum encoder cable length"
Sine/Cosine inputs
Signal transmission Differential signals, symmetrical
Signal frequency DC up to 400 kHz
Differential voltage 1 VSS
Common-mode voltage Max. ±10 V
Terminating resistors 120 Ω
Encoder supply
Output voltage 5V
Min. output voltage at 300 mA 4.86 V
Load capability 300 mA
Protective measures
Overload protection Yes
Short circuit protection Yes
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating See section "Derating"
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5+0.2 mm

Table 426: X20DC1073 - Technical data

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4.16.3.4 LED status indicators

For a description of the various operating modes, see the 2.11.1 "re LEDs" section.
Figure LED Color Status Description
r Green Off No power to module
Single flash RESET mode
Double flash BOOT mode (during firmware update)1)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset state. Possible cause:
• Encoder supply error
Single flash I/O error. Possible cause:
• Sine/Cosine relative position error (open line)
Single flash, inverted Error or reset state and I/O error
UP Green On The "UP/DN" LEDs are lit depending on the rotational direction and the
speed of the connected encoder.
The "UP" LED indicates when the encoder position changes in the pos-
itive direction.
DN Green On The "DN" LED indicates when the encoder position changes in the neg-
ative direction.

1) Depending on the configuration, a firmware update can take up to several minutes.

4.16.3.5 Pinout

Shielded cables must be used for all signal lines.

r e
X20 DC 1073

UP
DN

A A\

B B\

R R\

Encoder 5V + GND

Figure 413: Pinout

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4.16.3.6 Connection example

DC SinCos encoders

A
A\
Sine-Cosine
B
B\
R
Reference track
R\

+24 VDC +24 VDC

GND GND

4.16.3.7 Analog inputs - Input circuit diagram

A/D Input value

Converter

A\

A/D Input value

Converter

B\

Input status
Evaluation

R\

Figure 414: Input circuit diagram for analog inputs

4.16.3.8 Circuit diagram for the encoder supply and LEDs

24 V UP
DC
Encoder 5 V
DC

LED (green)
GND

GND
DN

LED (green)

Figure 415: Circuit diagram for the encoder supply and LEDs

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4.16.3.9 Calculating the maximum encoder cable length

The following encoder data is assumed for this sample calculation:

Encoder data
Input voltage 4.75 V – 5.25 V
Max. input current 0.12 A
Module encoder output
Min. output voltage at 300 mA 4.86 V

Calculation of the maximum voltage drop for the cable

The maximum permitted voltage drop is calculated using the minimum encoder output voltage for the module
(UModuleMin) and the minimum encoder input voltage (UEncoderMin) of the encoder being used.
UCableMax = (UModuleMin – UEncoderMin) / 2
Example: UCableMax = (4.86 V – 4.75 V) / 2 = 0.055 V

Calculation of the maximum cable length

Cable lengthMax = UCableMax * Wire cross section (mm2) / (0.01786 * IEncoder)
This means:
IEncoder Current consumption of encoder in amps
UCableMax Maximum permitted voltage drop in volts

Example with resolver cable "8BCR0xxxx.1111A-0"

Encoder with 120 mA max. current consumption
Resolver cable cross section = 0.25 mm2
Results in a total cable length of:
Cable lengthMax = 0.055 V * 0.25 mm2 / 0.01786 * 0.12 A) = 6.41 m

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4.16.4 X20DS1828

4.16.4.1 General information

The X20DS1828 module is equipped with a HIPERFACE encoder interface. This module can be used to evaluate
encoders installed in motors from other manufacturers as well as encoders for external axes (encoders that scan
any machine movement). The input signals are monitored, making it possible to detect open or shorted lines as
well as encoder supply failures.
• HIPERFACE encoder interface
• Encoder input monitoring
• 11 VDC and GND for encoder supply
• NetTime function: Time stamp for position
HIPERFACE
HIPERFACE is a standard developed by Max Stegmann GmbH (www.stegmann.de), which like EnDat incorporates
the advantages of absolute and incremental position measurement while also offering a read/write parameter
memory in the encoder. With absolute position measurement (the absolute position is sampled serially), a homing
procedure is usually not required. Where necessary, a multi-turn encoder should be installed. To save costs, a
single-turn encoder and a reference switch can also be used. In this case, a homing procedure must be carried out.
The incremental process allows the short delay times necessary for position measurement on drives with excep-
tional dynamic properties. With the sinusoidal incremental signal and the fine resolution in the HIPERFACE mod-
ule, a very high positioning resolution is achieved in spite of the moderate signal frequencies used.
NetTime position timestamp
Highly dynamic positioning tasks require not only the position value, but also the exact time at which the position
was determined. The module has a NetTime function for this, which adds a timestamp to the recorded position
with microsecond accuracy.
The module provides the PLC with the position value and timestamp as absolute time value. The NetTime mech-
anisms ensure that the PLC NetTime clock and the local NetTime clock on the module have exactly the same
absolute time at all times.

4.16.4.2 Order data

Model number Short description Figure

Digital signal processing and preparation
X20DS1828 X20 digital signal module, 1x HIPERFACE, NetTime module
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 427: X20DS1828 - Order data

4.16.4.3 Technical data

Product ID X20DS1828
Short description
I/O module 1x HIPERFACE interface
General information
B&R ID code 0xAEC7
Status indicators Counting direction, operating status, module status
Diagnostics
Module run/error Yes, using status LED and software status
Counting direction Yes, using status LED

Table 428: X20DS1828 - Technical data

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Product ID X20DS1828
Power consumption
Bus 0.01 W
Internal I/O 1.3 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Type of signal lines Shielded cables should be used for all signal lines
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Encoder inputs
Angular position resolution 13-bit, with a 1 VSS signal
Encoder monitoring Yes
Max. encoder cable length 10 m
Sine/Cosine inputs
Signal transmission Differential signals, symmetric
Signal frequency DC up to 200 kHz
Differential voltage 1 VSS
Common-mode voltage Max. ±10 V
Terminating resistor 120 Ω
Encoder supply
Output voltage 11 V
Load capability 150 mA
Protective measures
Overload protection Yes
Short circuit protection Yes
Parameter channel (RS485)
Signal transmission 5 VDC differential signal, EiA RS-485 standard
Transmission status See HIPERFACE specification
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
Protection in accordance with EN 60529 IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating When operated at temperatures above 55°C, the power consumption of
the modules to the left and right of this module must not exceed 1.15 W.
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5+0.2 mm

Table 428: X20DS1828 - Technical data

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4.16.4.4 LED status indicators

Figure LED Color Status Description

r Green Off No power to module
Single flash Reset mode
Double flash Boot mode (during firmware update)
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off No power to module or everything OK
On Error or reset state. Possible cause:
• Encoder supply error
Single flash I/O error. Possible causes:
• Sine/Cosine relative position error (open line)
• Sine/Cosine absolute position error (reference)
Double flash System error. Possible causes:
• HIPERFACE communication error
Triple flash I/O error and system error
Single flash, inverted Error or reset state and I/O error
Double flash, inverted Error or reset state and system error
Triple flash, inverted Error or reset state, I/O error and system error
UP Green On The UP/DN LEDs are lit depending on the rotational direction and
speed of the connected encoder.
The UP LED indicates when the encoder position changes in the pos-
itive direction.
DN Green On The DN LED indicates when the encoder position changes in the neg-
ative direction.

Table 429: Status display

4.16.4.5 Pinout

Shielded cables must be used for all signal lines.

r e
X20 DS 1828

UP
DN

SIN REF SIN

COS REF COS

D\ D

Encoder 11V + GND

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4.16.4.6 Connection example

DS HIPERFACE encoder

SIN
REF SIN
Process data channel
COS
REF COS

D\
Parameter channel
D

+24 VDC +24 VDC

GND GND

4.16.4.7 Input diagram for the process data channel (sine-cosine track)

SIN

A/D Input value

converter

REF SIN

COS

A/D Input value

converter

REF COS

4.16.4.8 Circuit diagram for the parameter channel (RS485 interface)

D DIN

RS485
drivers DOUT
D\

4.16.4.9 Circuit diagram for the encoder supply and LEDs

24 V UP
DC
Encoder 11 V
DC

LED (green)
GND

GND
DN

LED (green)

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4.16.4.10 Register description

4.16.4.10.1 Register overview - Function model 0 (standard)

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Module configuration
513 CfO_SIframeGenID USINT ●
Basic functions
683 SDCLifeCount SINT ● ●
1236 PositionHW_64 UDINT ● ●
1244 PositionLW_64 UDINT
Position_32 DINT
1228 PosTime_32 DINT ● ●
1230 PosTime_16 INT
1219 PosCycle_8 SINT ● ●
Error management
387 ErrorEnableID_0F08 USINT ●
259 ErrorInfo USINT ● ●
323 AckErrorInfo USINT ● ●
2116 HfErrorCode UDINT ● ●
Sin/Cos - Configuration
1025 SinCosEnable USINT ●
1027 SinCosRefSource USINT ●
1034 SinCosVssMin UINT ●
1038 SinCosVssMax UINT ●
1044 SinCosQuitTime UDINT ●
HIPERFACE - Configuration
2049 HfMode USINT ●
2053 HfParity USINT ●
2055 HfCharTimeout USINT ●
2060 HfBaud UDINT ●
2068 HfRepressErrTime UDINT ●
2073 HfRefAdr USINT ●
2075 HfRefWidth USINT ●
HIPERFACE - Identification
2561 HfAdrIdent USINT ●
2563 HfSelectionIdent USINT ●
2631 HfIdentOkByte USINT ●
2688 HfRs485Settings USINT ●
2689 HfEncoderType USINT ●
2690 HfEepromSize USINT ●
2691 HfOptionFlags USINT ●
2692 HfFreeMemory USINT ●
2693 HfDataFields USINT ●
2693 + HfExtByte01 USINT ●
Index HfExtByte[02...10]
HIPERFACE - Additional positions
2817 AddPosAdr01 USINT ●
2887 AddPosOkByte USINT ● ●
2956 AddPosition01_32 DINT ● ●
2958 AddPosition01_16 INT ● ●
2948 AddPosTime01_32 DINT ● ●
2950 AddPosTime01_16 INT ● ●
2825 AddPosAdr02 USINT ●
2972 AddPosition02_32 DINT ● ●
2974 AddPosition02_16 INT ● ●
2964 AddPosTime02_32 DINT ● ●
2966 AddPosTime02_16 INT ● ●
HIPERFACE - Additional analog values
3073 AnalogAdrCh01 USINT ●
3075 AnalogCh01 USINT ●
3143 AnalogChOkByte USINT ● ●
3210 AnalogChValue01_u UINT ● ●
AnalogChValue01_s INT
3204 AnalogChTime01_32 DINT ● ●
3206 AnalogChTime01_16 INT ● ●
3081 AnalogAdrCh02 USINT ●
3083 AnalogCh02 USINT ●
3226 AnalogChValue02_u UINT ● ●
AnalogChValue02_s INT
3220 AnalogChTime02_32 DINT ● ●
3222 AnalogChTime02_16 INT ● ●
3089 AnalogAdrCh03 USINT ●
3091 AnalogCh03 USINT ●

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Register Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
3242 AnalogChValue03_u UINT ● ●
AnalogChValue03_s INT
3236 AnalogChTime03_32 DINT ● ●
3238 AnalogChTime03_16 INT ● ●
3097 AnalogAdrCh04 USINT ●
3099 AnalogCh04 USINT ●
3258 AnalogChValue04_u UINT ● ●
AnalogChValue04_s INT
3252 AnalogChTime04_32 DINT ● ●
3254 AnalogChTime04_16 INT ● ●
FlatStream mode
2305 OutputMTU USINT ●
2307 InputMTU USINT ●
2309 FlatStreamMode USINT ●
2311 Forward USINT ●
2316 ForwardDelay UINT ●
2368 InputSequence USINT ● ●
2368 + RxByte1 USINT ● ●
Index RxByte[2…15]
2400 OutputSequence USINT ● ●
2400 + TxByte1 USINT ● ●
Index TxByte[2…15]

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4.16.4.10.2 Variable mapping in Automation Studio (X2X master)

Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Basic functions
SDCLifeCount SINT ●
PositionHW UDINT ●
PositionLW UDINT
Position DINT
PosTime DINT ●
INT
PosCycle SINT ●
Error management
HfErrorCode UDINT ●
ErrorInfo USINT ●
→ EncoderSupplyError BOOL
→ VssCheckError BOOL
→ PositionError BOOL
→ HfComError BOOL
→ HfRefWarning BOOL
AckErrorInfo USINT ●
→ AckEncoderSupplyError BOOL
→ AckVssCheckError BOOL
→ AckPositionError BOOL
→ AckHfComError BOOL
→ AckHfRefWarning BOOL
HIPERFACE - Additional positions
AddPosOk01 BOOL ●
AddPosOk02
AddPosition01 INT ●
AddPosition02 DINT
AddPosTime01 INT ●
AddPosTime02 DINT
HIPERFACE - Additional analog values
AnalogChOk01 BOOL ●
AnalogChOk[02…04]
AnalogChValue01 UINT ●
AnalogChValue[02…04] INT
AnalogChTime01 INT ●
AnalogChTime[02…04] DINT
FlatStream mode
InputSequence USINT ●
RxByte1 USINT ●
RxByte[2…15]
OutputSequence USINT ●
TxByte1 USINT ●
TxByte[2…15]

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4.16.4.10.3 Register overview - Function model 254 (bus controller)

Register Object offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Module configuration
513 - CfO_SIframeGenID USINT ●
Basic functions
1236 0 PositionHW_64_CANIO UDINT ●
1244 4 PositionLW_64_CANIO UDINT ●
1219 15 PosCycle_8_CANIO SINT ●
Error management
387 - ErrorEnableID_0F08 USINT ●
323 14 ErrorInfo_CANIO USINT ●
259 6 AckErrorInfo_CANIO USINT ●
2116 - HfErrorCode UDINT ●
Sin/Cos - Configuration
1025 - SinCosEnable USINT ●
1027 - SinCosRefSource USINT ●
1034 - SinCosVssMin UINT ●
1038 - SinCosVssMax UINT ●
1044 - SinCosQuitTime UDINT ●
HIPERFACE - Configuration
2049 - HfMode USINT ●
2053 - HfParity USINT ●
2055 - HfCharTimeout USINT ●
2060 - HfBaud UDINT ●
2068 - HfRepressErrTime UDINT ●
2073 - HfRefAdr USINT ●
2075 - HfRefWidth USINT ●
HIPERFACE - Information
2561 - HfAdrIdent USINT ●
2563 - HfSelectionIdent USINT ●
2631 - HfIdentOkByte USINT ●
2688 - HfRs485Settings USINT ●
2689 - HfEncoderType USINT ●
2690 - HfEepromSize USINT ●
2691 - HfOptionFlags USINT ●
2692 - HfFreeMemory USINT ●
2693 - HfDataFields USINT ●
2693 + - HfExtByte01 USINT ●
Index HfExtByte[02...10]
HIPERFACE - Additional positions
2817 - AddPosAdr01 USINT ●
2887 - AddPosOkByte USINT ●
2956 - AddPosition01_32 DINT ●
2958 - AddPosition01_16 INT ●
2825 - AddPosAdr02 USINT ●
2972 - AddPosition02_32 DINT ●
2974 - AddPosition02_16 INT ●
HIPERFACE - Additional analog values
3073 - AnalogAdrCh01 USINT ●
3075 - AnalogCh01 USINT ●
3143 - AnalogChOkByte USINT ●
3210 - AnalogChValue01_u UINT ●
AnalogChValue01_s INT ●
3081 - AnalogAdrCh02 USINT ●
3083 - AnalogCh02 USINT ●
3226 - AnalogChValue02_u UINT ●
AnalogChValue02_s INT ●
3089 - AnalogAdrCh03 USINT ●
3091 - AnalogCh03 USINT ●
3242 - AnalogChValue03_u UINT ●
AnalogChValue03_s INT ●
3097 - AnalogAdrCh04 USINT ●
3099 - AnalogCh04 USINT ●
3258 - AnalogChValue04_u UINT ●
AnalogChValue04_s INT ●
FlatStream mode
2305 - OutputMTU USINT ●
2307 - InputMTU USINT ●
2309 - FlatStreamMode USINT ●
2311 - Forward USINT ●
2316 - ForwardDelay UINT ●
2368 8 InputSequence_CANIO USINT ●

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Register Object offset Name Data type Read Write
Cyclic Acyclic Cyclic Acyclic
2368 + 9...13 RxByte1_CANIO USINT ●
Index RxByte[2...5]_CANIO
2400 0 OutputSequence_CANIO USINT ●
2400 + 1...5 TxByte1_CANIO USINT ●
Index TxByte[2...5]_CANIO

4.16.4.10.4 Variable mapping in Automation Studio (CANIO)

Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Basic functions
PositionHW UDINT ●
PositionLW UDINT ●
PosCycle SINT ●
Error management
HfErrorCode UDINT ●
ErrorInfo USINT ●
→ EncoderSupplyError BOOL
→ VssCheckError BOOL
→ PositionError BOOL
→ HfComError BOOL
→ HfRefWarning BOOL
AckErrorInfo USINT ●
→ AckEncoderSupplyError BOOL
→ AckVssCheckError BOOL
→ AckPositionError BOOL
→ AckHfComError BOOL
→ AckHfRefWarning BOOL
HIPERFACE - Additional positions
AddPosOk01 BOOL ●
AddPosOk02
AddPosition01 INT ●
AddPosition02 DINT
HIPERFACE - Additional analog values
AnalogChOk01 BOOL ●
AnalogChOk[02…04]
AnalogChValue01 UINT ●
AnalogChValue[02…04] INT
FlatStream mode
InputSequence USINT ●
RxByte1 USINT ●
RxByte[2…5]
OutputSequence USINT ●
TxByte1 USINT ●
TxByte[2…5]

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4.16.4.10.5 Module configuration

The following configuration registers can be used to define various module settings. They can be used, for example,
to modify the module's behavior on an X2X Link network. The X20DS1828 also provides one optional register.

4.16.4.10.5.1 Data query

Names (pChannelName):
CfO_SIframeGenID
This register can be used to define when the synchronous/cyclic input data is generated. "X2X cycle optimized"
should be set for jitter-free data acquisition. "Minimal latency" can be set for the best performance.
Data type Value
USINT 09 ... Minimal latency
14 ... X2X cycle optimized (bus controller default setting)

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4.16.4.10.6 Basic functions

This module can read a position when used together with a HIPERFACE encoder. The received position data is
prepared in two different formats and given a timestamp. Six registers are available for further processing. This
allows the user to select the format that best fits the application at hand.

4.16.4.10.6.1 SDCLifeCount

Names (pChannelName):
SDCLifeCount
The 8-bit counter register is needed for the SDC software package. It is incremented with the system clock to allow
the SDC to check the validity of the data frame.
Data type Value
SINT -128 to 127

4.16.4.10.6.2 Position (64-bit)

Names (pChannelName):
PositionHW
PositionHW_64 / PositionHW_64_CANIO
PositionLW
PositionLW_64 / PositionLW_64_CANIO
The absolute position of the encoder is defined using 64-bit resolution. The position value is stored in the Position-
HW and PositionLW registers. The upper 32 bits are stored the PositionHW register, while the lower 32 bits are
stored in the PositionLW register.
Data type Value
2x UDINT 0 to 4,294,967,295

4.16.4.10.6.3 Position (32-bit)

Names (pChannelName):
Position
Position_32
The SDC library requires a signed 32-bit position value. The position's low word can be accessed separately for
this. The value can also be used as default position value, however.
Data type Value
DINT -2,147,483,648 to 2,147,483,647

4.16.4.10.6.4 PosTime (32-bit)

Names (pChannelName):
PosTime
PosTime_32
In this register, the current NetTime value is assigned to each position value read. The NetTime is recorded with
µs accuracy.
Data type Value
DINT -2.147.483.648 to 2.147.483.647 ... Nettime [µs]

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4.16.4.10.6.5 PosTime (16-bit)

Names (pChannelName):
PosTime
PosTime_16
The SDC library requires a 16-bit value. The NetTime value is therefore also generated in this format.
Data type Value
INT -32.768 to 32.767 ... Nettime [µs]

4.16.4.10.6.6 PosCycle

Names (pChannelName):
PosCycle
PosCycle_8 / PosCycle_8_CANIO
PosCycle is an integer counter that is incremented as soon as the module has saved a new valid position value.
Data type Value
SINT -128 to 127

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4.16.4.10.7 Error management

This module can be used to diagnose error states. There are two ways the X20DS1828 performs error diagnostics:
• Module-based diagnostics
• HIPERFACE-based diagnostics

4.16.4.10.7.1 Module-based diagnostics

Like most B&R modules, the X20DS1828 is able to detect errors on its own. It diagnoses five different errors or
warnings. The error bits can be retrieved individually or grouped together.

Error registers

Names (pChannelName):
ErrorEnableID_0F08
ErrorInfo / ErrorInfo_CANIO
AckErrorInfo / AckErrorInfo_CANIO
Names of individual bits (pChannelName):
EncoderSupplyError
VssCheckError
PositionError
HfComError
HfRefWarning
AckEncoderSupplyError
AckVssCheckError
AckPositionError
AckHfComError
AckHfRefWarning
B&R's approach to error management uses three independent registers.
Data type Value
USINT See bit structure

The implemented diagnostics algorithms can be enabled or disabled using the Enable byte.
"ErrorEnableID_0F08" structure:
Bit Name Information
0 Encoder supply 0 Error detection disabled
1 Error detection enabled (bus controller default)
1 Reserved -
2 Vss Sin/Cos 0 Error detection disabled
1 Error detection enabled (bus controller default)
3 Position error 0 Error detection disabled
1 Error detection enabled (bus controller default)
4 HIPERFACE communication 0 Error detection disabled
1 Error detection enabled (bus controller default)
5 HIPERFACE reference warning 0 Warning disabled
1 Warning enabled (bus controller default)
6-7 Reserved -

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The State byte indicates any errors or warnings that have not yet been acknowledged.
"ErrorInfo" structure:
Bit Name Information
0 EncoderSupplyError 0 No error
1 Encoder supply error
1 Reserved -
2 VssCheckError 0 No error
1 Vss error on the Sin/Cos track
3 PositionError 0 No error
1 Position error
4 HfComError 0 No error
1 HIPERFACE communication error
5 HfRefWarning 0 No warning
1 HIPERFACE reference warning
6-7 Reserved -

The Ack byte is used to acknowledge an error or warning message.

"AckErrorInfo" structure:
Bit Name Information
0 AckEncoderSupplyError 0 No error acknowledgment
1 Error acknowledgment
1 Reserved -
2 AckVssCheckError 0 No error acknowledgment
1 Error acknowledgment
3 AckPositionError 0 No error acknowledgment
1 Error acknowledgment
4 AckHfComError 0 No error acknowledgment
1 Error acknowledgment
5 AckHfRefWarning 0 No acknowledgment
1 Confirmation
6-7 Reserved -

Encoder supply
The encoder supply voltage is below the permitted limit.

Vss Sin/Cos
The voltage value for the Sin/Cos track violates the configured limit values.
→ See registers SinCosVssMin and SinCosVssMax.

Position error
The position value determined violates internal requirements.

HIPERFACE communication
Communication error on the HIPERFACE interface (RS485)
→ See register HfErrorCode.

HIPERFACE reference warning

The digital interface provides an absolute position value that can be used to accurately describe the axis position.
The position value is homed to this absolute value at the beginning of a measurement. The analog interface can be
used to incrementally sample changes that occur very rapidly. This enables the module to continue sampling the
position value at a high resolution. Both the analog and the digital signal are sampled cyclically. If the value read
incrementally deviates from the absolute value during operation, then the warning is generated and the position
must be homed again.

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4.16.4.10.7.2 HIPERFACE-based diagnostics

Memory areas are provided in the HIPERFACE standard for error diagnostics. Error management has been ad-
justed in order to use error detection in accordance with the HIPERFACE standard. An additional register has
been implemented in the module to provide this area in the encoder's memory. This error memory is mirrored in
the module's registers and can be interpreted by the user. Detailed information regarding the errors that can be
detected in this way can be found in the encoder's manual.

HfErrorCode

Names (pChannelName):
HfErrorCode
This register stores the error code that identifies the current problem with the HIPERFACE interface.
Data type Value
UDINT See bit structure

Internally, the register consists of four pieces of information.

Bit structure:
Bit Name Information
00-07 Error ID See below
08-15 Last command Command that caused the error on the slave
16-23 Station address Address of the faulty HIPERFACE slave
24-31 Error counter Counts the number of errors that have occurred

Bits 00-07 (error ID)

These 8 bits of this register specify the error that has occurred. The error ID is not a standard value, however, and
must be looked up in the manual for the HIPERFACE slave. The X20DS1828 also diagnoses a time overrun on
the HIPERFACE interface. This triggers error ID 255.

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4.16.4.10.8 Sin/Cos - Analog interface configuration

In addition to the digital HIPERFACE interface, this module is also equipped with an analog interface for sampling
a differential sine-cosine signal. To increase the resolution, the EnDat standard supports cooperation between
the analog and digital data. This enables a highly dynamic representation of the position while maintaining high
resolution.

4.16.4.10.8.1 SinCosEnable

Names (pChannelName):
SinCosEnable
This register must always have the value 1 for configuration reasons.
Data type Value
USINT 1!
Bus controller default: 1

4.16.4.10.8.2 SinCosRefSource

Names (pChannelName):
SinCosRefSource
This register must always have the value 3 for configuration reasons.
Data type Value
USINT 3!
Bus controller default: 3

4.16.4.10.8.3 SinCosVssMin

Names (pChannelName):
SinCosVssMin
The SinCosVssMin register specifies the lower limit value for the peak-to-peak voltage of the sine/cosine track.
The incoming signal is monitored in this way. If the incoming value falls below this specified limit, then the module
reports the corresponding error.
Data type Value
UINT 0 to 1500 [mV]
Bus controller default: 800

4.16.4.10.8.4 SinCosVssMax

Names (pChannelName):
SinCosVssMax
The SinCosVssMax register specifies the upper limit value for the peak-to-peak voltage of the sine/cosine track.
The incoming signal is monitored in this way. If the incoming value exceeds this specified limit, then the module
reports the corresponding error.
Data type Value
UINT 0 to 1500 [mV]
Bus controller default: 1200

4.16.4.10.8.5 SinCosQuitTime

Names (pChannelName):
SinCosQuitTime
If an error is detected on the analog interface, the last correctly read values remain valid. An interval can be defined
here at which the module begins receiving correct values again after the error state without processing them further
internally. Only then will newly sampled correct analog values be recognized as valid.
Data type Value
UDINT 0 to 20,000,000 [µs]
Bus controller default: 100000

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4.16.4.10.9 HIPERFACE

4.16.4.10.9.1 HIPERFACE - Digital interface configuration

HIPERFACE builds upon the RS-485 (EIA-485) specification and permits communication with multiple HIPER-
FACE slaves.
There are two methods available to use the slave data in a PLC program. One is to store the necessary slave
values temporarily in the module, where they can then be provided to the CPU. The other is to use the module's
FlatStream mode, which supports the full range of commands defined in the HIPERFACE specification.
Additional information regarding the HIPERFACE specification is provided in the "Description of HIPERFACE"
document.

HfMode

Names (pChannelName):
HfMode
This register is used to enable the HIPERFACE interface and must always be set to the value 1 for configuration
reasons.
Data type Value
USINT 1!
Bus controller default: 1

HfParity

Names (pChannelName):
HfParity
This register configures the parity bit for the interface.
Data type Value
USINT 69 ... E → Even parity
78 ... N → No parity
79 ... O → Odd parity
Bus controller default: 69

HfCharTimeout

Names (pChannelName):
HfCharTimeout
This register configures the time that the module waits after receiving the last data block to add additional data to
the current data packet (frame). When this time expires, the data received thus far is saved in a frame. The transfer
is complete and the data can be evaluated.

Information:
Time is specified as a char value in order to ensure identical behavior regardless of the baud rate
setting.
Data type Value
USINT 1 to 255 [char]
Bus controller default: 55

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HfBaud

Names (pChannelName):
HfBaud
This register configures the baud rate (transfer rate) of the interface.
The module does not allow a transfer rate of 600 baud.
Data type Value
UDINT 1200, 2400, 4800, 9600, 19200, 38400 ... [Baud]
Bus controller default: 9600

HfRepressErrTime

Names (pChannelName):
HfRepressErrTime
This register configures the minimum time that an error code remains in the "HfErrorCode" register. This makes it
possible to ensure that the CPU registers every error that occurs.
Data type Value
UDINT 1 to 20,000,000 [µs]
Bus controller default: 100000

HfRefAdr

Names (pChannelName):
HfRefAdr
This module can manage up to 32 HIPERFACE slaves via its the digital interface. High-resolution position sampling,
however, requires information from both the digital and analog interfaces. The HIPERFACE address of the station
whose sine/cosine track is being read by the module is entered in this register. If there is only one slave on the
network, the broadcast address (255) can also be used.
Data type Value
USINT 0 ... Operation without sine/cosine track
64 to 95 ... Open address range for max. 32 HIPERFACE slaves
255 ... Broadcast address
Bus controller default: 255

HfRefWidth

Names (pChannelName):
HfRefWidth
This register sets the absolute width for the sampled position. The number of bits must be taken from the data
provided by the encoder manufacturer and usually consists of three values:
• 5 bits: Resolution of the digital absolute position
• x bits: HIPERFACE data format, number of bits per revolution
• 2y bits: Number of sine/cosine periods per revolution
The sum of the sampled values results in the HfRefWidth (HfRefWidth = 5+x+y).
Data type Value
USINT 8 to 32
Bus controller default: 32

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4.16.4.10.9.2 HIPERFACE - Read ID

The digital interface provides the option of assigning a HIPERFACE slave a specific ID. Its parameter data can
be queried when booting the PLC, for example. Any deviations from the previous hardware constellation can then
be handled accordingly in the program.

Configuration
The parameter to be read is specified by two registers. One of the registers contains the address of the desired
HIPERFACE slave; the other contains a code for the value to be read.

HfAdrIdent

Names (pChannelName):
HfAdrIdent
This register specifies the address of the HIPERFACE slave whose parameter should be read by the module.
Data type Value
USINT 0 ... Identification disabled
64 to 95 ... Open address range for max. 32 HIPERFACE slaves
255 ... Broadcast address (when operating with one slave)
Bus controller default: 0

HfSelectionIdent

Names (pChannelName):
HfSelectionIdent
This register defines the parameters that should be provided in the slave response and buffered in the module's
HfExtByte register.
Data type Value
USINT Selection codes
0 ... Serial number
1 ... Firmware date
2 ... High part of firmware version
3 ... Low part of firmware version
Bus controller default: 0

Call
After being configured correctly, the selected parameter is transmitted cyclically to the module. There are eight
registers that serve as temporary storage. The module confirms successful receipt by setting the HfIdentOkByte.

HfIdentOkByte

Names (pChannelName):
HfIdentOkByte
This register's bits provide information about the validity of the latest ID values in temporary storage.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Information
0 HfIdentOk01 0 Parameter 01 invalid
1 Parameter 01 valid
1-7 Reserved -

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HfRs485Settings

Names (pChannelName):
HfRs485Settings
This register temporarily stores the current network configuration expected by the slave. The register value is
specifically structured for HIPERFACE.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Information
0-2 Speed code 0-6 Baud rate:
1 (001 b) ... 1200 baud
2 (010 b) ... 2400 baud
3 (011 b) ... 4800 baud
4 (100 b) ... 9600 baud
5 (101 b) ... 19200 baud
6 (110 b) ... 38400 baud
Bus controller default: 4
3 Reserved -
4 Number of parity bits 0 No parity bit
1 One parity bit (default)
5 Type of parity bit 0 Even (default)
1 Odd
6 Timeout behavior 0 Timeout 11/baud rate
1 Timeout 4*11/baud rate (default)
7 Network behavior 0 Bus
1 Direct connection (default)

HfEncoderType

Names (pChannelName):
HfEncoderType
This register temporarily stores the ID of the current encoder. The register value is structured specifically for each
slave and must be looked up in the encoder's data sheet.
Data type Value
USINT 0 to 255

HfEepromSize

Names (pChannelName):
HfEepromSize
This register stores the size of the EEPROM being used. The number of 16-byte blocks is specified.
Data type Value
USINT 0 to 255 [16-byte blocks]

HfOptionFlags

Names (pChannelName):
HfOptionFlags
This register stores slave-specific hardware and software settings.
Data type Value
USINT 0 to 255

HfFreeMemory

Names (pChannelName):
HfFreeMemory
This register shows the number of free 16-byte blocks remaining on the HIPERFACE slave.
Data type Value
USINT 0 to 255 [16-byte blocks]

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HfDataFields

Names (pChannelName):
HfDataFields
This register indicates the number of data fields that have been written thus far.
Data type Value
USINT 0 to 255

HfExtByte

Names (pChannelName):
HfExtByte01
HfExtByte[02...10]
These registers provide the respective parameters according to how "HfSelectionIdent" is configured.
Data type Value
USINT 0 to 255

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4.16.4.10.9.3 HIPERFACE - Reading additional encoder positions

This module can read up to two additional position values via the HIPERFACE interface and provide them to the
PLC. Each position value is accompanied by a timestamp.

Configuration
The address must be specified in order to read the position value from the respective HIPERFACE interface. One
address register is provided for each position value.

AddPosAdr

Names (pChannelName):
AddPosAdr01
AddPosAdr02
These registers specify the addresses of the HIPERFACE slaves whose position values should be processed in
the module.
Data type Value
USINT 0 ... Additional encoder position disabled
64 to 95 ... Open address range for max. 32 HIPERFACE slaves
255 ... Broadcast address (when operating with one slave)
Bus controller default: 0

Call
After being configured correctly, the position value is transmitted cyclically to the module. Each slave has five reg-
isters that serve as temporary storage. The module automatically generates the timestamp and confirms success-
ful transmission by setting the corresponding AddPosOK0x bit. The HIPERFACE specification does not specify in
which format the parameters must be received. The module therefore provides the position value and time in two
formats. Which of the position registers should be used for further processing depends on the HIPERFACE slave.
The user is free to define the format of the timestamp.

AddPosOkByte

Names (pChannelName):
AddPosOk01
AddPosOk02
This register's bits provide information about the validity of the last position values in temporary storage.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Information
0 AddPosOk01 0 Position value 01 invalid
1 Position value 01 valid
1 AddPosOk02 0 Position value 02 invalid
1 Position value 02 valid
2-7 Reserved -

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AddPosition (32-bit)

Names (pChannelName):
AddPosition01
AddPosition02
AddPosition01_32
AddPosition02_32
These registers provide the corresponding position values as signed 4-byte values.
Data type Value
DINT -2,147,483,648 to 2,147,483,647

AddPosition (16-bit)

Names (pChannelName):
AddPosition01
AddPosition02
AddPosition01_16
AddPosition02_16
These registers provide the corresponding position values as signed 2-byte values.
Data type Value
INT -32,768 to 32,767

AddPosTime (32-bit)

Names (pChannelName):
AddPosTime01
AddPosTime02
AddPosTime01_32
AddPosTime02_32
These registers provide the timestamps of the most recently received position values as signed 4-byte values.
Data type Value
DINT -2.147.483.648 to 2.147.483.647 ... Nettime [µs]

AddPosTime (16-bit)

Names (pChannelName):
AddPosTime01
AddPosTime02
AddPosTime01_16
AddPosTime02_16
These registers provide the timestamps of the most recently received position values as signed 2-byte values.
Data type Value
INT -32.768 to 32.767 ... Nettime [µs]

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4.16.4.10.9.4 HIPERFACE - Reading additional analog values

This module can read up to four analog values (16-bit) via the HIPERFACE interface and provide them to the PLC.
Each analog value is accompanied by a timestamp.

Configuration
The analog value to be read is specified by two registers. One of them contains the address of the desired station,
and the other the channel of the parameter to be read. An overview of analog values that can be read is provided
in the data sheet for the respective slave.

AnalogAdrCh

Names (pChannelName):
AnalogAdrCh01
AnalogAdrCh02
AnalogAdrCh03
AnalogAdrCh04
These registers specify the addresses of the HIPERFACE slaves whose analog values should be processed in
the module. To query multiple values from one HIPERFACE slave, it may make sense to write the same address
to different AnalogAdrCh registers.
Data type Value
USINT 0 ... Additional analog values disabled
64 to 95 ... Open address range for max. 32 HIPERFACE slaves
255 ... Broadcast address (when operating with one slave)
Bus controller default: 0

AnalogCh

Names (pChannelName):
AnalogCh01
AnalogCh02
AnalogCh03
AnalogCh04
These registers define the channel to be read that is written by the bus station to the module's temporary storage.
Data type Value
USINT See encoder data sheet
Bus controller default: 0

Call
After being configured correctly, the analog value is transmitted cyclically to the module. There are five registers
that serve as temporary storage. The module automatically generates the timestamp and confirms successful
transmission by setting the corresponding AnalogChOk0x bit. The HIPERFACE specification does not specify in
which format the parameters must be received. The module therefore provides the value and time in two formats.
Which of the value registers should be used for further processing depends on the peripheral equipment. The user
is free to define the format of the timestamp.

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AnalogChOkByte

Names (pChannelName):
AnalogChOk01
AnalogChOk02
AnalogChOk03
AnalogChOk04
This register's bits provide information about the validity of the values in temporary storage.
Data type Value
USINT See bit structure

Bit structure:
Bit Name Information
0 AnalogChOk01 0 Analog value 01 invalid
1 Analog value 01 valid
1 AnalogChOk02 0 Analog value 02 invalid
1 Analog value 02 valid
2 AnalogChOk03 0 Analog value 03 invalid
1 Analog value 03 valid
3 AnalogChOk04 0 Analog value 04 invalid
1 Analog value 04 valid
4-7 Reserved -

AnalogChValue (unsigned)

Names (pChannelName):
AnalogChValue01_u
AnalogChValue02_u
AnalogChValue03_u
AnalogChValue04_u
These registers provide the current analog values as signed 2-byte values.
Data type Value
UINT 0 to 65,535

AnalogChValue (signed)

Names (pChannelName):
AnalogChValue01_s
AnalogChValue02_s
AnalogChValue03_s
AnalogChValue04_s
These registers provide the corresponding analog values as signed 2-byte values.
Data type Value
INT -32,768 to 32,767

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AnalogChTime (32-bit)

Names (pChannelName):
AnalogChTime01_32
AnalogChTime02_32
AnalogChTime03_32
AnalogChTime04_32
These registers provide the timestamps of the most recently received analog values as signed 4-byte values.
Data type Value
DINT -2,147,483,648 to 2,147,483,647 [µs]

AnalogChTime (16-bit)

Names (pChannelName):
AnalogChTime01_16
AnalogChTime02_16
AnalogChTime03_16
AnalogChTime04_16
These registers provide the timestamps of the most recently received analog values as signed 2-byte values.
Data type Value
INT -32768 to 32,767 [µs]

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4.16.4.10.10 FlatStream communication

4.16.4.10.10.1 Introduction

B&R offers an additional communication method for some modules. "FlatStream" was designed for X2X and
POWERLINK networks and allows data transmission to be adapted to individual demands. Although this method
is not 100% real-time capable, it still allows data transmission to be handled more efficiently than with standard
cyclic polling.
Field device
X2X language

Cyclic call
via I/O mapping

B&R CPU
Cyclic call B&R module Cyclic
PLC or B&R field device
of cached values cached value communication
Bus controller

Acyclic call
via
library functions
B&R CPU
Acyclic call B&R module Cyclic
PLC or B&R field device
of cached values cached value communication
Bus controller

FlatStream

B&R CPU X2X-compatible B&R module

PLC or Device command B&R field device
device command as a bridge
Bus controller

Figure 416: Three types of communication

FlatStream extends cyclic and acyclic data queries. With FlatStream communication, the module acts as a bridge.
It is used to pass CPU queries directly on to the field device.

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4.16.4.10.10.2 Message, segment, sequence, MTU

The physical properties of the bus system limit the amount of data that can be transmitted during one bus cycle.
With FlatStream communication, all messages are viewed as part of a continuous data stream. Long data streams
must be broken down into several fragments that are sent one after the other. To understand how the receiver puts
these fragments back together to get the original information, it is important to understand the difference between
a message, a segment, a sequence and an MTU.
Message
A message refers to information exchanged between two partner stations. The length of a message is not restricted
by the FlatStream communication method. Nevertheless, module-specific limitations must be considered.
Segment (logical division of a message):
A segment has a finite size and can be understood as a section of a message. The number of segments per
message is arbitrary. So that the recipient can correctly reassemble the transmitted segments, each segment
is preceded by a byte with additional information. This control byte contains information such as the length of a
segment and whether the approaching segment completes the message. This makes it possible for the receiving
station to interpret the incoming data stream correctly.
Sequence (how a segment needs to be arranged physically):
The maximum size of a sequence corresponds to the number of enabled Rx or Tx bytes (later: "MTU"). The
transmitting station splits the transmit array into valid sequences. These sequences are then written successively
to the MTU and transmitted to the receiving station where they are put back together again. The receiver stores
the incoming sequences in a receive array, obtaining an image of the data stream in the process.
With FlatStream communication, the number of sequences sent are counted. Successfully transmitted sequences
must be acknowledged by the receiving station to ensure the integrity of the transmission.
MTU (Maximum Transmission Unit) – Physical transport:
MTU refers to the enabled USINT registers used with FlatStream. These registers can accept at least one se-
quence and pass it on to the receiving station. A separate MTU is defined for each direction of communication.
The OutputMTU defines the number of FlatStream Tx bytes, and the InputMTU specifies the number of FlatStream
Rx bytes. The MTUs are transported cyclically via the X2X Link, increasing the load with each additional enabled
USINT register.
Features
FlatStream messages are not transmitted cyclically or in 100% real time. Many bus cycles may be needed to trans-
mit a particular message. Although the Rx and Tx registers are exchanged between the transmitter and the receiv-
er cyclically, they are only processed further if explicitly accepted by the "InputSequence" or "OutputSequence"
register.
Behavior in the event of an error (brief summary)
The protocol for X2X and POWERLINK networks specifies that the last valid values should be retained when
disturbances occur. With conventional communication (cyclic/acyclic data queries), this type of error can generally
be ignored.
In order for communication to also take place without errors using FlatStream, all of the sequences issued by the
receiver must be acknowledged. If Forward functionality is not used, then subsequent communication is delayed
for the length of the disturbance.
If Forward functionality is being used, the receiving station receives a transmission counter that is incremented
twice. The receiver stops, i.e. it no longer returns any acknowledgments. The transmitting station uses the Se-
quenceAck to determine that the transmission was faulty and that all affected sequences will have to be repeated.

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4.16.4.10.10.3 The FlatStream principle

Prerequisites and requirements

Before FlatStream can be used, the respective communication direction must be synchronized, i.e. both commu-
nication partners cyclically query the sequence counter on the opposite station. This checks to see if there is new
data that should be accepted.
Communication
If a communication partner wants to transmit a message to its opposite station, it should first create a transmit
array that corresponds to FlatStream conventions. This allows the FlatStream data to be organized very efficiently
without having to block other important resources.
PLC / Bus controller Module
Module-internal Module-internal
Transmit array OutputMTU receive buffer receive array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 TxBytes Cyc. *RxBytes _data_01

_data_02 _data_02
When OutputMTU The transmit buffer If the OutputSequence
_data_03 released: of the module is counter is increased: _data_03
adjusted cyclically to
_data_04 CPU fills OutputMTU via X2X Module adds the transmit buffer _data_04
OutputMTU to the internal array
_data_05 with the next
_data_05
... sequence of the If successful: ...
transmit array InputSequenceAck is
_data_xx adjusted to the _data_xx
transmit counter

Module-internal Module-internal
Receive array InputMTU transmit buffer transmit array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 RxBytes Cyc. *TxBytes _data_01

_data_02 _data_02
If the InputMTU is If permitted:
_data_03 InputSequence adjusted cyclically Module fills the internal _data_03
counter is increased: to the receive transmit buffer with the
_data_04 buffer via X2X next sequence of the _data_04
_data_05 InputMTU must be transmit array _data_05
added to the end
... of the receive array Module increases the ...
(increase InputSequenceAck InputSequence counter
_data_xx to end properly) _data_xx

Figure 417: FlatStream communication

Procedure
The first thing that happens is that the message is broken into valid segments of up to 63 bytes, and the corre-
sponding control bytes are created. The data is formed into a data stream made up of one control bytes per asso-
ciated segment. This data stream can be written to the transmit array. The maximum size of each array element
matches that of the enabled MTU so that one element corresponds to one sequence.
When the array has been completely created, the transmitter checks whether the MTU is allowed to be refilled.
Then it copies the first element of the array or the first sequence to the Tx byte registers. The MTU is transported to
the receiver station via X2X Link and stored in the corresponding Rx byte registers. To signal that the data should
be accepted by the receiver, the transmitter increases its SequenceCounter.
If the communication direction is synchronized, the opposite station detects the incremented SequenceCounter.
The current sequence is appended to the receive array and acknowledged by SequenceAck. This acknowledgment
signals to the transmitter that the MTU can now be refilled.
If the transmission is successful, the data in the receive array will correspond 100% to the data in the transmit array.
During the transmission, the receiving station must detect and evaluate the incoming control bytes. A separate
receive array should be created for each message. This allows the receiver to immediately begin further processing
of messages once they have been completely transmitted.

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4.16.4.10.10.4 Registers for FlatStream mode

Five registers are available for configuring FlatStream. The default configuration can be used to transmit small
amounts of data relatively easily.

Information:
The CPU communicates directly with the field device via the "OutputSequence" and "InputSequence"
as well as the enabled Tx and Rx bytes. For this reason, the user needs to have sufficient knowledge
of the communication protocol being used on the field device.

FlatStream configuration

To use FlatStream, the program sequence must first be expanded. The cycle time of the FlatStream routines must
be set to a multiple of the bus cycle. Other program routines should be implemented in Cyclic #1 to ensure data
consistency.
At the absolute minimum, the "InputMTU" and "OutputMTU" registers need to be configured. All other registers are
filled in with default values at the beginning and can be used immediately. These registers are used for additional
options, e.g. to transmit data in a more compact way or to increase the efficiency of the general procedure.
The Forward registers extend the functionality of the FlatStream protocol. This functionality is useful for substan-
tially increasing the FlatStream data rate, but it also requires quite a bit of extra work when creating the program
sequence.

Number of enabled Tx and Rx bytes

Name:
OutputMTU
InputMTU
These registers define the number of enabled Tx or Rx bytes, i.e. the maximum size of a sequence. The user must
consider that the more bytes made available also means a higher load on the bus system.

Information:
In the rest of this documentation, the names "OutputMTU" and "InputMTU" do not refer to the registers
explained here. Instead, they are used as synonyms for the currently enabled Tx or Rx bytes.
Data type Value
USINT See the module-specific register overview (theoretically: 3 to 27)

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FlatStream operation

When using FlatStream, the communication direction is enormously important. For sending data to a module ("out-
put" direction), the Tx bytes are used. For receiving data from a module ("input" direction), the Rx bytes are used.
The "OutputSequence" and "InputSequence" registers are used to control and ensure that communication is taking
place properly, i.e. the transmitter issues the directive that the data should be accepted and the receiver acknowl-
edges that a sequence has been transmitted successfully.

Transporting the payload data and the control bytes

Name:
TxByte1 to TxByteN
RxByte1 to RxByteN
(The value the number N is different depending on the bus controller model used.)
The Tx and Rx bytes are cyclic registers used to transport the payload data and the necessary control bytes. The
number of active Tx and Rx bytes is taken from the configuration of the "OutputMTU" and "InputMTU" registers,
respectively.
In the user program, only the Tx and Rx bytes from the CPU can be used. The corresponding counterparts are
located in the module and are not accessible to the user. For this reason, names were chosen from the CPU point
of view.
• "T" - "Transmit" → CPU transmits data to the module.
• "R" - "Receive" → CPU receives data from the module.
Data type Value
USINT 0 to 65535

Control bytes

In addition to the payload data, the Tx and Rx bytes also transmit the necessary control bytes. These control bytes
contain additional information about the data stream so that the receiver can reconstruct the original message from
the transmitted segments.
Bit structure of a control byte
Bit Name Value Information
0-5 SegmentLength 0 - 63 Size of the subsequent segment in bytes (default: Max. MTU size - 1)
6 nextCBPos 0 Next control byte at the beginning of the next MTU
1 Next control byte directly after the end of the current segment
7 MessageEndBit 0 Message continues after the subsequent segment
1 Message ended by the subsequent segment

SegmentLength
The segment length lets the receiver know the length of the coming segment. If the configured segment length
is insufficient for a message, then the information must be distributed over several segments. In these cases, the
actual end of the message is detected using bit 7 of the control byte.

Information:
The control byte is not included in the calculation to determine the segment length. The segment length
is only derived from the bytes of payload data.
nextCBPos
This bit indicates the position where the next control byte is to be expected. This information is especially important
when using the "MultiSegmentMTU" option.
When using FlatStream communication with multi-segment MTUs, the next control byte is no longer expected in
the first Rx byte of the subsequent MTU, but directly after the current segment.

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MessageEndBit
The "MessageEndBit" is set if the subsequent segment completes a message. The message has then been com-
pletely transmitted and is ready for further processing.

Information:
In the output direction, this bit must also be set if one individual segment is enough to hold the entire
message. The module will only process a message internally if this identifier is detected.
The size of the message being transmitted can be calculated by adding all of the message's segment
lengths together.
FlatStream formula for calculating message length:
Message [bytes] = SegmentLengths (all CBs without ME) + SegmentLength (of the first CB with CB Control byte
ME) ME MessageEndBit

Communication status of the CPU

Name:
OutputSequence
The "OutputSequence" register contains information about the communication status of the CPU. It is written by
the CPU and read by the module.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-2 OutputSequenceCounter 0-7 Counter for the sequences issued in the output direction
3 OutputSyncBit 0 Output direction disabled
1 Output direction enabled
4-6 InputSequenceAck 0-7 Mirrors the InputSequenceCounter value
7 InputSyncAck 0 Input direction not ready (disabled)
1 Input direction ready (enabled)

OutputSequenceCounter
The OutputSequenceCounter is a continuous counter of sequences that have been issued by the CPU. The CPU
uses the OutputSequenceCounter to direct the module to accept a sequence (the output direction must be syn-
chronized when this happens).
OutputSyncBit
The CPU uses the OutputSyncBit to attempt to synchronize the output channel.
InputSequenceAck
InputSequenceAck is used for acknowledgment. The value of the InputSequenceCounter is mirrored if the CPU
has received a sequence successfully.
InputSyncAck
The InputSyncAck bit acknowledges the synchronization of the input channel for the module. This indicates that
the CPU is ready to receive data.

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Communication status of the module

Name:
InputSequence
The "InputSequence" register contains information about the communication status of the module. It is written by
the module and should only be read by the CPU.
Data type Value
USINT See bit structure.

Bit structure:
Bit Name Value Information
0-2 InputSequenceCounter 0-7 Counter for sequences issued in the input direction
3 InputSyncBit 0 Not ready (disabled)
1 Ready (enabled)
4-6 OutputSequenceAck 0-7 Mirrors the InputSequenceCounter value
7 OutputSyncAck 0 Not ready (disabled)
1 Ready (enabled)

InputSequenceCounter
The InputSequenceCounter is a continuous counter of sequences that have been issued by the module. The
module uses the InputSequenceCounter to direct the CPU to accept a sequence (the input direction must be
synchronized when this happens).
InputSyncBit
The module uses the InputSyncBit to attempt to synchronize the input channel.
OutputSequenceAck
OutputSequenceAck is used for acknowledgment. The value of the OutputSequenceCounter is mirrored if the
module has received a sequence successfully.
OutputSyncAck
The OutputSyncAck bit acknowledges the synchronization of the output channel for the CPU. This indicates that
the module is ready to receive data.

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Relationship between OutputSequence and InputSequence

Outputsequenz Input sequence

CPU communication status Module communication status

0-2 OutputSequenceCounter 0-2 InputSequenceCounter

3 OutputSyncBit Intersecting 3 InputSyncBit

4-6 InputSequenceAck Handshakes 4-6 OutputSequenceAck

7 InputSyncAck 7 OutputSyncAck

Figure 418: Relationship between OutputSequence and InputSequence

The "OutputSequence" and "InputSequence" registers are logically composed of two half-bytes. The low part sig-
nals to the opposite station whether a channel should be opened or if data should be accepted. The high part is
to acknowledge that the requested action was carried out.
SyncBit and SyncAck
If SyncBit and SyncAck are set in one communication direction, then the channel is considered "synchronized", i.e.
it is possible to send messages in this direction. The status bit of the opposite station must be checked cyclically.
If SyncAck has been reset, then the SyncBit must be adjusted on that station. Before new data can be transmitted,
the channel needs to be resynchronized.
SequenceCounter and SequenceAck
The communication partners cyclically check whether the low nibble on the opposite station changes. When one
of the communication partners finishes writing a new sequence to the MTU, it increments its SequenceCounter.
The current sequence is then transmitted to the receiver, which acknowledges its receipt with SequenceAck. In
this way, a "handshake" is initiated.

Information:
If communication is interrupted, segments from the unfinished message are discarded. All messages
that were transmitted completely are processed.

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Synchronization

During synchronization, a communication channel is opened. It is important to make sure that a module is present
and that the current value of the SequenceCounter is stored on the station receiving the message.
FlatStream can handle full-duplex communication. This means that both channels / communication directions can
be handled separately. They have to be synchronized independently so that simplex communication can theoret-
ically be carried out as well.

Synchronization in the output direction (CPU as the transmitter):

The corresponding synchronization bits (OutputSyncBit and OutputSyncAck) are reset. Because of this, FlatStream
cannot be used at this point in time to send messages from the CPU to the module.
Algorithm
1) The CPU must write 000 to the OutputSequenceCounter and reset the OutputSyncBit.
The CPU must cyclically query the high nibble of the "InputSequence" register (checks for 000 in OutputSequenceAck and 0 in OutputSyncAck).
The module does not accept the current contents of the InputMTU since the channel is not yet synchronized.
The module matches OutputSequenceAck and OutputSyncAck to the values of the OutputSequenceCounter and OutputSyncBit.
2) If the CPU registers the expected values in OutputSequenceAck and OutputSyncAck, it is allowed to increment the OutputSequenceCounter.
The CPU continues cyclically querying the high nibble of the "OutputSequence" register (checks for 001 in OutputSequenceAck and 0 in InputSyncAck).
The module does not accept the current contents of the InputMTU since the channel is not yet synchronized.
The module matches OutputSequenceAck and OutputSyncAck to the values of the OutputSequenceCounter and OutputSyncBit.
3) When the CPU registers the expected values in OutputSequenceAck and OutputSyncAck, it is allowed to increment the OutputSequenceCounter.
The CPU continues cyclically querying the high nibble of the "OutputSequence" register (checks for 001 in OutputSequenceAck and 1 in InputSyncAck).

Note:
Theoretically, data can be transmitted from this point forward. However, it is still recommended to wait until the output direction is completely synchronized be-
fore transmitting data.
The module sets OutputSyncAck.
The output direction is synchronized, and the CPU can transmit data to the module.

Synchronization in the input direction (CPU as the receiver):

The corresponding synchronization bits (InputSyncBit and InputSyncAck) are reset. Because of this, FlatStream
cannot be used at this point in time to send messages from the module to the CPU.
Algorithm
The module writes 000 to the InputSequenceCounter and resets the InputSyncBit.
The module monitors the high nibble of the "OutputSequence" registers and expects 000 in InputSequenceAck and 0 in InputSyncAck.
1) The CPU is not allowed to accept the current contents of the InputMTU since the channel is not yet synchronized.
The CPU has to match InputSequenceAck and InputSyncAck to the values of InputSequenceCounter and InputSyncBit.
If the module registers the expected values in InputSequenceAck and InputSyncAck, it increments the InputSequenceCounter.
The module monitors the high nibble of the "OutputSequence" registers and expects 001 in InputSequenceAck and 0 in InputSyncAck.
2) The CPU is not allowed to accept the current contents of the InputMTU since the channel is not yet synchronized.
The CPU has to match InputSequenceAck and InputSyncAck to the values of InputSequenceCounter and InputSyncBit.
If the module registers the expected values in InputSequenceAck and InputSyncAck, it sets the InputSyncBit.
The module monitors the high nibble of the "OutputSequence" register and expects 1 in InputSyncAck.
3) The CPU is allowed to set InputSyncAck.

Note:
Theoretically, data can already be transmitted in this cycle.
If the InputSyncBit is set and InputSequenceCounter has been increased by 1, the values in the enabled Rx bytes have to be accepted and acknowledged (see
also "Communication in the input direction").
The input direction is synchronized, and the module can transmit data to the CPU.

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Transmitting and receiving

If a channel is synchronized, then the opposite station is ready to receive messages from the transmitter. Before
the transmitter can send data, it needs to first create a transmit array in order to meet FlatStream requirements.
The transmitting station must also generate a control byte for each segment created. This control byte contains
information about how the subsequent part of the data being transmitted should be processed. The position of the
next control byte in the data stream can vary. For this reason, it must be clearly defined at all times when a new
control byte is being transmitted. The first control byte is always in the first byte of the first sequence. All subsequent
positions are determined recursively.
FlatStream formula for calculating the position of the next control byte:
Position (of the next control byte) = Current position + 1 + Segment length
Example
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The rest of the configuration corresponds to the default settings.

Message 1: Transmit/Receive array

With 7 USINT elements according to

the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Default
Message 2:

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

C2 A7 - - - - - Sequence for bus cycle 2

Message 3:
C3 B1 B2 - - - - Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C4 D1 D2 D3 D4 D5 D6 Sequence for bus cycle 4

No more data to transmit C5 D7 D8 D9 - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 419: Transmit/Receive array (default)

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First, the messages must be split into segments. In the default configuration, it is important to ensure that each
sequence can hold an entire segment, including the associated control byte. The sequence is limited to the size of
the enable MTU. In other words, a segment must be at least 1 byte smaller than the MTU.
MTU = 7 bytes → Max. segment length = 6 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 6 bytes of data

➯ Second segment = Control byte + 1 data byte
• Message 2 (2 bytes)

➯ First segment = Control byte + 2 bytes of data

• Message 3 (9 bytes)

➯ First segment = Control byte + 6 bytes of data

➯ Second segment = Control byte + 3 data bytes
• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C0 (control byte 0) C1 (control byte 1) C2 (control byte 2)
- SegmentLength (0) = 0 - SegmentLength (6) = 6 - SegmentLength (1) = 1
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (0) = 0 - MessageEndBit (0) = 0 - MessageEndBit (1) = 128
Control byte Σ 0 Control byte Σ 6 Control byte Σ 129

Table 430: FlatStream determination of the control bytes for the default configuration example (part 1)
C3 (control byte 3) C4 (control byte 4) C5 (control byte 5)
- SegmentLength (2) = 2 - SegmentLength (6) = 6 - SegmentLength (3) = 3
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (1) = 128 - MessageEndBit (0) = 0 - MessageEndBit (1) = 128
Control byte Σ 130 Control byte Σ 6 Control byte Σ 131

Table 431: FlatStream determination of the control bytes for the default configuration example (part 2)

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Transmitting data to a module (output)

When transmitting data, the transmit array must be generated in the application program. Sequences are then
transmitted one by one using FlatStream and received by the module.

Information:
Although all B&R modules with FlatStream communication always support the most compact trans-
missions in the output direction, it is recommended to use the same design for the transfer arrays in
both communication directions.

PLC / Bus controller Module

Module-internal Module-internal
Transmit array OutputMTU receive buffer receive array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 TxBytes Cyc. *RxBytes _data_01

_data_02 _data_02
When OutputMTU The transmit buffer If the OutputSequence
_data_03 released: of the module is counter is increased: _data_03
adjusted cyclically to
_data_04 CPU fills OutputMTU via X2X Module adds the transmit buffer _data_04
OutputMTU with to the internal array
_data_05 the next sequence
_data_05
... of transmit array If successful: ...
InputSequenceAck is
_data_xx adjusted to the _data_xx
transmit counter

Figure 420: FlatStream communication (output)

The length of the message is initially smaller than the OutputMTU. In this case, one sequence would be sufficient
to transmit the entire message and the necessary control byte.
Algorithms
Cyclic status query:
- The Module monitors the OutputSequenceCounter.
0) Cyclic checks:
- The CPU must check OutputSyncAck.
→ If OutputSyncAck = 0: Reset the OutputSyncBit and resynchronize the channel.
- The CPU must check whether OutputMTU is enabled.
→ If OutputSequenceCounter > InputSequenceAck: MTU is not enabled because the last sequence has not yet been acknowledged.
1) Preparation (create transmit array):
- The CPU must split up the message into valid segments and create the necessary control bytes.
- The CPU must add the segments and control bytes to the transmit array.
2) Transmit:
- The CPU transfers the current element of the transmit array to the OutputMTU.
→ The OutputMTU is transferred cyclically to the module's transmit buffer but not processed further.
- The CPU must increase the OutputSequenceCounter.
Response:
- The module accepts the bytes from the internal receive buffer and adds them to the internal receive array.
- The module sends acknowledgment and writes the value of the OutputSequenceCounter to OutputSequenceAck.
3) Completion:
- The CPU must monitor the OutputSequenceAck.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via OutputSequenceAck. In order to detect potential trans-
mission errors in the last sequence as well, it is important to make sure that the length of the Completion phase is run through long enough.

Note:
To monitor communication times exactly, the task cycles that have passed since the last increase of the OutputSequenceCounter should be counted. In this
way, the number of previous bus cycles necessary for the transmission can be measured. If the monitoring counter exceeds a predefined threshold, then the
sequence can be considered lost.
(The relationship of bus to task cycle can be influenced by the user so that the threshold value needs to be determined individually.)
- Subsequent sequences can only be transmitted in the next bus cycle after the completion check has been carried out successfully.

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Message larger than the OutputMTU

The transmit array, which needs to be created in the program sequence, consists of several elements. The user
has to arrange the control and data bytes correctly and transfer the array elements one after the other. The transfer
algorithm remains the same and is repeated starting at the point Cyclic checks.
General flow chart

Start

► diff = (OutputSequenceCounter -
OutputSequenceAck) AND 7
► limit = (OutputSequenceCounter -
LastValidAck) AND 7

(diff ≤ limit)
No OutputSequenceAck = No LastValidAck = Yes
AND (OutputSyncAck = 1)
AND (OutputSyncBit = 1) ? OutputSequenceCounter ? OutputSequenceCounter ?

Yes Yes No

No LastValidAck =
diff = 0 ?
OutputSequenceAck

Yes

LastValidAck = No
OutputSequenceAck = 0 ?
OutputSequenceAck

Yes

No OutputSequenceCounter = 0
More sequences to be sent ? OutputSequenceCounter = 1 OutputSyncBit = 1
LastValidAck = 0

Yes

copy next sequence to MTU

increase OutputSequenceCounter

Sequence handling Synchronisation

Figure 421: Flow chart for the output direction

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Receiving data from a module (input)

When receiving data, the transmit array is generated by the module, transferred via FlatStream and must then
be reproduced in the receive array. The structure of the incoming data stream can be configured with the mode
register. The algorithm for receiving the data does not change in this regard.
PLC / Bus controller Module
Module-internal Module-internal
Receive array InputMTU transmit buffer transmit array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 RxBytes Cyc. *TxBytes _data_01

_data_02 _data_02
If the InputMTU is If permitted:
_data_03 InputSequence adjusted cyclically Module fills the internal _data_03
counter is increased: to the receive transmit buffer with the
_data_04 buffer via X2X next sequence of the _data_04
InputMTU must be transmit array
_data_05 added to the end
_data_05
... of the receive array Module increases the ...
(increase InputSequenceAck InputSequence counter
_data_xx to end properly) _data_xx

Figure 422: FlatStream communication (input)

Algorithms
0) Cyclic status query:
- The CPU must monitor the InputSequenceCounter.
Cyclic checks:
- The module checks InputSyncAck.
- The module checks InputSequenceAck.
Preparation:
- The module forms the segments and control bytes and creates the transmit array.
Action:
- The module transfers the current element of the internal transmit array to the internal transmit buffer.
- The module increases the InputSequenceCounter.
1) Receiving (as soon as InputSequenceCounter is increased):
- The CPU must accept data from the InputMTU and append it to the end of the receive array.
- The CPU must match InputSequenceAck to the InputSequenceCounter of the sequence currently being processed.
Completion:
- The module monitors InputSequenceAck.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via InputSequenceAck .
- Subsequent sequences are only transmitted in the next bus cycle after the completion check has been carried out successfully.

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General flow chart

Start

► InputSequenceAck = InputSequenceCounter

Synchronisation
No
InputSyncBit = 1 ? ► RemainingSegmentSize = 0
► SegmentFlags = 0
Yes

No No
InputSyncAck = 1 ? InputSequenceAck > 0 ?

Yes Yes

MTU_Offset = 0 InputSyncAck = 1

(InputSequenceCounter – No
InputSequenceAck)
AND 0x07 = 1 ?

Yes
► RemainingSegmentSize =
Yes MTU_Data[MTU_Offset] AND 0b0011 1111
RemainingSegmentSize = 0 ? ► SegmentFlags =
MTU_Data[MTU_Offset] AND 0b1100 0000
No ► MTU_Offset = MTU_Offset + 1

Yes RemainingSegmentSize > No

(InputMTU_Size – MTU_Offset) ?

Segment data handling

► DataSize = InputMTU_Size – MTU_Offset ► DataSize = RemainingSegmentSize

► copy segment data e.g. memcpy(xxx, ADR(MTU_Data[MTU_Offset]), DataSize)

► MTU_Offset = MTU_Offset + DataSize
► RemainingSegmentSize = RemainingSegmentSize - DataSize

RemainingSegmentSize = 0 AND Yes

► Mark Frame as complete
(SegmentFlags AND 0x80) = 0 ?

No

RemainingSegmentSize = 0 AND Yes

(SegmentFlags AND 0x40) = 0 ?

No

Yes
► InputSequenceAck =
InputMTU_Size = MTU_Offset ?
InputSequenceCounter

No

Figure 423: Flow chart for the input direction

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Details

It is recommended to store transmitted messages in separate receive arrays.

After a set MessageEndBit is transmitted, the subsequent segment should be added to the receive array. The
message is then complete and can be passed on internally for further processing. A new/separate array should
be created for the next message.

Information:
When transmitting with MultiSegmentMTUs, it is possible for several small messages to be part of one
sequence. In the program, it's important to make sure that a sufficient number of receive arrays can
be managed. The entire sequence must be accepted before it is possible to change the Acknowledge
register.
If a SequenceCounter is incremented by more than one value, then an error has occurred.
Note: This situation is very unlikely when operating without "Forward" functionality.
In this case, the receiver stops. All additional incoming sequences are ignored until the transmission with the correct
SequenceCounter is retried. This response prevents the transmitter from receiving any more acknowledgments for
transmitted sequences. The transmitter can identify the last successfully transmitted sequence from the opposite
station's SequenceAck and continue the transmission from this point.
Acknowledgments must be checked for validity.
If the receiver has successfully accepted a sequence, it must be acknowledged. The receiver takes on the Se-
quenceCounter value sent along with the transmission and matches the SequenceAck to it. The transmitter reads
the SequenceAck and registers the successful transmission. If the transmitter acknowledges a sequence that has
not yet been dispatched, then the transmission needs to be interrupted and the channel resynchronized. The syn-
chronization bits are reset and the current/incomplete message is discarded. It needs to be sent again once the
channel has been resynchronized.

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FlatStream mode

Name:
FlatstreamMode
In the input direction, the transmit array is generated automatically. This register offers two options to the user
that allow an incoming data stream to have a more compact arrangement. Once enabled, the program code for
evaluation must be adapted accordingly.

Information:
All B&R modules that offer FlatStream mode support the options "Large segments" and "MultiSeg-
mentMTUs" in the output direction. Compact transmission only needs to be explicitly allowed in the
input direction.
Bit structure:
Bit Name Value Information
0 MultiSegmentMTU 0 Not allowed (default)
1 Allowed
1 Large segments 0 Not allowed (default)
1 Allowed
2-7 Reserved

Default
By default, both options relating to compact transmission in the input direction are disabled.
1. The module only forms segments that are at least one byte smaller than the enabled MTU. Each sequence
begins with a control byte so that the data stream is clearly structured and relatively easy to evaluate.
2. Since a FlatStream message can be of any length, the last segment of the message frequently doesn't fill up
all of the MTU's space. By default, the remaining bytes during this type of transfer cycle are not used.

Bus cycle 1 Bus cycle 2 Bus cycle 3

C C C
- - -
ME0 ME1 ME1

Segment 1 Segment 2 Segment 3

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 424: Message arrangement in the MTU (default)

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MultiSegmentMTUs allowed
With this option, the InputMTU is completely filled (if enough data is pending). The previously unfilled Rx bytes
transmit the next control bytes and their segments. This allows the enabled Rx bytes to be used more efficiently.
Bus cycle 1 Bus cycle 2 Bus cycle 3

C C C C
- -
ME0 ME1 ME0 ME1

Segment 1 Segment 2 3 Segment 4

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 425: Arrangement of messages in the MTU (MultiSegmentMTUs)

Large segments allowed
When transmitting very long messages or when enabling only very few Rx bytes, then a great many segments must
be created by default. The bus system is more stressed than necessary since an additional control byte needs to
be created and transmitted for each segment. With the "Large segments" option, the segment length is limited to
63 bytes independently of the InputMTU. One segment can stretch across several sequences, i.e. it is possible for
"pure" sequences to occur without a control byte.

Information:
It is still possible to split up a message into several segments, however. If this option is used and
messages with more than 63 bytes occur, for example, then messages can still be split up among
several segments.

Bus cycle 1 Bus cycle 2 Bus cycle 3

C C
- - - -
ME1 ME1

Segment 1 Segment 2 Segment 3

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 426: Arrangement of messages in the MTU (large segments)

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Using both options

It is also possible to use both options at the same time.
Bus cycle 1 Bus cycle 2 Bus cycle 3

C C
- - - -
ME1 ME1

Segment 1 Segment 2 Segment 3

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 427: Arrangement of messages in the MTU (large segments and MultiSegmentMTUs)

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Adjusting the FlatStream

If the way messages are structured is changed, then the way data in the transmit/receive array is arranged is also
different. The following changes apply to the example given earlier.
MultiSegmentMTU
If MultiSegmentMTUs are allowed, then "open positions" in an MTU can be used. These "open positions" occur if
the last segment in a message does not fully use the entire MTU. MultiSegmentMTUs allow these bits to be used to
transmit the subsequent control bytes and segments. In the program sequence, the "nextCBPos" bit in the control
byte is set so that the receiver can correctly identify the next control byte.
Example
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The configuration allows transmission of MultiSegmentMTUs.
Message 1: Transmit/Receive array

With 7 USINT elements according to

the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Message 2: MultiSegmentMTU

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

C2 A7 C3 B1 B2 C4 D1 Sequence for bus cycle 2

Message 3:
C5 D2 D3 D4 D5 D6 D7 Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C6 D8 D9 C0 - - - Sequence for bus cycle 4

No more data to transmit C0 - - - - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 428: Transmit/receive array (MultiSegmentMTUs)

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First, the messages must be split into segments. As in the default configuration, it is important for each sequence
to begin with a control byte. The free bits in the MTU at the end of a message are filled with data from the following
message, however. With this option, the "nextCBPos" bit is always set if payload data is sent after the control byte.
MTU = 7 bytes → Max. segment length = 6 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 6 bytes of data (MTU full)

➯ Second segment = Control byte + 1 byte of data (MTU still has 5 open bytes)
• Message 2 (2 bytes)

➯ First segment = Control byte + 2 bytes of data (MTU still has 2 open bytes)
• Message 3 (9 bytes)

➯ First segment = Control byte + 1 byte of data (MTU full)

➯ Second segment = Control byte + 6 bytes of data (MTU full)
➯ Third segment = Control byte + 2 bytes of data (MTU still has 4 open bytes)
• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C1 (control byte 1) C2 (control byte 2) C3 (control byte 3)
- SegmentLength (6) = 6 - SegmentLength (1) = 1 - SegmentLength (2) = 2
- nextCBPos (1) = 64 - nextCBPos (1) = 64 - nextCBPos (1) = 64
- MessageEndBit (0) = 0 - MessageEndBit (1) = 128 - MessageEndBit (1) = 128
Control byte Σ 70 Control byte Σ 193 Control byte Σ 194

Table 432: FlatStream determination of the control bytes for the MultiSegmentMTU example (part 1)

Warning!
The second sequence must have been completely processed before it can be acknowledged with Se-
quenceAck. In this example, there are three different segments within the second sequence, i.e. the
program must include enough receive arrays to handle this situation.
C4 (control byte 4) C5 (control byte 5) C6 (control byte 6)
- SegmentLength (1) = 1 - SegmentLength (6) = 6 - SegmentLength (2) = 2
- nextCBPos (6) = 6 - nextCBPos (1) = 64 - nextCBPos (1) = 64
- MessageEndBit (0) = 0 - MessageEndBit (1) = 0 - MessageEndBit (1) = 128
Control byte Σ 7 Control byte Σ 70 Control byte Σ 194

Table 433: FlatStream determination of the control bytes for the MultiSegmentMTU example (part 2)

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Large segments
Segments are limited to a maximum of 63 bytes. This means they can be larger than the active MTU. These large
segments are divided among several sequences when transmitted. It is possible for sequences to be completely
filled with payload data and not have a control byte.

Information:
It is still possible to subdivide a message into several segments so that the size of a data packet does
not also have to be limited to 63 bytes.
Example
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The configuration allows the transmission of large segments.

Message 1: Transmit/Receive array

With 7 USINT elements according to

the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Message 2: Large segments

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

A7 - - - - - - Sequence for bus cycle 2

Message 3:
C2 B1 B2 - - - - Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C3 D1 D2 D3 D4 D5 D6 Sequence for bus cycle 4

No more data to transmit D7 D8 D9 - - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 429: Transmit/receive array (large segments)

First, the messages must be split into segments. The ability to form large segments means that messages are split
up less frequently, which results in fewer control bytes generated.
Large segments allowed → Max. segment length = 63 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 7 bytes of data

• Message 2 (2 bytes)

➯ First segment = Control byte + 2 bytes of data

• Message 3 (9 bytes)

➯ First segment = Control byte + 9 bytes of data

• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C1 (control byte 1) C2 (control byte 2) C3 (control byte 3)
- SegmentLength (7) = 7 - SegmentLength (2) = 2 - SegmentLength (9) = 9
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (1) = 128 - MessageEndBit (1) = 128 - MessageEndBit (1) = 128
Control byte Σ 135 Control byte Σ 130 Control byte Σ 137

Table 434: FlatStream determination of the control bytes for the large segment example

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Large segments and MultiSegmentMTU

Example
Three autonomous messages (7 bytes, 2 bytes and 9 bytes) are being transmitted using an MTU with a width of
7 bytes. The configuration allows transmission of large segments as well as MultiSegmentMTUs.
Message 1: Transmit/Receive array
With 7 USINT elements according to
the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Message 2: Both options

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

A7 C2 B1 B2 C3 D1 D2 Sequence for bus cycle 2

Message 3:
D3 D4 D5 D6 D7 D8 D9 Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C0 - - - - - - Sequence for bus cycle 4

No more data to transmit C0 - - - - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 430: Transmit/receive array (large segments and MultiSegmentMTUs)

First, the messages must be split into segments. If the last segment of a message does not completely fill the
MTU, it can be used for other data in the data stream. The "nextCBPos" bit must always be set if the control byte
belongs to a segment with payload data.
The ability to form large segments means that messages are split up less frequently, which results in fewer control
bytes generated. Control bytes are generated in the same way as with the "Large segments" option.
Large segments allowed → Max. segment length = 63 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 7 bytes of data

• Message 2 (2 bytes)

➯ First segment = Control byte + 2 bytes of data

• Message 3 (9 bytes)

➯ First segment = Control byte + 9 bytes of data

• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C1 (control byte 1) C2 (control byte 2) C3 (control byte 3)
- SegmentLength (7) = 7 - SegmentLength (2) = 2 - SegmentLength (9) = 9
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (1) = 128 - MessageEndBit (1) = 128 - MessageEndBit (1) = 128
Control byte Σ 135 Control byte Σ 130 Control byte Σ 137

Table 435: FlatStream determination of the control bytes for the large segment and MultiSegmentMTU example

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4.16.4.10.10.5 Example of Forward functionality on X2X Link

Forward functionality is a method that can be used to substantially increase the FlatStream data rate. The basic
principle is also used in other technical areas such as "pipelining" for microprocessors.

Operating principle

X2X Link communication cycles through five different steps to transmit a FlatStream sequence. At least five bus
cycles are therefore required to successfully transfer the sequence.
Step I Step II Step III Step IV Step V
Actions Transfer sequence from Cyclic matching of MTU and Append sequence to re- Cyclic matching of Check SequenceAck
transmit array, module buffer ceive array MTU and module buffer
increase Sequence- Adjust SequenceAck
Counter
Resource Transmitter Bus system Recipient Bus system Transmitter
(task to transmit) (direction 1) (task to receive) (direction 2) (task for Ack checking)

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 ...

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Figure 431: Comparison of transmission without/with Forward

Each of the five steps (tasks) requires different resources. If Forward functionality is not used, the sequences are
executed one after the other. Each resource is then only active if it is needed for the current sub-action.
With Forward, a resource that has executed its task can already be used for the next message. The condition for
enabling the MTU is changed to allow for this. Sequences are then passed to the MTU according to the timing. The
transmitting station no longer waits for an acknowledgment from SequenceAck, which means that the available
bandwidth can be used much more efficiently.
In the most ideal situation, all resources are working during each bus cycle. The receiver still has to acknowledge
every sequence received. Only when SequenceAck has been changed and checked by the transmitter is the
sequence considered as having been transmitted successfully.

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Configuration

The Forward function only has to be enabled for the input direction. Two additional configuration registers are
available for doing so. FlatStream modules have been optimized in such a way that they support this function. In
the output direction, the Forward function can be used as soon as the size of the OutputMTU is specified.

Number of unconfirmed sequences

Name:
Forward
With the "Forward" register, the user specifies how many unacknowledged sequences the module is allowed to
transmit.
Recommendation:
X2X Link: Max. 5
POWERLINK: Max. 7
Data type Value
USINT 1 to 7
Default: 1

Delay time

Name:
ForwardDelay
The "ForwardDelay" register is used to specify the delay time in µs. This is the amount of time the module has
to wait after sending a sequence until it is allowed to write new data to the MTU in the following bus cycle. The
program routine for receiving sequences from a module can therefore be run in a task class whose cycle time is
slower than the bus cycle.
Data type Value
UINT 0 to 65,535 [µs]
Default: 0

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Zeit

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Zeit

Figure 432: Effect of ForwardDelay when using FlatStream communication with the Forward function
In the program, it is important to make sure that the CPU is processing all of the incoming InputSequences and In-
putMTUs. The ForwardDelay value causes delayed acknowledgment in the output direction and delayed reception
in the input direction. In this way, the CPU has more time to process the incoming InputSequence or InputMTU.

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Transmitting and receiving with Forward

The basic algorithm for transmitting and receiving data remains the same. With the Forward function, up to seven
unacknowledged sequences can be transmitted. Sequences can be transmitted without having to wait for the
previous message to be acknowledged. Since the delay between writing and response is eliminated, a considerable
amount of additional data can be transferred in the same time window.
Algorithm for transmitting
Cyclic status query:
- The Module monitors the OutputSequenceCounter.
0) Cyclic checks:
- The CPU must check OutputSyncAck.
→ If OutputSyncAck = 0: Reset the OutputSyncBit and resynchronize the channel.
- The CPU must check whether OutputMTU is enabled.
→ If OutputSequenceCounter > OutputSequenceAck + 7, then it is not enabled because the last sequence has not yet been acknowledged.
1) Preparation (create transmit array):
- The CPU must split up the message into valid segments and create the necessary control bytes.
- The CPU must add the segments and control bytes to the transmit array.
2) Transmit:
- The CPU must transfer the current part of the transmit array to the OutputMTU.
- The CPU must increase the OutputSequenceCounter for the sequence to be accepted by the module.
- The CPU can then transmit in the next bus cycle if the MTU has been enabled.
The module responds since OutputSequenceCounter > OutputSequenceAck:
- The module accepts data from the internal receive buffer and appends it to the end of the internal receive array.
- The module is acknowledged and the currently received value of the OutputSequenceCounter is transferred to OutputSequenceAck.
- The module requests the status cyclically again.
3) Completion (acknowledgment):
- The CPU must check OutputSequenceAck cyclically.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via OutputSequenceAck. In order to detect potential trans-
mission errors in the last sequence as well, it is important to make sure that the algorithm is run through long enough.

Note:
To monitor communication times exactly, the task cycles that have passed since the last increase of the OutputSequenceCounter should be counted. In this
way, the number of previous bus cycles necessary for the transmission can be measured. If the monitoring counter exceeds a predefined threshold, then the
sequence can be considered lost (the relationship of bus to task cycle can be influenced by the user so that the threshold value needs to be determined individ-
ually).

Algorithm for receiving

0) Cyclic status query:
- The CPU must monitor the InputSequenceCounter.
Cyclic checks:
- The module checks InputSyncAck.
- The module checks if InputMTU is enabled.
→ Enabling criteria: InputSequenceCounter > InputSequenceAck + Forward
Preparation:
- The module forms the control bytes / segments and creates the transmit array.
Action:
- The module transmits the current part of the transmit array to the receive buffer.
- The module increases the InputSequenceCounter.
- The module waits for a new bus cycle after the ForwardDelay time has expired.
- The module repeats the action if the InputMTU is enabled.
1) Receiving (InputSequenceCounter > InputSequenceAck):
- The CPU must accept data from the InputMTU and append it to the end of the receive array.
- The CPU must match InputSequenceAck to the InputSequenceCounter of the sequence currently being processed.
Completion:
- The module monitors InputSequenceAck.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via InputSequenceAck .

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Details/Background
1. Illegal SequenceCounter size (counter offset)
Error situation: MTU not enabled
If the difference between SequenceCounter and SequenceAck is larger than allowed during transmission,
then a transmission error has occurred. In this case, all unacknowledged sequences must be repeated with
the old SequenceCounter value.
2. Checking an acknowledgment
After an acknowledgment has been received, a check must verify whether the acknowledged sequence has
been transmitted and had not yet been unacknowledged. If a sequence has been acknowledged more than
once, then a fatal error has occurred. The channel must be closed and resynchronized (same behavior as
when not using Forward).

Information:
In exceptional cases, the module can increment OutputSequenceAck by more than 1 when using
Forward.
This is not an error. The CPU is permitted to consider all sequences up to the one being acknowl-
edged as having been transmitted successfully.

3. Transmit and receive arrays

The Forward function has no effect on the structure of the transmit and receive arrays. They are created and
must be evaluated in the same way.

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Errors when using Forward

In industrial environments, it is often the case that many different devices from various manufacturers are being
used side by side. The electrical and/or electromagnetic properties of these technical devices can sometimes cause
them to interfere with one another. These kinds of situations can be reproduced and protected against in laboratory
conditions only to a certain point.
Precautions have been taken for X2X Link transmissions if this type of interference occurs. For example, if an
invalid checksum occurs, the I/O system will ignore the data from this bus cycle and the receiver receives the last
valid data once more. With conventional (cyclic) data points, this error can often be ignored. In the following cycle,
the same data point is again retrieved, adjusted and transmitted.
Using Forward functionality with FlatStream communication makes this situation more complex. The receiver re-
ceives the old data again in this situation as well, i.e. the previous values for SequenceAck/SequenceCounter and
the old MTU.
Loss of acknowledgment (SequenceAck)
If a SequenceAck value is lost, then the MTU was already transmitted properly. For this reason, the receiver is per-
mitted to continue processing with the next sequence. The SequenceAck is aligned with the associated Sequence-
Counter and sent back to the transmitter. Checking the incoming acknowledgments shows that all sequences up
to the last one acknowledged have been transmitted successfully (see sequences 1 and 2 in the image).
Loss of transmission (SequenceCounter, MTU):
If a bus cycle drops out and the SequenceCounter value and/or filled MTU are lost, then no data reaches the
receiver. At this point, the transmission routine is not yet affected by the error. The time-controlled MTU is released
again and can be rewritten to.
The receiver receives SequenceCounter values that have been incremented several times. For the receive array
to be put together correctly, the receiver is only allowed to process transmissions whose SequenceCounter has
been increased by one. The incoming sequences must be ignored, i.e. the receiver stops and no longer transmits
back any acknowledgments.
If the maximum number of unacknowledged sequences has been sent and no acknowledgments are returned, the
transmitter must repeat the affected SequenceCounter and associated MTUs (see sequence 3 and 4 in the image).

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Sequence 4 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Sequence 1 Step I Step II Step III

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step I Step II Step III

Sequence 4 Step I Step II Step I Step II

Bus cycle 1 Bus cycle 2 Bus cycle 3 EMC Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Figure 433: Effect of a lost bus cycle

Loss of acknowledgment
In sequence 1, the acknowledgment is lost due to disturbance. Sequences 1 and 2 are therefore acknowledged
in Step V of sequence 2.
Loss of transmission
In sequence 3, the entire transmission is lost due to disturbance. The receiver stops and no longer sends back
any acknowledgments.
The transmitting station continues transmitting until it has issued the maximum permitted number of unacknowl-
edged transmissions.
Five bus cycles later at the earliest (depending on the configuration), it begins resending the unsuccessfully sent
transmissions.

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4.16.4.10.11 HIPERFACE with FlatStream

HIPERFACE is an asynchronous interface capable of half-duplex communication. Various features have been
included to ensure that signals are transmitted without errors.
• The user can choose to have a parity bit added when transmitting a data block.
• A checksum is sent together with a signal and evaluated by the receiver.
• The command to which the encoder is responding is repeated at the start of a response.
In FlatStream mode, the module acts as a bridge between the CPU and the HIPERFACE slave. HIPERFACE-spe-
cific algorithms have been implemented to monitor timeouts and handle checksums. During normal operation, the
user does not have access to these details.
Additional information is provided in the "Description of HIPERFACE" document.

4.16.4.10.11.1 Overview of conventional HIPERFACE commands for FlatStream mode

Command byte [hex] Command Code0
0x42 Read position
0x43 Set position ●
0x44 Read analog value
0x46 Read counter
0x47 Increment counter
0x49 Delete counter ●
0x4A Read data
0x4B Save data
0x4C Read status of a data field
0x4D Create data field
0x4E Read available memory area
0x4F Change access key
0x50 Read encoder status
0x52 Read nameplate
0x53 Reset encoder
0x55 Allocate encoder address ●
0x56 Read serial number and program version
0x57 Configure serial interface ●

Code0 is a byte that was added to the transfer protocol for safety reasons. It protects important system parameters
from being overwritten by mistake (default: Code0 = 0x55).

4.16.4.10.11.2 Read position (0x42)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x42 Command byte (read position)
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address and command byte (safety)
2 0x42
3 Pos_HH Response (data bytes)
4 Pos_HL
5 Pos_LH
6 Pos_LL
Master

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4.16.4.10.11.3 Set position (0x43)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x43 Command byte (set position)
3 Pos_HH New position (data bytes)
4 Pos_HL
5 Pos_LH
6 Pos_LL
7 Code0 Safety byte in accordance with the HIPERFACE specification
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address and command byte (safety)
2 0x43
Master

4.16.4.10.11.4 Read analog value (0x44)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x44 Command byte (read analog value)
3 Channel Channel byte (selects desired analog value)
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address, command byte and channel byte (safety)
2 0x44
3 Channel
4 Value_H Value read
5 Value_L
Master

4.16.4.10.11.5 Read counter (0x46)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x46 Command byte (read counter)
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address and command byte (safety)
2 0x46
3 Ctr_H Counter value
4 Ctr_M
5 Ctr_L
Master

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4.16.4.10.11.6 Increment counter (0x47)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x47 Command byte (increment counter)
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address and command byte (safety)
2 0x47
Master

4.16.4.10.11.7 Clear counter (0x49)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x49 Command byte (clear counter)
3 Code0 Safety byte in accordance with the HIPERFACE specification
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address and command byte (safety)
2 0x49
Master

4.16.4.10.11.8 Read data (0x4A)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x4A Command byte (read data)
3 Data field ID of data to be read:
4 Byte address Number of the data field, start byte within the data field and number of bytes to be read
5 Count
6 Access code Access code in accordance with the HIPERFACE specification
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address, command byte and ID of data to be read (safety)
2 0x4A
3 Data field
4 Byte address
5 Count
6...n Data1...n Data to be read
Master

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4.16.4.10.11.9 Save data (0x4B)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x4B Command byte (save data)
3 Data field ID of data to be saved:
4 Byte address Number of the data field, start byte within the data field and number of bytes to be read
5 Count
6 Access code Access code in accordance with the HIPERFACE specification
7...x Data1...n Data to be saved
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address, command byte and ID of data to be saved (safety)
2 0x4B
3 Data field
4 Byte address
5 Count
Master

4.16.4.10.11.10 Read status of a data field (0x4C)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x4C Command byte (determine status of a data field)
3 Data field Number of the data field
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address, command byte and number of the data field (safety)
2 0x4C
3 Data field
4 Status Access mode for queried data field
Master

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4.16.4.10.11.11 Create data field (0x4D)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x4D Command byte (create data field)
3 Data field Number of the data field
4 Status Access mode for the data field
5 Access code Access code in accordance with the HIPERFACE specification
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address, command byte, number of the data field and access mode of the data field (safety)
2 0x4D
3 Data field
4 Status
Master

4.16.4.10.11.12 Read available memory area (0x4E)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x4E Command byte (read available memory area)
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address and command byte (safety)
2 0x4E
3 Free memory Number of available 16-byte blocks
4 Number of Number of data fields
data fields
Master

4.16.4.10.11.13 Change access key (0x4F)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x4F Command byte (change access key)
3 Code number Safety code from the slave manufacturer
4 Old code
5 New code
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address, command byte and code number (safety)
2 0x4F
3 Code number
Master

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4.16.4.10.11.14 Read encoder status (0x50)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x50 Command byte (read encoder status)
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address and command byte (safety)
2 0x50
3 Encoder Status byte as specified by the slave manufacturer
status
Master

4.16.4.10.11.15 Read nameplate (0x52)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x52 Command byte (read nameplate)
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address and command byte (safety)
2 0x52
3 RS485 Nameplate in accordance with HIPERFACE specification:
settings HIPERFACE configuration, type of encoder, size of memory and other options
4 Encoder type
5 Size of
EEPROM
6 Options
Master

4.16.4.10.11.16 Encoder reset (0x53)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x53 Command byte (encoder reset)
Slave

Slave response
Protocol bytes Information
No. Name
Slave
- - No response
Master

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4.16.4.10.11.17 Allocate encoder address (0x55)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x55 Command byte (allocate encoder address)
3 New address New HIPERFACE address
4 Code0 Safety byte in accordance with the HIPERFACE specification
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address and command byte (safety)
2 0x55
Master

4.16.4.10.11.18 Read serial number and program version (0x56)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x56 Command byte (read serial number and program version)
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address and command byte (safety)
2 0x56
3...11 Serial number 9 characters
12...n Firmware Max. 20 characters
version
...n+8 Firmware date 8 characters (format: DD.MM.YY)
Master

4.16.4.10.11.19 Configure serial interface (0x57)

Master command
Protocol bytes Information
No. Name
Master
1 Address Address of the HIPERFACE slave
2 0x57 Command byte (configure serial interface)
3 RS485 New baud rate in accordance with the HIPERFACE specification
settings
4 Code0 Safety byte in accordance with the HIPERFACE specification
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 Address Repeated address, command byte and new baud rate (safety)
2 0x57
3 RS485
settings
Master

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4.16.4.10.12 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without causing a communication error
or impaired functionality. It should be noted that very fast cycles decrease the idle time available for handling
monitoring, diagnostics and acyclic commands.
Minimum cycle time
100 µs

4.16.4.10.13 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
100 µs

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4.16.5 X20DS1928

4.16.5.1 General information

The X20DS1928 module is equipped with an EnDat encoder interface. The X20DS1928 automatically detects
whether an encoder is connected with EnDat 2.1 or EnDat 2.2. This module can be used to evaluate encoders
installed in B&R servo motors as well as encoders for external axes (encoders that scan any machine movement).
The input signals are monitored. This makes it possible to detect open or shorted lines as well as encoder supply
failures.
• EnDat 2.1 and EnDat 2.2 encoder interface
• Encoder input monitoring
• 5 VDC and GND for encoder supply
• NetTime function: Time stamp for position
EnDat encoders
EnDat is a standard developed by Johannes Heidenhain GmbH (www.heidenhain.de) that incorporates the advan-
tages of absolute and incremental position measurement and also offers a read/write parameter memory in the
encoder. With absolute position measurement, the homing procedure is generally not required. Where necessary
a multi-turn encoder should be installed. To save costs, a single-turn encoder and a reference switch can also be
used. In this case, a homing procedure must be carried out.
NetTime position timestamp
Highly dynamic positioning tasks require not only the position value, but also the exact time at which the position
was determined. The module has a NetTime function for this, which adds a timestamp to the recorded position
with microsecond accuracy.
The module provides the PLC with the position value and timestamp as absolute time value. The NetTime mech-
anisms ensure that the PLC NetTime clock and the local NetTime clock on the module have exactly the same
absolute time at all times.

4.16.5.2 Order data

Model number Short description Figure

Digital signal processing and preparation
X20DS1928 X20 digital signal module, 1x EnDat 2.1/2.2, NetTime module
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Terminal blocks
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 436: X20DS1928 - Order data

4.16.5.3 Technical data

Product ID X20DS1928
Short description
I/O module 1x EnDat interface
General information
B&R ID code 0xA912
Status indicators Counting direction, operating status, module status
Diagnostics
Module run/error Yes, using status LED and software status
Counting direction Yes, with status LED
Power consumption
Bus 0.01 W
I/O internal 1.3 W

Table 437: X20DS1928 - Technical data

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Product ID X20DS1928
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
Channel - Bus Yes
Channel - Channel No
Type of signal lines Shielded cables should be used for all signal lines
Certification
CE Yes
c-UL-us In preparation
GOST-R Yes
Encoder inputs
Type EnDat 2.1/2.2
Angular position resolution 13-bit, with a 1 VSS signal
Encoder monitoring Yes
Max. encoder cable length 10 m, with a line cross-section of #≥0.5 mm²
Sine-cosine inputs
Signal transfer Differential signals, symmetric
Signal frequency DC up to 400 kHz
Differential voltage 1 VSS
Common mode voltage Max. ±10 V
Terminating resistor 120 Ω
Encoder supply
Output voltage 5V
Load capability 300 mA
Protective measures / safeguards
Overload protection Yes
Short circuit protection Yes
Serial EnDat interface
Signal transfer 5 VDC differential signal, EiA RS-485 standard
Transfer status See EnDat specification
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at altitudes above sea level
0 to 2000 m No limitations
> 2000 m Reduction of ambient temperature by 0,5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating When operated at temperatures above 55°C, the power consumption of
the modules to the left and right of this module must not exceed 1.15 W.
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%
Storage 5 to 95%
Transport 5 to 95%
Mechanical characteristics
Note Order 1x X20TB12 terminal block separately
Order 1x X20BM11 bus module separately
Spacing 12.5+0.2 mm

Table 437: X20DS1928 - Technical data

4.16.5.4 Status LEDs

Image LED Color Status Description

r Green Off Module supply not connected
Single flash Reset mode
Double flash Linked mode
Blinking PREOPERATIONAL mode
On RUN mode
e Red Off Module supply not connected or everything is OK
On Error or reset state - Possible cause:
• Encoder supply error
Single flash I/O error - Possible causes:
• Sine/Cosine relative position error (open line)
• Sine/Cosine absolute position error (reference)

Table 438: Status display

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Image LED Color Status Description
Double flash System error - Possible causes:
• EnDat communication error
• EnDat position error
• EnDat error defining parameters
Tripple flash I/O error and system error
Single flash, inverted Error or reset state and I/O error
Double flash, inverted Error or reset state and system error
Triple flash, inverted Error or reset state, I/O error and system error
UP Green On The UP/DN LEDs are lit depending on the rotational direction and the
speed of the connected encoder.
The UP LED indicates when the encoder position changes in the pos-
itive direction.
DN Green On The DN LED indicates when the encoder position changes in the neg-
ative direction.

Table 438: Status display

4.16.5.5 Pinout

Shielded cables should be used for all signal lines.

X20 DS 1928 r e
UP
DN

B\ B

A\ A

D\ D

T\ T

Encoder 5V + GND

4.16.5.6 Connection example

DS EnDat Encoder

B\
B Incremental signals
A\ (sine-cosine track)
A

D\
D Serial EnDat
T\ Interface
T

+24 VDC +24 VDC

GND GND

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4.16.5.7 Input diagram for the incremental signals (sine-cosine track)

A/D Input value

Converter

A\

A/D Input value

Converter

B\

4.16.5.8 Input diagram for the serial EnDat interface

D DIN

RS485
Drivers DOUT
D\

T
RS485
Drivers DOUT

Transmitter
T\

4.16.5.9 Encoder supply scheme and LEDs

24 V UP
DC
Encoder 5 V
DC

LED (green)
GND

GND
DN

LED (green)

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4.16.5.10 Register description

4.16.5.10.1 Register overview - Function model 0 (standard)

Register Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Module configuration
513 CfO_SIframeGenID USINT ●
654 CfO_SystemCyclePrescaler UINT ●
Basic functions
683 SDCLifeCount SINT ● ●
4180 PositionHW_64 UDINT ● ●
PositionLW_64 UDINT
4188 ● ●
Position_32 DINT
4172 PosTime_32 DINT ● ●
4174 PosTime_16 INT ● ●
4163 PosCycle_8 SINT ● ●
Error management
389 ErrorEnableID_1710 USINT ●
261 ErrorInfo USINT ● ●
325 AckErrorInfo USINT ● ●
4352 EnDatError UINT ● ●
4353 EnDatWarning UINT ● ●
4099 EnDatAck USINT ● ●
Sin/Cos - Configuration
1025 SinCosEnable USINT ●
1027 SinCosRefSource USINT ●
1034 SinCosVssMin UINT ●
1038 SinCosVssMax UINT ●
1044 SinCosQuitTime UDINT ●
EnDat - Read ID
4097 EnDatMode USINT ●
4400 + OperatingParam_00
UINT ●
Index OperatingParam_[01…15]
4352 + OperatingStatus_00
UINT ●
Index OperatingStatus_[01…03]
4352 + ParamManuf_04
UINT ●
Index ParamManuf_[05…47]
4416 + ParamManufEnDat22_00
UINT ●
Index ParamManufEnDat22_[01…63]
EnDat - Read additional information
4860 + EnDatInfoCmd01
UDINT ●
Index*8 EnDatInfoCmd[02...04]
4935 EnDatInfoOKByte USINT ● ●
EnDatInfo01_u16
UINT
4978 + EnDatInfo[02...04]_u16
● ●
Index*16 EnDatInfo01_s16
INT
EnDatInfo[02...04]_s16
Flatstream mode
4609 OutputMTU USINT ●
4611 InputMTU USINT ●
4613 FlatStreamMode USINT ●
4615 Forward USINT ●
4620 ForwardDelay UINT ●
4672 InputSequence USINT ● ●
4672 + RxByte1
USINT ● ●
Index RxByte[2…15]
4704 OutputSequence USINT ● ●
4704 + TxByte1
USINT ● ●
Index TxByte[2…15]

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4.16.5.10.2 Variable assignment in Automation Studio (X2X master)

Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Basic functions
SDCLifeCount SINT ●
PositionHW UDINT ●
PositionLW UDINT
●
Position DINT
DINT
PosTime ●
INT
PosCycle SINT ●
Error management
EnDatError UINT ●
EnDatWarning UINT ●
EnDatAck USINT ●
ErrorInfo USINT
→ EncoderSupplyError BOOL
→ VssCheckError BOOL
→ SinCosPosError BOOL
●
→ EnDatComError BOOL
→ EnDatPosError BOOL
→ EnDatParSetError BOOL
→ EnDatRefWarning BOOL
AckErrorInfo USINT
→ AckEncoderSupplyError BOOL
→ AckVssCheckError BOOL
→ AckSinCosPosError BOOL
●
→ AckEnDatComError BOOL
→ AckEnDatPosError BOOL
→ AckEnDatParSetError BOOL
→ AckEnDatRefWarning BOOL
EnDat - Read additional information
EnDatInfoOK01
USINT ●
EnDatInfoOK[02…04]
EnDatInfo01 UINT
●
EnDatInfo[02…04] INT
Flatstream mode
InputSequence USINT ●
RxByte1
USINT ●
RxByte[2…15]
OutputSequence USINT ●
TxByte1
USINT ●
TxByte[2…15]

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4.16.5.10.3 Register overview - Bus controller function model 254

Register Object offset Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Module configuration
513 - CfO_SIframeGenID USINT ●
654 - CfO_SystemCyclePrescaler UINT ●
Basic functions
4180 0 PositionHW_64_CANIO UDINT ●
4188 4 PositionLW_64_CANIO UDINT ●
4163 15 PosCycle_8_CANIO SINT ●
Error management
389 - ErrorEnableID_1710 USINT ●
261 14 ErrorInfo_CANIO USINT ●
325 6 AckErrorInfo_CANIO USINT ●
4352 - EnDatError UINT ●
4353 - EnDatWarning UINT ●
4099 - EnDatAck USINT ●
Sin/Cos - Configuration
1025 - SinCosEnable USINT ●
1027 - SinCosRefSource USINT ●
1034 - SinCosVssMin UINT ●
1038 - SinCosVssMax UINT ●
1044 - SinCosQuitTime UDINT ●
EnDat - Read ID
4097 - EnDatMode USINT ●
4400 + OperatingParam_00
- UINT ●
Index OperatingParam_[01…15]
4352 + OperatingStatus_00
- UINT ●
Index OperatingStatus_[01…03]
4352 + ParamManuf_04
- UINT ●
Index ParamManuf_[05…47]
4416 + ParamManufEnDat22_00
- UINT ●
Index ParamManufEnDat22_[01…63]
EnDat - Read additional information
4860 + EnDatInfoCmd01
- UDINT ●
Index*8 EnDatInfoCmd[02...04]
4935 - EnDatInfoOKByte USINT ●
EnDatInfo01_u16
UINT
4978 + EnDatInfo[02...04]_u16
- ●
Index*16 EnDatInfo01_s16
INT
EnDatInfo[02...04]_s16
Flatstream mode
4609 - OutputMTU USINT ●
4611 - InputMTU USINT ●
4613 - FlatStreamMode USINT ●
4615 - Forward USINT ●
4620 - ForwardDelay UDINT ●
4704 0 OutputSequence_CANIO USINT ●
4704 + TxByte1_CANIO
1…5 USINT ●
Index TxByte[2…5]_CANIO
4672 8 InputSequence_CANIO USINT ●
4672 + RxByte1_CANIO
9…13 USINT ●
Index RxByte[2…5]_CANIO

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4.16.5.10.4 Variable assignment in Automation Studio (CANIO)

Name Data type Read Write

Cyclic Acyclic Cyclic Acyclic
Basic functions
PositionHW UDINT ●
PositionLW UDINT ●
PosCycle SINT ●
EnDat - Read additional information
EnDatInfoOK01
USINT ●
EnDatInfoOK[02…04]
EnDatInfo01 UINT
●
EnDatInfo[02…04] INT
Error management
EnDatError UINT ●
EnDatWarning UINT ●
EnDatAck USINT ●
ErrorInfo USINT
→ EncoderSupplyError BOOL
→ VssCheckError BOOL
→ SinCosPosError BOOL
●
→ EnDatComError BOOL
→ EnDatPosError BOOL
→ EnDatParSetError BOOL
→ EnDatRefWarning BOOL
AckErrorInfo USINT
→ AckEncoderSupplyError BOOL
→ AckVssCheckError BOOL
→ AckSinCosPosError BOOL
●
→ AckEnDatComError BOOL
→ AckEnDatPosError BOOL
→ AckEnDatParSetError BOOL
→ AckEnDatRefWarning BOOL
Flatstream mode
InputSequence USINT ●
RxByte1
USINT ●
RxByte[2…5]
OutputSequence USINT ●
TxByte1
USINT ●
TxByte[2…5]

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4.16.5.10.5 Module configuration

The following configuration register can be used to configure different module settings. For example, the behavior
on the X2X bus can be modified this way. The user can choose between two option registers.

4.16.5.10.5.1 Data query

Names (pChannelName):
CfO_SIframeGenID
This register can be used to define when the synchronous/cyclic input data will be generated. X2X cycle optimized
should be set for jitter-free data acquisition or minimal latency for the best performance.
Data type Values
USINT 09 ... Minimal latency
14 ... X2X cycle optimized

4.16.5.10.5.2 Prescaler

Names (pChannelName):
CfO_SystemCyclePrescaler
In order for the module to communicate with the CPU as well as the EnDat encoder, the EnDat cycle time must be
at least twice the module cycle time. The actual EnDat cycle time is a result of multiplying the module cycle time
by the value in the register "CfO_SystemCyclePrescaler".
Data type Values
UINT 2 ... EnDat cycle: 200 to 400 μs
4 ... EnDat cycle: 400 to 800 μs
8 ... EnDat cycle: 800 to 1600
Bus controller default: 2

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4.16.5.10.6 Basic functions

This module can import a position when used together with an EnDat encoder. The received data is prepared in
two different formats and given a time stamp. Six registers are available for post-processing. This allows the user
to select the format that best fits the application at hand.

4.16.5.10.6.1 SDCLifeCount

Names (pChannelName):
SDCLifeCount
The 8-bit counter register is needed for the SDC software package. It is incremented with the system clock to allow
the SDC to check the validity of the data frame.
Data type Values
SINT -128...127

4.16.5.10.6.2 Position (64 bit)

Names (pChannelName):
PositionHW
PositionHW_64 / PositionHW_64_CANIO
PositionLW
PositionLW_64 / PositionLW_64_CANIO
The absolute position of the encoder is defined in 64 bit resolution. The position value is placed in the registers
PositionHW and PositionLW. The upper 32 bits are in the PositionHW register and the lower 32 bits in the Posi-
tionLW register.
Data type Values
2x UDINT 0...4294967295

4.16.5.10.6.3 Position (32 bit)

Names (pChannelName):
Position
Position_32
The SDC library requires a signed 32-bit position value. The position's Low Word can be addressed separately for
this. However, the value can also be used as default position value.
Data type Values
DINT -2147483648...2147483647

4.16.5.10.6.4 PosTime (32 bit)

Names (pChannelName):
PosTime
PosTime_32
In this register, each position determined is assigned to the current NetTime value. The NetTime is recorded with
µs precision.
Data type Values [NetTime]
DINT -2147483648...2147483647

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4.16.5.10.6.5 PosTime (16 bit)

Names (pChannelName):
PosTime
PosTime_16
The SDC library requires a 16 bit value. This is why the NetTime value is prepared in 16 bit format.
Data type Values [NetTime]
INT -32768...32767

4.16.5.10.6.6 PosCycle

Names (pChannelName):
PosCycle
PosCycle_8 / PosCycle_8_CANIO
PosCycle is an integer counter that is incremented as soon as the module has saved a new valid position value.
Data type Values
SINT -128...127

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4.16.5.10.7 Error management

The module can also provide diagnostics about error states. There are two ways in which this is done:
• Module-based diagnostics
• EnDat-based diagnostics

4.16.5.10.7.1 Module-based diagnostics

The module diagnoses seven different errors or warnings. Depending on the settings, the error bits can be called
either individually or packed together.

Error registers

Names (pChannelName):
ErrorEnableID_1710
ErrorInfo / ErrorInfo_CANIO
AckErrorInfo / AckErrorInfo_CANIO
Names of the individual bits (pChannelName):
EncoderSupplyError
VssCheckError
PositionError
EnDatComError
EnDatPosError
EnDatParSetError
EnDatRefWarning
AckEncoderSupplyError
AckVssCheckError
AckPositionError
AckEnDatComError
AckEnDatPosError
AckEnDatParSetError
AckEnDatRefWarning
Three independent registers are provided in accordance with B&R's approach to error management.
Data type Values
3x USINT See bit structure

The implemented diagnostics algorithms can be activated or deactivated in the Enable byte.
Bit structure of "ErrorEnableID_1710":
Bit Name Information
0 Encoder supply 0 Error detection disabled
1 Error detection enabled (Bus Controller default setting)
1 Reserved -
2 Vss Sin/Cos 0 Error detection disabled
1 Error detection enabled (Bus Controller default setting)
3 Position Error 0 Error detection disabled
1 Error detection enabled (Bus Controller default setting)
4 EnDat - Communication 0 Error detection disabled
1 Error detection enabled (Bus Controller default setting)
5 EnDat - Position 0 Error detection disabled
1 Error detection enabled (Bus Controller default setting)
6 EnDat - Parameter 0 Error detection disabled
1 Error detection enabled (Bus Controller default setting)
7 EnDat - Reference warning 0 Warning disabled
1 Warning enabled (Bus Controller default setting)

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The State byte indicates which error or warning is currently pending.

Bit structure of "ErrorInfo":
Bit Name Information
0 EncoderSupplyError 0 Error not present
1 Encoder supply error
1 Reserved -
2 VssCheckError 0 Error not present
1 Vss error Sin/Cos track
3 PositionError 0 Error not present
1 Position Error
4 EnDatComError 0 Error not present
1 EnDat communication error
5 EnDatPosError 0 Error detection disabled
1 Error detection enabled
6 EnDatParSetError 0 Error detection disabled
1 Error detection enabled
7 EnDatRefWarning 0 Warning disabled
1 Warning enabled

The Quit byte is used to acknowledge a pending error message.

Bit structure of "AckErrorInfo":
Bit Name Information
0 AckEncoderSupplyError 0 No error acknowledgment
1 Error acknowledgment
1 Reserved -
2 AckVssCheckError 0 No error acknowledgment
1 Error acknowledgment
3 AckPositionError 0 No error acknowledgment
1 Error acknowledgment
4 AckEnDatComError 0 No error acknowledgment
1 Error acknowledgment
5 AckEnDatPosError 0 No error acknowledgment
1 Error acknowledgment
6 AckEnDatParSetError 0 No error acknowledgment
1 Error acknowledgment
7 AckEnDatRefWarning 0 No acknowledgment
1 Confirmation

Encoder supply:
Encoder supply voltage below permitted limit

Vss Sin/Cos:
Voltage value for Sin/Cos-Spur violates configured limit values
→ see the register SinCosVssMin or SinCosVssMax

Position error:
The determined position value violates requirements of the application

EnDat – Communication:
Communication error on the EnDat interface (e.g. incorrect checksum)

EnDat – Position:
Encoder evaluates determined position value as invalid

EnDat – Parameter:
Inconsistent register values for encoder identification
→ Counter-measures: Check wiring or rescan (see EnDatAck)

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EnDat – Reference warning:

The digital interface provides an absolute position value that can be used to accurately describe the axis position.
The position value is homed to this absolute value at the beginning of a measurement. The analog interface can
be used to incrementally record changes that happen at a very rapid pace. This enables the module to continue
sampling the position value in high resolution. Both the analog and the digital signals are imported cyclically. If the
value determined incrementally deviates from the absolute value during operation then the referencing warning is
displayed and the position must be referenced again.

4.16.5.10.7.2 EnDat-based diagnostics

Memory areas are provided in the EnDat standard for error handling. Error management was tailored to utilize
error detection according to the EnDat standard. Three additional registers were implemented in the module which
prepare these areas in the encoder memory.
The module allows access to all previously defined memory areas for error handling. The memory areas are mir-
rored in the module registers and can be interpreted by the user.
Please refer to the encoder's manual for detailed information regarding the errors that can be detected this way.

EnDatError

Names (pChannelName):
EnDatError
This register is used to indicate critical conditions on the EnDat encoder. The system has generally ceased to work
and requires service.
Data type Values
UINT See bit structure

The bit structure described below is designed according to the general recommendations of the EnDat standard.
The specification does not limit which trigger algorithms to use or which of the listed messages must be supported.
Please refer to the encoder's manual for further details.
Bit structure:
Bit Name Information
0 Lighting 0 ok
1 Failed
1 Signal amplitude 0 ok
1 Error
2 Position value 0 ok
1 Error
3 Overvoltage 0 No
1 Yes
4 Undervoltage 0 No
1 Yes
5 Overcurrent 0 No
1 Yes
6 Battery 0 ok
1 Must be changed
7-15 Reserved -

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EnDatWarning

Names (pChannelName):
EnDatWarning
This register is used to indicate critical conditions on the EnDat encoder. Encoder still functional, but must be
checked immediately. This generally means that defined tolerances have been exceeded.
Data type Values
UINT See bit structure

The bit structure described below is designed according to the general recommendations of the EnDat standard.
The specification does not limit which trigger algorithms to use or which of the listed messages must be supported.
Please refer to the encoder's manual for further details.
Bit structure:
Bit Name Information
0 Frequency collision 0 No
1 Yes
1 Temperature exceeded 0 No
1 Yes
2 Control reserve - Lighting 0 Not required
1 Mandatory
3 Charge - Battery 0 ok
1 Low
4 Reference point 0 Reached
1 Not reached
5-15 Reserved -

EnDatAck

Names (pChannelName):
EnDatAck
The "EnDatAck" acknowledges all errors and warnings from the registers "EnDatError" and "EnDatWarning". It can
also instruct the module to re-import the parameters for identification.
Data type Values
USINT See bit structure

If one of the bits in this register is set, the system automatically resets it and the respective algorithm is run.
Bit structure:
Bit Name Information
0 EnDatError/EnDatWarning 0 No acknowledgment
1 Acknowledged
1 Rescan - Identification register 0 Imported parameters retained
1 Re-import parameters
2-7 Reserved -

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4.16.5.10.8 Sin/Cos - Analog interface configuration

In addition to the digital EnDat, the module is also equipped with an analog interface for recording a differential
sine-cosine signal. To increase the resolution, the EnDat standard specifies a cooperation between the analog and
digital information. This enables highly dynamic display of the position while maintaining high resolution.

4.16.5.10.8.1 SinCosEnable

Names (pChannelName):
SinCosEnable
This register must always have the value 1 for configuration reasons.
Data type Values
USINT 1!
Bus controller default setting: 1

4.16.5.10.8.2 SinCosRefSource

Names (pChannelName):
SinCosRefSource
This register must always have the value 1 for configuration reasons.
Data type Values
USINT 1!
Bus controller default setting: 1

4.16.5.10.8.3 SinCosVssMin

Names (pChannelName):
SinCosVssMin
The SinCosVssMin register specifies the lower limit value for the peak-peak voltage of the sine/cosine track. This
ensures that the pending signal is monitored. If the incoming value falls below this specified limit, then the module
reports the corresponding error.
Data type Values [mV]
UINT 0...1500
Bus controller default setting: 800

4.16.5.10.8.4 SinCosVssMax

Names (pChannelName):
SinCosVssMax
The SinCosVssMax register specifies the upper limit value for the peak-peak voltage of the sine/cosine track. This
ensures that the pending signal is monitored. If the incoming value exceeds this specified limit, then the module
reports the corresponding error.
Data type Values [mV]
UINT 0...1500
Bus controller default setting: 1200

4.16.5.10.8.5 SinCosQuitTime

Names (pChannelName):
SinCosQuitTime
If an error is detected on the analog interface, the latest correctly determined values remain valid. A time span
can be defined here in which the module begins receiving correct values again after the error state without post-
processing them internally. Only then will newly imported correct analog values be recognized as valid.
Data type Values [µs]
UDINT 0...20000000
Bus controller default setting: 100000

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4.16.5.10.9 EnDat

4.16.5.10.9.1 EnDat - Digital interface configuration

The EnDat interface allows you to establish a point-to-point connection with exactly one EnDat encoder.
There are two ways to use the encoder data in the PLC program. The important encoder values can be buffered in
the module before being made available on the CPU or the module's Flatstream mode can be used, which supports
the full command range in accordance with the EnDat specification.
Detailed information about the EnDat specification can be found in the document, "Technical Information – EnDat
2.2".

EnDatMode

Names (pChannelName):
EnDatMode
A variety of module properties are pre-defined in the "EnDatMode" register.
Data type Values
USINT See bit structure

Bit structure:
Bit Name Information
0 EnDat interface 0 Disabled
1 Enabled (bus controller default setting)
1 Format of imported position data 0 Unsigned (bus controller default setting)
1 Signed
2 Fast EnDat cycle (6 MHz) 0 Enabled if encoder compatible (bus controller default setting)
1 Disabled
3 Sin/Cos track 0 Enabled (bus controller default setting)
1 Disabled
4-7 Reserved -

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4.16.5.10.9.2 EnDat - Read ID

The EnDat interface does more than just help the user specify axis positions. It can also be used to readout certain
data stored in the encoder memory.
The EnDat specification divides the encoder memory into logical groups. These include memory areas for the op-
erating parameters, operating status, manufacturer parameters, and manufacturer parameters according to EnDat
2.2.
The four most important memory areas are mirrored in the module registers. The information can be accessed in
the application and used to identify a particular encoder.

Information:
There are different types of EnDat. Please keep this in mind. EnDat has been continuously expanded to
include new technical possibilities while maintaining backward compatibility. Several advancements
have been made to the standard, which has resulted in a non-uniform structure.
In general, data is queried from memory for identification purposes when the module is started. Additionally, the
data can be re-imported using the "EnDatAck" register (see Error management section). The module reads the
data from the encoder, which is then mapped for the PLC.

Operating Parameters

Names (pChannelName):
OperatingParam_00
OperatingParam_[01…15]
These registers can be used to read out the current operating parameters. The data in these registers correspond
exactly to the values on the encoder. More detailed information can be found in the encoder's manual or by referring
to the latest EnDat specification.
Data type Values
16x UINT See encoder manual

Operating status

Names (pChannelName):
OperatingStatus_00
OperatingStatus_[01…03]
This register can be used to read the encoder's current operating state. The first two registers from this group
are identical to the registers "EnDatError" and "EnDatWarning". A special setting is provided because they are
update cyclically.
Information about write protection and other configuration settings is managed in registers 02 and 03. The data in
these registers correspond exactly to the values on the encoder.
More detailed information can be found in the encoder's manual or by referring to the latest EnDat specification.
Data type Values
4x UINT See encoder manual

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Manufacturer parameters

Names (pChannelName):
ParamManuf_04
ParamManuf_[05…47]
These registers are used to prepare the manufacturer parameters according to the EnDat standard 2.1. The exact
arrangement of information can be found in the documentation "Technical Information - EnDat 2.2".
Data type Values
44x UINT see "Technical Information - EnDat 2.2" or encoder manufacturer data

Additional manufacturer parameters according to EnDat 2.2

Names (pChannelName):
ParamManufEnDat22_00
ParamManufEnDat22_[01…63]
These registers are used to prepare the manufacturer parameters according to the EnDat standard 2.2. The exact
arrangement of information can be found in the documentation "Technical Information - EnDat 2.2".
Data type Values
64x UINT see "Technical Information - EnDat 2.2" or encoder manufacturer data

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4.16.5.10.9.3 EnDat - Read additional information

In addition to the identification data, other information can also be accessed from the encoder. However, the fol-
lowing algorithm requires exact knowledge of the encoder's memory structure and the EnDat specification.

Configuration
There are four different channels that can be operated during a cycle. One register per channel each is used for
configuration, (i.e. determines which data is read from the encoder and mirrored on the respective Info byte).

EnDatInfoCmd

Names (pChannelName):
EnDatInfoCmd01
EnDatInfoCmd[02…04]
The "EnDatInfoCmd" register controls which data is processed on the corresponding Info byte for each channel.
The register consists of up to four separate 8-bit values.
Data type Values
4x UDINT see bit structure
Bus controller default setting: 0

Bit structure:
Bit Name Information
00-07 Command Selects the response section
08-15 Memory area code MRS code
Parameters not in blocks Parameters arranged in blocks
16-23 Memory ID Parameter number Block number
24-31 Memory ID - Parameter number

There is a difference when querying data from an encoder using an EnDat 2.1 command or an EnDat 2.2 command.
When querying encoder data with an EnDat 2.1 command (0x04 and 0x06) the parameter number and (optionally)
the block number must be specified in addition to the MRS code.
When querying the memory with an EnDat 2.2 command, the parameter number and block number are not required.
The module consecutively sends all four words of the memory area, which was selected using the MRS code. The
right command must be selected depending on which of the four response bytes is needed.

Memory area code:

The code to be defined is identical to the MRS code for the encoder memory. The EnDat specification has left
a few of the encoders memory areas undefined and available for future developments. This is why a clear and
reliable explanation cannot be provided here.
More detailed information can be found in the encoder's manual or by referring to the latest EnDat specification.

Parameter number:
EnDat 2.1 requires the corresponding parameter number to be entered in order to specifically address the desired
parameter in the encoder memory. Older EnDat versions did not divide the encoder memory into blocks. This is
why there are memory areas that can be selected without specifying a block number. In this case, the parameter
number must be entered on the third byte.
More detailed information can be found in the encoder's manual or by referring to the latest EnDat specification.

Block number:
To expand the address range of the encoder memory, additional block numbers were added starting at the second
section. If the desired parameter is located in this blocked area, then the block number must be specified on the
third byte. In this case, the parameter number is indicated on the fourth byte.
More detailed information can be found in the encoder's manual or the latest EnDat specification.

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Call
After proper configuration, the position value is transferred cyclically to the module. Two registers are available per
channel as a buffer. The module confirms successful receipt by setting an OK bit. The EnDat specification does not
specify in which format the parameters must be received. Therefore, the module provides the information in two
ways. Which of the two registers should be used for further processing depends on the parameters being read.

EnDatInfoOKByte

Names (pChannelName):
EnDatInfoOK01
EnDatInfoOK[02…04]
This register's bits provide information about the validity of the latest Info data in the buffer.
Data type Values
USINT See bit structure

Bit structure:
Bit Name Information
0 EnDatInfoOK01 0 Value 01 invalid
1 Value 01 valid
1 EnDatInfoOK02 0 Value 02 invalid
1 Value 02 valid
2 EnDatInfoOK03 0 Value 03 invalid
1 Value 03 valid
3 EnDatInfoOK04 0 Value 04 invalid
1 Value 04 valid
4-7 Reserved -

EnDatInfo (unsigned)

Names (pChannelName):
EnDatInfo01_u16
EnDatInfo[02…04]_u16
The registers provide the corresponding requested information as an unsigned 2 byte value.
Data type Values
UINT 0...65535

EnDatInfo (signed)

Names (pChannelName):
EnDatInfo01_s16
EnDatInfo[02…04]_s16
The registers provide the corresponding requested information as a signed 2 byte value.
Data type Values
INT -32768...32767

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4.16.5.10.10 FlatStream communication

4.16.5.10.10.1 Introduction

B&R offers an additional communication method for some modules. "FlatStream" was designed for X2X and
POWERLINK networks and allows data transfer adapted to individual demands. Although this method is not 100%
real-time capable, it still allows data transfer to be handled more efficiently than with standard cyclic polling.
Field device
X2X language

Cyclic call
via I/O mapping

B&R CPU
Cyclic call B&R module Cyclic
PLC or B&R field device
of cached values cached value communication
Bus controller

Acyclic call
via
library functions
B&R CPU
Acyclic call B&R module Cyclic
PLC or B&R field device
of cached values cached value communication
Bus controller

FlatStream

B&R CPU X2X-compatible B&R module

PLC or Device command B&R field device
device command as a bridge
Bus controller

Figure 434: Three types of communication

FlatStream extends cyclic and acyclic data queries. With FlatStream communication, the module acts as a bridge.
It is used to pass CPU queries directly on to the field device.

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4.16.5.10.10.2 Message, segment, sequence, MTU

The physical properties of the bus system limit the amount of data that can be transferred during one bus cycle.
With FlatStream communication, all messages are viewed as part of a continuous data stream. Long data streams
must be broken down into several fragments that are sent one after the other. To understand how the receiver puts
these fragments back together to get the original information, it is important to understand the difference between
a message, a segment, a sequence and the MTU.
Message:
A message refers to information exchanged between two partner stations. The length of a message is not restricted
by the FlatStream communication method. Nevertheless, module-specific limitations must be considered.
Segment (logical division of a message):
A segment has a finite size and can be understood as a section of a message. The number of segments per
message is arbitrary. So that the recipient can correctly reassemble the transferred segments, each segment
is preceded by a byte with additional information. This control byte contains information such as the length of
a segment and whether the approaching segment completes message. This makes it possible for the receiving
station to interpret the incoming data stream correctly.
Sequence (how a segment needs to be arranged physically):
The size of a sequence corresponds exactly to the number of activated Rx or Tx bytes (later: "MTU"). The trans-
mitting station splits the transmit array into valid sequences. These sequences are then written successively to
the MTU and transferred to the receiving station where they are put back together again. The receiver stores the
incoming sequences in a receive array, obtaining an image of the data stream in the process.
With FlatStream communication, the number of sequences sent are counted. Sequences transferred successfully
must be acknowledged by the receiving station to ensure the integrity of the transmission.
MTU (Maximum Transmission Unit) - Physical transport:
MTU refers to the activated USINT registers used with FlatStream. These registers can accept a sequence and
pass it on to the receiving station. A separate MTU is defined for each direction of communication. The OutputMTU
defines the number of FlatStream Tx bytes, and the InputMTU specifies the number of FlatStream Rx bytes. The
MTUs are transported cyclically via the X2X bus, increasing the load with each additional activated USINT register.
Properties:
FlatStream messages are not transferred cyclically or in 100% real time. Many bus cycles may be needed to trans-
fer a certain message. Although the Rx and Tx registers are exchanged between the transmitter and the receiv-
er cyclically, they are only processed further if explicitly accepted by the "InputSequence" or "OutputSequence"
register.
Behavior in the event of an error (brief summary):
The protocol for X2X and POWERLINK networks specifies that the last valid values should be retained when
disturbances occur. With conventional communication (cyclic/acyclic data queries), this type of error can generally
be ignored.
In order for communication to also take place without errors using FlatStream, all of the sequences issued by the
receiver must be acknowledged. If "Forward" functionality is not used, then subsequent communication is delayed
for the length of the disturbance.
If "Forward" functionality is being used, the receiving station receives a transmission counter that is incremented
twice. The receiver stops, i.e. it no longer returns any acknowledgments. The transmitting station uses the Se-
quenceAck to determine that the transmission was faulty and all affected sequences will have to be repeated.

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4.16.5.10.10.3 The FlatStream principle

Requirement:
Before FlatStream can be used, the respective communication direction must be synchronized, i.e. both commu-
nication partners cyclically query the sequence counter on the opposite station. This checks to see if there is new
data that should be accepted.
Communication:
If a communication partner wants to transmit a message to its opposite station, it should first create a transmit
array that corresponds to FlatStream conventions. This allows the FlatStream data to be organized very efficiently
without having to block other important resources.
PLC / Bus controller Module
Module-internal Module-internal
Transmit array OutputMTU receive buffer receive array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 TxBytes Cyc. *RxBytes _data_01

_data_02 _data_02
When OutputMTU The transmit buffer If the OutputSequence
_data_03 released: of the module is counter is increased: _data_03
adjusted cyclically to
_data_04 CPU fills OutputMTU via X2X Module adds the transmit buffer _data_04
OutputMTU to the internal array
_data_05 with the next
_data_05
... sequence of the If successful: ...
transmit array InputSequenceAck is
_data_xx adjusted to the _data_xx
transmit counter

Module-internal Module-internal
Receive array InputMTU transmit buffer transmit array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 RxBytes Cyc. *TxBytes _data_01

_data_02 _data_02
If the InputMTU is If permitted:
_data_03 InputSequence adjusted cyclically Module fills the internal _data_03
counter is increased: to the receive transmit buffer with the
_data_04 buffer via X2X next sequence of the _data_04
_data_05 InputMTU must be transmit array _data_05
added to the end
... of the receive array Module increases the ...
(increase InputSequenceAck InputSequence counter
_data_xx to end properly) _data_xx

Figure 435: FlatStream communication

Approach:
The first thing that happens is that the message is broken into valid segments of up to 63 bytes, and the corre-
sponding control bytes are created. The data is added to a data stream, alternating control bytes followed by their
corresponding segments This data stream can be written to the transmit array. The maximum size of each array
element matches that of the enabled MTU so that one element corresponds to one sequence.
When the array has been completely created, the transmitter checks whether the MTU is allowed to be refilled.
Then it copies the first element of the array or the first sequence to the Tx byte registers. The MTU is transported
to the receiver station via the X2X bus and stored in the corresponding Rx byte registers. To signal that the data
should be accepted by the receiver, the transmitter increases its SequenceCounter.
If the communication direction is synchronized, the opposite station detects the incremented SequenceCounter.
The current sequence is appended to the receive array and acknowledged by SequenceAck. This acknowledgment
signals to the transmitter that the MTU can now be refilled.
If the transmission is successful, the data in the receive array will correspond 100% to the data in the transmit array.
During the transfer, the receiving station must detect and evaluate the incoming control bytes. A separate receive
array should be created for every message. This allows the receiver to immediately begin further processing of
messages once they have been completely transferred.

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4.16.5.10.10.4 Registers for FlatStream mode

Five registers are available for configuring FlatStream. The default configuration can be used to transmit small
amounts of data relatively easily.

Information:
The CPU communicates directly with the field device via the OutputSequence/InputSequence registers
and the enabled Tx / Rx bytes. For this reason, the user needs to have sufficient knowledge of the
communication protocol being used on the field device.

FlatStream configuration

To use FlatStream, the program sequence must first be expanded. The cycle time of the FlatStream routines must
be set to a multiple of the bus cycle. Other program routines should be implemented in Cyclic #1 to ensure data
consistency.
At the absolute minimum, the "InputMTU" and "OutputMTU" registers need to be configured. All other registers are
filled in with default values at the beginning and can be used immediately. These registers are used for additional
options, e.g. to transmit data in a more compact way or to increase the efficiency of the general procedure.
The Forward registers extend the functionality of the FlatStream protocol. This functionality is useful for substan-
tially increasing the FlatStream data rate, but it also requires quite a bit of extra work when creating the program
sequence.

OutputMTU, InputMTU
These registers define the number of enabled Tx or Rx bytes, i.e. the maximum size of a sequence. The user must
consider that the more bytes made available also means a higher load on the bus system.

Information:
In the rest of this documentation, the names "OutputMTU" and "InputMTU" do not refer to the registers
explained here. Instead, they are used as synonyms for the currently enabled Tx or Rx bytes.
Data type Value
USINT See the module-specific register overview (theoretically: 3 - 27)

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FlatStream operation

When using FlatStream, the communication direction is enormously important. For sending data to a module ("out-
put" direction), the Tx bytes are used. For receiving data from a module ("input" direction"), the Rx bytes are used.
The "OutputSequence" and "InputSequence" registers are used to control and ensure that communication is taking
place properly, i.e. the transmitter issues the directive that the data should be accepted and the receiver acknowl-
edges that a sequence has been transferred successfully.
Tx-/Rx-Bytes:
The Tx and Rx bytes are cyclic registers used to transport the payload data and the necessary control bytes.
The number of active Tx/Rx bytes is taken from the configuration of the "OutputMTU" and "InputMTU" registers,
respectively.
In the user's program, only the Tx/Rx bytes from the CPU can be used. The corresponding counterparts are located
in the module and are not accessible to the user. For this reason, names were chosen from the CPU point of view.
• "T" - "Transmit" → CPU transmits data to the module
• "R" - "Receive" → CPU receives data from the module
Data type Values
USINT 0...65535

Control bytes:
In addition to the payload data, the Tx and Rx bytes also transfer the necessary control bytes. These control bytes
contain additional information about the data stream so that the receiver can reconstruct the original message from
the transferred segments.
Bit structure of a control byte:
Bit Name Information
0-5 SegmentLength 0-63 Size in bytes of the following segment (default: max. MTUSize
- 1)
6 nextCBPos 0 Next control byte at the beginning of the next MTU
1 Next control byte directly at the end of this segment
7 MessageEndBit 0 Message continues after the subsequent segment
1 Message ends after the subsequent segment

Segment length:
The segment length lets the receiver know the length of the coming segment. If the configured segment length
is insufficient for a message, then the information must be distributed over several segments. In these cases, the
actual end of the message is detected using bit 7 of the control byte.

Information:
The control byte is not included in the calculation to determine the segment length. The segment length
is only derived from the bytes of payload data.
nextCBPos:
This bit indicates the position where the next control byte is to be expected. This information is especially important
when using the "MultiSegmentMTU" option.
When using FlatStream communication with multi-segment MTUs, the next control byte is no longer expected in
the first Rx byte of the subsequent MTU, but directly after the current segment.
MessageEndBit:
The "MessageEndBit" is set if the subsequent segment completes a message. The message is then completely
transferred and can be processed further.

Information:
In the output direction, this bit must also be set if one individual segment is enough to take on the
entire message. The module will only process a message internally if this identifying mark is detected.
The size of the message being transferred can be calculated by adding all of the message's segment
lengths together.
FlatStream formula for calculating message length:
Message [bytes] = SegmentLengths (all CBs without ME) + SegmentLength (of the first CB with CB Control byte
ME) ME MessageEndBit

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OutputSequence
The "OutputSequence" register contains information about the communication status of the CPU. It is written by
the CPU and read by the module.
Data type Values
USINT See bit structure

Bit structure:
Bit Name Information
0-2 OutputSequenceCounter 0-7 Counter for the sequences issued in the output direction
3 OutputSyncBit 0 Output direction disabled
1 Output direction enabled
4-6 InputSequenceAck 0-7 Mirrors the InputSequenceCounter value
7 InputSyncAck 0 Input direction not ready (disabled)
1 Input direction ready (enabled)

OutputSequenceCounter:
The OutputSequenceCounter is a continuous counter of sequences that have been issued by the CPU. The CPU
uses the OutputSequenceCounter to direct the module to accept a sequence (the output direction must be syn-
chronized when this happens).
OutputSyncBit:
The CPU uses the OutputSyncBit to try and synchronize the output channel.
InputSequenceAck:
InputSequenceAck is used for acknowledgment. The value of the InputSequenceCounter is mirrored if the CPU
has received a sequence successfully.
InputSyncAck:
The InputSyncAck bit acknowledges the synchronization of the input channel for the module. This indicates that
the CPU is ready to receive data.

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InputSequence
The "InputSequence" register contains information about the communication status of the module. It is written by
the module and should only be read by the CPU.
Data type Values
USINT See bit structure

Bit structure:
Bit Name Information
0-2 InputSequenceCounter 0-7 Counter for the sequences issued in the input direction
3 InputSyncBit 0 Not ready (disabled)
1 Ready (enabled)
4-6 OutputSequenceAck 0-7 Mirrors the OutputSequenceCounter value
7 OutputSyncAck 0 Not ready (disabled)
1 Ready (enabled)

InputSequenceCounter:
The InputSequenceCounter is a continuous counter of sequences that have been issued by the module. The
module uses the InputSequenceCounter to direct the CPU to accept a sequence (the input direction must be
synchronized when this happens).
InputSyncBit:
The module uses the InputSyncBit to try and synchronize the input channel.
OutputSequenceAck:
OutputSequenceAck is used for acknowledgment. The value of the OutputSequenceCounter is mirrored if the
module has received a sequence successfully.
OutputSyncAck:
The OutputSyncAck bit acknowledges the synchronization of the output channel for the CPU. This indicates that
the module is ready to receive data.

Relationship between OutputSequence and InputSequence

Outputsequenz Input sequence

CPU communication status Module communication status

0-2 OutputSequenceCounter 0-2 InputSequenceCounter

3 OutputSyncBit Intersecting 3 InputSyncBit

4-6 InputSequenceAck Handshakes 4-6 OutputSequenceAck

7 InputSyncAck 7 OutputSyncAck

Figure 436: Relationship between OutputSequence and InputSequence

The OutputSequence and InputSequence registers are logically composed of two half-bytes. The low part signals
to the opposite station whether a channel should be opened or if data should be accepted. The high part is to
acknowledge that the requested action was carried out.
SyncBit und SyncAck:
If SyncBit and SyncAck are set in one communication direction, then the channel is considered "synchronized", i.e.
it is possible to send messages in this direction. The status bit of the opposite station must be checked cyclically.
If SyncAck has been reset, then the SyncBit must be adjusted on that station. Before new data can be transferred,
the channel needs to be resynchronized.
SequenceCounter und SequenceAck:
The communication partners cyclically check whether the low nibble on the opposite station changes. When one
of the communication partners finishes writing a new sequence to the MTU, it increments its SequenceCounter.
The current sequence is then transferred to the receiver, who acknowledges its receipt with SequenceAck. In this
way, a "handshake" is initiated.

Information:
If communication is interrupted, segments from the unfinished message transfer are discarded. All
messages that were transferred completely are processed.

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Synchronization

During synchronization, a communication channel is opened. It is important to make sure that a module is present
and that the current value of the SequenceCounter is stored on the station receiving the message.
FlatStream can handle full-duplex communication. This means that both channels / communication directions can
be handled separately. They have to be synchronized independently so that simplex communication can theoret-
ically be carried out as well.

Synchronization in the output direction (CPU as the transmitter):

The corresponding synchronization bits (OutputSyncBit and OutputSyncAck) are reset. Because of this, FlatStream
cannot be used at this point in time to send messages from the CPU to the module.
Algorithm:
1.) The CPU must write 000 to the OutputSequenceCounter and reset the OutputSyncBit.
The CPU must cyclically query the high nibble of the "InputSequence" register (checks for 000 in OutputSequenceAck and 0 in OutputSyncAck).
The module does not accept the current contents of the InputMTU since the channel is not yet synchronized.
The module matches OutputSequenceAck and OutputSyncAck to the values of the OutputSequenceCounter and OutputSyncBit.
2.) If the CPU registers the expected values in OutputSequenceAck and OutputSyncAck, it is allowed to increment the OutputSequenceCounter.
The CPU continues cyclically querying the high nibble of the "OutputSequence" register (checks for 001 in OutputSequenceAck and 0 in InputSyncAck).
The module does not accept the current contents of the InputMTU since the channel is not yet synchronized.
The module matches OutputSequenceAck and OutputSyncAck to the values of the OutputSequenceCounter and OutputSyncBit.
3.) When the CPU registers the expected values in OutputSequenceAck and OutputSyncAck, it is allowed to increment the OutputSequenceCounter.
The CPU continues cyclically querying the high nibble of the "OutputSequence" register (checks for 001 in OutputSequenceAck and 1 in InputSyncAck).
Note:
Theoretically, data can be transmitted from this point forward. However, it is still recommended to wait until the output direction is completely synchronized be-
fore transmitting data.
The module sets OutputSyncAck.
The output direction is synchronized, and the CPU can transmit data to the module.

Synchronization in the input direction (CPU as the receiver):

The corresponding synchronization bits (InputSyncBit and InputSyncAck) are reset. Because of this, FlatStream
cannot be used at this point in time to send messages from the module to the CPU.
Algorithm:
The module writes 000 to the InputSequenceCounter and resets the InputSyncBit.
The module monitors the high nibble of the "OutputSequence" register and expects 000 in InputSequenceAck and 0 in InputSyncAck.
1.) The CPU is not allowed to accept the current contents of the InputMTU since the channel is not yet synchronized.
The CPU has to match InputSequenceAck and InputSyncAck to the values of InputSequenceCounter and InputSyncBit.
If the module registers the expected values in InputSequenceAck and InputSyncAck, it increments the InputSequenceCounter.
The module monitors the high nibble of the "OutputSequence" registers and expects 001 in InputSequenceAck and 0 in InputSyncAck.
2.) The CPU is not allowed to accept the current contents of the InputMTU since the channel is not yet synchronized.
The CPU has to match InputSequenceAck and InputSyncAck to the values of InputSequenceCounter and InputSyncBit.
If the module registers the expected values in InputSequenceAck and InputSyncAck, it sets the InputSyncBit.
The module monitors the high nibble of the "OutputSequence" register and expects 1 in InputSyncAck.
3.) The CPU is allowed to set InputSyncAck.
Note:
Theoretically, data can already be transmitted in this cycle.
If the InputSyncBit is set and InputSequenceCounter has been increased by 1, the values in the enabled Rx bytes have to be accepted and acknowledged (see
also "Communication in the input direction").
The input direction is synchronized, and the module can transmit data to the CPU.

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Sending and receiving

If a channel is synchronized, then the opposite station is ready to receive messages from the transmitter. Before
the transmitter can send data, it needs to first create a transmit array in order to meet FlatStream requirements.
The transmitting station must also generate a control byte for each segment created. This control byte contains
information about how the subsequent part of the data being transferred should be processed. The position of the
next control byte in the data stream can vary. For this reason, it must be absolutely clear at all time when a new
control byte is being transferred. The first control byte is always in the first byte of the first sequence. All subsequent
positions are conveyed recursively.
FlatStream formula for calculating the position of the next control byte:
Position (of the next control byte) = Current position + 1 + Segment length
Example:
Three autonomous messages (7 bytes, 2 bytes, 9 bytes) are being transferred using an MTU with a width of 7
bytes. The rest of the configuration corresponds to the default settings.

Message 1: Transmit/Receive array

With 7 USINT elements according to

the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Default
Message 2:

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

C2 A7 - - - - - Sequence for bus cycle 2

Message 3:
C3 B1 B2 - - - - Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C4 D1 D2 D3 D4 D5 D6 Sequence for bus cycle 4

No more data to transmit C5 D7 D8 D9 - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 437: Transmit/Receive array (default)

First, the messages must be split into segments. In the default configuration, it is important to ensure that each
sequence can hold an entire segment, including the associated control byte. The sequence is limited to the size of
the activated MTU. In other words, a segment must be at least 1 byte smaller than the MTU.
MTU = 7 bytes → Max. segment length = 6 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 6 data bytes

➯ Second segment = Control byte + 1 data byte
• Message 2 (2 bytes)

➯ First segment = Control byte + 2 data bytes

• Message 3 (9 bytes)

➯ First segment = Control byte + 6 data bytes

➯ Second segment = Control byte + 3 data bytes
• No more messages

➯ C0 control byte

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A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C0 (control byte 0) C1 (control byte 1) C2 (control byte 2)
- SegmentLength (0) = 0 - SegmentLength (6) = 6 - SegmentLength (1) = 1
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (0) = 0 - MessageEndBit (0) = 0 - MessageEndBit (1) = 128
Control byte Σ 0 Control byte Σ 6 Control byte Σ 129

Table 439: FlatStream determination of the control bytes for default configuration example (part 1)
C3 (control byte 3) C4 (control byte 4) C5 (control byte 5)
- SegmentLength (2) = 2 - SegmentLength (6) = 6 - SegmentLength (3) = 3
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (1) = 128 - MessageEndBit (0) = 0 - MessageEndBit (1) = 128
Control byte Σ 130 Control byte Σ 6 Control byte Σ 131

Table 440: FlatStream determination of the control bytes for default configuration example (part 2)

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Transmitting data to a module (output)

When transmitting data, the transmit array must be generated in the application program. Sequences are then
transferred one by one using FlatStream and received by the module.

Information:
Although all B&R modules with FlatStream communication always support the most compact trans-
missions in the output direction, it is recommended to use the same design for the transfer arrays in
both communication directions.

PLC / Bus controller Module

Module-internal Module-internal
Transmit array OutputMTU receive buffer receive array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 TxBytes Cyc. *RxBytes _data_01

_data_02 _data_02
When OutputMTU The transmit buffer If the OutputSequence
_data_03 released: of the module is counter is increased: _data_03
adjusted cyclically to
_data_04 CPU fills OutputMTU via X2X Module adds the transmit buffer _data_04
OutputMTU with to the internal array
_data_05 the next sequence
_data_05
... of the transmit array If successful: ...
InputSequenceAck is
_data_xx adjusted to the _data_xx
transmit counter

Figure 438: FlatStream communication (output)

The length of the message is initially smaller than the OutputMTU. In this case, one sequence would be sufficient
to transfer the entire message and the necessary control byte.
Algorithm:
Cyclic status query:
- Module monitors OutputSequenceCounter
0. Cyclic checks:
- The CPU must check OutputSyncAck
→ If OutputSyncAck = 0: reset OutputSyncBit and resynchronize channel
- The CPU must check whether OutputMTU enabled
→ If OutputSequenceCounter > InputSequenceAck: MTU not enabled since last sequence not yet acknowledged
1. Preparation (create transmit array):
- The CPU must split up message into valid segments and create the necessary control bytes
- The CPU must add the segments and control bytes to the transmit array
2. Transmission:
- The CPU transfers the current element of the transmit array to the OutputMTU
→ OutputMTU is transferred cyclically to the module's transmit buffer but not processed further
- The CPU must increase OutputSequenceCounter
Response:
- The module accepts the bytes from the internal receive buffer and adds them to the internal receive array
- The module sends acknowledgment, writes the value of OutputSequenceCounter to OutputSequenceAck
3. Completion:
- The CPU must monitor OutputSequenceAck
→ A sequence is only considered to have been transferred successfully if it has been acknowledged via OutputSequenceAck. In order to detect potential trans-
fer errors in the last sequence as well, it's important to make sure that the length of the completion phase is sufficient.
Note:
To monitor communication times exactly, the task cycles that have passed since the last increase of the OutputSequenceCounter should be counted. In this
way, the number of previous bus cycles necessary for the transfer can be measured. If the monitoring counter exceeds a predefined threshold, then the se-
quence can be considered lost.
(The relationship of bus to task cycle can be influenced by the user so that the threshold value needs to be determined individually.)
- Subsequent sequences may only be sent in the next bus cycle after the completion check has been carried out successfully.

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Message larger than the OutputMTU:

The transmit array, which needs to be created in the program sequence, consists of several elements. The user
has to arrange the control and data bytes correctly and transfer the array elements one after the other. The transfer
algorithm remains the same and is repeated at the point Cyclic checks.
General flow chart:

Start

► diff = (OutputSequenceCounter -
OutputSequenceAck) AND 7
► limit = (OutputSequenceCounter -
LastValidAck) AND 7

(diff ≤ limit)
No OutputSequenceAck = No LastValidAck = Yes
AND (OutputSyncAck = 1)
AND (OutputSyncBit = 1) ? OutputSequenceCounter ? OutputSequenceCounter ?

Yes Yes No

No LastValidAck =
diff = 0 ?
OutputSequenceAck

Yes

LastValidAck = No
OutputSequenceAck = 0 ?
OutputSequenceAck

Yes

No OutputSequenceCounter = 0
More sequences to be sent ? OutputSequenceCounter = 1 OutputSyncBit = 1
LastValidAck = 0

Yes

copy next sequence to MTU

increase OutputSequenceCounter

Sequence handling Synchronisation

Figure 439: Flow chart for the output direction

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Receiving data from a module (input)

When receiving data, the transmit array is generated by the module, transferred via FlatStream and must then
be reproduced in the receive array. The structure of the incoming data stream can be configured with the mode
register. The algorithm for receiving the data does not change in this regard.
PLC / Bus controller Module
Module-internal Module-internal
Receive array InputMTU transmit buffer transmit array
Type: USINT Type: USINT Type: USINT Type: USINT

_data_01 RxBytes Cyc. *TxBytes _data_01

_data_02 _data_02
If the InputMTU is If permitted:
_data_03 InputSequence adjusted cyclically Module fills the internal _data_03
counter is increased: to the receive transmit buffer with the
_data_04 buffer via X2X next sequence of the _data_04
InputMTU must be transmit array
_data_05 added to the end
_data_05
... of the receive array Module increases the ...
(increase InputSequenceAck InputSequence counter
_data_xx to end properly) _data_xx

Figure 440: FlatStream communication (input)

Algorithm:
0. Cyclic status query:
- The CPU must monitor InputSequenceCounter
Cyclic checks:
- The module checks InputSyncAck
- The module checks InputSequenceAck
Preparation:
- The module forms the segments, creates the control bytes and transmit array
Action:
- The module transfers the current element of the internal transmit array to the internal transmit buffer
- The module increases InputSequenceCounter
1. Receiving (as soon as InputSequenceCounter is increased):
- The CPU must accept data from the InputMTU and append it to the end of the receive array
- The CPU must match InputSequenceAck to the InputSequenceCounter of the sequence currently being processed
Completion:
- The module monitors InputSequenceAck
→ A sequence is only considered to have been transferred successfully if it has been acknowledged via InputSequenceAck.
- Subsequent sequences may only be sent in the next bus cycle after the completion check has been carried out successfully.

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General flow chart:

Start

► InputSequenceAck = InputSequenceCounter

Synchronisation
No
InputSyncBit = 1 ? ► RemainingSegmentSize = 0
► SegmentFlags = 0
Yes

No No
InputSyncAck = 1 ? InputSequenceAck > 0 ?

Yes Yes

MTU_Offset = 0 InputSyncAck = 1

(InputSequenceCounter – No
InputSequenceAck)
AND 0x07 = 1 ?

Yes
► RemainingSegmentSize =
Yes MTU_Data[MTU_Offset] AND 0b0011 1111
RemainingSegmentSize = 0 ? ► SegmentFlags =
MTU_Data[MTU_Offset] AND 0b1100 0000
No ► MTU_Offset = MTU_Offset + 1

Yes RemainingSegmentSize > No

(InputMTU_Size – MTU_Offset) ?

Segment data handling

► DataSize = InputMTU_Size – MTU_Offset ► DataSize = RemainingSegmentSize

► copy segment data e.g. memcpy(xxx, ADR(MTU_Data[MTU_Offset]), DataSize)

► MTU_Offset = MTU_Offset + DataSize
► RemainingSegmentSize = RemainingSegmentSize - DataSize

RemainingSegmentSize = 0 AND Yes

► Mark Frame as complete
(SegmentFlags AND 0x80) = 0 ?

No

RemainingSegmentSize = 0 AND Yes

(SegmentFlags AND 0x40) = 0 ?

No

Yes
► InputSequenceAck =
InputMTU_Size = MTU_Offset ?
InputSequenceCounter

No

Figure 441: Flow chart for the input direction

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Details

It is recommended to store transmitted messages in separate receive arrays.

After a set MessageEndBit is transmitted, the subsequent segment should be added to the receive array. The
message is then complete and can be passed on internally for further processing. A new/separate array should
be created for the next message.

Information:
When transmitting with MultiSegmentMTUs, it is possible for several small messages to be part of one
sequence. In the program, it's important to make sure that a sufficient number of receive arrays can
be managed. The entire sequence must be accepted before it is possible to change the Acknowledge
register.
If a SequenceCounter is incremented by more than one value, then an error has occurred (this situation is very
unlikely when operating without "Forward" functionality).
In this case, the receiver stops. All additional incoming sequences are ignored until the transmission with the correct
SequenceCounter is retried. This response prevents the transmitter from receiving any more acknowledgments for
transmitted sequences. The transmitter can identify the last successfully transmitted sequence from the opposite
station's SequenceAck and continue the transmission from this point.
Acknowledgments must be checked for validity.
If the receiver has successfully accepted a sequence, it must be acknowledged. The receiver takes on the Se-
quenceCounter value sent along with the transmission and matches the SequenceAck to it. The transmitter reads
the SequenceAck and registers the successful transmission. If the transmitter acknowledges a sequence that has
not yet been dispatched, then the transmission needs to be interrupted and the channel resynchronized. The syn-
chronization bits are reset and the current/incomplete message is discarded. It needs to be sent again once the
channel has been resynchronized.

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FlatStream mode register

In the input direction, the transmit array is generated automatically. This register offers two options to the user
that allow an incoming data stream to have a more compact arrangement. Once enabled, the program code for
evaluation must be adapted accordingly.

Information:
All B&R modules that offer FlatStream mode support the options "Large segments" and "Multi-segment
MTU" in the output direction. Compact transmission only needs to be explicitly allowed in the input
direction.
Bit structure:
Bit Name Information
0 MultiSegmentMTU 0 Not allowed (default)
1 Allowed
1 Large segments 0 Not allowed (default)
1 Allowed
2-7 Reserved

Default:
By default, both options relating to compact transfers in the input direction are disabled.
1. The module only forms segments that are at least one byte smaller than the activated MTU. Each sequence
begins with a control byte so that the data stream is clearly structured and relatively easy to evaluate.
2. Since a FlatStream message can be of any length, the last segment of the message frequently doesn't fill up
all of the MTU's space. By default, the remaining bytes during this type of transfer cycle are not used.

Bus cycle 1 Bus cycle 2 Bus cycle 3

C C C
- - -
ME0 ME1 ME1

Segment 1 Segment 2 Segment 3

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 442: Message arrangement in the MTU (default)

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MultiSegmentMTU allowed:
With this option, the InputMTU is completely filled (if enough data is pending). The previously unfilled Rx bytes
transfer the next control bytes and their segments. This allows the activated Rx bytes to be used more efficiently.
Bus cycle 1 Bus cycle 2 Bus cycle 3

C C C C
- -
ME0 ME1 ME0 ME1

Segment 1 Segment 2 3 Segment 4

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 443: Message arrangement in the MTU (MultiSegmentMTU)

Large segments allowed:
When transferring very long messages or when activating only very few Rx bytes, then a great many segments
must be created by default. The bus system is more stressed than necessary since an additional control byte needs
to be created and transferred for every segment. With the "Large segments" option, the segment length is limited
to 63 bytes independently of the InputMTU. One segment can stretch across several sequences, i.e. it's possible
for "pure" sequences to occur without a control byte.

Information:
It is still possible to split up a message into several segments, however. If this option is used and
messages with more than 63 bytes occur, for example, the messages can still be split up among several
segments.

Bus cycle 1 Bus cycle 2 Bus cycle 3

C C
- - - -
ME1 ME1

Segment 1 Segment 2 Segment 3

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 444: Message arrangement in the MTU (large segments)

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Using both options:

It is also possible to use both options at the same time.
Bus cycle 1 Bus cycle 2 Bus cycle 3

C C
- - - -
ME1 ME1

Segment 1 Segment 2 Segment 3

Message 1 Message 2

C
Control byte with MessageEndBit = 0
ME0

C
Control byte with MessageEndBit = 1
ME1

Figure 445: Message arrangement in the MTU (large segments and MultiSegmentMTU)

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FlatStream adjustment

If the way messages are structured is changed, then the way data in the transmit/receive array is arranged is also
different. The following changes apply to the example given earlier on.
MultiSegmentMTU:
If MultiSegmentMTUs are allowed, then "open positions" in an MTU can be used. These "open positions" occur if
the last segment in a message doesn't fully use the entire MTU. MultiSegmentMTUs allow these bits to be used
to transfer the following control bytes and segments. In the program sequence, the "nextCBPos" bit in the control
byte is set so that the receiver can correctly identify the next control byte.
Example:
Three autonomous messages (7 bytes, 2 bytes, 9 bytes) are being transferred using an MTU with a width of 7 bytes.
The configuration allows the transfer of MultiSegmentMTUs.
Message 1: Transmit/Receive array

With 7 USINT elements according to

the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Message 2: MultiSegmentMTU

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

C2 A7 C3 B1 B2 C4 D1 Sequence for bus cycle 2

Message 3:
C5 D2 D3 D4 D5 D6 D7 Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C6 D8 D9 C0 - - - Sequence for bus cycle 4

No more data to transmit C0 - - - - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 446: Transmit/Receive array (MultiSegmentMTU)

First, the messages must be split into segments. As in the default configuration, it's important for each sequence
to begin with a control byte. The free bits in the MTU at the end of a message are filled with data from the following
message, however. With this option, the "nextCBPos" bit is always set if payload data is transferred after the control
byte.
MTU = 7 bytes → Max. segment length = 6 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 6 data bytes (MTU full)

➯ Second segment = Control byte + 1 data byte (MTU still has 5 open bytes)
• Message 2 (2 bytes)

➯ First segment = Control byte + 2 data bytes (MTU still has 2 open bytes)
• Message 3 (9 bytes)

➯ First segment = Control byte + 1 data byte (MTU full)

➯ Second segment = Control byte + 6 data bytes (MTU full)
➯ Third segment = Control byte + 2 data bytes (MTU still has 4 open bytes)
• No more messages

➯ C0 control byte

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A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C1 (control byte 1) C2 (control byte 2) C3 (control byte 3)
- SegmentLength (6) = 6 - SegmentLength (1) = 1 - SegmentLength (2) = 2
- nextCBPos (1) = 64 - nextCBPos (1) = 64 - nextCBPos (1) = 64
- MessageEndBit (0) = 0 - MessageEndBit (1) = 128 - MessageEndBit (1) = 128
Control byte Σ 70 Control byte Σ 193 Control byte Σ 194

Table 441: FlatStream determination of the control bytes for default configuration example (part 1)

Warning!
The second sequence must have been completely processed before it can be acknowledged with Se-
quenceAck. In the example, there are three different segments within the second sequence, i.e. the
program must include enough receive arrays to handle this situation.
C4 (control byte 4) C5 (control byte 5) C6 (control byte 6)
- SegmentLength (1) = 1 - SegmentLength (6) = 6 - SegmentLength (2) = 2
- nextCBPos (6) = 6 - nextCBPos (1) = 64 - nextCBPos (1) = 64
- MessageEndBit (0) = 0 - MessageEndBit (1) = 0 - MessageEndBit (1) = 128
Control byte Σ 7 Control byte Σ 70 Control byte Σ 194

Table 442: FlatStream determination of the control bytes for default configuration example (part 2)

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Large segments:
Segments are limited to a maximum of 63 bytes. This means they can be larger than the active MTU. These large
segments are divided among several sequences when transferred. It is possible for sequences to be completely
filled with payload data and not have a control byte.

Information:
It is still possible to subdivide a message into several segments so that the size of a data packet doesn't
also have to be limited to 63 bytes.
Example:
Three autonomous messages (7 bytes, 2 bytes, 9 bytes) are being transferred using an MTU with a width of 7 bytes.
The configuration allows the transfer of large segments.

Message 1: Transmit/Receive array

With 7 USINT elements according to

the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Message 2: Large segments

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

A7 - - - - - - Sequence for bus cycle 2

Message 3:
C2 B1 B2 - - - - Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C3 D1 D2 D3 D4 D5 D6 Sequence for bus cycle 4

No more data to transmit D7 D8 D9 - - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 447: Transmit/Receive array (large segments)

First, the messages must be split into segments. The ability to form large segments means that messages are split
up less frequently, which results in fewer generated control bytes.
Large segments allowed → Max. segment length = 63 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 7 data bytes

• Message 2 (2 bytes)

➯ First segment = Control byte + 2 data bytes

• Message 3 (9 bytes)

➯ First segment = Control byte + 9 data bytes

• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C1 (control byte 1) C2 (control byte 2) C3 (control byte 3)
- SegmentLength (7) = 7 - SegmentLength (2) = 2 - SegmentLength (9) = 9
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (1) = 128 - MessageEndBit (1) = 128 - MessageEndBit (1) = 128
Control byte Σ 135 Control byte Σ 130 Control byte Σ 137

Table 443: FlatStream determination of the control bytes for large segments example

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Large segments and MultiSegmentMTU:

Example:
Three autonomous messages (7 bytes, 2 bytes, 9 bytes) are being transferred using an MTU with a width of 7 bytes.
The configuration allows the transfer of large segments as well as MultiSegmentMTUs.
Message 1: Transmit/Receive array
With 7 USINT elements according to
the configurable MTU size
A1 A2 A3 A4 A5 A6 A7

Message 2: Both options

C1 A1 A2 A3 A4 A5 A6 Sequence for bus cycle 1

B1 B2

A7 C2 B1 B2 C3 D1 D2 Sequence for bus cycle 2

Message 3:
D3 D4 D5 D6 D7 D8 D9 Sequence for bus cycle 3

D1 D2 D3 D4 D5 D6 D7 D8 D9
C0 - - - - - - Sequence for bus cycle 4

No more data to transmit C0 - - - - - - Sequence for bus cycle 5

- - - ... C0 - - - - - - Sequence for bus cycle 6

Figure 448: Transmit/Receive array (large segments and MultiSegmentMTU)

First, the messages must be split into segments. If the last segment of a message doesn't completely fill the MTU,
it can be used for other data in the data stream. The "nextCBPos" bit must always be set if the control byte belongs
to a segment with payload data.
The ability to form large segments means that messages are split up less frequently, which results in fewer gen-
erated control bytes. Control bytes are generated in the same way as with the "Large segments" option.
Large segments allowed → Max. segment length = 63 bytes
• Message 1 (7 bytes)

➯ First segment = Control byte + 7 data bytes

• Message 2 (2 bytes)

➯ First segment = Control byte + 2 data bytes

• Message 3 (9 bytes)

➯ First segment = Control byte + 9 data bytes

• No more messages

➯ C0 control byte
A unique control byte must be generated for each segment. In addition, the C0 control byte is generated to keep
communication on standby.
C1 (control byte 1) C2 (control byte 2) C3 (control byte 3)
- SegmentLength (7) = 7 - SegmentLength (2) = 2 - SegmentLength (9) = 9
- nextCBPos (0) = 0 - nextCBPos (0) = 0 - nextCBPos (0) = 0
- MessageEndBit (1) = 128 - MessageEndBit (1) = 128 - MessageEndBit (1) = 128
Control byte Σ 135 Control byte Σ 130 Control byte Σ 137

Table 444: FlatStream determination of the control bytes for large segments and MultiSegmentMTU example

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4.16.5.10.10.5 "Forward" function example on the X2X bus

The "Forward" function is a method that can be used to substantially increase the FlatStream data rate. The basic
principle is also used in other technical areas such as "pipelining" for microprocessors.

How it works

Communication on the X2X bus cycles through five different steps to transfer a FlatStream sequence. A successful
sequence transfer therefore requires at least five bus cycles.
Step I Step II Step III Step IV Step V
Actions Transfer sequence from Cyclic matching of MTU and Append sequence Cyclic matching Check SequenceAck
transmit array, module buffer toreceive array, of MTU and module buffer
increase Sequence- adjust SequenceAck
Counter
Resource Transmitter Bus system Receiver Bus system Transmitter
(task for sending) (direction 1) (task for receiving) (direction 2) (task for Ack checking)

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 ...

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Figure 449: Comparison of transmission without/with "Forward"

Each of the five steps (tasks) requires different resources. If the Forward function is not used, the sequences are
executed one after the other. Each resource is then only active if it is needed for the current sub-action.
With Forward, a resource that has executed its task can already be working on the next message. The condition
for enabling the MTU has been changed to allow for this. Now the sequences are passed to the MTU based on
timing. The transmitting station no longer waits for an acknowledgment from SequenceAck, which means that the
given bandwidth can be used much more efficiently.
In the most ideal situation, all resources are working during each bus cycle. The receiver still has to acknowledge
every sequence received. Only when SequenceAck has been changed and checked by the transmitter is the
sequence considered as having been transferred successfully.

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Configuration

The Forward function only has to be enabled for the input direction. Two additional configuration registers are
available for doing so. FlatStream modules have been optimized in such a way that they support this function. In
the output direction, the Forward function can be used as soon as the size of the OutputMTU is specified.
Forward:
With the "Forward" register, the user specifies how many unacknowledged sequences the module is allowed to
send.
Recommendation:
X2X bus: Max. 5
POWERLINK: Max. 7
Data type Values
USINT 1...7
Default: 1

ForwardDelay:
The "ForwardDelay" register is used to specify the delay time in µs. This is the amount of time the module has
to wait after sending a sequence until it is allowed to write new data to the MTU in the following bus cycle. The
program routine for receiving sequences from a module can therefore be run in a task class whose cycle time is
slower than the bus cycle.
Data type Values [µs]
UINT 0...65535
Default: 0

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Zeit

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Zeit

Figure 450: Effect of ForwardDelay when using FlatStream communication with the Forward function
In the program, it is important to make sure that the CPU is processing all of the incoming InputSequences and In-
putMTUs. The ForwardDelay value causes delayed acknowledgment in the output direction and a delayed recep-
tion in the input direction. In this way, the CPU has more time to process the incoming InputSequence or InputMTU.

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Transmitting and receiving with Forward

The basic algorithm for transmitting and receiving data remains the same. With the Forward function, up to seven
unacknowledged sequences can be transmitted. Sequences can be transmitted without having to wait for the
previous message to be acknowledged. Since the delay between writing and response is eliminated, a considerable
amount of additional data can be transferred in the same time window.
Algorithm for transmitting:
Cyclic status query:
- The Module monitors the OutputSequenceCounter.
0. Cyclic checks:
- The CPU must check OutputSyncAck.
→ If OutputSyncAck = 0: Reset the OutputSyncBit and resynchronize the channel.
- The CPU must check whether OutputMTU is enabled.
→ If OutputSequenceCounter > OutputSequenceAck + 7, then it is not enabled because the last sequence has not yet been acknowledged.
1. Preparation (create transmit array):
- The CPU must split up the message into valid segments and create the necessary control bytes.
- The CPU must add the segments and control bytes to the transmit array.
2. Transmitting:
- The CPU must transfer the current part of the transmit array to the OutputMTU.
- The CPU must increase the OutputSequenceCounter for the sequence to be accepted by the module.
- The CPU can then transmit in the next bus cycle if the MTU has been enabled.
The module responds since OutputSequenceCounter > OutputSequenceAck:
- The module accepts data from the internal receive buffer and appends it to the end of the internal receive array.
- The module is acknowledged and the currently received value of the OutputSequenceCounter is transferred to OutputSequenceAck.
- The module requests the status cyclically again.
3. Completion (acknowledgment):
- The CPU must check OutputSequenceAck cyclically.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via OutputSequenceAck. In order to detect potential trans-
mission errors in the last sequence as well, it is important to make sure that the algorithm is run through long enough.
Note:
To monitor communication times exactly, the task cycles that have passed since the last increase of the OutputSequenceCounter should be counted. In this
way, the number of previous bus cycles necessary for the transmission can be measured. If the monitoring counter exceeds a predefined threshold, then the
sequence can be considered lost (the relationship of bus to task cycle can be influenced by the user so that the threshold value needs to be determined individ-
ually).

Algorithm for receiving:

0. Cyclic status query:
- The CPU must monitor the InputSequenceCounter.
Cyclic checks:
- The module checks InputSyncAck.
- The module checks if InputMTU is enabled.
→ Enabling criteria: InputSequenceCounter > InputSequenceAck + Forward
Preparation:
- The module forms the control bytes / segments and creates the transmit array.
Action:
- The module transmits the current part of the transmit array to the receive buffer.
- The module increases the InputSequenceCounter.
- The module waits for a new bus cycle after the ForwardDelay time has expired.
- The module repeats the action if the InputMTU is enabled.
1. Receiving (InputSequenceCounter > InputSequenceAck):
- The CPU must accept data from the InputMTU and append it to the end of the receive array.
- The CPU must match InputSequenceAck to the InputSequenceCounter of the sequence currently being processed.
Completion:
- The module monitors InputSequenceAck.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via InputSequenceAck .

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Details/Background:
1. Illegal SequenceCounter size (counter offset)
Error situation: MTU not enabled
If the difference between SequenceCounter and SequenceAck is larger than allowed during transmission,
then a transmission error has occurred. In this case, all unacknowledged sequences must be repeated with
the old SequenceCounter value.
2. Checking an acknowledgment
After an acknowledgment has been received, a check must verify whether the acknowledged sequence has
been transmitted and had not yet been unacknowledged. If a sequence has been acknowledged more than
once, then a fatal error has occurred. The channel must be closed and resynchronized (same behavior as
when not using Forward).

Information:
In exceptional cases, the module can increment OutputSequenceAck by more than 1 when using
Forward.
This is not an error. The CPU is permitted to consider all sequences up to the one being acknowl-
edged as having been transmitted successfully.

3. Transmit and receive arrays

The Forward function has no effect on the structure of the transmit and receive arrays. They are created and
must be evaluated in the same way.

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Errors when using Forward

In industrial environments, it's often the case that many different devices from various manufacturers are being
used side by side. The electrical and/or electromagnetic properties of these technical devices can sometimes cause
them to interfere with one another. These kinds of situations can be reproduced and protected against in laboratory
conditions only to a certain point.
Precautions have been taken for X2X bus transfers if this type of interference occurs. For example, if an invalid
checksum occurs, the I/O system will ignore the data from this bus cycle and the receiver receives the last valid
data once more. With conventional (cyclic) data points, this error can often just be ignored. In the following cycle,
the same data point is again retrieved, adjusted and transferred.
Using the "Forward" function with FlatStream communication makes this situation more complex. The receiver
receives the old data again in this situation as well, i.e. the previous values for SequenceAck/SequenceCounter
and the old MTU.
Loss of acknowledgment (SequenceAck):
If a SequenceAck value is lost, then the MTU was already transferred properly. For this reason, the receiver is per-
mitted to continue processing with the next sequence. The SequenceAck is aligned with the associated Sequence-
Counter and sent back to the transmitter. The check of incoming acknowledgments shows that all sequences up
to the last one acknowledged have been transferred successfully (see image: Sequence 1, 2).
Loss of transmission (SequenceCounter, MTU):
If a bus cycle drops out and the SequenceCounter value and/or filled MTU are lost, then no data reaches the
receiver. At this point, the transfer routine is not yet affected by the error. The time-controlled MTU is released
again and can be rewritten to. The receiver receives SequenceCounter values that have been incremented several
times. For the receive array to be put together correctly, the receiver is only allowed to process transmissions
whose SequenceCounter has been increased by one. The incoming sequences must be ignored, i.e. the receiver
stops and doesn't send back any more acknowledgments. If the maximum number of unacknowledged sequences
has been sent and no acknowledgments are returned, the transmitter must repeat the affected SequenceCounter
and associated MTUs (see image: Sequence 3, 4).

Sequence 1 Step I Step II Step III Step IV Step V

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step III Step IV Step V

Sequence 4 Step I Step II Step III Step IV Step V

Bus cycle 1 Bus cycle 2 Bus cycle 3 Bus cycle 4 Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Sequence 1 Step I Step II Step III

Sequence 2 Step I Step II Step III Step IV Step V

Sequence 3 Step I Step II Step I Step II Step III

Sequence 4 Step I Step II Step I Step II

Bus cycle 1 Bus cycle 2 Bus cycle 3 EMC Bus cycle 5 Bus cycle 6 Bus cycle 7 Bus cycle 8 Bus cycle 9 Bus cycle 10

Time

Figure 451: Effect of a lost bus cycle

Loss of acknowledgment:
In Sequence 1, the acknowledgment is lost due to disturbance. Sequences 1 and 2 are therefore acknowledged
in Step V of Sequence 2.
Loss of transmission:
In Sequence 3, the entire transmission is lost due to disturbance. The receiver stops and doesn't send back any
more acknowledgments.
The sending station continues transmitting until it has issued the maximum allowed number of unacknowledged
transmissions.
Five bus cycles later at the earliest (depending on the configuration), it begins resending the unsuccessfully sent
transmissions.

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4.16.5.10.11 EnDat on Flatstream

EnDat is a synchronous interface capable of half-duplex communication. A variety of safety measures are taken
to ensure error-free signal transfer.
• An automatically generated checksum is sent together with a signal and evaluated by the recipient.
• The command which the encoder is responding to is repeated at the start of a response.
In Flatstream mode, the module acts as a bridge between the CPU and the EnDat slave. EnDat-specific algorithms
were implemented to monitor timeouts and handle checksums. During normal operation, the user does not have
access to these details.
More detailed information can be found in the documentation "Technical Information - EnDat 2.2" and the encoder's
manufacturer data.

4.16.5.10.11.1 Overview of conventional EnDat commands for the Flatstream mode

Command Command EnDat 2.2 only
byte [hex]
0x00 Reset
0x01 Acknowledge error
0x04 Read parameter
0x05 Write parameter
0x06 Read parameter from memory block ●
0x07 Write parameter in memory block ●
0x08 Read word 1 from additional information ●
0x09 Read word 2 from additional information ●
0x0A Read word 3 from additional information ●
0x0B Read word 4 from additional information ●

4.16.5.10.11.2 Reset (0x00)

Master command
Protocol bytes Information
No. Name
Master
1 0x00 Command (Reset)
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 0x00 Repetition (safety)
Master

4.16.5.10.11.3 Acknowledge error (0x01)

Master command
Protocol bytes Information
No. Name
Master
1 0x01 Command (acknowledge error)
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 0x01 Repetition (safety)
Master

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4.16.5.10.11.4 Read parameter (0x04)

Master command
Protocol bytes Information
No. Name
Master
1 0x04 Command (read parameter)
2 MRS code
Memory area to read
3 Parameter no.
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 0x04
2 MRS code Repetition (safety)
3 Parameter no.
4 Value_L
Value read
5 Value_H
Master

4.16.5.10.11.5 Write parameter (0x05)

Master command
Protocol bytes Information
No. Name
Master
1 0x05 Command (write parameter)
2 MRS code
Memory area to write to
3 Parameter no.
4 Value_L
Value to be written
5 Value_H
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 0x05
2 MRS code Repetition (safety)
3 Parameter no.
Master

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4.16.5.10.11.6 Read parameter from memory block (0x06)

Master command
Protocol bytes Information
No. Name
Master
1 0x06 Command (read parameter from memory block)
2 MRS code
3 Block no. Memory area to read
4 Parameter no.
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 0x06
2 MRS code
Repetition (safety)
3 Block no.
4 Parameter no.
5 Value_L
Value read
6 Value_H
Master

4.16.5.10.11.7 Write parameter in memory block (0x07)

Master command
Protocol bytes Information
No. Name
Master
1 0x07 Command (write parameter in memory block)
2 MRS code
3 Block no. Memory area to write to
4 Parameter no.
5 Value_L
Value to be written
6 Value_H
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 0x07
2 MRS code
Repetition (safety)
3 Block no.
4 Parameter no.
Master

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4.16.5.10.11.8 Read word 1 from additional information (0x08)

Master command
Protocol bytes Information
No. Name
Master
1 0x08 Command (read word 1 from additional information)
2 MRS code Memory area to read
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 0x08
Repetition (safety)
2 MRS code
3 Value_L
Word 1 from additional information
4 Value_H
Master

4.16.5.10.11.9 Read word 2 from additional information (0x09)

Master command
Protocol bytes Information
No. Name
Master
1 0x09 Command (read word 2 from additional information)
2 MRS code Memory area to read
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 0x09
Repetition (safety)
2 MRS code
3 Value_L
Read word 1 from additional information (overhead)
4 Value_H
5 Value_L
Word 2 from additional information
6 Value_H
Master

4.16.5.10.11.10 Read word 3 from additional information (0x0A)

Master command
Protocol bytes Information
No. Name
Master
1 0x0A Command (read word 3 from additional information)
2 MRS code Memory area to read
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 0x0A
Repetition (safety)
2 MRS code
3 Value_L
Read word 1 from additional information (overhead)
4 Value_H
5 Value_L
Read word 2 from additional information (overhead)
6 Value_H
7 Value_L
Word 3 from additional information
8 Value_H
Master

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4.16.5.10.11.11 Read word 4 from additional information (0x0B)

Master command
Protocol bytes Information
No. Name
Master
1 0x0B Command (read word 4 from additional information)
2 MRS code Memory area to read
Slave

Slave response
Protocol bytes Information
No. Name
Slave
1 0x0B
Repetition (safety)
2 MRS code
3 Value_L
Read word 1 from additional information (overhead)
4 Value_H
5 Value_L
Read word 2 from additional information (overhead)
6 Value_H
7 Value_L
Read word 3 from additional information (overhead)
8 Value_H
9 Value_L
Word 4 from additional information
10 Value_H
Master

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4.16.5.10.12 Function models

Name Number Automation CANopen DeviceNet Modbus/TCP CANIO

Studio
Standard function model 0 ●
Bus controller function model 254 ● ● ● ●

A function model specifies the registers on the module (storage model) that are available for the application. Only
these registers are processed on the module during each cycle and transferred cyclically via the bus. In this way,
it is possible to minimize the cycle time by selecting the correct function model.

4.16.5.10.13 Minimum cycle time

The minimum cycle time defines how far the bus cycle can be reduced without causing a communication error
or impaired functionality. It should be noted that very fast cycles decrease the idle time available for handling
monitoring, diagnostics and acyclic commands.
Minimum cycle time
100 µs

4.16.5.10.14 Minimum I/O update time

The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
100 µs

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 X20 system modules • Dummy modules • X20IF0000

4.17 Dummy modules

The dummy module is used as a placeholder to prevent configuration errors caused by empty slots.

4.17.1 Brief information

Product ID Short description on page
X20IF0000 X20 dummy interface module (non-functional) 1453
X20ZF0000 Dummy X20 module (non-functional) 1455
X20ZF000F Dummy X20 module (non-functional) 1458

4.17.2 X20IF0000

4.17.2.1 General information

Covers for unused interface module slots are included with X20 CPUs. If an X20 system is used in a maritime
environment, then the system will be subjected to increased vibration fatigue. In order to achieve the stability
necessary for operation, the X20IF0000 dummy interface module from the X20 series is used instead of the covers.
• Cover for unused interface module slots
• IF dummy modules required if the X20 system is subjected to increased vibration fatigue
• Module with no electrical function

4.17.2.2 Order data

Model number Short description Figure

Dummy modules
X20IF0000 X20 dummy interface module (non-functional)

Table 445: X20IF0000 - Order data

4.17.2.3 Technical data

Product ID X20IF0000
Short description
Accessories Non-functional dummy module
General information
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
GL Yes
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20

Table 446: X20IF0000 - Technical data

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Product ID X20IF0000
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Slot In X20 CPU, X20BB3x and X20BB8x

Table 446: X20IF0000 - Technical data

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 X20 system modules • Dummy modules • X20ZF0000

4.17.3 X20ZF0000

4.17.3.1 General information

The X20ZF0000 module is used as a place holder for later system expansion.
• Place holder for later system expansion
• Used as a terminal holder
• Module with no electrical function

4.17.3.2 Order data

Model number Short description Figure

Dummy modules
X20ZF0000 Dummy X20 module (non-functional)
Required accessories
Bus modules
X20BM01 X20 power supply bus module, 24 VDC keyed, internal I/O sup-
ply interrupted to the left
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
X20cBM01 X20 supply bus module, coated, internal I/O supply interrupted
to the left
X20cBM11 X20 bus module, coated, 24 V keyed, internal I/O supply con-
tinuous
Terminal blocks
X20TB06 X20 terminal block, 6-pin, 24 VDC keyed
X20TB12 X20 terminal block, 12-pin, 24 VDC keyed

Table 447: X20ZF0000 - Order data

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4.17.3.3 Technical data

Product ID X20ZF0000
Short description
Accessories Non-functional dummy module
General information
Certification
CE Yes
cULus Yes
ATEX Zone 2 Yes
GL Yes
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB06 or X20TB12 terminal block separately
Order 1x X20BM11 bus module or 1x X20BM01 supply bus module separately
Spacing 12.5 +0.2 mm

Table 448: X20ZF0000 - Technical data

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4.17.3.4 Pinout

X20 ZF 0000
4.17.3.5 Connection example

+24 VDC +24 VDC

GND GND

4.17.4 X20ZF000F

4.17.4.1 General information

The X20ZF000F module is used as a placeholder for later system expansion.

• Placeholder for later system expansion
• Used as a terminal holder
• Module with no electrical function

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4.17.4.2 Order data

Model number Short description Figure

Dummy modules
X20ZF000F Dummy X20 module (non-functional)
Required accessories
Bus modules
X20BM01 X20 power supply bus module, 24 VDC keyed, internal I/O sup-
ply interrupted to the left
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
X20cBM01 X20 supply bus module, coated, internal I/O supply interrupted
to the left
X20cBM11 X20 bus module, coated, 24 V keyed, internal I/O supply con-
tinuous
Terminal blocks
X20TB1E X20 terminal block, 12-pin, 24 VDC keyed, 2x PT1000 integrated
for terminal temperature compensation
X20TB1F X20 terminal block, 16-pin, 24 VDC keyed

Table 449: X20ZF000F - Order data

4.17.4.3 Technical data

Product ID X20ZF000F
Short description
Accessories Non-functional dummy module
General information
Certification
CE Yes
ATEX Zone 2 Yes
Operating conditions
Mounting orientation
Horizontal Yes
Vertical Yes
Installation at elevations above sea level
0 to 2000 m No limitations
>2000 m Reduction of ambient temperature by 0.5°C per 100 m
EN 60529 protection IP20
Environmental conditions
Temperature
Operation
Horizontal installation -25 to 60°C
Vertical installation -25 to 50°C
Derating -
Storage -40 to 85°C
Transport -40 to 85°C
Relative humidity
Operation 5 to 95%, non-condensing
Storage 5 to 95%, non-condensing
Transport 5 to 95%, non-condensing
Mechanical characteristics
Note Order 1x X20TB1E or 1x X20TB1F terminal block separately
Order 1x X20BM11 bus module or 1x X20BM01 supply bus module separately
Spacing 12.5 +0.2 mm

Table 450: X20ZF000F - Technical data

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4.17.4.4 Pinout

4.17.4.5 Connection example

+24 VDC +24 VDC

GND GND

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X20 system modules • X20 electronics module communication • Brief information

4.18 X20 electronics module communication

The CS modules allow complex devices to be remotely connected to the X20 system via a serial interface.

4.18.1 Brief information

Product ID Short description on page
X20CS1011 X20 interface module, 1 Moeller SmartWire interface 1461
X20CS1012 X20 interface module, 1x M-Bus master, integrated slave supply 1476
X20CS1013 X20 interface module, 1x DALI master 1524
X20CS1020 X20 interface module, 1 RS232 interface, max. 115.2 kbit/s 1533
X20CS1030 X20 interface module, 1 RS422/485 interface, max. 115.2 Mbit/s 1575
X20CS1070 X20 interface module, 1x CAN, max. 1 Mbit/s, object buffer in transmit and receive direction 1617
X20CS2770 X20 interface module, 2x CAN, max. 1 Mbit/s, object buffer in transmit and receive direction 1662

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4.18.2 X20CS1011

4.18.2.1 General information

SmartWire from the company Moeller makes it possible to very easily integrate switching devices such as contac-
tors or motor protection switches in the X20 system without extensive wiring. It replaces the control circuit wiring
between the controller and switching devices with pluggable, pre-assembled connection cables.
Although SmartWire is an intelligent connection, this changes almost nothing for the machine programmer. Inte-
gration in the X20 system via the interface module cuts down on overall communication. The individual switching
devices can simply be viewed as digital inputs and outputs.

Practical applications
SmartWire allows up to 16 switching devices to be connected using pre-assembled cables and attached to the X20
SmartWire interface module. The system can configure itself completely at the push of a button without additional
intervention or effort. This replaces the wiring test that was previously necessary.
At the same time, the device configuration is known to the system. If a device is no longer available due to an error
or intervention, it will be detected immediately. Once corrected, the system continues to run.
The interface module is designed as a normal electronic module, which means it can be placed anywhere on the
remote backplane.
• X2X SmartWire master for controlling up to 16 SmartWire slaves
• Simple connection using pre-assembled connection cables
• Moeller SmartWire modules for Moeller standard switching devices
• Replaces control circuit wiring
• Contactor activation
• Contactor switching status
• Motor circuit breaker status
• 24 VDC control voltage via SmartWire connection cable

4.18.2.2 Order data

Model number Short description Figure

X20 electronics module communication
X20CS1011 X20 interface module, 1 Moeller SmartWire interface
Required accessories
Bus modules
X20BM11 Bus module, 24 VDC keyed, internal I/O supply continuous
Undefined
X20CA4S00.0005 SmartWire attachement cable, X20TB12 to SmartWire connec-
tor, 0.5 m
X20CA4S00.0015 SmartWire attachement cable, X20TB12 to SmartWire connec-
tor, 1.5 m

Table 451: X20CS1011 - Order data

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4.18.2.3 Technical data

Product ID X20CS1011
Short description
Communication module 1 SmartWire master for controlling up to 16 slaves
General information
B&R ID code 0xA38D
Status indicators SmartWire bus function, external supply voltage, operating state, module status
Diagnostics
Module run/error Yes, using status LED and software
SmartWire operating state Yes, using status LED and software
U Aux Yes, using status LED
Power output
Internal I/O 6.8 W for supplying external slaves (equal to 16 slaves each with 0.425 W)
Power consumption
Bus 0.01 W
Internal I/O 1.5 W
Additional power dissipation caused by the actua- -
tors (resistive) [W]
Electrical isolation
SmartWire bus - X2X Link Yes
SmartWire supply (17 VDC) - I/O supply No
Certification
CE Yes
cULus Yes
cCSAus HazLoc Class 1 Division 2 Yes
ATEX Zone 2 Yes
KC Yes
GOST-R Yes
Interfaces
Interface
Type SmartWire (LIN bus)
Design Connection made using 12-pin X20TB12 terminal block
Transfer rate 19200 bit/s
SmartWire
Data format 1 start bit, 8 data bits, no parity bit, 1 stop bit
Max. distance 4m
Configuration button
Internal Integrated in the module on the bottom of the housing.
External Connection via 12-pin terminal block
N.O. contact, not electrically isolated (use potential-free contact)
SWIRE terminal 1 (24 VDC)
Voltage drop for reverse polarity protection at Max. 0.1 VDC
3A
Voltage range Voltage and supply
Current load Max. 3 A
Short circuit protection No, only with external fuse
Monitoring 20 VDC < 24 VDC Aux < 29.4 VDC (via firmware)
SWIRE terminal 2
Daisy chain signal 5 VDC, CMOS level
SWIRE terminal 5 (bus level)
Dominant <2 VDC
Recessive >14.85 VDC
SWIRE terminal 6 (17 VDC)
Voltage range Typ. 16.6 VDC (16.3 VDC to 16.8 VDC)
Summation current Max. 400 mA for 16 SmartWire slaves
Short circuit protection Yes
Monitoring 14.2 VDC < 17 VDC Aux < 17.9 VDC (via firmware)
U-Aux (24 VDC aux supply)
Connection Externally via 12-pin terminal block 1)
Input voltage 24 VDC -15% / +20%
Fuse Recommended line fuse: 3 A, slow-blow
Summation current Max. 3 A fo