Power Supply Works with FET Drivers, DrMOS and Power

Blocks for Flexible Placement Near Microprocessors

Theo Phillips

As microprocessors demand progressively more current at lower voltages, it becomes

important to minimize conduction losses by placing the power supply as close to
the load as possible. This increases the value of every square millimeter of board
space near the load—particularly when multiple power stages are used. It is also
important to locate the DC/DC controller away from high current paths, which can
be difficult when the MOSFET gate drivers are in the controller package, because the
gate traces must also be kept short. Sometimes the best solution is to use external
power train devices or discrete N-channel MOSFETs and associated gate drivers.
The LTC3860 is a dual output step-down voltage (VOUT) and ground terminals Voltage mode operation ensures that
DC/DC controller designed to work in are monitored using a single differential per-phase currents up to 30A can be
conjunction with drivers or power train amplifier, enabling tight regulation even achieved while a stable switching wave-
devices such as DrMOS and power blocks, where IR losses occur through vias, trace form is maintained. In a current mode
enabling flexible design configurations runs and interconnects. Regulation is converter, the voltage on the output of
with PolyPhase® operation. Up to 12 further enhanced by the accuracy of the the error amplifier controls the peak
stages can be paralleled to increase output 600mV reference, which is ±0.75% with or valley switch current, such that the
current and clocked out of phase to mini- junction temperatures from 0°C to 85°C. switch current must always be moni-
mize input and output filtering (Figure 1). tored. With typical sense voltages of less
In PolyPhase configurations, both output than 100mV and current sense elements
having resistance of less than 1mΩ, the
VSNSOUT1
introduction of noise is always a con-
cern. In contrast, the LTC3860 compares
VCC 0°, 180° VCC 60°, 240° VCC 120°, 300° the differentially sensed error voltage on
+60° +60° +90°
CLKIN CLKOUT CLKIN CLKOUT CLKIN CLKOUT VOUT to a sawtooth ramp, which is on
PHSMD PHSMD PHSMD
FB1 FB1 FB1 the order of 1V. The ramp controls duty
FB2 FB2 FB2
ILIM2 COMP1 ILIM2 COMP1 ILIM2 COMP1
cycle—the larger the error voltage, the
ILIM1 COMP2 ILIM1 COMP2 ILIM1 COMP2 longer each phase’s top switch stays on.
IAVG TRACK/SS1,2 IAVG TRACK/SS1,2 IAVG TRACK/SS1,2

A 2-PHASE, SINGLE OUTPUT

REGULATOR USING INTEGRATED
DRIVER-MOSFETs (DrMOS)
VCC 210°, 30° VCC 270°, 90° VCC 330°, 150°
+60° +60°
Citing needs for high power density,
CLKIN CLKOUT CLKIN CLKOUT CLKIN CLKOUT
PHSMD PHSMD PHSMD increased efficiency at high switching
FB1 FB1 FB1
FB2 FB2 FB2
frequencies, and interoperability between
ILIM2 COMP1 ILIM2 COMP1 ILIM2 COMP1 controllers and power devices, Intel has
ILIM1 COMP2 ILIM1 COMP2 ILIM1 COMP2
IAVG TRACK/SS1,2 IAVG TRACK/SS1,2 IAVG TRACK/SS1,2 issued a set of technical specifications for
integrated driver-MOSFETs (DrMOS) used
in step-down DC/DC converters powering
its microprocessors. The compact lay-
Figure 1. Pin interconnections for a 12-phase buck converter using the LTC3860 out reduces efficiency losses due to stray

26 | July 2011 : LT Journal of Analog Innovation

 design features

Because the LTC3860 has a PWM output instead of

onboard MOSFET drivers, it can occupy board space
away from critical high current paths. Its applications
include high current power distribution and industrial
systems, and telecom, DSP and ASIC supplies.

VIN
9V +
470µF 100pF
CMDSH-3

VCC DRMBIAS VIN

5V 4.7µF 22µF
0.1µF
100k 0.22µF
VCIN VIN HSEN BOOT
PGOOD
RUN DISB 0.19µH**
SW1
FDMF8704 VSWH VOSP
VCC PWM
5V PWM1 100µF
1µF CGND PGND 1.74k 6.3V
4.99k
VCC
TRACK/SS1
VINSNS
IAVG
PGOOD1
RUN1
PWMEN1
PWM1

×10*
SGND 51.1k
1000pF VOSN
PWMEN1,2
VDIFF1 FB1 ILIM1
COMP1 ISNS1P 0.22µF
20k 49.9Ω 100pF VDIFF VSNSOUT ISNS1N
VOS VSNSN LTC3860 ISNS2N
6.8nF VOS VSNSP ISNS2P 0.22µF
30.1k 3.16k COMP2 ILIM2
VCC
TRACK/SS2

FB2 RUN2 VCC

PWMEN2
PGOOD2
CLKOUT
PHSMD

PWM2
CLKIN
FREQ

1.74k
CGND PGND
PWM2
TRACK/SS PWM SW2 0.19µH**
FDMF8704 VSWH
DISB
FREQ SET FOR 600kHz VCC
4.99k VCIN VIN HSEN BOOT 0.22µF
RUN

DRMBIAS VIN
* MURATA GRM32ERG0J107M 5V 4.7µF 22µF
** WÜRTH 744355019
CMDSH-3

Figure 2. A 2-phase, single output converter using the FDMF8704 in each power stage to produce a 1V, 50A converter with all ceramic output capacitors

inductance. Several manufacturers have The LTC3860 provides a PWM signal com- three-state, an external resistor pulls the
produced compliant devices. They are patible with DrMOS-compliant devices. For PWMEN pin low. Thus, three-state opera-
expected to operate at >500kHz (preferably example, the Fairchild FDMF8704 DrMOS is tion of the power stage is accomplished
1MHz), deliver 25A per phase at ~1V from specified for operation up to 1MHz at here by tying the PWMEN pin of the
a 5V–16V input, and occupy 8mm × 8mm 25A per phase, and the LTC3860 can be LTC3860 to the DISB pin of the DrMOS.
or 6mm × 6mm packages with defined programmed for a switching frequency
Figure 2 is the schematic for a 2-phase,
pinouts. They must accept a PWM input, from 200kHz –1.2MHz. The LTC3860’s
single output converter using the
which is used to alternately turn the top high and low commands are interpreted
FDMF8704 in each power stage to pro-
and bottom MOSFETs on and off when the by the FDMF8704 as top MOSFET on and
duce a 1V, 50A converter. A switching
input is high or low. It must be possible bottom MOSFET on, respectively. This
frequency of 600kHz is selected by tying
to turn both MOSFETs off (three-state), DrMOS does not recognize three-state
CLKIN low and FREQ high. The effective
by leaving the PWM pin floating or by signals on the PWM pin, but both of its
frequency is 1.2MHz, because the two
pulling the DISB pin of the DrMOS low. MOSFETs turn off when its DISB pin is
channels operate 180° out of phase.
An external inductor is required. pulled low. The LTC3860’s PWMEN pulls
high through an open drain when- By reducing the latency between clock
ever PWM is high or low. When PWM is cycles, the high switching frequency

July 2011 : LT Journal of Analog Innovation | 27

The LTC3860 has internal current sharing, and only
requires simple pin configurations and one external
capacitor at the IAVG pin to run phases together.
The IAVG pin stores a charge corresponding to the
instantaneous average current of all phases.

ILOAD
20A/DIV
IL
5A/DIV
IL
5A/DIV

VOUT VOUT VOUT

100mV/DIV 50mV/DIV 50mV/DIV
(AC-COUPLED) (AC-COUPLED) (AC-COUPLED)

20µs/DIV 4µs/DIV 4µs/DIV

LOAD STEP = 10A TO 30A LOAD STEP = 10A TO 20A LOAD STEP = 20A TO 10A

a b

Figure 3. Load transient response for the converter Figure 4. The converter of Figure 2 demonstrates stable current sharing at
of Figure 2 both edges of a load transient: (a) rising edge; (b) falling edge.

improves transient response. Stable connected to INTVCC , a single differential to a potential between VSNSOUT and SGND.
operation is possible with all ceramic amplifier is placed ahead of the master’s VSNSOUT is tied to the feedback string
output capacitors, which minimize the FB pin, and each TRACK/SS, COMP, and leading to FB of the master channel. This
output ripple because of their low ESR. output is tied to the other. The power arrangement overcomes error due to
Figure 3 shows the converter’s tran- stages are now actively balanced. One board interconnection losses, which often
sient response to a large load step. power good indicator, PGOOD1, reports result in voltage offsets between power
undervoltage and overvoltage events. ground and SGND. For this 1V output,
A common drawback of voltage mode
the difference between no load and
converters is that they do not play The maximum current sense mismatch
full load VOUT is typically just 1mV.
well together when they are combined between phases is ±2mV between chan-
to increase power capability. They nels on the same IC or on different ICs. WHEN EFFICIENCY IS THE PRIORITY
typically use the outputs of onboard This translates to tight current sharing When efficiency is a higher priority than
op amps as their loop compensation between channels in PolyPhase applica- minimizing board space, operating the
nodes. Because these outputs are low tions, particularly when the current sense LTC3860 at a relatively low switching
impedance, they cannot just be tied elements are well matched. Here, the frequency reduces switching losses, while
together to balance the current from Würth 744355019 inductors’ DC resistance adding a synchronous MOSFET reduces
each power stage. An external circuit is specified to have a tolerance of ±10% conduction losses, particularly if the
would be needed for each phase. at 20°C. Figures 4a and 4b show that converter operates at low duty cycle.
the inductor current levels follow each Since DrMOS packages contain just one
The LTC3860 has internal current shar-
other closely during a load transient. main and one synchronous MOSFET, it
ing, and only requires simple pin con-
becomes beneficial to use discrete FETs
figurations and one external capacitor at A differential amplifier provides remote
and drivers. The powerful LTC4449
the IAVG pin to run phases together. The sensing of the output voltage. VSNSP and
driver is ideally suited to the task.
IAVG pin stores a charge corresponding VSNSN are tied to VOUT and PGND at the
to the instantaneous average current of point of load. The potential between The LTC4449 is designed to drive top
all phases. The slave channel’s FB pin is these pins is translated, with unity gain, and bottom MOSFETs in a synchronous

28 | July 2011 : LT Journal of Analog Innovation

 design features

When efficiency is a higher priority than minimizing board space, operating the
LTC3860 at a relatively low switching frequency reduces switching losses, while
adding a synchronous MOSFET reduces conduction losses, particularly if the
converter operates at low duty cycle. Since DrMOS packages contain just one main
and one synchronous MOSFET, it is beneficial to use discrete FETs and drivers.

VIN
VIN 22µF
7V TO 18V + ×2
150µF DRMBIAS
PWM1 5V
LTC4449 VOS1P
1µF IN GND M1
VCC BG1
VLOGIC BG 0.3µH VOUT
0.1µF TG1 SW1
VCC TS 1.2V
100k 4.7µF 2.2Ω
BOOST TG + 25A
RUN M2 M3 330µF
×3
VCC
5V VCC 2.74k
1µF
VCC
TRACK/SS1
VINSNS
IAVG
PGOOD1
RUN1
PWM1

0.22µF VOS1N
SGND 49.9k
1nF
PWMEN1,2 SW1
VDIFF1 FB1 ILIM1 47µF
COMP1 ISNS1P 0.22µF ×3
20k 47pF VDIFF1
1% 220Ω VSNSOUT ISNS1N
VOS1N VSNSN LTC3860 ISNS2N
20k 470pF VOS1P VSNSP ISNS2P M1,M2, M3: RJK0305DPB
1% 1.74k COMP2 ILIM2 COUT: 330µF ×3 SANYO 2R5TPE330M9
VCC
TRACK/SS2

FB2 RUN2 L: 0.3µH PULSE PA0515.321NL

PGOOD2
CLKOUT
PHSMD

PWM2
CLKIN
FREQ

PWM2

FREQ SET FOR 400kHz 0Ω

Figure 5. The LTC3860 can use the LTC4449 to drive discrete MOSFETs. A synchronous MOSFET is added to improve efficiency.

DC/DC converter. It accepts high, low and can occur. The driver is available in a 400kHz operation is set by tying the
three-state inputs, with thresholds pro- low profile 2mm × 3mm DFN package. FREQ and CLKIN pins low. Other switching
portional to the LTC3860 power supply frequencies, from 250kHz to 1.25MHz, can
Figure 5 shows a schematic for a single
because the LTC4449 VLOGIC is at the same be programmed with a single resistor from
channel, 400kHz, single phase converter
potential as the LTC3860 VCC . The VCC of FREQ to ground, or synchronized with
using the LTC4449 and discrete MOSFETs.
the LTC3860 can range from 3V to 5.5V, an external signal source, with a smooth
Figure 6 shows the improvement in
and if it drops below the undervoltage transition to and from the resistor-set
efficiency compared to a DrMOS solu-
lockout (UVLO) threshold (2.9V falling, frequency if an interruption in the sync
tion operating at the same frequency
3.0V rising), both channels of the LTC3860 signal occurs. No external PLL filter com-
with the same passive components.
are disabled. UVLO ensures that the driver ponents are required for synchronization.
operates only when VCC is at safe levels. Discrete MOSFETs also provide an input
The VINSNS pin monitors the input voltage
voltage capability higher than the
For maximum efficiency, the LTC4449’s and immediately adjusts the duty cycle in
DrMOS requirement (16V). The VINSNS pin
top gate has pull-up and pull-down a manner inversely proportional to VIN,
of the LTC3860, which connects to the
times of 8ns and 7ns; the bottom bypassing the feedback loop. This feature
supply at the drain of the main MOSFET,
gate, 7ns and 4ns, while looking into brings two benefits: a set of compensation
can handle up to 24V. This allows
3000pF loads. Adaptive shoot-through values works across the entire VIN range,
LTC3860 applications to benefit from
protection ensures that the dead times and during a line transient deviation in
the large number of 30V MOSFETs avail-
are short enough to avoid power loss, VOUT is minimal, as Figure 7 shows.
able from various manufacturers.
but not so short that cross-conduction

July 2011 : LT Journal of Analog Innovation | 29

Instead of selecting power stage components,
designers have the option of specifying an entire
power stage on a small PC board. Known as a power
block, it includes MOSFETs, a MOSFET driver, an
inductor, and minimal input and output capacitors.

100
90 LTC4449 + MOSFETs
80
PIP212-12M
70
EFFICIENCY (%)

60
SW
50 5V/DIV
IL
40 10A/DIV
30 VOUT
100mV/DIV
20 (AC-COUPLED) VOUT
1V/DIV
10
SHORT CIRCUIT
0
0 1 10 100 5µs/DIV 20ms/DIV
ILOAD (A) VIN = 12V L = PA0515.321NL
VOUT = 1.2V RLIM = 61.9k

Figure 6. The circuit of Figure 5 shows improved Figure 7. Through its VINSNS pin, the LTC3860 Figure 8. Short circuit behavior of the LTC3860
efficiency compared with a typical DrMOS solution. provides line feedforward compensation, preventing
The compromise is in board space—a DrMOS steady state and dynamic variations in VOUT when
occupies 36mm2 or 64mm2, and the driver and three VIN is not constant.
MOSFETs occupy 101mm2, excluding the traces
connecting the components.

The ILIM pin provides a handle for setting WHEN SIMPLICITY IS REQUIRED Connections are also provided for tem-
current limit. It sources 20µ A through Instead of selecting power stage com- perature sensing and inductor DCR sens-
an external resistor, providing a voltage ponents, designers have the option of ing. They typically operate at 12V input,
proportional to the current limit. When specifying an entire power stage on a switching at 400kHz –500kHz and source
current limit is reached, the LTC3860 small PC board. Known as a power block, 20A–40A. Unlike DrMOS, power blocks
three-states the PWM output, resets the it includes MOSFETs, a MOSFET driver, an do not occupy a standard footprint.
soft-start timer, and waits 32768 switch- inductor and minimal input and output
The LTC3860 is shown in Figure 10
ing cycles before restarting (Figure 8). capacitors. Electrical and mechanical
coupled with a Delta power block. This
connection is made through standoffs
The LTC3860 has the ability to start high current, 400kHz, 2-phase applica-
which surface mount onto the main board.
up into a prebiased output. When the tion can source 45A at its output. Since
TRACK/SS voltage is below the voltage at each channel operates 180° out of phase
Figure 9. Start-up into a prebiased output for
FB, the LTC3860 will not switch (except for discrete MOSFET application
with respect to the other, the effective
refresh pulses, which keep the boost capac- switching frequency is doubled, mini-
itor charged). When TRACK/SS exceeds mizing stress on the input and output
FB, switching commences, but inductor 1.2V capacitors. The power block’s physical
VOUT
current is not allowed to reverse until the 500mV/DIV dimensions are approximately 1.0"L
0.9V
output reaches regulation, when continu- TRACK/SS × 0.5"W × 0.5"H, yielding a small solu-
500mV/DIV
ous conduction mode begins. Thus, the tion size. Topside heat sinks are pro-
output is allowed to rise gently (Figure 9). vided for the onboard MOSFETs, and
IL
5A/DIV
200LFM airflow at <55°C is required.

2ms/DIV

30 | July 2011 : LT Journal of Analog Innovation

 design features

The LTC3860 is a dual output step-down DC/DC

controller designed to work in conjunction with drivers or
power train devices such as DrMOS and power blocks,
enabling flexible design configurations with PolyPhase
operation. Up to 12 stages can be paralleled.

SOME OPTIONS WITH THIS voltage accuracy over an operating CONCLUSION

VERSATILE CONTROLLER temperature range of –40°C to 125°C. The LTC3860 is a voltage mode buck
The applications presented here use the controller that supports up to 12 phases in
drop across the inductor to sense cur- Instead of the default 2ms soft-start used
parallel with onboard current sharing. It
rent sharing and current limit. If a small by the applications here, adjustable soft-
may be used with DrMOS, power blocks or
increase in power loss is acceptable, start (>2ms) and tracking are also pos-
discrete MOSFETs and the LTC4449 driver.
greater accuracy may be achieved by using sible for each output. Longer soft-start
Because the LTC3860 has a PWM output
a discrete sense resistor in series with times are achieved by adding >10nF from
instead of onboard MOSFET drivers, it can
the inductor. The applications here also TRACK/SS to ground. Tracking is achieved
occupy board space away from critical
have output voltages in the 1.x range. by driving the pin with a DC voltage of
high current paths. Its applications include
Outputs as low as 0.6V (the reference less than 0.6V. The output regulates to the
high current power distribution and
voltage) or as high as 4V (the maximum lowest of the internal 600mV reference,
industrial systems, and telecom, DSP and
output voltage of the differential ampli- the voltage on the TRACK/SS pin, or the
ASIC supplies. The LTC3860 is available in
fier) are also possible, with ±1% reference internal soft-start ramp for that channel.
a 32-lead 5mm × 5mm QFN package. n

Figure 10. A 2-phase, single output converter using a 45A Delta power block for the power stage

VIN
10V TO 14V + VCC 100pF
180µF VCC
5V 100k VOS1P
1µF 7V BIAS
4.7µF
51Ω
PGOOD +7V VOUT1
TEMP1 VOUT1 1V
RUN PWM1
PWM1 100µF
+ 330µF 4.7µF 45A
×6 ×6 ×2
POWER BLOCK GND
VCC

VINSNS
IAVG
PGOOD1
RUN1
RUN2
PWM1

53.6k
GND DELTA
PWMEN1,2 ILIM1 D12S1R845A 51Ω
FB1 +CS1
1500pF
COMP1 ISNS1P 0.22µF VOS1N
VDIFF1 VDIFF1 VSNSOUT ISNS1N –CS1
VOS1N VSNSN LTC3860 ISNS2N –CS2
20k 562Ω 100pF
1% VOS1P VSNSP ISNS2P 0.22µF
COMP2 +CS2
30.1k VCC FB2 ILIM2
TRACK/SS1
TRACK/SS2

1.5nF VCC
1% VIN1 VIN
PGOOD2
CLKOUT

4.64k
PHSMD

PWM2

22µF
CLKIN
FREQ

16V
×4
VIN2
VCC TEMP2 VOUT2
RUN PWM2
PWM2
GND
0.1µF 34.8k 100k
1%
FREQUENCY SET FOR 400kHz VCC

July 2011 : LT Journal of Analog Innovation | 31