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CONTENTS

1. INTRODUCTION………………………………………………………………3

2. OVERVIEW……………………………………………………………………..3

3. DESIGN PROCESS…………………………………………………………….4

4. ASSIGNMENT SPECIFICATION………………………………………….5

5. FSM DESIGN FOR DIGITAL LOCK………………………………………6

6. ALGORITHM FOR TASK 1 AN TASK2………………………………...7

7. FSM FOR TASK3……………………………………………………………….8

8. VHDL DESCRIPTION FOR DIGITAL LOCK……………………………9

9. TECHNICAL ACHIEVEMENTS IN DESIGN PROCESS…………….9

10. SYNTHESIS RESULTS……………………………………………………….11

11. REAL TIME RESULTS ON NEXYS 4 DDR HARDWARE………..13

12. CONCLUSION AND FUTURE SCOPE…………………………………15

13. APPENDIX……………………………………………………………………….16
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INTRODUCTION

Taking security into consideration as one of the priority issues of this

generation, human beings are always on exploring advance
techniques which can keep their assets to maximum security level.
Designing a digital lock using VHDL have tremendous advantages over
other systems in terms of speed, parallel processing, portability and
other critical parameters. The advantage of using VHDL is that this
language has constructs to handle parallelism inherent in hardware
designs, file input and output capability, can be mapped onto a
programmable logic device and it can be used for several FPGA
implementations. [1]

OVERVIEW

This mini project/assignment gives a brief overview of how digital lock

using VHDL description is implemented on NEXYS 4 DDR hardware.
The main objective of the assignment is to design, implement a
simple combination lock using VHLD and synchronous design
techniques to implement it on the FPGA board. The interface between
the user and the board will be through the usage of push buttons,
LED’S 7-Segments Display and slider switches on the NEXYS 4 DDR
board.
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DESIGN PROCESS
The basic procedure to implement a digital design into hardware using VHDL are
followed as below.

VHDL DESCRIPTION

SIMULATION

SYNTHESIS

IMPLEMNATATION

CONFIGURATION

 After completing the design of the system, the next stage is to write a
VHDL code.
 VHDL code must be synthesised. Synthesis procedure converts the VHDL
code into series of logical components which in turn can be constructed
into nexys 4 DDR hardware.
 Simulation is a way of telling the user how the system behaves before
implementing into hardware, it also gives the user an idea on how the
system will operate.
 Next comes the implementation process. This process is mainly
responsible for planning the positions of logical components on chip.
 The final procedure consists of configuring the hardware according to
the design the VHDL code has developed. This is done by generating a
coded file which in turn streamed to Nexys 4 DDR Board using
designated programming software.[2]
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Assignment Specification

Task 1: A simple digital combinational lock

 Code sequence to unlock– 42429
 One of the push buttons will be used to indicate that the user wishes to
enter a code sequence. (Button named BTNU is used for this purpose)
 A digit will be entered as a binary number on the slider switches.
 Once the digit has been a set up on the slider switches, a second button
named BTNC will be used by the user to indicate that the first digit is ready
to be read.
 The user then uses the slider switches and the second push button to
enter the remaining four digits.
 If the code sequence is correct, LEDS 0 to 7 will light up indicating user
has entered correct sequence.
 If the code sequence is wrong, LEDS 0 to 7 will turn off indicating user has
entered wrong code sequence.

Task 2: Improvising user interface

 Along with lighting up led’s if the user has entered the correct sequence,
Code sequence should be displayed on 7 segments display on 5 digits and
OK message should also be displayed. Displaying of code sequence and
message should alternate at 1 second time interval.
 Same procedure is followed for incorrect sequence except message Ok.
Here ,Err message is displayed if the user enters wrong sequence .

Task 3:An Improved Combinational Lock

 Here system request the user to enter two random digits index in the code
sequence .If the users enters the corresponding two digits task 2
procedure is followed and vice versa.
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FSM DESIGN FOR DIGITAL CLOCK

State Diagram For Task 1 and Task2

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ALGORITHM FOR TASK1 AND TASK2

Proposed structure and design of the system:

Step 1: Current state will be in sc. It prompts the user to enter BTNC push button.
Once pressing this button systems alerts user to enter the lock code sequence.
Hence current state shifts to state_init on pressing BTNC button.
Step 2. A digit will be entered as a binary number on the slider switches. Switches
0 to 3 in nexys 4 DDR is used for this purpose. A second button named BTNC is
triggered which displays first digit on 7 segments display and control further
moves to state_2.
Step 3. Same procedure is followed for remaining 4 digits as mentioned in
step2.At this point of time system will be in state_out which decides whether
the code sequence is correct or wrong
Step 4. If the code sequence is correct, display message of OK and Code
sequence will be displayed alternating at 1 sec time interval.
Step 5. If the code sequence is wrong, display message of Err and Code sequence
will be displayed alternating at 1 sec time interval.
Step 6. At any point of time if the user presses reset button it shifts to current
state (i.e. sc => waits for user to enter BTNU) reverts back to step 1 .
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FSM DESIGN FOR TASK 3

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VHDL DESCRIPTION OF DIGITAL LOCK

Complete VHDL description is listed in appendix with proper comments for

digital lock obeying all the specifications of task1, task2 and task 3 in one single
integrated code showcasing RTL, Data-Flow level as well as structural styles of
description.

TECHNICAL ACHIEVEMENTS IN DESIGNING PROCESS

However certain critical features implemented in vhdl description are as follows
 Clock divider to derive 1 kHz, 1 Hz signals wrapped inside the process by
taking the counts of corresponding x Hz * 100 MHz in binary form. This
show cases RTL Level of description.

 Building up from normal synchronous finite state machine template to

complex finite state machine code for pre-defined specification .VHDL
code is listed in appendix.
 7 segment display driver is taken from the basic template and modified
to required specifications.
 Also, continuous display of digits on 5 digit 7 segment display by usage
of high frequency clock is made use in vhdl description.
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 Structural style of description is also exposed in case of clock divider

circuit and 7 segment display driver by calling components which is similar
to modularity approach used in conventional programming languages.

 Two random number is generated which is incorporated from two

different high speed clock one 1khz and other 100 MHz clock signal.
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SYNTHESIS RESULTS

 Figure shows the schematic after synthesizing the vhdl description for
the finite state machine digital lock showcasing all the requirements in
specification in the assignment in one integrated code.
 By enhancing the structural style of description where ever possible for
above implemented design ,(for example building components for
comparison ,complex boolean expression,generating random no from
clock divider) results of synthesis would have been more efficient
compared to existing one .
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 As we can see from the above figure it projects the overall utilisation of
on- chip power which is approximately equal to 100 mw.
 Since the total on chip power is less (in terms of mw), design is
synthesised efficiently because of using integrated ,structural and RTL
level of description (i.e. mixed style of description ) where ever
required.
 Dynamic power accounts 19 % of the total on chip power whereas static
power utilization accounts for 81 % percent

 Figure above shows how much power has been power has been utilised
for input and output parameters
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REAL TIME RESULTS ON NEXYS 4 DDR HARDWARE

Case a:
When user enters correct code sequence display message ‘OK’ and code
sequence 42429 gets displayed on 5 digit 7 segment display at 1 sec time
interval .Also leds 0 to 7 will turn on indicating user has entered correct
sequence .

Case b:
When users enters wrong sequence same happens as mentioned in case a
except message Err is displayed instead of message Ok
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Case c:
If user enters third button ,system generates two random generator in the
range 0 to 4.Here user enters wrong two digits due to which error message
and code sequence will get displayed at 1 sec time interval. Whole process
explained is illustrated below.
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Conclusion and Future Scope

During the entire process of this assignment I understood how we can

concurrently executes the different process at same time which makes this
behaviour different from normal microntroller, microprocessor due to which
makes an easy method of designing digital systems .Also designing a digital using
finite state machine gives a clinical approach to solve complex digital design .This
assignment enhanced my skills and gave a deep insight on designing a finite
state machine for digital system from software level to implementing it on real
hardware.

If I ever get a chance to work on designing complex digital system in future this
basic foundation will help in designing the system in more efficient manner ,hig
speed and also splitting the system into individual blocks where ever possible as
modularity approach helps to locate troubleshoot anywhere in the complete
system.
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APPENDIX

VHDL CODE
Main source file
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Displaydriver code

Clock divider code