Arithmetic Logic Unit (ALU)

Introduction to Computer
p
Yung-Yu Chuang

with slides by Sedgewick & Wayne (introcs.cs.princeton.edu), Nisan & Schocken

(www.nand2tetris.org) and Harris & Harris (DDCA)
 Let's Make an Adder Circuit

Goal. x + y = z for 4-bit integers.

 We build 4-bit adder: 9 inputs,
p 4 outputs.
p
 Same idea scales to 128-bit adder.
 Key computer component.
1 1 1 0

2 4 8 7

+ 3 5 7 9

6 0 6 6

2
Binary addition

Assuming a 4-bit system:

0 0 0 1 1 1 1 1
1 0 0 1 + 1 0 1 1+
0 1 0 1 0 1 1 1

0 1 1 1 0 1 0 0 1 0

no overflow overflow

 Algorithm: exactly the same as in decimal addition

 Overflow (MSB carry) has to be dealt with.

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 3
Representing negative numbers (4-bit system)

0 0000  The codes of all positive numbers

begin with a “0”
1 0001 1111 -1
2 0010 1110 -2  The codes of all negative numbers
3 0011 1101 -3 begin with a “1“
4 0100 1100 -4
 To convert a number:b
5 0101 1011 -5 leave all trailing 0’s and first 1 intact,
6 0110 1010 -6 and flip all the remaining bits
7 0111 1001 -7
1000 -8

Example:
p 2 - 5 = 2 + (-5) = 0010
+1011
1101 = -3
3

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 4
 Let's Make an Adder Circuit

Step 1. Represent input and output in binary.

1 1 0 0

0 0 1 0

+ 0 1 1 1

1 0 0 1

x3 x2 x1 x0

+ y3 y2 y1 y0

z3 z2 z1 z0

5
 Let's Make an Adder Circuit

Goal. x + y = z for 4-bit integers.

cout cin

x3 x2 x1 x0

Step 2. [first attempt]

+ y3 y2 y1 y0

Build truth table.

z3 z2 z1 z0


4-Bit Adder Truth Table

c0 x3 x2 x1 x0 y3 y2 y1 y0 z3 z2 z1 z0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 0 0 0 1 1 0 0 1 1 28+1 = 512 rows!
0 0 0 0 0 0 1 0 0 0 1 0 0
. . . . . . . . . . . . .
1 1 1 1 1 1 1 1 1 1 1 1 1

Q. Why is this a bad idea?

A 128-bit adder: 2256+1
A. 56 rows >> # electrons

in universe!
6
 1-bit half adder

We add numbers one bit at a time.

x c
ADD
y s

x y s c

7
 1-bit full adder

x y
x y Cin Cout s
Cin
ADD
Coutt

8
8-bit adder

9
 Let's Make an Adder Circuit

Goal. x + y = z for 4-bit integers. c out c3 c2 c1 c0 = 0

x3 x2 x1 x0

Step 2. [do one bit at a time] + y3 y2 y1 y0

 Build truth table for carry bit. z3 z2 z1 z0

 Build truth table for summand bit.

Carry Bit Summand Bit

xi yi ci ci+1 xi yi ci zi
0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 1
0 1 0 0 0 1 0 1
0 1 1 1 0 1 1 0
1 0 0 0 1 0 0 1
1 0 1 1 1 0 1 0
1 1 0 1 1 1 0 0
1 1 1 1 1 1 1 1

10
 Let's Make an Adder Circuit

Goal. x + y = z for 4-bit integers.

Step 3.
 Derive (simplified) Boolean expression.

Carry Bit Summand Bit

xi yi ci ci+1 MAJ xi yi ci zi ODD

0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1 1 1
0 1 0 0 0 0 1 0 1 1
0 1 1 1 1 0 1 1 0 0
1 0 0 0 0 1 0 0 1 1
1 0 1 1 1 1 0 1 0 0
1 1 0 1 1 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1

11
 Let's Make an Adder Circuit

Goal. x + y = z for 4-bit integers.

Step 4.
 Transform Boolean expression into circuit.
 Chain together 1-bit adders.

12
Adder: Interface

13
Adder: Component Level View

14
Adder: Switch Level View

15
 Subtractor

Subtractor circuit: z = x – y.
 One approach:
pp design
g like adder circuit
 Subtractor

Subtractor circuit: z = x – y.
 One approach:
pp design
g like adder circuit
 Better idea: reuse adder circuit
– 2’s complement: to negate an integer, flip bits, then add 1

17
 Subtractor

Subtractor circuit: z = x – y.
 One approach:
pp design
g like adder circuit
 Better idea: reuse adder circuit
– 2’s complement: to negate an integer, flip bits, then add 1

18
 Shifter
Only one of them will be on at a time.
s0 s1 s2 s3

x0

x1
SHIFT
x2

x3

z0 z1 z2 z3

4 bit Shifter
4-bit Shift

19
 Shifter

z0 z1 z2 z3
s0
s1
s2
s3

20
 Shifter

z0 z1 z2 z3
s0 x0 x1 x2 x3
s1 0 x0 x1 x2
s2 0 0 x0 x1
s3 0 0 0 x0

z0 = s0‧x0 + s1‧0 + s2‧0 + s3‧0

z1 = s0‧x1 + s1‧x0 + s2‧0 + s3‧0
z2 = s0‧x2 + s1‧x1 + s2‧x0 + s3‧0
z3 = s0‧x3 + s1‧x2 + s2‧x1 + s3‧x0
21
 Shifter

z0 = s0‧x0 + s1‧0 + s2‧0 + s3‧0

z1 = s0‧x1 + s1‧x0 + s2‧0 + s3‧0
z2 = s0‧x2 + s1‧x1 + s2‧x0 + s3‧0
z3 = s0‧x3 + s1‧x2 + s2‧x1 + s3‧x0
22
 N-bit Decoder

N-bit decoder
 N address inputs,
p 2N data outputs
p
 Addresses output bit is 1;
all others are 0

23
 N-bit Decoder

N-bit decoder
 N address inputs,
p 2N data outputs
p
 Addresses output bit is 1;
all others are 0

24
 2-Bit Decoder Controlling 4-Bit Shifter

Ex. Put in a binary amount r0r1 to shift.

25
 Arithmetic Logic Unit

Arithmetic logic unit (ALU). Computes all

p
operations in parallel.
p
 Add and subtract.
 Xor.
 A d
And.
 Shift left or right.

Q. How to select desired answer?

Q

26
 1 Hot OR

1 hot OR. adder

 All devices compute

p their answer;
we pick one.
 Exactly one select line is on.
 Implies exactly one output line is xor

relevant.

x．1 = x
x．0
0=0 shifter

x+0=x

27
 1 Hot OR
x．11 = x
adder
x．0 = 0

x+0=x
xor
decoder

shift

28
 Bus

16-bit bus
 Bundle
u of
f 16 w
wires
 Memory transfer
Register transfer

8-bit bus
 Bundle of 8 wires
 TOY memory y address

4 bit bus
4-bit b
 Bundle of 4 wires
 TOY register address

29
 Bitwise AND, XOR, NOT

Bitwise logical operations

 Inputs
p x and y:
y n bits each
 Output z: n bits
 Apply logical operation to each corresponding pair
of bits

30
 TOY ALU

TOY ALU
 Big
g combinational logic
g
 16-bit bus
 Add, subtract, and, xor, shift left, shift right,
copy input 2

31
 Device Interface Using Buses
16 bit words for TOY memory
16-bit

Device. Processes a word at a time.

p bus. Wires on top.
Input p
Output bus. Wires on bottom.
Control. Individual wires on side.

32
 ALU

Arithmetic logic unit.

 Add and subtract.
 Xor.
 And.
 Shift left or right.
right

Arithmetic logic unit.

 Computes all operations in
parallel.
 Uses 1-hot OR to pick each
bit answer.
answer

How to convert opcode to

1-hot OR signal?
33
34
35
 Hack ALU

16
x 16
16-bit
16
out
adder
y

zx nx zy ny f no out(x, y, control bits) =

x+y, x-y, y–x,
0, 1, -1,
x
16 bits x, y, -x, -y,
ALU out
y 16 bits x!, y!,
16 bits
x+1 y+1
x+1, y+1, x
x-1,
1 yy-1,
1
x&y, x|y
zr ng
Hack ALU
The ALU in the CPU context (a sneak preview of the Hack platform)

c1,c2, … ,c6

D
D register

a
out

ALU
A
A register

A/M

Mux
M
RAM M

(selected
register)

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 38
Perspective

 Combinational logic

 Our adder design is very basic: no parallelism

 It pays to optimize adders

 Our ALU is also very basic: no multiplication, no division

 Wh
Where is the
th seat
s t of
f more
m advanced
d n d math
m th operations?
p ti ns?
a typical hardware/software tradeoff.

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 39