Addressing Modes Instruction Set Architecture

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Introduction:

The Instruction is task or command, performed by a computer program consist of a sequence of small
steps called as micro-operations such as adding two numbers, transferring the data from memory or
input device to CPU, testing for a condition. Set of instruction of a computer must perform the
following operations: Data transfer (memory, register, I/O transfer), Arithmetic and logical, Program
control and sequencing. (Type of instructions according to operation performed by instruction)

Basic instruction has two fields: Op-code operations code and operand (data or address of data or
name of register). Operation performed by any instruction can be represented in from of register a
transfer statement which is called as Register Transfer Notation (RTN) or Register Transfer Language
(RTL). Another type of symbolic representation is used called Assembly Language Notation.

R3←R1+R2 Register Transfer Notation

SUM R1,R2,R3 Assembly Language Notation

R1←[MAR] Register Transfer Notation


(MAR is memory address register)

Addressing mode:
The addressing mode is the way in which the location of an operand is specified. Generally, data type
used in computer are constant and variable. In assembly language, variable is represented by
allocating register or memory location to hold its value.
Register Addressing:
The operand is the contents of a processor register; the name (address) of the register is given in the
instruction.
Move R1, R2 : Register Transfer Statement R2←R1
Direct Addressing:
The operand is in a memory location; the address of this location (effective address) is given explicitly
in the instruction. This is called as absolute addressing mode. The address which directly point the
operand (data) is called as Effective Address (EA).
Move PLACE, R2 : PLACE is memory location

The instruction given above PLACE is memory location where contents of R2 will be copied. This
instruction uses the both addressing mode, direct and register. In some high level programming
absolute addressing mode is use to represent global variable.
Integer A, B;
In this statement compiler will allocate a memory location to each of the variable A and B. Whenever
they are referenced later in the program, the compiler can generate assembly language instruction
that use the direct mode to access the variable.
Immediate Addressing:
The operand is immediate data or explicitly given in the instruction.
Move 45 (immediate), R1
Immediate data 45 will be loaded in the register R1. The sharp Sign (#) is generally used to represent
the immediate addressing. Hence, above instruction can be in form
Move #45, R1

A high level program


Integer A, B;
A← 6+B;

Can be represented in the assembly program as given below. Constant A and B can be accessed by
absolute addressing as explained above.

Move B, R1
Add #6, R1
Move R1, A
Indirect Addressing:
Effective address of operand is the content of register or memory location, which name or address is
given in the instruction. Name of register or address of memory given in the memory is not the
effective address or directly point the data, but contents of that has the effective address.

Representation of this addressing mode is given below. First figure shows that register R1 has EA1
which is the effective address of operand. Similarly, in second figure address location given in
instruction POINT is not an effective address. Effective address is given at the location POINT that is
EA2 which will actually point the operand.

The memory location or register that contains the address of an operand is called a pointer. The
pointer is important and powerful concept in programming. By changing the contents of register R1 or
memory location POINT, Add instruction fetches different operands to add in R0.

Address Content Address Content


Add (R1), R2 Add (POINT), R2
: Memory : Memory
: :
EA1 Operand POINT EA2
:
R1 EA1 Register EA2 Operand

Consider the C-language statement

A=*B

Where b is pointer variable. This statement may be compiled into

Move B, R1
Move (R1), A
This action can be achieved by the instruction
Move (B), A
But indirect addressing through memory required two memory accesses; therefore, it is not used in
computer. Indirect through register is used extensively.

Index addressing:

The effective address of the operand is generated by adding a constant value to the contents of
register. The register used for this purpose may be special register or one of the general purpose
registers. Register used for this purpose is called as index register. This type of addressing mode is
useful in list and array. The symbolic representation of this mode is given as:

X(Ri)

X denotes the constant value given in the register and Ri is index register. Therefore, effective
address will be:

EA = X + (Ri)

Constant X must be in sign-extended.

Add 4(R0), R1

Effective address (EA) is generated by 4+R0 , data pointed by EA is added with content of R1 and
result is stored in R1 .

Base Index Addressing:

The effective address is the sum of the contents of base register and index register.

EA = [RB]+[Ri]

RB is index register and Ri is index register.

Relative Addressing:

The effective address is determined by the Index mode using the program counter (PC) in place of
the general-purpose register. X(PC) can be used to address a memory location that is X bytes away
from the location presently pointed by program counter. This is use to specify the target address in
branch instruction. An instruction such as

Branch LOOP

When assembler process this instruction, it computes the offset value and generate the
corresponding machine instruction using X(PC).

Auto-increment Addressing:

The effective address of the operand is the contents of a register specified in the instruction. After
accessing the operand, the contents of this register are automatically incremented to point to the
next item in a list. The auto-increment mode is written as (Ri)+. Example is given as
Add (R1)+, R2
Effective address is contents of R1, operand is accessed from that location and added with content of
R2. After accessing the operand contents of R1is incremented by one to point the next location in
memory. This type of addressing is used in stack related instructions. To pop the data from the stack
memory, first data pointed by stack pointer is popped and then pointer is incremented by one which
will point the next location in stack memory. Detail use of this will be discussed in the section called
the stack.

Auto-decrement Addressing:

The content of register specified in the instruction is first automatically decrement and then used as
effective address of operand. This can be represent as –(Ri) . This addressing is use in stack related
instructions. Before writing (push) in the stack pointer is decremented by one and data will be
pushed at that location.

Move –(R1),R2

Content of register R1 is decremented by one, which will be the effective address of the operand.
Data from the memory pointed by the effective address will be accessed and transfer to the register
R2.

We have used normal word like Move, Add, Increment, Decrement, Store, and Branch to represent
the instruction operation. When writing program or symbolic representation for a specific computer,
such a words are called as mnemonics MOV, ST, BR, INR, DCR, ADD etc. A complete set of such
symbolic name and rules for their use is called the assembly language. For the addressing mode of
instruction is given as # immediate, () indirect, ()+ auto-increment, -() auto-decrement are used. These
are the way to represent the addressing mode. Like immediate addressing can be given as MVI, ADI (I
denote the immediate, # is also used), LDX (X denote indirect in some programming languages @ is
also used for indirect addressing). Assembly language for given computer may or may not be case
sensitive. Therefore, for different processor or computer different set of assembly language
instructions are available.

User’s original program given in text, word or symbols is called as source program. Assembler will
automatically translate the assembly language instructions in to sequence of machine instruction that
is set of 0’s or 1’s which is later executed by the computer. This machine instructions are program is
called as object program. . Assembler program is one of the system software stored in the memory
of computer.

Classification of Instruction: According to the operation performed by computer instruction is


classified as

1. Data transfer instruction: MOV, ST, LD, MOV, XCH, IN, OUT, PUSH, POP

2. Arithmetic instruction: ADD, SUB, INC, DEC, MUL, DIV, ADDC, SUBB

3. Logical instruction: CLR, COM, AND, XOR, OR, CLRC, SETC, COMC, EI, DI, SHR, SHL, SHRA,
SHLA,
4. Program Control: BR, CALL, JMP, SKP, RET, CMP, TST (these can be use with status condition
like: over flow, carry, sign, and zero),

Mnemonics Branch condition Test condition


BZ Brach if zero Z = 1 (result is zero)
BNZ Branch if not zero Z = 0 (result is non zero)
BC Branch if carry C =1
BNC Branch if no carry C=0
BP Branch if positive S=0
BM Branch if negative S=1
BV Branch if overflow V=1
Compare conditions (A -B)
BHI Branch if Higher A>B
BHE Branch if Higher or equal A≥B
BLO Branch if lower A˂B
BLOE Branch if lower or equal A≤B
BE Branch if Equal A=B
BNE Branch if not equal A ≠B

Classification of instruction according the address or operand field:

1. Zero address instruction: ADD

2. One address instruction: ADD B

3. Two address instruction: ADD A,B

4. Three address instruction: ADD, A,B,C

1. Zero address instruction: ADD Stack organized CPU


2. One address instruction: ADD B Accumulator based CPU

3. Two address instruction: ADD A,B


4. Three address instruction: ADD, A,B,C Register organized CPU
CPU Organization

The CPU has three main parts: set of registers, ALU and Control unit. Control unit control the
operation performed by ALU and data transfer among the registers. From the designer point of view,
it has to select the hardware to perform the tasks depending on the instruction set architecture. The
programmer must be aware the instruction set and operation performed by each instruction,
memory structure, register set and data type supported by specific system.
Most computers fall in to three type of CPU organization.
(1) Single Accumulator Organized Computer
(2) General Register Organized Computer
(3) Stack Organized Computer

(1) Single Accumulator Organization:


All the operations performed with accumulator only and result is stored in Accumulator itself.
Instruction has only one address field (address of operand). The organization discussed in
above section is based on this. This is the single bus architecture.

ADD X
Where X is the address of the operand stored in memory. Add operation will be performed
with content of AC as given below.
AC←AC+M[X]
Other instruction may be AND, LDA, STORE etc.

Memory

Accumulator

ALU

This architecture is also called as the Accumulator based CPU. Simplified block diagram of CPU can
be divided in two part (1) Data path or data processing unit and (2) Control or program control unit.
Data path unit will perform the data routing, store the operand and data processing. Control unit
decodes the instruction, control the program sequence, and generate the timing and control signals
to control the flow of micro-operations performed by CPU.
Control
unit
Instruction Control
decoder Signals

IR AR PC

To Memory and System Bus


I/O devices

DR AC

Arithmetic and Logic


Circuit

Datapath
unit
(2) General Register Organization
Because the memory access in the time consuming operation, so it is more efficient to store the
intermediate data in the processor register. When large numbers of registers are there then it is
convenient to connect them through common bus operations. These registers communicate each
other directly for data transfer and micro-operation.

Input
R1
R2
R3
R4
R5
R6
R7

Load R7 Load R1
n-bit 8X1 n-bit 8X1
Select A Select B
MUX A MUX B
3X8
Decode
r
OPR
ALU
Select D

Block Diagram

3 3 3 5
SELA SELB SELD OPR

Control word (Instruction format)

SELA and SELB used to select the two source data registers and SELD is used to select the destination
register to store the result coming from the ALU. Operation may be perform on the operand may
coming from the input (external data from the input). Only seven output lines of 3 x 8 decoder are
use to activate the load pin of one of the seven registers.

R1 ← R2 + R3

To perform the above add operation, SELA (MUX A) select the R2 and SELB (MUX B) select the R3
and result is stored in R1 which will be selected by the SELD (decoder). OPR bit pattern will decide
the operation which should be for ADD (suppose 00010). Size of control word is 14. Decoding of
each field is given in the tables.
Table: Register selection field

Binary code SELA SELB SELD

000 Input input None


001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
: : : :
: : : :

Selection of ALU operation field

OPR Operation Symbol

00000 Transfer A TSFA


00001 Increment A INCA
00010 ADD A +B ADD
00011 Subtract A- B SUB
00100 Decrement DECA
00101 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHAL

To perform any operation control word should be specify. The control word can be derived from the
selection variable of source, destination and operation. For example,

R1←R2−R3

From the tables given above we can derive the each field.

Field: SELA SELB SELD OPR


Symbol: R2 R3 R1 SUB
Control Word: 010 011 001 00101

The increment and transfer micro-operation do not use the B input for ALU. 000 assign to any
unused field. Following is the list of some micro-operation and field.
Example of Micro-operations

Symbolic Designation
Micro-operation SELA SELB SELD OPR Control Word

R1←R2−R3 R2 R3 R1 SUB 000 011 001 00101


R4←R4 ᴠ R5 R4 R5 R4 OR 100 101 100 01010
R6←R6 + 1 R6 -- R6 INCA 110 000 110 00001
R7← R1 R1 -- R7 TSFA 001 000 111 00000
Out ←R2 R2 -- None TSFA 000 000 000 00000
Output ← Input Input -- None TSFA 000 000 000 00000
R4 ←shl R4 R4 -- R4 SHAL 100 000 100 11000
R5←0 R5 R5 R5 XOR 101 101 101 01100
Multiple Bus Organization (general register organized) CPU: In single bus system only one data can
be transfer over the data bus in a clock. To reduce the time multiple bus system is used. All the
general purpose registers are combined into a block called register file. VLSI technology allows
efficient way of design the registers. Register file is the RAM with multiple ports. Two port to read
the source data and one write port to write the data. Therefore, a three bus system can be used to
interface the register file and ALU. As given in the figure Bus A and B is used to read the source
operands to input A and B of ALU. The Bus C is used to write the data or result in register file. Each
bus is has its dedicated function.

Address lines
Bus A Bus B Bus C

AR

PC

Register File

ALU

IR

DR

Three-bus System/ Register organized CPU


Register file:

Set of general purpose registers in modern CPU know as register file. Each register Ri in register file is
individually addressable. Register file are same as RAM but multiple port. The block diagram of RF
(register file) is given below. Two output port to read the two operands over the two buses and one
input port two write the data in register file through third bus. These two operands will be supplied
to input of ALU and result may be loaded in register file using third bus. Name or addresses of registers
are given in the instruction. Implementation of register file is given in fig. Register file is set of four
registers (R1, R2, R3 and R4) of 16 bit each. For design the bus system two 4X1 MUX (16 bits each line)
are required.

Function R3← f(R1,R2), can be implemented by using the three address instructions program. R1 and
R2 contents the two operands and result stored in R3, f is function are op-code given in instruction.

Data in to port C from


Bus C

Address/
Name of Port C
Port A
Register File

Address/Name A Port A Port B Address/Name B

Data out from A Data out from B


over to Bus A over to Bus B

Block diagram of
Register file
Data input
(16 bit)

Write address 4X1 MUX


C (16 bit)

R1 R2 R3 R4

Read address
4X1 MUX 4X1 MUX B
(16 bit) (16 bit)
Read address
A Data out Data out
(16 bit) (16 bit)

ALU

Implementation of register file


Stack Organization:

Stack is memory unit that can be used for temporary data storage. It can be unit of memory or set of
register s. It is based on LIFO (Last In First Out). The register that holds the address for the stack is
called a stack pointer (SP). SP always point to the top location of stack. Two push and pop can be
used to insert and delete the data from the stack.

Memory Stack: Figure show the stack pointer has the initial value of 4001d. It represents that top
location stack is 4001, and stack will be grow with decreasing the SP. So we can say that first data
will be stored at location 4000 in stack and second at location 3999 and so on. There is no limit of
stack (higher or lower). If computer system has any limit then it should be check after each push and
pop operation manually. So it is programmer responsibly to check that stack is full or not. Two
instructions PUSH and POP is used for inserting and deleting the items from the stack. After pop,
data are not physically removed from the memory. In PUSH following set of micro-operation are
performed.

SP ← SP−1
M [SP] ← DR
Stack pointer is decremented by one so that it points the next location. We have assumed that
memory write is perform through DR only, so data available in DR will be place in push operation.
Similarly, in the POP following set of micro-operation will be performed.

DR ← M [SP]
SP ← SP +1
Data pointer by SP will be read from the memory and paced in DR. SP is incremented by one now
that will point the top of the stack.
Stack may be growing by increasing the SP or decrementing the SP that will depend on the stack
organization. Stack should e initialize by the bottom address of memory and grow by decreasing the
SP.

SP
Stack Memory

ALU
Infix, prefix (polish) and postfix (reverse polish) notation: Arithmetic expression can be
represented in these notations. infix notation operator written the operands. To evaluate the
arithmetic expression scan back and forth along the expression to decide which operation to be
performed. For example,
A×B+C×D
First A × B and C × D will be performed and then + will be performed on the result.

A+B Infix notation


+AB Prefix or Polish notation
AB+ Postfix or reverse Polish notation
(RPN)

Reverse polish notation is suitable for the stack organized computer. Above expression can be
represented in RPN as,

AB × CD × +
To evaluate the, scan the expression from the left to right, when operator is reached perform the
operation on the two operands found on the left side of operator. Remove the operands and
operator and replace these by new result found by operation. Repeat this process for each operator.
To implement above operation on stack organize CPU, program can be written as:
PUSH A //TOS is A
PUSH B //TOS is B
MUL // multiplication with top two data, TOS is AXB
PUSH C //TOS is C
PUSH D //TOS is D
MUL // multiplication with top two data, TOS is CXD
ADD // top two data are AXB and CXD multiply these, TOS is (AXB) + (CXD)

B C C CXD

A A AXB AXB AXB AXB (AXB)+(CXD)

Stack memory and their content after each execution of instruction

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