HU

Dept of Electrical and Computer Engineering

420 Intro to VLSI Design
Lecture 0: Course Introduction and
Overview

Valencia M. Joyner
Spring 2005

ECE420 Intro to VLSI Design

HU Getting Started

 Syllabus
 About the Instructor
 Labs, Problem Sets, and Project
 Grading
 Collaboration
 Textbook
 Student Expectations
 CAD Tools and Projects

ECE420 Intro to VLSI Design

HU Today’s Topics

 Course Objectives
 The Billion $ Industry
 What is an integrated circuit?
 What is CMOS, VLSI, ASIC?
 Review of the Fundamentals
 How are CMOS transistors built?
 Building logic gates from transistors
 Transistor layout and fabrication

ECE420 Intro to VLSI Design

HU Course Objectives (I)

 By the end of the semester, you will be able to……

 VLSI Circuit Analysis:
• Understand MOS transistor operation, design eqns.
• Understand parasitics & perform simple calculations
• Understand static & dynamic CMOS logic
• Estimate delay of CMOS gates, networks, & long
wires
• Estimate power consumption
• Understand design and operation of latches &
flip/flops

ECE420 Intro to VLSI Design

HU Course Objectives (II)

 CMOS Processing and Layout

• Understand the VLSI manufacturing process.
• Have an appreciation of current trends in VLSI
manufacturing.
• Understand layout design rules.
• Design and analyze layouts for simple digital
CMOS circuits
• Design and analyze hierarchical circuit layouts.
• Understand ASIC Layout styles.

ECE420 Intro to VLSI Design

HU Course Objectives (III)

 VLSI System Design

• Understand the design flows used in industrial IC
design.
• Design simple combinational and sequential logic
circuits using using a Hardware Description Language
(HDL).
• Design a small standard-cell chip in its entirety using
a variety of CAD tools and check it for correct
operation.

ECE420 Intro to VLSI Design

HU Course Objectives (IV)

 Special Topics
• Understand issues related to the integration of
analog and digital circuits on a single chip
• Understand the adverse affects of
space/nuclear radiation on ICs

ECE420 Intro to VLSI Design

HU The Billion $ Industry

ECE420 Intro to VLSI Design

HU VLSI Trends:
Moore’s Law
 In 1965, Gordon Moore predicted that transistors
would continue to shrink, allowing:
 Doubled transistor density every 18-24 months
 Doubled performance every 18-24 months
 History has proven Moore right
 But, is the end is in sight?
 Physical limitations
 Economic limitations

Gordon Moore
Intel Co-Founder and Chairmain Emeritus
Image source: Intel Corporation www.intel.com

ECE420 Intro to VLSI Design

HU IC Evolution (I)

 SSI – Small Scale Integration (1965)

 contained 1 – 10 logic gates
 MSI – Medium Scale Integration (1970)
 logic functions, counters (30-103)
 LSI – Large Scale Integration (1980)
 first microprocessors on the chip (103- 105)
 VLSI – Very Large Scale Integration (1985)
 now offers 64-bit microprocessors,
complete with cache memory (L1 and often L2),
floating-point arithmetic unit(s), etc.
 (105-107)

ECE420 Intro to VLSI Design

HU IC Evolution (II)

 ULSI – Ultra Large Scale Integration (1990)

 107 – 109
 Giga-Scale Integration (2005)
 109 – 1011
 Tera-Scale Integration (2020)
 1011 - 1013

ECE420 Intro to VLSI Design

HU IC Evolution (III)

 Bipolar technology
 TTL (transistor-transistor logic)
 ECL (emitter-coupled logic)
 MOS (Metal-oxide-silicon)
 although invented before bipolar transistor,
was initially difficult to manufacture
 nMOS (n-channel MOS) technology developed in
1970s
required fewer masking steps, was denser, and
consumed less power than equivalent bipolar ICs =>
an MOS IC was cheaper than a bipolar IC and led to
investment and growth of the MOS IC market.

ECE420 Intro to VLSI Design

HU IC Evolution (IV)

 aluminum gates for replaced by polysilicon by early

1980
 CMOS (Complementary MOS): n-channel and p-
channel MOS transistors =>
lower power consumption, simplified fabrication
process
 Bi-CMOS - hybrid Bipolar, CMOS (for high speed)
 GaAs - Gallium Arsenide (for high speed)
 Si-Ge - Silicon Germanium (for RF)

ECE420 Intro to VLSI Design

HU VLSI Tech: CMOS

Key feature:
transistor length L 2002: L=130nm
2003: L=90nm
2005: L=65nm?

ECE420 Intro to VLSI Design

HU CMOS Devices

ECE420 Intro to VLSI Design

HU Silicon Lattice

 Transistors are built on a silicon substrate

 Silicon is a Group IV material
 Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si

ECE420 Intro to VLSI Design

HU Dopants

 Silicon is a semiconductor
 Pure silicon has no free carriers and conducts poorly
 Adding dopants increases the conductivity
 Group V: extra electron (n-type)
 Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

ECE420 Intro to VLSI Design

HU p-n Junctions

 A junction between p-type and n-type semiconductor

forms a diode.
 Current flows only in one direction

p-type n-type

anode cathode

ECE420 Intro to VLSI Design

HU nMOS Transistor
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
 Gate and body are conductors
 SiO2 (oxide) is a very good insulator
 Called metal – oxide – semiconductor (MOS)
capacitor
 Even though gate is Source Gate Drain
Polysilicon
no longer made of metal SiO2

n+ n+

p bulk Si

ECE420 Intro to VLSI Design

HU nMOS Operation

 Body is commonly tied to ground (0 V)

 When the gate is at a low voltage:
 P-type body is at low voltage
 Source-body and drain-body diodes are OFF
 No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

ECE420 Intro to VLSI Design

HU nMOS Operation Cont.

 When the gate is at a high voltage:

 Positive charge on gate of MOS capacitor
 Negative charge attracted to body
 Inverts a channel under gate to n-type
 Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

ECE420 Intro to VLSI Design

HU pMOS Transistor

 Similar, but doping and voltages reversed

 Body tied to high voltage (VDD)
 Gate low: transistor ON
 Gate high: transistor OFF
 Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

ECE420 Intro to VLSI Design

HU Power Supply Voltage

 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
 High VDD would damage modern tiny transistors
 Lower VDD saves power
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

ECE420 Intro to VLSI Design

HU Transistors as Switches

 We can view MOS transistors as electrically

controlled switches
 Voltage at gate controls path from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

ECE420 Intro to VLSI Design

HU CMOS Inverter

A Y VDD
0
1

A Y

A Y
GND

ECE420 Intro to VLSI Design

HU CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0

ON
A Y
GND

ECE420 Intro to VLSI Design

HU CMOS Inverter

A Y VDD
0 1
1 0 ON
A=0 Y=1

OFF
A Y
GND

ECE420 Intro to VLSI Design

HU CMOS NAND Gate

A B Y
0 0
0 1 Y
1 0 A
1 1
B

ECE420 Intro to VLSI Design

HU CMOS NAND Gate

A B Y
0 0 1 ON ON
0 1 Y=1
A=0
1 0 OFF
1 1
B=0
OFF

ECE420 Intro to VLSI Design

HU CMOS NAND Gate

A B Y
0 0 1 OFF ON
0 1 1 Y=1
A=0
1 0 OFF
1 1
B=1
ON

ECE420 Intro to VLSI Design

HU CMOS NAND Gate

A B Y
0 0 1 ON OFF
0 1 1 Y=1
A=1
1 0 1 ON
1 1
B=0
OFF

ECE420 Intro to VLSI Design

HU CMOS NAND Gate

A B Y
0 0 1 OFF OFF
0 1 1 Y=0
A=1
1 0 1 ON
1 1 0
B=1
ON

ECE420 Intro to VLSI Design

HU CMOS NOR Gate

A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

ECE420 Intro to VLSI Design

HU 3-input NAND Gate

 Y pulls low if ALL inputs are 1

 Y pulls high if ANY input is 0

ECE420 Intro to VLSI Design

HU 3-input NAND Gate

 Y pulls low if ALL inputs are 1

 Y pulls high if ANY input is 0

Y
A
B
C

ECE420 Intro to VLSI Design

HU CMOS Fabrication

 CMOS transistors are fabricated on silicon wafer

 Lithography process similar to printing press
 On each step, different materials are deposited or
etched
 Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process

ECE420 Intro to VLSI Design

HU Inverter Cross-section

 Typically use p-type substrate for nMOS transistors

 Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

ECE420 Intro to VLSI Design

HU Well and Substrate Taps

 Substrate must be tied to GND and n-well to VDD

 Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
 Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

ECE420 Intro to VLSI Design

HU Inverter Mask Set

 Transistors and wires are defined by masks

 Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

ECE420 Intro to VLSI Design

HU Detailed Mask Views

 Six masks n well

 n-well
 Polysilicon
Polysilicon

 n+ diffusion
 p+ diffusion n+ Diffusion

 Contact p+ Diffusion

 Metal Contact

Metal

ECE420 Intro to VLSI Design

HU Fabrication Steps

 Start with blank wafer

 Build inverter from the bottom up
 First step will be to form the n-well
 Cover wafer with protective layer of SiO2 (oxide)
 Remove layer where n-well should be built
 Implant or diffuse n dopants into exposed wafer
 Strip off SiO2

p substrate

ECE420 Intro to VLSI Design

HU Oxidation

 Grow SiO2 on top of Si wafer

 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

ECE420 Intro to VLSI Design

HU Photoresist

 Spin on photoresist
 Photoresist is a light-sensitive organic polymer
 Softens where exposed to light

Photoresist
SiO2

p substrate

ECE420 Intro to VLSI Design

HU Lithography

 Expose photoresist through n-well mask

 Strip off exposed photoresist

Photoresist
SiO2

p substrate

ECE420 Intro to VLSI Design

HU Etch

 Etch oxide with hydrofluoric acid (HF)

 Seeps through skin and eats bone; nasty stuff!!!
 Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

ECE420 Intro to VLSI Design

HU Strip Photoresist

 Strip off remaining photoresist

 Use mixture of acids called piranah etch
 Necessary so resist doesn’t melt in next step

SiO2

p substrate

ECE420 Intro to VLSI Design

HU n-well

 n-well is formed with diffusion or ion implantation

 Diffusion
 Place wafer in furnace with arsenic gas
 Heat until As atoms diffuse into exposed Si
 Ion Implanatation
 Blast wafer with beam of As ions
 Ions blocked by SiO2, only enter exposed Si
SiO2

n well

ECE420 Intro to VLSI Design

HU Strip Oxide

 Strip off the remaining oxide using HF

 Back to bare wafer with n-well
 Subsequent steps involve similar series of steps

n well
p substrate

ECE420 Intro to VLSI Design

HU Polysilicon

 Deposit very thin layer of gate oxide

 < 20 Å (6-7 atomic layers)
 Chemical Vapor Deposition (CVD) of silicon layer
 Place wafer in furnace with Silane gas (SiH4)
 Forms many small crystals called polysilicon
 Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

ECE420 Intro to VLSI Design

HU Polysilicon Patterning

 Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

ECE420 Intro to VLSI Design

HU Self-Aligned Process

 Use oxide and masking to expose where n+ dopants

should be diffused or implanted
 N-diffusion forms nMOS source, drain, and n-well
contact

n well
p substrate

ECE420 Intro to VLSI Design

HU N-diffusion

 Pattern oxide and form n+ regions

 Self-aligned process where gate blocks diffusion
 Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing

n+ Diffusion

n well
p substrate

ECE420 Intro to VLSI Design

HU N-diffusion cont.

 Historically dopants were diffused

 Usually ion implantation today
 But regions are still called diffusion

n+ n+ n+
n well
p substrate

ECE420 Intro to VLSI Design

HU N-diffusion cont.

 Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate

ECE420 Intro to VLSI Design

HU P-Diffusion

 Similar set of steps form p+ diffusion regions for

pMOS source and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate

ECE420 Intro to VLSI Design

HU Contacts

 Now we need to wire together the devices

 Cover chip with thick field oxide
 Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+
n well
p substrate

ECE420 Intro to VLSI Design

HU Metalization

 Sputter on aluminum over whole wafer

 Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate

ECE420 Intro to VLSI Design

HU Layout

 Chips are specified with set of masks

 Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
 Feature size f = distance between source and drain
 Set by minimum width of polysilicon
 Feature size improves 30% every 3 years or so
 Normalize for feature size when describing design
rules
 Express rules in terms of λ = f/2
 E.g. λ = 0.3 µm in 0.6 µm process

ECE420 Intro to VLSI Design

HU Simplified Design Rules

 Conservative rules to get you started

ECE420 Intro to VLSI Design

HU Inverter Layout

 Transistor dimensions specified as Width / Length

 Minimum size is 4λ / 2λ, sometimes called 1 unit
 In f = 0.6 µm process, this is 1.2 µm wide, 0.6 µm
long

ECE420 Intro to VLSI Design

HU Summary

 MOS Transistors are stack of gate, oxide, silicon

 Can be viewed as electrically controlled switches
 Build logic gates out of switches
 Draw masks to specify layout of transistors

 Now you know everything necessary to start

designing schematics and layout for a simple chip!

ECE420 Intro to VLSI Design