DATA REPRESENTATIONS

 Several formats are used to store data.

 Because a computer uses binary numbers all these formats are
patterns of 1’s and 0’s.
 These binary digits are called BITS.
 In Computer circuits, 0’s and 1’s are voltage levels where a 0 is
low voltage / OFF and a 1 is high Voltage /ON

These formats fall in two main categories

1. Number Formats: They store only numbers; There are
three number formats:
 Integer or Fixed point Formats.
 Floating Point Formats
 Binary Coded decimal (BCD)

2. Alphanumeric Codes: These store both numbers and

characters including the alphabetic characters.

NUMBER FORMATS
Integer Formats
Human beings are trained to understand decimal system.
e.g. 5437 = 5000 + 400 + 30 + 7 = (5 * 103) + (4 * 102) + (3 * 101) + (7 * 100)

In Binary
11011 = (1 * 24) + (1 * 23) + (0 * 22) + (1 * 21)+ (1 * 20) = 16 + 8 + 0 + 2 + 1 = 2710

Horner’s Rule: Used to convert binary numbers to decimal.

e.g. 101101 = (1 * 25) + (0 * 24) + (1 * 23) + (1 * 22) + (0 * 21) + (1 * 20)
= 32 + 0 + 8 + 4 + 0 + 1 = 4510
Using Horner’s Rule: ((((1 * 2 + 0)2 +1)2 + 1)2 + 0)2 + 1 = 4510
 2

 To convert from decimal to binary you perform successive

divisions.
 e.g. 4510 = 1011012; 13710 = 10010012

Hexadecimal
It has 15 digits 0 – 15
Decimal Hexadecimal Binary Octal
0 0 0000 0
1 1 0001 1
2 2 0010 2
3 3 0011 3
4 4 0100 4
5 5 0101 5
6 6 0110 6
7 7 0111 7
8 8 1000 10
9 9 1001 11
10 A 1010 12
11 B 1011 13
12 C 1100 14
13 D 1101 15
14 E 1110 16
15 F 1111 17
16 10 10000 20

It’s easier to represent numbers in hexadecimal than in binary.

e.g. To convert 1100110112 to Hexadecimal
(1 * 28)+ (1 * 27) + (1 * 24) + (1 * 23)+ (1 * 21)+ (1 * 20)
256 + 128 + 16 +8 + 2 + 1 = 41110

411 / 16 = 25 rem 11 B
25/16 = 1 rem 9 9 => 41110 = 19B16

 Each Hexadecimal digit can be represented by a unique

combination of 4 binary bits
 = > 1 1001 1011 = 0001 1001 1011
1 9 B
 To convert 1C2E16 to decimal you expand.
 To convert 1579710 to hexadecimal you perform successive
divisions.
 3

Octal System
Each octal digit can be represented by a unique combination of three
bits.
e.g. to convert 1100110112 to base 8 first covert to decimal then perform
successive divisions of 8 on the decimal number.
1100110112 = 41110
411/8 = 51 rem 3
51/8 = 6 rem 3 => 1100110112 = 41110 = 6338

1010110001102 = 101 011 000 110 = 53068

= 1010 1100 0110 = AC616
15738 = 001 101 111 011
= 0011 0111 1011 = 37B16
A74816 = 1010 011 0100 1000 =
= 001 010 011 101 001 000 = 1235108

In decimal you can expand numbers with fractions. E.g.

631.25 = (6 * 102) + (3 * 101) + (1 * 100) +(2 * 10-1) +(5 * 10-2)
Similarly in binary;
101.11 = (1 * 22) + (0 * 21) + (1 * 20) + (1 * 2-1) + (1 * 2-2) = 4 + 0 + 1 + ½ + ¼ = 5.7510

 If a decimal number is given the binary equivalent of the integer

portion is obtained as usual but the fraction part is obtained by
successively multiplying by 2.
 e.g. 13.6875;

13 = 1101 1 0 1 1
.6875 * 2 = 1.375
.375 * 2 = 0.75
.75 * 2 = 1.5
.5 * 2 = 1.0
=> 13.6875 = 1101.1011
Similarly 150.312510 = 10010110.01012

 If a binary number contains digits to the right of the decimal point

we convert them by starting at the binary point and move to the
right.
 4

e.g. 11.10100110112 = 011 101 001 101 100 = 3.51548

= 0011 1010 0110 1100 = 3.A6C16

Similarly
5.1458 = 101 001 100 101 = 0101 0011 0010 1000 = 5.32816
 Just like in Base 10 the decimal point can be moved by multiplying
by the appropriate power of the base.
e.g. 101.11 = 1011 * 2-2 = 0.1011 * 23

 Horner’s Rule can also be applied to numbers with fractions

e.g. 0.0101 = 0 + (0 * 2-1) + (1 * 2-2) +(0 * 2-3) +(1 * 2-4) = ¼ + 1/16 = 5/16 = 0.3125

Using Horner’s rule

0.5(0 + 0.5(1+0.5(0+0.5 * 1))) = 0.3125

Binary Arithmetic
110101 101101 10110 11111101 / 1011
+ 10010 -100110 * 1011
1000111 111

BA41 BA41
+ 14AF -14AF
CEF0 A592

REPRESENTATION OF NUMBERS IN COMPUTERS

Because the storage capacity of a computer’s memory and control
circuitry is finite, it is necessary to group the bits it operates on into finite
sequences. The size of bit groupings is an important factor in designing
a computer.
Once a group of bits is decided upon there are only finite numbers of
integers that can be represented by the group.
If there are n bits in a group the number of possible combinations of 0’s
and 1’s is 2n.
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If the bits are used to represent non–negative integers, integers 0

through 2n - 1 can be represented.
With 8 bits integers 0 – 255 can be represented.

We usually estimate high powers when the groups are large where n
may be 24, 32, 64 etc.
210 = 1024 = 103
e.g. 236 = 26.230 = 26(210)3 = 26(103)3 = 64 * 109

If the result of any operation does not fit into the number of bits reserved
for it an overflow is said to occur.
All the 4 arithmetic operations can cause an overflow.
360 + 720 – 300 = 360 + (720 – 300) and (360 + 720) – 300

SIGNED INTEGERS
Normally a negative number is written by writing its magnitude and then
placing a negative sign to the left of the magnitude of the number.
 A computer element can take only a 0 or 1; so a minus sign must
be represented by a 0 or a 1.
 If a number is to be stored in n bits, the magnitude is placed in the
n – 1 right most bits and the MSB represents the sign.
 A negative number is represented by a 1 and a positive number by
a 0.
 Such a format is called the Sign Magnitude Format.
In this format there is a difference between – 0 and + 0 but they both
have the same magnitude.

 The range of integers that can be expressed in a group of 8 bits is

from – (27 – 1) = -127 to (27 – 1) = +127
 6

 In general a d bit binary sign magnitude representation in which the

first bit represents the sign has a range of
– (2d-1 – 1) to + (2d-1 – 1).

In an 8 bit signed magnitude format, numbers

001010112 = + 4310 10101011 = -4310
011111112 = + 12710 11111111 = -12710
000000002 = + 0 10000000 = -0

To add two sign magnitude numbers, we follow the usual addition rules.
 If the sign differs we subtract the smaller number from the larger
number and give the result the sign of the larger number.
 If the signs are the same we add them and we give the result the
same sign.

 +5 + -7 = 10000111 -5 + -7 = 10000101
- 00000101 - 10000111
10000010 (-2) 10001100 (-12)

COMPLEMENTS
They are used to simplify subtraction & logical operations.
Consider numbers –1000 to 999 and let X be any number in that range.
The 4 digit 10’s complement of X is defined as 10 4 – X
If X = 0572, the 4 digit 10’s complement of X is 10000 – 0572 = 9428

Consider the addition 0557 + - 328 = 229

The 10’s complement of 328 = 104 – 328 = 9672
Add 0557 The 10’s complement is used to represent its negative value
+ 9672
1 0229 Only 4 of the significant digits are saved.
This one is lost
0557 + - 725 => 104 – 725 = 9275 = > 0557 +9275 = 9832
 7

(i) A 9 in the most significant Digit indicates that the sum is negative.
If the magnitude is wanted the 10’s complement of the sum is taken.
i.e. 104 – 9832 = 0162
(ii) N.B. The most significant digit is reserved to represent the sign
leaving 3 digits for the magnitude.

2’s Complement
The d digit 2’s complement of a d bit binary integer N is equal to
2d – N where the subtraction is done in binary.

=> The eight bit 2’s complement of an 8 bit binary number 000000101
is 100000000 – 00000101 = 11111011

 Subtraction of 01101010 – 01011011 = 00001111

 Using 2’s complement, the complement of 01011011 = 100000000 –
01011011 = 10100101
 01101010
+ 10100101
1 00001111
1 is lost
The 2’s complement may also be computed by applying the following
rules.
(1) Invert the bit values; the result is called one’s complement.
(2) Add 1
e.g. for N = 00000101 Invert 11111010 + 1 = 11111011

1710 = 00010001 Invert 11101110 + 1 = 11101111 = -17

11910 = 00010001 Invert 10001000 + 1 =10001001 = -119

N.B. Note the difference between the sign magnitude representation and
the 2’s complement representation.

Rules to convert to decimal:

(i) If a number is positive (beginning with a 0), convert it to
base 10 directly as usual.
 8

(ii) If it is negative (begins with 1) get its 2’s complement and

convert it to base 10.
e.g. to convert a 2’s complement number 11111001 to decimal:
 It is a 2’s complement number; it is negative because it
begins with a 1
 Get its complement ; i.e. 11111001 Invert 00000110 + 1 =
00000111 = - 7

Addition of 2’s Complement Binary Integers:

Note that the left most bits are not treated separately as in signed
magnitude numbers.
(a) 7 00000111 (b) -7 11111001
+5 00000101 +5 00000101
12 00001100 -2 11111110

(c) -7 11111001 (d) 7 00000111

+- 5 11111011 + -5 11111011
-12 1 11110100 2 1 00000010
The carry is discarded

Overflow in 2’s complement:

An overflow in 2’s complement occurs when:
(i) The sign of the result differs from the sign of the
common numbers being added OR
(ii) There is a carry into but not out of the MSB OR
(iii) There is a carry out of but not into the MSB.
e.g. 126 01111110 -126 10000010
+ 5 + 00000101 +-5 11111011
131 10000011 -131 01111101

FLOATING POINT FORMATS

It is a format for storing numbers given in scientific notation inside the
computer. This helps to handle very large and very small numbers. It
 9

also helps to reduce leading and trailing zeros. It is written in the form
Fraction * baseexponent
e.g in base 10 0.000000357 = 0.357 * 10-6 , 625000000 = 0.625 * 109

The fraction part is sometimes called the significand and the exponent
the characteristic.
A floating point format is designated by:
(i) The base
(ii) The number of bits reserved for the exponent
(iii) The number of bits reserved for the fraction
(iv) The method for storing the sign and magnitude of
the exponent
(v) The method for storing the sign and magnitude of
the fraction.
(vi) The order in which the two signs and the two
magnitudes are to occur.
The combination of the above factors for a given computer depends
upon the designer.

The Typical floating Point Format:

Sign of Magnitude of Exponent Sign of Magnitude of fraction

Exponent fraction

1 bit------N bits------------- >< 1 bit > ------------M bits--------

 Although a base is chosen, it never appears in the format; once
chosen it is fixed. Bases are always powers of 2, 8, and 16.
 1 bit is needed for each sign
 The total number of bits therefore in the FPF is N + M + 2 where N
= bits reserved for the magnitude of the exponent and M = bits
reserved for the magnitude of the fraction.
Designers usually determine
 10

i. The resolution (number of bits reserved for the magnitude of the fraction) that
the system must be able to accommodate and
ii. The largest and smallest non-zero magnitude that the system must
be able to handle.
If base 2 is assumed the largest number that can be stored using a
N
floating point format is approximately 2 2-1 where N = number of bits
reserved for the exponent.

If N = 7 the largest number is approximately

2127 = 27(210)12 = 128 * 1036 = 1038 and the smallest is 2-126 = 10-38
 If an operation results in a number that is so large that the
maximum size of the exponent is exceeded an exponent
overflow is said to occur.
 Similarly if the exponent is negative and the magnitude becomes
too large, then an exponent underflow occurs.
 If N + 1 bits are reserved for the exponent and the sign, the offset
or bias chosen = 2N and the format is called the excess 2N format
 If N = 7 the offset = 2 7 = 128 = 10000000 2 and the format is called
the excess 128 format.
 When using the excess format the exponent is obtained from the
quantity by subtracting the offset.
 In excess 128 format, the number 01111110 = 126 implies that the
exponent = -2.
 In Excess 2N format a 1 in the MSB represents a positive exponent
and a 0 in the MSB represents a negative exponent.

The Typical 32 bit floating Point Format:

Base 2 Exponent Sign of Magnitude of fraction

In Excess 128 fraction
------8 bits-----1 bit->---------------23 bits--------------------------
 11

------8 bits---------- < 1 bit >----------------------23 bits---------------------------

Consider a number –13.6875 = - 1101.10112 = - 0.11011011 * 24

 The Exponent in excess 128 = 128 + 4 = 132 = 100001002
 Sign of the fraction is negative => 1
10000100 1 1101101100000000……
Exponent sign fraction = 84ED80000
 To reverse consider a number 7E5C0000
 => Exponent = 7E = 01111110 = 126 => 126 – 128 = -2
5C = 0 .101 1110 = > 0.101111 * 2-2 = 0.00101112 = 0.179687510
Sign of fraction

Steps in Arithmetic
1. Pre-normalisation if the operands are not normalized.
2. Alignment
3. Post normalization of the result.

Examples
(1) 826013AC Alignment 826013AC
+8040AB04 82102AC1
82703E6D

(2) 83600000 No Alignment

+83C00000
83200000 normalisation 82400000

(3) 82600000 No Alignment

x 85D00000
87BC0000 normalisation 86F80000

The IEEE/INTEL 32 bit floating Point Format:

It has 2 forms; the single precision and the double precision format
where N = 127 and 1023 respectively.
Sign of Base 2 Exponent Magnitude of fraction
fraction In Excess 127

- 1 bit-> --------8 bits--------------------------------23 bits---------------------------

Sign of Base 2 Exponent Magnitude of fraction

fraction In Excess 1023
 12

-1 bit->--------11 bits----------------------------52 bits------------------------------

e.g. –5.375 = -101.011 = -1.01011 * 22

Exponent = 2 + 127 = 129 = 10000001
1 10000001 01011 ….. = C0AC0000

Conversely 3E600000 = 0011 1110 0110 0000 00000 …

=>Exponent = 01111100 = 124 – 127 = -3
=>Fraction = 0.11
Significant = 1.11 * 2-3 = 0.00112 = 0.2187510

Examples
(1) 40700000 (2) 40C00000 No Alignment
+C0580000 + C0800000
40180000 3EC00000 40C00000 40000000

(3) 41380000 (4) C0A80000

*3F400000 / 40E00000
410A0000 BF400000

BINARY CODED DECIMAL (BCD)

In BCD each figure of the number to be coded is represented by its 4 bit
binary equivalent e.g.
8159 = 1000 0001 0101 1001
There are two BCD formats.
1. Packed (Condensed) BCD: In this format each figure occupies
half a byte; e.g. 341 = 0011 0100 0001
2. Extended (unpacked) BCD: Each decimal figure is represented
by a byte. In this case the first 4 bits of a byte can be filled with
zeros or ones depending on the manufacturer, e.g.
341 = 00000011 00000100 00000001

 Hardware designed for BCD is more complex than that for binary
formats. E.g. 16 bits are used to write 8159 in BCD while only 13
bits (1111111011111) would be required in binary.

The advantage of BCD format is that it is closer to the alphanumeric

codes used for I/Os.
 13

Numbers in text data formats must be converted from text form to binary
form. Conversion is usually done by converting text input data to BCD,
converting BCD to binary, do calculations then convert the result to BCD,
then BCD to text output.
To convert a BCD number to binary, multiply consecutively by 10 =
10102
e.g. 82510 = 1000 0010 0101
((1000 * 1010) + 0010)1010 +0101 = 1100111001.
The reverse conversion is done by successive divisions by 10 (1010 2)
then using the 4 bit remainder as the BCD digit, e.g. Using the above
example:
1100111001/1010 = 1010010 rem 0101; 1010010/1010 = 1000 rem 0010
 1000 0010 0101
Because only 10 of the 16 bit combinations are needed to represent the
decimal digits, any 2 of the remaining combinations can be used to
represent positive and negative signs.
The four bit combinations representing the sign can appear either to the
left or to the right of the combinations.
The signs often used are 1100 for positive and 1101 for negative.
e.g. –34 = 0011 0100 1101; +159 = 0001 0101 1001 1100

BCD addition can be done by successively adding the binary

representation of the digits and adjusting the results.
The adjustment rule is: If the sum of 2 digits is > 9, add 6 to the sum.
1748 0001 0111 0100 1000
+ 2925 0010 1001 0010 0101
4673 0100 0000 0111 1101
0110 0110
0100 0110 0111 0011

ALPHANUMERIC CODES
It is the assignment of bit combinations to the letters of the alphabet,
decimal digits 0 – 9, punctuation marks and several special characters.
The two most prominent Alphanumeric Codes are:
 14

1. EBCDIC (Extended Binary Coded Decimal Interchange Code); this

is mostly used by IBM.
2. ASCII: (American Standard Code for Information Interchange);
used by other manufacturers.
ASCII represents each character with a 7 bit string
 The total number of characters that can be represented is 2 7 = 128
e.g. J O H N = 4A 6F 68 6E = 1001010 110111 1101000 1101110
Since most computers manipulate an 8 bit quantity, the extra bit when 7
bit ASCII is used depends on the designer. It can be set to a particular
value or ignored.

EXPRESSION EVALUATION
 When writing an algebraic expression we use parenthesis to
indicate the order in which the elementary operations are to be
performed.
 If the ordering is specified by using parenthesis the expression is
said to be in an infix notation because the operators are placed
between their operands.
 The postfix or reverse Polish Notation places operators after the
operands.
e.g.: A/(B + C) = ABC+/

(A + B) * [C * (D + E) + F] = AB+CDE+*F+*

a + b * c(d + e) = abc * de + *+ fgh - * /

f * (g + h)

Evaluating Postfix Expressions

Uses LIFO Structure (Stack)
AB*CDE/-+ = (A * B) + (C – D/E)
Prefix
A/B^C + D*E – A*C = +/A^BC – *DE * AC OR -+ / ^ BC * DE * AC
 15

ASCII CODE
ASCII HEX Control ASCII HEX Control ASCII HEX Control
Char Code Character Char Code Character Char Code Character
NUL 00 Null + 2B V 56
SOH 01 Start heading , 2C W 57
STX 02 Start text - 2D X 58
ETX 03 End text . 2E Y 59
EOT 04 End transmission / 2F Z 5A
ENQ 05 Inquiry 0 30 [ 5B
ACK 06 Acknowledgment 1 31 \ 5C
BEL 07 Bell 2 32 ] 5D
BS 08 Backspace 3 33 ^ 5E
HT 09 Horizontal tab 4 34 _ 5F
LF 0A Line feed 5 35 ‘ 60
VT 0B Vertical tab 6 36 a 61
FF 0C Form feed 7 37 b 62
CR 0D Carriage return 8 38 c 63
SO 0E Shift out 9 39 d 64
SI 0F Shift in : 3A e 65
DLE 10 Data link escape ; 3B f 66
DC1 11 Device control 1 < 3C g 67
DC21 12 Device control 2 = 3D h 68
DC3 13 Device control 3 > 3E i 69
DC4 14 Device control 4 ? 3F j 6A
NAK 15 Neg. acknowledge @ 40 k 6B
SYN 16 Synchronous/Idle A 41 l 6C
ETB 17 End trans. Block B 42 m 6D
CAN 18 Cancel data C 43 n 6E
EM 19 End of medium D 44 o 6F
SUB 1A Start special seq. E 45 p 70
ESC 1B Escape F 46 q 71
FS 1C File separator G 47 r 72
GS 1D Group Separator H 48 s 73
RS 1E Record separator I 49 t 74
US 1F Unit separator J 4A u 75
SP 20 Space K 4B v 76
! 21 L 4C w 77
“ 22 M 4D x 78
# 23 N 4E y 79
$ 24 0 4F z 7A
% 25 P 50 { 7B
& 26 Q 51 | 7C
‘ 27 R 52 } 7D
( 28 S 53 ~ 7E
) 29 T 54 DEL 7F Delete rubout
* 2A U 55
 16

LOGIC CIRCUITS
 Digital computers are based upon electronic components
whose inputs and outputs are at anyone point in one of two
possible states; the states are mostly voltage levels;
 One voltage level can be denoted by a 1 and another by a 0.
 If the higher voltage is associated with 1, the circuit is said to
be based upon positive logic. If the lower voltage is associated
with a 1, the circuit is said to be based on negative logic.
 A variable that can take on two states e.g. (0, 1, True, false;
on/off) is called a logical variable.
 A circuit whose inputs and outputs are described by logical
variables is called a logical network.
INPUTS OUTPUTS
Logical Network

Logical Variables Logical Variables

There are two types of logical networks:

1. Combinatorial networks: Their outputs depend on the current
inputs.
2. Sequential Networks: Their outputs depend on both the current
state of the network as well as the inputs.

Logic Gates
A combinatorial circuit with only one output is called a logic gate. They
accept logical values at their inputs and they produce corresponding
logical values at their outputs.
 A table listing all the outputs for the various inputs is called a
truth table (derived from the True/ False logic in mathematics.)
 All combinatorial circuits can be constructed from the
elementary logic gates.
 17

The most common 7 logic gates are:

1. The inverter(NOT) Gate:
When the input is 1 the output is 0 and vice versa.
_
A A INPUT OUTPUT
_
A A
0 1

1 0

2. The AND Gate:

A
A AND B
B AB

Input Output
A B AB
0 0 0
0 1 0
1 0 0
1 1 1
The output is 1 if all the inputs are 1’s
.
3. The OR Gate:
A
A OR B
A+B
B

Input Output
A B A + B
0 0 0
0 1 1
1 0 1
1 1 1

The output is 0 if all the inputs are 0’s.

If an inverter is combined with another logic gate, the presence of the

inverter is indicated by placing a small circle at the affected input or
output.

4. The NAND (NOT AND) Gate:

 18

A NAND B
A __
B AB

Input Output
__
A B AB
0 0 1
0 1 1
1 0 1
1 1 0

The output is 0 if all the inputs are 1’s.

5. The NOR (Not OR) Gate:

A A OR B
B _____
A+B

Input Output
____
A B A+B
0 0 1
0 1 0
1 0 0
1 1 0
The output is 1 if all the inputs are 0’s.

6. The EXCLUSIVE OR Gate:

A A Excl OR B
B A + B

Input Output
A B A + B
0 0 0
0 1 1
1 0 1
1 1 0
The output is 0 if all the inputs are the same.

7. The EXCLUSIVE NOR Gate:

A Excl NOR B A
______
A + B B

Input Output
 19

_____
A B A +B
0 0 1
0 1 0
1 0 0
1 1 1
The output is 1 if all the inputs are the same.

Complex Logic gates

Complex logic circuits can be built by combining several of the
elementary logic gates.
A graphical illustration of a logic circuit is called a logical diagram.

C _
AC + BC

Two logic circuits are said to be equivalent if they have exactly the same
input /output relationship.
One way to prove equivalence is to compare the truth table outputs of the
two circuits.
A

_
(A + B) C
C

_ _ _ _ _
A B C B AC BC AC + BC A+B (A + B)C
0 0 0 1 0 0 0 1 0
0 0 1 1 0 1 1 1 1
0 1 0 0 0 0 0 0 0
0 1 1 0 0 0 0 0 0
1 0 0 1 0 0 0 1 0
1 0 1 1 1 1 1 1 1
1 1 0 0 0 0 0 1 0
1 1 1 0 1 0 1 1 1

To try Circuits for AB(C+D) and (ABC + ABD) and their Truth Tables.
X = AB + ACD + ACEF + ACEG
A A B C D E F G
 20

B
C
D
E
F
G

X
(Causes minimum delay)

Causes maximum delay

X minimum number of inputs

BOOLEAN ALGEBRA
It is a mathematical structure that consists of a set containing only a 0
and 1, the unary operator (complementation) and the binary operation of
addition and multiplication. Subtraction and Division are not defined in
Boolean algebra. This branch of mathematics was developed by George
Boole in 1847.
Some of the equivalencies mostly frequently used in reducing Boolean Expressions
A = A
AA = A
A+A = A
A.0 = 0
A+0 = A
A.1 = A
A+1 = 1
_
A.A = 0
_
A+A = 1
AB = BA
A+B = B+A
(AB)C = A(BC)
A + (B + C) = (A + B) + C
A(B + C) = AB + AC
 21

(B + C)A = BA + CA
____ _ _
A+B = AB
___ _ _
AB = A+B
_
AB + AB = A
A + AB = A
_
(A + B)B = AB
_
(A + B) (A + B) = A
(A + B) (A + C) = A + BC
A(A + B)= A
_
AB + B = A+B
_ _
AB + AB = A + B
__
AB(A + B) = A + B

e.g.
__
ABC + BC + AB
__
 C(AB + B) + AB
 _
 C(A + B) + AB (third equivalence from the bottom)
 _
 AC + BC + AB
 _ _
 AC + (A + A)BC + AB
 _ _
 AC + ABC + ABC + AB

 _
 AC(1 + B) + AB(C + 1)
 _
 AC + AB
_ _ _
ABC + ABC + ABC + ABC
_ _ _
 ABC + ABC + ABC + ABC + ABC + ABC
 _ _ _
 (A + A)BC + (B + B)AC + (C + C)AB
 BC + AC + AB

Digital Design Process

1. Determine all the input/output relationships that must be true for
the network being designed and put them in convenient tabular
form.
 22

2. Use the drawn up table to find Boolean expressions for each

output.
3. Simplify the expressions from 2 above
4. Use the expressions resulting from step 3 to develop the desired
logical diagram.

Three design tools have been introduced:

1. Truth Table (To define a logical network)
2. Boolean Expression (for minimization)
3. Logic diagram (For the actual design)
A designer must be able to convert from one form of a network’s
description to another.

Truth Table Boolean Logic

Expression Diagram

Example
Suppose that a three input network is needed that will output a 1 if the majority of the
inputs are 1’s otherwise the output is zero.

Step 1 (Draw a truth Table)

A B C X
0 0 0 0 X0
0 0 1 0 X1
0 1 0 0 X2
0 1 1 1 X3
1 0 0 0 X4
1 0 1 1 X5
1 1 0 1 X6
1 1 1 1 X7

Step 2 (Find the Boolean expression.)

There are two types of Boolean Expressions
(i) SUM OF PRODUCTS (SOP’s)
A product is 1 if and only if all of its factors are 1
A sum is 1 if at least one of its terms is a 1.
 23

_ _ _
X3 = ABC; X5 = ABC; X6 = ABC; X7 = ABC
X = X3 + X5 + X6 + X7
_ _ _
=> ABC + ABC + ABC + ABC

(ii) PRODUCT OF SUMS (POS)

A product is 0 if at least one of its factors is 0
A sum is 0 if all its terms are 0’s.
_ _ _
X0 = A + B + C X1 = A + B + C X2 = A + B + C X4 = A + B + C
_ _ _
X = X0X1X2X4 =>(A + B +C)(A + B + C)(A + B + C)(A + B + C)

Step 3 Simplify the expression

_ _ _
=> ABC + ABC + ABC + ABC = BC + AC + AB

Step 4 Draw the logic diagram.

A B C

BC

AC BC + AC + AB

AB

Minimisation of expressions using Karnaugh Maps

 The occurrence of a variable or its complement in an
expression is called a literal.
 A term in the SUM OF PRODUCTS that includes a literal for
every input is called a miniterm.
 A term in the PRODUCT OF SUMS that includes a literal for
every input is called a maxiterm.
_ _ _ _ _ _
e.g. in ABC + ABC + AC; ABC and ABC are miniterms, AC is not a
miniterm.
_ _ _ _ _ _ _ _ _
 24

Similarly in (A +B+C)(A+B+C)(A+C), (A +B+C) and (A+B+C) are

_
maxiterms, (A+C) is not.

A Karnaugh map is a truth table for a single output consisting of arrays of squares
where each square corresponds to a row of a truth table.
The symbols at the top represent the variables associated with the
columns and the symbols on the left represent the variables associated
with the rows.
The value of each output for each input is put in the corresponding
square.
For each 1 in the Karnaugh map there is a corresponding miniterm in the
output’s Sum of product expression and each 0 represents a maxiterm in
the Product of Sums expression.
Two inputs Three inputs Four inputs
A AB AB
0 1 00 01 11 10 00 01 11 10
0 0 2 0 0 2 6 4 00 0 4 12 8
B C 01 1 5 13 9
1 1 3 1 1 3 7 5 CD
11 3 7 15 11

10 2 6 14 10

Example 1
A B C X Using Boolean simplification:
0 0 0 0 _ _
0 0 1 0 ABC +ABC + ABC
0 1 0 0 _ _
0 1 1 1 ABC +ABC + ABC + ABC
1 0 0 0
1 0 1 0 = AB + BC AB
1 1 0 1 00 01 11 10
1 1 1 1 0 0 0 1 0
C 1 0 1 1 0

Look for adjacent groups that include 2 n miniterms where n is an integer.

The larger the group the greater is the reduction.
 25

Example 2
A B C X Using Boolean simplification:
0 0 0 0 _ _ _
0 0 1 0 ABC +ABC + ABC + ABC
0 1 0 0 _ _ _
0 1 1 1 ABC +ABC + ABC + ABC + ABC + ABC
1 0 0 0
1 0 1 1 = BC + AC + AB
1 1 0 1
1 1 1 1
AB
00 01 11 10
0 0 0 1 0
C
1 0 1 1 1

A function may be used to state where the output is 1 instead of drawing

a Karnaugh map. e.g. for the above example F(A,B,C) = (3,5,6,7)

Example 3
F(A,B,C) = (0,1,2,3,7) AB
_ 00 01 11 10
A 0 1 1 0 0 _
C A + BC
BC 1 1 1 1 0
AB AB
00 01 11 10 00 01 11 10
0 1 0 1 1 _ 0 1 0 0 1
C AC C
1 1 0 0 1 1 0 1 0 0

_ _ _ __
B + AC ABC + BC
AB AB
00 01 11 10 00 01 11 10
00 0 1 1 1 00
1 0 0 1
01 0 1 0 1 01
CD CD 1 0 0 0
11 0 0 0 1 11
1 0 0 1
10 0 0 0 1 10
1 0 0 1
_ _ __ _ __ _ _ _
ABC + ACD + AB AB + BC + BD

For some designs some input combinations cannot occur. Outputs

corresponding to these combinations are optional. These combinations
may be chosen to be either 0 or 1 as is convenient in the maximization
process.
 26

These outputs are represented by X’s in the Karnaugh Map and they
may or may not be included in the prime implicants.
They are called Don’t Care Cases denoted by the function d(A,B,C) =
(….)
AB
00 01 11 10
00 X

01 1
CD _
11 1 AB + AC

10 X 1 1

___ _ _
It is important to include the miniterm ABCD in C but not ABCD

Example
A network is needed that will output a 1 if the binary A 3A2A1A0 is greater
than 0 and less than 4.
Assume also the inputs are controlled by a rotary switch such that only
one input can be a 1 at any given time except when the switch position
will also allow all inputs to be 1.

A3 A2 A1 A0 X A3A2
0 0 0 0 0 00 01 11 10
0 0 0 1 1 00 0 0 X X
0 0 1 0 1
0 0 1 1 X 01 1 X X X
0 1 0 0 0 A1A0
0 1 0 1 X 11 X X 0 X
0 1 1 0 X
0 1 1 1 X 10 1 X X X
1 0 0 0 0
1 0 0 1 X
1 0 1 0 X _ _
1 0 1 1 X = A1A0 + A0A3
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 0
BINARY ADDER
A circuit for adding 2 1 bit quantities is called a half adder.
 27

A A B S C A B
+ B 0 0 0 0
Carry sum 0 1 1 0
1 0 1 0
1 1 0 1

A B C = AB
_ _
S = AB + AB = A + B

C
HA C S
S

Full Adder
For a 2 bit addition, addition of a higher order bit takes into account a
possible carry from the low order sum.
The adder that includes a carry input from a lower order sum is called a
Full Adder.
A B A B

FA
CO Ci

S
A B Ci S Co
0 0 0 0 0
0 0 1 1 0 Ci
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

_ _ _
Co = ABC +ABC + ABC + ABC
_ _ _
= C( AB +AB) + AB(C +C)
= C( A + B) + AB
Co S
__ _ _ __ _ _ _ __
S= ABC + ABC + ABC + ABC = A(BC + BC) + A(BC + BC)
_ ______
= A(B + C) + A(B + C) = A+ B + C
To build an adder of more bits, you just duplicate the full adders the
required number of times.
 28

Such a circuit is called a Ripple Carry Adder. The carry out bit is used
as a carry in into its left neighbour. The carry into the right most bit is set
to 0.

MULTIPLEXER (Data Selector)

It is a logical network capable of selecting a single set of data inputs
from a number of sets of inputs and it passes the selected inputs to the
outputs.
A multiplexer has 2 kinds of inputs, the control inputs and the data
inputs.
The control inputs serve to select which of the inputs in the data is to be
passed through to the outputs.
Ao An The simplest multiplexer is
the 2 to 1 multiplexer. It has
Control MUX(n) 2 data inputs, A and B, one
control input and one output
Output X.

When the control input P = 0, the output X is A and when P = 1, X = B.

P A B X _ _ _ _
0 0 0 0 X = PAB + PAB + PAB + PAB
0 0 1 0 _ _ _
0 1 0 1 = PA(B + B) + PB( A + A) A B
0 1 1 1 _
1 0 0 0 = PA + PB P
1 0 1 1
1 1 0 0
1 1 1 1

A 4 to 1 multiplexer
 29

It selects only one of the 4 inputs. It has 2 control lines to choose one of
the 4 possible inputs.
A B C D
P

X
In general for an n to 1 multiplexer, the inequality 2 K >= n must be
satisfied where k = number of control lines.

A Demultiplexer
It has 1 set of data inputs and two or more sets of outputs and a set of
control inputs whose purpose is to select the set of outputs to transmit.
The other outputs are 0.
Inputs P A X Y
0 0 0 0 _
Control 0 1 1 0 X = PA
DMUX(n) 1 0 0 0
1 1 0 1 Y = PA

outputs A

X Y

A comparator
 30

Compares two sets of inputs and outputs a 1 if the comparison is

satisfied. The comparisons are =,!=, >, >=, <, <=
Inputs

A B

The equality comparator

The design is based upon the XNOR gate which outputs a 1 if its inputs
are the same and a 0 if they are not equal.
B2B1B0 = A2A1A0
An Bn A1 B1 A0 B0

1 bit > comparator

X = 1 if A > B
_ A B
A B X => X = AB
0 0 0
0 1 0
1 0 1
0 0 0

2 bit > comparator X = 1 if A1A0 > B1B0 X

A1 A0 B1 B0 Xo :
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
Decoder
 31

Circuit whose outputs are miniterms of the inputs. Exactly only one
output is a 1 at any given time.
If n is the number of inputs and m the number of outputs then 2n >= m
e.g. if the binary number on the input lines is k then output line k will be 1
and all the others will be 0’s.
A1 A2 A3 X0 X1 X2 X3 X4 X5 X6 X7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
A3

A2

A1

X0 X1 X2 X3 X4 X5 X6 X7

The Encoder
The opposite of a decoder. Only one input can be a 1 (activated) at a
time. Its number in binary is presented as the output.
It has 2n inputs and n outputs.
A0 A1 A2 A3 X1 X2
1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
0 0 1 1 1 1

Inputs
A1 A2 A3 A4 A5 X1 X2 X3
1 0 0 0 0 0 0 1
0 1 0 0 0 0 1 0
0 0 1 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 0 0 1 1 0 1

X3 = A1 + A3 + A5 X2 = A2 + A3 X1 = A4 + A5
A1
 32

A2
A3
A4
A5

X3 X2 X1

Code Converters
They are electronic circuits whose purpose is to convert data from one
format to another.
Data in a computer system may take on several different forms as it
changes from one format to another.
e.g. the decimal input from a keyboard calculator must be converted into
BCD using an encoder.
The CPU’s output is in BCD and the decoder translates the BCD to a
special 7 segment display code by a decoder.

7 8 9
Encoder CPU Decoder

4 5 6

1 2 3

0
Decimal
Keyboard Display

The encoder circuit

The encoder has 10 active inputs and 4 outputs connected to input
lamps. The input 7 causes a BCD output of 0111.
 33

9
23 22 21 20
8 9 A
B
8 A
7 DECIMAL
D TO
7
6 BCD DECODER
6 B
5
5

4 4 C

3 3

2
2 D
1
1
0
0

a
0 A b a
c b
1 B d c
DECODER e d DISPLAY
1 C f e
g f
1 D g

f b
g

e c
d

A B C D a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 0 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 0 0 1 1

ROMS AND PLA’S

 34

ROM
Read Only Memory. The circuit is equivalent to a decoder that outputs all
possible miniterms of the inputs followed by an encoder.
The output combinations are permanently embedded in its circuitry and
the inputs serve to select one of these combinations. Each output is
obtained by disconnecting the OR inputs from the AND gates whose
miniterms are not to be included in the output.
Because a ROM must produce all the possible miniterms its decoder
portion is fixed by n. Its encoder portion however depends on both the
outputs and the way in which all the outputs of a decoder are used to
generate the final ROM outputs.
A1 DECODER ENCODER
A2 2n X1
miniterms Xn
An

Once the disconnections are made they cannot be changed. (ROM

nature). e.g to construct a 2 input ( A, B) three output (X, Y, Z) ROM such that
_ _ _ _
X = AB + AB; Y = AB + AB Z = AB + AB

A
These connections
B are always made

__ _ _
AB AB AB AB
These are
Selectively made

X Y Z
When a ROM is used as memory the inputs are the memory’s address
and the outputs are the contents of the address.
 35

PLA (Programmed Logic Array)

Similar to a ROM but does not output all the miniterms that will not be
needed in any of the outputs. i.e. the decoder does not necessarily
produce all the miniterms. For an n input network, we have <= 2 n AND
gates
DECODER ENCODER
A1 < 2n X1
A2 miniterms
Xn
An

e.g. a three AND gate PLA implementation of the ROM in the previous
example.
A

Both sets of connections

Are made selectively.
_ _
AB AB AB

X Y Z

PARITY GENERATION AND DETECTION

When transmitting or storing data errors may occur due to
electromagnetic noise or phyisical damage to the storage medium.
These errors need to be detected and possibly corrected. One method of
error protection is by adding an extra bit called a parity bit to the data bits
and it is set according to the following rules:
 36

An Even Parity bit is set if an odd number of 1’s occurs in the data bits;
otherwise it is cleared. Therefore, the total number of 1’s is even.
An Odd Parity bit is set if an even number of 1’s in the data bits occurs;
otherwise it is cleared. Therefore, the total number of 1’s is odd.

Assume that even parity is to be used and consider the situation of two
networks where the output from each network is 1 if there is an odd
number of input 1’s.

Output = 1 if and only if there is an odd number of input 1’s

for the individual network

Inputs Network 1

Inputs
Network2
Output = 1 if and only if the total number of
inputs 1’s is odd.

Parity Bit generation

Parity bit

Data Bits

Error Detection

1 if there is an error
0 if there is no error

Parity Bit

Data Bits

SEQUENTIAL LOGIC & COMPUTER CIRCUITS

 37

Combinatorial circuits have no memory, do not contain feedbacks and

they are time independent. They cannot therefore be used for storage.
Their outputs solely depend on their inputs. They have no intrinsic timing
control.
Sequential circuits have internal states that can be used to store
information and modify their inputs.
E.g.
(i) A simple counting device; its output depends on the
input signal that causes the output to increment and also on the
current count that was previously determined.
(ii) A memory circuit; the input causes the contents of
memory to be applied to the outputs.
Time in a sequential circuit takes on a significant role.

A sequential network is defined according to its inputs and outputs over

a period of time. The aid used in examining the time dependent aspect
of a sequential network is called a timing diagram.

Increasing Time

A begins in state 0, B and X begin in state 1.

Transition of A to 1 does not change X.
Transition of B from 1 to 0 causes X to change to 0.
 38

Transition of A from 1 to 0 does not affect X but the following transition

of A causes X to change to 1.
Output Y changes state 25 s after a change in X.
The S shaped curves indicate that the state of Y at a particular time is
not known but a change in state will occur. If it was a 0 it will change to 1
and vece versa.
Sequential networks are synchronised by a time standard called a clock.
A clock generates an evenly spaced train of pulses.
Time between consecutive pulses is called a period. The number of
periods per second a frequency.

Period

Elementary sequential circuits fall into a class of binary electronic circuits

known as multvibrators which may be astable, monostable or stable.

Astable multivibrators
The cannot maintain a fixed state but the keep on switching back and
forth between its states.

Monostable multivibrators
They can take on two states but are stable in only one of them. They can
only temporarily stay in the unstable state.

Bistable
They are stable in either of the 2 states and can therefore maintain either
state indefinetely.
 39

Flip Flops
They are bistable devices i.e. they are 2 state devices in nature. They
assume one of the 2 possible states and they will maintain that current
state until an external excitation causes it to change state.
They are devices used in sequential networks.
The most common flip-flops are the R-S, J-K, T, and the D flip flop.

The R-S flip flop (Reset –Set)

S
Q

C
_
Q

R
_
R S Q+ Q+
S FF Q Q 0 0 Q- Q-
C _ _ 0 1 1 0
R Q Q 1 0 0 1
1 1 - -

It has 3 inputs and 2 outputs.

A clock input synchronises the action of the flip-flop with its surrounding
_
network. S and R (Set / Reset Inputs). The two outputs (Q and Q) are
always in opposite states from each other. Because both R and S inputs
are ANDED with the clock, they have no effect on the state of the flip-
flop when the clock is in 0 state. The network is then stable. In this state,
_ _ _
if Q = 1, Q is = 0 and Q is maintained at 1. If Q is 1 Q = 0 and Q is
maintained at 1. If the clock is raised to 1 the network will not change if
R=S=0
_
If R = 1, S = 0 => Q = 0 and Q = 1
_
R = 0, S = 1 => Q = 1 and Q = 0
 40

Most significant changes occur when there is a clock transition.

_
If R = S = 1 => Q = Q = 1 is not a useful combination of inputs; this is not
defined in the table.
_
The subscripts Q- and Q- indicate outputs just before the clock
_
becomes 1 and the subscripts Q and Q+ show outputs just after the
+

clock becomes 1. When the clock is high (i.e. = 1) the output follows the
changes in the inputs.
R and S = 0 => no changes in outputs.If S is pulsed, Q will be set
_
(becomes 1) regardless of its previous state and Q will be cleared. =>
_
(becomes 0). If R is pulsed, Q is cleared (or reset) and Q will become 1.
S

Q
_
Q

Q +ve edge triggered

If the clock input is constant, the outputs will follow the changes in the
inputs at all times.
All clocked flip flops that react to their inputs anytime C = 1 are called
latches.
The R-S flip-flop is called a latch because it uses the clock inputs to
determine whether or not the inputs will be recognised.
If a flip-flop changes only at the very beginning (or the very end) of a
clock pulse it is called an edge triggered flipflop. They change state
only when there is a 0 to 1 transition at C (+ve edge triggered) or a 1 to 0
transition at C (-ve edge triggered)
 41

A change from 0 to 1 is a +ve transition and the +ve transition of a clock

pulse is called the leading edge.
A change from 1 to 0 is a negative transition and the negative transition
of a clock is called a trailing edge.

The J-K Filp Flop

It is an R-S flip flop that has been modified by feeding the outputs back
and ANDYING them with the inputs. It has the same behaviour like the
R-S flip flop except that the C = J = K = 1 combination is meaningful and
the results in the output states is reversed.

J Q
S
C C _
R Q
K

_
J K Q+ Q+
J FF Q _
C _ 0 0 Q- Q-
K Q 0 1 0 1
1 0 1 0
_
1 1 Q- Q-

The J-K flip –flop is constructed from an edge triggered R-S flip-flop
otherwise the C=J=K=1 state would be unstable.
A modification of the J-K flipflop is the master-slave J-K flip-flop. The
master responds to the +ve level of the clock ; the slave responds to the
–ve level of the clock.
By properly adjusting the trigger levels on the master and slave the slave
can be disconnected from the master while the master is being set and
the master can be disconnected from the inputs while the slave is being
reset.
 42

J
S S
C C C
R R
K

With a simple J-K flip-flop an input transition while it is being triggered

can cause the output to be momentarily unstable.
The isolation of the master from the slave while the master is being set
eliminates this problem and guarantees a clear switching action at the
output.
Toggling (change of state) occurs when the clock pulse changes from
high to low.
The J-K flip-flop is –ve edge triggered flip-flop. i.e. it takes a low to
activate the clock.

The T Flip –Flop (Toggle)

It has only one input. Its output states are reversed each time the input is
pulsed.
FF
T
S Q
C C _
T Q+ Q+
_
R Q _
0 Q- Q-
_
1 Q- Q-

It is used in the design of counters.

A T flip flop can be obtained from a J-K flip flop by permanently applying
1’s to the J and K inputs. The R-S flip flop must be edge triggered.

The D flip flop (Data)

 43

It has 2 inputs, a clock input and an input labelled D such that the Q
output is equal to the D input whenever the clock input is set to 1;
otherwise it is not affected by the D input.
D S
Q D FF
C
C _
R Q C
_
D Q+ Q+
0 0 1
1 1 0

It is used in sequential networks like in registers . It is easily constructed

from the R-S flip flop by letting the D input be S input and connecting R
to D through an inverter.
C

Latch Q

+ve edge triggered

-ve edge triggered

Clear and Preset Inputs

Flip flops can clear or set the Q output irrespective of the state of the
other inputs. The clear input clears Q and the Preset input sets Q

D FF
Preset
J
C
C Clear
K
Clear

A D flipflop with a A J-K flipflop with clear

Clear feature and preset inputs

The indicates a negative logic nature whereby a 0 input

initiates the action instead of a 1 input.
 44

REGISTERS
A number of flipflops placed in parallel to form several bits of storage.
Each flip flop is capable of storing 1 bit of information. Registers are
used anywhere in the computer where it is necessary to store a number
of bits.
e.g. a 4 bit register constructed from four D flipflops
D3 D2 D1 D0

D Q D Q D Q D Q

_ _ _ _
C Q C Q C Q C Q

Load

Read

Q3 Q2 Q1 Q0

The common clock load permits new information to be loaded.

The common Read line and associated AND gates provide a controlled
Read out mechanism.
If n flip flops are used, the register is said to have a length of width n.
The currently stored data are the current states of the flip flops and can
be monitored at the Q outputs.
In general a register consists of a group of flipflops and gates. The flip
flops hold the binary information and the gates control when and how
new information is transferred into the register.
Transfer of new information into the register is known as loading the
register.
If all bits of the register are loaded simultaneously with a common clock
pulse transition we say that the loading is done in parallel.
 45

Shift registers
Frequently it is necessary to shift the bits in a register either to the left or
to the right. A register that is capable of performing this function is called
a shift register.
Shifting bits is necessary because some registers must be able to re-
arrange their contents. e.g. if the flip flops in an 8 bit register contain
0 1 1 0 0 1 0 1 and a 1 bit left shift operation is performed, the
new contents of the register will be 1 1 0 0 1 0 1 0.
After a 1 bit right shift the new contents would be 0 0 1 1 0 0 1 0
For the left shift the left most bit is lost and 0 is inserted on the right.
If the left most bit is brought around and put in the right bit during a left
shift, or the right most bit is put in the left bit during a right shift the
operation is called a rotation.

RLC (Rotate Left)

The content of the accumulator is rotated left one position. The low order
bit and the carry flag are both set to the value shifted out of the high
order bit position.
0 0 0 0 0 1 1 1

RRC (Rotate Right)

The content of the accumulator is rotated right one position. The high
order bit and the carry flag are both set to the value shifted out of the low
order bit position.
0 0 0 0 1 1 1 1

RAL (Rotate Left through carry)

 46

The content of the accumulator is rotated left one position through the
carry flag. The low order bit is set equal to the carry flag and the carry
flag is set to the value shifted out of the high order bit position.
0 0 0 1 0 1 1 1

RAR (Rotate Right through carry)

The content of the accumulator is rotated right one position through the
carry flag. The high order bit is set equal to the carry flag and the carry
flag is set to the value shifted out of the low order bit position.
0 0 0 1 1 1 1 1

E.G
Consider initially A = 01101001 and the carry flag (c) = 1
RLC 11010010 RRC 10110100
RAL 11010011 RAR 10110100

Multiplication by 2 has the same effect as shifting a binary number left by

1 bit and another way of performing a left shift is to add the A register to
itself.
One way of programming the multiplication of two single precision
integers is to zero the pair of registers that will hold the result and
successively examine the bits of the multiplier starting with the least
significant bit. If the bit is 1 the multiplicand is added to the product
register pair otherwise no addition is done; then the multiplicand is
shifted one to the left and the next bit in the multiplier is tested. The
process is continued until all the multiplier bits have been examined.
Shift registers are classified according to their inputs and outputs. Both
the input and output may be classified as serial or parallel.
 47

Serial input is one for which the input arrives 1 bit at a time, and each
time a bit arrives, the register is shifted by 1 to accommodate the new
bit.
A parallel input is one for which the inputs are all loaded at the same
time.
Serial and parallel outputs are similarly defined.
Shift registers are used in
 Interfaces for changing the form of data that are to be transmitted
or are being received.
 Processing elements (microprocessors) for performing packing,
unpacking, bit searching and arithmentic operations.

Data Transmission
Shift registers are used most importantly in converting different types of
data communications.
Most computers include 2 types of binary data transmission.
If n bits are to be transmitted they could be sent simultaneously over n
signal paths. This is called parallel data transmission.
Alternatively they could be sent one after the other over 1 signal path.
This is called Serial Data transmission.
In parallel transmission, the number of lines employed is greater than the
number of bits. The extra lines are the control lines that are used by the
transmitting device to signal to the receiving device when data is ready
to be read and the receiving device to signal to the transmitting device
that the data has been read.
The passing back and forth of signals on the control lines during
transmission is called handshaking.
 48

Sometimes one of the control lines transmits clock pulses and the timing
of all the other signals is controlled by these pulses. Data transmission in
this case is said to be synchronous.
A transmission that is not controlled by a common clock signal is said to
be asynchoronous.
In serial transmission data is sent over a single line in sequential fashion.
For each character the transmitter and receiver divide the period of time
used to transmit data into sub intervals. One subinterval is a bit.
Control lines may again be used for handshaking or synchronisation.
Serial transmission is often made over a single pair of lines and the
beginning and end of transmission are marked by special bits called a
start bit, a stop bit and parity bits.
A character transmitted in the asynchronous serial mode consists of the
following 4 parts:
1 A start bit
2 Five to 8 data bits
3 An optional even / odd parity bit
4 1 or 2 stop bits.

A timing diagram to transmit an ASCII character E = 45 with 1 start bit and 1 stop bit

1 0 1 0 0 0 1 0
Start bit Data bits Stop bit

At the end of each character the signal always goes to a logical 1 for the
stop bit. It remains 1 until the start of the next character which begins
with a start bit at logical 0.
The logical 1 and logical 0 are respectively knows as the mark and
space.
 49

Advantages of Parallel transmission

Higher information transfer rate can be attained.

Disadvantages
More wires (or communication channels) are needed.

Whenever distance is a factor serial transmission is chosen.

If the transfer rate must be high parallel communication may be required.
Because a computer system includes both types of data
communications, it must also include means of converting from one type
to another.

Serial to parallel converter

A negative logic reset precedes each data character thus clearing the
shift register.
Each clock pulse loads a data bit until the register is full. After the 4 bit
character is loaded it can be read from the parallel output lines D 0 – D3
Parallel Output

D0 D1 D2 D3

Serial D Q D Q D Q D Q
Input
_ _ _ _
Clock C Q C Q C Q C Q
clear clear clear clear

Reset

Parallel to Serial converter

Once data is made available at D 3 – D0 it can be loaded into the shift
register by load signal. The 4 clock pulses are used to cause the 4 bit
character to appear sequentially at the output
 50

D0 D1 Parallel Input D2 D3

Enable Input Preset Preset Preset Preset Serial

0 J Q J Q J Q J Q output
Clock C _ C _ C _ C _
1 K Q K Q K Q K Q
clear clear clear clear

Reset

Binary Counters
They are circuits used to count and store the number of pulses arriving
at its input.
Counters are found in almost all equipment containing digital logic.
They count the number of occurrences of an event and they are useful
for generating timing signals to control the sequence of operations in
digital computers.
A counter that follows the binary number sequence is called a binary
counter. An n bit binary counter is a register of n flip flops and associated
gates that follows a sequence of states according to the binary count of
n bits from 0 to 2n – 1
e.g. a 4 bit counter capable of counting from 0000 through 1111.
FF FF FF FF
Q Q Q Q
Enable Input T _ T _ T _ T _
Q Q Q Q
clear clear clear clear

Reset

Q0(20) Q1(21) Q2(22) Q3(23)

The T flip flops are negatively edge triggered.

Incrementing takes place on the trailing edge of the input pulses.
 51

The enable input provides a means of turning the counting process on

and off without removing the clock signal from the flip flop and the reset
input clears the counter.
Going through a sequence of binary numbers e.g. 0000 0001, 00010
etc, the lower order bit is complemented after every count and every
other bit is complemented from one count to the next if all its lower bits
are equal to 1.
A sixteenth pulse has the same effect as the Reset input for it clears all
the 4 bits.
A counter circuit employs flip flops with complementing capabilities like a
J-K flip flop when C = J = K = 1 or a T flip flop.

(Read about a decade counter (1001)

Serial Adders and subtractors

The combinatorial adders and subtractors are parallel devices because
they receive all the bits in the operands in parallel.
It is possible to design serial arithmetic circuits that receive their
operands one bit at a time.
A1 A2

D Q D Q Q D

_ _ _
Clock C Q C Q Q C
clear clear clear

Reset

FA
Carry in
Carry out

S
 52

Because carries and borrows must be saved until the next bit arrives,
these circuits must have memories. They must be sequential.
A serial adder is a FA with D flip flops in three input lines.
The carry out output is fed back into the carry in flipflop so that it will
provide the carry in for the next bit.
The flipflops must be reset to 0 and the lower order bits must be
received first.

(Read Multipliers and Dividers)

Link Connections
When joining distinct logic circuits together with a link you need to:
 Convert from voltage signals to current signals or viceversa.
 Increase the power of the signal
 Electrically disconnect a logic circuit from the link
 Connect several logic circuits to the same set of conductors.
The first two problems are resolved by using circuits referred to as
drivers. A driver that is on the receiving end of a transmission is called a
receiver; combinations that both transmit and receive are called
transceivers.

Driver

The third problem is solved by a tristate driver or tristate gate whose

output may be 0, 1 or a high impedence state.
Control

Optional
IEEE standard tristate
Output symbol
 53

A tristate driver has two inputs, a data input and a control input. When
the control input is 1, the output is the same as the input (or the
complement of the input if the driver is also the inverter); when the
control input is 0 the input is disconnected from the output (the high
impedence state).

Control Input Output

0 0 Disconnected
0 1 Disconnected
1 0 0
1 1 1

The fourth problem can be solved by using a wire-ORed gate (open gate
collector) whose output can be directly tied to the outputs of other wire-
ORed gates without damaging any gate.The state at the common point
is 1 if all the gate outputs would normally be 1; otherwise it is a zero. A
resisitor called a pull up resisitor is placed between the common output
and the state 1 voltage.
1
Pull up resistor
A
A+B
B

Sequential Network Design

The design of a sequential network is primarily based upon the states of
the network. The behaviour of a sequential circuit is determined from the
inputs, the outputs and the state of the flipflops.
A state is determined by a 0 & 1 combination of the outputs of the
flipflops of the network.
 54

If a network contains n flip flops, the possible number of states would be

2n. The actual number of states that the network can be in may be less
because the construction of the network may not allow some input
combinations to occur.
If m is the number of states that can occur then 2n >= m.
Each state is assigned a unique 0 – 1 combination of the outputs of the
flipflop. Both the outputs and the next state are a function of the inputs
and the present state.
A sequential circuit is specified by:
(i) A State Table that relates the next state as a function of the
inputs and the present state. In clocked sequential circuits, the
transition from the current to the next state is activated by a clock
signal.
(ii) Output Table: gives the outputs as a function of the current
state.

Example: assume 2 inputs A and B, five states S0 –S4 and three

outputs X, Y, Z.
State table Output Table
Inputs Outputs
00 01 11 10 X Y Z
S0 S1 S1 S0 S0 S0 0 0 1
S1 S0 S4 S3 S3 S1 0 1 0
S2 S2 S0 S1 S0 new state S2 0 1 1
S3 S1 S2 S1 S3 S3 1 0 0
S4 S4 S4 S4 S4 S4 1 1 1

If the current state is S2 and the input is 01, then the new state will be
S0.
10,11 00,01,11,10
S0 00,01 S1
001 010 01
00 S4
01,00 11 10 00 111
11 01
01
00 S2 S3 10
 55

011 100

Information in the state table and output tables can be combined into a
state diagram where circles represent the states and outputs and the
arrows represent the transition between states.

Example:
The state table, output table and state diagram of a network consisting
of only one J-K flip flop
State table
JK Output Table
00 01 11 10 X
S0 S0 S0 S1 S1 S0 0
S1 S1 S0 S0 S1 S1 1
S0 corresponds to Q = 0 S1 to Q = 1
00,10
00,01 10,11
S0 S1
0 1
01,11

Delays
No electronic circuits react instataneously whether they are
combinatorial or not. The length of the delay depends upon the
resistances and capacitances built within the circuits.
Sometimes delays are undesirable, other times they are desirable such
that if natural delays are not enough special circuits called delay
devices are included in a design to create the required delay.
For a delay device the output is the same as the input except that the
output occurs at a later time.
Amount of delay is referred to as the delay time.

Construction of a delay circuit.

… ……………
Delay
 56

The amount of time it takes for a logic gate’s or flipflop’s output to reflect
its inputs is called its switching time and the propagation delay is the
time it takes electromagnetic signals to travel through the circuit and
links.
If 2n inverters are used to build a delay device then the delay time = 2n *
switching time of the inverter.
(Read Timing considerations and output devices)

INTEGRATED CIRCUITS AND TECHNOLOGIES.

Modern digital logic circuits are constructed onto the surfaces of thin
slices of a base material e.g. silicon. The resulting products are
Integrated devices (IC’s) which are normally 0.1cm 3 to 1cm3 in volume
but may contain hundreds of thousands of logic gates.
Advantages of fabricating circuits containing large numbers of gates into
a small area include:
1. The small transistors used to make the gates use very small
power.
2. Capacitances are small. So the swiching time is very little.
3. Distances are short so that propagation delays are short.
4. The number of soldered connections is limited to the relatively low
number of connections to the circuitry outside the IC.

Disadvantages:
1. Because of the small size of the IC’s transistors, the amount of
power that an IC can output may be small.
2. Because of the small surface area, special means may be
needed to dissipate the heat generated by the IC.

Limitations in putting all the computer’s circuitry into a single IC include:

 57

1. Fabrication techniques and heat dissipation requirements limit

the density of the transistors in a circuit.
2. An IC’s phyisical size is limited.

Reliability of an IC depends on its temperature and the materials used to

make the IC.
For an IC to be functional, its temperature must be kept below a limit that
is characteristic of the materials. Special cooling may be used to keep
the temperature down thereby allowing the density or speed of the IC’s
to be increased.
For some fast computers like the supercomputers, the processing
elements are submerged in liquid nitrogen.
The other restriction is due to the fact that flaws occurring during IC
manufacturing cannot be corrected and therefore any flaw would cause
the entire IC worthless.
The probability of a manufacturing flaw increases as the area of the IC’s
surface increases. The percentage of the rejects is proportional to the
size of the IC.
The ratio of the good IC’s to the total produced is called the YIELD.

A method of constructing an IC is called a technology. It is determined

by both the geometry of a transistor and the materials used.
As the technology of IC’s has improved the number of gates that can be
put on a chip has also increased.

SSI Small Scale Integration (SSI) devices contain several independent

gates in a single package. The inputs and outputs of the gates are
connected directly to the pins in the package. The number of gates is
 58

usually less than 10 and it is limited to the number of pins available to

the IC.

Medium Scale Integration (MSI): between 10 – 500 gates on a single

chip. They are used in elementary digital functions e.g. in adders,
decoders, registers etc.

Large Scale Integration (LSI): 500 to a few thousand gates in a sigle

package. They include digital systems like memory chips, processors
e.t.c.

Very Large Scale Intrgration (VLSI): contain thousands of gates on a

chip. E.g. large memory arrays and other complex microcomputer chips.
The most common technologies are the following:
1. Transistor-Transistor Logic (TTL):
Power dissipation = 10 mW
Switching time = 9ns
It has been operational for many years and it is sometimes
considered as a standard.
It was an evolution of the previous technologies that used diodes
and transistors. It was first called DTL (Diode Transistor Logic).
The diodes were later replaced by transistors to improve on circuit
operation.
Several variations of the TTL include
 High Speed TTL
 Low Power TTL
 Schottky TTL
 Low Power Schottky TTL
 Advanced Schottky TTL.
 59

Emitter Coupled Logic: (ECL)

Power 25 mW
Switching Time 2ns

Used in systems requiring high speed operations.e.g. in super

computers and signal processors where high speed is essential.
 60

MICRO COMPUTER ARCHITECTURE

The Architecture of the computer is the physical arrangement of the
parts of the computer system, the principal features of these
components(CPU, Registers, Buses e.t.c.) and how they are connected
together.
The main components of the computer are the following:

The microprocessor
At the centre of all operations is the MPU (Microprocessor Unit). In a
microcomputer the CPU is the microprocessor. Its purpose is to
 Decode the instructions and use them to control the
activities within the system
 It also performs the arithmetic( + , -, /, *) and logical
(>,>=,<,<=, =, =!) computations.

Memory
 Stores both data and instructions that are currently being
used. Memory is broken down into modules where each module
contains several thousand locations.
 Each location is associated with an identifier called a
memory address.

The I/O Sub System

Consists of a variety of devices for communicating with the external
world and for storing large quantities of information e.g keyboards, light
pens, e.t.c. for input and CRT monitors, printers, plotters for output.
Computer components for permanently storing programs and data are
referred to as mass storage units e.g the magnetic tapes, disk units,
magnetic bubble memory e.t.c
 61

N.B. Both programs and data although they can be stored on mass
storage devices they must be transferred to memory first.

System Bus.
A set of conductors that connect the CPU to its memory and I/O devices.
The bus conductors are normally separated into 3 groups:
1. The Data Lines: for transmitting information
2. Address Lines: Indicate where information is to come from or
where it is to be placed.
3. Control Lines: To regulate the activities on the bus.

Interface
Circuitry needed to connect the bus to a device. It matches the electrical
characteristics of the device to those of the bus.
The Memory interfaces are incorporated within the memory’s control
activity. consist of logic
 Needed to decode the address of the memory location being
accessed.
 Buffer data onto/off the bus.
 Contain circuitry to perform memory reads or write.

I/O interfaces must

 Buffer data onto/off the system bus
 Receive commands from the CPU
 Transmit information from their devices to the CPU.

Bus Control Unit

It is the interface of the CPU to the system bus which regulates the bus
activities.
 62

Two arrangements of these components can be described:

(i) The single bus / processor architecture which has only
one processing element and all the other components are
connected to a single link (the System Bus )
Microprocessor
(CPU)

Bus Control Logic

Interface Interface Interface

Interface

Main Memory Mass Storage

I/O Devices I/O Devices

(ii) The Multiprocessing System which has several

processing elements surrounded by different subsystems and a
central link (the system bus) connecting the different subsystems
together.

Memory Mass I/O Memory Mass I/O

Storage Devices Storage Devices

Local Bus Local Bus

Processing Processing
Element Element
System Bus

Shared Shared Mass Shared I/O

memory Storage Devices

The links in the subsystems are called local buses. Each

subsystem can operate as an independent computer but can take
advantage of the shared resources. The shared main memory can
be used for passing information between subsystems and the
shared mass storage can be used to store large programs and
 63

large quantities of data that are needed by more than one

subsystem.
The competition for the shared resources by the different elements
is called contention.

THE CPU
Factors that must be considered when learning about any CPU are
1. Microprocessor Architecture:The arrangement of registers in the
CPU, number of bits in the address and data buses etc.
2. Instruction Set: Listing of operations the microprocessor can
perform:
 Transfering data
 Arithmetic and logical operations
 Data testing
 Branching instructions
 I/O operations
3. Control Signals: Outputs that direct other IC’s e.g. ROMS and I/O
ports when to operate.
4. Pin Functions: gives details about special inputs and outputs of the
microprocessor.
5. Minimal System: how other devices are connected to the
microprocessor.

A typical CPU consists of the control unit which contains the following
registers:
1. The Program Counter (PC) :It holds the address of the main
memory location from which the next instruction is to be fetched.
2. Instruction Register (IR) Receives the instruction when it is brought
from memory and holds it while it gets decoded and executed.
 64

3. Processor Status Word (PSW) contains condition flags which

indicate the current status of the CPU and the important
characteristics of the result of the previous instruction.
4. Stack Pointer (SP): Accesses a special part of memory called a
stack. It is used to temporarily store important information while
sub routines are being executed. It hold the address at the top of
the stack.
Control memory
Control Unit Working Registers
Program counter Address Registers

Instruction Register

Processor status word

Stack pointer
Arithmetic
registers

Bus
Control
Unit Arithmetic/Logic Unit

Unless a branch instruction is encountered a machine level program is

executed in sequence.
The address in the PC is put on the address bus.
Memory places the instruction on the data bus and it is transported to
the CPU.
The CPU inputs the instruction in the IR and it is decoded. While the
instruction is being decoded, its length in bytes is calculated and the PC
 65

is incremented by its length in order to make it point to the next

instruction.
A flow chart of instruction execution
Start

CPU sends address contained in the PC to memory

Memory gets the machine instruction in the location being

addressed and sends it back to the CPU

CPU puts the machine instruction in the IR and decodes it

T Branch F
Instruction?

T Execute the
Conditional Instruction
Branch?
Examine
PSW
F
T Condition F
Met?

Set PC to address of next

instruction

Set PC to Branch
Address

When the execution of the instruction is complete the contents of the PC

are placed on the address bus and the cycle is repeated.
For an unconditional branch the contents of the PC are replaced by the
branch address.
Conditional branches may replace the contents of the PC or increment
these contents depending on the results of the previous condition.

Control Memory
 66

This is optional. It holds a set of instructions called microcode. The

microcode is of two types:
(i) Microinstructions: perform only the most elementary operations
e.g. the assignment instructions like A = 4.
(ii) Macroinstructions: A group of micro instructions.

Working Registers
They are Arithmetic registers or accumulators and address registers.
(i) Arithmetic Registers: They temporarily hold the operands and the
result of the arithmetic operations.
Accessing a register is faster than accessing memory. If several
operations are tobe performed it is better to have the operands in
registers than in memory and return only the result to memory. The
more arithmetic registers a CPU has the faster it can execute
computations.
(ii) Address Registers: for addressing data and instructions in main
memory.
If a register can be used for both arithmetic operations and addressing it
is then called a general purpose register.

Arithmetic/Logic Unit
It performs arithmetic and logical operations on the contents of the
working registers, the PC, memory locations etc.. It also sets and clears
the appropriate flags.

MEMORY
A byte: a group of 8 bits
A nibble: a group of 4 bits
A word: a group of 2,3, or 4 bytes depending on the computer and its
system bus structure.
 67

Each byte has an identifying address associated with it.

When a byte is to be accessed its address is transmitted to the
appropriate interface via address lines.
Addresses are composed of bit combinations and the set of all bit
combinations for a given situation is called an address space.
Some of the high order bits in a memory address are used to select the
module and the remaining lower order bits identify the bytes or word
within the module.
Similarly an interface is identified by the high order bits of an I/O address
and the register within the interface is selected by the 2 or 3 low order
bits.
The act of putting information into or taking information from a memory
location is called memory access.
The number of bits in an address determine the size of an address
space. If an address is n bits wide then there are 2 n possible addresses
(0 – 2n–1).
The number of address lines in the system bus dictates the size of
memory or memory and the I/O space. A total of n address lines would
imply a maximum memory (or overall memory and I/O) capacity of 2 n
bytes.
16 address lines imply 216 = 26 (210) = 64K

Byte Ordering
Bytes in a word can be numbered from left to right or from right to left.
Big Endian: numbering from left to right.
Little Endian: numbering from right to left: This is the numbering adopted
by Intel.
Classifications of memory
 68

Memory can be classified as to whether it can retain its contents when

power is turned off. In this class we have:
(iii) Volatile: (MOS (Metal Oxide Semiconductor))
(iv) Non Volatile: (Magnetic Core).
It can also be classified according t o its Read/Write capabilities.
(a) ROM: (Read Only Memory): It cannot be written to
and its contents cannot therefore be changed accidentally. Once
its contents are set they can only be changed by special
equipment.
There are mainly 4 types of ROM depending on the way in which
their contents are set. Setting the contents of memory is called
programming.
(i) MASKED ROM: contents are set by a masking operation
performed while the chip is being manufactured. They cannot
be altered by the user.
(ii) PROM (Programmable ROM): contents can be set by the
user using special equipment. Once programmed its
contents can never be changed.
(iii) EPROM(Erasable Programmable ROM) Programmed by
charge injection and once programmed the charge
distribution is maintained until it is disturbed by some
external energy source like Ultra Violet light.
It is primarily used during the development / testing stages
and are replaced with ROMS or PROMS once the design is
complete.
Eproms are non volatile but they can lose their contents with
age. A device that cancels the contents of Eprom is called an
Eprom Eraser.
 69

(iv) EAPROM(Electrically Alterable Programmable ROM)

Programmed and erased electrically instead of ultra violet
light.

(b) RAM: (Random Access Memory) : It can be read and written

to. It is called Random because all locations can be
accessed with equal ease.
Ram is of two types:
(i) Static Ram: keep its contents so long as power is on.
(ii) Dynamic Ram: made of capacitors that can be charged or
discharged. It must be refreshed often because of
charge leakage.

I/O INTERFACES
All data transfers except that within the CPU itself is done over one or
more buses. All I/O devices and main memory must somehow be
connected to these buses. If there is more than one bus one bus is for
memory and the other is for the other peripherals.
If there is only one bus (Single bus architecture) the same bus is used
for both memory and I/O transfers. Most micro computers have single
buses.
Memory and peripherals are connected to these buses through
interfaces and controllers.
A controller is circuitry needed to initiate commands given to a device
and to sense the status of the device.
An interface is circuitry needed to connect the peripheral and its control
circuitry to the bus.
The interface must perform some combination of the following functions.
 70

(i) Make the status of the peripheral available to the

computer.
(ii) Provide buffer storage for input data.
(iii) Relay commands from the computer to the peripheral.
(iv) Provide buffer storage for output data.
(v) Signal to the CPU when the operation is complete.
(vi) Signal to the computer when an error occurs.
(vii) Pack bits into bytes or words for input and unpack them
for output.

Data transfers between I/O or mass storage devices and the CPU or
memory is categorised according to the amount of data transferred.
1. Byte/Word Transfer: one byte or word is mobed by one
command. e.g. a terminal.
2. Block Transfer: A whole block of information is moved by a
single command e.g. Direct memory Access transfers which are
between memory and the peripheral.

In block transfers a device’s interface must be used in conjunction with a

DMA controller that can access memory directly without intervention by
the CPU. e.g. a disk uses DMA.
Most devices that require high transfer rates are DMA devices.
When DMA capability is available it has higher priority over all other bus
activity. Many interfaces are designed to perform both types of transfers.

SYSTEM BUS
Data Lines: transfer information. When communicating with memory the
information is data or instructions. With I/O or mass storage devices
information may be data, device status or commands.
 71

The number of data lines determine the number of bits that can be
transferred simultaneously; they have a direct bearing on speed.
The number of data lines are used to classify a microcomputer as 8 bit,
16 bit or 32 bit.

Address Lines: carry bit combinations that are decoded as addresses by

the interfaces connected to the bus.
In a memory module each byte has its own address. The memory
interface is designed to recognise all addresses of the bytes in its
memory. No two bytes can have the same address.
The top few bits of an address select the module while the remaining bits
find the particular memory location within the module.
If I/O devices share a bus with memory some addresses are reserved for
their interface registers. Each register must have its own address and
each interface must recognise the addresses of all its registers.
Once a memory or device interface recognises one of its addresses it
either inputs the information on the data lines and transmits it to the
proper place or it retrieves the necessary data and puts it on the data
lines.

Control Lines: control signals must be passed back and forth among the
CPU, the memory modules and the device interfaces. This information
includes:
(i) Request for Bus Usage:made by the DMA controller.
(ii) Grant for Bus usage: Given by the CPU according to the pre-
determined priority scheme.
(iii) Interrupt signals: External events require attention of the CPU.
(iv) Timing Signals: coordinating data and address transfers on the
bus.
 72

(v) Parity signals: Indicating data transfer errors.

(vi) Signals for indicating malfunctions or power loss.

EXAMPLES OF CPU’S
The Intel 8085

Address/Data (16 lines)

Control Lines (20)

Bus Control Clock

S Z AC P C

Processor Status Word

Program Counter (16 bits)

Stack Pointer (16 bits)

Accumulator (8 bits)
B (8 bits) C (8 bits)
D (8 bits) E (8 bits)

H (8 bits) L (8 bits)
General Purpose Registers

ALU

It is an 8 bit processor i.e. has 8 data lines (1 byte of data can be

transmitted at a time.
Has 6 general purpose registers namely B, C, D, E, H, L with 8 bits each
and associated in pairs.
1 8 bit accumulator.
1 16 bit stack pointer
1 16 bit program counter
1 PSW with 5 flags.
Zero (Z): set when the result of the operation is zero.
 73

Sign (S): set when sign of the result is negative.

Parity (P): When the parity of the bits in the result is even.
Carry (C): Addition resulted into a carry or subtraction or comparison
resulted into a borrow.
Auxiliary Carry (AC) Carry in BCD arithmetic.

The address and data share the same bus lines and they must take
turns to use them. (They are time multiplexed). The address must
be sent first and then data is sent or received.

The 8085 Pin Assignment

CLOCK X1 1 40 VCC +5 V SUPPLY

OSCILLATOR X2 2 39 HOLD
RESET OUT 3 38 HLDA
SOD 4 37 CLK (OUT)
SID 5 36 RESET IN
TRAP 6 35 READY
CONTROL RST 7.5 7 34 IO/M CONTROL
RST 6.5 8 33 S1
RST 5.5 9 32 RD
INTR 10 8085 31 WR
INTA 11 30 ALE
AD0 12 29 S0
AD1 13 28 A15
AD2 14 27 A14
ADDRESS / DATA AD3 15 26 A13
AD4 16 25 A12 ADDRESS
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
GROUND VSS 20 21 A8

1&2 X1 X2 Oscillation input pins.

 74

3. Reset Out: Indicates that the CPU is being reset. It can be used to
reset other components in the system.
4. SOD Serial Output Data Provide capability to output 1 bit at a
time.
5. SID: Serial Input Data: Provide capability to input 1 bit at a time.
6. TRAP: Causes a non-maskable interrupt. Input remains high until
sampled.
7– 9 RST7.5, RST6.5, RSR 5.5: Restart Interrupt Requests. They are
maskable interrupts.
10 INTR: Interrupt Request: A maskable interrupt which when
recognized causes the 8085 to execute an instruction provided by the
interrupting device.
11 INTA: Interrupt Acknowledge: Indicates that the INTRA has been
accepted. It can be used by an interrupting device to place an
instruction on the bus.
12 – 19 AD0 – AD7 Address Data bus. Shared by the address and data.
20. Vss – Ground
21 – 28 A8 – A15 Address bus.
30 ALE Address Latch Enable: Indicates that A8 – A15 and AD7 – AD0
represents a valid address.
31 WR Write Memory or I/O write command
32 RD Read Memory or I/O read
29, 33, 34: S0, S1, IO/M: Output Control signals. They notify peripherals
the type of machine cycle that the CPU is performing.
IO/M S1 S0 Status
0 0 1 Memory Write
0 1 0 Memory Read
0 1 1 Opcode Fetch
1 0 1 I/O Write
 75

1 1 0 I/O Read
1 1 1 Interrupt Acknowledge
* 0 0 Halt
* * * Hold/Reset
35 Ready: Acknowledgement from memory or I/O
device that input data is available on the bus or output data has
been accepted.
36. RESET IN: Reset :
Resets the CPU to its initial state.
It is generated automatically when the system is turned on.
It clears the program counter to 0000H
All maskable interrupts are disabled.
37. CLK : Clock Out: It provides clock signals for all other system
components.
39.HOLD: Hold Request from the DMA Controller. It notifies the CPU
that another device wants to use the bus.
38. HLDA Hold Acknowledge: Indicates that the HOLD request
has been accepted.
The CPU relinquishes control of the buses.
40. Vcc Power supply. +5 V

Instruction Execution Time

The combination of actions taken during the execution of an instruction
is called an instruction cycle. Instruction cycles are subdivided into
machine cycles and the machine cycles are in turn subdivided into
states (clock cycles). Each machine cycle is equivalent to a memory or
I/O access. The retrieval of the first byte of the instruction from memory
is called the instruction fetch. The first machine cycle of an instruction
 76

cycle is called a fetch cycle. The fetch cycle normally consists of 4 to 6

states depending on what actions are taken in addition to the instruction
fetch. All the other machine cycles normally consist of three states. E.g.
the instruction LDA NUM has 4 machine cycles which
are:
(i) the fetch cycle
(ii) 2 cycles to read the address
(iii) 1 cycle to read the byte at NUM.
The fetch cycle has 4 states and each of the other three cycles has 3
states which makes a total of 13 states.
Accessing memory ordinarily takes 3 states:
(i) To send the address to memory
(ii) Memory looks up for the required information
(iii) Memory transmits the information back to the CPU.
A write operation is broken down similarly.
Instruction Cycle
M1 M2 M3 M4

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3 T1 T2 T3
Op code fetch Read Program Read program Write in
Memory memory memory

In each case one of the states is used by memory. If the memory cycle
time is more than the clock cycle time memory then needs more than
one state to perform its function and a wait state is thereby introduced
to enable the memory to complete its operation.
E.g. If a clock period is 300ns and the memory access time is 700ns the
CPU will need 5 states to get 1 byte of information from memory i.e. the
usual three states plus two wait states and the total required would be
1500ns.
The LXI instruction requires three memory accesses and the number of
states required is 10. If the clock cycle time is 300ns and the memory
 77

access time is 700ns then it will take 10 + (3 memory accesses * 2 wait

states) = 16 states and 4800ns to complete the LXI instruction.
Memory modules can be of different speeds. The instruction may be in a
module that has a different speed from that of the operands. If the LHLD
instruction is in the 200ns access time module and the operand is in the
700ns access time module the total number of states needed to execute
the instruction assuming a 300 ns clock cycle would be
16 + (0 * 3) + (2 * 2) = 20 states and the total time needed
would be 6000ns.
In general, if:
B Basic number of states in the table
Wm Wait states for instruction memory
Bi Bytes in instruction
Wo Wait states for operand memory
Bo Bytes in operand.
Then the total number of states is determined by:
B + (Wm * Bi) + (Wo * Bo)
The instruction execution time is obtained by multiplying the total number
of states with clock’s period.
 78

Summary of the 8085 instruction set execution times . Two possible times (e.g. 7/10)
indicates time depends on condition flag settings. First figure corresponds to no branch.

Instruction Machine States Instruction Machine Sates

Cycles Cycles
MOV r1, r2 1 4 ANA r 1 4
MOV M, r 2 7 XRA r 1 4
MOV r, M 2 7 ORA r 1 4
MVI r 2 7 ANA M 2 7
MVI M 3 10 XRA M 2 7
LXI rp 3 10 ORA M 2 7
XCHG 1 4 ANI 2 7
STA 4 13 XRI 2 7
LDA 4 13 ORI 2 7
STAX B 2 7 CMA 1 4
STAX D 2 7 JMP 3 10
LDAX B 2 7 J(condition) 2/3 7/10
LDAX D 7 PCHL 1 6
SHLD 5 16 CALL 5 18
LHLD 5 16 C(Condition) 2/5 9/18
INX rp 1 6 RET 3 10
DCX rp 1 6 R (condition) 1/3 6/12
INR r 1 4 RLC 1 4
DCR 1 4 RRC 1 4
INR M 3 10 RAL 1 4
DCR M 3 10 RAR 1 4
ADD r 1 4 DAD rp 3 10
ADC r 1 4 CMC 1 4
SUB r 1 4 STC 1 4
SBB r 1 4 NOP 1 4
CMP r 1 4 HLT 1 5
ADD M 2 7 PUSH rp 3 12
ADC M 2 7 PUSH PSW 3 12
SUB M 2 7 POP rp 3 10
SBB M 2 7 POP PSW 3 10
CMP M 2 7 SPHL 1 6
ADI 2 7 XTHL 5 16
ACI 2 7 IN 3 10
SUI 2 7 OUT 3 10
SBI 2 7 RST 3 12
CPI 2 7 EI 1 4
DAA 1 4 DI 1 4
RIM 1 4
SIM 1 4
 79

INPUT / OUTPUT PROGRAMMING

Transfer of data between the computer and its peripheral devices is
called input / output.
Most micro computer systems require different I/O routines, depending
on the I/O instruction set, the peripheral devices, the bus structure and
the speed requirements of the particular system.
There is therefore need to understand the various I/O programming
techniques
There are three basic techniques for the transfer of data between a
microcomputer and its I/O devices.
1. Programmed I/O
2. Interrupt I/O
3. Direct memory Access
The first 2 most common ones use a CPU register as a buffer to transfer
1 byte at a time.
For the 3rd case data transfer bypasses the microprocessor and takes
place directly between memory and the I/O devices. For this case extra
hardware, a DMA controller is required to support this type of high speed
transfer.
To support I/O programming, the microprocessor has a set of
instructions called I/O instructions which are used for the following
purposes.
1. To output a byte of data from the microprocessor to a peripheral
device e.g. to send an ASCII character from the accumulator to a
terminal.
2. To send a control command to a peripheral device. E.g. by sending a
special command word to a terminal interface, it can be enabled to
generate an interrupt whenever data is ready to be transferred to
the microprocessor.
 80

3. To input a byte of data from a peripheral device to the accumulator.

E.g. to input an ASCII character from a terminal.
4. To examine the status of a peripheral so that the processor can make
a data transfer decision. E.g. the status of a terminal can be
checked to determine whether or not a byte of data is ready to be
transferred to the processor.

Intel 8085 has the following two I/O instructions.

IN port 1 1 0 1 1 0 1 1
Port

An 8 bit byte is read from the input device at the specified port (up to 256
input ports can be addressed) into the accumulator.

OUT port 1 1 0 1 0 0 1 1
Port

The contents of the accumulator are sent to the output device at the
specified port. (Up to 256 input ports can be addressed).
Some microprocessors e.g. the Motorola MC 6809 do not have these
special instructions. They do not have separate I/O and memory spaces;
part of the memory space is reserved for the I/O addresses and memory
reference instructions are also used for I/O data transfer. This scheme is
referred to as memory mapped I/O.

Programmed I/O
An interface generally contains a number of registers that participate in
I/O transfers.
Typically a single I/O transfer will involve 4 registers; i.e. a status
register, 2 buffer registers and a control register.
 81

The status register contains the current status of the I/O device and of
the data being transferred.
Input Error Bit
0 = error did not occur Data IN ready bit
1 = error occurred 0 = empty
1 = Full

Status Register
Data out ready bit
0 = Full
1 = empty
3 2 1 0

Receiver /Input Buffer register

Transmitter /Output Buffer Register

Control Register

In some cases there may be two status registers; one for input and one
for output.
An input or receiver buffer register receives the data from the device and
temporarily holds it until the computer is ready to accept it and an output
or transmitter buffer register receives the data from the processor and
holds it until the I/O device is ready to accept it.

Programmed I/O is performed by monitoring the status bits to

determine when data is available for input or when the data out buffer
can accept an output.
Before a data transfer is performed the status of the peripheral device is
first brought into the processor from the status register by an IN
instruction.
A status flag is continuously tested until it becomes 1 indicating that the
I/O element has put data in the input buffer. A byte of data is then
transferred to the interface and the error bit is tested to determine if an
error occurred during the transfer.
If an error, occurred an error procedure is called.
 82

If the device is not ready the program performs a loop that checks
the status repeatedly.
Before the next data transfer, the program moves data from the
accumulator to memory, increments the data byte counter, adjusts the
buffer pointer so that it points to the next memory location.

The status register contains 2 bits that indicate the status of the buffer
registers.
When data is put in the input buffer registers, bit 1 is set to 1; when data
is taken out of the buffer, bit 1 is cleared to 0.
For output, bit 0 is cleared to 0 or set to 1 when data is input or taken
from the data out buffer respectively.

No

Input Device Status

No
Is Ready Bit Set

YES

Transfer a Character to or from a

buffer register

Store input character to memory or

get the next output character from
memory

Update counter and buffer pointer

End of
NO character
string

YES
Process data
 83

The status register may contain bits that indicate whether or not errors
(e.g. parity errors) have occurred during a transfer between the interface
and the I/O device.
The error bit is set to 1 if the error occurred and it is 0 if no error
occurred.

Advantages of Programmed I/O

Simplicity: It does not require complicated hardware to implement the
interface. BUT a microprocessor is idle while waiting to input or output a
byte of data.
E.g. if the input device is a keyboard, the processor time is wasted
waiting the user to type the next character.
Similarly in output to a terminal, time is spent waiting for the character to
be transmitted and displayed.
The method is useful to low speed computers or in systems that are
dedicated to monitor a device continuously.

INTERRUPT I/O
There are three types of interrupts:
1. External: These are due to signals that originate from outside the
processing unit.
2. Internal: Caused by events internal to the CPU.
3. Software Interrupts: Initiated by special instructions.

A facility for supervising external interrupts includes:

(i) Interfaces for sending Interrupt requests which require servicing.
(ii) A processing element for responding to interrupt requests.
(iii) Lines in the system bus for relaying the requests and perhaps
returning interrupt acknowledgement to the interfaces.
 84

Consider a typical computer that can execute two instructions that read
the status register and check the flag in 1µs. Assume that the input-
output device can transfer information at a maximum rate of 10
characters per second. This is equivalent to 1 character every
100,000µs. Two instructions are executed when the computer checks
the flag bit and decides not to transfer information. This means that at
the maximum rate the computer will check the flag 50,000 times
between each transfer.
When a microprocessor is waiting it could be doing something useful like
processing data already in memory.
The microprocessor can be timeshared between independent routines
i.e. a background routine for computation and a foreground routine for
data transfer.
This overlapping of computation and control of I/O devices can be
accomplished via interrupt facilities.

Main Routine Continue with data processing

Data ready
Causes an Return to where
Interrupt an interrupt occurred

Interrupt service routine

Performs data transfer

Most of the time, the microprocessor is executing the main routine.

Whenever a byte of data is ready for transfer the I/O device sends an
interrupt request signal.
If the request is recognized by the microprocessor, it waits until the
current instruction is completed and then leaves the main routine
temporarily to service the device.
This type of interrupt is an External Interrupt since it is initiated by an
external device.
 85

The routine that is executed during an interrupt is called an Interrupt

Service Routine. Once the microprocessor has completed the data
transfer, it returns to the main routine from where the interrupt occurred.
Because the interrupted routine is to be continued later, its status must
be saved.
A CPU status consists of contents of the program counter and condition
flags in the PSW.
The instruction PUSH PSW is used to save the contents of the PSW.
The registers to be used by the service routine should also be stored
before they are modified, and then restored before returning to the
routine that was interrupted.
Return to the interrupted routine is accomplished by a Return from
Interrupt instruction RET. It is used as if from a subroutine.
The 8085 processor has 5 pins to input interrupt requests i.e. TRAP,
RST 5.5, RST 6.5, RST 7.5 and INTR.
The latter 4 pins are associated with a set of bits called mask flags. By
selectively setting or clearing these flags, certain combinations of these
requests can be ignored. RST and INTR requests are said to be
maskable.
A TRAP request will always be recognized and it is therefore non
maskable.
For the remaining 4 interrupts the interrupt will be ignored if the CPU’s
enable flag (INTE) is not set to 1.
Furthermore RST 5.5, RST 6.5, RST 7.5 can be individually masked by
setting their corresponding mask bits.
If simultaneous requests occur, TRAP has the highest priority followed
by RST 7.5, RST 6.5, RST 5.5 and INTR has the lowest priority.
The interrupt enable flag can be set by the EI instruction and cleared by
the DI instruction.
 86

The EI instruction enables the processor to recognize and respond to an

INTR request and also to RST requests provided that their masks are
cleared. It sets the INTE flag to 1.
The DI instruction causes the processor to ignore all maskable requests
including the RST. It resets the INTE flag to 0.

The INTR Request

When the CPU recognizes an INTR request from an external device the
following occurs.
1. The instruction currently executed is completed.
2. The INTE flag is reset to 0. This disables further maskable interrupts
until an EI instruction is executed.
3. The processor returns an Interrupt acknowledgement signal INTA and
inputs an instruction from the interrupting device that receives the
INTA signal.

The instruction mentioned in 3 does not appear anywhere in memory

because it is a function of the interrupting device’s interface design. The
programmer has no control over it.
The program counter is not incremented while this instruction is
executed.

The RST Instruction

It has the form RST N where N is an integer in the range of 0 to 7.
It will push the contents of the program counter onto a stack and transfer
control to an instruction whose address is 8 * N.
The servicing routine from the interrupting device will be started via a
sequence of instructions occupying memory locations 8 * N to (8 * N) +
7.
 87

The number 8 * N specifies an address to which the program jumps to

find an appropriate service routine and is referred to as an interrupt
vector.
The 8085 uses 3 bits for interrupt vectors. There are 8 different
addresses for the service routines.
To execute a service routine with more than 8 bytes an unconditional
branch instruction is normally stored in the location pointed to by the
interrupt vector.
Since a RESET causes the 8085 to branch to location 0, RST 0 should
not be used by an interrupting device.

1 1 N N N 1 1 1

NNN ranges from 000 up to 111

E.g. RST 5 = 101 = 11101111 => Restart subroutine at address 28H.

The RST Interrupts

RST 5.5, RST 6.5, RST 7.5 interrupts are similar to the INTR because
they cause the CPU to clear the INTE flag and execute a RESTART
instruction which is generated inside instead of being fetched from the
interrupting device.
Starting addresses corresponding to the RST 5.5, RST 6.5 and RST 7.5
are 002C, 0034, and 003C respectively.
The RST interrupts are also enabled by the EI instruction and disabled
by the DI. In addition each of the three RST interrupts can be individually
masked by setting its mask flag to 1.

The instructions to examine and modify the RST mask flags are the RIM
(Read Interrupt mask) and SIM (Set interrupt mask).
 88

The RIM Instruction. (Read Interrupt Mask)

It does the following:
Loads the settings of the RST 5.5, RST 6.5 and RST 7.5 masks into the
accumulator.
The state of the Interrupt Enable flag is also loaded.
Pending requests from the RST 5.5, 6.5 and 7.5 pins plus the input from
the serial in line are also loaded.
This instruction allows the user to determine which maskable interrupts
are disabled and which RST interrupt requests have been received but
are not yet serviced.

Contents of the accumulator after the RIM instruction.

SID I7.5 I6.5 I5.5 INTE M7.5 M6.5 M5.5

Input from serial Pending RST Interrupt masks for RST 5.5, 6.5
Input pin. Interrupt requests. and 7.5. 1 indicates interrupt is
1 is pending, 0 blocked, 0 interrupt is allowed.
No request
Interrupt Enable flag
1 implies interrupt facility
is enabled and 0 indicates
disabled.

The SIM Instruction (Set Interrupt Mask)

SOD SOE Not Used R7.5 MSE M7.5 M6.5 M5.5

Interrupt masks for RST 5.5,

Output to the Serial Out 6.5 and 7.5. 1 to block the request
Serial-out pin. Enable. 1 to 0 to allow the request.
(ignored if bit 6 output bit 7 to Bits 2-0 will be ignored if bit 3 is 0.
is 0 the Serial output
pin, 0 causes no Mask Set Enable. If 1, masks
action are set according to bits 2-0
. If 0 masks are not affected.
Reset RST 7.5 interrupt Request
to 1 to clear the pending request from
the RST 7.5 pin, 0 no action

It selectively sets the masks for the RST interrupt requests according to
the contents of the accumulator.
 89

Before the SIM instruction is executed, a control byte that specifies

which mask bits are to be set must be stored in the accumulator.

To change the RST 5.5 – RST 7.5 mask bits, bit 3 must be 1.
E.g. to disable RST 5.5 and RST 7.5 requests and to enable RST 6.5
the following code could be used.
MVI A, 0D
SIM
EI

The TRAP interrupt

It is non-maskable and it has the highest priority among external
interrupts. It is reserved for events that must be responded to
immediately e.g. power failure.
When recognized the CPU saves the return address, clears the INTE
flag and then branches to 24H.

Polling
Several devices may share one interrupt vector. The 8085 has only 12
interrupt vectors, 8 for INTR requests, 3 for RST requests and 1 for the
TRAP request. The device that generates an interrupt must be identified
before it can be serviced because several devices can generate the
same interrupt. This process is called Polling.
It is done by checking the Interrupt Request Register to find which bit
has been set to 1 or by checking the interrupt bit in each of the device’s
status register.
An Interrupt Request Register has interrupt request lines from several
devices connected to it.
If a device requests for an interrupt, the device’s corresponding bit in the
Interrupt Request Register is set to 1.
 90

When the Interrupt is acknowledged, the processor reads the interrupt

request register into the accumulator and the position on the non zero bit
is determined.
No more than 1 bit in the Interrupt Request Register is set.
Examining the status register for each device becomes necessary if an
interrupt request register is not available or if there are more than 8
devices using the same Interrupt vector.

Priority Interrupt Systems.

Each of the 8 devices connected to the INTR pin is not of equal
importance.
A system may include high speed devices that retain information for a
short time and may require immediate attention.
A Priority Management Logic system therefore must be established so
that in case there is more than 1 interrupt pending the one with the
highest priority is recognized first.
The priority management logic determines which interrupting device has
the highest priority and compares it with the mask to decide which
interrupt is to be sent to the microprocessor.

DIRECT MEMORY ACCESS

Programmed I/O and interrupt I/O can be used in cases where the data
transfer rate from an I/O is relatively low.
Some storage devices like disk drives and Analog to Digital converters
require transfer rates of over 1 million transfers per second which could
not be handled by Programmed or Interrupt I/O because for each byte
transfer, several instructions have to be executed to transfer a byte
between the accumulator and the device, between the accumulator and
memory, update the buffer pointers and byte counters.
 91

By transferring data directly between memory and the device the transfer
rate can be increased.
Because the microprocessor is bypassed, this transfer is called DMA or
Direct Memory Access.
DMA is achieved when an interface or logic associated with the interface
is able to take control of the system bus and make the data transfer
directly to or from memory.
When a DMA transfer is initiated, a DMA module controls the actual
transfer of data between memory and an external device without
intervention of the microprocessor.
The logic that controls the system bus during DMA transfer is called a
DMA controller.
The CPU normally has control of the bus but the DMA controller can
gain control by sending a bus request to the CPU.
After receiving the bus request and completing the current bus transfer,
the CPU turns supervision of the bus over to the DMA controller by
sending a bus grant to the controller.
After the grant the controller supervises the direct transfer of data
between memory and the interface.
The act of taking control of the bus and performing a DMA transfer is
called Cycle Stealing.

A typical DMA controller contains the following registers:

1. Control Register: it stores the commands issued by the CPU e.g.
enabling the DMA
specifying the type of transfer (Read or Write)
Specify the interrupt condition (Enabled/Disabled)
2. Status Register: To inform the CPU whether the controller is busy,
transfer is complete or certain errors have occurred.
 92

Sometimes both the control and status registers are combined into
1.
Memory

I/O or mass
Bus Interface storage element
Control
Logic

System Bus
DMA DMA
Bus Request ack. Req.

Bus Grant

DMA Controller

3. Byte Counter: Loaded with the number of bytes to be transferred

before the DMA operation. The contents of this register are
decremented by 1 after each transfer. The transfer process stops
when the counter is 0.
4. The Buffer Register: contains the current address of the memory
location to be accessed, and it is incremented by 1 after each byte
transfer. It is loaded with the beginning address of the block before
the block transfer is initiated.

Block transfer involves 3 distinct stages:

1. Initialization :
(i) Output the number of bytes to be transferred to the
controller’s byte counter register.
(ii) Output the starting address of the buffer area to the buffer
pointer.
 93

(iii) Output a command to specify the transfer direction (input or

Output) and to start the DMA transfer.
(iv) Transfer State: includes cycle stealing and carrying out the
transfers while other processing may be taking place.
(v) Completion Stage: does error checking and other termination
activities.
DMA ack DMA req

Transfer Complete
Status

System Bus Counter

Buffer Pointer

Control

DO
Input / Output

Interrupt on Completion

One of the bits in the control register is the DO bit. It is set at the very
end of the initialization stage and when it is set the transfer state begins.
If the Interrupt on Completion bit is not set a program must test the
Transfer Complete Status bit to determine if the entire block transfer is
complete.
As with programmed I/O the program could enter into a loop to test the
transfer complete bit over and over until it is set.
The completion stage consists of executing the completion routine which
does error checking.
The error bits in the status register of a block transfer indicate errors in
the whole block. Parity bits could indicate only one parity error.
In addition to or in place of having a parity bit associated with each byte,
some information is generated at the end of the block to indicate error
 94

checking. This information is referred to as Block Check Characters

(BCCs).
A typical Block Format Termination character

Header Data BCCs

Delimiting Flags
The header contains identifying and descriptive information (e.g. length
of the block) that may be used by the completion routine.
A termination character and delimiting flags mark the beginning and
end of the block.

Input – Output Processor (IOP)

It is used in cases where the computer has independent sets of data,
address and control buses; one for memory and another for I/O. Memory
communicates with both the CPU and the IOP through a memory bus. It
is a processor with DMA capabilities. The IOP communicates also with
the input and output devices through a separate I/O bus with its own
address, data and control lines. The purpose of the IOP is to provide an
independent pathway for the transfer of information between the external
devices and the internal memory. The IOP is sometimes called a data
channel. It helps in avoiding each interface communicating with the
CPU.

CPU
Memory Bus

Peripheral Devices
Memory PD PD PD PD
Memory
IOP
I/O Bus
 95

IOP’s are assigned a task of communicating directly with all the I/O
devices. Each IOP takes care of input and output tasks and it relieves
the CPU from tasks involved in I/O transfers. A processor that
communicates with remote terminals over telephone and other
communication media in a serial fashion is called a Data
communication processor (DCP).

I/O Processing
The IOP is designed to handle details of I/O processing. It can fetch and
execute its own instructions. Apart from facilitating I/O transfers it can
also execute other tasks like arithmetic, logic, branching and code
translation. The CPU initiates the I/O program and from there the IOP
operates independently of the CPU.
Data is gathered in the IOP at the device rate while the CPU is executing
other functions. After the data is assembled into a memory word, it is
transferred from the IOP directly into memory by stealing one memory
cycle from the CPU. Output is similarly performed.
Apart from initiating the data transfer the CPU also tests the I/O status
conditions needed for making decisions on various I/O activities. The
IOP asks for CPU attention by means of an interrupt. It also responds to
CPU requests by placing a status word in a prescribed memory location
to be examined later by the CPU. When an I/O operation is required the
CPU informs the IOP where to find the I/O program and then leaves the
transfer details to the IOP.
 96

CPU-IOP Communication

CPU Operations IOP operations

Send instruction
to test IOP path
Transfer status word
to memory location

If status OK send start

I/O instruction to IOP Access memory for
IOP program

CPU continues with

Conduct I/O transfers
another program
using DMA; prepare
status report

I/O transfer completed;

Request IOP status interrupt CPU

Transfer status word

to memory location
Check status word
for correct transfer

Continue
The CPU sends an instruction to test the IOP path. The IOP inserts a
status word in memory for the CPU to check. The bits of the status word
indicate the condition of the IOP and the I/O device. The CPU refers to
the status word in memory to decide what to do next. If it is OK the CPU
sends the instruction to start I/O transfer. The memory address received
with this instruction tells the IOP where to find its program.
The CPU now can continue with another program while the IOP is busy
with the I/O program.
When the IOP is through with the transfer it sends an interrupt request to
the CPU. The CPU issues an instruction to read the status from the IOP.
The IOP sends it status word into a specified memory location. The CPU
 97

determines if the I/O operation was completed satisfactorily without

errors.