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4 Substractor

This document describes experiments on VHDL code for adder circuits, including 4-bit half adders and 4-bit full adders. It provides the theory of half subtractors and full subtractors, truth tables, circuit diagrams, Boolean expressions, and VHDL code for 4-bit implementations. The VHDL code is simulated and synthesized with a technology library to verify the adder circuits.

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Yidnekachwe Mekuria
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146 views4 pages

4 Substractor

This document describes experiments on VHDL code for adder circuits, including 4-bit half adders and 4-bit full adders. It provides the theory of half subtractors and full subtractors, truth tables, circuit diagrams, Boolean expressions, and VHDL code for 4-bit implementations. The VHDL code is simulated and synthesized with a technology library to verify the adder circuits.

Uploaded by

Yidnekachwe Mekuria
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Adama Science & Technology University

School of Electrical Engineering &Computing


Department of Electronic &Communication Engineering

Experiment-4

Aim: To write VHDL code for Adder circuits: 4-bit Half Adder, 4-bit Full Adder and observe the
waveform and synthesize the code with technological library with given Constraints.
Apparatus: Modelsim PE Student Edition 10.1 Software.
Theory:
Binary Subtractor is a decision making circuit that subtracts two binary numbers from each other,
for example, X – Y to find the resulting difference between the two numbers.
Binary Subtraction can take many forms but the rules for subtraction are the same whichever
process you use. As binary notation only has two digits, subtracting a “0” from a “0” or a “1” leaves
the result unchanged as 0-0 = 0 and 1-0 = 1. Subtracting a “1” from a “1” results in a “0”, but sub-
tracting a “1” from a “0” requires a borrow. In other words 0 – 1 requires a borrow.
Half Subtractor
A half subtractor is a logical circuit that performs a subtraction operation on two binary digits. The
half subtractor produces a sum and a borrow bit for the next stage.

Figure 4.1 The Half Subtractor Circuit.

Table 3.1 Truth Table of Half Subtractor

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Adama Science & Technology University
School of Electrical Engineering &Computing
Department of Electronic &Communication Engineering

From the truth table of the half subtractor we can see that the DIFFERENCE (D) output is the result
of the Exclusive-OR gate and the Borrow-out (Bout) is the result of the NOT-AND combination.
Then the Boolean expression for a half subtractor is as follows.
For the DIFFERENCE bit:
D=X⊕Y
For the BORROW bit
B =(NOT X) .Y

VHDL code for 4-bit Half Adder:


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Half_Subtractor IS
PORT(X,Y: IN STD_LOGIC_vector(3 downto 0); DIFF, BARROW: OUT STD_LOGIC_vector(3
downto 0));
END Half_Subtractor;

ARCHITECTURE DATAFLOW OF Half_Subtractor IS


BEGIN
DIFF <= X XOR Y;
BARROW <= ((NOT X) AND Y);
END DATAFLOW;

Figure 3.1. Simulation waveform results of Half Subtractor

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Adama Science & Technology University
School of Electrical Engineering &Computing
Department of Electronic &Communication Engineering

Full Subtractor
The main difference between the Full Subtractor and the previous Half Subtractor circuit is that a
full subtractor has three inputs. The two single bit data inputs X (minuend) and Y (subtrahend) the
same as before plus an additional Borrow-in (B-in) input to receive the borrow generated by the
subtraction process from a previous stage
Table 3.2. The Truth table of the Full Adder Circuit.

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Adama Science & Technology University
School of Electrical Engineering &Computing
Department of Electronic &Communication Engineering

Figure 3.2. The Full adder circuit diagram.

Then the Boolean expression for a full subtractor is as follows.


For the DIFFERENCE (D) bit:
D = (X.Y.BIN) + (X.Y.BIN) + (X.Y.BIN) + (X.Y.BIN)
which can be simplified too:
D = (X ⊕ Y) ⊕ BIN
For the BORROW OUT (BOUT) bit:
BOUT = ((NOT X) AND Y) OR (Y and Z) OR (Z AND (NOT X))

VHDL code for 4-bit Full Adder:

Figure 3.2. Simulation waveform results of Half Adder

Results: VHDL code for the adder circuits is written, the waveform is observed and the code is
synthesized with the technological library and is verified.

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