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Experiment-5: Aim: To Write VHDL Code For 2:4 Decoder, Observe The Waveform and Synthesize The Code With

The document describes designing a 2:4 decoder using VHDL. It includes the circuit diagram, truth table, VHDL code, and simulation results. The VHDL code implements a 2-input, 4-output decoder that decodes the 2-bit input into a unique 4-bit output based on the truth table. The code was simulated and synthesized successfully.

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Yidnekachwe Mekuria
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289 views2 pages

Experiment-5: Aim: To Write VHDL Code For 2:4 Decoder, Observe The Waveform and Synthesize The Code With

The document describes designing a 2:4 decoder using VHDL. It includes the circuit diagram, truth table, VHDL code, and simulation results. The VHDL code implements a 2-input, 4-output decoder that decodes the 2-bit input into a unique 4-bit output based on the truth table. The code was simulated and synthesized successfully.

Uploaded by

Yidnekachwe Mekuria
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Experiment-5

Aim: To write VHDL code for 2:4 decoder, observe the waveform and synthesize the code with
technological library with given Constraints.
Apparatus: Modelsim PE Student Edition 11.1 Software
Theory:
A decoder is a combinational circuit that converts binary information from n inputs line to a
maximum of 2^n unique output lines.

Fligure 5.1: 2:4 Decoder

Table 5.1 Decoder circuit Truth Table


E A1 A0 D3 D2 D1 D0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Decoder is
port (A : in STD_LOGIC_VECTOR(1 downto 0); E : in STD_LOGIC;D : out
STD_LOGIC_VECTOR (3 downto 0));
end Decoder;

1
architecture behavioral of Decoder is
begin
process (A)
begin
if(E = '1')
then
case A is
when "00"=> D<="0001";
when "01"=> D<="0010";
when "10"=> D<="0100";
when "11"=> D<="1000";
end case;
end if;
end process;
end behavioral;

Simulation waveform results of 2 to 4 Decoder


Results: VHDL code for the Decider is written, the waveform is observed and the code is synthesized
with the technological library and is verified.

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