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712 views340 pages

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DesignWare Cores HDMI Transmitter Controller

Databook

DWC_hdmi_tx (with or without HDCP)

1.40a-ea00, Early Adopter Edition

July 2012
HDMI Transmitter Controller Databook, Early Adopter Edition

Copyright Notice and Proprietary Information

Copyright © 2012 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information
that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or
copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced,
transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written
permission of Synopsys, Inc., or as expressly provided by the license agreement.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals
of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and
to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE.
Registered Trademarks (®)
Synopsys, AEON, AMPS, Astro, Behavior Extracting Synthesis Technology, Cadabra, CATS, Certify, CHIPit, CoMET, Confirma, CODE V,
Design Compiler, DesignWare, EMBED-IT!, Formality, Galaxy Custom Designer, Global Synthesis, HAPS, HapsTrak, HDL Analyst,
HSIM, HSPICE, Identify, Leda, LightTools, MAST, METeor, ModelTools, NanoSim, NOVeA, OpenVera, ORA, PathMill, Physical Compiler,
PrimeTime, SCOPE, Simply Better Results, SiVL, SNUG, SolvNet, Sonic Focus, STAR Memory System, Syndicated, Synplicity, the
Synplicity logo, Synplify, Synplify Pro, Synthesis Constraints Optimization Environment, TetraMAX, UMRBus, VCS, Vera, and
YIELDirector are registered trademarks of Synopsys, Inc.
Trademarks (™)
AFGen, Apollo, ARC, ASAP, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, BEST, Columbia, Columbia-CE, Cosmos, CosmosLE,
CosmosScope, CRITIC, CustomExplorer, CustomSim, DC Expert, DC Professional, DC Ultra, Design Analyzer, Design Vision,
DesignerHDL, DesignPower, DFTMAX, Direct Silicon Access, Discovery, Eclypse, Encore, EPIC, Galaxy, HANEX, HDL Compiler,
Hercules, Hierarchical Optimization Technology, High-performance ASIC Prototyping System, HSIMplus, i-Virtual Stepper, IICE, in-Sync,
iN-Tandem, Intelli, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, Liberty, Libra-Passport, Library Compiler, Macro-PLUS, Magellan,
Mars, Mars-Rail, Mars-Xtalk, Milkyway, ModelSource, Module Compiler, MultiPoint, ORAengineering, Physical Analyst, Planet, Planet-
PL, Polaris, Power Compiler, Raphael, RippledMixer, Saturn, Scirocco, Scirocco-i, SiWare, Star-RCXT, Star-SimXT, StarRC, System
Compiler, System Designer, Taurus, TotalRecall, TSUPREM-4, VCSi, VHDL Compiler, VMC, and Worksheet Buffer are trademarks of
Synopsys, Inc.
Service Marks (SM)
MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc.

SystemC is a trademark of the Open SystemC Initiative and is used under license.
ARM and AMBA are registered trademarks of ARM Limited.
Saber is a registered trademark of SabreMark Limited Partnership and is used under license.
PCI Express is a trademark of PCI-SIG.
All other product or company names may be trademarks of their respective owners.

Synopsys, Inc.
700 E. Middlefield Road
Mountain View, CA 94043
www.synopsys.com

2 SolvNet Synopsys, Inc. 1.40a-ea00

DesignWare.com July 2012
HDMI Transmitter Controller Databook, Early Adopter Edition

Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Databook Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Web Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Chapter 1
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.1 General Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.1.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1.2 Standards Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1.3 Unsupported Features and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1.4 HDMI Operational Model Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.2 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5 HDMI Transmit API Low-Level Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.6 Speed and Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7 Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Chapter 2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.1 DWC_hdmi_tx Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2 Video Pixel Sampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3 Supported Video Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.4 Video Packetizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.5 Color Space Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.6 Audio Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.6.1 Supported Audio Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.6.2 I2S interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.6.3 S/PDIF Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.6.4 Generic Parallel Audio (GPA) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.6.5 AHB Audio DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.7 Frame Composer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.8 HDCP Encryption Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.8.1 Controller Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.8.2 OESS Window of Opportunity Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.8.3 Random Number Generation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.8.4 DVI or HDMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

1.40a-ea00 Synopsys, Inc. SolvNet 3

July 2012 DesignWare.com
Contents HDMI Transmitter Controller Databook, Early Adopter Edition

2.8.5 Features 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

2.8.6 R Value Verification Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.8.7 Bypass Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.8.8 I2C Fast Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.8.9 Enhanced Link Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.8.10 Encryption Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.8.11 Advance Cipher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.8.12 Receiver or Repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.8.13 Memory Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.9 EDID/HDCP I2C E-DDC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.9.1 I2C Master Interface Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.9.2 I2C Master Interface Extended Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.9.3 I2C Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.10 AMBA APB 3.0 Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.11 CEC Hardware Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Chapter 3
Hardware Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Chapter 4
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.1 Naming and Description Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.1.1 Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.1.2 Signal Name Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.1.3 Signal Name Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.2 Top-Level I/O Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.3.1 Video Input Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.3.2 Audio Input Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.3.3 System and Slave Register Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.3.4 E-DDC Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.3.5 CEC Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.3.6 HDCP Encryption Engine Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.3.7 Scan Test Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.8 HDMI TX PHY Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.3.9 HDMI 3D TX PHY (PHY GEN 2) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.3.10 HDMI HEAC PHY Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.3.11 HDMI TX External PHY Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Chapter 5
Software Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.1 Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.2 Register and Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.2.1 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.2.2 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.2.3 Video Sampler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.2.4 Video Packetizer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.2.5 Frame Composer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
5.2.6 HDMI Source PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
5.2.7 I2C Master PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

4 SolvNet Synopsys, Inc. 1.40a-ea00

DesignWare.com July 2012
HDMI Transmitter Controller Databook, Early Adopter Edition Contents

5.2.8 Audio Sampler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

5.2.9 Generic Parallel Audio Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
5.2.10 Audio DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
5.2.11 Main Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
5.2.12 Color Space Converter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
5.2.13 HDCP Encryption Engine Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
5.2.14 HDCP BKSV Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
5.2.15 HDCP AN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
5.2.16 CEC Engine Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
5.2.17 I2C Master Registers (E-DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Appendix A
HDCP Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
A.1 Authentication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
A.1.1 First Part of Authentication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
A.1.2 Second Part of Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
A.1.3 Third Part of Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
A.2 HDCP State Machines and Debug Observation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
A.2.1 HDCP Authentication FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
A.2.2 HDCP Cipher FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
A.2.3 HDCP Revocation FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
A.2.4 OESS (Ordinary Encryption Status Signaling) FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
A.2.5 EESS (Enhanced Encryption Status Signaling) FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

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Preface

This databook describes the DesignWare Cores HDMI Transmitter Controller, which, along with the
Synopsys DWC HDMI TX PHY, is a part of a complete HDMI TX interface solution.
Throughout this databook, HDMI TX is used to reference the DWC_hdmi_tx controller.

Databook Organization
The chapters of this databook are organized as follows:
■ Chapter 1, “Product Overview” provides an introduction to the HDMI TX, including a block
diagram, supported features, deliverables, supported standards, and so.
■ Chapter 2, “Functional Description” details the functions of the HDMI TX.
■ Chapter 3, “Hardware Configuration Parameters” describes the hardware configuration parameters.
■ Chapter 4, “Signals” provides descriptions of the HDMI TX’s inputs/outputs.
■ Chapter 5, “Software Registers” provides the memory map of the HDMI TX and descriptions of the
programmable software registers.
■ Appendix A, “HDCP Application Note” provides more detail on the HDCP authentication protocol.

Related Documentation
Refer to the following documentation:
■ coreConsultant User’s Guide
■ coreAssembler User’s Guide

Web Resources
The following web links are various Synopsys online resources you may find useful:
■ DesignWare IP product information: http://www.designware.com
■ Your custom DesignWare IP page: http://www.mydesignware.com
■ Documentation through SolvNet: http://solvnet.synopsys.com (Solvnet ID required)
■ Synopsys Common Licensing (SCL): http://www.synopsys.com/keys

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Customer Support
To obtain support for your product, choose one of the following:
■ First, prepare the following debug information, if applicable:
❑ For environment setup problems or failures with configuration, simulation, or synthesis that
occur within coreConsultant or coreAssembler, use the following menu entry:
File > Build Debug Tar-file
Check all the boxes in the dialog box that apply to your issue. This menu entry gathers all the
Synopsys product data needed to begin debugging an issue and writes it to the file
core tool startup directory/debug.tar.gz.
❑ For simulation issues outside of coreConsultant or coreAssembler:
■ Create a waveforms file (such as VPD or VCD)
■ Identify the hierarchy path to the DesignWare instance
■ Identify the timestamp of any signals or locations in the waveforms that are not understood
■ Then, contact Support Center, with a description of your question and supplying the above
information, using one of the following methods:
❑ For fastest response, use the SolvNet website. If you fill in your information as explained below,
your issue is automatically routed to a support engineer who is experienced with your product.
The Sub Product entry is critical for correct routing.
Go to http://solvnet.synopsys.com/support/open_case.action.
Provide the requested information, including:
■ Product: DesignWare Cores
■ Sub Product: HDMI Controller
■ Version: 1.40a-ea00
■ Problem Type:
■ Priority:
■ Title: Provide a short summary of the issue or list the error message you have encountered.
■ Description: For simulation issues, include the timestamp of any signals or locations in
waveforms that are not understood
After creating the case, attach any debug files you created in the previous step.
❑ Or, send an e-mail message to [email protected] (your e-mail will be queued and
then, on a first-come, first-served basis, manually routed to the correct support engineer):
■ Include the Product name, Sub Product name, and Tool Version number in your e-mail (as
identified above) so it can be routed correctly.
■ For simulation issues, include the timestamp of any signals or locations in waveforms that are
not understood
■ Attach any debug files you created in the previous step.
❑ Or, telephone your local support center:
■ North America:
Call 1-800-245-8005 from 7 AM to 5:30 PM Pacific time, Monday through Friday.

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■ All other countries:

http://www.synopsys.com/Support/GlobalSupportCenters

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1
Product Overview

This chapter includes the following topics:

■ “General Product Description” on page 22
■ “Interfaces” on page 26
■ “Features” on page 27
■ “Deliverables” on page 28
■ “HDMI Transmit API Low-Level Driver” on page 28
■ “Speed and Clock Requirements” on page 29
■ “Area” on page 30

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1.1 General Product Description

The DesignWare Cores HDMI Transmitter Controller includes the DWC_hdmi_tx core and its verification
environment. Synopsys also provides the coreConsultant tool for automated configuration, simulation, and
synthesis of the DWC_hdmi_tx core.
The HDMI TX Controller can be configured with or without a High-bandwidth Digital Content Protection
(HDCP) system. If you want HDCP enabled, you need an additional license. The DWC_hdmi_tx digital core
is designed to interface with the Synopsys HDMI Transmitter Physical Layer (DWC HDMI TX PHY),
enabling the integration of a complete HDMI Transmitter interface.
Figure 1-2 shows the DWC_hdmi_tx in an example system on chip design.

Figure 1-1 DWC_hdmi_tx in System on Chip Example

System Memory
System
CPU
Drivers

System Bus

MIPI DigRF PCIe USB Link HDMI

Controller Controller Controller Controller Controller 10/100
Ethernet
Controller
MIPI DigRF PCIe USB HDMI
PHY PHY PHY PHY PHY

Ethernet
PHY

RF Chip

Chip-to-Chip
Communications Data Multimedia Network
Sensor Module-to-Module Connectivity Communication
Interface Communications Connectivity

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1.1.1 Applications
Typical applications for an HDMI device built with the DWC_hdmi_tx core are:
■ Blue-ray and HD-DVD player
■ A/V Receiver
■ Set-Top Box
■ Digital Still Camera
■ HDTV Camcorder
■ Portable Media Player
■ Video Game Console
■ Personal Computer
■ Mobile Phone

1.1.2 Standards Compliance

HDMI TX conforms to the following standards:
■ HDMI 1.4b (www.hdmi.org)
■ HDMI CTS 1.4b (www.hdmi.org)
■ HDCP 1.4 (click here for specification)
■ AMBA APB 3.0 Specification from ARM
■ AMBA AHB 2.0 Specification from ARM
■ I2C Bus Specification, Version 2.1 from NXP
■ I2S Bus Specification, June 5, 1996

1.1.3 Unsupported Features and Exceptions

The following are features not supported in this version of DWC_hdmi_tx:
■ Low priority data island packets: (see Table 2-14 on page 68)
❑ One-bit audio (DSD and DST)
❑ MPEG

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1.1.4 HDMI Operational Model Overview

The High Definition Multimedia Interface (HDMI) is a wired digital interconnect that replaces the analog
SCART connection. HDMI is capable of transferring uncompressed video, audio, and data using a single
cable. The video pixel rates are typically from 25 MHz up to 297 MHz (4k x 2k and 3D video modes), but
HDMI can support higher rates up to 340 MHz. HDMI supports a number of audio standards, including: up
to eight IEC60958 L-PCM audio channels, IEC61937 compressed non-linear PCM (AC-3, MPEG-1/-2 Audio,
DTS®, MPEG-2/-4 AAC, ATRAC, WMA, MAT), and HBR audio formats (Dolby® True-HD and DTS-HD
Master Audio).
Additionally, HDMI has the capability of automatically setting the display format configuration (intelligent
link). Optionally, HDMI can include a content protection system called HDCP (High-bandwidth Data
Content Protection). The HDMI connections can be used to connect DVD recorders, set-top boxes, and game
consoles to flat panel televisions and an AV amplifier that can act as repeater/router.
HDMI system architecture consists of sources (transmitter) and sinks (receiver). As shown in Figure 1-2, the
HDMI cable and connectors carry four differential pairs that make up the TMDS data and clock channels.
These channels are used to carry video, audio, and auxiliary data. In addition, HDMI carries a VESA Data
Display Channel (DDC). The DDC is used for configuration and status exchange between a single source
and a single sink. The optional CEC protocol provides high-level control functions between all of the
various audiovisual products in a user’s environment.

Figure 1-2 HDMI Block Diagram

HDMI Source HDMI Sink

TMDS Channel 0 Video

Video

HDMI TMDS Channel 1 Audio

HDMI
Audio Transmitter Receiver
TMDS Channel 2
Control/Status
Control/Status

TMDS Clock Channel

EDID
Display Data Channel (DDC) ROM

CEC Line
CEC CEC

Utility Line
HEAC
CEC HEAC
CEC

detect
CEC High/Low
HPD Line

Audio, video, and auxiliary data is transmitted across the three TMDS data channels. A TMDS clock
running at 1x (24-bit true color mode), 1.25x (30-bit Deep color mode), 1.5x (36-bit deep color mode), or 2x
(48-bit Deep-Color mode), the video pixel rate is transmitted on the TMDS clock channel and used by the

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receiver as a frequency reference for data recovery on the three TMDS data channels. Video data can have a
pixel size of 24, 30, 36, or 48 bits. Video at the default 24-bit color depth is carried at a TMDS clock rate equal
to the pixel clock rate. Higher color depths are carried using a correspondingly higher TMDS clock rate.
Video formats with TMDS rates below 25 MHz (such as, 13.5 MHz for 480i/NTSC) can be transmitted using
a pixel-repetition scheme. The video pixels can be encoded in either RGB, YCBCR 4:4:4, or YCBCR 4:2:2
formats.
HDMI uses a packet structure to transmit audio and auxiliary data across the TMDS channels. To attain the
highest reliability required of audio and control data, this data is protected with a BCH error correction code
and is encoded using a special error reduction code to produce the transmitted 10-bit word.
Basic audio functionality consists of a single IEC 60958 L-PCM audio stream (two audio channels) at sample
rates of 32 kHz, 44.1 kHz, or 48 kHz, which can accommodate any normal stereo stream. Optionally, HDMI
can carry audio at sample rates up to 192 kHz and with three to eight audio channels. HDMI can also carry
an IEC 61937 compressed (such as, surround sound) audio stream at bit rates up to 24.576 Mbps. For bit
rates above 6.144 Mbps, compressed audio streams conforming to IEC 61937 are carried using HBR Audio
Stream Packets. Each packet carries four IEC 60958 frames, which corresponds to (4x2x16 =) 128 contiguous
bits of an IEC 61937 stream.
The source uses the DDC to read the sink’s Enhanced Extended Display Identification Data (E-EDID) to
obtain the sink’s configuration and/or capabilities.
The DesignWare Cores HDMI TX Controller schedules the three periods: Video Data Period, Data Island
period, and Control period. During the Video Data Period, the active pixels of an active video line are
transmitted. During the Data Island period, audio and auxiliary data are transmitted using a series of
packets. The Control period is used when no video, audio, or auxiliary data needs to be transmitted. A
Control Period is required between any two periods that are not Control Periods. An example of each
period placement is shown in Figure 1-3.
The optional HEAC (HDMI Ethernet and Audio Return Channel) functionality provides the capability of
transporting bi-directional Ethernet traffic and an S/PDIF Audio Return Channel (from the receiver to the
transmitter) over the HDMI cable.

Figure 1-3 TMDS Periods in 720x480p Video Frame

TMDS Periods in 720x480 Video Frame
V
e
r Data Island Period
t
I
c
a ControlPeriod
Command Period
l
Control
CommandPeriod
Period
525

T
o 480
t
a A
l c
t
L i
i v Data Video Data Period
n e Island Active Video
e Period
s L
i
n
e
s

Horzontal Blanking 720 Active Pixels

858 Total Pixels

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1.2 Interfaces
HDMI TX has the following interfaces:
■ Optional HDCP interface
❑ External ROM interface for key storage
❑ External RAM interface for revocation
❑ Random number generator interface
■ Video input interface
❑ RGB 4:4:4
❑ YCbCr4:2:2
❑ YCbCr4:4:4
■ Digital audio input interface
❑ Four I2S interfaces for eight-channel audio
❑ S/PDIF interface
❑ Generic Parallel Audio
❑ AHB audio DMA
■ System interface
❑ AMBA APB
■ Scan test interface
■ HDMI TX PHY interface
■ CEC interface

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1.3 Features
HDMI TX supports the following features:
■ Video formats:
❑ All CEA-861-E video formats up to 1080p at 60 Hz and 720p/1080i at 120 Hz
❑ Optional HDMI 1.4b video formats: (configuration dependent)
■ All CEA-861-E video formats up to 1080p at 120 Hz
■ HDMI 1.4b 4K x 2K video formats
■ HDMI 1.4b 3D video modes with up to 340 MHz (TMDS clock)
■ Colorimetry:
❑ 24/30/36/48-bit RGB 4:4:4
❑ 24/30/36/48-bit YCbCr 4:4:4
❑ 16/20/24-bit YCbCr 4:2:2
❑ xvYCC601
❑ xvYCC709
❑ Optional HDMI 1.4b colorimetry:
■ sYCC601
■ Adobe RGB
■ Adobe YCC601
■ Optional color space converter (CSC):
❑ RGB (4:4:4) to/from YCbCr (4:4:4 or 4:2:2)
■ Optional HDMI 1.4b supported Infoframes:
❑ Audio InfoFrame packet extension to support LFE playback level information
❑ AVI infoFrame packet extension to support YCC Quantization range (Limited Range, Full Range)
❑ AVI infoFrame packet extension to support Content type (Graphics, Photo, Cinema, Game)
■ Audio formats:
Table 2-3 on page 44 shows the supported audio formats for the DWC_hdmi_tx’s interfaces. Previous
versions of the DWC_hdmi_tx core included a High Bit Rate (HBR) audio interface. This interface is
now obsolete, however, the interfaces described in Table 2-3 on page 44 all support HBR.
■ Up to 192 kHz IEC60958 audio sampling rate
■ Pixel clock from 13.5 MHz up to 340 MHz
■ Option to remove pixel repetition clock (prepclk) from HDMI TX interface for an easy integration
with third-party HDMI TX PHYs
■ Flexible synchronous enable per clock domain to set functional power down modes
■ AMBA APB 3.0 register access
■ I2C DDC, EDID block read mode

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■ Advanced PHY testability

■ Integrated CEC hardware engine
■ Synopsys and external PHY Interfaces
■ Configurable number of positive-edge-triggered flip-flops connected for data synchronization

1.4 Deliverables
The HDMI TX executable .run installation file contains the following deliverables:
■ HDMI TX custom-configured RTL source code (using coreConsultant or coreAssembler)
■ HDMI TX synthesis, design-for-test, and power reduction scripts (using coreConsultant or
coreAssembler)
■ HDMI TX Verilog test environment (using coreConsultant or coreAssembler)
■ This databook
■ DesignWare HDMI Transmitter Controller Installation Guide (PDF)
■ DesignWare HDMI Transmitter Controller Release Notes (PDF)
■ DesignWare HDMI Transmitter Controller User Guide (PDF)
Synopsys’ coreConsultant/coreAssembler tools, part of the coreTools suite of tools from Synopsys, are
necessary to generate RTL. Additional synthesis and simulation tools are required to create a gate level
netlist or verify the configured RTL.

1.5 HDMI Transmit API Low-Level Driver

The Synopsys HDMI Transmit API low-level driver provides the following features:
■ HDMI TX controller configuration
■ HDMI TX PHY test register access
■ EDID reading and parsing
■ HDCP handling and engine configuration
■ HDCP Repeater support
■ CEC low-level protocol
If you would like this driver, contact Synopsys customer support.

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1.6 Speed and Clock Requirements

Table 1-1 shows the clock frequency of the DWC_hdmi_tx core.
Table 1-1 DWC_hdmi_tx Clock Frequency

Clock Domain Minimum Frequency Maximum Frequency

ispdifclk (DRU enabled or HBR_ON_SPDIF enabled) 16.384 MHz 98.304 MHz

ispdifclk (DRU bypassed and HBR_ON_SPDIF disabled) 4.096 MHz 24.576 MHz

i2sclk 4.096 MHz 24.576 MHz

igpaclk 4.096 MHz -

ipixelclk 13.5 MHz 340 MHz

isfrclk 18 MHz 27 MHz

iapbclk 27 MHz -

iceclk 32.768 kHz 32.768 kHz

idmahclk 27 MHz -

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1.7 Area
If you are using the TSMC 40nm LP technology, the following gate areas are applicable:
Table 1-2 DWC_hdmi_tx TSMC 40LP Gate Count

Configuration Interface Area (gates)

Base APB + S/PDIF without DRU 109K
I2S 30K
S/PDIF with DRU 1K
S/PDIF with HBR support 33K
DOUBLE 40K
GP Audio 32K
Audio
GDOUBLE 49K
AHB audio DMA, FIFO depth=128 71K
AHB audio DMA, FIFO depth=256 107K
AHB audio DMA, FIFO depth=512 178K
AHB audio DMA, FIFO depth=1024 322K
CEC 7K
HDCP 29K
HDCP with 8-bit memory interface 30K
CSC 41K
Pixel Repitition 31K
Support for HDMI 1.4 0K

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2
Functional Description

This chapter describes the functional architecture of the DWC HDMI TX controller.
The topics described are:
■ “DWC_hdmi_tx Functional Overview” on page 32
■ “Video Pixel Sampler” on page 33
■ “Supported Video Modes” on page 36
■ “Video Packetizer” on page 42
■ “Color Space Conversion” on page 43
■ “Audio Interfaces” on page 44
■ “Frame Composer” on page 68
■ “HDCP Encryption Engine” on page 70
■ “EDID/HDCP I2C E-DDC Interface” on page 85
■ “AMBA APB 3.0 Slave Interface” on page 88
■ “CEC Hardware Engine” on page 88

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2.1 DWC_hdmi_tx Functional Overview

The DWC_hdmi_tx provides a variety of standard audio, video, and system interfaces. It includes an
optional high-bandwidth data content protection (HDCP) encryption engine for HDMI receiver
authentication, revocation, and data encryption. The HDCP feature requires an additional DesignWare
Cores license.
Figure 2-1 illustrates the block diagram of the DWC HDMI TX solution.

Figure 2-1 DWC_hdmi_tx Controller Block Diagram

DWC_hdmi_tx
References
Color Space Video
Video Sampler
Video (page 33) Converter Packetizer
Interface (page 43) (page 42) TMDSCLKP
PLL
TMDSCLKN
I2S (page 45)
S/PDIF TMDSDATAP[0]
PLL
Audio (page 49) Audio Frame HDCP TMDSDATAN[0]
Interface GP Audio Packetizer Composer Encryptor
(page 50) (page 44) (page 68) (page 70) TMDSDATAP[0]
DMA (page 54) PLL
(page 54) TMDSDATAN[0]

Audio Sampler TMDSDATAP[0]

PLL
TMDSDATAM[0]
I2C
Register Master
(page 234) HDMI TX PHY
AMBA APB Bank
Control (page 88) I2C/DDC
Interface DDC_SCL
Master
(page 85) DDC_SDA
Configuration Main Control
& CEC
Control Logic CEC
Controller External
(page 88)
Memory
Interface HDCP Keys
(page 75)

= additional license required for this feature = configuration dependent

The optional HDCP encryption engine is responsible for HDMI receiver authentication, revocation, and
data encryption. It has an exclusive read access to the external HDCP encryption Device Private Keys ROM,
making it impossible to access the confidential keys of the register bank and system interface.
You can configure the core to manually override several automatic actions like the N/CTS calculation or the
core’s power management state. Synchronous enables per clock domain give management modes the ability
to reduce the core’s power consumption. For example, you can configure DWC_hdmi_tx without HDCP
encryption, which puts the HDCP engine in idle operation mode.
The input video stream can be either RGB 4:4:4, YcbCr 4:2:2, or YcbCr 4:44 in single data rate (SDR) bus
formats as described in Table 2-1 on page 34. The video mode’s timing format must follow the CEA-861-E
specification. An embedded color space conversion allows the pixel color format to be converted on the
HDMI source side to match the best with the HDMI sink capabilities.

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The input audio stream can be provided through a standard I2S format interface, S/PDIF, an AHB DMA
master, or a Generic Parallel interface (for all audio types: L-PCM, NL-PCM, and HBR), as described in the
“Audio Interfaces” on page 44.
The system interface (the interface that connects to the processor bus) is an AMBA APB.
Finally, the core can output video in full HD with up to 48-bit color mode and inserts high fidelity audio up
to eight-channels over low resolution video formats by performing automatic pixel repetition over the input
video stream.

2.2 Video Pixel Sampler

The Video pixel sampler block is responsible for the video data synchronization, according to the video data
input mapping defined by the Color Depth (Deep Color) and format configuration. Optionally, for YCbCr
4:2:2 format, data mapping can be performed to conform to ITU.601 and ITU.656 standards but without the
support of embedded synchronizers.
Table 2-1 on page 34 provides input data mappings.
The video pixel sampler registers base address is 0x0200. For more detailed information on this register,
refer to Section 5.2.3 on page 164.

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Table 2-1 Input Data Mappings

Video Input
Format ivdata[47:0] mapping

Color Color 47-46 45- 43- 41- 39- 37- 35- 33- 31-30 29- 27- 25- 23- 21- 19- 17- 15-14 13- 11- 9- 7- 5- 3- 1-
Space Depth 44 42 40 38 35 34 32 28 26 24 22 20 18 16 12 10 8 6 4 2 0

8-bit R[7:0] G[7:0] B[7:0]

RGB 10-bit R[9:0] G[9:0] B[9:0]

4:4:4 12-bit R[11:0] G[11:0] B[11:0]

16-bit R[15:0] G[15:0] B[15:0]

8-bit Cb[7:0] Y[7:0] Cr[7:0]

YCbC 10-bit Cb[9:0] Y[9:0] Cr[9:0]

r 4:4:4 12-bit Cb[11:0] Y[11:0] Cr[11:0]

16-bit Cb[15:0] Y[15:0] Cr[15:0]

8-bit Cb[7:0] Y[7:0]

Cr[7:0] Y[7:0]

YCbC 10-bit Cb[9:0] Y[9:0]

r 4:2:2 Cr[9:0] Y[9:0]

12-bit Cb[11:0] Y[11:0]

Cr[11:0] Y[11:0]

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For each video timing format, there is a specific timing parameters defined in the CEA-861-E specification.
The following timing diagram is an example for the video mode format 1 (640x480p @ 59.94/60 Hz):
Data Enable = idataen, HSYNC = ihsync, VSYNC = ivsync.

Figure 2-2 Timing Parameters for 640x480p @ 59.94/60 Hz

800 Total Horizontal Clocks per line

Data
Enable

160 640 Clocks for Active Video

96
16 48 clocks

HSYNC

Progressive Frame: 45 Vertical Blanking Lines 480 Active Vertical Lines

Data
Enable
800 clocks 144
16

HSYNC

515 515 517 24 525 1 2 3 4 5 6 7 35 36 515 516 525

VSYNC

For a complete list of timing parameters and diagrams, refer to the CEA-861-E specification.
The SDR video sample input format is illustrated in Figure 2-3.

Figure 2-3 Video Sample Timing Interface for RGB, YCbCr SDR Format

idataen

ipclk

idata Data N Data N+1

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2.3 Supported Video Modes

Table 2-2 shows examples of the supported video modes.

Table 2-2 Video Modes

2D 3D Structure

L+depth+ Side-by-
Frame Side-by- graphics+ Side Top-and-
2D Packing Line Alt. Side (full) graphics- (Half) Bottom
H x V Active Refres Pixel Pixel Field Alt. Pixel Pixel L+depth depth Pixel Pixel
Video Resolution h Rate Rate Rate Pixel Rate Rate Rate Pixel Rate Pixel Rate Rate Rate
Mode Mode (pixel) (Hz) (Mp/s) (Mp/s) (Mp/s) (Mp/s) (Mp/s) (Mp/s) (Mp/s) (Mp/s) (Mp/s)

Interlaced Progr. Progr.

ALL CEA Only Only ALL CEA Progr. Only Only ALL CEA ALL CEA

Primary HDMI Video Format Timings (CEA-861-E)

1 59.94 25.18 50.35 50.35 50.35 50.35 100.70 25.18 25.18

640x480p (EDTV) 640 x 480
1 60.00 25.2 50.40 50.40 50.40 50.40 100.80 25.2 25.2

19 50.00 74.25 148.50 148.50 148.50 148.50 297.00 74.25 74.25

4 1280x720p (HDTV) 1280 x 720 59.94 74.18 148.35 148.35 148.35 148.35 296.70 74.18 74.18

4 60.00 74.25 148.50 148.50 148.50 148.50 297.00 74.25 74.25

20 50.00 74.25 148.50 148.50 148.50 74.25 74.25

5 1920x1080i (HDTV) 1920 x 1080 59.94 74.18 148.35 148.35 148.35 74.18 74.18

5 60.00 74.25 148.50 148.50 148.50 74.25 74.25

2.3 59.94 27.00 54.00 54.00 54.00 54.00 108.00 27.00 27.00
720x480p (EDTV) 720 x 480
2.3 60.00 27.03 54.05 54.05 54.05 54.05 108.11 27.03 27.03

6.7 720(1440)x480i 59.94 27.00 54.00 54.00 54.00 27.00 27.00

1440 x 480
6.7 (SDTV) 60.00 27.03 54.05 54.05 54.05 27.03 27.03

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Table 2-2 Video Modes (Continued)

2D 3D Structure

Interlaced Progr. Progr.

ALL CEA Only Only ALL CEA Progr. Only Only ALL CEA ALL CEA

17.18 720x576p (EDTV) 720 x 576 50.00 27.00 54.00 54.00 27.00 27.00

21.22 720(1440)x576i 1440 x 576 50.00 27.00 54.00 54.00 54.00 27.00 27.00
(SDTV)

Secondary HDMI video format timings (CEA-861-E)

8.9 59.94 27.00 54.00 54.00 54.00 54.00 108.00 27.00 27.00
720(1440)x240p 1440 x 240
8.9 60.00 27.03 54.05 54.05 54.05 54.05 108.11 27.03 27.03

10.11 59.94 54.00 108.00 108.00 108.00 54.00 54.00

1440(2880)x480i 2880 x 480
10.11 60.00 54.05 108.11 108.11 108.11 54.05 54.05

12.13 59.94 54.00 108.00 108.00 108.00 108.00 216.00 54.00 54.00
1440(2880)x240p 2880 x 240
12.13 60.00 54.05 108.11 108.11 108.11 108.11 216.22 54.05 54.05

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Table 2-2 Video Modes (Continued)

2D 3D Structure

Interlaced Progr. Progr.

ALL CEA Only Only ALL CEA Progr. Only Only ALL CEA ALL CEA

32 23.98 74.18 148.35 148.35 148.35 148.35 296.70 74.18 74.18

32 24.00 74.25 148.50 148.50 148.50 148.50 297.00 74.25 74.25

33 25.00 74.25 148.50 148.50 148.50 148.50 297.00 74.25 74.25

34 29.97 74.18 148.35 148.35 148.35 148.35 296.70 74.18 74.18

34 30.00 74.25 148.50 148.50 148.50 148.50 297.00 74.25 74.25

1920x1080p (HDTV) 1920 x 1080
31 50.00 148.5 297.00 297.00 297.00 297.00 148.5 148.5

16 59.94 148.35 296.70 296.70 296.70 296.70 148.35 148.35

16 60.00 148.5 297.00 297.00 297.00 297.00 148.5 148.5

64 100.00 297.00 297.00 297.00

63 120.00 297.00 297.00 297.00

40 100.00 148.5 297.00 297.00 297.00 148.5 148.5

46 1920x1080i (HDTV) 1920 x 1080 119.88 148.35 296.70 296.70 296.70 148.35 148.35

46 120.00 148.5 297.00 297.00 297.00 148.5 148.5

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Table 2-2 Video Modes (Continued)

2D 3D Structure

Interlaced Progr. Progr.

ALL CEA Only Only ALL CEA Progr. Only Only ALL CEA ALL CEA

60 24.00 59.40 118.80 118.80 118.80 118.80 237.60 59.40 59.40

61 25.00 74.25 148.50 148.50 148.50 148.50 297.00 74.25 74.25

62 30.00 74.25 148.50 148.50 148.50 148.50 297.00 74.25 74.25

1280x720p (HDTV) 1280 x 720
41 100.00 148.5 297.00 297.00 297.00 297.00 148.5 148.5

47 119.88 148.35 296.70 296.70 296.70 296.70 148.35 148.35

47 120.00 148.5 297.00 297.00 297.00 297.00 148.5 148.5

29, 30 1440x576p (EDTV) 1440 x 576 50.00 54.00 108.00 108.00 108.00 108.00 216.00 54.00 54.00

37.38 2880x576p (EDTV) 2880 x 576 50.00 108.00 216.00 216.00 216.00 216.00 108.00 108.00

14.15 59.94 54.00 108.00 108.00 108.00 108.00 216.00 54.00 54.00
1440x480p (EDTV) 1440 x 480
14.15 60.00 54.05 108.11 108.11 108.11 108.11 216.22 54.05 54.05

35.36 59.94 54.00 108.00 108.00 108.00 108.00 216.00 54.00 54.00
2880x480p (EDTV) 2880 x 480
35.36 60.00 54.05 108.11 108.11 108.11 108.11 216.22 54.05 54.05

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Table 2-2 Video Modes (Continued)

2D 3D Structure

Interlaced Progr. Progr.

ALL CEA Only Only ALL CEA Progr. Only Only ALL CEA ALL CEA

48.49 119.88 54.00 108.00 108.00 108.00 108.00 216.00 54.00 54.00

48.49 120.00 54.05 108.11 108.11 108.11 108.11 216.22 54.05 54.05
720x480p (EDTV) 720 x 480
56.57 239.76 108.00 216.00 216.00 216.00 216.00 108.00 108.00

56.57 240.00 108.11 216.22 216.22 216.22 216.22 108.11 108.11

50.51 119.88 54.00 108.00 108.00 108.00 54.00 54.00

50.51 720(1440)x480i 120.00 54.05 108.11 108.11 108.11 54.05 54.05

1440 x 480
58.59 (SDTV) 239.76 108.00 216.00 216.00 216.00 108.00 108.00

58.59 240.00 108.11 216.22 216.22 216.22 108.11 108.11

42.43 100.00 54.00 108.00 108.00 108.00 108.00 216.00 54.00 54.00
720x576p (EDTV) 720 x 576
52.53 200.00 108.00 216.00 216.00 216.00 216.00 108.00 108.00

44.45 720(1440)x576i 100.00 54.00 108.00 108.00 108.00 54.00 54.00

1440 x 576
54.55 (SDTV) 200.00 108.00 216.00 216.00 216.00 108.00 108.00

23.24 720(1440)x288p 1440 x 288 50.00 27.00 54.00 54.00 54.00 54.00 108.00 27.00 27.00

25.26 720(1440)x576i 1440 x 576 50.00 54.00 108.00 108.00 108.00 54.00 54.00

27.28 1440(2880)x288p 2880 x 288 50.00 54.00 108.00 108.00 108.00 108.00 216.00 54.00 54.00

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Table 2-2 Video Modes (Continued)

2D 3D Structure

Interlaced Progr. Progr.

ALL CEA Only Only ALL CEA Progr. Only Only ALL CEA ALL CEA

39 1920x1080i 1920 x 1080 50.00 72.00 144.00 144.00 144.00 72.00 72.00

HDMI Video modes (HDMI VIC)

0x01 4K x 2K 3840 x 2160 30.00 297.00

0x02 4K x 2K 3840 x 2160 25.00 297.00

0x03 4K x 2K 3840 x 2160 24.00 297.00

0x04 4K x 2K 3840 x 2160 24.00 297.00

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2.4 Video Packetizer

This block is responsible for:
■ Pixel repetition (if not already performed in the input video stream and needed by the user)
This is an optional feature that can be configured in coreConsultant.
■ 10-, 12-, and 16-bit packing when in deep color modes
■ YCC 422 remapping according to the HDMI 1.4b specification
■ Clock rate transformation from pixel or repetition clock to the final TMDS clock domain (by means of
FIFOs)
Figure 2-4 depicts a functional diagram of the Video Packetizer block. For more information about the
Video Packetizer registers, refer to Section 5.2.4 on page 168.

Figure 2-4 Video Packetizer Functional Diagram

default_phase
fix_pp_to_last
cx_goto_p0
pp_en
bypass_selector pp_stuffing
output_selector
Input_data
Pixel
Packing output_data
Pixel
Repeater 10, 12, 16
Packing Phase
FSM

16, 20, 24
YCC 422
remap ycc422_size,
ycc422_en

8-bit bypass
bypass_en

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2.5 Color Space Conversion

The Color Space Converter (CSC) is an optional feature that can be configured in coreConsultant. This block
is responsible for carrying out the following video color space conversion functions:
■ RGB to/from YCbCr
■ 4:2:2 to/from 4:4:4 up (pixel repetition or linear interpolation)/down-converter
■ Limited to/from full quantization range conversion

Figure 2-5 Color Space Converter Simplified Block Diagram

g_y_data[15:0] Color Space Converter g_y_data_csc[15:0]

r_cr_data[15:0] r_cr_data_csc[15:0]
b_cb_data[15:0] YCbCr YCbCr YCbCr RGB YCbCr YCbCr b_cb_data_csc[15:0]
4:2:2 4:4:4 4:4:4 4:4:4 4:4:4 4:2:2
de Chroma Color Chroma
de_csc
hsync Interpolation Space Decimation hsync_csc
vsync vsync_csc
pixelclk pixelclk_csc

There are six I2S modes:
■ Standard I2S mode
■ Right-justified I2S mode
■ Left-justified I2S mode
■ I2S Burst 1 mode
■ I2S Burst 2 mode
■ HBR and NL-PCM audio mode
Each I2S interface supports two audio channels. The DWC_hdmi_tx has four I2S interfaces supporting up to
eight audio channels simultaneously at 192 kHz. Each audio sample width can be configured to be from 16
bits up to 24 bits. The I2S_width field of the aud_conf1 register selects the bit width for each right/left
sample. Each right/left channel can carry 1 to N bits (N=16 to 24).
The i2slrck input signal must have the same frequency as the Audio Sampling Rate fs, that is 32 kHz to 192
kHz. The frequency of the i2sclk input clock depends on fs and the INPUTCLKFS register.
For example:
If INPUTCLKFS = 128fs, and fs=32 kHz,
Then i2sclk = 128 x 32 kHz=4096 kHz
While in I2S Format mode (as depicted in Figure 2-7), the most significant bit (MSB) is available on the
second rising edge of ii2sclk following an ii2slrclk transition. The other bits up to the least significant bit
(LSB) are then transmitted in order. Depending on word length, ii2sclk frequency, and sample rate, there
may be unused ii2sclk cycles between the LSB of one sample and the MSB of the next.

Figure 2-7 I2S Format

1 / fs

Left Channel Right Channel

i2slr ck

i 2sclk

i2sdata 1 2 3 N-2 N -1 N 1 2 3 N -2 N -1 N
1

MSB LSB MSB LSB

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While in Left Justified Format mode (as shown in Figure 2-8), the MSB is available on the first rising edge of
i2saudioclk following an ii2slrclk transition. The other bits up to the LSB are then transmitted in order.
Depending on word length, ii2sclk frequency, and sample rate, there may be unused ii2sclk cycles before
each ii2slrclk transition.

Figure 2-8 I2S Left Justified Format

1 / fs

Left Channel

i2slr ck Right Channel

i2sclk

i2sdata 1 2 3 N -2 N- 1 N 1 2 3 N-2 N -1 N
1

MSB LSB MSB LSB

While in Right Justified Format mode (as shown in Figure 2-9), the LSB is available on the last rising edge of
ii2sclk before an ii2slrclk transition. All other bits are transmitted before, MSB first. There may be unused
ii2sclk cycles after each ii2slrclk transition, depending on word length, ii2sclk frequency, and sample rate.

Figure 2-9 I2S Right Justified Format

1 / fs
Left Channel
Right Channel
i2slr ck

i2scl k

i 2sdata 1 2 3 N -2 N-1 N 1 2 3 N -2 N- 1 N
1

M SB LSB M SB LSB

While in Burst 1 Format mode (Figure 2-10), the left channel MSB is available on the second rising edge of
ii2sclk, following a rising edge of ii2slrclk. Right channel data immediately follows left channel data.
Depending on word length, ii2sclk frequency, and sample rate, there may be unused ii2sclk cycles between
the LSB of right channel data and the next sample.

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Figure 2-10 Burst 1 Format

1 / fs

i2sl r ck Left Channel Right Channel

i2scl k

i2sd ta 1 2 3 N -2 N- 1 N 1 2 3 N - 2 N-1 N 1 2
1

MSB LSB MSB LSB M SB

While in Burst 2 Format mode (Figure 2-11), the left channel MSB is available on the first rising edge of
ii2sclk, following a rising edge of ii2slrclk. Right channel data immediately follows left channel data.
Depending on word length, ii2sclk frequency, and sample rate, there may be unused ii2sclk cycles between
the LSB of right channel data and the next sample.

Figure 2-11 Burst 2 Format

1 / fs

i2slr ck Left Channel Right Channel

i 2sclk

i2sdata 1 2 3 N -2 N-1 N 1 2 3 N -2 N-1 N 1 2

MSB LSB MSB LSB MSB

For configuration details, refer to the Audio Sampler Registers described in Section 5.2.8 on page 244.

HBR and NL-PCM Support for I2S Interface

The I2S interface is not specifically designed for HBR and NL-PCM streaming. Hence, you need to manually
map the streaming, by following these steps:
1. Split the stream (768 kHz) in four sub-streams by sending the stream to a FIFO with four outputs of
192 kHz each.
Each sub-stream consists of a pair of samples.
2. Apply the i2sclk clock to the I2S interface with a frequency of 24.576 MHz.
3. Set the I2S sample width to 21 bits by using the aud_conf1.i2s_width bit field register.
This sample is sampleI2S[20:0].

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4. Configure the aud_conf2 register to HBR mode by using the HBR bit (bit 0).
5. Configure the I2S interface by using the aud_conf0.i2s_in_en bit field register.
Enable all the four channels so that each channel carries a pair of samples.
6. Map the I2S data sample, sampleI2S[20:0], in the following way:
sampleI2S[20:0] = {B,P,C,U,V, dataHBR[15:0]}
(Where B,P,C,U,V are IEC61937 parameters, and dataHBR[15:0] is the actual HBR sample data.)
7. Ensure that the I2S_in_en[3:0] channels adhere to the following arrangement:

Left Channel Right Channel

I2S_in_en[0] Sample 1 Sample 2

I2S_in_en[1] Sample 3 Sample 4

I2S_in_en[2] Sample 5 Sample 6

I2S_in_en[3] Sample 7 Sample 8

(B or M associated samples for (W associated samples for

IEC61937 NL-PCM) IEC61937 NL-PCM)

8. The input sample sequence is such that the line transports frames (1 frame = 2 samples), as indicated
in the following table:

Frame Line
Sample 1, 2 I2S_in_en[0]
Sample 3, 4 I2S_in_en[1]
Sample 5, 6 I2S_in_en[2]
Sample 7, 8 I2S_in_en[3]
Sample 9, 10 I2S_in_en[0]
Sample 10, 11 I2S_in_en[1]
... ...

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2.6.3 S/PDIF Interface

The S/PDIF audio input interface is compatible with the S/PDIF Linear and Non-linear (IEC90658 and
IEC61937) Digital Audio specification. The S/PDIF interface is a consumer version of the AES/EBU
interface; it is commonly used to move digital audio between pieces of consumer electronic equipment, such
as a DVD player and a surround-sound receiver.
The two data formats (S/PDIF and AES) and data rate are compatible with each other, differing only in the
electrical and physical connectors. The S/PDIF uses ispdifclk to sample the ispdifdata data and store it in a
29-bit width variable depth audio FIFO. The S/PDIF uses ispdifclk to sample the ispdifdata data, storing it
in a 29-bit width, 16-words depth audio FIFO.

ispdifclk Input Clock Requirements

The DWC_hdmi_tx only supports 512 x fs. The ispdifclk at the input must be synchronous with respect to
the audio stream; its frequency must be an exact multiple of the original audio bit stream.
For example, with fs = 32 kHz:
■ spdif rate = 64 x fs = 2048 kHz
■ Bi-phase Mark Code (BMC) = 2 x 64 x fs = 4096 kHz
The audio sampling rate for the correct Data Recovery Unit (DRU) operation on the S/PDIF interface is as
follows:
4 x 2 x 64 x fs = 512 x fs = 16384 kHz

Note When you select the Bypass S/PDIF DRU in coreConsultant, the 512xfs rate does not apply.
In this case, ispdifclk must be 128xfs and ispdifdata must be synchronous with it.

Table 2-4 shows the S/PDIF bit rates corresponding to various common audio sampling frequencies and the
required ispdifclk rate. The symbol rate of the S/PDIF signal is actually twice as fast as the bit rate because
each bit is encoded as two states (bi-phase channel coding).

Table 2-4 Data Rate, Bi-Phase Channel Coding Rate, Required ispdifclk Rate

Audio Sampling Rate S/PDIF Bit Rate Bi-phase Channel Coding ispdifclk Rate fs (kHz)
fs (kHz) 64xfs (Mbps) Rate 2x64xfs (MHz) 4x2x64xfs=512xfs (MHz)
32 2.048 4.096 16.384
44.1 2.8224 5.6448 22.5792
48 3.072 6.144 24.576
88.2 5.6448 11.2896 45.1584
96 6.144 12.288 49.152
176.4 11.2896 22.5792 90.3168
192 12.288 24.576 98.304
768a 49.152 98.304

a. Only available when HBR_ON_SPDIF is enabled.

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2.6.4 Generic Parallel Audio (GPA) Interface

The Generic Parallel Audio interface fetches audio samples for the enabled channels approximately at the
configured audio rate. It supports L-PCM, NL-PCM, and HBR audio. No audio clock is required. Software
configures the ACR information, N, and CTS, and the samples are clocked with igpaclk, which can be tied to
the system clock.
When a data transfer starts (igpavalid = 1), the source must contain enough samples to create at least one
audio packet. If this does not happen, the transmitted audio becomes misaligned. Also, the first transmitted
sample after reset must be the sample for Audio Channel 1, left sample, and the audio source must maintain
the alignment.

2.6.4.1 Timing information

The igpavalid signal must go low when no sample is required and remains high when the HDMI TX
activates the ogpadatareq signal again. There is no restriction in term of the cycle between the ogpadatareq
and the igpavalid. However, it must be assured that data can be transferred correctly; the maximum is two
cycles.
Figure 2-12 shows a correct transfer that is able to meet the HDMI audio flow.

Figure 2-12 Generic Parallel Audio Interface Timing Diagram

igpaclk

ogpadatareq

igpavalid

igpadata[28]

igpadata[27:0] 0 1 2 ... ...190 191 0 1 2 ... ... 190 191

Figure 2-13 Data Sample Request De-Assertion Timing Diagram

igpaclk

ogpadatareq Reqxxxx
1 cycle after or more
igpavalid

igpadata[28]

igpadata[27:0] 95 96 97 98 99 x 100 101

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2.6.4.2 Data Mapping Examples

The number of channels is configurable between 2 up to 8. Similar data mapping rules apply for 3, 4, …,8
channels.

In Table 2-5 and Table 2-6, the data from bits 28:24 can be omitted from the input and inserted
Note by the DWC_hdmi_tx controller. This functionality is only valid when the GP Audio interface is
selected (AUDIO_IF = GPAUD [6]) and for Linear PCM audio only.

Table 2-5 L-PCM Two-Channel Data Mapping

igpadata Bit

Sample No. 28 27 26 25 24 23 ... 8 7 ... 0

0 B.0. P C U V CH1LEFT

1 B.0. P C U V CH2RIGHT

2 B.0. P C U V CH1LEFT

3 B.0. P C U V CH2RIGHT

4 B.0. P C U V CH1LEFT

5 B.0. P C U V CH2RIGHT

6 B.0. P C U V CH1LEFT

7 B.0. P C U V CH2RIGHT

0x00

L-PCM 16-bit sample

L-PCM 24-bit sample

Table 2-6 L-PCM Eight-Channel Data Mapping

igpadata Bit

Sample No. 28 27 26 25 24 23 ... 8 7 ... 0

0 B.0. P C U V CH1LEFT

1 B.0. P C U V CH2RIGHT

2 B.1. P C U V CH3LEFT

3 B.1. P C U V CH4RIGHT

4 B.2. P C U V CH5LEFT

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Table 2-6 L-PCM Eight-Channel Data Mapping

igpadata Bit

Sample No. 28 27 26 25 24 23 ... 8 7 ... 0

5 B.2. P C U V CH6RIGHT

6 B.3. P C U V CH7LEFT

7 B.3. P C U V CH8RIGHT

0x00

L-PCM 16-bit sample

L-PCM 24-bit sample

Table 2-7 NL-PCM Data Mapping

igpadata Bit

Sample No. 28 27 26 25 24 23 ... 8 7 ... 0

0 B.0. P C U V DATA 0 0x0000

1 B.0. P C U V DATA 1 0x0000

2 B.0. P C U V DATA 2 0x0000

3 B.0. P C U V DATA 3 0x0000

4 B.0. P C U V DATA 4 0x0000

5 B.0. P C U V DATA 5 0x0000

... B.0. P C U V ... 0x0000

n B.0. P C U V DATA n 0x0000

NL-PCM 16-bit sample

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2.6.4.3 CTS Calculation

Because there is no audio clock carried through the HDMI link, only the TMDS clock is used. Software sets
the CTS/N with a value taken from Table 2-8, which shows the CTS and N value for the supported
standard. All other TMDS clocks are not supported; the TMDS clocks divided or multiplied by 1,001
coefficients are not supported.

Table 2-8 N and CTS for 8-Bit Color Depth

TMDS Clock (MHz)

25.2 27 54 74.25 148.5 297

Fs (kHZ) N CTS N CTS N CTS N CTS N CTS N CTS

32 4096 25200 4096 27000 4096 54000 4096 74250 4096 148500 3072 222750

44.1 6272 28000 6272 30000 6272 60000 6272 82500 6272 165000 4704 247500

48 6144 25200 6144 27000 6144 54000 6144 74250 6144 148500 5120 247500

88.2 12544 28000 12544 30000 12544 60000 12544 82500 12544 165000 9408 247500

96 12288 25200 12288 27000 12288 54000 12288 74250 12288 148500 10240 247500

176.4 25088 28000 25088 30000 25088 60000 25088 82500 25088 165000 18816 247500

192 24576 25200 24576 27000 24576 54000 24576 74250 24576 148500 20480 247500

768 Used for HBR audio only. N and CTS configured for Fs=192 kHZ (1/4th ACR value per specification)

To support the deep color mode and/or 3D video modes, the TMDS clock is multiplied by 4, 2, 1.5, or 1.25,
depending on the mode. In this case, the CTS value must also follow the same ratio.

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2.6.5 AHB Audio DMA Interface

The audio direct memory access (DMA) interface is intended for advanced systems running 32-bit CPU SoC
solutions with an AHB. This is useful in systems where a DSP handles audio processing. In these systems,
sending the incoming audio samples directly to the memory provides a cleaner architecture to the SoC,
without the overhead of converting several audio standards.

Figure 2-14 Audio DMA Block Diagram

Audio DMA BUFFER

DMA FIFO
(Fixed 16 samples
(Programmable depth) FIFO Sync
per channel)
29 29

8
AHB Master FIFO Empty
Interrupt

DMA
Engine

hclk tmdsclk

The audio DMA block combines an AHB master interface with a FIFO to perform direct memory access to
audio samples stored in a system memory.
The DMA engine is configurable through programmable software registers to perform autonomous burst
reading on a configured memory range.
For more information on the CTS/N values, see “CTS Calculation” on page 53.

2.6.5.1 AHB Master

The AHB master is compliant with the AMBA AHB Specification, Revision 2.0 from ARM. It supports the
following features:
■ Capable of operating on a bus with multiple masters and slaves
■ 32-bit data transfer
■ OKAY, ERROR, RETRY, and SPLIT slave responses
■ Rescheduling of burst requirements
■ IDLE, NONSEQ, and SEQ transfer types
■ Incremental burst modes: INCR, INCR4, INCR8, and INCR16 fixed-beat bursts
■ Configurable Master burst lock mechanism

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The following features are not supported:

■ Write transaction
■ Protection control
■ BUSY transfer type
■ Wrapping burst

Data Organization in System Memory

The AHB master block fetches the samples from system memory. The Audio Samples are organized
according to the channel allocation. For example, channel 0, 1, 3, and 5 are enabled (0 and 1 are always
enabled). The Audio Samples must be organized in the system memory as presented in the following tables:
Table 2-9 Audio Sample Arrangement in System Memory

Position Sample Channel

0 n-1 0

1 n-1 1

2 n-1 3

3 n-1 5

4 n 0

5 n 1

6 n 3

7 n 5

... ... ...

Table 2-10 Data Arrangement in System Memory for L-PCM (24 bits)

Bit Description

28 B – IEC B Bit

27 P – Parity Bit

26 C – Channel Status Bit

25 U – User Data Bit

24 V – Validity Bit

[23:0] Audio Sample Data

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Table 2-11 Data Arrangement in System Memory for L-PCM (16 bits) and NL-PCM (16 bits)

Bit Description

28 Bx – IEC B Bit

27 P – Parity Bit

26 C – Channel Status Bit

25 U – User Data Bit

24 V – Validity Bit

[23:8] Audio Sample Data

[7:0] 0x00

2.6.5.2 DMA Engine

The DMA engine is responsible for requesting burst transfers to the AHB master, taking into account the
FIFO threshold and register settings.

Functional Behavior
The engine:
■ Commands read requests to start the burst in the initial address with the size sufficient to fill the
FIFO (the size of the FIFO is a parameter in the audio DMA core)
After this first request, the DMA engine performs subsequent burst requests (incrementing
accordingly ohaddr[31:0] and determining correct ohburst[2:0]) towards final_addr[31:0] configured
at the register bank and taking into account the FIFO depth and fifo_threshold[7:0] configuration.
■ Stops operation upon ERROR slave response, signaling ointerror interrupt and staterror signal
■ Issues ointdone interrupt when it reaches final address reading or is stopped upon user request
■ Automatically starts new burst requests until the final_addr[31:0] is reached
The DMA engine is either stopped by the user or an error condition appears at the slave response.

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DMA Operation
Normal operation of the DMA engine is as follows:
1. The enable_hlock, incr_type[1:0], burst_mode, fifo_threshold[7:0], initial_addr[31:0], and
final_addr[31:0] are configured according to desired DMA operation.

Note The configured values must have the final_addr[31:0] value greater than the initial_addr[31:0]
value.

2. To start the audio DMA operation, a ‘1’ is written to start_dma_transaction.

3. The DMA engine starts the operation.
4. The DMA requests data either until enough audio samples are read to fill the FIFO, or until the
provided buffer is consumed. While DMA is reading samples from the AHB master and writing
samples to the Audio FIFO, a data fetch request from the internal frame composer block might
happen at the Audio FIFO interface, diminishing the number of samples in the FIFO.
5. When the number of samples in the Audio FIFO is lower than the configured fifo_threshold[7:0], the
DMA engine requests a new burst request to the AHB master interface with:
ohaddr[15:0] = last address in step 5);
ohburst[2:0] = INCR;
mburstlength[8:0] = 2^HDMI_TX_AHBDMAAUD_FIFO_ADDRWITH - fifo_threshold[7:0];
6. Steps 4 and 5 continue until the final_addr[31:0] is reached.

In the last burst request, the DMA engine calculates the mburstlength[10:0] such that
Attention
the last requested read position is the final_addr[31:0].

7. After completion of the DMA operation, the DMA engine issues the ointdone interrupt signaling end
of operation.
Variations of the DMA engine’s behavior occur when fixed-beat, incremental bursts are used by
INCR4/INCR8/INCR16 burst selects. When these burst modes are used, the DMA uses the selected transfer
size for the bulk of its transfers. It uses INCR transfers to resume from RETRY/SPLIT, and to finalize the
transfers if any one of the fields initial_addr[31:0], final_addr[31:0], or fifo_threshold are not aligned with
the selected burst size.
The following are exceptions to the described DMA behavior:
■ When a user requests end stop_dma_transaction, the DMA engine stops at the end of the current
burst operation and signals its completion with an ointdone interrupt.
■ When the AHB slave sends an error response, the DMA engine stops the current operation and
signals ointerror and ointdone interrupts.

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Transfer Data, Package, and Word

One transfer data can be composed of several transfer packages, and one transfer package can be composed
of one or several transfer bursts. One transfer burst can be composed of several transfer words. Figure 2-15
shows the transfer data structure for a fixed-beat, incremental burst.

Figure 2-15 Transfer Data Constitution for Unspecified Length, Incremental Burst

Package 1 Package M

burst1 burst2 ... burstN ... burst1 burst2 ... burstN

word1 word2 ... wordL

L = 4(for INCR4), 8(INCR8), 16(INCR16)

Figure 2-16 on page 58 depicts the transfer data structure for an unspecified burst length.

Figure 2-16 Transfer Data Constitution for Fixed-Beat, Incremental Burst

Package 1 Package M

burst1 ... burst1

word1 word2 ... wordL

L = unspecified number for INCR

Figure 2-17 illustrates the DMA state machine.

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Figure 2-17 DMA FSM Diagram

!s
DMA IDLE ta
n r t_
tio dm
ac
ns a_
tra tra
a_ n
dm sa
r t_ ct
sta ! start_dma_transaction ion

!FIFO below threshold AND

stop_dma_transaction
DMA REQ DMA STOP DMA ERR

Final address reached

OR
FIFO below threshold: stop_dma_transaction
AND pack finish
AND HRESP != ERR

DMA XFER AHB Master receives HRESP=ERR

HRESP != ERR AND

!final address AND
!AHB DMA FIFO full* !stop_dma_transaction AND
AHB DMA FIFO full* pack finish

DMA DONE

In this diagram, the FSM assumes the following states.

FSM DMA IDLE
The transaction has not started.
■ The operation request is written into start_dma_transaction.
■ The state switches from DMA IDLE to DMA REQ.

DMA REQ
The DMA is waiting in this state for the HDMI interface to consume samples.
■ When DMA FIFO goes below threshold, DMA calculates a new start address and burst length, and
the state changes from DMA REQ to DMA XFER.
■ If stop_dma_transfer is received at DMA REQ, the state changes from DMA REQ to DMA STOP.

DMA XFER
The DMA commands the AHB Master to perform data transfers. There are three possible transitions that
can occur from this state:
■ If an error occurs in the AHB bus (HRESP=ERROR), the FSM goes to the DMA ERR state.
■ If the final address is reached or a stop_dma_transaction is received, the FSM goes to the DMA STOP
state.

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■ If the AHB Master sends a pack finish signal, the FSM goes to state DMA DONE.
A pack is a block transfer of a maximum of 256 words. It can be lower due to the proximity of the 1K
address boundary, end of software buffer, or availiable headroom on the AHB DMA FIFO.

DMA DONE
The AHB DMA monitors the expected fill state of the AHB Audio DMA FIFO.
■ If the AHB Audio DMA FIFO is not full, the FSM goes to the DMA XFER state to request samples
from the AHB bus until enough samples are read to fill the FIFO.
■ If the AHB Audio DMA FIFO is full, the DMA FSM proceeds to the DMA REQ state to wait for a
below threshold event.

Note If samples are retrieved from the AHB Audio DMA FIFO during a sample read from the AHB
Bus, the AHB FIFO full event does not occur.

DMA STOP
A stop_dma_transaction signal is received.
■ The FSM waits for an inverted start_dma_transaction signal from the register bank as an
acknowledgement of a stop_dma_transaction signal.
■ When the start_dma_transaction signal inverts, the FSM goes to the state DMA IDLE.

2.6.5.3 Audio FIFO

This block contains a FIFO with the HDMI_TX_AHBDMAAUD_FIFO_ADDRWITH configuration
parameter.
The statthrfiffoempty flag is a version of the FIFO empty, that is active whenever the amount of samples in
the FIFO is smaller than the number of audio channels enabled.

2.6.5.4 CTS Calculation

Because there is no audio clock carried through the HDMI link. Only the pixel clock is used. The CTS/N has
to be set by software with value taken in the following table. Table 2-8 shows the CTS and N value for the
supported standard. All other TMDS clocks are not supported; the TMDS clocks divided or multiplied by
1,001 coefficients are not supported.

Table 2-12 N and CTS for 8-Bit Color Depth

TMDS Clock (MHz)

25.2 27 54 74.25 148.5 297

Fs N CTS N CTS N CTS N CTS N CTS N CTS

(kHZ)

32 4096 25200 4096 27000 4096 54000 4096 74250 4096 148500 3072 222750

44.1 6272 28000 6272 30000 6272 60000 6272 82500 6272 165000 4704 247500

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Table 2-12 N and CTS for 8-Bit Color Depth

TMDS Clock (MHz)

25.2 27 54 74.25 148.5 297

48 6144 25200 6144 27000 6144 54000 6144 74250 6144 148500 5120 247500

88.2 12544 28000 12544 30000 12544 60000 12544 82500 12544 165000 9408 247500

96 12288 25200 12288 27000 12288 54000 12288 74250 12288 148500 10240 247500

176.4 25088 28000 25088 30000 25088 60000 25088 82500 25088 165000 18816 247500

192 24576 25200 24576 27000 24576 54000 24576 74250 24576 148500 20480 247500

768 Used for HBR audio only. N and CTS configured for Fs=192kHZ (1/4th ACR value per spec)

To support the deep color mode and/or 3D video modes, the TMDS clock is multiplied by 4, 2, 1.5, or 1.25,
depending on the mode. In this case, the CTS value must also follow the same ratio.

2.6.5.5 Start-Stop, Auto-Start Mechanism

The HDMI audio transmission requires that a constant stream of audio samples is transmitted on the
DWC_hdmi_tx controller at the maximum rate of 1.536 Msamples/second (eight audio channels at 192
kHz). To achieve this worst-case constant stream, the DWC_hdmi_tx host system must be able to intercept
the done interruption, reconfigure the Start and Stop addresses, and re-issue a start_dma_transaction within
approximately 72μs.
The time gap between reconfigurations is obtained with the following formula:

HDMI_TX_AHBDMAAUD_FIFO_ADDRWITH
2 – 2 x Number of audio channels enabled
tfifo_hold = Number of audio channels enabled
Fs

The worst case scenario for safe operation (72μs) is achieved for an AHB audio DMA FIFO depth of 128
positions, an audio sampling frequency of 192 kHz, and eight audio channels enabled.
To increase this time gap, the DWC_hdmi_tx core includes a mechanism for a dual buffer and for
auto-starting the audio transfer. To use the auto-start mechanism, it is required to set (1’b1) the Appendix
5.2.10.14, “ahb_dma_conf2”.autostart_enable bit field register and configure two sets of audio sample
buffers on the ahb_dma_straddr_set0_*, ahb_dma_stpaddr_set0_*, ahb_dma_straddr_set1_*, and
ahb_dma_stpaddr_set1_* registers.
This mechanism enables that the time required between reconfigurations be only limited by the size of the
provided buffer (final_address – initial_address + 1) and is calculated by the following formula:

Number of audio samples in provided buffer

treconfig_autostart = Number of audio channels enabled
Fs

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Two operational modes are implemented and controlled through the ahb_dma_conf2.autostart_loop
register bit field. In the default mode (ahb_dma_conf2.autostart_loop set to 1‘b1), blind loop,
non-acknowledged operation is allowed. This mode targets a use case with static software buffers and
guaranteed audio samples throughput.
When autostart_loop is disabled (1’b0), you are required to acknowledge all buffer set usage, by updating at
least the LSB of the buffer stop address (ahb_dma_stpaddr_set0_0 or ahb_dma_stpaddr_set1_0). This flow
ensures that the hardware never uses a dirty buffer and targets use cases where the system is unable to
ensure the required audio data throughput at all times.
This bit has no effect if the autostart_enable is clear (1‘b0).
Figure 2-18 on page 63 and Figure 2-19 on page 64 shows the Set0 and Set1 audio sample buffers and the
auto-start mechanism.
Figure 2-20 on page 65 and Figure 2-21 on page 66 illustrate the programming flow for the auto-start
mechanism when Loop mode is enabled or disabled.

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Figure 2-18 Dual Buffer, Auto-Starting Audio Transfer (Loop Mode Enabled)

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Figure 2-19 Dual Buffer, Auto-Starting Audio Transfer (Loop Mode Disabled)

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Figure 2-20 Auto-Start Programming Model – Loop Mode Enabled, Static Buffer Location

Write
ahb_dma_conf2.autostart_enable = 1‘b1

Write
ahb_dma_conf2.autostart_loop = 1‘b1

Define Set 0 Buffer

Write ahb_dma_straddr_set0_0 to
ahb_dma_stpaddr_set0_3

Define Set 1 Buffer

Write ahb_dma_straddr_set1_0 to
ahb_dma_stpaddr_set1_3

Issue start_dma_transaction

Yes ■ Software can trigger system to

Done Interrupt
received? update the consumed buffer content
■ Software can read ahb_dma_status
to find out which buffer has been
No consumed

You can use this flow using dynamic allocated software buffers, but you must ensure that you
Note update the start and stop addresses before the next done interruption as hardware is not
checking if the buffers have been updated.

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Figure 2-21 Auto-Start Programming Model – Loop Mode Disabled

Write
ahb_dma_conf2.autostart_enable = 1‘b1

Write
ahb_dma_conf2.autostart_loop = 1‘b0

Define Set 0 Buffer

Write ahb_dma_straddr_set0_0 to
ahb_dma_stpaddr_set0_3

Define Set 1 Buffer

Write ahb_dma_straddr_set1_0 to
ahb_dma_stpaddr_set1_3

Issue start_dma_transaction

■ If ahb_dma_status.autostart_status is clear
(consuming buffer 0), update Set 1 Buffer
Yes (ahb_dma_straddr_set1_0 to
Done Interrupt ahb_dma_stpaddr_set1_3) — update at least
received? ahb_dma_stpaddr_set1_0
■ If ahb_dma_status.autostart_status is set
(consuming buffer 1), update Set 0 Buffer
No (ahb_dma_straddr_set0_0 to
ahb_dma_stpaddr_set0_3) — update at least
ahb_dma_stpaddr_set0_0

If the software is late updating the addresses of the Set 0 and/or Set 1 buffers, hardware
Note disables autostart_enable and the audio stream becomes lost. In this scenario, the AHB audio
DMA stops and requires a restart (clear the FIFOs through ahb_dma_conf0.sw_fifo_rst,
re-configure autostart_enable, start/stop addresses, and issue a start_dma_transaction).

The following exception handling applies, when ahb_dma_conf2.autostart_enable is set (1'b1):

■ When an AHB error occurs, the auto-start automatically clears (1‘b0).
■ When a stop_dma_transaction command is received, the auto-start automatically clears (1‘b0).
■ When a software reset is requested through ahb_dma_conf0.sw_fifo_rst or
mc_swrstzreq_2.ahbdmaswrst_req, the auto-start auto clears (1‘b0).

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■ If the autostart_loop is disabled (1'b0) and the controller detects that the next software buffer to be
used is not up to date (checked at the time of the done interruption), the autostart_enable
automatically clears (1'b0).

This feature reduces the overhead on the reconfiguration of the AHB audio DMA, but the
Note DWC_hdmi_tx host system must always ensure that samples reach the AHB audio DMA
master within the time gap determined tfifo_hold.

2.6.5.6 PCUV Insertion

The DWC_hdmi_tx controller can be configured through the ahb_dma_conf0.insert_pucv bit field register,
which inserts the PCUV (Parity, Channel status, User bit, Valid and B bits) data onto the outgoing audio
packets. When insert_pucv is active (1‘b1), any PCUV input data is ignored, and the parity and B pulse bits
are generated in run time, while the Channel status, User bit, and Valid bit are retrieved from the
fc_audschnls0 to fc_audschnls8, fc_audsu, and fc_audsv registers. When insert_pucv is inactive (1‘b0), the
data is sourced from the AHB audio DMA data stream.
This feature is only available only for Linear PCM audio transmission.

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2.7 Frame Composer

This block is responsible for assembling video, audio, and data packets in a consistent frame that are
streamed to the HDCP cipher and then finally to the HDMI TX PHY.
The HDMI standard precisely describes the packet insertion timing and distribution that must be followed
to correctly compose an HDMI TMDS (transition minimized differential signaling) stream. In this context,
there are data island packets that— when available (ready for insertion in output stream)—have higher
priority over others. Two packet descriptor queues are responsible for prioritizing packet insertion.
The higher priority packets are described in Table 2-13. These packets are inserted in the output stream as
soon as data to compose them is available (refer to the HDMI 1.3a standard).

Table 2-13 High Priority Data Island Packets

Packet Description

Audio Clock Regeneration (ACR) Indicates to sink device the N/CTS values that should be used in the ACR process

Audio Sample (AUDS) Transports L-PCM and IEC 61937 compressed audio

General Control (GCP) Indicates Color Depth, Pixel Packing phase, and AV mute information to sink
device

The packets described in Table 2-14 can be considered as low priority packets—even though they have
precise timing insertion—because their insertion timing is large (for example, one per frame or one per two
frames without specific location for some of the packet types and on user request transmit for others).

Table 2-14 Low Priority Data Island Packets

Packet Description

Audio Content Protection (ACP) Used to convey content-related information about the active audio stream
transmitted

Audio InfoFrame (AUDI) Indicates characteristics of the active audio stream by using IEC 60958
channel status bits, IEC 61937 burst info, and/or stream data (if present).

Null (NULL) Ignored by sink devices.

International Standard Recording Code Refer to HDMI 1.3a section 5.3.8.

(ISRC1/ISRC2)

Vendor Specific (VSD) InfoFrame According to CEA-861-E standard.

AVI infoFrame (AVI) Video information from source to sink.

Source Data Product Descriptor (SPD) Name and product type of the source device. MPEG (MPEG) Source
infoFrame InfoFrame packets (optional, implementation discouraged by CEA-861-E
Section 6.7). Describes several aspects of the compressed video stream
that were used to produce the uncompressed video.

The Frame Composer distributes and assembles the data island packets according to the module register
bank configuration. The block allows extended control periods to appear with a certain programmed

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spacing. The Frame Composer uses two packet buffers that allow a packet to be composed while another is
being sent to the output HDMI stream.
Packet requests are inserted into the packet queues by a data island flexible scheduler. The HDMI
specification requires that packet distribution and insertion timing correctly compose an output HDMI
TMDS stream. In this context, there are data island packets that are sent on data availability, while others
are sent once per frame or once per two frames. and finally others that are sent on user request.
Classification of the packets according to this insertion timing is described in Table 2-15.

Table 2-15 Packet Classification

Packet Classification

Audio Clock Regeneration (ACR) Sent on data availability.

Audio Sample (AUDS) Sent on data availability (precede ACR if present).

Audio Content Protection (ACP) On user request or automatic insertion.

Audio InfoFrame (AUDI) Once per two frames.

Null (NULL) On user request or automatic insertion to fill Data Island period.

General Control (GCP) Once per frame.

International Standard Recording Code On user request.

(ISRC1/ISRC2)

Vendor Specific (VSD) InfoFrame On user request or automatic insertion.

AVI infoFrame (AVI) Once per frame.

Source Data Product Descriptor (SPD) infoFrame On user request or automatic insertion.

The Data Island Scheduler (DIS) handles packet distribution in the Frame Composer. The DIS is a round-
robin (RDRB) state machine that is able to schedule packet insertion on an input video frame or line basis.
The DIS is fully configurable and can schedule any packet type to be inserted at a given input video frame
rate or input video line rate.
While determining packet distribution on an input video frame or line basis, the DIS schedules the packets
to be inserted in the output HDMI stream by inserting the packet descriptor in the corresponding packet
priority queue, according to packet priority classification.
After the packet descriptor has been inserted in the packet priority queues, the Data Island Packer (DIP) is
responsible for assembling and sequencing the packets for output HDMI stream insertion.
Dedicated ECC generators and checksum byte-wide sum hardware generate the BCH ECC parity codes and
infoFrames checksums for all the data islands packets.
The content of GCP, ISRC1/2, VSD, AVI, and SPD packets are configured through the registers bank
starting at address 0x1000. For more detailed information about the Frame Composer registers, refer to
Section 5.2.5 on page 174.

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2.8 HDCP Encryption Engine

Attention This feature must be configured and requires a separate license.

HDCP is designed to protect the transmission of audio-visual content between an HDCP Transmitter and
an HDCP Receiver. The system also allows for HDCP Repeaters that support downstream HDCP-protected
interface ports. The HDCP system allows up to seven levels of HDCP Repeaters and as many as 128 total
HDCP devices, including HDCP Repeaters, to be attached to an HDCP-protected interface port.
The authentication protocol enables the HDCP Transmitter to verify that a given HDCP Receiver is licensed.
With the legitimacy of the Receiver determined, encrypted HDCP content is transmitted between the two
based on shared secrets established during authentication. In the event that legitimate devices are
compromised to permit unauthorized use of the content, renewability allows an HDCP Transmitter to
identify such compromised devices and prevent the transmission of the content.
The implemented HDCP functionality is compliant with HDCP revision 1.4. The HDCP transmitter
implements the three layers of the HDCP cipher, including LFSR and other functions required to generate
the encryption key bytes that are then XORed with the data.
To perform the authentication steps of the HDCP protocol, the DWC_hdmi_tx includes a set of registers and
interrupts. It also includes AV mute capabilities via a mapped register configuration. HDCP keys and a
revocation list can be read from external ROM by a dedicated interface.
For more information about the HDCP authentication protocol, refer to Appendix A, “HDCP Application
Note” on page 323.
Figure 2-22 on page 71 shows a block diagram of the DWC_hdmi_tx with HDCP.

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Figure 2-22 Top-Level Diagram of HDMI TX Controller with HDCP

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2.8.1 Controller Unit

The DWC_hdmi_tx implements all the HDCP protocol defined by Digital Content Protection LLC
specification for the HDCP system.
The Controller Unit starts by authenticating the slave device through the I2C link after the system has been
properly configured and the RX detection command has been sent to the DWC_hdmi_tx.
The DWC_hdmi_tx must have its clock management block configured, and the HDCP configuration
variables should be set before the RX detection flag has been asserted. After authentication, the
DWC_hdmi_tx starts encrypting the TMDS channels and signals the slave device when it begins this
process. Periodically, the HDCP port is checked for integrity. This check ensures that the content is being
properly decrypted in the slave side.

2.8.2 OESS Window of Opportunity Generation

The HDCP controller is able to change the length of the HDCP window of opportunity in the OESS mode
through register 0x500a, a_oesswcfg.

Figure 2-23 OESS Window of Opportunity Programming

clk

dataen Signal polarity is active high

VSYNC Signal polarity is active high

wpesspffst[7:0] 8

OESS
OFFSET 0 32 .... 3 2 1 1
COUNTER

OESS
WINDOW

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2.8.3 Random Number Generation Interface

This external interface is needed for a random number generation. You can bypass this interface by using
the configuration as described in “HDCP AN Registers” on page 301.
The random numbers should be in such a way that in 1 million power up cycles, there are no duplicate An
values1 (as described in the HDCP Specification, page 53):
The bits of influence shall come from a source of reasonable variability or entropy. A reasonable level
of variability or entropy is established if, given 1,000,000 different power up cycles on the HDCP
transmitter logic such that the amount of time from power up to the initial authentication were
controlled precisely enough to eliminate any variability from the free running of the cipher before
initial authentication (i.e. the number of pixel clocks applied to the cipher in State E0 remains
unchanged between different tests), and the An values from the first authentication attempt after the
additional influence has been applied (using different content streams if this influence comes from
the content stream), the probability of there being any duplicates in this list of 1,000,000 An values
collected is less than 50%. This corresponds to about 40 (considering one million is about 2^20)
random bits out of the 64 (or equivalent if the bits are biased).
An (incomplete) list of sources of entropy might include:
a. A true Random Number Generator or analog noise source, even if a poor (biased) one
b. A pseudo-random number generator (PRNG), where the state is stored in non-volatile memory
after each use. (That is, every power on continues the sequence—it does not produce the same
sequence each time.) Flash memory or even disk is usable for this purpose as long as it is
reasonably secure from tampering. The hdcpRngCipher combined with tamper-resistant, non-
volatile memory is one such solution.
c. Timers, network statistics, error correction information, radio/cable television signals, disk seek
times, etc.
d. Since the random number An is not used for secret material, a reliable (not manipulated by the
user) calendar and time-of-day clock can be used as seed. For example, some broadcast content
sources may give reliable date and time information.
Figure 2-24 depicts the HDCP DWC_hdmi_tx as an embedded random number generator with timing
interface. The clk in the diagram represents the TMDS clock.

Figure 2-24 Random Number Input Interface

clk

mdnumgenena

mdnum[3:0] x Random n Random n Random n Random n

2.8.4 DVI or HDMI

The DWC_hdmi_tx must be configured whether the slave device is HDMI capable or just DVI capable. This
information is received in advance after reading the slave’s EDID content.
1. Pseudo-random values sent to HDCP Receiver/Repeater by the Transmitter.

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2.8.5 Features 1.1

The DWC_hdmi_tx supports Features 1.1, although its application depends on the slave capabilities that are
read during the protocol initialization through the I2C link channel.

2.8.6 R Value Verification Method

The link integrity check method can be configured; the verification can be performed once every two
seconds or once on every 128th encrypted frame.

2.8.7 Bypass Encryption

After reading the EDID, the system might not require content protection where a bypass to the entire
encryption path is implemented.

2.8.8 I2C Fast Mode

The I2C master device can be programmed to support the fast mode protocol (400 kHz), although this
feature is dependent on the slave’s capabilities.

2.8.9 Enhanced Link Verification

The link verification method can support Enhanced Link Verification, once every 16 encrypted frames;
pixel 0 of Channel 0 is XORed with the current Pj key, and through I2C polling it is compared with the
slave’s resulting pixel.

2.8.10 Encryption Disable

The DWC_hdmi_tx can be forced to stop encryption through software request; this stall does not make the
link lose its authenticity.

2.8.11 Advance Cipher

The DWC_hdmi_tx supports the Advance Cipher; it is activated once the master and slave have both
enabled the Features 1.1.

2.8.12 Receiver or Repeater

As stated in the HDCP specification, the DWC_hdmi_tx supports connectivity with a Receiver or a
Repeater; in the Repeater's case, it is capable of receiving a KSV FIFO of 128 keys.
You can read the KSV from a repeater from hdcpreg_bksv0 to hdcpreg_bksv4. Use the KSV registers (from
page 293) to read KSV from downstream devices from the revocation/KSV memory and get the permission
to access it through the register a_ksvmemctrl (bits KSVMEMreques and KSVMEMaccess).

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2.8.13 Memory Requirements

This section discusses the external memory requirements for the HDMI TX controller with an HDCP
Encryption Engine.

2.8.13.1 KSV MEM RAM – Revocation Memory

The DWC_hdmi_tx uses external memory to support repeaters. This section describes the memory
allocation, the revocation RAM interface, and two examples with the maximum and minimum memory
usage.
The external memory stores the values Bstatus (2 bytes), M0 (8 bytes), KSV List (5 bytes per KSV), VH, and a
Revocation List (5 bytes per KSV).
The DWC_hdmi_tx checks both lists to verify if there is any element in the KSV List that is black listed in the
Revocation List.
The size of the external memory is directly proportional to the number of downstream repeaters/receivers
that are attached to the repeater (maximum: 127), and to the number of KSVs in the Revocation List
(maximum: 1012).
The Revocation Period is the same as the SFR clock Period (must be 18 to 27 MHz), as illustrated in
Figure 2-25.

Figure 2-25 Revocation RAM Interface

Revoc Period

revocmemclk

revocmemaddress[12:0] x 14‘h0000 x 14‘h000 x

revocmemwen

revocmemcs

revocmemdataout[7:0] x valid

revocmemdatain[7:0] x valid x

Data is sampled at this clock edge

The revocmemclk signal defined in Figure 2-25 is the same as the SFR clock signal that is provided to the
DWC_hdmi_tx. For example, to support the maximum number of KSVs in the Revocation List, the external
memory is (10 + 127 * 5 + 20 + 2 + 1012 * 5) ~ 5.8 Kbytes.

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In Figure 2-25, although the revocemclk clock is provided to the revocation memory, the revocation
memory is essentially an asynchronous read memory, and it does not work as a synchronous memory by
default.
To support a synchronous KSV memory, perform read access in the way described in the following table.
Table 2-16 Read access for Synchronous KSV Memory

Address Data Read access operation

addr 1 data 1 Read addr 1 and discard the data

addr 2 data 2 Read addr 2 to get data1

addr 3 data 3 Read addr 3 to get data2

... ... ...

addr n-1 data n-1 Read addr (n-1) to get data (n-2)

addr n data n Read addr n to get data (n-1)

... ... Read addr n to get data n

Hence, you must perform one extra read operation to get a full list of n positions from a synchronous KSV
memory, while write access can be performed on any position.
Table 2-17 provides the address mapping for System Renewability Messages (SRM) and for the Revocation
List exchange with the HDCP encryption engine.
Table 2-17 Address Mapping for Maximum Memory Allocation

SRM / Revocation
Address in Memory Address Mapping to Registers Bit Location mapping

13'h0000 0x5020 Bstatus[7:0] SRM

13'h0001 0x5021 Bstatus[15:8]

13'h0002 0x5022 M0value[7:0]

... ... ...

13'h0009 0x5029 M0value[63:56]

13'h000A 0x502A KSV_LIST_1[7:0]

... ... ...

13'h000E 0x502E KSV_LIST_1[39:32]

13'h00036 ... ...

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Table 2-17 Address Mapping for Maximum Memory Allocation (Continued)

SRM / Revocation
Address in Memory Address Mapping to Registers Bit Location mapping

... ... ...

13'h0280 0x52A0 KSV_LIST_127[7:0]

... ... ...

13'h0284 0x52A4 KSV_LIST_127[39:32]

13'h0285 0x52A5 VH0[7:0]

... ... ...

13'h0288 0x52A8 VH0[31:24]

13'h0289 0x52A9 VH1[7:0]

... ... ...

13'h028C 0x52AC VH1[31:24] ...

13'h028D 0x52AD VH2[7:0]

... ... ...

13'h0290 0x52B0 VH2[31:24]

13'h0291 0x52B1 VH3[7:0]

... ... ...

13'h0294 0x52B4 VH3[31:24]

13'h0295 0x52B5 VH4[7:0]

... ... ...

13'h0298 0x52B8 VH4[31:24]

13'h0299 0x52B9 REVOC_LIST_SIZE[7:0]

Revocation List Size
13'h029A 0x52BA REVOC_LIST_SIZE[15:8]

13'h029B 0x52BB REVOC_KSV_0[7:0]

... ... ...

13'h029F 0x52BF REVOC_KSV_0[39:32]

... ... ... Revocation List

13'h165A 0x667A REVOC_KSV_1011[7:0]

... ... ...

13'h165E 0x667E REVOC_KSV_1011[39:32]

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You can decrease the size of the memory by using a system that supports lesser repeaters and lesser KSVs in
the Revocation List.
For example, to a system that supports five repeaters and 250 KSVs in the Revocation List, the external
memory needs to have a size of (2+8+5*5+20+2+250*5) ~ 1.3 Kbytes. Alternatively, with the same number of
repeaters supported and without the Revocation List, the external memory needs to have a size of
(2+8+5*5+20+2)= 57 bytes.
Table 2-18 provides the address mapping for System Renewability Messages (SRM) and for the Revocation
List exchange with the HDCP encryption engine for a system that supports five Repeaters and N KSVs in
the Revocation List.

The first VH byte address is always next to the last KSV address. The first REVOC_KSV byte
Note address is always 13'h029B, and the REVOC_LIST_SIZE[7:0] address is always 13'h0299.

Table 2-18 Address Mapping for Minimum Memory Allocation

SRM / Revocation
Address in Memory Address Mapping to Registers Bit Location mapping

13'h0000 0x5020 Bstatus[7:0] SRM

13'h0001 0x5021 Bstatus[15:8]

13'h0002 0x5022 M0value[7:0]

... ... ...

13'h0009 0x5029 M0value[63:56]

13'h000A 0x502A KSV_LIST_1[7:0]

... ... ...

13'h000E 0x502E KSV_LIST_1[39:32]

... ... ...

13'h001E 0x503E KSV_LIST_5[7:0]

... ... ...

13'h0022 0x5044 KSV_LIST_5[39:32]

13'h0023 0x5043 VH0[7:0]

... ... ...

13'h0026 0x5046 VH0[31:24]

13'h0027 0x5047 VH1[7:0]

... ... ...

13'h002A 0x504A VH1[31:24]

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Table 2-18 Address Mapping for Minimum Memory Allocation (Continued)

SRM / Revocation
Address in Memory Address Mapping to Registers Bit Location mapping

13'h002B 0x504B VH2[7:0]

... ... ...

13'h002E 0x504E VH2[31:24]

13'h002F 0x504F VH3[7:0]

... ... ...

13'h0032 0x5052 VH3[31:24]

13'h0033 0x5053 VH4[7:0]

... ... ...

13'h0036 0x5056 VH4[31:24]

13'h0299 0x52B9 REVOC_LIST_SIZE[7:0]

Revocation List Size
13'h029A 0x52BA REVOC_LIST_SIZE[15:8]

13'h029B 0x52BB REVOC_KSV_0[7:0]

... ... ...

13'h029F 0x52BF REVOC_KSV_0[39:32]

... ... ... Revocation List

(Nr5)h + 13'h029B (Nr5)h + 13'h029B +13'h0020 REVOC_KSV_Nr[7:0]

... ... ...

(Nr5)h + 13'h029B + 4 (Nr5)h + 13'h029B + 4 + 13'h0020 REVOC_KSV_Nr[39:32]

Note In the table, Nr = N-1; and (Nr*5)h is the hexadecimal conversion for Nr * 5.

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2.8.13.2 KEY ROM DEV – Device Private Keys ROM

This memory is used to store the Device Private Keys (DPK). It is usually an OTP ROM, internal to the SoC.

It is very important to make sure that is not possible to read this memory once programmed.
Note Only the DWC_hdmi_tx can have a read access to it.

The DWC_hdmi_tx includes two options for this memory interface: a 56-bit memory interface or an 8-bit
memory interface.

56-Bit HDCP DPK Memory Interface

The odpkclk signal defined in Figure 2-27 is the same as the SFR clock signal that is provided to the
DWC_hdmi_tx. The size is 41 words of 56 bits, 287 bytes. The Intclk period is the same as the SFR clock
period (which must be 18 to 27 MHz). This interface is included when the following hardware configuration
parameters are set:
■ HDCP = 1
■ DWC_HDMI_HDCP_DPK_8BIT = 0

Figure 2-26 56-Bit External HDCP Keys

D Q Read
odpkreq

async logic
Q odpkaccess
HDMI Address
D Q
odpkaddr
Q
Data External
Q D
idpkdatain HDCP Keys
Q idpkack

odpkclk

Figure 2-27 56-bit Device Private Keys ROM Interface Timing

Intclk Period
odpkclk

odpkaccess

odpkreq

odpkack

odpkaddr[5:0] x 6‘h00 6‘h01 6‘h02

idpkdatain[55:0] x datakey0 datakey1 datakey2

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The test DPKs are placed in the DPK memory of the DWC_hdmi_tx verification environment as follows
(note that DWC_hdmi_tx has the transmitter1 and transmitter2 DPKs placed in the ROM memory and each
set occupies 41 positions of 56 bit):

In a production environment, ROM memory must be filled with production DPKs. Otherwise,
Note the system does not work with other Receiver or Repeater devices. Each device must have its
own secret non-sharable DPKs.
To receive the DPKs, sign the HDCP agreement and purchase it from Digital Content
Protection LLC (DCP) (http://www.digital-cp.com/).
Place the received secret DPKs and KSV from DCP the way the test DPKs are placed, as
described previously. Typically, DCP sends one set of DPKs and the KSV; you should place
them on the 41 positions of 56 bits of the DPK ROM.

Table 2-19 HDCP DPK 56-bit Memory Mapping

Example value (Test key)

Offset Size Description (Replace them with your own Device Private Keys)

0 56-bit KSV 0x0000b70361f714

1 56-bit KEY #1 0x4da4588f131e69

2 56-bit KEY #2 0x1f823558e65009

3 56-bit KEY #3 0x8a6a47abb9980d

4 56-bit KEY #4 0xf3181b52cbc5ca

5 56-bit KEY #5 0xfb147f6896d8b4

6 56-bit KEY #6 0xe08bc978488f81

7 56-bit KEY #7 0xa0d064c8112c41

8 56-bit KEY #8 0xb39d5a28242044

9 56-bit KEY #9 0xb928b2bdad566b

10 56-bit KEY #10 0x91a47b4a6ce4f6

11 56-bit KEY #11 0x5600f8205e9d58

12 56-bit KEY #12 0x8c7fb706ee3fa0

13 56-bit KEY #13 0xc02d8c9d7cbc28

14 56-bit KEY #14 0x561261e54b9f05

15 56-bit KEY #15 0x74f0de8ccac1cb

16 56-bit KEY #16 0x3bb8f60efcdb6a

17 56-bit KEY #17 0xa02bbb16b22fd7

18 56-bit KEY #18 0x482f8e46785498

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Table 2-19 HDCP DPK 56-bit Memory Mapping (Continued)

Example value (Test key)

Offset Size Description (Replace them with your own Device Private Keys)

19 56-bit KEY #19 0x66ae2562274738

20 56-bit KEY #20 0x3d4952a323ddf2

21 56-bit KEY #21 0xe2d231767b3a54

22 56-bit KEY #22 0x4d581aede66125

23 56-bit KEY #23 0x326082bf7b22f7

24 56-bit KEY #24 0xf61b463530ce6b

25 56-bit KEY #25 0x360409f0d7976b

26 56-bit KEY #26 0xa1e105618d49f9

27 56-bit KEY #27 0xc98e9dd1053406

28 56-bit KEY #28 0x20c36794426190

29 56-bit KEY #29 0x964451ceac4fc3

30 56-bit KEY #30 0x3e904504e18c8a

31 56-bit KEY #31 0x290010579c2dfc

32 56-bit KEY #32 0xd7943b69e5b180

33 56-bit KEY #33 0x54c7ea5bdd7b43

34 56-bit KEY #34 0x74fb5887c790ba

35 56-bit KEY #35 0x935cfa364e1de0

36 56-bit KEY #36 0x03075e159a11ae

37 56-bit KEY #37 0x05d3408a78fb01

38 56-bit KEY #38 0x0059a5d7a04db3

39 56-bit KEY #39 0x373b634a2c9e40

40 56-bit KEY #40 0x2573bbb4562041

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8-Bit HDCP DKP Memory Interface

The DWC_hdmi_tx core used the HDCP interface to access the HDCP keys stored in an external memory, as
illustrated in Figure 2-28. The size is 289 words of 8 bits, 289 bytes. This interface is included when the
following hardware configuration parameters are set:
■ HDCP = 1
■ DWC_HDMI_HDCP_DPK_8BIT = 1

Figure 2-28 8-Bit External HDCP Keys

D Q Read
odpkmemreq

async logic
Q

HDMI Address
D Q
odpkmemaddr
Q
Data External
Q D
idpkmemdata HDCP Keys
Q
odpkclk

The HDCP interface requires only three signals: two output signals (odpkmemreq, odpkmemaddr to the
memory) and one input signal (idpkmemdata from the memory). Figure 2-29 shows the expected timing
behavior for the 8-bit memory interface (maximum frequency is 27 MHz). For more information about these
signals, refer to Table 4-6 on page 113.

Figure 2-29 8-bit Device Private Keys ROM Interface timing

odpkclk

odpkmemreq

odpkmemaddr [8:0] valid

idpkmemdatai[7:0] valid

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The HDCP DPK mapping into the external memory is defined in Table 2-20.
Table 2-20 HDCP DPK 8-bit Memory Mapping

Example value (Test key)

Offset Size Description (Replace them with your own Device Private Keys)

0 8-bit Reserved

1 8-bit KSV[7:0] 0x14

2 8-bit KSV[15:8] 0xF7

3 8-bit KSV[23:16] 0x61

4 8-bit KSV[31:24] 0x03

5 8-bit KSV[39:32] 0xB7

6 8-bit Reserved

7 8-bit Reserved

8 8-bit Reserved

9 8-bit KEY#1[7:0] 0x69

10 8-bit KEY#1[15:8] 0x1e

11 8-bit KEY#1[23:16] 0x13

12 8-bit KEY#1[31:24] 0x8f

13 8-bit KEY#1[39:32] 0x58

14 8-bit KEY#1[47:40] 0xa4

15 8-bit KEY#1[55:48] 0x4d

... 8-bit ... ...

282 8-bit KEY#40[7:0] 0x41

283 8-bit KEY#40[15:8] 0x20

284 8-bit KEY#40[23:16] 0x56

285 8-bit KEY#40[31:24] 0xb4

286 8-bit KEY#40[39:32] 0xbb

287 8-bit KEY#40[47:40] 0x73

288 8-bit KEY#40[55:48] 0x25

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2.9 EDID/HDCP I2C E-DDC Interface

The E-DDC channel is a dedicated I2C master interface that allows the read of sink E-EDID based on system
needs. Data read from sink E-EDID can be then transferred through the standard offered interfaces
(AMBA AHB, OCP, I2C, or dedicated ROM interface) to the I2C Master register bank, starting at address
0x7E00.
This block reads the E-EDID (and all its segments according to user configuration) and, after completion, it
warns the CPU of data availability. This block also arbitrates the I2C master interface to allow the
DWC_hdmi_tx’s HDCP authentication protocol to be performed through this interface. Sink HDCP links
(with addresses 0x74 and/or 0x76) should be present at these lines to enable HDCP-compliant behavior.
The interface is shared with the DDC channel of the HDMI controller through multiplexers and is I2C
compliant.

2.9.1 I2C Master Interface Normal Mode

This operation implements a single read or write operation using the Special Function Register
configuration. The I2C data transfer protocol used is the 7-bit addressed, as defined in Section 9 of the
I2C-bus Specification, version 2.1.

Figure 2-30 Data Write Transaction

_ _ _
S slaveaddr[6:0] W A addr[7:0] datao[7:0] A/A PA/A

Legend:
Transaction from master to slave. _ – Acknowledge (sdao low)
A
A – not Acknowledge (sdao high)
Transaction from slave to master.
S_ – Start condition
P – Stop condition
W – Write indication

Figure 2-31 Data Read Transaction

_ _ _
S slaveaddr[6:0] W A addr[7:0] A/A Sr slaveaddr[6:0] R A datai[7:0] A P

Legend:
Transaction from master to slave. A
_ – Acknowledge (sdao low)
A – not Acknowledge (sdao high)
Transaction from slave to master. S – Start condition
Sr
_ – Repeated start condition
P – Stop condition
W – Write indication
R – Read indication

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2.9.2 I2C Master Interface Extended Read Mode

This I2C extended read mode operation implements a segment pointer-based read operation using the
Special Register configuration.

Figure 2-32 Extended Data Read Operation

_ _
S segaddr[6:0] W X segpointer[7:0] X Sr slaveaddr[6:0] W A addr[7:0] A/A Sr slaveaddr[6:0] R A datai[7:0] A P

Legend:
Transaction from master to slave.

Transaction from slave to master.

A
_ – Acknowledge (sdao low)
A – not Acknowledge (sdao high)
S – Start condition
Sr – Repeated start condition
P_ – Stop condition
W – Write indication
R – Read indication
X – Don't care

2.9.3 I2C Clock Configuration

The following *CNT registers must be set before any I2C bus transaction can take place to ensure proper I/O
timing. The *CNT registers are:
■ *_I2CM_SS_SCL_HCNT
■ *_I2CM_SS_SCL_LCNT
■ *_I2CM_FS_SCL_HCNT
■ *_I2CM_FS_SCL_LCNT
Setting the *_LCNT registers, configures the number of SFR_CLKs that are required for setting the low time
of the SCL clock in each speed mode. For more information about these registers, refer to “I2C Master PHY
Registers” on page 234 and “I2C Master Registers (E-DDC)” on page 313.
Setting the *_HCNT* registers, configures the number of IC_CLKs that are required for setting the high time
of the SCL clock in each speed mode.
Setting the registers to the correct value is described as follows. The equation to calculate the proper number
of SFR_CLKs required for setting the proper SCL clocks high and low times is as follows:
IC_xCNT = (ROUNDUP(MIN_SCL_xxxtime*SFRFREQ,0))
ROUNDUP is an explicit Microsoft Excel® function call that is used to roundup the results of the division to
an integer.

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Table 2-21 Minimum High and Minimum Low @100 kbps

MIN_SCL_*time Variable Specification Value Compliance Valuea

MIN_SCL_HIGHtime 4000 ns 4500 ns

MIN_SCL_LOWtime 4700 ns 5200 ns

a. The values included in this column are used in Synopsys HDMI compliance testing of
the DWC_hdmi_tx controller. It is strongly recommended that you use these values to
avoid issues with existing compliance test equipment.

Example 2-1 SFR_CLK Frequency Example 1

SFR Clock Frequency (Hz) = SFRFREQ
SFRFREQ = 27 MHz
I2Cmode = fast, 400 kbit/s
MIN_SCL_HIGHtime = 600 ns.
MIN_SCL_LOWtime = 1300 ns.

IC_xCNT = (ROUNDUP(MIN_SCL_HIGH_LOWtime*SFRFREQ,0))
IC_HCNT = (ROUNDUP(600 ns * 27 MHz,0))
IC_HCNTSCL PERIOD = 17

IC_LCNT = (ROUNDUP(1300 ns * 27 MHz,0))

IC_LCNTSCL PERIOD = 36

Example 2-2 SFR_CLK Frequency Example 2

SFR Clock Frequency (Hz) = SFRFREQ
SFRFREQ = 27 MHz
I2Cmode = standard, 100 kbit/s
MIN_SCL_HIGHtime = 4000 ns.
MIN_SCL_LOWtime = 4700 ns.

IC_xCNT = (ROUNDUP(MIN_SCL_HIGH_LOWtime*SFRFREQ,0))
IC_HCNT = (ROUNDUP(4000 ns * 27 MHz,0))
IC_HCNTSCL PERIOD = 108

IC_LCNT = (ROUNDUP(4700 ns * 27 MHz,0))

IC_LCNTSCL PERIOD = 127
The minimum value for *_LCNT is 8 and the minimum *_HCNT is 6. Also, because of the digital filtering on
the receiver, the actual SCL high and low times are slightly longer than the specified count value 8.
The final values calculated in the equation for IC_*_HCNT and IC_*_LCNT (where * represents SS or FS) are
decimal values. For programming the actual registers, the values must be converted to hexadecimal. The
16-bit range on these registers allows a wide range of input clock frequencies to be used.
By default, the *CNT registers are configured to work with the SFR clock at 27 MHz. The SS*CNT and
FS*CNT registers are required to set the SFR clock frequency.

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2.10 AMBA APB 3.0 Slave Interface

The system interface (the interface that connects to the processor bus) is an AMBA APB 3.0 slave interface.
The AMBA APB slave interface module is compatible with the AMBA 3 APB Protocol Specification, revision
1.0. The APB slave interface is used in the DWC_hdmi_tx for register configuration. According to the APB
specification, all signal transitions are only related to the rising edge of the clock to enable the integration of
APB peripherals easily into any design flow. Every transfer takes at least two cycles. This interface supports
write and read transactions with wait cycles, which allow transposition to internal registers’ clock domain.

2.11 CEC Hardware Engine

Consumer Electronics Control (CEC) is a protocol that provides high-level control functions between all of
the various audiovisual products in a user’s environment. It is an optional feature in the HDMI 1.3a
Specification. It uses only one bidirectional line for transmission and reception.
All transactions on the CEC line consist of an initiator and one or more followers. The initiator is responsible
for sending the message structure and the data. The follower is the recipient of any data and is responsible
for setting any acknowledgement bits.

Figure 2-33 CEC Engine Simplified Block Diagram

ocecout

icecin CEC
Engine

There are two operation modes for a CEC controller.

■ Initiator Mode
In this mode, the CEC controller sends messages out and waits for a follower to feedback. The CEC
controller works in this mode when it starts to send a frame. After the transmission is done, it
automatically returns to the follower mode (no software control involved).
■ Follower Mode
In this mode, the CEC controller receives messages and feeds back the initiator with appropriate
signals. The CEC controller always works in the follower mode whenever it is not transmitting any
data.

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For correct CEC controller interface operation, initial reset is required in order to set internal registers to a
known state. After this reset, the interface is in an IDLE state, waiting for a read or write request coming
from the register configuration.

When you apply a software reset to CEC using the register mc_swrstzreq, set the value of the
Note bit cecclk_disable of the register mc_clkdis to 1, 0, and then 1 again.

A specific CEC API is provided that implements all necessary low-level register configuration to send and
receive CEC messages. For more information, see the CEC API documentation.
The CEC engine registers base address is 0x7D00. For more information about these registers, refer to 5.2.16
on page 305. For more information about CEC, refer to the Consumer Electronics Control (CEC) Application
Note.

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3
Hardware Configuration Parameters

This chapter provides a description of the hardware configuration parameters available for the
DWC_hdmi_tx. You use either the coreConsultant GUI to specify the configuration parameters.
The coreConsultant GUI groups the parameters as follows:
■ “Interfaces” on page 92
■ “Feature Definition” on page 93
■ “Metastability Option” on page 95

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Table 3-1 Controller Configuration Parameters

Label Parameter Definition

Interfaces
Audio Interface Parameter Name: AUDIO_IF
Values: I2S (1), SPDIF (2), DOUBLE (4), GPAUD (6), GDOUBLE (7),
AHBAUDDMA (8)
Default Value: I2S (1)
Dependencies: None
Description: Selects the desired DWC_hdmi_tx audio Interface(s):
1 – I2S interface
2 – S/PDIF interface
4 – I2S and S/PDIF audio interfaces (designated as DOUBLE interface)
6 – Generic Purpose (GP) Audio (AUD) interface
7 – Combines both the GP Audio and the I2S interfaces (designated as
GDOUBLE interface)
8 – AHB DMA Audio
AHB Audio DMA FIFO Address Parameter Name: HDMI_TX_AHBDMAAUD_FIFO_ADDRWITH
Width Values: 7, 8, 9, and 10
Default Value: 7
Dependencies: This parameter is enabled only when AUDIO_IF =
AHBAUDDMA (8).
Description: This parameter sets the Audio DMA FIFO address width (number
of bits). The FIFO size depends on this parameter because
FIFO_size = 2HDMI_TX_AHBDMAAUD_FIFO_ADDRWITH.
Bypass S/PDIF Data Recovery Parameter Name: HTX_SPDIFBYPDRU
Unit (DRU) Values: True (1) or False (0)
Default Value: False (0)
Dependencies: This parameter is enabled only when AUDIO_IF = 2 (S/PDIF)
or AUDIO_IF = 4 (DOUBLE).
Description: This parameter allows the S/PDIF Data Recovery Unit (DRU) to
be bypassed. This implies that ispdifclk must always be at 128xfs and that
ispdifdata must be a BMC stream synchronous with ispdifclk.
Support for HBR over SDPIF Parameter Name: HBR_ON_SPDIF
Values: True (1) or False (0)
Default Value: False (0)
Dependencies: This parameter is enabled only when HTX_SPDIFBYPDRU =
True (1).
Description: This parameter allows for High Bit Rate (HBR) audio reception
through the existing S/PDIF interface.

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Table 3-1 Controller Configuration Parameters (Continued)

Label Parameter Definition

Feature Definition
Support HDMI 1.4 Features Parameter Name: DWC_HDMI_TX_14
Values: True (1) or False (0)
Default Value: False (0)
Dependencies: None
License Dependencies: To use this feature, you must have both DWC-HDMI-
13-TX and DWC-HDMI-14-TX licenses.
Description: When selected, the DWC_hdmi_tx includes the HDMI 1.4b
specification features.
Support HDCP Parameter Name: HDCP
Values: True (1) or False (0)
Default Value: False (0)
Dependencies: None
License Dependencies:
To generate a DWC_hdmi_tx core with HDCP capabilities, you must have a
DWC-HDMI-13-TX-HDCP or DWC-HDMI-HDCP license.
Description:
This parameter enables High-bandwidth Digital Content Protection (HDCP)
system support:
1 – True: HDCP hardware present in DWC_hdmi_tx using dedicated port
connections
0 – False: HDCP hardware not present in DWC_hdmi_tx (dedicated ports are
automatically removed)
Support Color Space Converter Parameter Name: CSC
Values: True (1) or False (0)
Default Value: True (1)
Dependencies: None
Description: When selected, this parameter enables CSC support:
1 – True: Hardware instance of color space converter and corresponding filters
present at DWC_hdmi_tx.
0 – False: Not available at DWC_hdmi_tx (instance is automatically removed
from hardware configuration).
Support Consumer Electronics Parameter Name: CEC
Control Values: True (1) or False (0)
Default Value: True (1)
Dependencies: None
Description: When selected, this parameter enables CEC the interface:
1 – True: CEC hardware present in DWC_hdmi_tx using dedicated port
connections
0 – False: CEC hardware not present in DWC_hdmi_tx (dedicated ports are
automatically removed)

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Table 3-1 Controller Configuration Parameters (Continued)

Label Parameter Definition

Support Internal Pixel Repetition Parameter Name: DWC_HDMI_TX_INTPREPEN
Values: True (1) or False (0)
Default Value: True (1)
Dependencies: None
Description: When selected, this parameter enables the internal pixel
repetition support:
1 – True: DWC_hdmi_tx has dedicated hardware to perform internal pixel
repetition
0 – False: DWC_hdmi_tx does not support internal pixel repetition
NOTE: If your input video stream (to DWC_hdmi_tx) is purely CEA-compliant,
then pixel repetition is already present at the video stream and you may not
want this internal pixel repetition feature.
Support for Custom PHY (Non- Parameter Name: PHY_EXTERNAL
Synopsys) Values:
False (0) = a Synopsys PHY is used
True (1) = a Non-Synopsys (custom) PHY is used
Default Value: False (0)
Dependencies: None
Description: When enabled, the DWC_hdmi_tx uses a non-Synopsys, external
PHY.
Note: To enable your Synopsys PHY deliverable, you must set the
HDMITX_PHY_PATH variable. For example:
% setenv HDMITX_PHY_PATH /u/hdmi_phys/tsmc_040lp_hdmi_tx_14_phy_1.0a
% setenv HDMITX_PHY_LIBNAME hdmi_tx_phy_ss1p08v125c.lib

Enable SNPS HEAC PHY Parameter Name: HDMI_HEAC_PHY_EN

Values: True (1) or False (0)
Default Value: False (0)
Dependencies: This parameter is visible only if a PHY GEN2 is selected.
Description: When enabled, the DWC_hdmi_tx uses the SNPS HEAC PHY:
1 – True: Synopsys HEAC PHY hardware present at the DWC_hdmi_tx core
using dedicated port connections.
0 – False: No HEAC PHY hardware present at the DWC_hdmi_tx core.
NOTE: To enable your PHY deliverable, you must set the HDMITX_HEAC_PHY
and HDMITX_PHY_LIBNAME environment variables to the location of the PHY
behavioral models and PHY .lib files.
% setenv HDMITX_HEAC_PHY_PATH
/u/hdmi_phys/tsmc_040lp_hdmi_tx_14_heac_phy_1.0a
% setenv HDMITX_HEAC_PHY_LIBNAME hdmi_heac_phy_tt1p1v25c.lib

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Table 3-1 Controller Configuration Parameters (Continued)

Label Parameter Definition

Enable DPK Memory 8-Bit Data Parameter Name: DWC_HDMI_HDCP_DPK_8BIT
Interface Values: True (1) or False (0)
Default Value: False (0)
Dependencies: This parameter is visible only if HDCP = True (1).
License Dependencies: This feature is only available if you have an HDCP
license.
Description: When set, to True (1)this parameter supports the DPK memory 8-
bit data interface.
1 – True: DPK memory 8-bit data interface available
0 – False: DPK memory 56-bit data interface available
Metastability Option
Number of Flop Stages in Reset Parameter Name: HDMIRSYNCDEPTH
Synchronizers Values: 2, 3, or 4
Default Value: 2
Dependencies: None
Description: Number of synchronizing flip-flop stages in reset synchronizers:
2 – Two-stage flop synchronization with both stages positive-edge capturing
3 – Three-stage flop synchronization with all stages positive-edge capturing
4 – Four-stage flop synchronization with all stages positive-edge capturing
Number of Flop Stages in Data Parameter Name: HDMIDATASYNCDEPTH
Synchronizers Values: 2, 3, or 4
Default Value: 2
Dependencies: None
Description: Number of synchronizing flip-flop stages in data synchronizers:
2 – Two-stage flop synchronization with both stages positive-edge capturing
3 – Three-stage flop synchronization with all stages positive-edge capturing
4 – Four-stage flop synchronization with all stages positive-edge capturing

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4
Signals

This chapter helps you to understand HDMI TX signals and their properties. It describes the naming
conventions, I/O mapping, width, dependencies, and their behavior with various interfaces.
The topics include:
■ “Naming and Description Conventions” on page 98
■ “Signal Descriptions” on page 101
❑ “Video Input Interface Signals” on page 101
❑ “Audio Input Interface Signals” on page 103
❑ “System and Slave Register Interface Signals” on page 109
❑ “E-DDC Interface Signals” on page 111
❑ “CEC Interface Signals” on page 112
❑ “HDCP Encryption Engine Signals” on page 113
❑ “Scan Test Interface Signals” on page 117
❑ “HDMI TX PHY Interface Signals” on page 119
❑ “HDMI 3D TX PHY (PHY GEN 2) Interface Signals” on page 120
❑ “HDMI HEAC PHY Interface Signals” on page 121
❑ “HDMI TX External PHY Signals” on page 122

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4.1 Naming and Description Conventions

4.1.1 Signal Name
The signal name begins with the letter i when the signal is an input signal, with the letter o when the signal
is an output signal, and with the letters io when the signal is an I/O signal.

4.1.2 Signal Name Prefix

The signal name prefix indicates the interface to which the signal belongs.

4.1.3 Signal Name Description

The signal name description describes the function of each signal, and the type, that can be
■ Synchronous: The signal is asserted or deasserted with respect to a clock edge.
■ Asynchronous: The signal is not asserted or deasserted with respect to a clock edge.
■ Registered: The signal is captured (or launched) directly at the macro boundary with no intermediate
logic between the core boundary and the capturing (or launching) flip-flop.

Figure 4-1 Synchronous and Asynchronous signals

Inputs Outputs
Synchronous Registered boundary Synchronous Registered boundary

input output

clk clk

Synchronous Non-Registered Synchronous Non-Registered

input output

clk clk

Asynchronous Asynchronous

input output

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4.2 Top-Level I/O Diagram

DWC_hdmi_tx
idataen ii2c_msth13tddc_sclin E-DDC Interface
ihsync oi2c_msth13tddc_sclout
Video Input Interface Signals
ipixelclk
Signals ivdata
ii2c_msth13tddc_sdain
ivsync oi2c_msth13tddc_sdaout
icecclk
ii2sclk icecin
I2S Interface CEC Interface Signals
ii2slrclk
ii2sdata
ocecout

S/PDIF Interface ispdifclk odpkclk

ispdifdata idpkack
idpkdatain 56-bit DPK Memory
Audio Input Interface Signals

igpadata[28] odpkaddr Interface

HDCP Encryption Engine Signals

Generic Parallel igpadata[27] odpkreq
Audio (GPA) igpadata[26] odpkaccess
Interface igpadata[25]
igpadata[24] odpkmemreq 8-bit DPK Memory
igpadata[23:0] odpkmemaddr Interface
igpavalid idpkmemdatai
ogpadatareq
igpaclk irevocmemdatain
orevocmemclk Revocation Memory
idmahresetn orevocmemaddress Interface
idmahclk orevocmemcs
odmahaddr[31:0] orevocmemwen
odmahtrans[1:0] orevocmemdataout
odmahwrite
odmahsize[2:0] irndnum HDCP Encryption
AHB Master DMA odmahburst[2:0] orndnumgenena Engine Signals
Audio Interface odmahwdata[31:0]
idmahrdata[31:0] iscanclk
idmahready iscanrstz
idmahresp[2:0] iscanen
odmahbusreq Scan Test
iscanmode
odmahlock Interface Signals
iscan_ctrl_in
idmahgrant oscan_ctrl_out
System and Slave Register Interface Signals

iscan_phy_in
irstz oscan_phy_out
isfrclk
ointerrupt
ihpd
iapbclk ioavdd18
iapbrstz ioavdd10
iapbenable iovdd
iapbsel ioagnd18
APB 3.0 Slave
iapbaddr ioagnd10 HDMI TX PHY
Interface
iapbwrite iovss Interface Signals
oapbready iorref
iapbwdata ioatestmon
iapbwdata otmdsdatap
otmdsdatan
otmdsclkp
otmdsclkn

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DWC_hdmi_tx

iphyext_tclk iovp
iphyext_prepclk iovp_filt0
ophyext_dataencoded iovp_filt1
ophyext_rstz iovp_filt2
iphyext_lock iovph
HDMI TX External PHY iphyext_rxsense iogd HDMI 3D TX PHY (PHY
Signals ophyext_ppdq ioddccec GEN 2) Interface Signals
ophyext_txpwron ioresref_f
iphyext_hpd ioresref_s
ophyext_enhpdrxsense otmdsdatap
ophyext_sparectl otmdsdatan
ophyext_i2c_sdaout otmdsclkp
ophyext_i2c_sclout otmdsclkn
iphyext_i2c_sclin ophydtb
iphyext_i2c_sdain

iovdd_heac
iovss_heac
iogd_heac
iovph_heac
oheacphy_dtb
iscanin_heac HDMI HEAC PHY
oscanout_heac Interface Signals
ihectxdatan
ihectxdatap
oarcrxdata
ioheacn
ioheacp
iohecrxdatan
iohecrxdatap
ioresext
ioresextv

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4.3 Signal Descriptions

The following sections provide a detailed description of the DWC_hdmi_tx signals.
■ “Video Input Interface Signals”
■ “Audio Input Interface Signals” on page 103
■ “System and Slave Register Interface Signals” on page 109
■ “E-DDC Interface Signals” on page 111
■ “CEC Interface Signals” on page 112
■ “HDCP Encryption Engine Signals” on page 113
■ “Scan Test Interface Signals” on page 117
■ “HDMI TX PHY Interface Signals” on page 119
■ “HDMI 3D TX PHY (PHY GEN 2) Interface Signals” on page 120
■ “HDMI HEAC PHY Interface Signals” on page 121

4.3.1 Video Input Interface Signals

The Video Input Interface signals include the basic signals like the pixel clock, data input, data enable,
horizontal, and vertical sync signals. Dependencies are always present in such signals.

Figure 4-2 Video Input Interface Signals

DWC_hdmi_tx
idataen
ihsync
Video Input Interface ipixelclk
ivdata
ivsync

Table 4-1 Video Input Interface Signal Description

Width
Name (bits) I/O Description
idataen 1 I Video data enable
Active State: High
Registered: No
Synchronous to: ipixelclk
Dependencies: Always present
ihsync 1 I Video horizontal sync signal
Active State: Active
Registered: No
Synchronous to: ipixelclk
Dependencies: Always present

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Table 4-1 Video Input Interface Signal Description (Continued)

Width
Name (bits) I/O Description
ipixelclk 1 I Data pixel clock
Active State: N/A
Registered: No
Synchronous to: ipixelclk
Dependencies: Always present
ivdata 48 I Video data input
Active State: N/A
Registered: No
Synchronous to: ipixelclk
Dependencies: Always present
ivsync 1 I Video vertical sync signal
Active State: High
Registered: No
Synchronous to: ipixelclk
Dependencies: Always present

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4.3.2 Audio Input Interface Signals

The Audio Input Interface signals include the basic signals like the data pixel clock, audio data input, and
signals for data sample buses. These signals work on various interfaces like I2S, S/PDIF, and General Parallel Audio
(GPA) interfaces.

Figure 4-3 Audio Input Interface Signals

ii2sclk DWC_hdmi_tx
I2S Interface ii2slrclk
ii2sdata

ispdifclk
S/PDIF Interface ispdifdata

igpadata[28]
igpadata[27]
igpadata[26]
igpadata[25]
igpadata[24]
GPA Interface igpadata[23:0]
igpavalid
ogpadatareq
igpaclk

idmahresetn
idmahclk
odmahaddr[31:0]
odmahtrans[1:0]
odmahwrite
odmahsize[2:0]
DMA Audio Interface odmahburst[2:0]
odmahwdata[31:0]
AHB Master
idmahrdata[31:0]
idmahready
idmahresp[2:0]
odmahbusreq
odmahlock
idmahgrant

Table 4-2 Audio Input Interface Signal Description

Width
Name (bits) I/O Description

I2S Interface

ii2sclk 1 I I2S bit clock

Active State: N/A
Registered: No
Synchronous to: N/A
Dependencies: AUDIO_IF = I2S (1), DOUBLE (I2S and S/DPIF) [4], or GDOUBLE
(GP Audio and I2S) [7]

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Table 4-2 Audio Input Interface Signal Description (Continued)

Width
Name (bits) I/O Description

ii2slrclk 1 I I2S word clock

Active State: N/A
Registered: Yes
Synchronous to: ii2sclk
Dependencies: AUDIO_IF = I2S (1), DOUBLE (I2S and S/DPIF) [4], or GDOUBLE
(GP Audio and I2S) [7]

ii2sdata 4 I Audio data input. The following bits inputs audio data to sent in the specified
channels.
Bit 0 – Channel 1 and 2
Bit 1 – Channel 3 and 4
Bit 2 – Channel 5 and 6
Bit 3 – Channel 7 and 8
Active State: N/A
Registered: Yes
Synchronous to: ii2sclk
Dependencies: AUDIO_IF = I2S (1), DOUBLE (I2S and S/DPIF) [4], or GDOUBLE
(GP Audio and I2S) [7]

S/PDIF Interface

ispdifclk 1 I S/PDIF audio input clock (DRU/HBR_ON_SPDIF dependent)

Active State: N/A
Registered: No
Synchronous to: N/A
Dependencies: AUDIO_IF = S/PDIF (2) or DOUBLE (I2S and S/DPIF) [4]

ispdifdata 1 I S/PDIF digital audio input

Active State: N/A
Registered: Yes
Synchronous to: ispdifclk
Dependencies: AUDIO_IF = S/PDIF (2) or DOUBLE (I2S and S/DPIF) [4]

Generic Parallel Audio (GPA) Interface

igpadata[28] 1 I B flag
= 1 if the Sub-packet contains the first frame in a 192 frame IEC 60958 Channel
Status block.
= 0 otherwise
Active State: N/A
Registered: Yes
Synchronous to: igpaclk
Dependencies: AUDIO_IF = 6 (GPAUD) or 7 (GDOUBLE [I2S+GPAUD])

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Table 4-2 Audio Input Interface Signal Description (Continued)

Width
Name (bits) I/O Description

igpadata[27] 1 I P flag
Active State: N/A
Registered: Yes
Synchronous to: igpaclk
Dependencies: AUDIO_IF = 6 (GPAUD) or 7 (GDOUBLE [I2S+GPAUD])

igpadata[26] 1 I C flag
Active State: N/A
Registered: Yes
Synchronous to: igpaclk
Dependencies: AUDIO_IF = 6 (GPAUD) or 7 (GDOUBLE [I2S+GPAUD])

igpadata[25] 1 I U flag
Active State: N/A
Registered: Yes
Synchronous to: igpaclk
Dependencies: AUDIO_IF = 6 (GPAUD) or 7 (GDOUBLE [I2S+GPAUD])

igpadata[24] 1 I V flag
Active State: N/A
Registered: Yes
Synchronous to: igpaclk
Dependencies: AUDIO_IF = 6 (GPAUD) or 7 (GDOUBLE [I2S+GPAUD])

igpadata[23:0] 24 I Input data sample bus

Active State: N/A
Registered: Yes
Synchronous to: igpaclk
Dependencies: AUDIO_IF = 6 (GPAUD) or 7 (GDOUBLE [I2S+GPAUD])

igpavalid 1 I Indicates when a valid sample is available at the gpadata input interface when high
Active State: Active
Registered: Yes
Synchronous to: igpaclk
Dependencies: AUDIO_IF = 6 (GPAUD) or 7 (GDOUBLE [I2S+GPAUD])

ogpadatareq 1 O High when new data is required. Low when no data is required or when the parallel
interface is disabled.
Active State: High
Registered: Yes
Synchronous to: igpaclk
External Input Delay: N/A
Dependencies: AUDIO_IF = 6 (GPAUD) or 7 (GDOUBLE [I2S+GPAUD])
Value After Reset: 0

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Table 4-2 Audio Input Interface Signal Description (Continued)

Width
Name (bits) I/O Description

igpaclk 1 I System clock, used to capture the audio sample bus. It can be same as the system
bus clock, or any other clock above 20 MHz.
Active State: N/A
Registered: Yes
Synchronous to: igpaclk
External Input Delay: N/A
Dependencies: AUDIO_IF = 6 (GPAUD) or 7 (GDOUBLE [I2S+GPAUD])

AHB Master DMA Audio Interface

idmahresetn 1 I Asynchronous active low reset signal for AHB bus (not synchronized inside this
module).
Active State: Low
Registered: Asynchronous
Synchronous to: idmahclk
Dependencies: AUDIO_IF = AHB DMA Audio (8)

idmahclk 1 I Bus clock. This clock times all bus transfers. All signal timings are related to the
rising edge of HCLK
Active State: N/A
Registered: Yes
Synchronous to: N/A
Dependencies: AUDIO_IF = AHB DMA Audio (8)

odmahaddr 32 O Address bus. The 32-bit system address bus.

Active State: N/A
Registered: Yes
Synchronous to: idmahclk
Dependencies: AUDIO_IF = AHB DMA Audio (8)
Value After Reset: 0x00000000

odmahtrans 2 O Indicates the type of the current transfer, which can be NONSEQUENTIAL,
SEQUENTIAL, IDLE or BUSY.
Active State: N/A
Registered: Yes
Synchronous to: idmahclk
Dependencies: AUDIO_IF = AHB DMA Audio (8)
Value After Reset: 0x0

odmahwrite 1 O When HIGH, this signal indicates a write transfer; when LOW a read transfer.
Active State: N/A
Registered: Yes
Synchronous to: idmahclk
Dependencies: AUDIO_IF = AHB DMA Audio (8)
Value After Reset: 0

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Table 4-2 Audio Input Interface Signal Description (Continued)

Width
Name (bits) I/O Description

odmahsize 3 O Indicates the size of the transfer, which is typically byte (8-bit), halfword (16-bit) or
word (32-bit). The protocol allows for larger transfer sizes up to a maximum of 1024
bits.
Registered: Yes
Synchronous to: idmahclk
External Input Delay: N/A
Dependencies: AUDIO_IF = AHB DMA Audio (8)
Value After Reset: 0x2

odmahburst 3 O Indicates if the transfer forms part of a burst. Unidentified length, four, eight and
sixteen beat bursts are supported in incrementing burst type (wrapping is not
supported).
Registered: Yes
Synchronous to: idmahclk
External Input Delay: N/A
Dependencies: AUDIO_IF = AHB DMA Audio (8)
Value After Reset: 0x0

odmahwdata 32 O The write data bus is used to transfer data from the master to the bus slaves during
write operations. Exists only for AHB compliance. Not needed in the AHB audio
DMA operation context.
Active State: N/A
Registered: Yes
Synchronous to: idmahclk
Dependencies: AUDIO_IF = AHB DMA Audio (8)
Value After Reset: 0x0000000000000000

idmahrdata 32 I The read data bus is used to transfer data from bus slaves to the bus master during
read operations.
Active State: N/A
Registered: Yes
Synchronous to: idmahclk
Dependencies: AUDIO_IF = AHB DMA Audio (8)

idmahready 1 I Transfer done. When HIGH, the signal indicates that a transfer has finished on the
bus. This signal may be driven LOW to extend a transfer.
Active State: High
Registered: Yes
Synchronous to: idmahclk
Dependencies: AUDIO_IF = AHB DMA Audio (8)

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Table 4-2 Audio Input Interface Signal Description (Continued)

Width
Name (bits) I/O Description

idmahresp 2 I The transfer response provides additional information on the status of a transfer.
Four different responses are provided, OKAY, ERROR, RETRY and SPLIT.
Active State: N/A
Registered: Yes
Synchronous to: idmahclk
Dependencies: AUDIO_IF = AHB DMA Audio (8)

odmahbusreq 1 O A signal from AHB audio DMA bus master to the bus arbiter, which indicates that the
bus master requires the bus.
Active State: N/A
Registered: Yes
Synchronous to: idmahclk
Dependencies: AUDIO_IF = AHB DMA Audio (8)
Value After Reset: 0

odmahlock 1 O When HIGH this signal indicates to the arbiter that the master requires locked
access to the bus and no other master should be granted the bus until this signal is
LOW.
Active State: High
Registered: Yes
Synchronous to: idmahclk
Dependencies: AUDIO_IF = AHB DMA Audio (8)
Value After Reset: 0

idmahgrant 1 I This signal indicates that the AHB audio DMA is currently the highest priority
master. Ownership of the address/control signals changes at the end of a transfer
when ihready is HIGH, so a master gets access to the bus when both ihready and
ihgrant are HIGH.
Active State: High
Registered: Yes
Synchronous to: idmahclk
Dependencies: AUDIO_IF = AHB DMA Audio (8)

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4.3.3 System and Slave Register Interface Signals

The System and Slave Interface Signals include various clock signals, master interrupt signals, and master
and slave transfer signals.

Figure 4-4 System and Slave Register Interface Signals

DWC_hdmi_tx
irstz
isfrclk
ointerrupt

iapbclk
iapbrstz
iapbenable
iapbsel
APB 3.0 Slave Interface iapbaddr
iapbwrite
oapbready
iapbwdata
iapbwdata

Table 4-3 System and Slave Register Interface Signals Description

Width
Name (bits) I/O Description
irstz 1 I Active low asynchronous, master reset input (minimum duration of 500us for
active low reset state)
Active State: Low
Registered: No
Synchronous to: N/A
Dependencies: Always present
isfrclk 1 I Internal register configuration clock (must be in the range 18-27 MHz)
Active State: N/A
Registered: No
Synchronous to: N/A
Dependencies: Always present
ointerrupt 1 O Master interrupt signal
Active State: High
Registered: No
Synchronous to: Asynchronous
Dependencies: Always present
Value After Reset: 0
APB 3.0 Slave Interface
iapbclk 1 I APB bus clock (same as system controller core)
Active State: N/A
Registered: No
Synchronous to: N/A

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Table 4-3 System and Slave Register Interface Signals Description (Continued)

Width
Name (bits) I/O Description
iapbrstz 1 I APB bus synchronous active low reset (minimum duration of one AHB bus clock
cycle)
Active State: Low
Registered: No
Synchronous to: Asynchronous
iapbenable 1 I APB enable
Active State: High
Registered: Yes
Synchronous to: iapbclk
iapbsel 1 I APB Slave select signal
Active State: High
Registered: Yes
Synchronous to: iapbclk
iapbaddr 16 I APB address bus
Active State: N/A
Registered: Yes
Synchronous to: iapbclk
iapbwrite 1 I APB write indication signal
Active State: High
Registered: Yes
Synchronous to: iapbclk
oapbready 1 O APB Slave interface ready output signal
1: Slave ready
0: Slave not ready (wait cycles inserted)
Active State: High
Registered: Yes
Synchronous to: iapbclk
Value After Reset: 0
iapbwdata 8 I APB Write data bus
Active State: N/A
Registered: Yes
Synchronous to: iapbclk
oapbrdata 8 O APB Read data bus
Active State: N/A
Registered: Yes
Synchronous to: iapbclk
Value After Reset: 0x00

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4.3.4 E-DDC Interface Signals

To use the HDCP module, the isfrclk input clock (not shown in Table 4-4) must be 18 to 27 MHz for the
HDCP timers to operate correctly. These timers include the time-outs used for the authentication protocol,
and for the I2C bus used for DDC operation.

Figure 4-5 E-DDC Interface Signals

DWC_hdmi_tx
ii2c_msth13tddc_sclin
E-DDC Interface oi2c_msth13tddc_sclout
ii2c_msth13tddc_sdain
oi2c_msth13tddc_sdaout

Table 4-4 E-DDC Interface Signals Description

Width
Name (bits) I/O Description
ii2c_msth13tddc_sclin 1 I HDMI DDC I2C slave clock input for HDCP and E-EDID communication with
transmitter
Active State: N/A
Registered: No
Synchronous to: Asynchronous
Dependencies: None
oi2c_msth13tddc_sclout 1 O HDMI DDC I2C slave clock output
Active State: N/A
Registered: No
Synchronous to: Asynchronous
Dependencies: None
Value After Reset: 1
ii2c_msth13tddc_sdain 1 I HDMI DDC I2C slave data input for E-EDID access HDCP and ID
communication with transmitter.
Active State: N/A
Registered: No
Synchronous to: Asynchronous
Dependencies: None
oi2c_msth13tddc_sdaout 1 O HDMI DDC I2C slave data output for E-EDID access
Active State: N/A
Registered: No
Synchronous to: Asynchronous
Dependencies: None
Value After Reset: 1

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4.3.5 CEC Interface Signals

Use a 32,768 kHz clock to feed the icecclk input of the HDMI TX controller. The main reason is the
optimization handled for this frequency regarding bit timing tolerances, and robustness to detect CEC line
errors. See STAR 9000349252 for more details. You can obtain the 32,768 kHz clock from an external crystal,
or by dividing the isfrclk clock for HDMI with HDCP by 824: (for example, 27 MHz / 824 = 32.767 kHz).

Figure 4-6 CEC Interface Signals

DWC_hdmi_tx
icecclk
CEC Interface icecin
ocecout
ointerruptwakeup

Table 4-5 CEC Interface Signals Description

Width
Name (bits) I/O Description

icecclk 1 I CEC controller main clock input (Fixed frequency 32.768 kHz)
Active State: N/A
Registered: No
Synchronous to: N/A
Dependencies: CEC = 1

icecin 1 I CEC input data from CEC bus

Active State: N/A
Registered: No
Synchronous to: Asynchronous
Dependencies: CEC = 1

ocecout 1 O CEC output data to CEC bus

Active State: N/A
Registered: No
Synchronous to: Asynchronous
Dependencies: CEC = 1
Value After Reset: 1

ointerruptwakeup 1 O CEC engine dedicated interrupt signal raised by a wake-up event

Active State: N/A
Registered: No
Synchronous to: Asynchronous
Dependencies: Always present
Value After Reset: 0

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4.3.6 HDCP Encryption Engine Signals

To use the HDCP module, the isfrclk input clock (not shown in Table 4-6) must be 18 to 27 MHz so that the
HDCP timers operate correctly. These timers include time-outs used for the authentication protocol and for
the I2C bus to handle DDC operations.
Figure 4-7 HDCP Encryption Engine Signals

odpkclk DWC_hdmi_tx
idpkack
idpkdatain
56-bit DPK Memory Interface odpkaddr
odpkreq
odpkaccess

odpkmemreq
8-bit DPK Memory Interface odpkmemaddr
idpkmemdatai

irevocmemdatain
orevocmemclk
orevocmemaddress
Revocation Memory Interface orevocmemcs
orevocmemwen
orevocmemdataout

Random Number Generator Interface irndnum

orndnumgenena

Table 4-6 HDCP Encryption Engine Signal Descriptions

Width
Name (bits) I/O Description
odpkclk 1 O DPKs access clock signal (same as isfrclk clock)
Note: This signal does not stop under test/scan mode because it is directly
connected to sfrclk. If you require this output to be muted in scan mode, you
must connect it externally to the DWC_hdmi_tx core.
Active State: N/A
Registered: No
Synchronous to: N/A
Dependencies: HCDP = 1 (True)
Value After Reset: 0
56-bit DPK Memory Interface
idpkack 1 I Device Private Keys (DPKs) read access acknowledge signal
Active State: High
Registered: Yes
Synchronous to: odpkclk
Dependencies: HCDP = 1 (True) and DWC_HDMI_HDCP_DPK_8BIT = 0

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Table 4-6 HDCP Encryption Engine Signal Descriptions (Continued)

Width
Name (bits) I/O Description
idpkdatain 6 O DPKs data input bus
Active State: N/A
Registered: Yes
Synchronous to: odpkclk
Dependencies: HCDP = 1&DWC_HDMI_HDCP_DPK_8BIT = 0
odpkaddr 6 O DPKs address bus
Active State: N/A
Registered: Yes
Synchronous to: odpkclk
Dependencies: HCDP = 1&DWC_HDMI_HDCP_DPK_8BIT = 0
Value After Reset: 0x00
odpkreq 1 O DPKs read access request signal
Active State: High
Registered: Yes
Synchronous to: odpkclk
Dependencies: HCDP = 1&DWC_HDMI_HDCP_DPK_8BIT = 0
Value After Reset: 0
odpkaccess 1 O DPKs access notification signal
Active State: High
Registered: Yes
Synchronous to: odpkclk
Dependencies: HCDP = 1&DWC_HDMI_HDCP_DPK_8BIT = 0
Value After Reset: 0
8-bit DPK Memory Interface
odpkmemreq 1 O DPKs read enable
Active State: High
Registered: Yes
Synchronous to: odpkclk
Dependencies: HDCP = 1&DWC_HDMI_HDCP_DPK_8BIT = 1
Value After Reset: 0
odpkmemaddr 9 O DPKs Address bus
Active State: N/A
Registered: Yes
Synchronous to: odpkclk
Dependencies: HDCP = 1&DWC_HDMI_HDCP_DPK_8BIT = 1
Value After Reset: 0x00

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Table 4-6 HDCP Encryption Engine Signal Descriptions (Continued)

Width
Name (bits) I/O Description
idpkmemdatai 8 I DPKs input data bus
Active State: N/A
Registered: Yes
Synchronous to: odpkclk
Dependencies: HDCP = 1&DWC_HDMI_HDCP_DPK_8BIT = 1
Revocation Memory Interface
irevocmemdatain 8 I KSV MEM read data bus
Active State: N/A
Registered: Yes
Synchronous to: orevocmemclk
Dependencies: HCDP = 1
orevocmemclk 1 O KSV MEM clock signal (same as isfrclk clock)
Active State: N/A
Registered: No
Synchronous to: N/A
Dependencies: HCDP = 1
Value After Reset: 0
orevocmemaddress 13 O KSV MEM address bus
Active State: N/A
Registered: Yes
Synchronous to: orevocmemclk
Dependencies: HCDP = 1
Value After Reset: 0x1fff
orevocmemcs 1 O KSV MEM chip select signal
Active State: High
Registered: Yes
Synchronous to: orevocmemclk
Dependencies: HCDP = 1
Value After Reset: 0
orevocmemwen 1 O KSV MEM write enable
Active State: Low
Registered: Yes
Synchronous to: orevocmemclk
Dependencies: HCDP = 1
Value After Reset: 1

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Table 4-6 HDCP Encryption Engine Signal Descriptions (Continued)

Width
Name (bits) I/O Description
orevocmemdataout 8 O KSV MEM write data bus
Active State: N/A
Registered: Yes
Synchronous to: orevocmemclk
Dependencies: HCDP = 1
Value After Reset: 0x00
Random Number Generator Interface
This interface can be bypassed through the “HDCP AN Registers” on page 301.
irndnum 4 I Random Number input bus
Active State: N/A
Registered: Yes
Synchronous to: itmdsclk
Dependencies: HCDP = 1
orndnumgenena 1 O Random Number Generation enable
Active State: High
Registered: Yes
Synchronous to: itmdsclk
Dependencies: HCDP = 1
Value After Reset: 1

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4.3.7 Scan Test Interface Signals

The Scan Test Interface Signals include the scan mode clock, scan test mode enable, and HDMI controller
scan chain input signals. The dependencies are always present.

Figure 4-8 Scan Test Interface Signals

DWC_hdmi_tx
iscanclk
iscanrstz
iscanen
Scan Test Interface iscanmode
iscan_ctrl_in
oscan_ctrl_out
iscan_phy_in
oscan_phy_out

Table 4-7 Scan Test Interface Signals Description

Width
Name (bits) I/O Description

iscanclk 1 I Scan mode clock

Active State: N/A
Registered: No
Synchronous to: N/A
Dependencies: Always Present

iscanrstz 1 I Scan reset input

Active State: Low
Registered: Yes
Synchronous to: Asynchronous
Dependencies: Always Present

iscanen 1 I Scan test mode enable (must be low for normal operation)
Active State: Low
Registered: Yes
Synchronous to: iscanclk
Dependencies: Always Present

iscanmode 1 I Scan enable signal (must be low for normal operation)

Active State: Low
Registered: Yes
Synchronous to: iscanclk
Dependencies: Always Present

iscan_ctrl_in 1 I HDMI controller scan chain input

Active State: N/A
Registered: Yes
Synchronous to: iscanclk
Dependencies: Always Present

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Table 4-7 Scan Test Interface Signals Description (Continued)

Width
Name (bits) I/O Description

oscan_ctrl_out 1 O HDMI PHY scan chain input

Active State: N/A
Registered: Yes
Synchronous to: iscanclk
Dependencies: Always Present
Value After Reset: Hi-Z (not connected in RTL)

iscan_phy_in 1 I HDMI controller scan chain output

Active State: N/A
Registered: Yes
Synchronous to: iscanclk
Dependencies: Always Present

oscan_phy_out 1 O HDMI PHY scan chain output

Active State: N/A
Registered: Yes
Synchronous to: iscanclk
Dependencies: Always Present
Value After Reset: Hi-Z (not connected in RTL)

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4.3.8 HDMI TX PHY Interface Signals

The HDMI TX PHY Interface Signals include hot plug detect input, analog and digital power supply signals.

Figure 4-9 HDMI TX PHY Interface Signals

DWC_hdmi_tx
ihpd
ioavdd18
ioavdd10
iovdd
ioagnd18
HDMI TX PHY Interface ioagnd10
iovss
iorref
ioatestmon
otmdsdatap
otmdsdatan
otmdsclkp
otmdsclkn

Table 4-8 HDMI TX PHY Interface Signal Description

Width
Name (bits) I/O Description

ihpd 1 I Hot Plug Detect input

ioavdd18 1 I/O Analog power supply

ioavdd10 1 I/O Analog power supply

iovdd 1 I/O Digital power supply

ioagnd18 1 I/O Analog supply ground return

ioagnd10 1 I/O Analog supply ground return

iovss 1 I/O Digital supply ground return

iorref 1 I/O Current reference input. Used to connect to an external resistance for bias
current generation

ioatestmon 2 I/O Analog probing nodes for test debugging

otmdsdatap 3 O Positive TMDS differential line driver data output

otmdsdatan 3 O Negative TMDS differential line driver data output

otmdsclkp 1 O Positive TMDS differential line driver clock output

otmdsclkn 1 O Negative TMDS differential line driver clock output

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4.3.9 HDMI 3D TX PHY (PHY GEN 2) Interface Signals

HDMI 3D TX PHY (phy_gen2) Interface Signals include the analog power supply, reference resistors, and
TMDS differential line driver data output signals. The following signals are only written to the
DWC_hdmi_tx top-level interface when the controller is configured to use with the HDMI 3D TX PHY.

Figure 4-10 HDMI 3D TX PHY (phy_gen2) Interface Signals

DWC_hdmi_tx
iovp
iovp_filt0
iovp_filt1
iovp_filt2
iovph
iogd
HDMI 3D TX PHY Interface ioddccec
ioresref_f
ioresref_s
otmdsdatap
otmdsdatan
otmdsclkp
otmdsclkn
ophydtb

Table 4-9 HDMI 3D TX PHY (phy_gen2) Interface Signal Description

Width
Name (bits) I/O Descriptiona

iovp 1 I/O Analog power supply.

iovp_filt0 1 I/O Analog powe supply.

iovp_filt1 1 I/O Analog power supply

iovp_filt2 1 I/O Analog power supply

iovph 1 I/O Analog power supply

iogd 1 I/O Analog ground

ioddccec 1 I/O Ground reference for the Hot Plug Detect signal

ioresref_f 1 I/O Reference resistor connection

ioresref_s 1 I/O Precision resistor to ground

otmdsdatap 3 O Analog Positive TMDS differential line driver data output

otmdsdatan 3 O Analog Negative TMDS differential line driver data output

otmdsclkp 1 O Analog Positive TMDS differential line driver clock output

otmdsclkn 1 O Analog Negative TMDS differential line driver clock output

ophydtb 2 O PHY Digital Test Bus

a. For more information about these signals, refer to the PHY GEN2 databook.

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4.3.10 HDMI HEAC PHY Interface Signals

The HDMI HEAC PHY Interface Signals include digital power supply, digital and analog ground, and
termination analog power supply signals. The following signals are only written to the DWC_hdmi_tx top-
level interface when the controller is configured to use the HDMI 3D TX PHY (phy_gen2) AND when the
HDMI_HEAC_PHY_EN hardware configuration option is set to True (1).

Figure 4-11 HDMI HEAC PHY Interface Signals

DWC_hdmi_tx
iovdd_heac
iovss_heac
iogd_heac
iovph_heac
oheacphy_dtb
iscanin_heac
oscanout_heac
HDMI HEAC PHY Interface ihectxdatan
ihectxdatap
oarcrxdata
ioheacn
ioheacp
iohecrxdatan
iohecrxdatap
ioresext
ioresextv

Table 4-10 HDMI HEAC PHY Interface Signals Description

Width
Name (bits) I/O Description

iovdd_heac 1 I/O Digital power supply

iovss_heac 1 I/O Digital ground

iogd_heac 1 I/O Analog ground return path

iovph_heac 1 I/O Analog 2.5V power supply

oheacphy_dtb 2 O Digital Test Bus

iscanin_heac 1 I Scan In. Serial data stream input when core is in Scan mode.

oscanout_heac 1 O Scan Out. Serial data stream output when core is in Scan mode.

ihectxdatan 1 I Input data for HEAC– (negative pulse)

ihectxdatap 1 I Input data for HEAC+ (positive pulse)

oarcrxdata 1 O Output from ARC RX

ioheacn 1 I/O Analog HEAC- (negative pulse)

ioheacp 1 I/O Analog HEAC+ (positive pusle)

iohecrxdatan 1 I/O Analog negative output for the modified 100BaseTX PHY

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Table 4-10 HDMI HEAC PHY Interface Signals Description (Continued)

Width
Name (bits) I/O Description

iohecrxdatap 1 I/O Analog positive output for the modified 100BaseTX PHY

ioresext 1 I/O Analog external reference resistor

ioresextv 1 I/O Analog external reference resistor ground

Attention HEAC PHY is only available with the phy_gen2 interface.

4.3.11 HDMI TX External PHY Signals

The HDMI TX External PHY Interface Signals include the encoded data port, clock inputs, and a PHY
configuration interface. The following signals are only written to the DWC_hdmi_tx top-level interface
when the controller is configured for use with the External PHY and the parameter PHY_EXTERNAL= 1.

Figure 4-12 HDMI TX External PHY Signals

DWC_hdmi_tx
iphyext_tclk
iphyext_prepclk
ophyext_dataencoded
ophyext_rstz
iphyext_lock
iphyext_rxsense
ophyext_ppdq
ophyext_txpwron
HDMI TX External PHY Signals iphyext_hpd
ophyext_enhpdrxsense
ophyext_sparectl
ophyext_i2c_sdaout
ophyext_i2c_sclout
iphyext_i2c_sclin
iphyext_i2c_sdain

The signals that are described as optional in descriptions are not mandatory when the PHY configuration
and status pooling is done by other means.
The Synopsys HDMI Transmit API Low-Level Driver does not support an external PHY (non-Synopsys).
The interruption mechanism set by registers PHY_STAT0, PHY_INT0, PHY_MASK0 and PHY_POL0 is
operational when the PHY_EXTERNAL parameter is defined, and the inputs iphyext_lock, iphyext_hpd
and iphyext_rxsense are connected.

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I2C Interface for PHY Configuration

An I2C interface is provided to be used for PHY configuration and status reading. This I2C implementation
has a 16-bit data interface (two data words) with the transmission structure shown here. This structure is
controlled by the “I2C Master PHY Registers” on page 234.

Figure 4-13 I2C Interface for PHY Configuration

Figure 4-14 on page 124 shows the standard connection of the PHY I2C Master to an I2C bus.

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Figure 4-14 Connection of External PHY I2C Master to I2C Bus

iphyext_i2c_sdain I2C SDA Line

ophyext_i2c_sdaout

DWC_hdmi_tx

iphyext_i2c_sclin I2C SCL Line

ophyext_i2c_sdout

Table 4-11 HDMI TX External PHY Interface Signals Description

Width
Name (bits) I/O Description

iphyext_tclk 1 I TMDS clock for controller (symbol clock)

Active State: N/A
Registered: No
Synchronous to: Asynchronous
Dependencies: PHY_EXTERNAL=1
Value After Reset: N/A
Optional: No

iphyext_prepclk 1 I Pixel repetition clock for controller

Active State: N/A
Registered: No
Synchronous to: Asynchronous
Dependencies: PHY_EXTERNAL=1 and
DWC_HDMI_TX_INTPREPEN=1
Optional: No

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Table 4-11 HDMI TX External PHY Interface Signals Description

Width
Name (bits) I/O Description

ophyext_dataencoded 30 I Encoded data vector by TERC4, 2b10b and 8b10b as per the HDMI
1.4b Specification
■ Channel 0 - ophyext_dataencoded [ 9: 0]
■ Channel 1 - ophyext_dataencoded [19:10]
■ Channel 2 - ophyext_dataencoded [29:20]
Active State: N/A
Registered: Yes
Synchronous to: iphyext_tclk
Dependencies: PHY_EXTERNAL=1
Value After Reset: 30'd0
Optional: No

ophyext_rstz 1 O Software controlled PHY reset

Mapped to register mc_phyrstz, bit 0.
Active State: Low
Registered: Yes
Synchronous to: isfrclk
Dependencies: PHY_EXTERNAL=1
Value After Reset: 1
Optional: Yes

iphyext_lock 1 I PHY status: PLL lock

Mapped to register phy_stat0, bit 0.
Active State: Logic high when locked
Registered: Yes
Synchronous to: isfrclk
Dependencies: PHY_EXTERNAL=1
Optional: Yes

iphyext_rxsense 1 I HDMI link status: Sink detected signal

Mapped to register phy_stat0, bit 4.
Active State: Logic high when HDMI RX present
Registered: No
Synchronous to: isfrclk
Dependencies: PHY_EXTERNAL=1
Optional: Yes

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Table 4-11 HDMI TX External PHY Interface Signals Description

Width
Name (bits) I/O Description

ophyext_ppdq 1 O PHY configuration: Power down control

Mapped to register phy_conf0, bit 4.
Active State: N/A
Registered: Yes
Synchronous to: isfrclk
Dependencies: PHY_EXTERNAL=1
Value After Reset: 0
Optional: Yes

ophyext_txpwron 1 O PHY configuration: transmitter power on

Mapped to register phy_conf0, bit 3.
Active State: N/A
Registered: Yes
Synchronous to: isfrclk
Dependencies: PHY_EXTERNAL=1
Value After Reset: 0
Optional: Yes

iphyext_hpd 1 I HDMI link status: Hot Plug Detect signal

Mapped to register phy_stat0, bit 1.
Active State: Logic high when HPD present
Registered: Yes
Synchronous to: isfrclk
Dependencies: PHY_EXTERNAL=1
Optional: Yes

ophyext_enhpdrxsense 1 O PHY configuration: HPD and RX sense enable

Mapped to register phy_conf0, bit 2.
Active State: N/A
Registered: Yes
Synchronous to: isfrclk
Dependencies: PHY_EXTERNAL=1
Value After Reset: 0
Optional: Yes

ophyext_sparectl 1 O PHY configuration: Spare control bit

Mapped to register phy_conf0, bit 5.
Active State: N/A
Registered: Yes
Synchronous to: isfrclk
Dependencies: PHY_EXTERNAL=1
Value After Reset: 0
Optional: Yes

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Table 4-11 HDMI TX External PHY Interface Signals Description

Width
Name (bits) I/O Description

ophyext_i2c_sdaout 1 O PHY configuration: I2C SDA output

Active State: N/A
Registered: Yes
Synchronous to: isfrclk
External Input Delay: N/A
Dependencies: PHY_EXTERNAL=1
Value After Reset: 1
Optional: Yes

ophyext_i2c_sclout 1 O PHY configuration: I2C SCL output

Active State: N/A
Registered: Yes
Synchronous to: isfrclk
External Input Delay: N/A
Dependencies: PHY_EXTERNAL=1
Value After Reset: 1
Optional: Yes

iphyext_i2c_sclin 1 I PHY configuration: I2C SCL input

Active State: N/A
Registered: No
Synchronous to: Asynchronous
External Input Delay: N/A
Dependencies: PHY_EXTERNAL=1
Optional: Yes

iphyext_i2c_sdain 1 I PHY configuration: I2C SDA input

Active State: N/A
Registered: No
Synchronous to: Asynchronous
External Input Delay: N/A
Dependencies: PHY_EXTERNAL=1
Optional: Yes

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5
Software Registers

The following subsections describe the HDMI TX software registers:

■ “Register Memory Map” on page 130
■ “Register and Field Descriptions” on page 147

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5.1 Register Memory Map

All registers are byte addressable; each unused bit or address location is reserved for future use and read
back as 0.
The following registers are covered in this memory map:
■ “Identification Registers” on page 130
■ “Interrupt Registers” on page 131
■ “Video Sampler Registers” on page 132
■ “Video Packetizer Registers” on page 132
■ “Frame Composer Registers” on page 133
■ “HDMI Source PHY Registers” on page 138
■ “I2C Master PHY Registers” on page 138
■ “Audio Sampler Registers” on page 139
■ “Generic Parallel Audio Interface Registers” on page 140
■ “Audio DMA Registers” on page 140
■ “Main Controller Registers” on page 141
■ “Color Space Converter Registers” on page 142
■ “HDCP Encryption Engine Registers” on page 142
■ “HDCP BKSV Registers” on page 144
■ “HDCP AN Registers” on page 144
■ “CEC Engine Registers” on page 144
■ “I2C Master Registers (E-DDC)” on page 145
Table 5-1 on page 130 summarizes the register memory map for HDMI TX.

Table 5-1 HDMI TX Memory Map

Address Value after

Name Offset Width R/W Description Reset
Identification Registers
design_id (page 148) 0x0000 8 bits R Design Identification Register 0x14
revision_id (page 148) 0x0001 8 bits R Revision Identification Register 0x0A
product_id0 (page 149) 0x0002 8 bits R Product Identification Register 0 0xA0
product_id1 (page 149) 0x0003 8 bits R Product Identification Register 1 Implementation
Dependent
config0_id (page 150) 0x0004 8 bits R Configuration Identification Register Implementation
0 Dependent

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Table 5-1 HDMI TX Memory Map (Continued)

Address Value after

Name Offset Width R/W Description Reset
config1_id (page 150) 0x0005 8 bits R Configuration Identification Register Implementation
1 Dependent
config2_id (page 151) 0x0006 8 bits R Configuration Identification Register Implementation
2 Dependent
config3_id (page 151) 0x0007 8 bits R Configuration Identification Register Implementation
3 Dependent
Reserved and read as zero
Interrupt Registers
ih_fc_stat0 (page 152) 0x0100 8 bits CoW/ Read Only Packet Sent Sticky Bit 0x00
R Interrupt
ih_fc_stat1 (page 153) 0x0101 8 bits CoW/ Read Only Packet Sent Sticky Bit 0x00
R Interrupt
ih_fc_stat2 (page 153) 0x0102 8 bits CoW/ Read Only Packet Queue Overflow 0x00
R Sticky Bit Interrupt
ih_as_stat0 (page 154) 0x0103 8 bits CoW/ Read Only Audio FIFO Sticky Bit 0x00
R Interrupt
ih_phy_stat0 (page 154) 0x0104 8 bits CoW/ Read Only Sticky Bit Interrupt 0x00
R
ih_i2cm_stat0 (page 155) 0x0105 8 bits CoW/ Read Only Sticky Bit Interrupt 0x00
R
ih_cec_stat0 (page 155) 0x0106 8 bits CoW/ Read Only Sticky Bit Interrupt 0x00
R
ih_vp_stat0 (page 156) 0x0107 8 bits CoW/ Read Only Sticky Bit Interrupt 0x00
R
ih_i2cmphy_stat0 (page 157) 0x0108 8 bits CoW/ PHY GEN2 I2C Master Interrupt 0x00
R Status Register
ih_ahbdmaaud_stat0 (page 157) 0x0109 8 bits CoW/ AHB Audio DMA Interrupt Status 0x00
R Register
Reserved and read as zero
ih_decode (page 158) 0x0170 8 bits R Interruption Handler Decode Assist 0x00
Register
ih_mute_fc_stat0 (page 157) 0x0180 8 bits R/W Mute ih_fc_stat0 0x00
ih_mute_fc_stat1 (page 159) 0x0181 8 bits R/W Mute ih_fc_stat1 0x00
ih_mute_fc_stat2 (page 159) 0x0182 8 bits R/W Mute ih_fc_stat2 0x00
ih_mute_as_stat0 (page 160) 0x0183 8 bits R/W Mute ih_as_stat0 0x00
ih_mute_phy_stat0 (page 160) 0x0184 8 bits R/W Mute ih_phy_stat0 0x00

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Table 5-1 HDMI TX Memory Map (Continued)

Address Value after

Name Offset Width R/W Description Reset
ih_mute_i2cm_stat0 (page 161) 0x0185 8 bits R/W Mute ih_i2cm_stat0 0x00
ih_mute_cec_stat0 (page 161) 0x0186 8 bits R/W Mute ih_cec_stat0 0x00
ih_mute_vp_stat0 (page 162) 0x0187 8 bits R/W Mute ih_vp_stat0 0x00
ih_mute_i2cmphy_stat0 (page 162) 0x0188 8 bits R/W Mute ih_i2cmphy_stat0 0x00
ih_mute_ahbdmaaud_stat0 (page 0x0189 8 bits R/W Mute ih_ahbdmaaud_stat0 0x00
163)
ih_mute (page 163) 0x01FF 8 bits R/W Mute All Interrupts 0x03
Reserved and read as zero
Video Sampler Registers
tx_invid0 (page 164) 0x0200 8 bits R/W Input Video Mapping 0x01
tx_instufffing (page 165) 0x0201 8 bits R/W Video Stuffing Control 0x00
tx_gydata0 (page 165) 0x0202 8 bits R/W G and Y Data In Stuffing Mode 0x00
tx_gydata1 (page 166) 0x0203 8 bits R/W G and Y Data In Stuffing Mode 0x00
tx_rcrdata0 (page 166) 0x0204 8 bits R/W G and Cr Data In Stuffing Mode 0x00
tx_rcrdata1 (page 166) 0x0205 8 bits R/W G and Cr Data In Stuffing Mode 0x00
tx_bcbdata0 (page 167) 0x0206 8 bits R/W B and Cb Data In Stuffing Mode 0x00
tx_bcbdata1 (page 167) 0x0207 8 bits R/W B and Cb Data In Stuffing Mode 0x00
Reserved and read as zero
Video Packetizer Registers
vp_status (page 168) 0x0800 8 bits R Packing Phase Indication 0x00
vp_pr_cd (page 169) 0x0801 8 bits R/W Pixel Repetition Factor and Color 0x00
Depth Configuration
vp_stuff (page 170) 0x0802 8 bits R/W Pixel Repetition, Pixel packing, and 0x00
YCC422 Stuffing Control
vp_remap (page 171) 0x0803 8 bits R/W YCC 422 Remap Control 0x00
vp_conf (page 172) 0x0804 8 bits R/W Output Selection, Bypass Select, 0x46
YCC422 Enable, Pixel Repeater, or
Pixel Packing Enable
Reserved and read as zero 0x0805 to
0x0806
vp_mask (page 173) 0x0807 8 bits R/W VP FIFOs Interrupt Mask 0x00
Reserved and read as zero

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Table 5-1 HDMI TX Memory Map (Continued)

Address Value after

Name Offset Width R/W Description Reset
Frame Composer Registers
fc_invidconf (page 174) 0x1000 8 bits R/W Interlaced/progressive, Vblank 0x70
variation, DVI Operation Mode, and
Polarity of All Input Video
Synchronism signals
fc_inhactiv0 (page 175) 0x1001 8 bits R/W Input Video Horizontal Active Pixel 0x00
fc_inhactiv1 (page 175) 0x1002 8 bits R/W Region 0x00
fc_inhblank0 (page 176) 0x1003 8 bits R/W Input Video Horizontal Blank Pixel 0x00
fc_inhblank1 (page 176) 0x1004 8 bits R/W Region 0x00
fc_invactiv0 (page 177) 0x1005 8 bits R/W 0x00
Input Video Vertical Active Lines
fc_invactiv1 (page 177) 0x1006 8 bits R/W 0x00
fc_invblank (page 178) 0x1007 8 bits R/W Input Video Vertical Blank Lines 0x00
fc_hsyncindelay0 (page 178) 0x1008 8 bits R/W 0x00
Hsync Active Edge Delay
fc_hsyncindelay1 (page 179) 0x1009 8 bits R/W 0x00
fc_hsyncinwidth0 (page 179) 0x100A 8 bits R/W 0x00
Hsync Active Pulse Width
fc_hsyncinwidth1 (page 180) 0x100B 8 bits R/W 0x00
fc_vsyncindelay (page 180) 0x100C 8 bits R/W Vsync Active Edge Delay 0x00
fc_vsyncinwidth (page 181) 0x100D 8 bits R/W Vsync Active Pulse Width 0x00
fc_infreq0 (page 181) 0x100E 8 bits R/W Video Refresh Rate in Hz*1E3 0x00
fc_infreq1 (page 182) 0x100F 8 bits R/W 0x00
fc_infreq2 (page 182) 0x1010 8 bits R/W 0x00
fc_ctrldur (page 183) 0x1011 8 bits R/W Control Period Duration 0x00
fc_exctrldur (page 183) 0x1012 8 bits R/W Extended Control Period Duration 0x00
fc_exctrlspac (page 183) 0x1013 8 bits R/W Extend Control Period Maximum 0x00
Spacing
fc_ch0pream (page 184) 0x1014 8 bits R/W 8-bit Filling for Preamble Filler for 0x00
Ch0
fc_ch1pream (page 184) 0x1015 8 bits R/W 6-bit Filling for Preamble Filler for 0x00
Ch1
fc_ch2pream (page 185) 0x1016 8 bits R/W 6-bit Filling for Preamble Filler for 0x00
Ch2
fc_aviconf3 (page 185) 0x1017 8 bits R/W Quantization range and IT content 0x00
type according to CEA specification

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Table 5-1 HDMI TX Memory Map (Continued)

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5.2 Register and Field Descriptions

The following subsections describe the data fields of the HDMI TX registers.
■ “Identification Registers”
■ “Interrupt Registers” on page 152
■ “Video Sampler Registers” on page 164
■ “Video Packetizer Registers” on page 168
■ “Frame Composer Registers” on page 174
■ “HDMI Source PHY Registers” on page 226
■ “I2C Master PHY Registers” on page 234
■ “Audio Sampler Registers” on page 244
■ “Main Controller Registers” on page 269
■ “Color Space Converter Registers” on page 275
■ “HDCP Encryption Engine Registers” on page 284
■ “HDCP BKSV Registers” on page 299
■ “HDCP AN Registers” on page 301
■ “CEC Engine Registers” on page 305
■ “I2C Master Registers (E-DDC)” on page 313

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5.2.1 Identification Registers

The following are the registers used to identify the DWC_hdmi_tx controller.

5.2.1.1 design_id
■ Name: Design Identification Register
■ Address Offset: 0x0000
■ Size: 8 bits
■ Value after Reset: 0x13
■ Access: Read

Table 5-2 Design Identification Register

Bits Name R/W Description

7:0 design_id R Design ID code fixed by Synopsys that identifies the instantiated
DWC_hdmi_tx controller.
For example, dwc_hdmi_tx 1.31a, DESIGN_ID = 13

5.2.1.2 revision_id
■ Name: Revision Identification Register
■ Address Offset: 0x0001
■ Size: 8 bits
■ Value after Reset: 0x2A
■ Access: Read

Table 5-3 Revision Identification Register

Bits Name R/W Description

7:0 revision_id R Revision ID code fixed by Synopsys that Identifies the instantiated
DWC_hdmi_tx controller.
For example, dwc_hdmi_tx 1.31a, REVISION_ID = 1Ah

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5.2.1.3 product_id0
■ Name: Product Identification Register 0
■ Address Offset: 0x0002
■ Size: 8 bits
■ Value after Reset: 0xA0
■ Access: Read

Table 5-4 Product identification Register 0

Bits Name R/W Description

7:0 product_id0 R This one byte fixed code Identifies Synopsys's product line (“A0h” for
DWC_hdmi_tx products).

5.2.1.4 product_id1
■ Name: Product Identification Register 1
■ Address Offset: 0x0003
■ Size: 8 bits
■ Value after Reset: Implementation Dependent
■ Access: Read

Table 5-5 Product Identification Register 1

Bits Name R/W Description

7:6 product_id1_tx_hdcp R These bits identifiy a Synopsys’ HDMI Controller with HDCP encryption
according to Synopsys product line.

5:2 Reserved and read as zero

1 product_id1_rx R This bit Identifies Synopsys DWC_hdmi_tx Controller according to

Synopsys product line.

0 product_id1_tx R This bit Identifies Synopsys DWC_hdmi_tx Controller according to

Synopsys product line.

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5.2.1.5 config0_id
■ Name: Configuration Identification Register 0
■ Address Offset: 0x0004
■ Size: 8 bits
■ Value after Reset: Implementation Dependent
■ Access: Read

Table 5-6 Configuration Identification Register 0

Bits Name R/W Description

7 prepen R Indicates if it is possible to use internal pixel repetition

6 Reserved and read as zero

5 audspdif R Indicates if S/PDIF interface is present

4 audi2s R Indicates if I2S interface is present

3 hdmi14 R Indicates if HDMI 1.4 features are present

2 csc R Indicates if Color Space Conversion block is present

1 cec R Indicates if CEC is present

0 hdcp R Indicates if HDCP is present

5.2.1.6 config1_id
■ Name: Configuration Identification Register 1
■ Address Offset: 0x0005
■ Size: 8 bits
■ Value after Reset: Implementation Dependent
■ Access: Read

Table 5-7 Configuration Identification Register 1

Bits Name R/W Description

7:2 Reserved and read as zero

1 confapb R Indicates that configuration interface is APB interface

0 Reserved and read as zero

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5.2.1.7 config2_id
■ Name: Configuration Identification Register 2
■ Address Offset: 0x0006
■ Size: 8 bits
■ Value after Reset: Implementation Dependent
■ Access: Read

Table 5-8 Configuration Identification Register 2

Bits Name R/W Description

7:0 phytype R Indicates the type of PHY interface selected:

0x00: Legacy PHY (HDMI TX PHY)
0xF2: PHY_Gen2 (HDMI 3D TX PHY)
0xE2: PHY_Gen2 (HDMI 3D TX PHY) + HEAC PHY

5.2.1.8 config3_id
■ Name: Configuration Identification Register 3
■ Address Offset: 0x0007
■ Size: 8 bits
■ Value after Reset: Implementation Dependent
■ Access: Read

Table 5-9 Configuration Identification Register 3

Bits Name R/W Description

7:2 Reserved and read as zero

1 confahbauddma R Indicates that the audio interface is AHB AUD DMA

0 confgpaud R Indicates that the audio interface is Generic Parallel Audio (GPAUD)

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5.2.2 Interrupt Registers

This section describes clear on write (1 to corresponding bit) status registers, which contain the following
active-high, sticky bit interrupts.
DWC_hdmi_tx introduces a new set of sticky bit mute control registers (ih_mute_fc_stat0 to
ih_mute_ahbdmaaud_stat0) that correspond to the interrupt registers. You can ignore a sticky bit interrupt
by setting the corresponding mute control register bit to 1. This puts the global interrupt line on a higher
priority than the sticky bit interrupt.

5.2.2.1 ih_fc_stat0
■ Name: Frame Composer Interrupt Status Register 0 - Packet interrupts
■ Address Offset: 0x0100
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Clear on Write/Read

Table 5-10 ih_fc_stat0 Register

Bits Name R/W Description

7 AUDI CoW/R Active after successful transmission of an Audio InfoFrame packet.

6 ACP CoW/R Active after successful transmission of an Audio Content Protection packet.

5 HBR CoW/R Active after successful transmission of an Audio HBR packet.

4:3 Reserved and read as zero

2 AUDS CoW/R Active after successful transmission of an Audio Sample packet. Due to high number of
audio sample packets transmitted, this interrupt is by default masked at frame
composer.

1 ACR CoW/R Active after successful transmission of an Audio Clock Regeneration (N/CTS
transmission) packet.

0 NULL CoW/R Active after successful transmission of a Null packet. Due to high number of audio
sample packets transmitted, this interrupt is by default masked at frame composer.

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5.2.2.2 ih_fc_stat1
■ Name: Frame Composer Interrupt Status Register 1 – Packet Interrupts
■ Address Offset: 0x0101
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Clear on Write/Read

Table 5-11 ih_fc_stat1 Register

Bits Name R/W Description

7 GMD CoW/R Active after successful transmission of an Gamut metadata packet.

6 ISCR1 CoW/R Active after successful transmission of an International Standard Recording Code 1
packet.

5 ISCR2 CoW/R Active after successful transmission of an International Standard Recording Code 2
packet.

4 VSD CoW/R Active after successful transmission of an Vendor Specific Data infoFrame packet.

3 SPD CoW/R Active after successful transmission of an Source Product Descriptor infoFrame
packet.

2 Reserved and read as zero

1 AVI CoW/R Active after successful transmission of an AVI infoFrame packet.

0 GCP CoW/R Active after successful transmission of an General Control Packet.

5.2.2.3 ih_fc_stat2
■ Name: Frame Composer Interrupt Status Register 2 – Packet Queue Overflow Interrupts
■ Address Offset: 0x0102
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Clear on Write/Read

Table 5-12 ih_fc_stat2 Register

Bits Name R/W Description

7:2 Reserved and read as zero

1 LowPriority_overflow CoW/R Frame Composer low priority packet queue descriptor overflow
indication.

0 HighPriority_overflow CoW/R Frame Composer high priority packet queue descriptor overflow
indication.

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5.2.2.4 ih_as_stat0
■ Name: Audio Sampler Interrupt Status Register – FIFO Threshold, Underflow and Overflow
Interrupts
■ Address Offset: 0x0103
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Clear on Write/Read

Table 5-13 ih_as_stat0 Register

Bits Name R/W Description

7:5 Reserved and read as zero

4 fifo_underrun CoW/R Indicates an underrun on the audio FIFO

This bit is only present when the AUDIO_IF is set to AHBAUDDMA.

3 fifo_overrun CoW/R Indicates an overrun on the audio FIFO.

2 Aud_fifo_underflow_thr CoW/R Audio Sampler audio FIFO empty threshold (four samples) indication
for HBR audio
For AHB_DMA, this bit indicates that the number of samples in the
FIFO is equal to (or less) than the number of active audio channels.

1 Aud_fifo_underflow CoW/R Audio Sampler audio FIFO empty indication

0 Aud_fifo_overflow CoW/R Audio Sampler audio FIFO full indication

5.2.2.5 ih_phy_stat0
■ Name: PHY Interface Interrupt Status Register – RXSENSE, PLL Lock, and HPD Interrupts
■ Address Offset: 0x0104
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Clear on Write/Read

Table 5-14 ih_phy_stat0 Register

Bits Name R/W Description

7:6 Reserved and read as zero

5 RX_SENSE[3] CoW/R TX PHY RX_SENSE indication for driver 3. You may need to mask or
change polarity of this interrupt after it has become active.

4 RX_SENSE[2] CoW/R TX PHY RX_SENSE indication for driver 2. You may need to mask or
change polarity of this interrupt after it has become active.

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Table 5-14 ih_phy_stat0 Register (Continued)

Bits Name R/W Description

3 RX_SENSE[1] CoW/R TX PHY RX_SENSE indication for driver 1. You may need to mask or
change polarity of this interrupt after it has become active.

2 RX_SENSE[0] CoW/R TX PHY RX_SENSE indication for driver 0. You may need to mask or
change polarity of this interrupt after it has become active.

1 TX_PHY_LOCK CoW/R TX PHY PLL lock indication. Please refer to PHY datasheet for more
information. You may need to mask or change polarity of this interrupt
after it has become active.

0 HDP CoW/R HDMI Hot Plug Detect indication. You may need to mask or change
polarity of this interrupt after it has become active.

5.2.2.6 ih_i2cm_stat0
■ Name: E-DDC I2C Master Interrupt Status Register – Done and Error Interrupts
■ Address Offset: 0x0105
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Clear on Write/Read

Table 5-15 ih_i2cm_stat0 Register

Bits Name R/W Description

7:2 Reserved and read as zero

1 I2Cmasterdone CoW/R I2C Master done indication

0 I2Cmastererror CoW/R I2C Master error indication

5.2.2.7 ih_cec_stat0
This register exists when the hardware configuration parameter CEC = 1 (True).
■ Name: CEC Interrupt Status Register – Functional Operation Interrupts
■ Address Offset: 0x0106
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Clear on Write/Read

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Table 5-16 ih_cec_stat0 Register

Bits Name R/W Description

7 Reserved and read as zero

6 WAKEUP CoW/R CEC Wake-up indication

5 ERROR_FOLLOW CoW/R CEC Error_follow indication

4 ERROR_INITIATOR CoW/R CEC Error_follow indication

3 ARB_LOST CoW/R CEC Arb_Lost indication

2 NACK CoW/R CEC Nack indication

1 EOM CoW/R CEC End of Message Indication

0 DONE CoW/R CEC Done Indication

5.2.2.8 ih_vp_stat0
■ Name: Video Packetizer Interrupt Status Register – FIFO Full and Empty Interrupts
■ Address Offset: 0x0107
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Clear on Write/Read

Table 5-17 ih_vp_stat0 Register

Bits Name R/W Description

7 fifofullrepet CoW/R Video packetizer pixel repeater FIFO full interrupt

6 fifoemptyrepet CoW/R Video packetizer pixel repeater FIFO empty interrupt

5 fifofullpp CoW/R Video packetizer pixel packing FIFO full interrupt

4 fifoemptypp CoW/R Video packetizer pixel packing FIFO empty interrupt

3 fifofullremap CoW/R Video packetizer pixel YCC 422 re-mapper FIFO full interrupt

2 fifoemptyremap CoW/R Video packetizer pixel YCC 422 re-mapper FIFO empty interrupt

1 fifofullbyp CoW/R Video packetizer 8 bit bypass fifo full interrupt

0 fifoemptybyp CoW/R Video packetizer 8 bit bypass fifo empty interrupt

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5.2.2.9 ih_i2cmphy_stat0
This clear on write (1 to corresponding bit) register contains the following active high sticky bit interrupts.
That I2C Master PHY is the I2C Master block used to access the PHY I2C Slave. This register exists when the
hardware configuration parameter PHY_EXTERNAL = 1 (True) or a GEN2 PHY is used.
■ Name: PHY GEN2 I2C Master Interrupt Status Register – Done and Error Interrupts
■ Address Offset: 0x0108
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Clear on Write/Read

Table 5-18 ih_i2cmphy_stat0 Register

Bits Name R/W Description

7:2 Reserved and read as zero

1 i2cmphydone CoW/R I2C Master PHY done indication

0 i2cmphyerror CoW/R I2C Master PHY error indication

5.2.2.10 ih_ahbdmaaud_stat0
■ Name: AHB Audio DMA Interrupt Status Register – Functional Operation and Buffer Full and
Empty Interrupts
■ Address Offset: 0x0109
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Clear on Write/Read
Table 5-19 ih_ahbdmaaud_stat0

Bits Name R/W Description

7 Reserved and read as zero

6 ahbdmaaud_intbuffoverrun CoW/R AHB audio DMA Buffer underrun interruption

5 ahbdmaaud_interror CoW/R AHB audio DMA error interrupt

4 ahbdmaaud_intlostownership CoW/R AHB audio DMA lost ownership interrupt

3 ahbdmaaud_intretrysplit CoW/R AHB audio DMA RETRY/SPLIT interrupt

2 ahbdmaaud_intdone CoW/R AHB audio DMA done interrupt

1 ahbdmaaud_intbufffull CoW/R AHB audio DMA Buffer full interrupt

0 ahbdmaaud_intbuffempty CoW/R AHB audio DMA Buffer empty interrupt

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5.2.2.11 ih_decode
This register allows to quick decoding of which interruptions has triggered the rise of the DWC_hdmi_tx
interruption output port. Only the unmuted interruptions are observed in this register.
■ Name: Interruption Handler Decode Assist Register
■ Address Offset: 0x0170
■ Size: 8 bits per register
■ Value after Reset: 0x00
■ Access: Read
Table 5-20 ih_decode

Bits Name R/W Description

7 ih_fc_stat0 R Interruption active at the ih_fc_stat0 register
6 ih_fc_stat1 R Interruption active at the ih_fc_stat1 register
5 ih_fc_stat2_vp R Interruption active at the ih_fc_stat2 or ih_vp_stat0 register
4 ih_as_stat0 R Interruption active at the ih_as_stat0 register
3 ih_phy R Interruption active at the ih_phy_stat0 or ih_i2cmphy_stat0 register
2 ih_i2cm_stat0 R Interruption active at the ih_i2cm_stat0 register
1 ih_cec_stat0 R Interruption active at the ih_cec_stat0 register
0 ih_ahbdmaaud_stat0 R Interruption active at the ih_ahbdmaaud_stat0 register

5.2.2.12 ih_mute_fc_stat0
■ Name: Frame Composer Interrupt Mute Control Register 0
■ Address Offset: 0x0180
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-21 ih_mute_fc_stat0

Bits Name R/W Description

7 AUDI R/W When set to 1, mutes ih_fc_stat0[7]
6 ACP R/W When set to 1, mutes ih_fc_stat0[6]
5 Reserved and read as zero
4 DST R/W When set to 1, mutes ih_fc_stat0[4]
3 OBA R/W When set to 1, mutes ih_fc_stat0[3]
2 AUDS R/W When set to 1, mutes ih_fc_stat0[2]
1 ACR R/W When set to 1, mutes ih_fc_stat0[1]
0 NULL R/W When set to 1, mutes ih_fc_stat0[0]

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5.2.2.13 ih_mute_fc_stat1
■ Name: Frame Composer Interrupt Mute Control Register 1
■ Address Offset: 0x0181
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-22 ih_mute_fc_stat1

Bits Name R/W Description

7 GMD R/W When set to 1, mutes ih_fc_stat1[7]
6 ISCR1 R/W When set to 1, mutes ih_fc_stat1[6]
5 ISCR2 R/W When set to 1, mutes ih_fc_stat1[5]
4 VSD R/W When set to 1, mutes ih_fc_stat1[4]
3 SPD R/W When set to 1, mutes ih_fc_stat1[3]
2 Reserved and read as zero
1 AVI R/W When set to 1, mutes ih_fc_stat1[1]
0 GCP R/W When set to 1, mutes ih_fc_stat1[0]

5.2.2.14 ih_mute_fc_stat2
■ Name: Frame Composer Interrupt Mute Control Register 2
■ Address Offset: 0x0182
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-23 ih_mute_fc_stat2

Bits Name R/W Description

7:2 Reserved and read as zero

1 LowPriority_overflow R/W When set to 1, mutes ih_ fc_stat2[1]

0 HighPriority_overflow R/W When set to 1, mutes ih_fc_stat2[0]

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5.2.2.15 ih_mute_as_stat0
■ Name: Audio Sampler Interrupt Mute Control Register 0
■ Address Offset: 0x0183
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-24 ih_mute_as_stat0

Bits Name R/W Description

7:5 Reserved and read as zero
4 fifo_underrun R/W When set to 1, mutes ih_as_stat0[4]
This bit is only present when the AUDIO_IF is set to AHBAUDDMA (8).
3 fifo_overrun R/W When set to 1, mutes ih_as_stat0[3]
2 Aud_fifo_underflow_thr R/W When set to 1, mutes ih_ as_stat0[2]
1 Aud_fifo_underflow R/W When set to 1, mutes ih_ as_stat0[1]
0 Aud_fifo_overflow R/W When set to 1, mutes ih_ as_stat0[0]

5.2.2.16 ih_mute_phy_stat0
■ Name: PHY Interface Interrupt Mute Control Register
■ Address Offset: 0x0184
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-25 ih_mute_phy_stat0 Register

Bits Name R/W Description

7:6 Reserved and read as zero

5 RX_SENSE_3 R/W When set to 1, mutes ih_phy_stat0[5]

4 RX_SENSE_2 R/W When set to 1, mutes ih_phy_stat0[4]

3 RX_SENSE_1 R/W When set to 1, mutes ih_phy_stat0[3]

2 RX_SENSE_0 R/W When set to 1, mutes ih_phy_stat0[2]

1 TX_PHY_LOCK R/W When set to 1, mutes ih_phy_stat0[1]

0 HDP R/W When set to 1, mutes ih_phy_stat0[0]

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5.2.2.17 ih_mute_i2cm_stat0
■ Name: E-DDC I2C Master Interrupt Mute Control Register
■ Address Offset: 0x0185
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-26 ih_mute_i2cm_stat0 Register

Bits Name R/W Description

7:2 Reserved and read as zero

1 I2Cmasterdone R/W When set to 1, mutes ih_i2cm_stat0[1]

0 I2Cmaster error R/W When set to 1, mutes ih_i2cm_stat0[0]

5.2.2.18 ih_mute_cec_stat0
This register exists when the hardware configuration parameter CEC = 1 (True).
■ Name: CEC Interrupt Mute Control Register
■ Address Offset: 0x0186
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-27 ih_mute_cec_stat0

Bits Name R/W Description

7 Reserved and read as zero
6 WAKEUP R/W When set to 1, mutes ih_cec_stat0[6]
5 ERROR_FOLLOW R/W When set to 1, mutes ih_cec_stat0[5]
4 ERROR_INITIATOR R/W When set to 1, mutes ih_cec_stat0[4]
3 ARB_LOST R/W When set to 1, mutes ih_cec_stat0[3]
2 NACK R/W When set to 1, mutes ih_cec_stat0[2]
1 EOM R/W When set to 1, mutes ih_cec_stat0[1]
0 DONE R/W When set to 1, mutes ih_cec_stat0[0]

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5.2.2.19 ih_mute_vp_stat0
■ Name: Video Packetizer Interrupt Mute Control Register
■ Address Offset: 0x0187
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-28 ih_mute_vp_stat0 Register

Bits Name R/W Description

7 fifofullrepet R/W When set to 1, mutes ih_vp_stat0[7]
6 fifoemptyrepet R/W When set to 1, mutes ih_vp_stat0[6]
5 fifofullpp R/W When set to 1, mutes ih_vp_stat0[5]
4 fifoemptypp R/W When set to 1, mutes ih_vp_stat0[4]
3 fifofullremap R/W When set to 1, mutes ih_vp_stat0[3]
2 fifoemptyremap R/W When set to 1, mutes ih_vp_stat0[2]
1 fifofullbyp R/W When set to 1, mutes ih_vp_stat0[1]
0 fifoemptybyp R/W When set to 1, mutes ih_vp_stat0[0]

5.2.2.20 ih_mute_i2cmphy_stat0
■ Name: PHY GEN 2 I2C Master Interrupt Mute Control Register
■ Address Offset: 0x0188
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-29 ih_mute_i2cmphy_stat0 Register

Bits Name R/W Description

7:2 Reserved and read as zero

1 i2cmphydone R/W When set to 1, mutes ih_i2cmphy_stat0[1]

0 i2cmphyerror R/W When set to 1, mutes ih_i2cmphy_stat0[0]

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5.2.2.21 ih_mute_ahbdmaaud_stat0
■ Name: AHB Audio DMA Interrupt Mute Control Register
■ Address Offset: 0x0189
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-30 Register ih_mute_ahbdmaaud_stat0

Bits Name R/W Description

7 Reserved and read as zero

6 ahbdmaaud_intbuffoverrun R/W When set to 1, mutes ih_ahbdmaaud_stat0[6]

5 ahbdmaaud_interror R/W When set to 1, mutes ih_ahbdmaaud_stat0[5]

4 ahbdmaaud_intlostownership R/W When set to 1, mutes ih_ahbdmaaud_stat0[4]

3 ahbdmaaud_intretrysplit R/W When set to 1, mutes ih_ahbdmaaud_stat0[3]

2 ahbdmaaud_intdone R/W When set to 1, mutes ih_ahbdmaaud_stat0[2]

1 ahbdmaaud_intbufffull R/W When set to 1, mutes ih_ahbdmaaud_stat0[1]

0 ahbdmaaud_intbuffempty R/W When set to 1, mutes ih_ahbdmaaud_stat0[0]

5.2.2.22 ih_mute
■ Name: Global Interrupt Mute Control Register
■ Address Offset: 0x01FF
■ Size: 8 bits
■ Value after Reset: 0x03
■ Access: Read/Write

Table 5-31 ih_mute Register

Bits Name R/W Description

7:2 Reserved and read as zero

1 mute_wakeup_interrupt R/W When set to 1, mutes the main interrupt output port. The sticky bit
interrupts continue with their state accessible through the configuration
bus, only the main interrupt line is muted.

0 mute_all_interrupt R/W When set to 1, mutes the main interrupt line (where all interrupts are
ORed). The sticky bit interrupts continue with their state; only the main
interrupt line is muted.

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5.2.3 Video Sampler Registers

5.2.3.1 tx_invid0
This registers contains the input video mapping code as defined in Table 2-1.
■ Name: Video Input Mapping and Internal Data Enable Configuration Register
■ Address Offset: 0x0200
■ Size: 8 bits
■ Value after Reset: 0x01
■ Access: Read/Write

Table 5-32 tx_invid0 Register

Bits Name R/W Description

7 internal_de_generator R/W Internal data enable (DE) generator enable. If data enable is not
available for the input video the user may set this bit to one to activate
the internal data enable generator.
Attention: This feature only works for input video modes that have
native repetition (such as, all CEA videos). No desired pixel repetition
can be used with this feature because these configurations only affect
the Frame Composer and not this block.
The DE Generator does not work for the following:
■ Transmission of video with CEA VIC 39
■ Transmission of 3D video using the field alternative structure

6:5 Reserved and read as zero

4:0 video_mapping R/W Color Color

Space Depth Video_Mapping

RGB 8-bit 0x01

4:4:4
10-bit 0x03

12-bit 0x05

16-bit 0x07

YCbCr 8-bit 0x09

4:4:4
10-bit 0x0B

12-bit 0X0D

16-bit 0X0F

YCbCr 8-bit 0x16

4:2:2
10-bit 0x14

12-bit 0x12

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5.2.3.2 tx_instufffing
This register enables the stuffing mechanism of the Video Sampler module in order to correctly perform
Color Space Conversion of the ITU.601 standard YCC video. In this case, when “de” is low, the output video
components gydata[15:0], rcrdata[15:0], and bcbdata[15:0] can be configured.
■ Name: Video Input Stuffing Enable Register
■ Address Offset: 0x0201
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-33 tx_instuffing Register

Bits Name R/W Description

7:3 Reserved and read as zero

2 bcbdata_stuffing R/W 0b: When the dataen signal is low, the value in the bcbdata[15:0]
output is the one sampled from the corresponding input data.
1b: When the dataen signal is low, the value in the bcbdata[15:0]
output is given by the values in register tx_bcbdta0 and tx_bcbdata1.

1 rcrdata_stuffing R/W 0b: When the dataen signal is low, the value in the rcrdata[15:0] output
is the one sampled from the corresponding input data.
1b: When the dataen signal is low, the value in the rcrdata[15:0] output
is given by the values in tx_rcrdta0 and tx_rcrdata1 registers.

0 gydata_stuffing R/W 0b: when the dataen signal is low, the value in the gydata[15:0] output
is the one sampled from the corresponding input data.
1b: When the dataen signal is low, the value in the gydata[15:0] output
is given by the values in tx_gydta0 and tx_gydata1 registers.

5.2.3.3 tx_gydata0
■ Name: Video Input GY Data Channel Stuffing Register 0
■ Address Offset: 0x0202
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-34 tx_gydata0 Register

Bits Name R/W Description

7:0 gydata[7:0] R/W This register defines the value of gydata[7:0] when tx_instuffing[0]
(gydata_stuffing) is set to 1b.

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5.2.3.4 tx_gydata1
■ Name: Video Input GY Data Channel Stuffing Register 1
■ Address Offset: 0x0203
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-35 tx_gydata1 Register

Bits Name R/W Description

7:0 gydata[15:8] R/W This register defines the value of gydata[15:8] when tx_instuffing[0]
(gydata_stuffing) is set to 1b.

5.2.3.5 tx_rcrdata0
■ Name: Video Input RCR Data Channel Stuffing Register 0
■ Address Offset: 0x0204
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-36 tx_rcrdata0 Register

Bits Name R/W Description

7:0 rcrdata[7:0] R/W This register defines the value of rcrydata[7:0] when tx_instuffing[1]
(rcrdata_stuffing) is set to 1b.

5.2.3.6 tx_rcrdata1
■ Name: Video Input RCR Data Channel Stuffing Register 1
■ Address Offset: 0x0205
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-37 tx_rcrdata1 Register

Bits Name R/W Description

7:0 rcrdata[15:8] R/W This register defines the value of rcrydata[15:8] when tx_instuffing[1]
(rcrdata_stuffing) is set to 1b.

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5.2.3.7 tx_bcbdata0
■ Name: Video Input RCB Data Channel Stuffing Register 0
■ Address Offset: 0x0206
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-38 tx_bcbdata0 Register

Bits Name R/W Description

7:0 bcbdata[7:0] R/W This register defines the value of bcbdata[7:0] when tx_instuffing[2]
(bcbdata_stuffing) is set to 1b.

5.2.3.8 tx_bcbdata1
■ Name: Video Input RCB Data Channel Stuffing Register 1
■ Address Offset: 0x0207
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-39 tx_bcbdata1 Register

Bits Name R/W Description

7:0 bcbdata[15:8] R/W This register defines the value of bcbdata[15:8] when tx_instuffing[2]
(bcbdata_stuffing) is set to 1b.

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5.2.4 Video Packetizer Registers

2 ycc422_stuffing R/W YCC 422 remap stuffing control. For horizontal blanking, the action is
stated corresponding to ycc422_stuffing:
■ 0b: YCC 422 remap block in direct mode (input blanking data goes
directly to output).
■ 1b: YCC 422 remap block in stuffing mode. When “de” goes to low,
the outputs are fixed to 0x00.

1 pp_stuffing R/W Pixel packing stuffing control. The action is stated corresponding to
pp_stuffing:
■ 0b: Pixel packing block in direct mode (input blanking data goes
directly to output).
■ 1b: Pixel packing block in stuffing mode. When “de_rep” goes to low
the outputs are fixed to 0x00.

0 pr_stuffing R/W Pixel repeater stuffing control. The action is stated corresponding to
pp_stuffing:
0b: Pixel repeater block in direct mode (input blanking data goes
directly to output).
1b: Pixel repeater block in stuffing mode. When “de” goes to low the
outputs are fixed to 0x00.

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5.2.4.4 vp_remap
This register controls YCC422 remap of the Video Packetizer. For more information about YCC422 remap
refer to HDMI 1.4b specification.
■ Name: Video Packetizer YCC422 Remapping Register
■ Address Offset: 0x0803
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-43 vp_remap Register

Bits Name R/W Description

7:2 Reserved and read as zero

1:0 ycc422_size[1:0] R/W YCC 422 remap input video size:

ycc422_size[1:0] Action
00b YCC 422 16-bit input video (8 bits per component).
01b YCC 422 20-bit input video (10 bits per component).
10b YCC 422 24-bit input video (12 bits per component).
11b Reserved. Not used.

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5.2.4.5 vp_conf
This register controls the Video Packetizer output selection, bypass select, YCC422 enable, Pixel repeater,
and pixel packing enabling.
■ Name: Video Packetizer Output, Bypass, and Enable Configuration Register
■ Address Offset: 0x0804
■ Size: 8 bits
■ Value after Reset: 0x46
■ Access: Read/Write

Table 5-44 vp_conf Register

Bits Name R/W Description

7 Reserved and read as zero

6 bypass_en R/W Bypass enable. Disabling forces bypass module to output always zeros.

5 pp_en R/W Pixel packing enable. Disabling forces bypass module to output always zeros.

4 pr_en R/W Pixel repeater enable. Disabling forces bypass module to output always zeros.

3 ycc422_en R/W YCC 422 select enable. Disabling forces bypass module to output always zeros.

2 bypass_select R/W bypass_select Action

0b Data from pixel repeater block.
1b Data from input of video packetizer block.

1:0 output_selector[1:0] R/W Video packetizer output selection

output_selector[1:0] Action
00b Data from pixel packing block
01b Data from YCC 422 remap block
10b Data from 8 bit bypass block
11b Data from 8 bit bypass block

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5.2.4.6 vp_mask
Mask register for generation of VP_INT interrupts.
■ Name: Video Packetizer Interrupt Mask Register
■ Address Offset: 0x0807
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-45 vp_mask Register

Bits Name R/W Description

7 ointfullrepet R/W Mask bit for Video packetizer pixel repeater FIFO full

6 ointemptyrepet R/W Mask bit for Video packetizer pixel repeater FIFO empty

5 ointfullpp R/W Mask bit for Video packetizer pixel packing FIFO full

4 ointemptypp R/W Mask bit for Video packetizer pixel packing FIFO empty

3 ointfullremap R/W Mask bit for Video packetizer pixel YCC 422 re-mapper FIFO full

2 ointemptyremap R/W Mask bit for Video packetizer pixel YCC 422 re-mapper FIFO empty

1 ointfullbyp R/W Mask bit for Video packetizer 8-bit bypass FIFO full

0 ointemptybyp R/W Mask bit for Video packetizer 8-bit bypass FIFO empty

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5.2.5 Frame Composer Registers

5.2.5.1 fc_invidconf
This register configures the Interlaced/Progressive, Vblank variation and polarity of all video synchronism
of the input video signal.
■ Name: Frame Composer Input Video Configuration and HDCP Keepout Register
■ Address Offset: 0x1000
■ Size: 8 bits
■ Value after Reset: 0x70
■ Access: Read/Write

Table 5-46 fc_invidconf Register

Bits Name R/W Description

7 HDCP_keepout R/W Start/stop HDCP keepout window generation

1b: Active

6 vsync_in_polarity R/W Vsync input polarity

1b: Active high
0b: Active low

5 hsync_in_polarity R/W Hsync input polarity

1b: Active high
0b: Active low

4 de_in_polarity R/W Data enable input polarity

1b: Active high
0b: Active low

3 DVI_modez R/W Active low

0b: DVI mode selected
1b: HDMI mode selected

2 Reserved and read as zero

1 r_v_blank_in_osc R/W Used for CEA861-D modes with fractional Vblank (for example, modes 5, 6, 7,
10, 11, 20, 21, and 22. For more modes, see the CEA861-D specification.
Note: Set this field to 1 for video mode 39, although there is no Vblank
oscillation.
1b: Active high

0 in_I_P R/W Input video mode:

1b: Interlaced
0b: Progressive

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5.2.5.2 fc_inhactiv0
■ Name: Frame Composer Input Video HActive Pixels Register 0
■ Address Offset: 0x1001
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-47 fc_inhactiv0 Register

Bits Name R/W Description

7:0 H_in_activ[7:0] R/W Input video Horizontal active pixel region width. Number of Horizontal active
pixels [0...8191].

5.2.5.3 fc_inhactiv1
■ Name: Frame Composer Input Video HActive Pixels Register 1
■ Address Offset: 0x1002
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-48 fc_inhactiv1 Register

Bits Name R/W Description

7:5 Reserved and read as zero

4 H_in_activ_12/ R/W Input video Horizontal active pixel region width (0 .. 8191).
reserved Dependencies:
If configuration parameter DWC_HDMI_TX_14 = True (1), then this bit field
holds bit 12. Otherwise, it is reserved and read as zero.

3:0 H_in_activ R/W Input video Horizontal active pixel region width.

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5.2.5.4 fc_inhblank0
■ Name: Frame Composer Input Video HBlank Pixels Register 0
■ Address Offset: 0x1003
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-49 fc_inhblank0 Register

Bits Name R/W Description

7:0 H_in_blank[7:0] R/W Input video Horizontal blanking pixel region width. Number of Horizontal
blanking pixels [0...4095].

5.2.5.5 fc_inhblank1
■ Name: Frame Composer Input Video HBlank Pixels Register 1
■ Address Offset: 0x1004
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-50 fc_inhblank1 Register

Bits Name R/W Description

7:5 Reserved and read as zero

4:2 H_in_blank_12/ R/W Input video Horizontal blanking pixel region width.
Reserved Dependencies:
If configuration parameter DWC_HDMI_TX_14 = True (1), then this bit field
holds bit 12. Number of Horizontal blanking pixels [0...8191]. Otherwise, this bit
is reserved and read as zero.

1:0 H_in_blank R/W Input video Horizontal blanking pixel region width.

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5.2.5.6 fc_invactiv0
■ Name: Frame Composer Input Video VActive Pixels Register 0
■ Address Offset: 0x1005
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-51 fc_invactiv0 Register

Bits Name R/W Description

7:0 V_in_activ[7:0] R/W Input video Vertical active pixel region width. Number of Vertical active lines
[0...4095].

5.2.5.7 fc_invactiv1
■ Name: Frame Composer Input Video VActive Pixels Register 1
■ Address Offset: 0x1006
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-52 fc_invactiv1 Register

Bits Name R/W Description

7:5 Reserved and read as zero

4:3 V_in_activ_12_11/ R/W Input video Vertical active pixel region width.
reserved Dependencies:
If configuration parameter DWC_HDMI_TX_14 = True (1), then this bit field
holds bits 12:11. Number of Vertical active lines [0...8191]. Otherwise, it is
reserved and read as zero.

1:0 V_in_activ R/W Input video Vertical active pixel region width.

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5.2.5.8 fc_invblank
■ Name: Frame Composer Input Video VBlank Pixels Register
■ Address Offset: 0x1007
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-53 fc_invblank Register

Bits Name R/W Description

7:0 V_in_blank[7:0] R/W Input video Vertical blanking pixel region width. Number of Vertical blanking
lines [0...255].

5.2.5.9 fc_hsyncindelay0
■ Name: Frame Composer Input Video HSync Front Porch Register 0
■ Address Offset: 0x1008
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-54 fc_hsyncindelay0 Register

Bits Name R/W Description

7:0 H_in_delay[7:0] R/W Input video Hsync active edge delay. Integer number of pixel clock cycles from
“de” non active edge of the last “de” valid period [0...4095].

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5.2.5.10 fc_hsyncindelay1
■ Name: Frame Composer Input Video HSync Front Porch Register 1
■ Address Offset: 0x1009
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-55 fc_hsyncindelay1 Register

Bits Name R/W Description

7:5 Reserved and read as zero

4:3 H_in_delay_12/ R/W Input video Hsync active edge delay.

reserved Dependencies:
If configuration parameter DWC_HDMI_TX_14 = True (1), then this bit field
holds bit 12. Integer number of pixel clock cycles from “de” non active edge of
the last “de” valid period [0...8191]. Otherwise, this field is reserved and read as
zero.

2:0 H_in_delay R/W Input video Horizontal active edge delay.

5.2.5.11 fc_hsyncinwidth0
■ Name: Frame Composer Input Video HSync Width Register 0
■ Address Offset: 0x100A
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-56 fc_hsyncinwidth0 Register

Bits Name R/W Description

7:0 H_in_width[7:0] R/W Input video Hsync active pulse width. Integer number of pixel clock cycles
[0...511].

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5.2.5.12 fc_hsyncinwidth1
■ Name: Frame Composer Input Video HSync Width Register 1
■ Address Offset: 0x100B
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-57 fc_hsyncinwidth1 Register

Bits Name R/W Description

7:2 Reserved and read as zero

1 H_in_width_9/ Input video Hsync active pulse width.

reserved Dependencies:
If configuration parameter DWC_HDMI_TX_14 = True (1), then this bit field
holds bit 9. Integer number of horizontal active pixels [0...1024]. Otherwise, this
bit field is reserved and read as zero.

0 H_in_width R/W Input video Hsync active pulse width.

5.2.5.13 fc_vsyncindelay
■ Name: Frame Composer Input Video VSync Front Porch Register
■ Address Offset: 0x100C
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-58 fc_vsyncindelay Register

Bits Name R/W Description

7:0 V_in_delay[7:0] R/W Input video Vsync active edge delay. Integer number of Hsync pulses from “de”
non active edge of the last “de” valid period. [0...255].

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5.2.5.14 fc_vsyncinwidth
■ Name: Frame Composer Input Video VSync Width Register
■ Address Offset: 0x100D
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-59 fc_vsyncinwidth Register

Bits Name R/W Description

7:6 Reserved and read as zero

5:0 V_in_width[5:0] R/W Input video Vsync active pulse width: Integer number of lines [0...63].

5.2.5.15 fc_infreq0
■ Name: Frame Composer Input Video Refresh Rate Register 0
■ Address Offset: 0x100E
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-60 fc_infreq0 Register

Bits Name R/W Description

7:0 infreq[7:0] R/W Video refresh rate in Hz*1E3 format. This registers are provided for debug and
informative purposes. No data is written to this registers by the DWC_hdmi_tx
and the data here written by software is not used in any way by the
DWC_hdmi_tx.

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5.2.5.16 fc_infreq1
■ Name: Frame Composer Input Video Refresh Rate Register 1
■ Address Offset: 0x100F
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-61 fc_infreq1 Register

Bits Name R/W Description

7:0 infreq[15:8] R/W Video refresh rate in Hz*1E3 format. This registers are provided for debug and
informative purposes. No data is written to this registers by the DWC_hdmi_tx
and the data here written by software is not used in any way by the
DWC_hdmi_tx.

5.2.5.17 fc_infreq2
■ Name: Frame Composer Input Video Refresh Rate Register 2
■ Address Offset: 0x1010
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-62 fc_infreq2 Register

Bits Name R/W Description

7:4 Reserved and read as zero

3:0 infreq[19:16] R/W Video refresh rate in Hz*1E3 format. This registers are provided for debug and
informative purposes. No data is written to this registers by the DWC_hdmi_tx
and the data here written by software is not used in any way by the
DWC_hdmi_tx.

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7:0 exctrlperiodspacing R/W Configuration of the maximum spacing between consecutive extended control
periods (max of 50msec, refer to HDMI 1.4b specification):
generated spacing = (1/freq tmds clock)*256*256*extctrlperiodspacing

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5.2.5.21 fc_ch0pream
■ Name: Frame Composer Channel 0 Non-Preamble Data Register
■ Address Offset: 0x1014
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-66 fc_ch0pream Register

Bits Name R/W Description

7:0 ch0_preamble_filter R/W When in control mode, configures 8-bits that are going to fill the channel 0 data
lines not used to transmit the preamble (for more clarifications refer to HDMI
1.4b specification).

5.2.5.22 fc_ch1pream
■ Name: Frame Composer Channel 1 Non-Preamble Data Register
■ Address Offset: 0x1015
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-67 fc_ch1pream Register

Bits Name R/W Description

7:6 Reserved and read as zero

5:0 ch1_preamble_filter R/W When in control mode, configures 6-bits that are going to fill the channel 1 data
lines not used to transmit the preamble (for more clarifications refer to HDMI
1.4b specification).

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5.2.5.23 fc_ch2pream
■ Name: Frame Composer Channel 2 Non-Preamble Data Register
■ Address Offset: 0x1016
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-68 fc_ch2pream Register

Bits Name R/W Description

7:6 Reserved and read as zero

5:0 ch2_preamble_filter R/W When in control mode, configures 6-bits that are going to fill the channel 2 data
lines not used to transmit the preamble (for more clarifications, refer to HDMI
1.4b specification).

5.2.5.24 fc_aviconf3
■ Name: Frame Composer AVI Configuration Register 3
■ Address Offset: 0x1017
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
This register exists only when DWC_HDMI_TX_14 = True (1).

Table 5-69 fc_aviconf3 Register

Bits Name R/W Description

7:4 Reserved and read as zero

3:2 YQ R/W Quantization range according to the CEA specification.

1:0 CN R/W IT content type according to the CEA specification

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5.2.5.25 fc_gcp
Configures the General Control Packet A/V mute indicators and the default phase.
■ Name: Frame Composer GCP Packet Configuration Register
■ Address Offset: 0x1018
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-70 fc_gcp Register

Bits Name R/W Description

7:3 Reserved and read as zero

2 default_phase R/W Value of “default_phase” in the GCP packet. This data should be equal to the
default phase used at Video packetizer packing machine.
Value after Reset: 0b

1 set_avmute R/W Value of “set_avmute” in the GCP packet.

Value after Reset: 0b
Once the AVmute is set, the frame composer schedules the GCP packet with
AVmute set in the packet scheduler to be sent once (may only be transmitted
between the active edge of VSYNC and 384 pixels following this edge).

0 clear_avmute R/W Value of “clear_avmute” in the GCP packet.

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5.2.5.26 fc_aviconf0–fc_aviconf2
Configure the following contents of the AVI infoFrame:
■ RGB/YCC indication
■ Bar information
■ Scan information
■ Active format present
■ Progressive/Interlaced indicator
■ Active aspect ratio
■ Picture aspect ratio
■ Colorimetry
■ IT content
■ Extended colorimetry
■ Quantization range
■ Non-uniform picture scaling
For more information, refer to HDMI 1.4b and CEA - 861D specifications.

5.2.5.26.1 fc_aviconf0
❑ Name: Frame Composer AVI Packet Configuration Register 0
❑ Address Offset: 0x1019
❑ Size: 8 bits
❑ Value after Reset: 0x00
❑ Access: Read/Write

Table 5-71 fc_aviconf0 Register

Bits Name R/W Description

7 Reserved and read as zero

6 active_format_present R/W Active format present

5:4 scan_information R/W Scan information

3:2 bar_information R/W Active aspect ratio

1:0 rgc_ycc_indication R/W Active aspect ratio

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5.2.5.26.2 fc_aviconf1
❑ Name: Frame Composer AVI Packet Configuration Register 1
❑ Address Offset: 101A
❑ Size: 8 bits
❑ Value after Reset: 0x00
❑ Access: Read/Write

Table 5-72 fc_aviconf1 Register

Bits Name R/W Description

7:6 Colorimetry R/W Colorimetry

5:4 picture_aspect_ratio R/W Picture aspect ratio

3:0 active_aspect_ratio R/W Active aspect ratio

5.2.5.26.3 fc_aviconf2
❑ Name: Frame Composer AVI Packet Configuration Register 2
❑ Address Offset: 0x101B
❑ Size: 8 bits
❑ Value after Reset: 0x00
❑ Access: Read/Write

Table 5-73 fc_aviconf2 Register

Bits Name R/W Description

7 it_content R/W IT content

6:4 extended_colorimetry R/W Extended colorimetry

7:6 Reserved and read as zero

5:4 SS R/W Sampling size

3 Reserved and read as zero

2:0 SF R/W Sampling frequency

5.2.5.37.2 fc_audiconf2
❑ Name: Frame Composer AUD Packet Configuration Register 2
❑ Address Offset: 0x1027
❑ Size: 8 bits
❑ Value after Reset: 0x00
❑ Access: Read/Write

Table 5-85 fc_audiconf2 Register

Bits Name R/W Description

7:0 CA R/W Channel allocation

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5.2.5.37.3 fc_audiconf3
❑ Name: Frame Composer AUD Packet Configuration Register 3
❑ Address Offset: 0x1028
❑ Size: 8 bits
❑ Value after Reset: 0x00
❑ Access: Read/Write
For the FC_AUDICONF3 register, bits [6:5] correspond to LFEPBL1, LFEPBL0 LFE playback level as
compared to the other channels (from HDMI 1.4b Specification).

Table 5-86 fc_audiconf3 Registers

Bits Name R/W Description

7 Reserved and read as 0

6:5 LFEPBL/reserved R/W LFE playback information

Dependencies: Exists only when DWC_HDMI_TX_14 = True (1)

4 DM_INH Down mix enable

3:0 LSv Level shift value (for down mixing)

5.2.5.38 fc_vsdieeeid2
■ Name: Frame Composer VSI packet Data IEEE Register 2
■ Address Offset: 0x1029
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-87 fc_vsdieeeid2 Registers

Bits Name R/W Description

7:0 IEEE R/W This register configures the Vendor Specific infoFrame IEEE registration
identifier. For more information, refer to CEA-861D specification.

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5.2.5.39 fc_vsdsize
■ Name: Frame Composer VSI Packet Data Size Register
■ Address Offset: 0x102A
■ Size: 8 bits
■ Value after Reset: 0x1B
■ Access: Read/Write
This register exists only when DWC_HDMI_TX_14 = True (1).

Table 5-88 fc_vsdsize Register

Bits Name R/W Description

7:5 Reserved and read as zero

4:0 VSDSIZE R/W Packet size as described in HDMI Vendor Specific InfoFrame (from HDMI
specification).

5.2.5.40 fc_vsdieeeid1
This register configures the Vendor Specific infoFrame IEEE registration identifier. For more information,
refer to CEA-861D specification.
■ Name: Frame Composer VSI Packet Data IEEE Register 1
■ Address Offset: 0x1030
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-89 fc_vsdieeeid1 Register

Bits Name R/W Description

7:0 IEEE R/W This register configures the Vendor Specific infoFrame IEEE registration
identifier. For more information, refer to CEA-861D specification.

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5.2.5.41 fc_vsdieeeid0
This register configures the Vendor Specific infoFrame IEEE registration identifier. For more information,
refer to CEA-861D specification.
■ Name: Frame Composer VSI Packet Data IEEE Register 0
■ Address Offset: 0x1031
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-90 fc_vsdieeeid0 Register

Bits Name R/W Description

7:0 IEEE R/W This register configures the Vendor Specific infoFrame IEEE registration
identifier. For more information, refer to CEA-861D specification.

5.2.5.42 fc_vsdpayload0 – fc_vsdpayload23

These registers configure the Vendor Specific infoFrame 24 bytes specific payload. For more information,
refer to CEA-861D specification.
■ Name: Frame Composer VSI Packet Payload Register 0 to Frame Composer VSI Packet Payload
Register 23
■ Address Offset: 0x1032 to 0x1049
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-91 fc_vsdpayloadn Registers

Bits Name R/W Description

7:0 fc_vsdpayloadn R/W Frame Composer VSI packet Data Payload Register n, where n is 0 to 23.
where n is 0 to 23

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5.2.5.43 fc_spdvendorname0 – fc_spdvendorname7

These registers configure the Source Product Descriptor infoFrame 8 bytes Vendor name. For more
information, refer to CEA-861D specification.
■ Name: Frame Composer SPD Packet Data Vendor Name Register 0 to Frame Composer SPD Packet
Data Vendor Name Register 7
■ Address Offset: 0x104A to 0x1051
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-92 fc_spdvendornamen Registers

Bits Name R/W Description

7:0 fc_spdvendornamen R/W Frame Composer SPD packet Data Vendor Name Register n, where n is
where n is 0 to 7 0 to 7.

5.2.5.44 fc_spdproductname0 – fc_spdproductname15

These registers configure the Source Product Descriptor infoFrame 16 bytes Product name. For more
information, refer to CEA-861D specification.
■ Name: Frame Composer SPD Packet Data Product Name Register 0 to Frame Composer SPD Packet
Data Product Name Register 15
■ Address Offset: 0x1052 to 0x1061
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-93 fc_spdproductnamen Registers

Bits Name R/W Description

7:0 fc_spdproductnamen R/W Frame Composer SPD packet Data Product Name Register n, where n is
where n is 0 to 15 0 to 15.

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5.2.5.45 fc_spddeviceinf
This register configures Source Product Descriptor infoFrame description device field. For more
information, refer to CEA-861D specification.
■ Name: Frame Composer SPD Packet Data Source Product Descriptor Register
■ Address Offset: 0x1062
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-94 fc_spddeviceinf Registers

Bits Name R/W Description

7:0 fc_spddeviceinf R/W Frame Composer SPD packet Data Source Product Descriptor Register

5.2.5.46 fc_audsconf
Configures the Audio sample packet sample flat and layout configuration. For more information, refer to
HDMI 1.4b specification.
■ Name: Frame Composer Audio Sample Flat and Layout Configuration Register
■ Address Offset: 0x1063
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-95 fc_audsconf Register

Bits Name R/W Description

7:4 aud_packet_sampfit[3:0] R/W Set the audio packet sample flat value to be sent on the packet.

3:1 Reserved and read as zero.

0 aud_packet_layout R/W Set the audio packet layout to be sent in the packet:
1b: layout 1
0b: layout 0

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5.2.5.47 fc_audsstat
Shows the data sample present indication of the last Audio sample packet sent by the HDMI TX Controller.
For more information, refer to HDMI 1.4b specification.
■ Name: Frame Composer Audio Packet Sample Present Status Register
■ Address Offset: 0x1064
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read

Table 5-96 fc_audsstat Register

Bits Name R/W Description

7:4 Reserved and read as zero.

3:0 packet_sampprs[3:0] R Shows the data sample present indication of the last Audio sample
packet sent by the HDMI TX Controller. This register information is at
TMDS clock rate.

5.2.5.48 fc_audsv
When transmitting IEC60958 linear PCM audio, this register allows to set the value of for the Validity bit of
each of the transmitted channels. For the moment this configuration is only used when the I2S audio
interface, General Purpose Audio (GPA) interface or AHB audio DMA (AHBAUDDMA) is active.
■ Name: Frame Composer Audio Sample Validity Flag Register
■ Address Offset: 0x1065
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-97 fc_audsv Register

Bits Name R/W Description

7 V3r R/W Set validity bit “V” for Channel 3, Right
6 V2r R/W Set validity bit “V” for Channel 2, Right
5 V1r R/W Set validity bit “V” for Channel 1, Right
4 V0r R/W Set validity bit “V” for Channel 0, Right
3 V3l R/W Set validity bit “V” for Channel 3, Left
2 V2l R/W Set validity bit “V” for Channel 2, Left
1 V1l R/W Set validity bit “V” for Channel 1, Left
0 V0l R/W Set validity bit “V” for Channel 0, Left

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5.2.5.49 fc_audsu
When transmitting IEC60958 linear PCM audio, this register allows to set the value of for the User bit of
each of the transmitted channels. For the moment this configuration is only used when the I2S audio
interface, General Purpose Audio (GPA) interface, or AHB audio DMA (AHBAUDDMA) is active.
■ Name: Frame Composer Audio Sample User Flag Register
■ Address Offset: 0x1066
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-98 fc_audsu Register

Bits Name R/W Description

7 U3r R/W Set validity bit “U” for Channel 3, Right
6 U2r R/W Set validity bit “U” for Channel 2, Right
5 U1r R/W Set validity bit “U” for Channel 1, Right
4 U0r R/W Set validity bit “U” for Channel 0, Right
3 U3l R/W Set validity bit “U” for Channel 3, Left
2 U2l R/W Set validity bit “U” for Channel 2, Left
1 U1l R/W Set validity bit “U” for Channel 1, Left
0 U0l R/W Set validity bit “U” for Channel 0, Left

5.2.5.50 fc_audschnls0 to fc_audschnls8

When transmitting IEC60958 linear PCM audio, this registers allow to configure the channel status
information of all the channel status bits in the IEC60958 frame. For the moment this configuration is only
used when the I2S audio interface, General Purpose Audio (GPA), or AHB audio DMA (AHBAUDDMA)
interface is active (for S/PDIF interface this information comes from the stream). Information configured is
the following:
■ IEC Copyright indication
■ CGMS-A
■ PCM audio mode
■ Category code
■ Source number
■ Channel number for first right sample
■ Channel number for second right sample
■ Channel number for third right sample
■ Channel number for fourth right sample
■ Channel number for first left sample
■ Channel number for second left sample

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■ Channel number for third left sample

■ Channel number for fourth left sample
■ Clock accuracy
■ Sampling frequency
■ Original sampling frequency
■ Word length configuration
For more information, refer to IEC60958-3 specification.
■ Name: Frame Composer Audio Sample Channel Status Configuration Register 0 to Frame Composer
Audio Sample Channel Status Configuration Register 8
■ Address Offset: 0x1067 to 0x106F
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-99 fc_audschnls0

Bits Name R/W

7:6 reserved and read as zeros

5:4 oiec_cgmsa R/W CGMS-A

3:1 reserved and read as zeros

0 oiec_copyright R/W IEC Copyright indication

Table 5-100 fc_audschnls1

Bits Name R/W Description

7:0 oiec_categorycode R/W Category code

Table 5-101 fc_audschnls2

Bits Name R/W Description

7 Reserved and read as 0
6:4 oiec_pcmaudiomode R/W PCM audio mode
3:0 oiec_sourcenumber R/W Source number

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Table 5-102 fc_audschnls3

Bits Name R/W Description

7:4 oiec_channelnumcr1 R/W Channel number for second right sample
3:0 oiec_channelnumcr0 R/W Channel number for first right sample

Table 5-103 fc_audschnls4

Bits Name R/W Description

7:4 oiec_channelnumcr3 R/W Channel number for fourth right sample
3:0 oiec_channelnumcr2 R/W Channel number for third right sample

Table 5-104 fc_audschnls5

Bits Name R/W Description

7:4 oiec_channelnumcr1 R/W Channel number for second left sample

3:0 oiec_channelnumcr0 R/W Channel number for first left sample

Table 5-105 fc_audschnls6

Bits Name R/W Description

7:4 oiec_channelnumcl3 R/W Channel number for fourth left sample

3:0 oiec_channelnumcl2 R/W Channel number for third left sample

Table 5-106 fc_audschnls7

Bits Name R/W Description

7:6 Reserved and read as zero

5:4 oiec_clkaccuracy R/W Clock accuracy

3:0 oiec_sampfreq R/W Sampling frequency

Table 5-107 fc_audschnls8

Bits Name R/W Description

7:4 oiec_origsampfreq R/W Original sampling frequency

3:0 oiec_wordlength R/W Word length configuration

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5.2.5.51 fc_ctrlqhigh
■ Name: Frame Composer Number of High Priority Packets Attended Configuration Register
■ Address Offset: 0x1073
■ Size: 8 bits
■ Value after Reset: 0x0F
■ Access: Read/Write

Table 5-108 fc_ctrlqhigh Register

Bits Name R/W Description

7:5 Reserved and read as zero

4:0 onhighattended[4:0] R/W Configures the number of high priority packets or audio sample packets
consecutively attended before checking low priority queue status.
Integer number [0..31]

5.2.5.52 fc_ctrlqlow
■ Name: Frame Composer Number of Low Priority Packets Attended Configuration Register
■ Address Offset: 0x1074
■ Size: 8 bits
■ Value after Reset: 0x03
■ Access: Read/Write

Table 5-109 fc_ctrlqlow Register

Bits Name R/W Description

7:5 Reserved and read as zero

4:0 onlowattended[4:0] R/W Configures the number of low priority packets or null packets consecutively
attended before checking high priority queue status or audio sample
availability.

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5.2.5.53 fc_acp0
Configures the following contents of the ACP packet. For more information, refer to the HDMI 1.4
specification.
■ Name: Frame Composer ACP Packet Type Configuration Register 0
■ Address Offset: 0x1075
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-110 fc_acp0 Register

Bits Name R/W Description

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5.2.5.57 fc_iscr2_15 to fc_iscr2_0

Configures the ISRC2 packet body of the ISRC2 packet.
■ Name: Frame Composer ISCR2 Packet Body Register 15 to Frame Composer ISCR2 Packet Body
Register 0
■ Address Offset: 0x10B2 to 0x10A3
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
For more information, refer to the HDMI 1.4 specification.

Table 5-114 fc_iscr2n Register

Bits Name R/W Description

7:0 fc_iscr2n, where n is 15 to 0 R/W Frame Composer ISRC2 packet body Register n, where n is 15 to 0

5.2.5.58 fc_datauto0
Configures the Frame Composer RDRB(1)/Manual(0) data island packet insertion for SPD, VSD, ISRC2,
ISRC1 and ACP packets. On RDRB mode the described packet scheduling is controlled by registers
FC_DATAUTO1 and FC_DATAUTO2, while in Manual mode register FC_DATMAN requests to FC the
insertion of the requested packet.
■ Name: Frame Composer Data Island Auto Packet Scheduling Register 0
■ Address Offset: 0x10B3
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-115 fc_datauto0 Register

Bits Name R/W Description

7:5 Reserved and read as zero

4 spd_auto R/W Enables SPD automatic packet scheduling

3 vsd_auto R/W Enables VSD automatic packet scheduling

2 iscr2_auto R/W Enables ISRC2 automatic packet scheduling

1 iscr1_auto R/W Enables ISRC1 automatic packet scheduling

0 acp_auto R/W Enables ACP automatic packet scheduling

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5.2.5.59 fc_datauto1
Configures the Frame Composer (FC) RDRB frame interpolation for SPD, VSD, ISRC2, ISRC1 and ACP
packet insertion on data island when FC is on RDRB mode for the listed packets.
■ Name: Frame Composer Data Island Auto Packet Scheduling Register 1
■ Address Offset: 0x10B4
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-116 fc_datauto1 Register

Bits Name R/W Description

7:4 Reserved and read as zero

3:0 auto frame interpolation R/W Packet frame interpolation, for automatic packet scheduling

5.2.5.60 fc_datauto2
Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for SPD,
VSD, ISRC2, ISRC1 and ACP packet insertion on data island when FC is on RDRB mode for the listed
packets.
■ Name: Frame Composer Data Island Auto Packet Scheduling Register 2
■ Address Offset: 0x10B5
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-117 fc_datauto2 Register

Bits Name R/W Description

7:4 auto frame packets R/W Packets per frame, for automatic packet scheduling

3:0 auto line spacing R/W Packets line spacing, for automatic packet scheduling

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5.2.5.61 fc_datman
Requests to the Frame Composer the data island packet insertion for NULL, SPD, VSD, ISRC2, ISRC1 and
ACP packets when FC_DATAUTO0 bit is in manual mode for the packet requested.
■ Name: Frame Composer Data Island Manual Packet Request Register
■ Address Offset: 0x10B6
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Write

Table 5-118 fc_datman Register

Bits Name R/W Description

7:6 Reserved and read as zero

5 null_tx W Null packet

4 spd_tx W SPD packet

3 vsd_tx W VSD packet

2 iscr2_tx W ISRC2 packet

1 isr1_tx W ISRC1 packet

0 acp_tx W ACP packet

5.2.5.62 fc_datauto3
Configures the Frame Composer Automatic(1)/RDRB(0) data island packet insertion for AVI, GCP, AUDI
and ACR packets. In Automatic mode, the packet is inserted on Vblanking when first line with active Vsync
appears.
■ Name: Frame Composer Data Island Auto Packet Scheduling Register 3
■ Address Offset: 0x10B7
■ Size: 8 bits
■ Value after Reset: 0x0F
■ Access: Read/Write

Table 5-119 fc_datauto3 Register

Bits Name R/W Description

7:4 Reserved and read as zero

3 avi_auto R/W Enable AVI packet insertion

2 gcp_auto R/W Enable GCP packet insertion

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Table 5-119 fc_datauto3 Register (Continued)

Bits Name R/W Description

1 audi_auto R/W Enable AUDI packet insertion

0 acr_auto R/W Enable ACR packet insertion

Table 5-127 fc_rdrb7 Register

Bits Name R/W Description

7:4 AVIpacketsinframe R/W AVI packets per frame
3:0 AVIpacketlinespacing R/W AVI packets line spacing

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5.2.5.71 fc_mask0
Mask register for generation of FC_INT0 interrupts.
■ Name: Frame Composer Packet Interrupt Mask Register 0
■ Address Offset: 0x10D2
■ Size: 8 bits
■ Value after Reset: 0x25
■ Access: Read/Write

Table 5-128 fc_mask0 Register

Bits Name R/W Description

7 AUDI R/W Mask bit for FC_INT0.AUDI interrupt bit
Value after Reset: 0b
6 ACP R/W Mask bit for FC_INT0.ACP interrupt bit
Value after Reset: 0b
5 HBR R/W Mask bit for FC_INT0.HBR interrupt bit
Value after Reset: 0b
4:3 spare R/W These bits have no associated functionality.
2 AUDS R/W Mask bit for FC_INT0.AUDS interrupt bit
Value after Reset: 0b
1 ACR R/W Mask bit for FC_INT0.ACR interrupt bit
Value after Reset: 0b
0 NULL R/W Mask bit for FC_INT0.NULL interrupt bit
Value after Reset: 0b

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5.2.5.72 fc_mask1
Mask register for generation of FC_INT1 interrupts.
■ Name: Frame Composer Packet Interrupt Mask Register 1
■ Address Offset: 0x10D6
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-129 FC_MASK1 Register

Bits Name R/W Description

7 GMD R/W Mask bit for FC_INT1.GMD interrupt bit

6 ISCR1 R/W Mask bit for FC_INT1.ISRC1 interrupt bit

5 ISCR2 R/W Mask bit for FC_INT1.ISRC2 interrupt bit

4 VSD R/W Mask bit for FC_INT1.VSD interrupt bit

3 SPD R/W Mask bit for FC_INT1.SPD interrupt bit

2 spare R/W This bit has no associated functionality.

1 AVI R/W Mask bit for FC_INT1.AVI interrupt bit

0 GCP R/W Mask bit for FC_INT1.GCP interrupt bit

5.2.5.73 fc_mask2
Mask register for generation of FC_INT2 interrupts.
■ Name: Frame Composer High/Low Priority Overflow Interrupt Mask Register 2
■ Address Offset: 0x10DA
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-130 fc_mask2 Register

Bits Name R/W Description

7:2 Reserved and read as zero.

1 LowPriority_overflow R/W Mask bit for fc_int1.LowPriority_overflow interrupt bit

Value after Reset: 0b

0 HighPriority_overflow R/W Mask bit for fc_int1.HighPriority_overflow interrupt bit

Value after Reset: 0b

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5.2.5.74 fc_prconf
Defines the Pixel Repetition ratio factor of the input and output video signal.
■ Name: Frame Composer Pixel Repetition Configuration Register
■ Address Offset: 0x10E0
■ Size: 8 bits
■ Value after Reset: 0x10
■ Access: Read/Write

Table 5-131 fc_prconf Register

Bits Name R/W Description

7:4 incoming_pr_factor[3:0] R/W Configures the input video pixel repetition. A plus 1 factor should be
added in this register configuration. For CEA modes this value should be
extracted from the CEA spec for the video mode being inputted.

incoming_pr_factor[3:0] Action
0000b No action. Not used.
0001b No pixel repetition (pixel sent only once)
0010b Pixel sent 2 times (pixel repeated once)
0011b Pixel sent 3 times
0100b Pixel sent 4 times
0101b Pixel sent 5 times
0110b Pixel sent 6 times
0111b Pixel sent 7 times
1000b Pixel sent 8 times
1001b Pixel sent 9 times
1010b Pixel sent 10 times
Other Reserved. Not used.

Note: When working in YCC422 video the actual repetition of the stream
is Incoming_pr_factor * (desired_pr_factor + 1). This calculation is done
internally in the H13TCTRL and no HW overflow protection is available.
Care must be taken to avoid this result passes the maximum number of 10
pixels repeated since no HDMI support is available for this in the
specification and the H13TPHY does not support this higher repetition
values.

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Table 5-131 fc_prconf Register (Continued)

Bits Name R/W Description

3:0 output_pr_factor[3:0] R/W Configures the video pixel repetition ratio to be sent on the AVI infoFrame.
This value must be valid according to HDMI spec. The output_pr_factor =
incoming_pr_factor(without the + 1 factor) * desired_pr_factor.

incoming_pr_factor[3:0] Action
0000b No action. Not used.
0001b Pixel sent 2 times (pixel repeated once)
0010b Pixel sent 3 times
0011b Pixel sent 4 times
0100b Pixel sent 5 times
0101b Pixel sent 6 times
0110b Pixel sent 7 times
0111b Pixel sent 8 times
1000b Pixel sent 9 times
1001b Pixel sent 10 times
Other Reserved. Not used.

5.2.5.75 fc_gmd_stat
Gamut metadata packet status bit information for no_current_gmd, next_gmd_field, gmd_packet_sequence
and current_gamut_seq_num. For more information, refer to the HDMI 1.4b specification.
■ Name: Frame Composer GMD Packet Status Register
■ Address Offset: 0x1100
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read

Table 5-132 fc_gmd_stat Register

Bits Name R/W Description

7 igmdno_crnt_gbd R Gamut scheduling: No current gamut data

6 igmddnext_field R Gamut scheduling: Gamut Next field

5:4 igmdpacket_seq[1:0] R Gamut scheduling: Gamut packet sequence

3:0 igmdcurrent_gamut_seq_num R Gamut scheduling: Current Gamut packet sequence number

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5.2.5.76 fc_gmd_en
This register enables Gamut metadata (GMD) packet transmission. Packets are inserted in the incoming
frame, starting in the line where active Vsync indication starts. After enable of GMD packets the outgoing
packet is sent with no_current_gmd active indication until update GMD request is performed in the
controller.
■ Name: Frame Composer GMD Packet Enable Register
■ Address Offset: 0x1101
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-133 fc_gmd_en Register

Bits Name R/W Description

7:1 Reserved and read as zero.

0 gmdenabletx R/W Gamut Metadata packet transmission enable (1b).

5.2.5.77 fc_gmd_up
This register performs an GMD packet content update according to the configured packet body
(FC_GMD_PB0 to FC_GMD_PB27) and packet header (FC_GMD_HB). This active high auto clear register
reflects the body and header configurations on the GMD packets sent arbitrating the
current_gamut_seq_num, gmd_packet_sequence and next_gmd_field bits on packet to correctly indicate to
source the Gamut change to be performed. After enable GMD packets the first update request is also
responsible for deactivating the no_current_gmd indication bit. Attention packet update request must only
be done after correct configuration of GMD packet body and header registers. Correct
affected_gamut_seq_num and gmd_profile configuration is user responsibility and must convey with
HDMI 1.4b standard gamut rules.
■ Name: Frame Composer GMD Packet Update Register
■ Address Offset: 0x1102
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Write

Table 5-134 fc_gmd_up Register

Bits Name R/W Description

7:1 Reserved and read as zero.

0 gmdupdatepacket W Gamut Metadata packet update.

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5.2.5.78 fc_gmd_conf
This register configures the number of GMD packets to be inserted per frame (starting always in the line
where the active Vsync appears) and the line spacing between the transmitted GMD packets. Note that for
profile P0 (refer to HDMI 1.4b spec) this register should only indicate one GMD packet to be inserted per
video field.
■ Name: Frame Composer GMD Packet Schedule Configuration Register
■ Address Offset: 0x1103
■ Size: 8 bits
■ Value after Reset: 0x10
■ Access: Read/Write

Table 5-135 fc_gmd_conf Register

Bits Name R/W Description

7:4 gmdpacketsinframe[3:0] R/W Number of GMD packets per frame or video field (profile P0)

3:0 gmdpacketlinespacing[3:0] R/W Number of line spacing between the transmitted GMD packets

5.2.5.79 fc_gmd_hb
This register configures the GMD packet header affected_gamut_seq_num and gmd_profile bits. For more
information, refer to the HDMI 1.4b specification.
■ Name: Frame Composer GMD Packet Profile and Gamut Sequence Configuration Register
■ Address Offset: 0x1104
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-136 fc_gmd_conf Register

Bits Name R/W Description

7 Reserved and read as zero.

6:4 gmdgbd_profile R/W GMD profile bits

3:0 gmdaffected_gamut_seq_num R/W Affected gamut sequence number

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5.2.5.80 fc_gmd_pb0 to fc_gmd_pb27

Configures the GMD packet body of the GMD packet.
■ Name: Frame Composer GMD Packet Body Register 0 to Frame Composer GMD Packet Body
Register 27
■ Address Offset: 0x1105 to 0x1120
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
For more information, refer to the HDMI 1.4b specification.

Table 5-137 fc_gmd_pbn Register

Bits Name R/W Description

7:0 fc_gmd_pbn, where n is 0 to 27 R/W Frame Composer GMD Packet Body Register n, where n is 0 to 27.

5.2.5.81 fc_dbgforce
This register allows to force the controller to output audio and video data the values configured in the
FC_DBGAUD and FC_DBGTMDS registers.
■ Name: Frame Composer Video/Audio Force Enable Register
■ Address Offset: 0x1200
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-138 fc_dbgforce Register

Bits Name R/W Description

7:5 Reserved and read as zero

Table 5-146 fc_dbgaudnch7 Register

Bits Name R/W Description

7:0 fc_dbgaudnch7, where n is 0 to 2 R/W Frame Composer Audio Data Channel 7 Register n, where n is 0 to 2.

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5.2.5.90 fc_dbgtmds0
Configures the video fixed data to be used in tmds channel 0 when in fixed video selection. This equals to
set B pixel component value in RGB video or Cb pixel component value in YCbCr.
■ Name: Frame Composer TMDS Channel 0 Register
■ Address Offset: 0x1219
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-147 fc_dbgtmds0 Register

Bits Name R/W Description

5.2.6.2 phy_tst0
PHY TX mapped text interface (control). For more information, refer to the DesignWare Cores HDMI TX PHY
Databook.
■ Name: PHY Test Interface Register 0
■ Address Offset: 0x3001
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-151 phy_ts0 Register

Bits Name R/W Description

7:6 spare_2 R/W Spare register with no associated functionality.
5 testclr R/W Test clear signal
Value after Reset: 0b
4 testen R/W Test enable signal
Value after Reset: 0b
3:1 spare_1 R/W Spare register with no associated functionality.
0 testclk R/W Test clock signal.
Value after Reset: 0b

Table 5-160 PHY_PLLCFGFREQ0 Register

Bits Name R/W Description

7:0 pllcfgfreq[7:0] R/W PLL Configuration Frequency (pclk_freq[7:0]). For more information, refer to PHY
databook.

5.2.6.12 PHY_PLLCFGFREQ1
This register is present when the Chartered 65 LPE PHY is selected.
■ Name: PHY Test Interface Register 1
■ Address Offset: 0x300b
■ Size: 8 bits
■ Value after Reset: 0x27
■ Access: Read/Write

Table 5-161 PHY_PLLCFGFREQ1 Register

Bits Name R/W Description

7:0 pllcfgfreq[7:0] R/W PLL Configuration Frequency (pclk_freq[15:8]). For more information, refer to PHY
databook.

5.2.6.13 PHY_PLLCFGFREQ2
This register is present when the Chartered 65 LPE PHY is selected.
■ Name: PHY Test Interface Register 2
■ Address Offset: 0x300c
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-162 PHY_PLLCFGFREQ2 Register

Bits Name R/W Description

7:0 pllcfgfreq[7:0] R/W PLL Configuration Frequency (pclk_freq[23:16]). For more information, refer to
PHY databook.

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5.2.7 I2C Master PHY Registers

5.2.7.1 phy_i2cm_slave
This register writes the slave address of the I2C Master PHY. This register is functional when PHY_GEN2=1
or PHY_EXTERNAL=1.
■ Name: PHY I2C Slave Address Configuration Register
■ Address Offset: 0x3020
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-163 phy_i2cm_slave Register

Bits Name R/W Description

7 Reserved and read as zero

6:0 slaveaddr R/W Slave address to be sent during read and write operations.
The PHY Gen2 slave address is: 7'h69
The HEAC PHY slave address is: 7'h49

5.2.7.2 phy_i2cm_address
This register writes the address for read and writer operations. This register is functional when
PHY_GEN2=1 or PHY_EXTERNAL=1.
■ Name: PHY I2C Address Configuration Register
■ Address Offset: 0x3021
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-164 phy_i2cm_address Register

Bits Name R/W Description

7:0 address R/W Register address for read and write operations.

7:0 datai[7:0] R Data MSB read from register pointed by phy_i2cm_address[7:0].

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5.2.7.6 phy_i2cm_datai_0
This register is functional when PHY_GEN2=1 or PHY_EXTERNAL=1.
■ Name: PHY I2C Data Read Register 0
■ Address Offset: 0x3025
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read

Table 5-168 phy_i2cm_datai_0 Register

Bits Name R/W Description

7:0 datai[7:0] R Data LSB read from register pointed by phy_i2cm_address[7:0].

5.2.7.7 phy_i2cm_operation
This register requests read and write operations from the I2C Master PHY. This register can only be written;
reading this register always results in 00h. Writing 1'b1 simultaneously to read and write requests is
considered a read request. This register is functional when PHY_GEN2=1 or PHY_EXTERNAL=1.
■ Name: PHY I2C Read/Write Operation Register
■ Address Offset: 0x3026
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Write

Table 5-169 phy_i2cm_operation Register

Bits Name R/W Description

7:5 Reserved and read as zero
4 wr W Write operation request
3:1 Reserved and read as zero
0 rd W Read operation request

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5.2.7.8 phy_i2cm_int
This register contains and configures I2C master PHY done interrupt. This register is functional when
PHY_GEN2=1 or PHY_EXTERNAL=1.
■ Name: PHY I2C Done Interrupt Register
■ Address Offset: 0x3027
■ Size: 8 bits
■ Value after Reset: 0x08
■ Access: Read/Write

Table 5-170 phy_i2cm_int Register

Bits Name R/W Description

5.2.7.13 phy_i2cm_ss_scl_hcnt_0_addr
This register is functional when PHY_GEN2=1 or PHY_EXTERNAL=1.0
■ Name: PHY I2C Slow Speed SCL High Level Control Register 0
■ Address Offset: 0x302C
■ Size: 8 bits
■ Value after Reset: 0x6C
■ Access: Read/Write

Table 5-175 phy_i2cm_ss_scl_hcnt_0_addr Register

Bits Name R/W Description

7:0 i2cmp_ss_scl_hcnt0 R/W PHY I2C Slow Speed SCL High Level Control Register 0
Value after Reset: 8'h6C

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5.2.7.14 phy_i2cm_ss_scl_lcnt_1_addr
This register is functional when PHY_GEN2=1 or PHY_EXTERNAL=1.
■ Name: PHY I2C Slow Speed SCL Low Level Control Register 1
■ Address Offset: 0x302D
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-176 phy_i2cm_ss_scl_lcnt_1_addr Register

Bits Name R/W Description

7:0 i2cmp_ss_scl_lcnt1 R/W PHY I2C Slow Speed SCL Low Level Control Register 1
Value after Reset: 8'h00

5.2.7.15 phy_i2cm_ss_scl_lcnt_0_addr
This register is functional when PHY_GEN2=1 or PHY_EXTERNAL=1.
■ Name: PHY I2C Slow Speed SCL Low Level Control Register 0
■ Address Offset: 0x302E
■ Size: 8 bits
■ Value after Reset: 0x7F
■ Access: Read/Write
Table 5-177 phy_i2cm_fs_scl_hcnt_0_addr Register

Bits Name R/W Description

7:0 i2cmp_ss_scl_lcnt0 R/W PHY I2C Slow Speed SCL Low Level Control Register 0
Value after Reset: 8'h7F

5.2.7.16 phy_i2cm_fs_scl_hcnt_1_addr
This register is functional when PHY_GEN2=1 or PHY_EXTERNAL=1.
■ Name: PHY I2C Fast Speed SCL High Level Control Register 1
■ Address Offset: 0x302F
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-178 phy_i2cm_fs_scl_hcnt_1_addr Register

Bits Name R/W Description

7:0 i2cmp_fs_scl_hcnt1 R/W PHY I2C Fast Speed SCL High Level Control Register 1
Value after Reset: 8'h00

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5.2.7.17 phy_i2cm_fs_scl_hcnt_0_addr
This register is functional when PHY_GEN2=1 or PHY_EXTERNAL=1.
■ Name: PHY I2C Fast Speed SCL High Level Control Register 0
■ Address Offset: 0x3030
■ Size: 8 bits
■ Value after Reset: 0x11
■ Access: Read/Write

Table 5-179 phy_i2cm_fs_scl_hcnt_0_addr Register

Bits Name R/W Description

7:0 i2cmp_fs_scl_hcnt0 R/W PHY I2C Fast Speed SCL High Level Control Register 0
Value after Reset: 8'h11

5.2.7.18 phy_i2cm_fs_scl_lcnt_1_addr
This register is functional when PHY_GEN2=1 or PHY_EXTERNAL=1.
■ Name: PHY I2C Fast Speed SCL Low Level Control Register 1
■ Address Offset: 0x3031
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-180 PHY_I2CM_FS_SCL_LCNT_1_ADDR Register

Bits Name R/W Description

7:0 i2cmp_fs_scl_lcnt1 R/W PHY I2C Fast Speed SCL Low Level Control Register 1
Value after Reset: 8'h00

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5.2.7.19 phy_i2cm_fs_scl_lcnt_0_addr
This register is functional when PHY_GEN2=1 or PHY_EXTERNAL=1.
■ Name: PHY I2C Fast Speed SCL Low Level Control Register 0
■ Address Offset: 0x3032
■ Size: 8 bits
■ Value after Reset: 0x24
■ Access: Read/Write

Table 5-181 phy_i2cm_fs_scl_lcnt_0_addr Register

Bits Name R/W Description

7:0 i2cmp_fs_scl_lcnt0 R/W PHY I2C Fast Speed SCL Low Level Control Register 0
Value after Reset: 8'h24

5.2.7.20 i2cm_phy_sda_hold
This register is functional when PHY_GEN2=1 or PHY_EXTERNAL=1.
■ Name: PHY I2C SDA Hold Register
■ Address Offset: 0x3033
■ Size: 8 bits
■ Value after Reset: 0x09
■ Access: Read/Write

Table 5-182 i2cm_phy_sda_hold Register

Bits Name R/W Description

7:0 osda_hold R/W Defines the number of SFR clock cycles to meet tHD;DAT (300 ns)
osda_hold = round_to_high_integer (300 ns / (1 / isfrclk_frequency))

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5.2.8 Audio Sampler Registers

5.2.8.1 aud_conf0
This register configures the I2S input enable that indicates which input I2S channels have valid data. It also
allows the system processor to reset audio FIFOs upon underflow/overflow error detection. This register is
present when the hardware configuration parameter AUDIO_IF = I2S (1), DOUBLE (4), or GDOUBLE (7).
■ Name: Audio I2S SW FIFO Reset, Select, and Enable Control Register 0
■ Address Offset: 0x3100
■ Size: 8 bits
■ Value after Reset: 0x2F
■ Access: Read/Write

Table 5-183 aud_conf0 Register

Bits Name R/W Description

7 sw_audio_fifo_rst R/W Audio FIFOs software reset
Writing 0b: no action taken
Writing 1b: Resets all audio FIFOs
Reading from this register always returns 0b.
Note: If a FIFO reset request (via SFR command) lands in the middle of a I2S
transaction, the samples become misaligned (left-right sequence lost). As a
solution, for each FIFO reset, an associated I2S reset must be issued (writing
8'hF7 to MC_SWRSTZ register).
Value after Reset: 0b
6 spare_2 R/W This bit has no associated functionality.
5 i2s_select R/W 1b: Selects I2S Audio Interface
0b: Selects the second (S/PDIF/GPA) interface, in configurations with more that
one audio interface (DOUBLE/GDOUBLE)
Value after Reset: 1b
4 spare_1 R/W This bit has no associated functionality.
3:0 I2S_in_en R/W Action
I2S_in_en[0] - I2Sdata[0] enable
I2S_in_en[1] - I2Sdata[1] enable
I2S_in_en[2] - I2Sdata[2] enable
I2S_in_en[3] - I2Sdata[3] enable

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5.2.8.2 aud_conf1
This register configures the I2S mode and data width of the input data. This register is present when the
hardware configuration parameter AUDIO_IF = I2S (1), DOUBLE (4), or GDOUBLE (7).
■ Name: Audio I2S Width and Mode Configuration Register 1
■ Address Offset: 0x3101
■ Size: 8 bits
■ Value after Reset: 0x18
■ Access: Read/Write

Table 5-184 aud_conf1 Register

Bits Name R/W Description

7:5 I2S_mode R/W I2S input data mode
I2S_mode[4:0] Action
000b Standard I2S mode
001b Right-justified I2S mode
010b Left-justified I2S mode
011b Burst 1 mode
100b Burst 2 mode
Value after Reset: 000b
4:0 I2S_width R/W I2S input data width
I2S_width[4:0] Action
00000b-01111b Not used
10000b 16 bit data samples at input
10001b 17 bit data samples at input
10010b 18 bit data samples at input
10011b 19 bit data samples at input
10100b 20 bit data samples at input
10101b 21 bit data samples at input
10110b 22 bit data samples at input
10111b 23 bit data samples at input
11000b 24 bit data samples at input
11001b-11111b Not used
Value after Reset: 11000b

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5.2.8.3 aud_int
This register configures the I2S FIFO status and interrupts. This register is present when the hardware
configuration parameter AUDIO_IF = I2S (1), DOUBLE (4), or GDOUBLE (7).
■ Name: Audio I2S FIFO Status and Interrupts Register 1
■ Address Offset: 0x3102
■ Size: 8 bits
■ Value after Reset: 0x03
■ Access: Read/Write

Table 5-185 aud_int Register

Bits Name R/W Description

7:4 Reserved and read as zero
3 fifo_empty_mask R/W FIFO empty mask.
2 fifo_full_mask R/W FIFO full mask.
1:0 Reserved and read as zero

5.2.8.4 aud_conf2
This register configures the I2S Audio Data mapping. This register is present when the hardware
configuration parameter AUDIO_IF = I2S (1), DOUBLE (4), or GDOUBLE (7).
By default, audio data mapping is the standard I2S Linear PCM (L-PCM) mapping. You can choose to use
the I2S interface to transport HBR or Non-Linear PCM (NL-PCM) audio, by setting the relevant bit in this
register.
■ Name: Audio I2S NL-PCM and HBR Configuration Register 2
■ Address Offset: 0x3103
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-186 AUD_CONF2

Bits Name R/W Description

7:2 Reserved
1 NLPCM R/W I2S NLPCM Mode Enable
Value after Reset: 0b
0 HBR R/W I2S HBR Mode Enable
Value after Reset: 0b

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Table 5-191 AUD_CTS1

Bits Name R/W Description

7:0 audCTS R/W HDMI Audio Clock Regenerator CTS calculated value. This value can be
manually set using the CTS_manual (AUD_CTS3) mechanism.

5.2.8.10 aud_cts2
For CTS expected values, refer to the HDMI 1.4b specification.
■ Name: Audio Clock Regenerator CTS Value Register 2
■ Address Offset: 0x3204
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-192 aud_cts2

Bits Name R/W Description

7:0 audCTS R/W HDMI Audio Clock Regenerator CTS calculated value. This value
can be manually set using the CTS_manual (AUD_CTS3)
mechanism.

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5.2.8.11 aud_cts3
For CTS expected values, refer to the HDMI 1.4b specification.
■ Name: Audio Clock Regenerator CTS Value Register 3
■ Address Offset: 0x3205
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-193 aud_cts3

Bits Name R/W Description

7:5 N_shifta R/W N_shift factor configuration:
N_shift N Shift Action
Factor
000b 1 This is the N shift factor used for the case that N' = “audN[19:0]”.
001b 16 This is the N shift factor used to calculate N' = “audN[19:0]”/(N
shift factor). For this configuration N' = “audN[19:0]”/16.
010b 32 This is the N shift factor used to calculate N' = “audN[19:0]”/(N
shift factor). For this configuration N' = “audN[19:0]”/32.
010b 64 This is the N shift factor used to calculate N' = “audN[19:0]”/(N
shift factor). For this configuration N = “audN[19:0]”/64
100b 128 This is the N shift factor used to calculate N' = “audN[19:0]”/(N
shift factor). For this configuration N' = “audN[19:0]”/128.
101b 256 This is the N shift factor used to calculate N' = “audN[19:0]”/(N
shift factor). For this configuration N' = “audN[19:0]”/256.
others 128 This is the N shift factor used to calculate N' = “audN[19:0]”/(N
shift factor). For this configuration N' = “audN[19:0]”/128.
4 CTS_manuala R/W If “CTS_manual” bit equals 0b this registers contains “audCTS[19:0]” generated by
the Cycle time counter according to specified timing. If “CTS_manual” bit equals 1b
this register should be configured with the “audCTS[7:0]” value that should be
outputted by the Audio Packetizer.
3:0 AudCTS R/W HDMI Audio Clock Regenerator CTS calculated value. This value can be manually
set using the CTS_manual (AUD_CTS3) mechanism.

a. When the General Parallel Audio Interface (GPAUD) is enabled (AUDIO_IF = 6) or the AHB DMA Audio Interface is
enabled (AUDIO_IF = 8), writing to these bits has no effect; reading these bits always return 0.

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5.2.8.12 aud_inputclkfs
Input audio clock FS factor.

When the General Parallel Audio Interface (GPAUD) is enabled (AUDIO_IF = 6), this register
Note has no meaning. Writing and reading to this register is possible but no functional action is
performed.

■ Name: Audio Input Clock FS Factor

■ Address Offset: 0x3206
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-194 aud_inputclkfs

Bits Name R/W Description

7:3 Reserved and read as zero
2:0 Ifsfactor R/W Fs factor configuration:
Audio
Ifsfactor[2:0] Clock Action
0 128xFs If you select the Bypass S/PDIF DRU unit in coreConsultant,
the input audio clock (either I2S or S/PDIF according to
configuration) is used at the audio packetizer to calculate the
CTS value and ACR packet insertion rate.
1 256xFs The input audio clock (I2S only) is divided by 2 and then used
at audio packetizer to calculate the CTS value and ACR packet
insertion rate.
2 512xFs The input audio clock (either I2S or S/PDIF according to
configuration) used divided by 4 and then used at the audio
packetizer to calculate the CTS value and ACR packet insertion
rate.
Note: When the S/PDIF interface is receiving an HBR audio
stream (HBR_ON_SPDIF parameter must be enabled), it is
required that the selected IFSFACTOR to be set at 512xFs in
order to comply with the HDMI ACR requirements for HBR
audio streams.
3 1024xF s The input audio clock (I2S only) is divided by 8 and then used
at the audio packetizer to calculate the CTS value and ACR
packet insertion rate.
4 64xFs The input audio clock (I2S only) is multiplied by 2 and then
used at the audio packetizer to calculate the CTS value and
ACR packet insertion rate.

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7:4 Reserved and read as zero
3 spdif_fifo_empty_mask R/W S/PDIF FIFO empty mask
2 spdif_fifo_full_mask R/W S/PDIF FIFO full mask
1:0 Reserved and read as zero

5.2.8.16 aud_spdifint1
This register masks interrupts present in the S/PDIF module. This is only present when the AUDIO_IF is set
to SPDIF (2) or DOUBLEIF (4).
■ Name: Audio S/PDIF Mask Interrupt Register 1
■ Address Offset: 0x3303
■ Size: 8 bits
■ Value after Reset: 0x10
■ Access: Read/Write

Table 5-198 aud_spdifint1 Register

Bits Name R/W Description

7:5 Reserved and read as zero
4 fifo_overrun_mask R/W FIFO overrun mask
3:0 Reserved and read as zero

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5.2.9 Generic Parallel Audio Interface Registers

This section includes descriptions for the GPAUD interface registers.

5.2.9.1 gp_conf0
This register is present when AUDIO_IF = GPAUD (6) or GDOUBLE (7).
■ Name: Audio GPA SW FIFO Reset Control Register 0
■ Address Offset: 0x3500
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-199 gp_conf0

Bits Name R/W Description

7:1 Reserved and read as zero
0 sw_audio_fifo_rst R/W Audio FIFOs software reset
Writing 0b: no action taken
Writing 1b: Resets all audio FIFOs
Reading from this register always returns 0b.
Note: If a FIFO reset request (via register write command) lands in the middle
of an GPAUD audio transaction, the samples becomes misaligned (left-right
sequence lost).
As a solution, for each FIFO reset, an associated S/PDIF reset must be issued
(writing 8'h7F to MC_SWRSTZ register).

5.2.9.2 gp_conf1
This register is present when AUDIO_IF = GPAUD (6) or GDOUBLE (7).
■ Name: Audio GPA Channel Enable Configuration Register 1
■ Address Offset: 0x3501
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-200 gp_conf1

Bits Name R/W Description

7:0 ch_in_en R/W Each bit controls the enabling of the respective audio channel. For
instance bit 1, when set (1'b1) the audio Channel 1 is enabled. When
cleared, the referred channel is disabled.

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5.2.9.3 gp_conf2
This register is present when AUDIO_IF = GPAUD (6) or GDOUBLE (7).
■ Name: Audio GPA HBR Enable Register 2
■ Address Offset: 0x3502
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-201 gp_conf2

Bits Name R/W Description

7:1 Reserved and read as zero
1 insert_pcuv R/W When set (1'b1), it enables the insertion of the PCUV (Parity, Channel Status, User
bit and Validity) bits on the incoming audio stream (support limited to Linear PCM
audio).
If disabled, the incomming audio stream must contain the PCUV bits, mapped
acording to 2.6.4.2 Data Mapping Examples
0 HBR R/W HBR packets enable. The DWC_hdmi_tx sends the HBR packets. This bit is
enabled when the audio frequency is higher than 192kHz.If this bit is enabled, the
number of channels configured in gp_conf1 is always 8.

5.2.9.4 gp_mask
This register is present when AUDIO_IF = GPAUD (6) or GDOUBLE (7).
■ Name: Audio GPA Full and Empty Mask Interrupt Register
■ Address Offset: 0x3506
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-202 gp_mask

Bits Name R/W Description

7:5 Reserved and read as zero
4 fifo_overrun_mask R/W FIFO overrun mask
3 Reserved and read as zero
1 fifo_empty_mask R/W FIFO empty flag mask
0 fifo_full_mask R/W FIFO full flag mask

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5.2.10 Audio DMA Registers

The AHB audio DMA is configured by programming the registers described in the following tables. These
registers are only present when the the AUDIO_IF is set to AHBAUDDMA (8).

5.2.10.1 ahb_dma_conf0
This register contains the software reset bit for the audio FIFOs. It also configures operating modes of the
AHB master. This register is only present when the the AUDIO_IF is set to AHBAUDDMA (8).
■ Name: Audio DMA Software FIFO Reset and DMA Configuration Register 0
■ Address Offset: 0x3600
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-203 ahb_dma_conf0

Bits Name R/W Description

7 sw_fifo_rst R/W This is the software reset bit for the audio and FIFOs clear.
■ Writing 0‘b does not result in any action.
■ Writing 1‘b to this register resets all audio FIFOs.
■ Reading from this register always returns 0‘b.
6 insert_pcuv R/W Enables the insertion of PCUV data
5 Reserved and read as zero
4 hbr R/W HBR packets enable.
The DWC_hdmi_tx sends the HBR packets. This bit must be enabled when
transmitting non-linear audio of frequency higher than 192 kHz. If this bit is
enabled, the number of channels configured in ahb_dma_conf1 is always 8.
3 enable_hlock R/W Enable request of locked burst AHB mechanism.
1‘b: Enables the usage of hlock for master request to arbiter of a locked
complete burst.
0‘b: Disables request of locked burst AHB mechanism
2:1 incr_type R/W Selects the preferred burst length size
00‘b: Corresponds to INCR4 fixed four beat incremental AHB burst mode. Only
valid when burst_mode is high.
01‘b: Corresponds to INCR8 fixed eight beat incremental AHB burst mode.
Only valid when burst_mode is high.
10‘b: Corresponds to INCR16 fixed 16 beat incremental AHB burst mode. Only
valid when burst_mode is high.
11‘b: Corresponds to INCR16 fixed 16 beat incremental AHB burst mode. Only
valid when burst_mode is high.
0 burst_mode R/W 1‘b:Forces the burst mode to be fixed beat incremental burst mode designated
by the incr_type[1:0] signal
0‘b: Normal operation is unspecified length incremental burst. It corresponds to
INCR AHB burst mode

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5.2.10.2 ahb_dma_start
This register is only present when the the AUDIO_IF is set to AHBAUDDMA (8).
The start_dma_transaction bit field signals the AHB audio DMA to start accessing system memory in order
to fetch data samples to store in the FIFO. After the operation starts, a new request for a DMA start is
ignored until the DMA is stopped or it reaches the end address. Only in one of these situations is a new start
request acknowledged.
The first DMA burst request after start_dma_transaction configuration uses initial_addr[31:0] as
ohaddr[31:0] value; mburstlength[8:0] is set to the maximum admissible value. This maximum value is
constrained by the size of buffer provided, the instantiated FIFO depth, or/and the number of words up to
the next 1 Kbyte boundary.
■ Name: Audio DMA Start Register
■ Address Offset: 0x3601
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-204 ahb_dma_start

Bits Name R/W Description

7:1 Reserved and read as zero
0 start_dma_transaction R/W Start DMA transaction

5.2.10.3 ahb_dma_stop
This register is only present when the the AUDIO_IF is set to AHBAUDDMA (8).
The stop_dma_transaction bit field signals the AHB audio DMA to stop current memory access. After it
stops, if a new start DMA operation is requested, the DMA engine restarts the memory access using the
initial_addr[31:0], which is programmed at ahb_dma_straddr0 to ahb_dma_straddr3.
■ Name: Audio DMA Stop Register
■ Address Offset: 0x3602
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-205 ahb_dma_stop

Bits Name R/W Description

7:1 Reserved and read as zero
0 stop_dma_transaction R/W Stop DMA transaction

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Table 5-209 ahb_dma_straddr_set0_2

Bits Name R/W Description

7:0 initial_addr[23:16] R/W Defines init_addr[23:16] for bits 7:0 to initiate DMA burst transactions

Table 5-210 ahb_dma_straddr_set0_3

Bits Name R/W Description

7:0 initial_addr[31:24] R/W Defines init_addr[31:24] for bits 7:0 to initiate DMA burst transactions

5.2.10.6 ahb_dma_stpaddr_set0_0 to ahb_dma_stpaddr_set0_3

This registers define the final_addr[31:0] used as the final point to the DMA burst read transactions. They
are only present when the the AUDIO_IF is set to AHBAUDDMA (8).
Upon start_dma_transaction configuration, the DMA engine starts requesting burst reads from the external
system memory. Each burst read can have a maximum theoretical length of 256 words (due to the AMBA
AHB specification 1 Kbyte boundary burst limitation).
The DMA engine is responsible for incrementing the burst starting address and defining its corresponding
burst length to reach the final_addr[31:0] address. The last burst request issued by the DMA engine takes
into account that it should only request data until the final_addr[31:0] address (included) and for that
should calculate the correct burst length.
After reaching the final_addr[31:0] address, the done interrupt is active to signal completion of DMA
operation.
For more information on the configuration of address registers, see “Rules for Configuration of Address
Registers” on page 261.
■ Name: Audio DMA Stop Address Register 0 to Audio DMA Stop Address Register 3
■ Address Offset: 0x3608 to 0x360B
■ Size: 8 bits per register
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-211 ahb_dma_stpaddr_set0_0

Bits Name R/W Description

7:0 final_addr[7:0] R/W Defines final_addr[7:0] for bits 7:0 to end DMA burst transactions

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Table 5-212 ahb_dma_stpaddr_set0_1

Bits Name R/W Description

7:0 final_addr[15:8] R/W Defines final_addr[15:8] for bits 7:0 to end DMA burst transactions

Table 5-213 ahb_dma_stpaddr_set0_2

Bits Name R/W Description

7:0 final_addr[23:16] R/W Defines final_addr[23:16] for bits 7:0 to end DMA burst transactions

Table 5-214 ahb_dma_stpaddr_set0_3

Bits Name R/W Description

7:0 final_addr[31:24] R/W Defines final_addr[31:24] for bits 7:0 to end DMA burst transactions

Rules for Configuration of Address Registers

■ Configure the last 2 bits of initial_addr with 0.
For example, 32’h0000_0000.
■ Configure the last 2 bits of final_addr with non-zero values.
For example,
32’hxxx_xxx3 or
32’hxxx_xxx7 or
32’hxxx_xxxB or
32’hxxx_xxxF
Where x= any value
■ The number of samples is calculated by using the following formula:
Number of samples = (final_addr - initial_addr + 1) / 4
Therefore, final_addr = (Number of samples x 4) + initial_addr -1
If a defined length burst is used, align initial_addr, final_addr and fifo_threshold with the value. If
the burst is not aligned, DMA uses AHB INCR transfers when required.
Then the number of samples = 100 (a multiple of 5)
■ The threshold must be
❑ Smaller than the selected FIFO DEPTH
❑ Greater than the number of channels enabled in channel allocation

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5.2.10.7 ahb_dma_bstaddr0 to ahb_dma_bstaddr3

These read-only registers compose the start address of the current burst operation.
burst_start_addr[31:0] = haddr[31:0] = initial_addr[31:0] + 16. They are only present when the the
AUDIO_IF is set to AHBAUDDMA (8).
■ Name: Audio DMA Burst Start Address Register 0 to Audio DMA Burst Start Address Register 3
■ Address Offset: 0x360C to 0x360F
■ Size: 8 bits per register
■ Value after Reset: 0x00
■ Access: Read

Table 5-215 ahb_dma_bstaddr0

Bits Name R/W Description

7:0 burst_start[7:0] R Start address for the current burst operation (burst_star[7:0])

Table 5-216 ahb_dma_bstaddr1

Bits Name R/W Description

7:0 burst_start[15:8] R Start address for the current burst operation (burst_star[15:8])

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Table 5-221 ahb_dma_mask (Continued)

Bits Name R/W Description

4 error_mask R/W Error interrupt mask. Active when slave indicates error through the
isresp[1:0].
3 Reserved and read as zero
2 fifo_thrempty_mask R/W Audio FIFO empty interrupt mask when audio FIFO has less than the
number of enabled audio channels. For more information, see “Audio FIFO”
on page 60.
1 fifo_full_mask R/W Audio FIFO full interrupt mask. For more information, see “Audio FIFO” on
page 60.
0 fifo_emplty_mask R/W Audio FIFO empty interrupt mask. For more information, see “Audio FIFO”
on page 60.

5.2.10.10 ahb_dma_conf1
In AUDS packet configuration with layout 0 selected, the maximum number of active channels is 2.
■ Name: Audio DMA Channel Enable Configuration Register 1
■ Address Offset: 0x3616
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-222 ahb_dma_conf1

Bits Name R/W Description

7:0 ch_in_en R/W Each bit controls the enabling of the respective audio channel. For instance when
bit 1, is set (1'b1), it enables audio Channel 1. When cleared, it disables the
referred channel.

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5.2.10.11 ahb_dma_buffmask
■ Name: Audio DMA Buffer Mask Interrupt Register
■ Address Offset: 0x3619
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-223 ahb_dma_buffmask

Bits Name R/W Description

7:5 Reserved and read as zero
4 mask_overrun_mask R/W Buffer overrun flag mask
3 Reserved and read as zero
1 mask_buff_full R/W Buffer full flag mask
0 mask_buff_empty R/W Buffer empty flag mask

5.2.10.12 ahb_dma_mask1
This register masks interrupts present in the AHB audio DMA module. This is only present when the
AUDIO_IF configuration parameter is set to AHBAUDDMA (8).
■ Name: Audio DMA Mask Interrupt Register 1
■ Address Offset: 0x361B
■ Size: 8 bits per register
■ Value after Reset: 0x03
■ Access: Read/Write

Table 5-224 ahb_dma_mask1

Bits Name R/W Description

7:2 Reserved and read as zero

1 fifo_underrun_mask R/W AHB DMA FIFO underrun mask

0 fifo_overrun_mask R/W AHB DMA FIFO overrun mask

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5.2.10.13 ahb_dma_status
■ Name: Audio DMA Status
■ Address Offset: 0x361C
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read

Table 5-225 ahb_dma_status

Bits Name R/W Description

7:1 Reserved R Reserved and read as zero

0 autostart_status R Indicates the set of start and stop addresses currently used by the AHB
audio DMA.
If clear (1'b0), the start and stop addresses configured in the address
range 0x3604 to 0x360B are being used, and when set (1'b1), the
configurations at address range 0x3620 to 0x3627 are being used.
This bit is always at zero when autostart_enable is clear (1'b0).

5.2.10.14 ahb_dma_conf2
■ Name: Audio DMA Configuration Register 2
■ Address Offset: 0x361D
■ Size: 8 bits
■ Value after Reset: 0x02
■ Access: Read/Write
Table 5-226 ahb_dma_conf2

Bits Name R/W Description

7:2 Reserved and read as zero
1 autostart_loop R/W Enables the AHB audio DMA auto-start loop mode
0 autostart_enable R/W Enables the AHB audio DMA auto-start feature

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5.2.10.15 ahb_dma_straddr_set1_0 to ahb_dma_straddr_set1_3

These registers define the initial_addr_1[31:0] used to initiate the DMA burst read transactions upon
start_dma_transaction configuration. They are only present when the AUDIO_IF configuration parameter is
set to AHBAUDDMA (8).
For more information on the configuration of address registers, see “Rules for Configuration of Address
Registers” on page 261.
■ Name: Audio DMA Start Address Set1 Register 0 to Audio DMA Start Address Set1 Register 3
■ Address Offset: 0x3620 to 0x3623
■ Size: 8 bits per register
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-227 ahb_dma_straddr_set1_0

Bits Name R/W Description

7:0 initial_addr_1[7:0] R/W Defines initial_addr_1[7:0] for bits 7:0 to initiate DMA burst transactions

Table 5-228 ahb_dma_straddr_set1_1

Bits Name R/W Description

7:0 initial_addr_1[15:8] R/W Defines initial_addr_1[15:8] for bits 7:0 to initiate DMA burst
transactions

Table 5-229 ahb_dma_straddr_set1_2

Bits Name R/W Description

7:0 initial_addr_1[23:16] R/W Defines initial_addr_1[23:16] for bits 7:0 to initiate DMA burst
transactions

Table 5-230 ahb_dma_straddr_set1_3

Bits Name R/W Description

7:0 initial_addr_1[31:24] R/W Defines initial_addr_1[31:24] for bits 7:0 to initiate DMA burst
transactions

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5.2.10.16 ahb_dma_stpaddr_set1_0 to ahb_dma_stpaddr_set1_3

These registers define the final_addr_1[31:0] used as the final point to the DMA burst read transactions.
They are only present when the AUDIO_IF configuration parameter is set to AHBAUDDMA (8).
Upon start_dma_transaction configuration, the DMA engine starts requesting burst reads from the external
system memory. Each burst read can have a maximum theoretical length of 256 words (due to the AMBA
AHB specification 1 Kbyte boundary burst limitation).
The DMA engine is responsible for incrementing the burst starting address and defining its corresponding
burst length to reach the final_addr[31:0] address. The last burst request issued by the DMA engine takes
into account that it should only request data until the final_addr[31:0] address (included) and for that
should calculate the correct burst length.
After reaching the final_addr_1[31:0] address, the done interrupt is active to indicate completion of the
DMA operation.
For more information on the configuration of address registers, see “Rules for Configuration of Address
Registers” on page 261.
■ Name: Audio DMA Stop Address Set1 Register 0 to Audio DMA Stop Address Set1 Register 3
■ Address Offset: 0x3624 to 0x3627
■ Size: 8 bits per register
■ Value after Reset: 0x00
■ Access: Read/Write
Table 5-231 ahb_dma_stpaddr_set1_0

Bits Name R/W Description

7:0 final_addr_1[7:0] R/W Defines final_addr_1[7:0] for bits 7:0 to end DMA burst transactions

Table 5-232 ahb_dma_stpaddr_set1_1

Bits Name R/W Description

7:0 final_addr[15:8] R/W Defines final_addr[15:8] for bits 7:0 to end DMA burst transactions

Table 5-233 ahb_dma_stpaddr_set1_2

Bits Name R/W Description

7:0 final_addr[23:16] R/W Defines final_addr[23:16] for bits 7:0 to end DMA burst transactions

Table 5-234 ahb_dma_stpaddr_set1_3

Bits Name R/W Description

7:0 final_addr[31:24] R/W Defines final_addr[31:24] for bits 7:0 to end DMA burst transactions

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5.2.11 Main Controller Registers

This section includes the descriptions for the Main Controller registers.

5.2.11.1 mc_clkdis
Main controller synchronous disable control per clock domain. Upon release of synchronous disable the
corresponding sw reset NRZ request signal, to that domain, is toggled asking to the output for a
synchronized active low reset to be generated to that domain.
■ Name: Main Controller Synchronous Clock Domain Disable Register
■ Address Offset: 0x4001
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-235 mc_clkdis

Bits Name R/W Description

7 Reserved and read as zero
6 hdcpclk_disable R/W HDCP clock synchronous disable signal. When active (1b) simultaneously
bypasses HDCP.
Dependencies: This bit is configurable when HDCP = 1 (True). Otherwise, it is
reserved and read as zero.
5 cecclk_disable R/W CEC Engine clock synchronous disable signal.
4 cscclk_disable R/W Color Space Converter clock synchronous disable signal.
3 audclk_disable R/W Audio Sampler clock synchronous disable signal.
2 prepclk_disable R/W Pixel Repetition clock synchronous disable signal.
1 tmdsclk_disable R/W TMDS clock synchronous disable signal.
It is required to perform a write action on one of the following registers:
- fc_invidconf, fc_inhactiv0, fc_inhactiv1, fc_inhblank0, fc_inhblank1,
fc_invactiv0,
- fc_invactiv1, fc_invblank, fc_hsyncindelay0, fc_hsyncindelay1,
fc_hsyncinwidth0,
- fc_hsyncinwidth1, fc_vsyncindelay, fc_vsyncinwidth, fc_ctrldur, fc_exctrldur,
fc_exctrlspac
0 pixelclk_disable R/W Pixel clock synchronous disable signal.

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5.2.11.2 mc_swrstzreq
Main controller software reset request per clock domain. Writing zero to a bit of this register results in an
NRZ signal toggle at sfrclk rate to an output signal that indicates a software reset request. This toggle must
be used to generate a synchronized reset to de corresponding domain, with at least 1 clock cycle. Register
defaults back to 0xFF.
■ Name: Main Controller Software Reset Register
■ Address Offset: 0x4002
■ Size: 8 bits
■ Value after Reset: 0xFF
■ Access: Read/Write

Table 5-236 mc_swrstzreq

Bits Name R/W Description

7 igpaswrst_req R/W GPAUD interface soft reset request. This bit is enabled when the Generic Parallel
Audio (GPAUD) interface is enabled (AUDIO_IF = 6). Otherwise, this bit returns zero.
This bit defaults to 1b after a reset is requested.
6 cecswrst_req R/W CEC software reset request. Defaults back to 1b after reset request.
Note: After you configure cecswrst_req, set the value of the bit csc_clk_disable of
the register mc_clkdis to 1, 0, and then 1 again.
5 Reserved and read as zero
4 ispdifswrst_req R/W S/PDIF audio software reset request. Defaults back to 1b after reset request.
3 ii2sswrst_req R/W I2S audio software reset request. Defaults back to 1b after reset request.
2 prepswrst_req R/W Pixel Repetition software reset request. Defaults back to 1b after reset request.
1 tmdsswrst_req R/W TMDS software reset request. Defaults back to 1b after reset request.
It is required to perform a write action on one of the following registers:
- fc_invidconf, fc_inhactiv0, fc_inhactiv1, fc_inhblank0, fc_inhblank1,
fc_invactiv0,
- fc_invactiv1, fc_invblank, fc_hsyncindelay0, fc_hsyncindelay1,
fc_hsyncinwidth0,
- fc_hsyncinwidth1, fc_vsyncindelay, fc_vsyncinwidth, fc_ctrldur, fc_exctrldur,
fc_exctrlspac
0 pixelswrst_req R/W Pixel software reset request. Defaults back to 1b after reset request.

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5.2.11.9 mc_swrstzreq_2
Main controller software reset request per clock domain. Writing zero to a bit of this register results in a
signal toggle that indicates a software reset request. This toggle is used to generate a synchronized reset to
the corresponding domain, with one or more clock cycles.
■ Name: Main Controller Software Reset Register 1
■ Address Offset: 0x400A
■ Size: 8 bits per register
■ Value after Reset: 0x01
■ Access: Read/Write

Table 5-243 mc_swrstzreq_2

Color Space Conversion A3 coefficient. This register is only present when hardware configuration
parameter CSC = 1 (True).
■ Name: Color Space Converter Matrix A3 Coefficient Register MSB, Color Space Converter Matrix A3
Coefficient Register LSB
■ Address Offset: 0x4106, 0x4107
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-250 csc_coef_a3_msb

Bits Name R/W Description

7:0 csc_coef_a3_msb R/W Color Space Converter Matrix A3 Coefficient Register MSB

7:0 csc_coef_b1_lsb R/W Color Space Converter Matrix B1 Coefficient Register LSB

5.2.12.8 csc_coef_b2_msb, csc_coef_b2_lsb

Color Space Conversion B2 coefficient. This register is only present when hardware configuration
parameter CSC = 1 (True).
■ Name: Color Space Converter Matrix B2 Coefficient Register MSB, Color Space Converter Matrix B2
Coefficient Register LSB
■ Address Offset: 0x410C, 0x410D
■ Size: 8 bits
■ Value after Reset: 0x20, 0x00
■ Access: Read/Write

Table 5-256 csc_coef_b2_msb

Bits Name R/W Description

7:0 csc_coef_b2_msb R/W Color Space Converter Matrix B2 Coefficient Register MSB

Table 5-257 csc_coef_b2_lsb

Bits Name R/W Description

7:0 csc_coef_b2_lsb R/W Color Space Converter Matrix B2 Coefficient Register LSB

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5.2.12.9 csc_coef_b3_msb, csc_coef_b3_lsb

Color Space Conversion B3 coefficient. This register is only present when hardware configuration
parameter CSC = 1 (True).
■ Name: Color Space Converter Matrix B3 Coefficient Register MSB, Color Space Converter Matrix B3
Coefficient Register LSB
■ Address Offset: 0x410E, 0x410F
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-258 csc_coef_b3_msb

Bits Name R/W Description

7:0 csc_coef_b3_msb R/W Color Space Converter Matrix B3 Coefficient Register MSB

7:0 csc_coef_c1_lsb R/W Color Space Converter Matrix C1 Coefficient Register LSB

5.2.12.12 csc_coef_c2_msb, csc_coef_c2_lsb

Color Space Conversion C2 coefficient. This register is only present when hardware configuration
parameter CSC = 1 (True).
■ Name: Color Space Converter Matrix C2 Coefficient Register MSB, Color Space Converter Matrix C2
Coefficient Register LSB
■ Address Offset: 0x4114, 0x4115
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-264 csc_coef_c2_msb

Bits Name R/W Description

7:0 csc_coef_c2_msb R/W Color Space Converter Matrix C2 Coefficient Register MSB

Table 5-265 csc_coef_c2_lsb

Bits Name R/W Description

7:0 csc_coef_c2_lsb R/W Color Space Converter Matrix C2 Coefficient Register LSB

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5.2.12.13 csc_coef_c3_msb, csc_coef_c3_lsb

Color Space Conversion C3 coefficient. This register is only present when hardware configuration
parameter CSC = 1 (True).
■ Name: Color Space Converter Matrix C3 Coefficient Register MSB, Color Space Converter Matrix C3
Coefficient Register LSB
■ Address Offset: 0x4116, 0x4117
■ Size: 8 bits
■ Value after Reset: 0x20, 0x00
■ Access: Read/Write

Table 5-266 csc_coef_c3_msb

Bits Name R/W Description

7:0 csc_coef_c3_msb R/W Color Space Converter Matrix C3 Coefficient Register MSB

5.2.13.4 a_hdcpobs1
This register is only present when hardware configuration parameter HDCP = 1 (True).
■ Name: HDCP Observation Register 1
■ Address Offset: 0x5003
■ Size: 8 bits
■ Value after Reset: N/A
■ Access: Read

Table 5-274 a_hdcpobs1

Bits Name R/W Description

7:6 Reserved and read as 0
5:3 STATEOEG R Observability register informs in which state the OESS machine is on.
2:0 STATER R Observability register informs in which state the revocation machine is on.

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5.2.13.5 a_hdcpobs2
This register is only present when hardware configuration parameter HDCP = 1 (True).
■ Name: HDCP Observation Register 2
■ Address Offset: 0x5004
■ Size: 8 bits
■ Value after Reset: N/A
■ Access: Read

4 dataenpol R/W Configuration of the video data enable polarity

3 vsyncpol R/W Configuration of the video Vertical synchronism polarity
2 spare_2 R/W This is a spare bit and has no associated functionality.
1 hsyncpol R/W Configuration of the video Horizontal synchronism polarity.
0 spare_1 R/W This is a spare bit and has no associated functionality.

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5.2.13.28 hdcp_revoc_size_1
This register is only present when hardware configuration parameter HDCP = 1 (True).
■ Name: HDCP Revocation KSV List Size Register 1
■ Address Offset: 0x52ba
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-295 hdcp_revoc_size_0

Bits Name R/W Description

7:0 hdcp_revoc_size_1 R/W Register containg LSB of KSV list size (ksv_list_size[7:0]). If memory access
has not been granted (see register a_ksvmemctrl), the value read is 8'hff.

5.2.13.29 hdcp_revoc_list[5120]
This register is only present when hardware configuration parameter HDCP = 1 (True).
■ Name: HDCP Revocation KSV Registers
■ Address Offset: 0x52bb
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-296 hdcp_revoc_list[5120]

Bits Name R/W Description

7:0 hdcp_revoc_list_ksv_byte R/W Revocation KSV byte, ordered in little endian(byte at address 0x52bb
bellows to byte 0 of VH0). If memory access has not been granted (see
register a_ksvmemctrl), the value read is 8'hff.

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5.2.14 HDCP BKSV Registers

During HDCP authentication, the HDCP Transmitter (Device A) sends an A Key Selection Vector (AKSV) to
the HDCP Receiver (Device B), which affirms its authorization to the HDCP Transmitter by sending a B Key
Selection Vector (BKSV). The BKSV registers contain the 40-bit BKSV value read by the HDCP transmitter
from the HDCP receiver.
The BKSV value that is received from the HDCP receiver enables DWC_hdmi_tx operation in repeater
applications. The BKSV value is only valid once the authentication is concluded (that is, HDCP is engaged).
Bit 7 of the register a_apiintstat denotes that HDCP is engaged.
If DWC_hdmi_tx is connected to a repeater, you can read the BKSV value of the repeater from the HDCP
BKSV Registers. However, the KSV list of the receivers attached to the repeater is stored in the
KSV/Revocation memory only. For more information, see “KSV MEM RAM – Revocation Memory” on
page 75.

5.2.14.1 hdcpreg_bksv0
This register is only present when hardware configuration parameter HDCP = 1 (True).
■ Name: HDCP BKSV Status Register 0
■ Address Offset: 0x7800
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read

Table 5-297 hdcpreg_bksv0

Bits Name R/W Description

7:0 hdcpreg_bksv0 R/W Contains the value of BKSV[7:0]. If memory access has not been granted
(see register a_ksvmemctrl), the value read is 8'hff.

5.2.14.2 hdcpreg_bksv1
This register is only present when hardware configuration parameter HDCP = 1 (True).
■ Name: HDCP BKSV Status Register 1
■ Address Offset: 0x7801
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read

Table 5-298 hdcpreg_bksv1

Bits Name R/W Description

7:0 hdcpreg_bksv1 R/W Contains the value of BKSV[15:8]. If memory access has not been
granted (see register a_ksvmemctrl), the value read is 8'hff.

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7:0 hdcpreg_bksv4 R/W Contains the value of BKSV[39:32]. If memory access has not been
granted (see register a_ksvmemctrl), the value read is 8'hff.

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5.2.15 HDCP AN Registers

During HDCP authentication, the HDCP Transmitter (Device A) sends an A Key Selection Vector (AKSV)
and a 64-bit pseudo-random value (AN) to the HDCP Receiver (Device B).
HDCP AN registers contain the 64-bit pseudo-random value (AN).
When you do not want to use the Random Number Generator Interface (irndnum, orndnumgenena) of the
DWC_hdmi_tx core, the registers force the test AN value to be used instead of the Random Number
Generator Interface value.

7 Reserved and read as zero.
6 wakeup R/W Follower wake-up signal mask
5 error_flow R/W An error is notified by a follower. Abnormal logic data bit error (for follower).
4 error_initiator R/W An error is detected on cec line (for initiator only).
3 arb_lost R/W The initiator losses the CEC line arbitration to a second initiator. (specification
CEC 9).
2 nack R/W A frame is not acknowledged in a directly addressed message. Or a frame is
negatively acknowledged in a broadcast message (for initiator only).
1 eom R/W EOM is detected so that the received data is ready in the receiver data buffer
(for follower only).
0 done R/W The current transmission is successful (for initiator only).

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5.2.16.3 cec_addr_l, cec_addr_h

CEC_ADDR_L and CEC_ADDR_H registers indicate the logical address(es) allocated to the CEC device.
The logical address mapping is shown in Table 5-313. This register is written by software when the logical
allocation is finished. Bit value 1 means the corresponding logical address is allocated to this device. Bit
value 0 means the corresponding logical address is not allocated to this device. These registers are only
present when hardware configuration parameter CEC = 1 (True).
■ Name: CEC Logical Address Register Low, CEC Logical Address Register High
■ Address Offset: 0x7D05, 0x7D06
■ Size: 8 bits
■ Value after Reset: 0x00, 0x80
■ Access: Read/Write

Table 5-313 cec_addr_l, cec_addr_h Registers

Value
after
Bits Field Name R/W Description Reset
cec_addr_l (0x7D05 address) and cec_addr_h (0x7D06 address)
0 cec_addr_l_0 R/W Logical address 0 – Device TV 1'b0
1 cec_addr_l_1 R/W Logical address 1 – Recording Device 1 1'b0
2 cec_addr_l_2 R/W Logical address 2 – Recording Device 2 1'b0
3 cec_addr_l_3 R/W Logical address 3 – Tuner 1 1'b0
4 cec_addr_l_4 R/W Logical address 4 – Playback Device 1 1'b0
5 cec_addr_l_5 R/W Logical address 5 – Audio System 1'b0
6 cec_addr_l_6 R/W Logical address 6 – Tuner 2 1'b0
7 cec_addr_l_7 R/W Logical address 7 – Tuner 3 1'b0
0 cec_addr_h_0 R/W Logical address 8 – Playback Device 2 1'b0
1 cec_addr_h_1 R/W Logical address 9 – Playback Device 3 1'b0
2 cec_addr_h_2 R/W Logical address 10 – Tuner 4 1'b0
3 cec_addr_h_3 R/W Logical address 11 – Playback Device 3 1'b0
4 cec_addr_h_4 R/W Logical address 12 – Reserved 1'b0
5 cec_addr_h_5 R/W Logical address 13 – Reserved 1'b0
6 cec_addr_h_6 R/W Logical address 14 – Free use 1'b0
7 cec_addr_h_7 R/W Logical address 15 – Unregistered (as initiator address), 1'b1
Broadcast (as destination address)

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5.2.16.4 cec_tx_cnt
This register indicates the size of the frame in bytes (including header and data blocks), which are available
in the transmitter data buffer. This register is only present when hardware configuration parameter CEC = 1
(True).

When the value is zero, the CEC controller ignores the send command triggered by software.
Note When the transmission is done (no matter success or not), the current value is held until it is
overwritten by software.

■ Name: CEC TX Frame Size Register

■ Address Offset: 0x7D07
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-314 cec_tx_cnt

Bits Name R/W Description

7:5 Reserved and read as zero
4:0 cec_tx_cnt R/W CEC Transmitter Counter register
Value after Reset: 5’b00000
Value Description
0 No data needs to be transmitted.
1 Frame size is 1 byte.
...
16 Frame size is 16 byte.

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5.2.16.5 cec_rx_cnt
This register indicates the size of the frame in bytes (including header and data blocks), which are available
in the receiver data buffer. This register is only present when hardware configuration parameter CEC = 1
(True).

Note Only after the whole receiving process is finished successfully, the counter is refreshed to the
value which indicates the total number of data bytes in the Receiver Data Register.

■ Name: CEC RX Frame Size Register

■ Address Offset: 0x7D08
■ Size: 8 bits
■ Value after Reset: N/A
■ Access: Read

Table 5-315 cec_rx_ctn Register

Bits Name R/W Description

7:5 Reserved and read as zero
4:0 cec_rx_cnt R CEC Receiver Counter register
Value after Reset: 5‘b00000
Value Description
0 No data received
1 1-byte data is received.
...
16 16-byte data is received.

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5.2.16.6 cec_tx_data0 to cec_tx_data15

These registers (8 bits each) are the buffers used for storing the data waiting for transmission (including
header and data blocks). These registers are only present when hardware configuration parameter CEC = 1
(True).
■ Name: CEC TX Data Register 0 to CEC TX Data Register 15
■ Address Offset: 0x7D10 .. 0x7D1F
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-316 cec_tx_data0 to cec_tx_data15 Registers

Value
after
Address Register Bit Field [7:0] R/W Description Reset
cec_tx_data0 to cec_tx_data15 - 0x7d10 to 0x7d1f addresses
0x7D10 cec_tx_data0 databyte R/W Data bit 0 0x00
0x7D11 cec_tx_data1 databyte R/W Data bit 1 0x00
0x7D12 cec_tx_data2 databyte R/W Data bit 2 0x00
… … R/W … …
0x7D1F cec_tx_data15 databyte R/W Data bit 15 0x00

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5.2.16.7 cec_rx_data0 to cec_rx_data15

These registers (8 bit each) are the buffers used for storing the received data (including header and data
blocks). These registers are only present when hardware configuration parameter CEC = 1 (True).
■ Name: CEC RX Data Register 0 to CEC RX Data Register 15
■ Address Offset: 0x7D20 .. 0x7D2F
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read

Table 5-317 cec_rx_data0 to cec_rx_data15 Registers

Value
after
Address Register Bit Field [7:0] R/W Description Reset
CEC_RX_DATA0 to CEC_RX_DATA15 - 0x7D20 to 0x7D2F addresses
0x7D20 cec_rx_data0 databyte R Data bit 0 0x00
0x7D21 cec_rx_data1 databyte R Data bit 1 0x00
0x7D22 cec_rx_data2 databyte R Data bit 2 0x00
… … R … …
0x7D2F cec_rx_data15 databyte R Data bit 15 0x00

5.2.16.8 cec_lock
This register is only present when hardware configuration parameter CEC = 1 (True).
■ Name: CEC Buffer Lock Register
■ Address Offset: 0x7D30
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-318 cec_lock Register

Bits Name R/W Description

7..1 Reserved and read as zero
0 locked_buffer R/W When a frame is received, this bit would be active. The CEC controller
answers to all the messages with NACK until the CPU writes it to '0'.

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5.2.16.9 cec_wkupctrl
■ Name: CEC Wake-up Control Register
■ Address Offset: 0x7D31
■ Size: 8 bits
■ Value after Reset: 0xFF
■ Access: Read/Write
After receiving a message in the CEC_RX_DATA1 (OPCODE) registers, the CEC engine verifies the
message opcode[7:0] against one of the previously defined values to generate the wake-up status:
Wakeupstatus is 1 when:
received opcode is 0x04 and opcode0x04en is 1 or
received opcode is 0x0D and opcode0x0Den is 1 or
received opcode is 0x41 and opcode0x41en is 1 or
received opcode is 0x42 and opcode0x42en is 1 or
received opcode is 0x44 and opcode0x44en is 1 or
received opcode is 0x70 and opcode0x70en is 1 or
received opcode is 0x82 and opcode0x82en is 1 or
received opcode is 0x86 and opcode0x86en is 1

Wakeupstatus is 0 when none of the previous conditions are true.

This formula means that the wake-up status (on CEC_STAT[6] register) is only ‘1’ if the opcode[7:0]
received is equal to one of the defined values and the corresponding enable bit of that defined value is set to
‘1’.

Table 5-319 cec_wkupctrl Register

Value
after
Bits Field Name R/W Description Reset
cec_wkupctrl – 0x7D31 address
7 opcode0x86en R/W OPCODE 0x86 wake up enable 1'b1
6 opcode0x82en R/W OPCODE 0x82 wake up enable 1'b1
5 opcode0x70en R/W OPCODE 0x70 wake up enable 1'b1
4 opcode0x44en R/W OPCODE 0x44 wake up enable 1'b1
3 opcode0x42en R/W OPCODE 0x42 wake up enable 1'b1
2 opcode0x41en R/W OPCODE 0x41 wake up enable 1'b1
1 opcode0x0den R/W OPCODE 0x0D wake up enable 1'b1
0 opcode0x04en R/W OPCODE 0x04 wake up enable 1'b1

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7:0 datao R/W Data to be written on register pointed by address[7:0].

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5.2.17.4 i2cm_datai
■ Name: I2C DDC Data Read Register
■ Address Offset: 0x7E03
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read

Table 5-323 i2cm_datai Register

Bits Name R/W Description

7:0 datai[7:0] R Data read from register pointed by address[7:0].

5.2.17.5 i2cm_operation
Read and write operation request. This register can only be written; reading this register always results in
00h. Writing 1'b1 simultaneously to rd, rd_ext and wr requests is considered as a read (rd) request.
■ Name: I2C DDC RD/RD_EXT/WR Operation Register
■ Address Offset: 0x7E04
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Write

Table 5-324 i2cm_operation Register

Bits Name R/W Description

7:5 Reserved and read as zero
4 wr W Write operation request.
3:2 Reserved and read as zero
1 rd_ext W After writing 1'b1 to rd_ext bit a extended data read operation is started (E-DDC read
operation).
0 rd W Read operation request.

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5.2.17.6 i2cm_int
This register contains and configures I2C master done interrupt.
■ Name: I2C DDC Done Interrupt Register
■ Address Offset: 0x7E05
■ Size: 8 bits
■ Value after Reset: 0x08
■ Access: Read/Write

Table 5-325 i2cm_int Register

Bits Name R/W Description

7:4 Reserved and read as zero
3 done_pol R/W Done interrupt polarity configuration.
2 done_mask R/W Done interrupt mask signal.
1 done_interrupt R Operation done interrupt bit. Only lasts for 1 SFR clock cycle and is auto
cleaned after it.
{done_interrupt = (done_mask==0b) && (done_status==done_pol)}.
0 done_status R Operation done status bit. Marks the end of a rd or write operation.

5.2.17.7 i2cm_ctlint
This register contains and configures I2C master arbitration error and not acknowledge error interrupt.
■ Name: I2C DDC Error Interrupt Register
■ Address Offset: 0x7E06
■ Size: 8 bits
■ Value after Reset: 0x88
■ Access: Read/Write

Table 5-326 i2cm_ctlint Register

Bits Name R/W Description

7 nack_pol R/W Not acknowledge error interrupt polarity configuration.
6 nack_mask R/W Not acknowledge error interrupt mask signal.
5 nack_interrupt R Not acknowledge error interrupt bit. Only lasts for 1 SFR clock cycle and is auto
cleaned after it.
{nack_interrupt = (nack_mask==0b) && (nack_status==nack_pol)}.
4 nack_status R Not acknowledge error status bit. Error on I2C not acknowledge.
3 arbitration_pol R/W Arbitration error interrupt polarity configuration.
2 arbitration_mask R/W Arbitration error interrupt mask signal.

5.2.17.16 i2cm_fs_scl_hcnt_1_addr
■ Name: I2C DDC Fast Speed SCL High Level Control Register 1
■ Address Offset: 0x7E0F
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-335 i2cm_ss_scl_hcnt_1_addr Register

Bits Name R/W Description

7:0 i2cmp_fs_scl_hcnt1 R/W I2C DDC Fast Speed SCL High Level Control Register 1
Value after Reset: 8'h00

5.2.17.17 i2cm_fs_scl_hcnt_0_addr
■ Name: I2C DDC Fast Speed SCL High Level Control Register 0
■ Address Offset: 0x7E10
■ Size: 8 bits
■ Value after Reset: 0x11
■ Access: Read/Write

Table 5-336 i2cm_fs_scl_hcnt_0_addr Register

Bits Name R/W Description

7:0 i2cmp_fs_scl_hcnt0 R/W I2C DDC Fast Speed SCL High Level Control Register 0
Value after Reset: 8'h11

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5.2.17.18 i2cm_fs_scl_lcnt_1_addr
■ Name: I2C DDC Fast Speed SCL Low Level Control Register 1
■ Address Offset: 0x7E11
■ Size: 8 bits
■ Value after Reset: 0x00
■ Access: Read/Write

Table 5-337 i2cm_fs_scl_lcnt_1_addr Register

Bits Name R/W Description

7:0 i2cmp_fs_scl_lcnt1 R/W I2C DDC Fast Speed SCL Low Level Control Register 1
Value after Reset: 8'h00

5.2.17.19 i2cm_fs_scl_lcnt_0_addr
■ Name: I2C DDC Fast Speed SCL Low Level Control Register 0
■ Address Offset: 0x7E12
■ Size: 8 bits
■ Value after Reset: 0x24
■ Access: Read/Write
Table 5-338 i2cm_fs_scl_lcnt_0_addr Register

Bits Name R/W Description

7:0 i2cmp_fs_scl_lcnt0 R/W I2C DDC Fast Speed SCL Low Level Control Register 0
Value after Reset: 8'h24

5.2.17.20 i2cm_sda_hold
■ Name: I2C DDC SDA HOLD Register
■ Address Offset: 0x7E13
■ Size: 8 bits
■ Value after Reset: 0x09
■ Access: Read/Write

Table 5-339 i2cm_sda_hold Register

Bits Name R/W Description

7:0 osda_hold R/W Defines the number of SFR clock cycles to meet tHD;DAT (300 ns)
osda_hold = round_to_high_integer (300 ns / (1 / isfrclk_frequency))

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A
HDCP Application Note

This application note discusses the authentication protocol defined by the HDMI 1.4b specification.

A.1 Authentication Protocol

A.1.1 First Part of Authentication Protocol
Figure A-1 illustrates the first part of the authentication exchange.

Figure A-1 First Part of Protocol

HDCP Transmitter (Device A) Initiate Authentication HDCP Receiver (Device B)

Generate An An, Aksv

Read: Bksv, REPEATER

Km = Σ Akeys over Bksv

(Ks, M0, R0) = hdcpBlkCipher(Km, Km’ = Σ Bkeys over Aksv
REPEATER || An) Read: R0‘ (Ks‘, M0‘, R0‘) = hdcpBlkCipher(Km‘,
REPEATER || An)
Verify R0 = R0‘

The first part of the protocol functions accordingly:

■ HDCP Transmitter starts at any time by sending its Aksv (key selection vector) and An (64-bit
pseudo-random value).
■ The Receiver responds with its own KSV (Bksv) and a REPEATER flag (if it is a Repeater or not)
■ The HDCP TX checks if the Bksv is not in the revocation black list, and if it has 20 ones and 20 zeros.
■ Both TX and RX calculate a shared secret key (km, km') with the KSV and DPKs. If either one has
invalid set of DPK, km is not equal to km'.
■ The cipher block calculates Ks (56-bit secret session key), M0 (64-bit secret value used on the second
part of the protocol and initialization value), and R0 (16-bit value)—which should be equal to the
receiver R0'. If they are not equal, authentication fails. Future Ri' values produced during the third
part of the protocol reveal that authentication has failed in the event of erroneous R0=R0'.

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■ HDCP TX enables encryption when the first part of the protocol succeeds.

A.1.2 Second Part of Protocol

The second part of the authentication protocol (illustrated in Figure A-2) is required if the HDCP Receiver is
an HDCP Repeater.

Figure A-2 Second Part of Protocol

This part of the protocol:

■ Reads the V’s and the list of KSV of all downstream devices attached to the Repeater once the KSV list
ready flag is set (after the Repeater calculates V'). Fails if the flag is not set in 5s. May be reattempted
through new transmission of An and Aksv.
■ HDCP TX checks if any received KSV is on the revocation black list and calculates its own V, based
on the KSV list, M0 and Bstatus (I2C read from the Repeater HDCP port)
■ Authentication fails if V0 not equal to the received V0' or if any KSV is on the black list or if the tree
topology exceeds the limits (HDCP specification).

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A.1.3 Third Part of Protocol

The third part of the authentication protocol occurs during the vertical blanking interval preceding the
frame for which it applies, as shown in Figure A-3.

Figure A-3 Third Part of Protocol

The third part of the protocol operates as follows:

■ Each cipher calculates new initialization values (Ki and Mi) and Ri for link integrity check that can be
read every 2s or every 128th frame. If Ri not equal to Ri' link integrity check and authentication fails.
■ In order to enhance the detection of the loss of encryption synchronization, enhanced link verification
can be done if supported by the receiver. Every 16 frames, a Pj value is calculated on both devices
based on the first pixel of channel 0 and the least significant byte of Rj. Unless a minimum of 3
successive mismatches are found, it is considered to be a pixel transmission error and not
authentication or synchronization error.

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A.2 HDCP State Machines and Debug Observation Registers

A.2.1 HDCP Authentication FSM
The following state diagrams (Figure A-4 and Figure A-5) and Table A-1 on page 328 show the main state
machine transitions that control the authentication protocol. Its state and sub-state can be observed on
HDCP register HDCPOBS0, stateA (bits 7:4) and sub-stateA (bits 3:1).

Figure A-4 HDCP Controller Authentication FSM

HD CP T R AN SM IT T ER
AUT H EN T ICAT ION PROTOC OL

A0:
Wait for a Wait fo r Active RX
acknow ledge I2C
read
N ot valid KSVs

A1:
Exch an ge KSVs
Send An, AKVS
R eceive BKSV
Start 100m s tim er

Not valid KSVs

Not R 0' ready
Not R 0==R0 '
A2: SR M int egr it y f ail
Calculate Km, Ks, C om pu tation s
M 0, R 0
St art KSV r evocation
C heck BKSV 20/ 20

A3:
Vali date receiver
HD CP RX not ready After 100ms
Read R0'
C hec k R 0==R0'
Check KSV r evocation
Not V==V'
KSV revocation
SR M integr ity fail
A6: N ot Ri ==R i'
Test if is repeater Test f or rep eater

A 8: A 4:
Wait f or 5 seconds W ait fo r R ead y Update UC CF A u then ti cat ed
Poll HD CP R X ready a) HD CP act ive
b)SRM validated
c)no dev ice revocation

A 9: A 5:
Read K SV list L in k In tegr ity Ch eck
R ead KSV list Check R i ==R i'
R ead V'
C om pute V
Check V==V'
C heck KSV r evocation

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Figure A-5 HDCP Controller Authentication FSM Commented

Waiting for a acknow ledge r ead from HD CP TR AN SMIT T ER

A successful read fr om the I2C slave
the I2C master, use a 100ms timer to AUT HENT ICAT ION PROTOCOL
determines that a active RX as been
try a I2C read, display low content
detected.
visual data during this per iod. A0:
Wait for a Wait f or Active RX
a cknow ledge I2C
read
N ot valid KSVs
Cipher gener ates the An. Wr ites An
After the BKSV is r ead computations
and AKSV to slave and start a
need to be done to determine the
a100ms timer.
authenticity of the receiver
R ead the receiver response BKSV A1:
Send An, AKVS Exchan g e KSVs
Receive BKSV
Start 100ms timer

No t valid KSVs
Revocation block starts checking
No t R0 ' ready
The block stays in computations until
BKSV integrity. Calculates Km, starts
cipher calculation of Ks, M 0 and R0 No t R0 ==R0 ' the 100ms timer is expired
A2: SRM integrity fail
C alculate Km, Ks, C omp u tatio ns
M0, R 0
Start KSV revocation
Ch eck BKSV 20/20

Read R0 from the I2C and compare

If the revocation reporrts the KSV is
w ith the obtained. Wait for revocation ok. Enable H AD CP encryption.
result.
A3:
HDC P R X not ready After 100ms Valid ate receiver
R ead R0'
Check R0 ==R0'
Check KSV revocation
N ot V==V'
KSV revocation
Test if the device is a repeater
SRM integr ity fail
A6: N ot Ri ==Ri'
Test fo r rep eater
Test if is r epeater

Wait for 5 second timer to poll the The H DCP is active and
H DCP RX ready bit. Once the Ready authenticated.
bit is detected
A8: A4:
Wait for 5 seconds Wait fo r Read y U pdate UCC F Au then ticated
Poll HD CP RX ready a)H DCP active
b)SRM validated
c)no device revocation

Reads the KSV and delivers them to

the uP that will check if they are in Timer tr igger s a new I2C read and
the revocation and cross check the the value R0 is again checked
r esulting message digest. A9: A5:
R ead K SV list L in k Int eg rit y Ch eck
Read KSV list C heck R i==Ri'
R ead V'
Compute V
Check V==V'
C heck KSV r evocation Once the Ready bit is
detected

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Table A-1 Authentication State and Sub-state Transitions

State ID Sub State ID Action

A0 Substate0 If I2C not busy and not timer100mson, request for I2C read Bcaps, go to
Substate1.

Substate1 If I2C busy falling edge, if acknowledge at 1 go to Substate3 else Substate2.

Else if timer100ms expired, start over again, go to Substate0.

Substate2 Set variables, go to Substate0.

Substate3 If I2C not busy, request for I2C read Bstatus, go to Substate4.

Substate4 If I2C busy falling edge, if acknowledge at 1 go to Substate5 else Substate2.

Else if timer100ms expired, start over again, go to Substate0.

Substate5 If HDMI_CAPABLE, test for device in HDMI mode; go to A1, else start again, go to
Substate0.

A1 Substate0 Request generate An, go to SubstateA1.

Substate1 If I2C not busy, request for I2C write Ainfo, go to Substate2.

Substate2 If I2C not busy and cipher not busy, request for I2C write An and AKSV,go to
SubstateA3.

Substate3 If I2C not busy, start timer100ms, request for I2C read BSK, go to SubstateA4.

Substate4 If I2C not busy, start check BKSV, go to Substate5.

Substate5 If check bit sum BKSV ended ok, if false go to Substate6 else start BKSV
revocation, go to Substate7.

Substate6 Set variables, go to A0.

Substate7 Set variables, go to A2.

A2 Substate0 Request cipher to calculate Ks, M0 and R0, go to Substate1.

Substate1 Set variables, go to A3.

A3 Substate0 If timer100ms stop and I2C not busy, request I2C read R0, go to Substate1.

Substate1 If I2C not busy and cipher not busy, check I2C acknowledge, go to Substate5 else
go to Substate4.

Substate2 If not Revocbusy, check status true, start timer2s go to Substate3 else go to
Substate4.

Substate3 Set variables, go to A6.

Substate4 Set variables, go to A0.

Substate5 If R0 equal, go to Sub-state 2.

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Table A-1 Authentication State and Sub-state Transitions (Continued)

State ID Sub State ID Action

A6 Substate0 If device is Repeater, go to Substate1; start timer5s, else go to Substate2.

Substate1 Set variables, go to A8.

Substate2 Set variables, go to A4.

A8 Substate0 If not timer5s and I2C not busy, request I2C read Bcaps, go to Substate1.

Substate1 If not I2Cbusy, check READY true and DEVICE_COUNT!=0, go to A9 else go to

A0.

A9 Substate0 Request revocation, check KSV list, go to Substate1.

Substate1 If Revocation not busy, check status if revoked go to Substate2 else go to

Substate3.

Substate2 Set variables, go to A0.

Substate3 Set variables, go to A4.

A4 Substate0 If Integrity Link Check not fail and ELV not failed, AUTHENTIC is true, stay in A4
else go to A0.

The state transitions in the previous table should transition as described on the HDCP spec., page 17 to 20.

When the authentication is not successful, the output image is red (by default). Check DDC
Note (I2C) operations during authentication to see what failed. To assist in debugging, check the
authentication, revocation, and cipher FSMs (presented next) by reading registers
A_HDCPOBS0-2. Make sure that the registers go from state to state as described in the
HDCP specification.
In DWC_hdmi_tx with HDCP, it is very important that the SFR clock be set between 18MHz
and 27 MHz so that the HDCP timers and I2C speed are correct for DDC operations and
successful authentication.
A very useful tool to check the HDCP authentication protocol is Quantum Data, which can be
installed on the DDC lines.

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A.2.2 HDCP Cipher FSM

The following state diagram in Figure A-6 and Table A-2 on page 331 show the Cipher Control state
machine transitions that control the implemented cipher (three layers of the HDCP cipher as described in
the HDCP specification, including LFSR and other functions required to generate the encryption key bytes
that are then XORed with the data). Its state can be observed on HDCP register HDCPOBS2, stateEE, bits
5:3.
This block implements the necessary cipher calculations for the authentication protocol and actively
generates the correct cipher to encrypt the outgoing data. The cipher has four different functions and each
one is used in a different state authentication and transmission. The functions are:
■ hdcpRngCipher
■ hdcpBlockCipher (during authentication protocol and vertical blanking)
■ hdcpStreamCipher
■ hdcpRekeyCipher
The cipher is needed in two different stages of the protocol: in the unauthenticated and authenticated states.
During the unauthenticated state, it is necessary to initiate authentication. For this to happen, it is necessary
to generate a pseudo-random number. For this, the cipher is used in hdcpRngCipher mode. There is also the
possibility to start a new authentication when the system is in an authenticated state, this means that this
operation mode can work on both authenticated and unauthenticated states. Still in the unauthenticated
state, it is necessary to verify the receiver’s M0 and R0 values to be considered authentic. For this to happen,
the cipher is requested to generate the Ks value followed by the M0 and R0 values. This request can also be
done during vertical blanking to new M and R values. When the system is in an authenticated state, the
cipher is requested to operate in all four existing functions.
The following state machine is used to keep track of the authentication processes in order to arbitrate which
operation can be requested to the cipher and also what controls can access them.

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Figure A-6 Cipher Control FSM

During this period HDCP Cipher Control State Machine

random seeds ar e
injected in the LSFR
E0:
Free Run

When AUTH_FAIL
AUTH_REQ
is pulsed

Stor es An content,
this takes 4 clock On this state the
cycles, Cipherbusy at KMR_REQ can be
1 E1: Done E2: attended by Cipher.
Store An Ready

! AUTHENTIC AUTH_REQ
Authenticated
Done

Wh ile AUTHENTIC, in Authentication

E4: E3:
her e Ciphe rrequest request
Act ive Derive Next Stores An content,
can be attended.
this takes 4 clock
cycles, Cipher busy at
1

AUTH_REQ

Table A-2 Cipher Control FSM

State Active controls

E0: Free Run AUTH_REQ.

E1: Store An None.

E2: Ready KMR_REQ, AUTH_REQ.

E3: Derive Next None.

E4: Active AUTHE_REQ, (Ciphermode=1 or Ciphermode=2) and Cipherrequest.

The state transitions in the previous table should transition as described on the HDCP specification, page 52
to 53.
While the hdcpRngCipher can be started in almost every state, the other three functions can only be called
when the state is E4(Active).It is important to notice that in order for the cipher state to transit from E2 to E4
it is necessary for the initial keys be calculated. Only after this happens can the protocol verify if the
receiving device is processing the same encryption content.

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A.2.3 HDCP Revocation FSM

The following state diagram in Figure A-7 shows the Revocation state machine transitions that control the
functions:
■ Revocation memory operations
■ KSV checks
■ KSV list check against revocation list
■ Km calculation
■ Comparison with Km read from downstream device
Its state can be observed on HDCP register HDCPOBS2, STATER, bits 2:0.

Figure A-7 Revocation FSM

HDCP Revocation State Machine

RESET R0:
RESET Once power-down or
reset are de-asserted
AKSV is read from
the DPK ROM
position 0
R1:
STARTUP Initial computations
ar e complete

R2: Check the KSV list

Done IDLE Done
with the revocation
table.
Check BKSV Check KSVlist
Revocation

Check BKSV integr ity

r equest uP for KSV R4: Check BKSV R5:
revocation check Check BKSV revocation Check KSV list

R3: Done
Check BKSV
Calculate bitwise sum
of the BKSV and
check is has 20 ones Calculate KM and
compare with internal
calculation.

1. The state machine starts from the reset state R0.

2. Leaving reset, the machine goes to state R1, where it stores the AKSV value on internal registers. This
is done by issuing a start-up request to the checkksv block.
3. The block performs the read operation and issues a done flag that enables the state machine to jump
to the next state and de-assert the busy flag.
4. After this, the machine goes to Idle state. State R2 is maintained until a request to check the content of
BKSV is issued. In state R3, the block simultaneously checks two aspects:
❑ If the BKSV bit-wise sum is equal to 20
❑ If the sum of the Device Private Keys selection with the BKSV is equal to the one with the AKSV

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5. After the operation is concluded, revocation ceases to be busy and state machine returns to IDLE sate
R2.
6. If all test are successful, the next step checks if the device has repeater capability.
a. If this is not true, the block’s work is over, returning to R2, and the BKSV has checked
successfully.
b. If true, the block waits on this state until the 5s expires or the READY flag has been successfully
pulled.
7. On state R5, the KSV list inside the Repeater’s FIFO is requested for a read and is checked with the
revocation list. The KSV list is requested to the Repeater and its content is saved inside the External
Revocation Memory between memory address space 13'h000A - 13'h0284.
8. After reading the KSV list, the SHA1 message digest is also requested to the Repeater and stored
between 13'h0285 - 13'h0298.
9. After reading all information from the Repeater device, the core writes the Bstatus and M0 data to the
memory in locations 13'h0000-13'h000A.
At this moment, all information required to calculate the SHA1 message digest of the Repeater’s KSV
FIFO list is available inside the External Revocation Memory.
10. An interruption is given to the API KSVsha1calcint (bit 1 of A_APIINTSTAT interruption register),
requesting the calculation and validation of such message.
There are no specification requirements for the time spent to respond to the SHA1 calculation even
though the core is waiting for this response and does not enable encryption to the Repeater device
during this period. Details on how the SHA1 message digest is calculated can be found in the HDCP
1.4 specification.

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A.2.4 OESS (Ordinary Encryption Status Signaling) FSM

The following state diagram in Figure A-8 shows the OESS state machine transitions. Its state can be
observed on HDCP register HDCPOBS1, STATEOEG, bits 5:3.
The state transitions in the diagram should transition as described in the HDCP specification,
pages 38 and 39.

Figure A-8 OESS FSM

Encr yption State Diagram

Reset condition, or tr ansitions to the OESS ENC_EN signal when in a
unauthenticated state cause authenticated sate, causes
encryption to be on Idle state. frame key calculation
D0:
Idle

New fr ame key is calculated for Entering video period

the next video frame causes this transition.
D1:
Frame Key Calc New video data
before ENC_EN
indicates that
encr yption is
Assertion of disabled
ENC_EN
star ts new fame In this state every ENC_EN
key calculation active,
pixel data is generate new
encrypted.
D2: frame key Assertion of
Encrypt ENC_EN
starts new fame
Video data key calculation

Not Video data

Star t Re Key
oper ation
D3: Assertion of
Video data signals Unknown blank VSYNC
next line to be
encrypted

Re Key operation
Assertion of continues if not
Re Key oper ation HSYNC
completed
continues if not
completed D4: D5:
Horizontal blank Vertical blank

Assertion of
VSYNC

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A.2.5 EESS (Enhanced Encryption Status Signaling) FSM

The state diagram in Figure A-9 shows the EESS state machine transitions. Its state can be observed on
HDCP register HDCPOBS2, STATEEEG, bits 2:0.
The state transitions in Figure A-9 should transition as described in the HDCP specification, pages 41 and
42.

Figure A-9 ESS FSM

Reset condition, or transitions to the

unauthenticated state cause Encryption State Diagram
encryption to be on Idle state. EESS
Assertion of
ENC_EN
G0:
Id le

New frame key is

calculated.
While AVMUTE
AVMUTE

ENC_DIS and ENC_DIS and

Packet data
not AC or not AC or
being sent Video data
AVMUT E G1: AVMUTE
Frame Key Calc being sent

Encrypt
data island
Encrypt
video period
Packet dat a
being sent

G2': G2: Not AVMUT E

Encrypt data En crypt video and ENC_EN

Packet data Video data

being sent being sent

G3': G3: End of video

Unknown bl ank Unkno wn blank period
ENC_EN and
not AVMUTE

Video data Start cipher

being sent re-key

Not AVMUTE
and ENC_EN
G1':
Frame Key Calc AC and
No HDCP
ENC_DIS and
activity here not AVMUTE
Not AVMUTE New frame key is
and ENC_DIS calculated. State only
and AC ENC_DIS and reached with AC
not AVMUTE

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Index

A Deliverables, of PCTL 28
Advance Cipher 74 Device Private Keys 80
AHB Master 54 Display
AMBA format configuration 24
APB slave interface 88 Display Channel (DDC) 24
An value 73 DMA
API low-level driver 28 Engine 56
Audio FSM 59
input interfaces 44 Operation 57
Audio DMA 54 DPK
56-Bit HDCP 80
Audio Stream
8-Bit HDCP 83
HBR 25
DPK (Device Private Keys 80
Audio stream
IEC 61937 compressed 25 DSD 23
L-PCM 25 DST 23
DVI 73
B
DWC_hdmi_tx
Burst 2 Format 47
block diagram 32
Bypass Encryption 74
E
C
ECC generators 69
CEC 88
EDID/HDCP I2C E-DDC 85
clock
E-EDID 25
frequencies 29
ispdifclk 49 Encryption Disable 74
clock channels 24 Enhanced Link Verification 74
Color Space Conversion 43 Ethernet traffic 25
matrix 43 F
Controller with HDCP 71 Features 1.1 74
CTS Calculation 53 Follower Mode 88
D Frame Composer 68
Data Island FSM
Packer 69 EESS 335
Scheduler 69 OESS 334
Data Island Packets Functional description, of PCTL 31
high priority 68 G
low priority 68 GPA 50

1.40a-ea00 Synopsys, Inc. SolvNet 337

July 2012 DesignWare.com
Index HDMI Transmitter Controller Databook, Early Adopter Edition

Data Mapping Examples 51 O

Timing 50 OESS 72
H Window of Opportunity Programming 72
Hardware configuration parameters, of HDMI TX 91 P
HDCP 24, 32 Packet Classification 69
Authentication FSM 326 Parameters
Authentication Protocol 323 Audio Interface 92
Revocation FSM 332 Bypass S/PDIF DRU 92
State Machine 326 Configuration 92
HDMI Enable 8-Bit Memory Interface 95
applications 23 Enable SNPS HEAC PHY 94
block diagram 24 Reset Synchronizers 95
features 27 Support
functional architecture 31 Color Space Converter 93
operational model 24 Consumer Electronics Control 93
product description 22 HDCP 93
standards 23 HDMI 1.4 93
System on Chip 22 Internal Pixel Repetition 94
HDMI TX PCTL
hardware configuration parameters 91 deliverables of 28
HEAC 25 description 31
I/O signals 97
I
software registers 129
I2C standards compliance 23
Fast Mode 74
Period
Master Interface 85, 86
Control 25
I2S Data Island 25
Format 45 Video Data 25
interface 45
Pixel
Left Justified Format 46
repetition 42
modes 45
Right Justified Format 46 R
Initiator Mode 88 R Value Verification 74
Interfaces 26 Random Number Generation Interface 73
L Receiver 74
L-PCM Registers
Eight-Channel Data Mapping 51 Audio DMA 257
Audio Sampler 244
M CEC Engine 305
manual configuration 32 Color Space Converter 275
Memory Debug Observation 326
allocation 76 Frame Composer 174
requirements 75 Generic Parallel Audio Interface 255
Revocation 75 HDCP BKSV 299
HDCP Encryption Engine 284
N I2C Master 313
NL-PCM I2C Master PHY 234
Data Mapping 52 Identification 148

SolvNet 1.40a-ea00
338 Synopsys, Inc.
DesignWare.com July 2012
HDMI Transmitter Controller Databook, Early Adopter Edition Index

Interrupt 152
Main Controller 269
Source PHY 226
Video Packetizer 168
Video Sampler 164
Repeater 74
revocmemclk 75
S
S/PDIF 49
SCART 24
Signals
3D TX PHY (phy_gen2) Interface 120
Audio Input Interface 103
CEC Interface 112
E-DDC Interface 111
HDCP Encryption Engine 113
HDMI TX PHY Interface 119
HEAC PHY Interface 121
Scan Test Interface 117
System and Slave Register Interface 109
Video Input Interface 101
Software registers
address map 130
bit map descriptions 147
of PCTL 129
Operational state configuration, control, and sta-
tus 148
Standards compliance, of PCTL 23
System Memory
data organization 55
T
TMDS data 24
Transfer Data Constitution 58
V
Video
data 25
data synchronization 33
Packetizer 42
pixel rates 24
pixel sampler 33
supported modes 36

1.40a-ea00 Synopsys, Inc. SolvNet 339

July 2012 DesignWare.com
Index HDMI Transmitter Controller Databook, Early Adopter Edition

SolvNet 1.40a-ea00
340 Synopsys, Inc.
DesignWare.com July 2012

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